clk-r8a73a4.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * r8a73a4 Core CPG Clocks
  4 *
  5 * Copyright (C) 2014  Ulrich Hecht
  6 */
  7
  8#include <linux/clk-provider.h>
  9#include <linux/clk/renesas.h>
 10#include <linux/init.h>
 11#include <linux/io.h>
 12#include <linux/kernel.h>
 13#include <linux/slab.h>
 14#include <linux/of.h>
 15#include <linux/of_address.h>
 16#include <linux/spinlock.h>
 17
 18struct r8a73a4_cpg {
 19	struct clk_onecell_data data;
 20	spinlock_t lock;
 21};
 22
 23#define CPG_CKSCR	0xc0
 24#define CPG_FRQCRA	0x00
 25#define CPG_FRQCRB	0x04
 26#define CPG_FRQCRC	0xe0
 27#define CPG_PLL0CR	0xd8
 28#define CPG_PLL1CR	0x28
 29#define CPG_PLL2CR	0x2c
 30#define CPG_PLL2HCR	0xe4
 31#define CPG_PLL2SCR	0xf4
 32
 33struct div4_clk {
 34	const char *name;
 35	unsigned int reg;
 36	unsigned int shift;
 37};
 38
 39static struct div4_clk div4_clks[] = {
 40	{ "i",	CPG_FRQCRA, 20 },
 41	{ "m3", CPG_FRQCRA, 12 },
 42	{ "b",	CPG_FRQCRA,  8 },
 43	{ "m1", CPG_FRQCRA,  4 },
 44	{ "m2", CPG_FRQCRA,  0 },
 45	{ "zx", CPG_FRQCRB, 12 },
 46	{ "zs", CPG_FRQCRB,  8 },
 47	{ "hp", CPG_FRQCRB,  4 },
 48	{ NULL, 0, 0 },
 49};
 50
 51static const struct clk_div_table div4_div_table[] = {
 52	{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
 53	{ 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
 54	{ 12, 10 }, { 0, 0 }
 55};
 56
 57static struct clk * __init
 58r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
 59			   void __iomem *base, const char *name)
 60{
 61	const struct clk_div_table *table = NULL;
 62	const char *parent_name;
 63	unsigned int shift, reg;
 64	unsigned int mult = 1;
 65	unsigned int div = 1;
 66
 67	if (!strcmp(name, "main")) {
 68		u32 ckscr = readl(base + CPG_CKSCR);
 69
 70		switch ((ckscr >> 28) & 3) {
 71		case 0:	/* extal1 */
 72			parent_name = of_clk_get_parent_name(np, 0);
 73			break;
 74		case 1:	/* extal1 / 2 */
 75			parent_name = of_clk_get_parent_name(np, 0);
 76			div = 2;
 77			break;
 78		case 2: /* extal2 */
 79			parent_name = of_clk_get_parent_name(np, 1);
 80			break;
 81		case 3: /* extal2 / 2 */
 82			parent_name = of_clk_get_parent_name(np, 1);
 83			div = 2;
 84			break;
 85		}
 86	} else if (!strcmp(name, "pll0")) {
 87		/* PLL0/1 are configurable multiplier clocks. Register them as
 88		 * fixed factor clocks for now as there's no generic multiplier
 89		 * clock implementation and we currently have no need to change
 90		 * the multiplier value.
 91		 */
 92		u32 value = readl(base + CPG_PLL0CR);
 93
 94		parent_name = "main";
 95		mult = ((value >> 24) & 0x7f) + 1;
 96		if (value & BIT(20))
 97			div = 2;
 98	} else if (!strcmp(name, "pll1")) {
 99		u32 value = readl(base + CPG_PLL1CR);
100
101		parent_name = "main";
102		/* XXX: enable bit? */
103		mult = ((value >> 24) & 0x7f) + 1;
104		if (value & BIT(7))
105			div = 2;
106	} else if (!strncmp(name, "pll2", 4)) {
107		u32 value, cr;
108
109		switch (name[4]) {
110		case 0:
111			cr = CPG_PLL2CR;
112			break;
113		case 's':
114			cr = CPG_PLL2SCR;
115			break;
116		case 'h':
117			cr = CPG_PLL2HCR;
118			break;
119		default:
120			return ERR_PTR(-EINVAL);
121		}
122		value = readl(base + cr);
123		switch ((value >> 5) & 7) {
124		case 0:
125			parent_name = "main";
126			div = 2;
127			break;
128		case 1:
129			parent_name = "extal2";
130			div = 2;
131			break;
132		case 3:
133			parent_name = "extal2";
134			div = 4;
135			break;
136		case 4:
137			parent_name = "main";
138			break;
139		case 5:
140			parent_name = "extal2";
141			break;
142		default:
143			pr_warn("%s: unexpected parent of %s\n", __func__,
144				name);
145			return ERR_PTR(-EINVAL);
146		}
147		/* XXX: enable bit? */
148		mult = ((value >> 24) & 0x7f) + 1;
149	} else if (!strcmp(name, "z") || !strcmp(name, "z2")) {
150		u32 shift = 8;
151
152		parent_name = "pll0";
153		if (name[1] == '2') {
154			div = 2;
155			shift = 0;
156		}
157		div *= 32;
158		mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f);
159	} else {
160		struct div4_clk *c;
161
162		for (c = div4_clks; c->name; c++) {
163			if (!strcmp(name, c->name))
164				break;
165		}
166		if (!c->name)
167			return ERR_PTR(-EINVAL);
168
169		parent_name = "pll1";
170		table = div4_div_table;
171		reg = c->reg;
172		shift = c->shift;
173	}
174
175	if (!table) {
176		return clk_register_fixed_factor(NULL, name, parent_name, 0,
177						 mult, div);
178	} else {
179		return clk_register_divider_table(NULL, name, parent_name, 0,
180						  base + reg, shift, 4, 0,
181						  table, &cpg->lock);
182	}
183}
184
185static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
186{
187	struct r8a73a4_cpg *cpg;
188	void __iomem *base;
189	struct clk **clks;
190	unsigned int i;
191	int num_clks;
192
193	num_clks = of_property_count_strings(np, "clock-output-names");
194	if (num_clks < 0) {
195		pr_err("%s: failed to count clocks\n", __func__);
196		return;
197	}
198
199	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
200	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
201	if (cpg == NULL || clks == NULL) {
202		/* We're leaking memory on purpose, there's no point in cleaning
203		 * up as the system won't boot anyway.
204		 */
205		return;
206	}
207
208	spin_lock_init(&cpg->lock);
209
210	cpg->data.clks = clks;
211	cpg->data.clk_num = num_clks;
212
213	base = of_iomap(np, 0);
214	if (WARN_ON(base == NULL))
215		return;
216
217	for (i = 0; i < num_clks; ++i) {
218		const char *name;
219		struct clk *clk;
220
221		of_property_read_string_index(np, "clock-output-names", i,
222					      &name);
223
224		clk = r8a73a4_cpg_register_clock(np, cpg, base, name);
225		if (IS_ERR(clk))
226			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
227			       __func__, np, name, PTR_ERR(clk));
228		else
229			cpg->data.clks[i] = clk;
230	}
231
232	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
233}
234CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks",
235	       r8a73a4_cpg_clocks_init);