nsscc-ipq9574.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved.
   5 */
   6
   7#include <linux/clk.h>
   8#include <linux/clk-provider.h>
   9#include <linux/err.h>
  10#include <linux/interconnect-provider.h>
  11#include <linux/kernel.h>
  12#include <linux/module.h>
  13#include <linux/of.h>
  14#include <linux/of_device.h>
  15#include <linux/platform_device.h>
  16#include <linux/pm_clock.h>
  17#include <linux/pm_runtime.h>
  18#include <linux/regmap.h>
  19
  20#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
  21#include <dt-bindings/interconnect/qcom,ipq9574.h>
  22#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
  23
  24#include "clk-alpha-pll.h"
  25#include "clk-branch.h"
  26#include "clk-pll.h"
  27#include "clk-rcg.h"
  28#include "clk-regmap.h"
  29#include "clk-regmap-divider.h"
  30#include "clk-regmap-mux.h"
  31#include "common.h"
  32#include "reset.h"
  33
  34/* Need to match the order of clocks in DT binding */
  35enum {
  36	DT_XO,
  37	DT_BIAS_PLL_CC_CLK,
  38	DT_BIAS_PLL_UBI_NC_CLK,
  39	DT_GCC_GPLL0_OUT_AUX,
  40	DT_UNIPHY0_NSS_RX_CLK,
  41	DT_UNIPHY0_NSS_TX_CLK,
  42	DT_UNIPHY1_NSS_RX_CLK,
  43	DT_UNIPHY1_NSS_TX_CLK,
  44	DT_UNIPHY2_NSS_RX_CLK,
  45	DT_UNIPHY2_NSS_TX_CLK,
  46};
  47
  48enum {
  49	P_XO,
  50	P_BIAS_PLL_CC_CLK,
  51	P_BIAS_PLL_UBI_NC_CLK,
  52	P_GCC_GPLL0_OUT_AUX,
  53	P_UBI32_PLL_OUT_MAIN,
  54	P_UNIPHY0_NSS_RX_CLK,
  55	P_UNIPHY0_NSS_TX_CLK,
  56	P_UNIPHY1_NSS_RX_CLK,
  57	P_UNIPHY1_NSS_TX_CLK,
  58	P_UNIPHY2_NSS_RX_CLK,
  59	P_UNIPHY2_NSS_TX_CLK,
  60};
  61
  62static const struct alpha_pll_config ubi32_pll_config = {
  63	.l = 0x3e,
  64	.alpha = 0x6666,
  65	.config_ctl_val = 0x200d4aa8,
  66	.config_ctl_hi_val = 0x3c,
  67	.main_output_mask = BIT(0),
  68	.aux_output_mask = BIT(1),
  69	.pre_div_val = 0x0,
  70	.pre_div_mask = BIT(12),
  71	.post_div_val = 0x0,
  72	.post_div_mask = GENMASK(9, 8),
  73	.alpha_en_mask = BIT(24),
  74	.test_ctl_val = 0x1c0000c0,
  75	.test_ctl_hi_val = 0x4000,
  76};
  77
  78static struct clk_alpha_pll ubi32_pll_main = {
  79	.offset = 0x28000,
  80	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
  81	.flags = SUPPORTS_DYNAMIC_UPDATE,
  82	.clkr = {
  83		.hw.init = &(const struct clk_init_data) {
  84			.name = "ubi32_pll_main",
  85			.parent_data = &(const struct clk_parent_data) {
  86				.index = DT_XO,
  87			},
  88			.num_parents = 1,
  89			.ops = &clk_alpha_pll_huayra_ops,
  90		},
  91	},
  92};
  93
  94static struct clk_alpha_pll_postdiv ubi32_pll = {
  95	.offset = 0x28000,
  96	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
  97	.width = 2,
  98	.clkr.hw.init = &(const struct clk_init_data) {
  99		.name = "ubi32_pll",
 100		.parent_hws = (const struct clk_hw *[]) {
 101			&ubi32_pll_main.clkr.hw
 102		},
 103		.num_parents = 1,
 104		.ops = &clk_alpha_pll_postdiv_ro_ops,
 105		.flags = CLK_SET_RATE_PARENT,
 106	},
 107};
 108
 109static const struct parent_map nss_cc_parent_map_0[] = {
 110	{ P_XO, 0 },
 111	{ P_BIAS_PLL_CC_CLK, 1 },
 112	{ P_UNIPHY0_NSS_RX_CLK, 2 },
 113	{ P_UNIPHY0_NSS_TX_CLK, 3 },
 114	{ P_UNIPHY1_NSS_RX_CLK, 4 },
 115	{ P_UNIPHY1_NSS_TX_CLK, 5 },
 116};
 117
 118static const struct clk_parent_data nss_cc_parent_data_0[] = {
 119	{ .index = DT_XO },
 120	{ .index = DT_BIAS_PLL_CC_CLK },
 121	{ .index = DT_UNIPHY0_NSS_RX_CLK },
 122	{ .index = DT_UNIPHY0_NSS_TX_CLK },
 123	{ .index = DT_UNIPHY1_NSS_RX_CLK },
 124	{ .index = DT_UNIPHY1_NSS_TX_CLK },
 125};
 126
 127static const struct parent_map nss_cc_parent_map_1[] = {
 128	{ P_XO, 0 },
 129	{ P_BIAS_PLL_UBI_NC_CLK, 1 },
 130	{ P_GCC_GPLL0_OUT_AUX, 2 },
 131	{ P_BIAS_PLL_CC_CLK, 6 },
 132};
 133
 134static const struct clk_parent_data nss_cc_parent_data_1[] = {
 135	{ .index = DT_XO },
 136	{ .index = DT_BIAS_PLL_UBI_NC_CLK },
 137	{ .index = DT_GCC_GPLL0_OUT_AUX },
 138	{ .index = DT_BIAS_PLL_CC_CLK },
 139};
 140
 141static const struct parent_map nss_cc_parent_map_2[] = {
 142	{ P_XO, 0 },
 143	{ P_UBI32_PLL_OUT_MAIN, 1 },
 144	{ P_GCC_GPLL0_OUT_AUX, 2 },
 145};
 146
 147static const struct clk_parent_data nss_cc_parent_data_2[] = {
 148	{ .index = DT_XO },
 149	{ .hw = &ubi32_pll.clkr.hw },
 150	{ .index = DT_GCC_GPLL0_OUT_AUX },
 151};
 152
 153static const struct parent_map nss_cc_parent_map_3[] = {
 154	{ P_XO, 0 },
 155	{ P_BIAS_PLL_CC_CLK, 1 },
 156	{ P_GCC_GPLL0_OUT_AUX, 2 },
 157};
 158
 159static const struct clk_parent_data nss_cc_parent_data_3[] = {
 160	{ .index = DT_XO },
 161	{ .index = DT_BIAS_PLL_CC_CLK },
 162	{ .index = DT_GCC_GPLL0_OUT_AUX },
 163};
 164
 165static const struct parent_map nss_cc_parent_map_4[] = {
 166	{ P_XO, 0 },
 167	{ P_BIAS_PLL_CC_CLK, 1 },
 168	{ P_UNIPHY0_NSS_RX_CLK, 2 },
 169	{ P_UNIPHY0_NSS_TX_CLK, 3 },
 170};
 171
 172static const struct clk_parent_data nss_cc_parent_data_4[] = {
 173	{ .index = DT_XO },
 174	{ .index = DT_BIAS_PLL_CC_CLK },
 175	{ .index = DT_UNIPHY0_NSS_RX_CLK },
 176	{ .index = DT_UNIPHY0_NSS_TX_CLK },
 177};
 178
 179static const struct parent_map nss_cc_parent_map_5[] = {
 180	{ P_XO, 0 },
 181	{ P_BIAS_PLL_CC_CLK, 1 },
 182	{ P_UNIPHY2_NSS_RX_CLK, 2 },
 183	{ P_UNIPHY2_NSS_TX_CLK, 3 },
 184};
 185
 186static const struct clk_parent_data nss_cc_parent_data_5[] = {
 187	{ .index = DT_XO },
 188	{ .index = DT_BIAS_PLL_CC_CLK },
 189	{ .index = DT_UNIPHY2_NSS_RX_CLK },
 190	{ .index = DT_UNIPHY2_NSS_TX_CLK },
 191};
 192
 193static const struct parent_map nss_cc_parent_map_6[] = {
 194	{ P_XO, 0 },
 195	{ P_GCC_GPLL0_OUT_AUX, 2 },
 196	{ P_BIAS_PLL_CC_CLK, 6 },
 197};
 198
 199static const struct clk_parent_data nss_cc_parent_data_6[] = {
 200	{ .index = DT_XO },
 201	{ .index = DT_GCC_GPLL0_OUT_AUX },
 202	{ .index = DT_BIAS_PLL_CC_CLK },
 203};
 204
 205static const struct parent_map nss_cc_parent_map_7[] = {
 206	{ P_XO, 0 },
 207	{ P_UBI32_PLL_OUT_MAIN, 1 },
 208	{ P_GCC_GPLL0_OUT_AUX, 2 },
 209	{ P_BIAS_PLL_CC_CLK, 6 },
 210};
 211
 212static const struct clk_parent_data nss_cc_parent_data_7[] = {
 213	{ .index = DT_XO },
 214	{ .hw = &ubi32_pll.clkr.hw },
 215	{ .index = DT_GCC_GPLL0_OUT_AUX },
 216	{ .index = DT_BIAS_PLL_CC_CLK },
 217};
 218
 219static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] = {
 220	F(24000000, P_XO, 1, 0, 0),
 221	F(353000000, P_BIAS_PLL_UBI_NC_CLK, 1, 0, 0),
 222	{ }
 223};
 224
 225static struct clk_rcg2 nss_cc_ce_clk_src = {
 226	.cmd_rcgr = 0x28404,
 227	.mnd_width = 0,
 228	.hid_width = 5,
 229	.parent_map = nss_cc_parent_map_1,
 230	.freq_tbl = ftbl_nss_cc_ce_clk_src,
 231	.clkr.hw.init = &(const struct clk_init_data) {
 232		.name = "nss_cc_ce_clk_src",
 233		.parent_data = nss_cc_parent_data_1,
 234		.num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
 235		.ops = &clk_rcg2_ops,
 236	},
 237};
 238
 239static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] = {
 240	F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0),
 241	{ }
 242};
 243
 244static struct clk_rcg2 nss_cc_cfg_clk_src = {
 245	.cmd_rcgr = 0x28104,
 246	.mnd_width = 0,
 247	.hid_width = 5,
 248	.parent_map = nss_cc_parent_map_3,
 249	.freq_tbl = ftbl_nss_cc_cfg_clk_src,
 250	.clkr.hw.init = &(const struct clk_init_data) {
 251		.name = "nss_cc_cfg_clk_src",
 252		.parent_data = nss_cc_parent_data_3,
 253		.num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
 254		.ops = &clk_rcg2_ops,
 255	},
 256};
 257
 258static const struct freq_tbl ftbl_nss_cc_clc_clk_src[] = {
 259	F(533333333, P_GCC_GPLL0_OUT_AUX, 1.5, 0, 0),
 260	{ }
 261};
 262
 263static struct clk_rcg2 nss_cc_clc_clk_src = {
 264	.cmd_rcgr = 0x28604,
 265	.mnd_width = 0,
 266	.hid_width = 5,
 267	.parent_map = nss_cc_parent_map_6,
 268	.freq_tbl = ftbl_nss_cc_clc_clk_src,
 269	.clkr.hw.init = &(const struct clk_init_data) {
 270		.name = "nss_cc_clc_clk_src",
 271		.parent_data = nss_cc_parent_data_6,
 272		.num_parents = ARRAY_SIZE(nss_cc_parent_data_6),
 273		.ops = &clk_rcg2_ops,
 274	},
 275};
 276
 277static const struct freq_tbl ftbl_nss_cc_crypto_clk_src[] = {
 278	F(24000000, P_XO, 1, 0, 0),
 279	F(300000000, P_BIAS_PLL_CC_CLK, 4, 0, 0),
 280	F(600000000, P_BIAS_PLL_CC_CLK, 2, 0, 0),
 281	{ }
 282};
 283
 284static struct clk_rcg2 nss_cc_crypto_clk_src = {
 285	.cmd_rcgr = 0x16008,
 286	.mnd_width = 16,
 287	.hid_width = 5,
 288	.parent_map = nss_cc_parent_map_3,
 289	.freq_tbl = ftbl_nss_cc_crypto_clk_src,
 290	.clkr.hw.init = &(const struct clk_init_data) {
 291		.name = "nss_cc_crypto_clk_src",
 292		.parent_data = nss_cc_parent_data_3,
 293		.num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
 294		.flags = CLK_SET_RATE_PARENT,
 295		.ops = &clk_rcg2_ops,
 296	},
 297};
 298
 299static struct clk_rcg2 nss_cc_haq_clk_src = {
 300	.cmd_rcgr = 0x28304,
 301	.mnd_width = 0,
 302	.hid_width = 5,
 303	.parent_map = nss_cc_parent_map_1,
 304	.freq_tbl = ftbl_nss_cc_ce_clk_src,
 305	.clkr.hw.init = &(const struct clk_init_data) {
 306		.name = "nss_cc_haq_clk_src",
 307		.parent_data = nss_cc_parent_data_1,
 308		.num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
 309		.ops = &clk_rcg2_ops,
 310	},
 311};
 312
 313static struct clk_rcg2 nss_cc_imem_clk_src = {
 314	.cmd_rcgr = 0xe008,
 315	.mnd_width = 0,
 316	.hid_width = 5,
 317	.parent_map = nss_cc_parent_map_1,
 318	.freq_tbl = ftbl_nss_cc_ce_clk_src,
 319	.clkr.hw.init = &(const struct clk_init_data) {
 320		.name = "nss_cc_imem_clk_src",
 321		.parent_data = nss_cc_parent_data_1,
 322		.num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
 323		.ops = &clk_rcg2_ops,
 324	},
 325};
 326
 327static const struct freq_tbl ftbl_nss_cc_int_cfg_clk_src[] = {
 328	F(200000000, P_GCC_GPLL0_OUT_AUX, 4, 0, 0),
 329	{ }
 330};
 331
 332static struct clk_rcg2 nss_cc_int_cfg_clk_src = {
 333	.cmd_rcgr = 0x287b4,
 334	.mnd_width = 0,
 335	.hid_width = 5,
 336	.parent_map = nss_cc_parent_map_3,
 337	.freq_tbl = ftbl_nss_cc_int_cfg_clk_src,
 338	.clkr.hw.init = &(const struct clk_init_data) {
 339		.name = "nss_cc_int_cfg_clk_src",
 340		.parent_data = nss_cc_parent_data_3,
 341		.num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
 342		.ops = &clk_rcg2_ops,
 343	},
 344};
 345
 346static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
 347	C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0),
 348	C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
 349};
 350
 351static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = {
 352	C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0),
 353	C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
 354};
 355
 356static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
 357	FMS(24000000, P_XO, 1, 0, 0),
 358	FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25),
 359	FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0),
 360	FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125),
 361	FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
 362	{ }
 363};
 364
 365static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = {
 366	C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0),
 367	C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
 368};
 369
 370static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = {
 371	C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0),
 372	C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
 373};
 374
 375static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = {
 376	FMS(24000000, P_XO, 1, 0, 0),
 377	FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25),
 378	FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0),
 379	FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125),
 380	FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
 381	{ }
 382};
 383
 384static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_25[] = {
 385	C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0),
 386	C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
 387};
 388
 389static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_125[] = {
 390	C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0),
 391	C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
 392};
 393
 394static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_312p5[] = {
 395	C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
 396	C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
 397};
 398
 399static const struct freq_multi_tbl ftbl_nss_cc_port5_rx_clk_src[] = {
 400	FMS(24000000, P_XO, 1, 0, 0),
 401	FM(25000000, ftbl_nss_cc_port5_rx_clk_src_25),
 402	FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0),
 403	FM(125000000, ftbl_nss_cc_port5_rx_clk_src_125),
 404	FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0),
 405	FM(312500000, ftbl_nss_cc_port5_rx_clk_src_312p5),
 406	{ }
 407};
 408
 409static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_25[] = {
 410	C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0),
 411	C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
 412};
 413
 414static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_125[] = {
 415	C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0),
 416	C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
 417};
 418
 419static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_312p5[] = {
 420	C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
 421	C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
 422};
 423
 424static const struct freq_multi_tbl ftbl_nss_cc_port5_tx_clk_src[] = {
 425	FMS(24000000, P_XO, 1, 0, 0),
 426	FM(25000000, ftbl_nss_cc_port5_tx_clk_src_25),
 427	FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0),
 428	FM(125000000, ftbl_nss_cc_port5_tx_clk_src_125),
 429	FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0),
 430	FM(312500000, ftbl_nss_cc_port5_tx_clk_src_312p5),
 431	{ }
 432};
 433
 434static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_25[] = {
 435	C(P_UNIPHY2_NSS_RX_CLK, 12.5, 0, 0),
 436	C(P_UNIPHY2_NSS_RX_CLK, 5, 0, 0),
 437};
 438
 439static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_125[] = {
 440	C(P_UNIPHY2_NSS_RX_CLK, 2.5, 0, 0),
 441	C(P_UNIPHY2_NSS_RX_CLK, 1, 0, 0),
 442};
 443
 444static const struct freq_multi_tbl ftbl_nss_cc_port6_rx_clk_src[] = {
 445	FMS(24000000, P_XO, 1, 0, 0),
 446	FM(25000000, ftbl_nss_cc_port6_rx_clk_src_25),
 447	FMS(78125000, P_UNIPHY2_NSS_RX_CLK, 4, 0, 0),
 448	FM(125000000, ftbl_nss_cc_port6_rx_clk_src_125),
 449	FMS(156250000, P_UNIPHY2_NSS_RX_CLK, 2, 0, 0),
 450	FMS(312500000, P_UNIPHY2_NSS_RX_CLK, 1, 0, 0),
 451	{ }
 452};
 453
 454static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_25[] = {
 455	C(P_UNIPHY2_NSS_TX_CLK, 12.5, 0, 0),
 456	C(P_UNIPHY2_NSS_TX_CLK, 5, 0, 0),
 457};
 458
 459static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_125[] = {
 460	C(P_UNIPHY2_NSS_TX_CLK, 2.5, 0, 0),
 461	C(P_UNIPHY2_NSS_TX_CLK, 1, 0, 0),
 462};
 463
 464static const struct freq_multi_tbl ftbl_nss_cc_port6_tx_clk_src[] = {
 465	FMS(24000000, P_XO, 1, 0, 0),
 466	FM(25000000, ftbl_nss_cc_port6_tx_clk_src_25),
 467	FMS(78125000, P_UNIPHY2_NSS_TX_CLK, 4, 0, 0),
 468	FM(125000000, ftbl_nss_cc_port6_tx_clk_src_125),
 469	FMS(156250000, P_UNIPHY2_NSS_TX_CLK, 2, 0, 0),
 470	FMS(312500000, P_UNIPHY2_NSS_TX_CLK, 1, 0, 0),
 471	{ }
 472};
 473
 474static struct clk_rcg2 nss_cc_port1_rx_clk_src = {
 475	.cmd_rcgr = 0x28110,
 476	.mnd_width = 0,
 477	.hid_width = 5,
 478	.parent_map = nss_cc_parent_map_4,
 479	.freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
 480	.clkr.hw.init = &(const struct clk_init_data) {
 481		.name = "nss_cc_port1_rx_clk_src",
 482		.parent_data = nss_cc_parent_data_4,
 483		.num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
 484		.ops = &clk_rcg2_fm_ops,
 485	},
 486};
 487
 488static struct clk_rcg2 nss_cc_port1_tx_clk_src = {
 489	.cmd_rcgr = 0x2811c,
 490	.mnd_width = 0,
 491	.hid_width = 5,
 492	.parent_map = nss_cc_parent_map_4,
 493	.freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
 494	.clkr.hw.init = &(const struct clk_init_data) {
 495		.name = "nss_cc_port1_tx_clk_src",
 496		.parent_data = nss_cc_parent_data_4,
 497		.num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
 498		.ops = &clk_rcg2_fm_ops,
 499	},
 500};
 501
 502static struct clk_rcg2 nss_cc_port2_rx_clk_src = {
 503	.cmd_rcgr = 0x28128,
 504	.mnd_width = 0,
 505	.hid_width = 5,
 506	.parent_map = nss_cc_parent_map_4,
 507	.freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
 508	.clkr.hw.init = &(const struct clk_init_data) {
 509		.name = "nss_cc_port2_rx_clk_src",
 510		.parent_data = nss_cc_parent_data_4,
 511		.num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
 512		.ops = &clk_rcg2_fm_ops,
 513	},
 514};
 515
 516static struct clk_rcg2 nss_cc_port2_tx_clk_src = {
 517	.cmd_rcgr = 0x28134,
 518	.mnd_width = 0,
 519	.hid_width = 5,
 520	.parent_map = nss_cc_parent_map_4,
 521	.freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
 522	.clkr.hw.init = &(const struct clk_init_data) {
 523		.name = "nss_cc_port2_tx_clk_src",
 524		.parent_data = nss_cc_parent_data_4,
 525		.num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
 526		.ops = &clk_rcg2_fm_ops,
 527	},
 528};
 529
 530static struct clk_rcg2 nss_cc_port3_rx_clk_src = {
 531	.cmd_rcgr = 0x28140,
 532	.mnd_width = 0,
 533	.hid_width = 5,
 534	.parent_map = nss_cc_parent_map_4,
 535	.freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
 536	.clkr.hw.init = &(const struct clk_init_data) {
 537		.name = "nss_cc_port3_rx_clk_src",
 538		.parent_data = nss_cc_parent_data_4,
 539		.num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
 540		.ops = &clk_rcg2_fm_ops,
 541	},
 542};
 543
 544static struct clk_rcg2 nss_cc_port3_tx_clk_src = {
 545	.cmd_rcgr = 0x2814c,
 546	.mnd_width = 0,
 547	.hid_width = 5,
 548	.parent_map = nss_cc_parent_map_4,
 549	.freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
 550	.clkr.hw.init = &(const struct clk_init_data) {
 551		.name = "nss_cc_port3_tx_clk_src",
 552		.parent_data = nss_cc_parent_data_4,
 553		.num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
 554		.ops = &clk_rcg2_fm_ops,
 555	},
 556};
 557
 558static struct clk_rcg2 nss_cc_port4_rx_clk_src = {
 559	.cmd_rcgr = 0x28158,
 560	.mnd_width = 0,
 561	.hid_width = 5,
 562	.parent_map = nss_cc_parent_map_4,
 563	.freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
 564	.clkr.hw.init = &(const struct clk_init_data) {
 565		.name = "nss_cc_port4_rx_clk_src",
 566		.parent_data = nss_cc_parent_data_4,
 567		.num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
 568		.ops = &clk_rcg2_fm_ops,
 569	},
 570};
 571
 572static struct clk_rcg2 nss_cc_port4_tx_clk_src = {
 573	.cmd_rcgr = 0x28164,
 574	.mnd_width = 0,
 575	.hid_width = 5,
 576	.parent_map = nss_cc_parent_map_4,
 577	.freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
 578	.clkr.hw.init = &(const struct clk_init_data) {
 579		.name = "nss_cc_port4_tx_clk_src",
 580		.parent_data = nss_cc_parent_data_4,
 581		.num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
 582		.ops = &clk_rcg2_fm_ops,
 583	},
 584};
 585
 586static struct clk_rcg2 nss_cc_port5_rx_clk_src = {
 587	.cmd_rcgr = 0x28170,
 588	.mnd_width = 0,
 589	.hid_width = 5,
 590	.parent_map = nss_cc_parent_map_0,
 591	.freq_multi_tbl = ftbl_nss_cc_port5_rx_clk_src,
 592	.clkr.hw.init = &(const struct clk_init_data) {
 593		.name = "nss_cc_port5_rx_clk_src",
 594		.parent_data = nss_cc_parent_data_0,
 595		.num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
 596		.ops = &clk_rcg2_fm_ops,
 597	},
 598};
 599
 600static struct clk_rcg2 nss_cc_port5_tx_clk_src = {
 601	.cmd_rcgr = 0x2817c,
 602	.mnd_width = 0,
 603	.hid_width = 5,
 604	.parent_map = nss_cc_parent_map_0,
 605	.freq_multi_tbl = ftbl_nss_cc_port5_tx_clk_src,
 606	.clkr.hw.init = &(const struct clk_init_data) {
 607		.name = "nss_cc_port5_tx_clk_src",
 608		.parent_data = nss_cc_parent_data_0,
 609		.num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
 610		.ops = &clk_rcg2_fm_ops,
 611	},
 612};
 613
 614static struct clk_rcg2 nss_cc_port6_rx_clk_src = {
 615	.cmd_rcgr = 0x28188,
 616	.mnd_width = 0,
 617	.hid_width = 5,
 618	.parent_map = nss_cc_parent_map_5,
 619	.freq_multi_tbl = ftbl_nss_cc_port6_rx_clk_src,
 620	.clkr.hw.init = &(const struct clk_init_data) {
 621		.name = "nss_cc_port6_rx_clk_src",
 622		.parent_data = nss_cc_parent_data_5,
 623		.num_parents = ARRAY_SIZE(nss_cc_parent_data_5),
 624		.ops = &clk_rcg2_fm_ops,
 625	},
 626};
 627
 628static struct clk_rcg2 nss_cc_port6_tx_clk_src = {
 629	.cmd_rcgr = 0x28194,
 630	.mnd_width = 0,
 631	.hid_width = 5,
 632	.parent_map = nss_cc_parent_map_5,
 633	.freq_multi_tbl = ftbl_nss_cc_port6_tx_clk_src,
 634	.clkr.hw.init = &(const struct clk_init_data) {
 635		.name = "nss_cc_port6_tx_clk_src",
 636		.parent_data = nss_cc_parent_data_5,
 637		.num_parents = ARRAY_SIZE(nss_cc_parent_data_5),
 638		.ops = &clk_rcg2_fm_ops,
 639	},
 640};
 641
 642static struct clk_rcg2 nss_cc_ppe_clk_src = {
 643	.cmd_rcgr = 0x28204,
 644	.mnd_width = 0,
 645	.hid_width = 5,
 646	.parent_map = nss_cc_parent_map_1,
 647	.freq_tbl = ftbl_nss_cc_ce_clk_src,
 648	.clkr.hw.init = &(const struct clk_init_data) {
 649		.name = "nss_cc_ppe_clk_src",
 650		.parent_data = nss_cc_parent_data_1,
 651		.num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
 652		.flags = CLK_SET_RATE_PARENT,
 653		.ops = &clk_rcg2_ops,
 654	},
 655};
 656
 657static const struct freq_tbl ftbl_nss_cc_ubi0_clk_src[] = {
 658	F(24000000, P_XO, 1, 0, 0),
 659	F(187200000, P_UBI32_PLL_OUT_MAIN, 8, 0, 0),
 660	F(748800000, P_UBI32_PLL_OUT_MAIN, 2, 0, 0),
 661	F(1497600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0),
 662	F(1689600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0),
 663	{ }
 664};
 665
 666static struct clk_rcg2 nss_cc_ubi0_clk_src = {
 667	.cmd_rcgr = 0x28704,
 668	.mnd_width = 0,
 669	.hid_width = 5,
 670	.parent_map = nss_cc_parent_map_2,
 671	.freq_tbl = ftbl_nss_cc_ubi0_clk_src,
 672	.clkr.hw.init = &(const struct clk_init_data) {
 673		.name = "nss_cc_ubi0_clk_src",
 674		.parent_data = nss_cc_parent_data_2,
 675		.num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
 676		.flags = CLK_SET_RATE_PARENT,
 677		.ops = &clk_rcg2_ops,
 678	},
 679};
 680
 681static struct clk_rcg2 nss_cc_ubi1_clk_src = {
 682	.cmd_rcgr = 0x2870c,
 683	.mnd_width = 0,
 684	.hid_width = 5,
 685	.parent_map = nss_cc_parent_map_2,
 686	.freq_tbl = ftbl_nss_cc_ubi0_clk_src,
 687	.clkr.hw.init = &(const struct clk_init_data) {
 688		.name = "nss_cc_ubi1_clk_src",
 689		.parent_data = nss_cc_parent_data_2,
 690		.num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
 691		.flags = CLK_SET_RATE_PARENT,
 692		.ops = &clk_rcg2_ops,
 693	},
 694};
 695
 696static struct clk_rcg2 nss_cc_ubi2_clk_src = {
 697	.cmd_rcgr = 0x28714,
 698	.mnd_width = 0,
 699	.hid_width = 5,
 700	.parent_map = nss_cc_parent_map_2,
 701	.freq_tbl = ftbl_nss_cc_ubi0_clk_src,
 702	.clkr.hw.init = &(const struct clk_init_data) {
 703		.name = "nss_cc_ubi2_clk_src",
 704		.parent_data = nss_cc_parent_data_2,
 705		.num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
 706		.flags = CLK_SET_RATE_PARENT,
 707		.ops = &clk_rcg2_ops,
 708	},
 709};
 710
 711static struct clk_rcg2 nss_cc_ubi3_clk_src = {
 712	.cmd_rcgr = 0x2871c,
 713	.mnd_width = 0,
 714	.hid_width = 5,
 715	.parent_map = nss_cc_parent_map_2,
 716	.freq_tbl = ftbl_nss_cc_ubi0_clk_src,
 717	.clkr.hw.init = &(const struct clk_init_data) {
 718		.name = "nss_cc_ubi3_clk_src",
 719		.parent_data = nss_cc_parent_data_2,
 720		.num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
 721		.flags = CLK_SET_RATE_PARENT,
 722		.ops = &clk_rcg2_ops,
 723	},
 724};
 725
 726static struct clk_rcg2 nss_cc_ubi_axi_clk_src = {
 727	.cmd_rcgr = 0x28724,
 728	.mnd_width = 0,
 729	.hid_width = 5,
 730	.parent_map = nss_cc_parent_map_7,
 731	.freq_tbl = ftbl_nss_cc_clc_clk_src,
 732	.clkr.hw.init = &(const struct clk_init_data) {
 733		.name = "nss_cc_ubi_axi_clk_src",
 734		.parent_data = nss_cc_parent_data_7,
 735		.num_parents = ARRAY_SIZE(nss_cc_parent_data_7),
 736		.ops = &clk_rcg2_ops,
 737	},
 738};
 739
 740static struct clk_rcg2 nss_cc_ubi_nc_axi_bfdcd_clk_src = {
 741	.cmd_rcgr = 0x2872c,
 742	.mnd_width = 0,
 743	.hid_width = 5,
 744	.parent_map = nss_cc_parent_map_1,
 745	.freq_tbl = ftbl_nss_cc_ce_clk_src,
 746	.clkr.hw.init = &(const struct clk_init_data) {
 747		.name = "nss_cc_ubi_nc_axi_bfdcd_clk_src",
 748		.parent_data = nss_cc_parent_data_1,
 749		.num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
 750		.flags = CLK_SET_RATE_PARENT,
 751		.ops = &clk_rcg2_ops,
 752	},
 753};
 754
 755static struct clk_regmap_div nss_cc_port1_rx_div_clk_src = {
 756	.reg = 0x28118,
 757	.shift = 0,
 758	.width = 9,
 759	.clkr.hw.init = &(const struct clk_init_data) {
 760		.name = "nss_cc_port1_rx_div_clk_src",
 761		.parent_data = &(const struct clk_parent_data) {
 762			.hw = &nss_cc_port1_rx_clk_src.clkr.hw,
 763		},
 764		.num_parents = 1,
 765		.flags = CLK_SET_RATE_PARENT,
 766		.ops = &clk_regmap_div_ops,
 767	},
 768};
 769
 770static struct clk_regmap_div nss_cc_port1_tx_div_clk_src = {
 771	.reg = 0x28124,
 772	.shift = 0,
 773	.width = 9,
 774	.clkr.hw.init = &(const struct clk_init_data) {
 775		.name = "nss_cc_port1_tx_div_clk_src",
 776		.parent_data = &(const struct clk_parent_data) {
 777			.hw = &nss_cc_port1_tx_clk_src.clkr.hw,
 778		},
 779		.num_parents = 1,
 780		.flags = CLK_SET_RATE_PARENT,
 781		.ops = &clk_regmap_div_ops,
 782	},
 783};
 784
 785static struct clk_regmap_div nss_cc_port2_rx_div_clk_src = {
 786	.reg = 0x28130,
 787	.shift = 0,
 788	.width = 9,
 789	.clkr.hw.init = &(const struct clk_init_data) {
 790		.name = "nss_cc_port2_rx_div_clk_src",
 791		.parent_data = &(const struct clk_parent_data) {
 792			.hw = &nss_cc_port2_rx_clk_src.clkr.hw,
 793		},
 794		.num_parents = 1,
 795		.flags = CLK_SET_RATE_PARENT,
 796		.ops = &clk_regmap_div_ops,
 797	},
 798};
 799
 800static struct clk_regmap_div nss_cc_port2_tx_div_clk_src = {
 801	.reg = 0x2813c,
 802	.shift = 0,
 803	.width = 9,
 804	.clkr.hw.init = &(const struct clk_init_data) {
 805		.name = "nss_cc_port2_tx_div_clk_src",
 806		.parent_data = &(const struct clk_parent_data) {
 807			.hw = &nss_cc_port2_tx_clk_src.clkr.hw,
 808		},
 809		.num_parents = 1,
 810		.flags = CLK_SET_RATE_PARENT,
 811		.ops = &clk_regmap_div_ops,
 812	},
 813};
 814
 815static struct clk_regmap_div nss_cc_port3_rx_div_clk_src = {
 816	.reg = 0x28148,
 817	.shift = 0,
 818	.width = 9,
 819	.clkr.hw.init = &(const struct clk_init_data) {
 820		.name = "nss_cc_port3_rx_div_clk_src",
 821		.parent_data = &(const struct clk_parent_data) {
 822			.hw = &nss_cc_port3_rx_clk_src.clkr.hw,
 823		},
 824		.num_parents = 1,
 825		.flags = CLK_SET_RATE_PARENT,
 826		.ops = &clk_regmap_div_ops,
 827	},
 828};
 829
 830static struct clk_regmap_div nss_cc_port3_tx_div_clk_src = {
 831	.reg = 0x28154,
 832	.shift = 0,
 833	.width = 9,
 834	.clkr.hw.init = &(const struct clk_init_data) {
 835		.name = "nss_cc_port3_tx_div_clk_src",
 836		.parent_data = &(const struct clk_parent_data) {
 837			.hw = &nss_cc_port3_tx_clk_src.clkr.hw,
 838		},
 839		.num_parents = 1,
 840		.flags = CLK_SET_RATE_PARENT,
 841		.ops = &clk_regmap_div_ops,
 842	},
 843};
 844
 845static struct clk_regmap_div nss_cc_port4_rx_div_clk_src = {
 846	.reg = 0x28160,
 847	.shift = 0,
 848	.width = 9,
 849	.clkr.hw.init = &(const struct clk_init_data) {
 850		.name = "nss_cc_port4_rx_div_clk_src",
 851		.parent_data = &(const struct clk_parent_data) {
 852			.hw = &nss_cc_port4_rx_clk_src.clkr.hw,
 853		},
 854		.num_parents = 1,
 855		.flags = CLK_SET_RATE_PARENT,
 856		.ops = &clk_regmap_div_ops,
 857	},
 858};
 859
 860static struct clk_regmap_div nss_cc_port4_tx_div_clk_src = {
 861	.reg = 0x2816c,
 862	.shift = 0,
 863	.width = 9,
 864	.clkr.hw.init = &(const struct clk_init_data) {
 865		.name = "nss_cc_port4_tx_div_clk_src",
 866		.parent_data = &(const struct clk_parent_data) {
 867			.hw = &nss_cc_port4_tx_clk_src.clkr.hw,
 868		},
 869		.num_parents = 1,
 870		.flags = CLK_SET_RATE_PARENT,
 871		.ops = &clk_regmap_div_ops,
 872	},
 873};
 874
 875static struct clk_regmap_div nss_cc_port5_rx_div_clk_src = {
 876	.reg = 0x28178,
 877	.shift = 0,
 878	.width = 9,
 879	.clkr.hw.init = &(const struct clk_init_data) {
 880		.name = "nss_cc_port5_rx_div_clk_src",
 881		.parent_data = &(const struct clk_parent_data) {
 882			.hw = &nss_cc_port5_rx_clk_src.clkr.hw,
 883		},
 884		.num_parents = 1,
 885		.flags = CLK_SET_RATE_PARENT,
 886		.ops = &clk_regmap_div_ops,
 887	},
 888};
 889
 890static struct clk_regmap_div nss_cc_port5_tx_div_clk_src = {
 891	.reg = 0x28184,
 892	.shift = 0,
 893	.width = 9,
 894	.clkr.hw.init = &(const struct clk_init_data) {
 895		.name = "nss_cc_port5_tx_div_clk_src",
 896		.parent_data = &(const struct clk_parent_data) {
 897			.hw = &nss_cc_port5_tx_clk_src.clkr.hw,
 898		},
 899		.num_parents = 1,
 900		.flags = CLK_SET_RATE_PARENT,
 901		.ops = &clk_regmap_div_ops,
 902	},
 903};
 904
 905static struct clk_regmap_div nss_cc_port6_rx_div_clk_src = {
 906	.reg = 0x28190,
 907	.shift = 0,
 908	.width = 9,
 909	.clkr.hw.init = &(const struct clk_init_data) {
 910		.name = "nss_cc_port6_rx_div_clk_src",
 911		.parent_data = &(const struct clk_parent_data) {
 912			.hw = &nss_cc_port6_rx_clk_src.clkr.hw,
 913		},
 914		.num_parents = 1,
 915		.flags = CLK_SET_RATE_PARENT,
 916		.ops = &clk_regmap_div_ops,
 917	},
 918};
 919
 920static struct clk_regmap_div nss_cc_port6_tx_div_clk_src = {
 921	.reg = 0x2819c,
 922	.shift = 0,
 923	.width = 9,
 924	.clkr.hw.init = &(const struct clk_init_data) {
 925		.name = "nss_cc_port6_tx_div_clk_src",
 926		.parent_data = &(const struct clk_parent_data) {
 927			.hw = &nss_cc_port6_tx_clk_src.clkr.hw,
 928		},
 929		.num_parents = 1,
 930		.flags = CLK_SET_RATE_PARENT,
 931		.ops = &clk_regmap_div_ops,
 932	},
 933};
 934
 935static struct clk_regmap_div nss_cc_ubi0_div_clk_src = {
 936	.reg = 0x287a4,
 937	.shift = 0,
 938	.width = 4,
 939	.clkr.hw.init = &(const struct clk_init_data) {
 940		.name = "nss_cc_ubi0_div_clk_src",
 941		.parent_data = &(const struct clk_parent_data) {
 942			.hw = &nss_cc_ubi0_clk_src.clkr.hw,
 943		},
 944		.num_parents = 1,
 945		.flags = CLK_SET_RATE_PARENT,
 946		.ops = &clk_regmap_div_ro_ops,
 947	},
 948};
 949
 950static struct clk_regmap_div nss_cc_ubi1_div_clk_src = {
 951	.reg = 0x287a8,
 952	.shift = 0,
 953	.width = 4,
 954	.clkr.hw.init = &(const struct clk_init_data) {
 955		.name = "nss_cc_ubi1_div_clk_src",
 956		.parent_data = &(const struct clk_parent_data) {
 957			.hw = &nss_cc_ubi1_clk_src.clkr.hw,
 958		},
 959		.num_parents = 1,
 960		.flags = CLK_SET_RATE_PARENT,
 961		.ops = &clk_regmap_div_ro_ops,
 962	},
 963};
 964
 965static struct clk_regmap_div nss_cc_ubi2_div_clk_src = {
 966	.reg = 0x287ac,
 967	.shift = 0,
 968	.width = 4,
 969	.clkr.hw.init = &(const struct clk_init_data) {
 970		.name = "nss_cc_ubi2_div_clk_src",
 971		.parent_data = &(const struct clk_parent_data) {
 972			.hw = &nss_cc_ubi2_clk_src.clkr.hw,
 973		},
 974		.num_parents = 1,
 975		.flags = CLK_SET_RATE_PARENT,
 976		.ops = &clk_regmap_div_ro_ops,
 977	},
 978};
 979
 980static struct clk_regmap_div nss_cc_ubi3_div_clk_src = {
 981	.reg = 0x287b0,
 982	.shift = 0,
 983	.width = 4,
 984	.clkr.hw.init = &(const struct clk_init_data) {
 985		.name = "nss_cc_ubi3_div_clk_src",
 986		.parent_data = &(const struct clk_parent_data) {
 987			.hw = &nss_cc_ubi3_clk_src.clkr.hw,
 988		},
 989		.num_parents = 1,
 990		.flags = CLK_SET_RATE_PARENT,
 991		.ops = &clk_regmap_div_ro_ops,
 992	},
 993};
 994
 995static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src = {
 996	.reg = 0x28214,
 997	.shift = 0,
 998	.width = 4,
 999	.clkr.hw.init = &(const struct clk_init_data) {
1000		.name = "nss_cc_xgmac0_ptp_ref_div_clk_src",
1001		.parent_data = &(const struct clk_parent_data) {
1002			.hw = &nss_cc_ppe_clk_src.clkr.hw,
1003		},
1004		.num_parents = 1,
1005		.flags = CLK_SET_RATE_PARENT,
1006		.ops = &clk_regmap_div_ro_ops,
1007	},
1008};
1009
1010static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src = {
1011	.reg = 0x28218,
1012	.shift = 0,
1013	.width = 4,
1014	.clkr.hw.init = &(const struct clk_init_data) {
1015		.name = "nss_cc_xgmac1_ptp_ref_div_clk_src",
1016		.parent_data = &(const struct clk_parent_data) {
1017			.hw = &nss_cc_ppe_clk_src.clkr.hw,
1018		},
1019		.num_parents = 1,
1020		.flags = CLK_SET_RATE_PARENT,
1021		.ops = &clk_regmap_div_ro_ops,
1022	},
1023};
1024
1025static struct clk_regmap_div nss_cc_xgmac2_ptp_ref_div_clk_src = {
1026	.reg = 0x2821c,
1027	.shift = 0,
1028	.width = 4,
1029	.clkr.hw.init = &(const struct clk_init_data) {
1030		.name = "nss_cc_xgmac2_ptp_ref_div_clk_src",
1031		.parent_data = &(const struct clk_parent_data) {
1032			.hw = &nss_cc_ppe_clk_src.clkr.hw,
1033		},
1034		.num_parents = 1,
1035		.flags = CLK_SET_RATE_PARENT,
1036		.ops = &clk_regmap_div_ro_ops,
1037	},
1038};
1039
1040static struct clk_regmap_div nss_cc_xgmac3_ptp_ref_div_clk_src = {
1041	.reg = 0x28220,
1042	.shift = 0,
1043	.width = 4,
1044	.clkr.hw.init = &(const struct clk_init_data) {
1045		.name = "nss_cc_xgmac3_ptp_ref_div_clk_src",
1046		.parent_data = &(const struct clk_parent_data) {
1047			.hw = &nss_cc_ppe_clk_src.clkr.hw,
1048		},
1049		.num_parents = 1,
1050		.flags = CLK_SET_RATE_PARENT,
1051		.ops = &clk_regmap_div_ro_ops,
1052	},
1053};
1054
1055static struct clk_regmap_div nss_cc_xgmac4_ptp_ref_div_clk_src = {
1056	.reg = 0x28224,
1057	.shift = 0,
1058	.width = 4,
1059	.clkr.hw.init = &(const struct clk_init_data) {
1060		.name = "nss_cc_xgmac4_ptp_ref_div_clk_src",
1061		.parent_data = &(const struct clk_parent_data) {
1062			.hw = &nss_cc_ppe_clk_src.clkr.hw,
1063		},
1064		.num_parents = 1,
1065		.flags = CLK_SET_RATE_PARENT,
1066		.ops = &clk_regmap_div_ro_ops,
1067	},
1068};
1069
1070static struct clk_regmap_div nss_cc_xgmac5_ptp_ref_div_clk_src = {
1071	.reg = 0x28228,
1072	.shift = 0,
1073	.width = 4,
1074	.clkr.hw.init = &(const struct clk_init_data) {
1075		.name = "nss_cc_xgmac5_ptp_ref_div_clk_src",
1076		.parent_data = &(const struct clk_parent_data) {
1077			.hw = &nss_cc_ppe_clk_src.clkr.hw,
1078		},
1079		.num_parents = 1,
1080		.flags = CLK_SET_RATE_PARENT,
1081		.ops = &clk_regmap_div_ro_ops,
1082	},
1083};
1084
1085static struct clk_branch nss_cc_ce_apb_clk = {
1086	.halt_reg = 0x2840c,
1087	.clkr = {
1088		.enable_reg = 0x2840c,
1089		.enable_mask = BIT(0),
1090		.hw.init = &(const struct clk_init_data) {
1091			.name = "nss_cc_ce_apb_clk",
1092			.parent_data = &(const struct clk_parent_data) {
1093				.hw = &nss_cc_ce_clk_src.clkr.hw,
1094			},
1095			.num_parents = 1,
1096			.flags = CLK_SET_RATE_PARENT,
1097			.ops = &clk_branch2_ops,
1098		},
1099	},
1100};
1101
1102static struct clk_branch nss_cc_ce_axi_clk = {
1103	.halt_reg = 0x28410,
1104	.halt_check = BRANCH_HALT,
1105	.clkr = {
1106		.enable_reg = 0x28410,
1107		.enable_mask = BIT(0),
1108		.hw.init = &(const struct clk_init_data) {
1109			.name = "nss_cc_ce_axi_clk",
1110			.parent_data = &(const struct clk_parent_data) {
1111				.hw = &nss_cc_ce_clk_src.clkr.hw,
1112			},
1113			.num_parents = 1,
1114			.flags = CLK_SET_RATE_PARENT,
1115			.ops = &clk_branch2_ops,
1116		},
1117	},
1118};
1119
1120static struct clk_branch nss_cc_clc_axi_clk = {
1121	.halt_reg = 0x2860c,
1122	.halt_check = BRANCH_HALT,
1123	.clkr = {
1124		.enable_reg = 0x2860c,
1125		.enable_mask = BIT(0),
1126		.hw.init = &(const struct clk_init_data) {
1127			.name = "nss_cc_clc_axi_clk",
1128			.parent_data = &(const struct clk_parent_data) {
1129				.hw = &nss_cc_clc_clk_src.clkr.hw,
1130			},
1131			.num_parents = 1,
1132			.flags = CLK_SET_RATE_PARENT,
1133			.ops = &clk_branch2_ops,
1134		},
1135	},
1136};
1137
1138static struct clk_branch nss_cc_crypto_clk = {
1139	.halt_reg = 0x1601c,
1140	.halt_check = BRANCH_HALT,
1141	.clkr = {
1142		.enable_reg = 0x1601c,
1143		.enable_mask = BIT(0),
1144		.hw.init = &(const struct clk_init_data) {
1145			.name = "nss_cc_crypto_clk",
1146			.parent_data = &(const struct clk_parent_data) {
1147				.hw = &nss_cc_crypto_clk_src.clkr.hw,
1148			},
1149			.num_parents = 1,
1150			.flags = CLK_SET_RATE_PARENT,
1151			.ops = &clk_branch2_ops,
1152		},
1153	},
1154};
1155
1156static struct clk_branch nss_cc_crypto_ppe_clk = {
1157	.halt_reg = 0x28240,
1158	.halt_check = BRANCH_HALT,
1159	.clkr = {
1160		.enable_reg = 0x28240,
1161		.enable_mask = BIT(0),
1162		.hw.init = &(const struct clk_init_data) {
1163			.name = "nss_cc_crypto_ppe_clk",
1164			.parent_data = &(const struct clk_parent_data) {
1165				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1166			},
1167			.num_parents = 1,
1168			.flags = CLK_SET_RATE_PARENT,
1169			.ops = &clk_branch2_ops,
1170		},
1171	},
1172};
1173
1174static struct clk_branch nss_cc_haq_ahb_clk = {
1175	.halt_reg = 0x2830c,
1176	.halt_check = BRANCH_HALT,
1177	.clkr = {
1178		.enable_reg = 0x2830c,
1179		.enable_mask = BIT(0),
1180		.hw.init = &(const struct clk_init_data) {
1181			.name = "nss_cc_haq_ahb_clk",
1182			.parent_data = &(const struct clk_parent_data) {
1183				.hw = &nss_cc_haq_clk_src.clkr.hw,
1184			},
1185			.num_parents = 1,
1186			.flags = CLK_SET_RATE_PARENT,
1187			.ops = &clk_branch2_ops,
1188		},
1189	},
1190};
1191
1192static struct clk_branch nss_cc_haq_axi_clk = {
1193	.halt_reg = 0x28310,
1194	.halt_check = BRANCH_HALT,
1195	.clkr = {
1196		.enable_reg = 0x28310,
1197		.enable_mask = BIT(0),
1198		.hw.init = &(const struct clk_init_data) {
1199			.name = "nss_cc_haq_axi_clk",
1200			.parent_data = &(const struct clk_parent_data) {
1201				.hw = &nss_cc_haq_clk_src.clkr.hw,
1202			},
1203			.num_parents = 1,
1204			.flags = CLK_SET_RATE_PARENT,
1205			.ops = &clk_branch2_ops,
1206		},
1207	},
1208};
1209
1210static struct clk_branch nss_cc_imem_ahb_clk = {
1211	.halt_reg = 0xe018,
1212	.halt_check = BRANCH_HALT,
1213	.clkr = {
1214		.enable_reg = 0xe018,
1215		.enable_mask = BIT(0),
1216		.hw.init = &(const struct clk_init_data) {
1217			.name = "nss_cc_imem_ahb_clk",
1218			.parent_data = &(const struct clk_parent_data) {
1219				.hw = &nss_cc_cfg_clk_src.clkr.hw,
1220			},
1221			.num_parents = 1,
1222			.flags = CLK_SET_RATE_PARENT,
1223			.ops = &clk_branch2_ops,
1224		},
1225	},
1226};
1227
1228static struct clk_branch nss_cc_imem_qsb_clk = {
1229	.halt_reg = 0xe010,
1230	.halt_check = BRANCH_HALT,
1231	.clkr = {
1232		.enable_reg = 0xe010,
1233		.enable_mask = BIT(0),
1234		.hw.init = &(const struct clk_init_data) {
1235			.name = "nss_cc_imem_qsb_clk",
1236			.parent_data = &(const struct clk_parent_data) {
1237				.hw = &nss_cc_imem_clk_src.clkr.hw,
1238			},
1239			.num_parents = 1,
1240			.flags = CLK_SET_RATE_PARENT,
1241			.ops = &clk_branch2_ops,
1242		},
1243	},
1244};
1245
1246static struct clk_branch nss_cc_nss_csr_clk = {
1247	.halt_reg = 0x281d0,
1248	.halt_check = BRANCH_HALT,
1249	.clkr = {
1250		.enable_reg = 0x281d0,
1251		.enable_mask = BIT(0),
1252		.hw.init = &(const struct clk_init_data) {
1253			.name = "nss_cc_nss_csr_clk",
1254			.parent_data = &(const struct clk_parent_data) {
1255				.hw = &nss_cc_cfg_clk_src.clkr.hw,
1256			},
1257			.num_parents = 1,
1258			.flags = CLK_SET_RATE_PARENT,
1259			.ops = &clk_branch2_ops,
1260		},
1261	},
1262};
1263
1264static struct clk_branch nss_cc_nssnoc_ce_apb_clk = {
1265	.halt_reg = 0x28414,
1266	.halt_check = BRANCH_HALT,
1267	.clkr = {
1268		.enable_reg = 0x28414,
1269		.enable_mask = BIT(0),
1270		.hw.init = &(const struct clk_init_data) {
1271			.name = "nss_cc_nssnoc_ce_apb_clk",
1272			.parent_data = &(const struct clk_parent_data) {
1273				.hw = &nss_cc_ce_clk_src.clkr.hw,
1274			},
1275			.num_parents = 1,
1276			.flags = CLK_SET_RATE_PARENT,
1277			.ops = &clk_branch2_ops,
1278		},
1279	},
1280};
1281
1282static struct clk_branch nss_cc_nssnoc_ce_axi_clk = {
1283	.halt_reg = 0x28418,
1284	.halt_check = BRANCH_HALT,
1285	.clkr = {
1286		.enable_reg = 0x28418,
1287		.enable_mask = BIT(0),
1288		.hw.init = &(const struct clk_init_data) {
1289			.name = "nss_cc_nssnoc_ce_axi_clk",
1290			.parent_data = &(const struct clk_parent_data) {
1291				.hw = &nss_cc_ce_clk_src.clkr.hw,
1292			},
1293			.num_parents = 1,
1294			.flags = CLK_SET_RATE_PARENT,
1295			.ops = &clk_branch2_ops,
1296		},
1297	},
1298};
1299
1300static struct clk_branch nss_cc_nssnoc_clc_axi_clk = {
1301	.halt_reg = 0x28610,
1302	.halt_check = BRANCH_HALT,
1303	.clkr = {
1304		.enable_reg = 0x28610,
1305		.enable_mask = BIT(0),
1306		.hw.init = &(const struct clk_init_data) {
1307			.name = "nss_cc_nssnoc_clc_axi_clk",
1308			.parent_data = &(const struct clk_parent_data) {
1309				.hw = &nss_cc_clc_clk_src.clkr.hw,
1310			},
1311			.num_parents = 1,
1312			.flags = CLK_SET_RATE_PARENT,
1313			.ops = &clk_branch2_ops,
1314		},
1315	},
1316};
1317
1318static struct clk_branch nss_cc_nssnoc_crypto_clk = {
1319	.halt_reg = 0x16020,
1320	.halt_check = BRANCH_HALT,
1321	.clkr = {
1322		.enable_reg = 0x16020,
1323		.enable_mask = BIT(0),
1324		.hw.init = &(const struct clk_init_data) {
1325			.name = "nss_cc_nssnoc_crypto_clk",
1326			.parent_data = &(const struct clk_parent_data) {
1327				.hw = &nss_cc_crypto_clk_src.clkr.hw,
1328			},
1329			.num_parents = 1,
1330			.flags = CLK_SET_RATE_PARENT,
1331			.ops = &clk_branch2_ops,
1332		},
1333	},
1334};
1335
1336static struct clk_branch nss_cc_nssnoc_haq_ahb_clk = {
1337	.halt_reg = 0x28314,
1338	.halt_check = BRANCH_HALT,
1339	.clkr = {
1340		.enable_reg = 0x28314,
1341		.enable_mask = BIT(0),
1342		.hw.init = &(const struct clk_init_data) {
1343			.name = "nss_cc_nssnoc_haq_ahb_clk",
1344			.parent_data = &(const struct clk_parent_data) {
1345				.hw = &nss_cc_haq_clk_src.clkr.hw,
1346			},
1347			.num_parents = 1,
1348			.flags = CLK_SET_RATE_PARENT,
1349			.ops = &clk_branch2_ops,
1350		},
1351	},
1352};
1353
1354static struct clk_branch nss_cc_nssnoc_haq_axi_clk = {
1355	.halt_reg = 0x28318,
1356	.halt_check = BRANCH_HALT,
1357	.clkr = {
1358		.enable_reg = 0x28318,
1359		.enable_mask = BIT(0),
1360		.hw.init = &(const struct clk_init_data) {
1361			.name = "nss_cc_nssnoc_haq_axi_clk",
1362			.parent_data = &(const struct clk_parent_data) {
1363				.hw = &nss_cc_haq_clk_src.clkr.hw,
1364			},
1365			.num_parents = 1,
1366			.flags = CLK_SET_RATE_PARENT,
1367			.ops = &clk_branch2_ops,
1368		},
1369	},
1370};
1371
1372static struct clk_branch nss_cc_nssnoc_imem_ahb_clk = {
1373	.halt_reg = 0xe01c,
1374	.halt_check = BRANCH_HALT,
1375	.clkr = {
1376		.enable_reg = 0xe01c,
1377		.enable_mask = BIT(0),
1378		.hw.init = &(const struct clk_init_data) {
1379			.name = "nss_cc_nssnoc_imem_ahb_clk",
1380			.parent_data = &(const struct clk_parent_data) {
1381				.hw = &nss_cc_cfg_clk_src.clkr.hw,
1382			},
1383			.num_parents = 1,
1384			.flags = CLK_SET_RATE_PARENT,
1385			.ops = &clk_branch2_ops,
1386		},
1387	},
1388};
1389
1390static struct clk_branch nss_cc_nssnoc_imem_qsb_clk = {
1391	.halt_reg = 0xe014,
1392	.halt_check = BRANCH_HALT,
1393	.clkr = {
1394		.enable_reg = 0xe014,
1395		.enable_mask = BIT(0),
1396		.hw.init = &(const struct clk_init_data) {
1397			.name = "nss_cc_nssnoc_imem_qsb_clk",
1398			.parent_data = &(const struct clk_parent_data) {
1399				.hw = &nss_cc_imem_clk_src.clkr.hw,
1400			},
1401			.num_parents = 1,
1402			.flags = CLK_SET_RATE_PARENT,
1403			.ops = &clk_branch2_ops,
1404		},
1405	},
1406};
1407
1408static struct clk_branch nss_cc_nssnoc_nss_csr_clk = {
1409	.halt_reg = 0x281d4,
1410	.halt_check = BRANCH_HALT,
1411	.clkr = {
1412		.enable_reg = 0x281d4,
1413		.enable_mask = BIT(0),
1414		.hw.init = &(const struct clk_init_data) {
1415			.name = "nss_cc_nssnoc_nss_csr_clk",
1416			.parent_data = &(const struct clk_parent_data) {
1417				.hw = &nss_cc_cfg_clk_src.clkr.hw,
1418			},
1419			.num_parents = 1,
1420			.flags = CLK_SET_RATE_PARENT,
1421			.ops = &clk_branch2_ops,
1422		},
1423	},
1424};
1425
1426static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk = {
1427	.halt_reg = 0x28248,
1428	.halt_check = BRANCH_HALT,
1429	.clkr = {
1430		.enable_reg = 0x28248,
1431		.enable_mask = BIT(0),
1432		.hw.init = &(const struct clk_init_data) {
1433			.name = "nss_cc_nssnoc_ppe_cfg_clk",
1434			.parent_data = &(const struct clk_parent_data) {
1435				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1436			},
1437			.num_parents = 1,
1438			.flags = CLK_SET_RATE_PARENT,
1439			.ops = &clk_branch2_ops,
1440		},
1441	},
1442};
1443
1444static struct clk_branch nss_cc_nssnoc_ppe_clk = {
1445	.halt_reg = 0x28244,
1446	.halt_check = BRANCH_HALT,
1447	.clkr = {
1448		.enable_reg = 0x28244,
1449		.enable_mask = BIT(0),
1450		.hw.init = &(const struct clk_init_data) {
1451			.name = "nss_cc_nssnoc_ppe_clk",
1452			.parent_data = &(const struct clk_parent_data) {
1453				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1454			},
1455			.num_parents = 1,
1456			.flags = CLK_SET_RATE_PARENT,
1457			.ops = &clk_branch2_ops,
1458		},
1459	},
1460};
1461
1462static struct clk_branch nss_cc_nssnoc_ubi32_ahb0_clk = {
1463	.halt_reg = 0x28788,
1464	.halt_check = BRANCH_HALT,
1465	.clkr = {
1466		.enable_reg = 0x28788,
1467		.enable_mask = BIT(0),
1468		.hw.init = &(const struct clk_init_data) {
1469			.name = "nss_cc_nssnoc_ubi32_ahb0_clk",
1470			.parent_data = &(const struct clk_parent_data) {
1471				.hw = &nss_cc_cfg_clk_src.clkr.hw,
1472			},
1473			.num_parents = 1,
1474			.flags = CLK_SET_RATE_PARENT,
1475			.ops = &clk_branch2_ops,
1476		},
1477	},
1478};
1479
1480static struct clk_branch nss_cc_nssnoc_ubi32_axi0_clk = {
1481	.halt_reg = 0x287a0,
1482	.halt_check = BRANCH_HALT,
1483	.clkr = {
1484		.enable_reg = 0x287a0,
1485		.enable_mask = BIT(0),
1486		.hw.init = &(const struct clk_init_data) {
1487			.name = "nss_cc_nssnoc_ubi32_axi0_clk",
1488			.parent_data = &(const struct clk_parent_data) {
1489				.hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
1490			},
1491			.num_parents = 1,
1492			.flags = CLK_SET_RATE_PARENT,
1493			.ops = &clk_branch2_ops,
1494		},
1495	},
1496};
1497
1498static struct clk_branch nss_cc_nssnoc_ubi32_int0_ahb_clk = {
1499	.halt_reg = 0x2878c,
1500	.halt_check = BRANCH_HALT,
1501	.clkr = {
1502		.enable_reg = 0x2878c,
1503		.enable_mask = BIT(0),
1504		.hw.init = &(const struct clk_init_data) {
1505			.name = "nss_cc_nssnoc_ubi32_int0_ahb_clk",
1506			.parent_data = &(const struct clk_parent_data) {
1507				.hw = &nss_cc_int_cfg_clk_src.clkr.hw,
1508			},
1509			.num_parents = 1,
1510			.flags = CLK_SET_RATE_PARENT,
1511			.ops = &clk_branch2_ops,
1512		},
1513	},
1514};
1515
1516static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_1_clk = {
1517	.halt_reg = 0x287bc,
1518	.halt_check = BRANCH_HALT,
1519	.clkr = {
1520		.enable_reg = 0x287bc,
1521		.enable_mask = BIT(0),
1522		.hw.init = &(const struct clk_init_data) {
1523			.name = "nss_cc_nssnoc_ubi32_nc_axi0_1_clk",
1524			.parent_data = &(const struct clk_parent_data) {
1525				.hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
1526			},
1527			.num_parents = 1,
1528			.flags = CLK_SET_RATE_PARENT,
1529			.ops = &clk_branch2_ops,
1530		},
1531	},
1532};
1533
1534static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_clk = {
1535	.halt_reg = 0x28764,
1536	.halt_check = BRANCH_HALT,
1537	.clkr = {
1538		.enable_reg = 0x28764,
1539		.enable_mask = BIT(0),
1540		.hw.init = &(const struct clk_init_data) {
1541			.name = "nss_cc_nssnoc_ubi32_nc_axi0_clk",
1542			.parent_data = &(const struct clk_parent_data) {
1543				.hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
1544			},
1545			.num_parents = 1,
1546			.flags = CLK_SET_RATE_PARENT,
1547			.ops = &clk_branch2_ops,
1548		},
1549	},
1550};
1551
1552static struct clk_branch nss_cc_port1_mac_clk = {
1553	.halt_reg = 0x2824c,
1554	.halt_check = BRANCH_HALT,
1555	.clkr = {
1556		.enable_reg = 0x2824c,
1557		.enable_mask = BIT(0),
1558		.hw.init = &(const struct clk_init_data) {
1559			.name = "nss_cc_port1_mac_clk",
1560			.parent_data = &(const struct clk_parent_data) {
1561				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1562			},
1563			.num_parents = 1,
1564			.flags = CLK_SET_RATE_PARENT,
1565			.ops = &clk_branch2_ops,
1566		},
1567	},
1568};
1569
1570static struct clk_branch nss_cc_port1_rx_clk = {
1571	.halt_reg = 0x281a0,
1572	.halt_check = BRANCH_HALT,
1573	.clkr = {
1574		.enable_reg = 0x281a0,
1575		.enable_mask = BIT(0),
1576		.hw.init = &(const struct clk_init_data) {
1577			.name = "nss_cc_port1_rx_clk",
1578			.parent_data = &(const struct clk_parent_data) {
1579				.hw = &nss_cc_port1_rx_div_clk_src.clkr.hw,
1580			},
1581			.num_parents = 1,
1582			.flags = CLK_SET_RATE_PARENT,
1583			.ops = &clk_branch2_ops,
1584		},
1585	},
1586};
1587
1588static struct clk_branch nss_cc_port1_tx_clk = {
1589	.halt_reg = 0x281a4,
1590	.halt_check = BRANCH_HALT,
1591	.clkr = {
1592		.enable_reg = 0x281a4,
1593		.enable_mask = BIT(0),
1594		.hw.init = &(const struct clk_init_data) {
1595			.name = "nss_cc_port1_tx_clk",
1596			.parent_data = &(const struct clk_parent_data) {
1597				.hw = &nss_cc_port1_tx_div_clk_src.clkr.hw,
1598			},
1599			.num_parents = 1,
1600			.flags = CLK_SET_RATE_PARENT,
1601			.ops = &clk_branch2_ops,
1602		},
1603	},
1604};
1605
1606static struct clk_branch nss_cc_port2_mac_clk = {
1607	.halt_reg = 0x28250,
1608	.halt_check = BRANCH_HALT,
1609	.clkr = {
1610		.enable_reg = 0x28250,
1611		.enable_mask = BIT(0),
1612		.hw.init = &(const struct clk_init_data) {
1613			.name = "nss_cc_port2_mac_clk",
1614			.parent_data = &(const struct clk_parent_data) {
1615				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1616			},
1617			.num_parents = 1,
1618			.flags = CLK_SET_RATE_PARENT,
1619			.ops = &clk_branch2_ops,
1620		},
1621	},
1622};
1623
1624static struct clk_branch nss_cc_port2_rx_clk = {
1625	.halt_reg = 0x281a8,
1626	.halt_check = BRANCH_HALT,
1627	.clkr = {
1628		.enable_reg = 0x281a8,
1629		.enable_mask = BIT(0),
1630		.hw.init = &(const struct clk_init_data) {
1631			.name = "nss_cc_port2_rx_clk",
1632			.parent_data = &(const struct clk_parent_data) {
1633				.hw = &nss_cc_port2_rx_div_clk_src.clkr.hw,
1634			},
1635			.num_parents = 1,
1636			.flags = CLK_SET_RATE_PARENT,
1637			.ops = &clk_branch2_ops,
1638		},
1639	},
1640};
1641
1642static struct clk_branch nss_cc_port2_tx_clk = {
1643	.halt_reg = 0x281ac,
1644	.halt_check = BRANCH_HALT,
1645	.clkr = {
1646		.enable_reg = 0x281ac,
1647		.enable_mask = BIT(0),
1648		.hw.init = &(const struct clk_init_data) {
1649			.name = "nss_cc_port2_tx_clk",
1650			.parent_data = &(const struct clk_parent_data) {
1651				.hw = &nss_cc_port2_tx_div_clk_src.clkr.hw,
1652			},
1653			.num_parents = 1,
1654			.flags = CLK_SET_RATE_PARENT,
1655			.ops = &clk_branch2_ops,
1656		},
1657	},
1658};
1659
1660static struct clk_branch nss_cc_port3_mac_clk = {
1661	.halt_reg = 0x28254,
1662	.halt_check = BRANCH_HALT,
1663	.clkr = {
1664		.enable_reg = 0x28254,
1665		.enable_mask = BIT(0),
1666		.hw.init = &(const struct clk_init_data) {
1667			.name = "nss_cc_port3_mac_clk",
1668			.parent_data = &(const struct clk_parent_data) {
1669				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1670			},
1671			.num_parents = 1,
1672			.flags = CLK_SET_RATE_PARENT,
1673			.ops = &clk_branch2_ops,
1674		},
1675	},
1676};
1677
1678static struct clk_branch nss_cc_port3_rx_clk = {
1679	.halt_reg = 0x281b0,
1680	.halt_check = BRANCH_HALT,
1681	.clkr = {
1682		.enable_reg = 0x281b0,
1683		.enable_mask = BIT(0),
1684		.hw.init = &(const struct clk_init_data) {
1685			.name = "nss_cc_port3_rx_clk",
1686			.parent_data = &(const struct clk_parent_data) {
1687				.hw = &nss_cc_port3_rx_div_clk_src.clkr.hw,
1688			},
1689			.num_parents = 1,
1690			.flags = CLK_SET_RATE_PARENT,
1691			.ops = &clk_branch2_ops,
1692		},
1693	},
1694};
1695
1696static struct clk_branch nss_cc_port3_tx_clk = {
1697	.halt_reg = 0x281b4,
1698	.halt_check = BRANCH_HALT,
1699	.clkr = {
1700		.enable_reg = 0x281b4,
1701		.enable_mask = BIT(0),
1702		.hw.init = &(const struct clk_init_data) {
1703			.name = "nss_cc_port3_tx_clk",
1704			.parent_data = &(const struct clk_parent_data) {
1705				.hw = &nss_cc_port3_tx_div_clk_src.clkr.hw,
1706			},
1707			.num_parents = 1,
1708			.flags = CLK_SET_RATE_PARENT,
1709			.ops = &clk_branch2_ops,
1710		},
1711	},
1712};
1713
1714static struct clk_branch nss_cc_port4_mac_clk = {
1715	.halt_reg = 0x28258,
1716	.halt_check = BRANCH_HALT,
1717	.clkr = {
1718		.enable_reg = 0x28258,
1719		.enable_mask = BIT(0),
1720		.hw.init = &(const struct clk_init_data) {
1721			.name = "nss_cc_port4_mac_clk",
1722			.parent_data = &(const struct clk_parent_data) {
1723				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1724			},
1725			.num_parents = 1,
1726			.flags = CLK_SET_RATE_PARENT,
1727			.ops = &clk_branch2_ops,
1728		},
1729	},
1730};
1731
1732static struct clk_branch nss_cc_port4_rx_clk = {
1733	.halt_reg = 0x281b8,
1734	.halt_check = BRANCH_HALT,
1735	.clkr = {
1736		.enable_reg = 0x281b8,
1737		.enable_mask = BIT(0),
1738		.hw.init = &(const struct clk_init_data) {
1739			.name = "nss_cc_port4_rx_clk",
1740			.parent_data = &(const struct clk_parent_data) {
1741				.hw = &nss_cc_port4_rx_div_clk_src.clkr.hw,
1742			},
1743			.num_parents = 1,
1744			.flags = CLK_SET_RATE_PARENT,
1745			.ops = &clk_branch2_ops,
1746		},
1747	},
1748};
1749
1750static struct clk_branch nss_cc_port4_tx_clk = {
1751	.halt_reg = 0x281bc,
1752	.halt_check = BRANCH_HALT,
1753	.clkr = {
1754		.enable_reg = 0x281bc,
1755		.enable_mask = BIT(0),
1756		.hw.init = &(const struct clk_init_data) {
1757			.name = "nss_cc_port4_tx_clk",
1758			.parent_data = &(const struct clk_parent_data) {
1759				.hw = &nss_cc_port4_tx_div_clk_src.clkr.hw,
1760			},
1761			.num_parents = 1,
1762			.flags = CLK_SET_RATE_PARENT,
1763			.ops = &clk_branch2_ops,
1764		},
1765	},
1766};
1767
1768static struct clk_branch nss_cc_port5_mac_clk = {
1769	.halt_reg = 0x2825c,
1770	.halt_check = BRANCH_HALT,
1771	.clkr = {
1772		.enable_reg = 0x2825c,
1773		.enable_mask = BIT(0),
1774		.hw.init = &(const struct clk_init_data) {
1775			.name = "nss_cc_port5_mac_clk",
1776			.parent_data = &(const struct clk_parent_data) {
1777				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1778			},
1779			.num_parents = 1,
1780			.flags = CLK_SET_RATE_PARENT,
1781			.ops = &clk_branch2_ops,
1782		},
1783	},
1784};
1785
1786static struct clk_branch nss_cc_port5_rx_clk = {
1787	.halt_reg = 0x281c0,
1788	.halt_check = BRANCH_HALT,
1789	.clkr = {
1790		.enable_reg = 0x281c0,
1791		.enable_mask = BIT(0),
1792		.hw.init = &(const struct clk_init_data) {
1793			.name = "nss_cc_port5_rx_clk",
1794			.parent_data = &(const struct clk_parent_data) {
1795				.hw = &nss_cc_port5_rx_div_clk_src.clkr.hw,
1796			},
1797			.num_parents = 1,
1798			.flags = CLK_SET_RATE_PARENT,
1799			.ops = &clk_branch2_ops,
1800		},
1801	},
1802};
1803
1804static struct clk_branch nss_cc_port5_tx_clk = {
1805	.halt_reg = 0x281c4,
1806	.halt_check = BRANCH_HALT,
1807	.clkr = {
1808		.enable_reg = 0x281c4,
1809		.enable_mask = BIT(0),
1810		.hw.init = &(const struct clk_init_data) {
1811			.name = "nss_cc_port5_tx_clk",
1812			.parent_data = &(const struct clk_parent_data) {
1813				.hw = &nss_cc_port5_tx_div_clk_src.clkr.hw,
1814			},
1815			.num_parents = 1,
1816			.flags = CLK_SET_RATE_PARENT,
1817			.ops = &clk_branch2_ops,
1818		},
1819	},
1820};
1821
1822static struct clk_branch nss_cc_port6_mac_clk = {
1823	.halt_reg = 0x28260,
1824	.halt_check = BRANCH_HALT,
1825	.clkr = {
1826		.enable_reg = 0x28260,
1827		.enable_mask = BIT(0),
1828		.hw.init = &(const struct clk_init_data) {
1829			.name = "nss_cc_port6_mac_clk",
1830			.parent_data = &(const struct clk_parent_data) {
1831				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1832			},
1833			.num_parents = 1,
1834			.flags = CLK_SET_RATE_PARENT,
1835			.ops = &clk_branch2_ops,
1836		},
1837	},
1838};
1839
1840static struct clk_branch nss_cc_port6_rx_clk = {
1841	.halt_reg = 0x281c8,
1842	.halt_check = BRANCH_HALT,
1843	.clkr = {
1844		.enable_reg = 0x281c8,
1845		.enable_mask = BIT(0),
1846		.hw.init = &(const struct clk_init_data) {
1847			.name = "nss_cc_port6_rx_clk",
1848			.parent_data = &(const struct clk_parent_data) {
1849				.hw = &nss_cc_port6_rx_div_clk_src.clkr.hw,
1850			},
1851			.num_parents = 1,
1852			.flags = CLK_SET_RATE_PARENT,
1853			.ops = &clk_branch2_ops,
1854		},
1855	},
1856};
1857
1858static struct clk_branch nss_cc_port6_tx_clk = {
1859	.halt_reg = 0x281cc,
1860	.halt_check = BRANCH_HALT,
1861	.clkr = {
1862		.enable_reg = 0x281cc,
1863		.enable_mask = BIT(0),
1864		.hw.init = &(const struct clk_init_data) {
1865			.name = "nss_cc_port6_tx_clk",
1866			.parent_data = &(const struct clk_parent_data) {
1867				.hw = &nss_cc_port6_tx_div_clk_src.clkr.hw,
1868			},
1869			.num_parents = 1,
1870			.flags = CLK_SET_RATE_PARENT,
1871			.ops = &clk_branch2_ops,
1872		},
1873	},
1874};
1875
1876static struct clk_branch nss_cc_ppe_edma_cfg_clk = {
1877	.halt_reg = 0x2823c,
1878	.halt_check = BRANCH_HALT,
1879	.clkr = {
1880		.enable_reg = 0x2823c,
1881		.enable_mask = BIT(0),
1882		.hw.init = &(const struct clk_init_data) {
1883			.name = "nss_cc_ppe_edma_cfg_clk",
1884			.parent_data = &(const struct clk_parent_data) {
1885				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1886			},
1887			.num_parents = 1,
1888			.flags = CLK_SET_RATE_PARENT,
1889			.ops = &clk_branch2_ops,
1890		},
1891	},
1892};
1893
1894static struct clk_branch nss_cc_ppe_edma_clk = {
1895	.halt_reg = 0x28238,
1896	.halt_check = BRANCH_HALT,
1897	.clkr = {
1898		.enable_reg = 0x28238,
1899		.enable_mask = BIT(0),
1900		.hw.init = &(const struct clk_init_data) {
1901			.name = "nss_cc_ppe_edma_clk",
1902			.parent_data = &(const struct clk_parent_data) {
1903				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1904			},
1905			.num_parents = 1,
1906			.flags = CLK_SET_RATE_PARENT,
1907			.ops = &clk_branch2_ops,
1908		},
1909	},
1910};
1911
1912static struct clk_branch nss_cc_ppe_switch_btq_clk = {
1913	.halt_reg = 0x2827c,
1914	.halt_check = BRANCH_HALT,
1915	.clkr = {
1916		.enable_reg = 0x2827c,
1917		.enable_mask = BIT(0),
1918		.hw.init = &(const struct clk_init_data) {
1919			.name = "nss_cc_ppe_switch_btq_clk",
1920			.parent_data = &(const struct clk_parent_data) {
1921				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1922			},
1923			.num_parents = 1,
1924			.flags = CLK_SET_RATE_PARENT,
1925			.ops = &clk_branch2_ops,
1926		},
1927	},
1928};
1929
1930static struct clk_branch nss_cc_ppe_switch_cfg_clk = {
1931	.halt_reg = 0x28234,
1932	.halt_check = BRANCH_HALT,
1933	.clkr = {
1934		.enable_reg = 0x28234,
1935		.enable_mask = BIT(0),
1936		.hw.init = &(const struct clk_init_data) {
1937			.name = "nss_cc_ppe_switch_cfg_clk",
1938			.parent_data = &(const struct clk_parent_data) {
1939				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1940			},
1941			.num_parents = 1,
1942			.flags = CLK_SET_RATE_PARENT,
1943			.ops = &clk_branch2_ops,
1944		},
1945	},
1946};
1947
1948static struct clk_branch nss_cc_ppe_switch_clk = {
1949	.halt_reg = 0x28230,
1950	.halt_check = BRANCH_HALT,
1951	.clkr = {
1952		.enable_reg = 0x28230,
1953		.enable_mask = BIT(0),
1954		.hw.init = &(const struct clk_init_data) {
1955			.name = "nss_cc_ppe_switch_clk",
1956			.parent_data = &(const struct clk_parent_data) {
1957				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1958			},
1959			.num_parents = 1,
1960			.flags = CLK_SET_RATE_PARENT,
1961			.ops = &clk_branch2_ops,
1962		},
1963	},
1964};
1965
1966static struct clk_branch nss_cc_ppe_switch_ipe_clk = {
1967	.halt_reg = 0x2822c,
1968	.halt_check = BRANCH_HALT,
1969	.clkr = {
1970		.enable_reg = 0x2822c,
1971		.enable_mask = BIT(0),
1972		.hw.init = &(const struct clk_init_data) {
1973			.name = "nss_cc_ppe_switch_ipe_clk",
1974			.parent_data = &(const struct clk_parent_data) {
1975				.hw = &nss_cc_ppe_clk_src.clkr.hw,
1976			},
1977			.num_parents = 1,
1978			.flags = CLK_SET_RATE_PARENT,
1979			.ops = &clk_branch2_ops,
1980		},
1981	},
1982};
1983
1984static struct clk_branch nss_cc_ubi32_ahb0_clk = {
1985	.halt_reg = 0x28768,
1986	.halt_check = BRANCH_HALT,
1987	.clkr = {
1988		.enable_reg = 0x28768,
1989		.enable_mask = BIT(0),
1990		.hw.init = &(const struct clk_init_data) {
1991			.name = "nss_cc_ubi32_ahb0_clk",
1992			.parent_data = &(const struct clk_parent_data) {
1993				.hw = &nss_cc_cfg_clk_src.clkr.hw,
1994			},
1995			.num_parents = 1,
1996			.flags = CLK_SET_RATE_PARENT,
1997			.ops = &clk_branch2_ops,
1998		},
1999	},
2000};
2001
2002static struct clk_branch nss_cc_ubi32_ahb1_clk = {
2003	.halt_reg = 0x28770,
2004	.halt_check = BRANCH_HALT,
2005	.clkr = {
2006		.enable_reg = 0x28770,
2007		.enable_mask = BIT(0),
2008		.hw.init = &(const struct clk_init_data) {
2009			.name = "nss_cc_ubi32_ahb1_clk",
2010			.parent_data = &(const struct clk_parent_data) {
2011				.hw = &nss_cc_cfg_clk_src.clkr.hw,
2012			},
2013			.num_parents = 1,
2014			.flags = CLK_SET_RATE_PARENT,
2015			.ops = &clk_branch2_ops,
2016		},
2017	},
2018};
2019
2020static struct clk_branch nss_cc_ubi32_ahb2_clk = {
2021	.halt_reg = 0x28778,
2022	.halt_check = BRANCH_HALT,
2023	.clkr = {
2024		.enable_reg = 0x28778,
2025		.enable_mask = BIT(0),
2026		.hw.init = &(const struct clk_init_data) {
2027			.name = "nss_cc_ubi32_ahb2_clk",
2028			.parent_data = &(const struct clk_parent_data) {
2029				.hw = &nss_cc_cfg_clk_src.clkr.hw,
2030			},
2031			.num_parents = 1,
2032			.flags = CLK_SET_RATE_PARENT,
2033			.ops = &clk_branch2_ops,
2034		},
2035	},
2036};
2037
2038static struct clk_branch nss_cc_ubi32_ahb3_clk = {
2039	.halt_reg = 0x28780,
2040	.halt_check = BRANCH_HALT,
2041	.clkr = {
2042		.enable_reg = 0x28780,
2043		.enable_mask = BIT(0),
2044		.hw.init = &(const struct clk_init_data) {
2045			.name = "nss_cc_ubi32_ahb3_clk",
2046			.parent_data = &(const struct clk_parent_data) {
2047				.hw = &nss_cc_cfg_clk_src.clkr.hw,
2048			},
2049			.num_parents = 1,
2050			.flags = CLK_SET_RATE_PARENT,
2051			.ops = &clk_branch2_ops,
2052		},
2053	},
2054};
2055
2056static struct clk_branch nss_cc_ubi32_axi0_clk = {
2057	.halt_reg = 0x28790,
2058	.halt_check = BRANCH_HALT,
2059	.clkr = {
2060		.enable_reg = 0x28790,
2061		.enable_mask = BIT(0),
2062		.hw.init = &(const struct clk_init_data) {
2063			.name = "nss_cc_ubi32_axi0_clk",
2064			.parent_data = &(const struct clk_parent_data) {
2065				.hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
2066			},
2067			.num_parents = 1,
2068			.flags = CLK_SET_RATE_PARENT,
2069			.ops = &clk_branch2_ops,
2070		},
2071	},
2072};
2073
2074static struct clk_branch nss_cc_ubi32_axi1_clk = {
2075	.halt_reg = 0x28794,
2076	.halt_check = BRANCH_HALT,
2077	.clkr = {
2078		.enable_reg = 0x28794,
2079		.enable_mask = BIT(0),
2080		.hw.init = &(const struct clk_init_data) {
2081			.name = "nss_cc_ubi32_axi1_clk",
2082			.parent_data = &(const struct clk_parent_data) {
2083				.hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
2084			},
2085			.num_parents = 1,
2086			.flags = CLK_SET_RATE_PARENT,
2087			.ops = &clk_branch2_ops,
2088		},
2089	},
2090};
2091
2092static struct clk_branch nss_cc_ubi32_axi2_clk = {
2093	.halt_reg = 0x28798,
2094	.halt_check = BRANCH_HALT,
2095	.clkr = {
2096		.enable_reg = 0x28798,
2097		.enable_mask = BIT(0),
2098		.hw.init = &(const struct clk_init_data) {
2099			.name = "nss_cc_ubi32_axi2_clk",
2100			.parent_data = &(const struct clk_parent_data) {
2101				.hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
2102			},
2103			.num_parents = 1,
2104			.flags = CLK_SET_RATE_PARENT,
2105			.ops = &clk_branch2_ops,
2106		},
2107	},
2108};
2109
2110static struct clk_branch nss_cc_ubi32_axi3_clk = {
2111	.halt_reg = 0x2879c,
2112	.halt_check = BRANCH_HALT,
2113	.clkr = {
2114		.enable_reg = 0x2879c,
2115		.enable_mask = BIT(0),
2116		.hw.init = &(const struct clk_init_data) {
2117			.name = "nss_cc_ubi32_axi3_clk",
2118			.parent_data = &(const struct clk_parent_data) {
2119				.hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
2120			},
2121			.num_parents = 1,
2122			.flags = CLK_SET_RATE_PARENT,
2123			.ops = &clk_branch2_ops,
2124		},
2125	},
2126};
2127
2128static struct clk_branch nss_cc_ubi32_core0_clk = {
2129	.halt_reg = 0x28734,
2130	.halt_check = BRANCH_HALT,
2131	.clkr = {
2132		.enable_reg = 0x28734,
2133		.enable_mask = BIT(0),
2134		.hw.init = &(const struct clk_init_data) {
2135			.name = "nss_cc_ubi32_core0_clk",
2136			.parent_data = &(const struct clk_parent_data) {
2137				.hw = &nss_cc_ubi0_div_clk_src.clkr.hw,
2138			},
2139			.num_parents = 1,
2140			.flags = CLK_SET_RATE_PARENT,
2141			.ops = &clk_branch2_ops,
2142		},
2143	},
2144};
2145
2146static struct clk_branch nss_cc_ubi32_core1_clk = {
2147	.halt_reg = 0x28738,
2148	.halt_check = BRANCH_HALT,
2149	.clkr = {
2150		.enable_reg = 0x28738,
2151		.enable_mask = BIT(0),
2152		.hw.init = &(const struct clk_init_data) {
2153			.name = "nss_cc_ubi32_core1_clk",
2154			.parent_data = &(const struct clk_parent_data) {
2155				.hw = &nss_cc_ubi1_div_clk_src.clkr.hw,
2156			},
2157			.num_parents = 1,
2158			.flags = CLK_SET_RATE_PARENT,
2159			.ops = &clk_branch2_ops,
2160		},
2161	},
2162};
2163
2164static struct clk_branch nss_cc_ubi32_core2_clk = {
2165	.halt_reg = 0x2873c,
2166	.halt_check = BRANCH_HALT,
2167	.clkr = {
2168		.enable_reg = 0x2873c,
2169		.enable_mask = BIT(0),
2170		.hw.init = &(const struct clk_init_data) {
2171			.name = "nss_cc_ubi32_core2_clk",
2172			.parent_data = &(const struct clk_parent_data) {
2173				.hw = &nss_cc_ubi2_div_clk_src.clkr.hw,
2174			},
2175			.num_parents = 1,
2176			.flags = CLK_SET_RATE_PARENT,
2177			.ops = &clk_branch2_ops,
2178		},
2179	},
2180};
2181
2182static struct clk_branch nss_cc_ubi32_core3_clk = {
2183	.halt_reg = 0x28740,
2184	.halt_check = BRANCH_HALT,
2185	.clkr = {
2186		.enable_reg = 0x28740,
2187		.enable_mask = BIT(0),
2188		.hw.init = &(const struct clk_init_data) {
2189			.name = "nss_cc_ubi32_core3_clk",
2190			.parent_data = &(const struct clk_parent_data) {
2191				.hw = &nss_cc_ubi3_div_clk_src.clkr.hw,
2192			},
2193			.num_parents = 1,
2194			.flags = CLK_SET_RATE_PARENT,
2195			.ops = &clk_branch2_ops,
2196		},
2197	},
2198};
2199
2200static struct clk_branch nss_cc_ubi32_intr0_ahb_clk = {
2201	.halt_reg = 0x2876c,
2202	.halt_check = BRANCH_HALT,
2203	.clkr = {
2204		.enable_reg = 0x2876c,
2205		.enable_mask = BIT(0),
2206		.hw.init = &(const struct clk_init_data) {
2207			.name = "nss_cc_ubi32_intr0_ahb_clk",
2208			.parent_data = &(const struct clk_parent_data) {
2209				.hw = &nss_cc_int_cfg_clk_src.clkr.hw,
2210			},
2211			.num_parents = 1,
2212			.flags = CLK_SET_RATE_PARENT,
2213			.ops = &clk_branch2_ops,
2214		},
2215	},
2216};
2217
2218static struct clk_branch nss_cc_ubi32_intr1_ahb_clk = {
2219	.halt_reg = 0x28774,
2220	.halt_check = BRANCH_HALT,
2221	.clkr = {
2222		.enable_reg = 0x28774,
2223		.enable_mask = BIT(0),
2224		.hw.init = &(const struct clk_init_data) {
2225			.name = "nss_cc_ubi32_intr1_ahb_clk",
2226			.parent_data = &(const struct clk_parent_data) {
2227				.hw = &nss_cc_int_cfg_clk_src.clkr.hw,
2228			},
2229			.num_parents = 1,
2230			.flags = CLK_SET_RATE_PARENT,
2231			.ops = &clk_branch2_ops,
2232		},
2233	},
2234};
2235
2236static struct clk_branch nss_cc_ubi32_intr2_ahb_clk = {
2237	.halt_reg = 0x2877c,
2238	.halt_check = BRANCH_HALT,
2239	.clkr = {
2240		.enable_reg = 0x2877c,
2241		.enable_mask = BIT(0),
2242		.hw.init = &(const struct clk_init_data) {
2243			.name = "nss_cc_ubi32_intr2_ahb_clk",
2244			.parent_data = &(const struct clk_parent_data) {
2245				.hw = &nss_cc_int_cfg_clk_src.clkr.hw,
2246			},
2247			.num_parents = 1,
2248			.flags = CLK_SET_RATE_PARENT,
2249			.ops = &clk_branch2_ops,
2250		},
2251	},
2252};
2253
2254static struct clk_branch nss_cc_ubi32_intr3_ahb_clk = {
2255	.halt_reg = 0x28784,
2256	.halt_check = BRANCH_HALT,
2257	.clkr = {
2258		.enable_reg = 0x28784,
2259		.enable_mask = BIT(0),
2260		.hw.init = &(const struct clk_init_data) {
2261			.name = "nss_cc_ubi32_intr3_ahb_clk",
2262			.parent_data = &(const struct clk_parent_data) {
2263				.hw = &nss_cc_int_cfg_clk_src.clkr.hw,
2264			},
2265			.num_parents = 1,
2266			.flags = CLK_SET_RATE_PARENT,
2267			.ops = &clk_branch2_ops,
2268		},
2269	},
2270};
2271
2272static struct clk_branch nss_cc_ubi32_nc_axi0_clk = {
2273	.halt_reg = 0x28744,
2274	.halt_check = BRANCH_HALT,
2275	.clkr = {
2276		.enable_reg = 0x28744,
2277		.enable_mask = BIT(0),
2278		.hw.init = &(const struct clk_init_data) {
2279			.name = "nss_cc_ubi32_nc_axi0_clk",
2280			.parent_data = &(const struct clk_parent_data) {
2281				.hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2282			},
2283			.num_parents = 1,
2284			.flags = CLK_SET_RATE_PARENT,
2285			.ops = &clk_branch2_ops,
2286		},
2287	},
2288};
2289
2290static struct clk_branch nss_cc_ubi32_nc_axi1_clk = {
2291	.halt_reg = 0x2874c,
2292	.halt_check = BRANCH_HALT,
2293	.clkr = {
2294		.enable_reg = 0x2874c,
2295		.enable_mask = BIT(0),
2296		.hw.init = &(const struct clk_init_data) {
2297			.name = "nss_cc_ubi32_nc_axi1_clk",
2298			.parent_data = &(const struct clk_parent_data) {
2299				.hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2300			},
2301			.num_parents = 1,
2302			.flags = CLK_SET_RATE_PARENT,
2303			.ops = &clk_branch2_ops,
2304		},
2305	},
2306};
2307
2308static struct clk_branch nss_cc_ubi32_nc_axi2_clk = {
2309	.halt_reg = 0x28754,
2310	.halt_check = BRANCH_HALT,
2311	.clkr = {
2312		.enable_reg = 0x28754,
2313		.enable_mask = BIT(0),
2314		.hw.init = &(const struct clk_init_data) {
2315			.name = "nss_cc_ubi32_nc_axi2_clk",
2316			.parent_data = &(const struct clk_parent_data) {
2317				.hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2318			},
2319			.num_parents = 1,
2320			.flags = CLK_SET_RATE_PARENT,
2321			.ops = &clk_branch2_ops,
2322		},
2323	},
2324};
2325
2326static struct clk_branch nss_cc_ubi32_nc_axi3_clk = {
2327	.halt_reg = 0x2875c,
2328	.halt_check = BRANCH_HALT,
2329	.clkr = {
2330		.enable_reg = 0x2875c,
2331		.enable_mask = BIT(0),
2332		.hw.init = &(const struct clk_init_data) {
2333			.name = "nss_cc_ubi32_nc_axi3_clk",
2334			.parent_data = &(const struct clk_parent_data) {
2335				.hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2336			},
2337			.num_parents = 1,
2338			.flags = CLK_SET_RATE_PARENT,
2339			.ops = &clk_branch2_ops,
2340		},
2341	},
2342};
2343
2344static struct clk_branch nss_cc_ubi32_utcm0_clk = {
2345	.halt_reg = 0x28748,
2346	.halt_check = BRANCH_HALT,
2347	.clkr = {
2348		.enable_reg = 0x28748,
2349		.enable_mask = BIT(0),
2350		.hw.init = &(const struct clk_init_data) {
2351			.name = "nss_cc_ubi32_utcm0_clk",
2352			.parent_data = &(const struct clk_parent_data) {
2353				.hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2354			},
2355			.num_parents = 1,
2356			.flags = CLK_SET_RATE_PARENT,
2357			.ops = &clk_branch2_ops,
2358		},
2359	},
2360};
2361
2362static struct clk_branch nss_cc_ubi32_utcm1_clk = {
2363	.halt_reg = 0x28750,
2364	.halt_check = BRANCH_HALT,
2365	.clkr = {
2366		.enable_reg = 0x28750,
2367		.enable_mask = BIT(0),
2368		.hw.init = &(const struct clk_init_data) {
2369			.name = "nss_cc_ubi32_utcm1_clk",
2370			.parent_data = &(const struct clk_parent_data) {
2371				.hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2372			},
2373			.num_parents = 1,
2374			.flags = CLK_SET_RATE_PARENT,
2375			.ops = &clk_branch2_ops,
2376		},
2377	},
2378};
2379
2380static struct clk_branch nss_cc_ubi32_utcm2_clk = {
2381	.halt_reg = 0x28758,
2382	.halt_check = BRANCH_HALT,
2383	.clkr = {
2384		.enable_reg = 0x28758,
2385		.enable_mask = BIT(0),
2386		.hw.init = &(const struct clk_init_data) {
2387			.name = "nss_cc_ubi32_utcm2_clk",
2388			.parent_data = &(const struct clk_parent_data) {
2389				.hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2390			},
2391			.num_parents = 1,
2392			.flags = CLK_SET_RATE_PARENT,
2393			.ops = &clk_branch2_ops,
2394		},
2395	},
2396};
2397
2398static struct clk_branch nss_cc_ubi32_utcm3_clk = {
2399	.halt_reg = 0x28760,
2400	.halt_check = BRANCH_HALT,
2401	.clkr = {
2402		.enable_reg = 0x28760,
2403		.enable_mask = BIT(0),
2404		.hw.init = &(const struct clk_init_data) {
2405			.name = "nss_cc_ubi32_utcm3_clk",
2406			.parent_data = &(const struct clk_parent_data) {
2407				.hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2408			},
2409			.num_parents = 1,
2410			.flags = CLK_SET_RATE_PARENT,
2411			.ops = &clk_branch2_ops,
2412		},
2413	},
2414};
2415
2416static struct clk_branch nss_cc_uniphy_port1_rx_clk = {
2417	.halt_reg = 0x28904,
2418	.halt_check = BRANCH_HALT,
2419	.clkr = {
2420		.enable_reg = 0x28904,
2421		.enable_mask = BIT(0),
2422		.hw.init = &(const struct clk_init_data) {
2423			.name = "nss_cc_uniphy_port1_rx_clk",
2424			.parent_data = &(const struct clk_parent_data) {
2425				.hw = &nss_cc_port1_rx_div_clk_src.clkr.hw,
2426			},
2427			.num_parents = 1,
2428			.flags = CLK_SET_RATE_PARENT,
2429			.ops = &clk_branch2_ops,
2430		},
2431	},
2432};
2433
2434static struct clk_branch nss_cc_uniphy_port1_tx_clk = {
2435	.halt_reg = 0x28908,
2436	.halt_check = BRANCH_HALT,
2437	.clkr = {
2438		.enable_reg = 0x28908,
2439		.enable_mask = BIT(0),
2440		.hw.init = &(const struct clk_init_data) {
2441			.name = "nss_cc_uniphy_port1_tx_clk",
2442			.parent_data = &(const struct clk_parent_data) {
2443				.hw = &nss_cc_port1_tx_div_clk_src.clkr.hw,
2444			},
2445			.num_parents = 1,
2446			.flags = CLK_SET_RATE_PARENT,
2447			.ops = &clk_branch2_ops,
2448		},
2449	},
2450};
2451
2452static struct clk_branch nss_cc_uniphy_port2_rx_clk = {
2453	.halt_reg = 0x2890c,
2454	.halt_check = BRANCH_HALT,
2455	.clkr = {
2456		.enable_reg = 0x2890c,
2457		.enable_mask = BIT(0),
2458		.hw.init = &(const struct clk_init_data) {
2459			.name = "nss_cc_uniphy_port2_rx_clk",
2460			.parent_data = &(const struct clk_parent_data) {
2461				.hw = &nss_cc_port2_rx_div_clk_src.clkr.hw,
2462			},
2463			.num_parents = 1,
2464			.flags = CLK_SET_RATE_PARENT,
2465			.ops = &clk_branch2_ops,
2466		},
2467	},
2468};
2469
2470static struct clk_branch nss_cc_uniphy_port2_tx_clk = {
2471	.halt_reg = 0x28910,
2472	.halt_check = BRANCH_HALT,
2473	.clkr = {
2474		.enable_reg = 0x28910,
2475		.enable_mask = BIT(0),
2476		.hw.init = &(const struct clk_init_data) {
2477			.name = "nss_cc_uniphy_port2_tx_clk",
2478			.parent_data = &(const struct clk_parent_data) {
2479				.hw = &nss_cc_port2_tx_div_clk_src.clkr.hw,
2480			},
2481			.num_parents = 1,
2482			.flags = CLK_SET_RATE_PARENT,
2483			.ops = &clk_branch2_ops,
2484		},
2485	},
2486};
2487
2488static struct clk_branch nss_cc_uniphy_port3_rx_clk = {
2489	.halt_reg = 0x28914,
2490	.halt_check = BRANCH_HALT,
2491	.clkr = {
2492		.enable_reg = 0x28914,
2493		.enable_mask = BIT(0),
2494		.hw.init = &(const struct clk_init_data) {
2495			.name = "nss_cc_uniphy_port3_rx_clk",
2496			.parent_data = &(const struct clk_parent_data) {
2497				.hw = &nss_cc_port3_rx_div_clk_src.clkr.hw,
2498			},
2499			.num_parents = 1,
2500			.flags = CLK_SET_RATE_PARENT,
2501			.ops = &clk_branch2_ops,
2502		},
2503	},
2504};
2505
2506static struct clk_branch nss_cc_uniphy_port3_tx_clk = {
2507	.halt_reg = 0x28918,
2508	.halt_check = BRANCH_HALT,
2509	.clkr = {
2510		.enable_reg = 0x28918,
2511		.enable_mask = BIT(0),
2512		.hw.init = &(const struct clk_init_data) {
2513			.name = "nss_cc_uniphy_port3_tx_clk",
2514			.parent_data = &(const struct clk_parent_data) {
2515				.hw = &nss_cc_port3_tx_div_clk_src.clkr.hw,
2516			},
2517			.num_parents = 1,
2518			.flags = CLK_SET_RATE_PARENT,
2519			.ops = &clk_branch2_ops,
2520		},
2521	},
2522};
2523
2524static struct clk_branch nss_cc_uniphy_port4_rx_clk = {
2525	.halt_reg = 0x2891c,
2526	.halt_check = BRANCH_HALT,
2527	.clkr = {
2528		.enable_reg = 0x2891c,
2529		.enable_mask = BIT(0),
2530		.hw.init = &(const struct clk_init_data) {
2531			.name = "nss_cc_uniphy_port4_rx_clk",
2532			.parent_data = &(const struct clk_parent_data) {
2533				.hw = &nss_cc_port4_rx_div_clk_src.clkr.hw,
2534			},
2535			.num_parents = 1,
2536			.flags = CLK_SET_RATE_PARENT,
2537			.ops = &clk_branch2_ops,
2538		},
2539	},
2540};
2541
2542static struct clk_branch nss_cc_uniphy_port4_tx_clk = {
2543	.halt_reg = 0x28920,
2544	.halt_check = BRANCH_HALT,
2545	.clkr = {
2546		.enable_reg = 0x28920,
2547		.enable_mask = BIT(0),
2548		.hw.init = &(const struct clk_init_data) {
2549			.name = "nss_cc_uniphy_port4_tx_clk",
2550			.parent_data = &(const struct clk_parent_data) {
2551				.hw = &nss_cc_port4_tx_div_clk_src.clkr.hw,
2552			},
2553			.num_parents = 1,
2554			.flags = CLK_SET_RATE_PARENT,
2555			.ops = &clk_branch2_ops,
2556		},
2557	},
2558};
2559
2560static struct clk_branch nss_cc_uniphy_port5_rx_clk = {
2561	.halt_reg = 0x28924,
2562	.halt_check = BRANCH_HALT,
2563	.clkr = {
2564		.enable_reg = 0x28924,
2565		.enable_mask = BIT(0),
2566		.hw.init = &(const struct clk_init_data) {
2567			.name = "nss_cc_uniphy_port5_rx_clk",
2568			.parent_data = &(const struct clk_parent_data) {
2569				.hw = &nss_cc_port5_rx_div_clk_src.clkr.hw,
2570			},
2571			.num_parents = 1,
2572			.flags = CLK_SET_RATE_PARENT,
2573			.ops = &clk_branch2_ops,
2574		},
2575	},
2576};
2577
2578static struct clk_branch nss_cc_uniphy_port5_tx_clk = {
2579	.halt_reg = 0x28928,
2580	.halt_check = BRANCH_HALT,
2581	.clkr = {
2582		.enable_reg = 0x28928,
2583		.enable_mask = BIT(0),
2584		.hw.init = &(const struct clk_init_data) {
2585			.name = "nss_cc_uniphy_port5_tx_clk",
2586			.parent_data = &(const struct clk_parent_data) {
2587				.hw = &nss_cc_port5_tx_div_clk_src.clkr.hw,
2588			},
2589			.num_parents = 1,
2590			.flags = CLK_SET_RATE_PARENT,
2591			.ops = &clk_branch2_ops,
2592		},
2593	},
2594};
2595
2596static struct clk_branch nss_cc_uniphy_port6_rx_clk = {
2597	.halt_reg = 0x2892c,
2598	.halt_check = BRANCH_HALT,
2599	.clkr = {
2600		.enable_reg = 0x2892c,
2601		.enable_mask = BIT(0),
2602		.hw.init = &(const struct clk_init_data) {
2603			.name = "nss_cc_uniphy_port6_rx_clk",
2604			.parent_data = &(const struct clk_parent_data) {
2605				.hw = &nss_cc_port6_rx_div_clk_src.clkr.hw,
2606			},
2607			.num_parents = 1,
2608			.flags = CLK_SET_RATE_PARENT,
2609			.ops = &clk_branch2_ops,
2610		},
2611	},
2612};
2613
2614static struct clk_branch nss_cc_uniphy_port6_tx_clk = {
2615	.halt_reg = 0x28930,
2616	.halt_check = BRANCH_HALT,
2617	.clkr = {
2618		.enable_reg = 0x28930,
2619		.enable_mask = BIT(0),
2620		.hw.init = &(const struct clk_init_data) {
2621			.name = "nss_cc_uniphy_port6_tx_clk",
2622			.parent_data = &(const struct clk_parent_data) {
2623				.hw = &nss_cc_port6_tx_div_clk_src.clkr.hw,
2624			},
2625			.num_parents = 1,
2626			.flags = CLK_SET_RATE_PARENT,
2627			.ops = &clk_branch2_ops,
2628		},
2629	},
2630};
2631
2632static struct clk_branch nss_cc_xgmac0_ptp_ref_clk = {
2633	.halt_reg = 0x28264,
2634	.halt_check = BRANCH_HALT,
2635	.clkr = {
2636		.enable_reg = 0x28264,
2637		.enable_mask = BIT(0),
2638		.hw.init = &(const struct clk_init_data) {
2639			.name = "nss_cc_xgmac0_ptp_ref_clk",
2640			.parent_data = &(const struct clk_parent_data) {
2641				.hw = &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw,
2642			},
2643			.num_parents = 1,
2644			.flags = CLK_SET_RATE_PARENT,
2645			.ops = &clk_branch2_ops,
2646		},
2647	},
2648};
2649
2650static struct clk_branch nss_cc_xgmac1_ptp_ref_clk = {
2651	.halt_reg = 0x28268,
2652	.halt_check = BRANCH_HALT,
2653	.clkr = {
2654		.enable_reg = 0x28268,
2655		.enable_mask = BIT(0),
2656		.hw.init = &(const struct clk_init_data) {
2657			.name = "nss_cc_xgmac1_ptp_ref_clk",
2658			.parent_data = &(const struct clk_parent_data) {
2659				.hw = &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw,
2660			},
2661			.num_parents = 1,
2662			.flags = CLK_SET_RATE_PARENT,
2663			.ops = &clk_branch2_ops,
2664		},
2665	},
2666};
2667
2668static struct clk_branch nss_cc_xgmac2_ptp_ref_clk = {
2669	.halt_reg = 0x2826c,
2670	.halt_check = BRANCH_HALT,
2671	.clkr = {
2672		.enable_reg = 0x2826c,
2673		.enable_mask = BIT(0),
2674		.hw.init = &(const struct clk_init_data) {
2675			.name = "nss_cc_xgmac2_ptp_ref_clk",
2676			.parent_data = &(const struct clk_parent_data) {
2677				.hw = &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr.hw,
2678			},
2679			.num_parents = 1,
2680			.flags = CLK_SET_RATE_PARENT,
2681			.ops = &clk_branch2_ops,
2682		},
2683	},
2684};
2685
2686static struct clk_branch nss_cc_xgmac3_ptp_ref_clk = {
2687	.halt_reg = 0x28270,
2688	.halt_check = BRANCH_HALT,
2689	.clkr = {
2690		.enable_reg = 0x28270,
2691		.enable_mask = BIT(0),
2692		.hw.init = &(const struct clk_init_data) {
2693			.name = "nss_cc_xgmac3_ptp_ref_clk",
2694			.parent_data = &(const struct clk_parent_data) {
2695				.hw = &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr.hw,
2696			},
2697			.num_parents = 1,
2698			.flags = CLK_SET_RATE_PARENT,
2699			.ops = &clk_branch2_ops,
2700		},
2701	},
2702};
2703
2704static struct clk_branch nss_cc_xgmac4_ptp_ref_clk = {
2705	.halt_reg = 0x28274,
2706	.halt_check = BRANCH_HALT,
2707	.clkr = {
2708		.enable_reg = 0x28274,
2709		.enable_mask = BIT(0),
2710		.hw.init = &(const struct clk_init_data) {
2711			.name = "nss_cc_xgmac4_ptp_ref_clk",
2712			.parent_data = &(const struct clk_parent_data) {
2713				.hw = &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr.hw,
2714			},
2715			.num_parents = 1,
2716			.flags = CLK_SET_RATE_PARENT,
2717			.ops = &clk_branch2_ops,
2718		},
2719	},
2720};
2721
2722static struct clk_branch nss_cc_xgmac5_ptp_ref_clk = {
2723	.halt_reg = 0x28278,
2724	.halt_check = BRANCH_HALT,
2725	.clkr = {
2726		.enable_reg = 0x28278,
2727		.enable_mask = BIT(0),
2728		.hw.init = &(const struct clk_init_data) {
2729			.name = "nss_cc_xgmac5_ptp_ref_clk",
2730			.parent_data = &(const struct clk_parent_data) {
2731				.hw = &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr.hw,
2732			},
2733			.num_parents = 1,
2734			.flags = CLK_SET_RATE_PARENT,
2735			.ops = &clk_branch2_ops,
2736		},
2737	},
2738};
2739
2740static struct clk_regmap *nss_cc_ipq9574_clocks[] = {
2741	[NSS_CC_CE_APB_CLK] = &nss_cc_ce_apb_clk.clkr,
2742	[NSS_CC_CE_AXI_CLK] = &nss_cc_ce_axi_clk.clkr,
2743	[NSS_CC_CE_CLK_SRC] = &nss_cc_ce_clk_src.clkr,
2744	[NSS_CC_CFG_CLK_SRC] = &nss_cc_cfg_clk_src.clkr,
2745	[NSS_CC_CLC_AXI_CLK] = &nss_cc_clc_axi_clk.clkr,
2746	[NSS_CC_CLC_CLK_SRC] = &nss_cc_clc_clk_src.clkr,
2747	[NSS_CC_CRYPTO_CLK] = &nss_cc_crypto_clk.clkr,
2748	[NSS_CC_CRYPTO_CLK_SRC] = &nss_cc_crypto_clk_src.clkr,
2749	[NSS_CC_CRYPTO_PPE_CLK] = &nss_cc_crypto_ppe_clk.clkr,
2750	[NSS_CC_HAQ_AHB_CLK] = &nss_cc_haq_ahb_clk.clkr,
2751	[NSS_CC_HAQ_AXI_CLK] = &nss_cc_haq_axi_clk.clkr,
2752	[NSS_CC_HAQ_CLK_SRC] = &nss_cc_haq_clk_src.clkr,
2753	[NSS_CC_IMEM_AHB_CLK] = &nss_cc_imem_ahb_clk.clkr,
2754	[NSS_CC_IMEM_CLK_SRC] = &nss_cc_imem_clk_src.clkr,
2755	[NSS_CC_IMEM_QSB_CLK] = &nss_cc_imem_qsb_clk.clkr,
2756	[NSS_CC_INT_CFG_CLK_SRC] = &nss_cc_int_cfg_clk_src.clkr,
2757	[NSS_CC_NSS_CSR_CLK] = &nss_cc_nss_csr_clk.clkr,
2758	[NSS_CC_NSSNOC_CE_APB_CLK] = &nss_cc_nssnoc_ce_apb_clk.clkr,
2759	[NSS_CC_NSSNOC_CE_AXI_CLK] = &nss_cc_nssnoc_ce_axi_clk.clkr,
2760	[NSS_CC_NSSNOC_CLC_AXI_CLK] = &nss_cc_nssnoc_clc_axi_clk.clkr,
2761	[NSS_CC_NSSNOC_CRYPTO_CLK] = &nss_cc_nssnoc_crypto_clk.clkr,
2762	[NSS_CC_NSSNOC_HAQ_AHB_CLK] = &nss_cc_nssnoc_haq_ahb_clk.clkr,
2763	[NSS_CC_NSSNOC_HAQ_AXI_CLK] = &nss_cc_nssnoc_haq_axi_clk.clkr,
2764	[NSS_CC_NSSNOC_IMEM_AHB_CLK] = &nss_cc_nssnoc_imem_ahb_clk.clkr,
2765	[NSS_CC_NSSNOC_IMEM_QSB_CLK] = &nss_cc_nssnoc_imem_qsb_clk.clkr,
2766	[NSS_CC_NSSNOC_NSS_CSR_CLK] = &nss_cc_nssnoc_nss_csr_clk.clkr,
2767	[NSS_CC_NSSNOC_PPE_CFG_CLK] = &nss_cc_nssnoc_ppe_cfg_clk.clkr,
2768	[NSS_CC_NSSNOC_PPE_CLK] = &nss_cc_nssnoc_ppe_clk.clkr,
2769	[NSS_CC_NSSNOC_UBI32_AHB0_CLK] = &nss_cc_nssnoc_ubi32_ahb0_clk.clkr,
2770	[NSS_CC_NSSNOC_UBI32_AXI0_CLK] = &nss_cc_nssnoc_ubi32_axi0_clk.clkr,
2771	[NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK] =
2772		&nss_cc_nssnoc_ubi32_int0_ahb_clk.clkr,
2773	[NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK] =
2774		&nss_cc_nssnoc_ubi32_nc_axi0_1_clk.clkr,
2775	[NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK] =
2776		&nss_cc_nssnoc_ubi32_nc_axi0_clk.clkr,
2777	[NSS_CC_PORT1_MAC_CLK] = &nss_cc_port1_mac_clk.clkr,
2778	[NSS_CC_PORT1_RX_CLK] = &nss_cc_port1_rx_clk.clkr,
2779	[NSS_CC_PORT1_RX_CLK_SRC] = &nss_cc_port1_rx_clk_src.clkr,
2780	[NSS_CC_PORT1_RX_DIV_CLK_SRC] = &nss_cc_port1_rx_div_clk_src.clkr,
2781	[NSS_CC_PORT1_TX_CLK] = &nss_cc_port1_tx_clk.clkr,
2782	[NSS_CC_PORT1_TX_CLK_SRC] = &nss_cc_port1_tx_clk_src.clkr,
2783	[NSS_CC_PORT1_TX_DIV_CLK_SRC] = &nss_cc_port1_tx_div_clk_src.clkr,
2784	[NSS_CC_PORT2_MAC_CLK] = &nss_cc_port2_mac_clk.clkr,
2785	[NSS_CC_PORT2_RX_CLK] = &nss_cc_port2_rx_clk.clkr,
2786	[NSS_CC_PORT2_RX_CLK_SRC] = &nss_cc_port2_rx_clk_src.clkr,
2787	[NSS_CC_PORT2_RX_DIV_CLK_SRC] = &nss_cc_port2_rx_div_clk_src.clkr,
2788	[NSS_CC_PORT2_TX_CLK] = &nss_cc_port2_tx_clk.clkr,
2789	[NSS_CC_PORT2_TX_CLK_SRC] = &nss_cc_port2_tx_clk_src.clkr,
2790	[NSS_CC_PORT2_TX_DIV_CLK_SRC] = &nss_cc_port2_tx_div_clk_src.clkr,
2791	[NSS_CC_PORT3_MAC_CLK] = &nss_cc_port3_mac_clk.clkr,
2792	[NSS_CC_PORT3_RX_CLK] = &nss_cc_port3_rx_clk.clkr,
2793	[NSS_CC_PORT3_RX_CLK_SRC] = &nss_cc_port3_rx_clk_src.clkr,
2794	[NSS_CC_PORT3_RX_DIV_CLK_SRC] = &nss_cc_port3_rx_div_clk_src.clkr,
2795	[NSS_CC_PORT3_TX_CLK] = &nss_cc_port3_tx_clk.clkr,
2796	[NSS_CC_PORT3_TX_CLK_SRC] = &nss_cc_port3_tx_clk_src.clkr,
2797	[NSS_CC_PORT3_TX_DIV_CLK_SRC] = &nss_cc_port3_tx_div_clk_src.clkr,
2798	[NSS_CC_PORT4_MAC_CLK] = &nss_cc_port4_mac_clk.clkr,
2799	[NSS_CC_PORT4_RX_CLK] = &nss_cc_port4_rx_clk.clkr,
2800	[NSS_CC_PORT4_RX_CLK_SRC] = &nss_cc_port4_rx_clk_src.clkr,
2801	[NSS_CC_PORT4_RX_DIV_CLK_SRC] = &nss_cc_port4_rx_div_clk_src.clkr,
2802	[NSS_CC_PORT4_TX_CLK] = &nss_cc_port4_tx_clk.clkr,
2803	[NSS_CC_PORT4_TX_CLK_SRC] = &nss_cc_port4_tx_clk_src.clkr,
2804	[NSS_CC_PORT4_TX_DIV_CLK_SRC] = &nss_cc_port4_tx_div_clk_src.clkr,
2805	[NSS_CC_PORT5_MAC_CLK] = &nss_cc_port5_mac_clk.clkr,
2806	[NSS_CC_PORT5_RX_CLK] = &nss_cc_port5_rx_clk.clkr,
2807	[NSS_CC_PORT5_RX_CLK_SRC] = &nss_cc_port5_rx_clk_src.clkr,
2808	[NSS_CC_PORT5_RX_DIV_CLK_SRC] = &nss_cc_port5_rx_div_clk_src.clkr,
2809	[NSS_CC_PORT5_TX_CLK] = &nss_cc_port5_tx_clk.clkr,
2810	[NSS_CC_PORT5_TX_CLK_SRC] = &nss_cc_port5_tx_clk_src.clkr,
2811	[NSS_CC_PORT5_TX_DIV_CLK_SRC] = &nss_cc_port5_tx_div_clk_src.clkr,
2812	[NSS_CC_PORT6_MAC_CLK] = &nss_cc_port6_mac_clk.clkr,
2813	[NSS_CC_PORT6_RX_CLK] = &nss_cc_port6_rx_clk.clkr,
2814	[NSS_CC_PORT6_RX_CLK_SRC] = &nss_cc_port6_rx_clk_src.clkr,
2815	[NSS_CC_PORT6_RX_DIV_CLK_SRC] = &nss_cc_port6_rx_div_clk_src.clkr,
2816	[NSS_CC_PORT6_TX_CLK] = &nss_cc_port6_tx_clk.clkr,
2817	[NSS_CC_PORT6_TX_CLK_SRC] = &nss_cc_port6_tx_clk_src.clkr,
2818	[NSS_CC_PORT6_TX_DIV_CLK_SRC] = &nss_cc_port6_tx_div_clk_src.clkr,
2819	[NSS_CC_PPE_CLK_SRC] = &nss_cc_ppe_clk_src.clkr,
2820	[NSS_CC_PPE_EDMA_CFG_CLK] = &nss_cc_ppe_edma_cfg_clk.clkr,
2821	[NSS_CC_PPE_EDMA_CLK] = &nss_cc_ppe_edma_clk.clkr,
2822	[NSS_CC_PPE_SWITCH_BTQ_CLK] = &nss_cc_ppe_switch_btq_clk.clkr,
2823	[NSS_CC_PPE_SWITCH_CFG_CLK] = &nss_cc_ppe_switch_cfg_clk.clkr,
2824	[NSS_CC_PPE_SWITCH_CLK] = &nss_cc_ppe_switch_clk.clkr,
2825	[NSS_CC_PPE_SWITCH_IPE_CLK] = &nss_cc_ppe_switch_ipe_clk.clkr,
2826	[NSS_CC_UBI0_CLK_SRC] = &nss_cc_ubi0_clk_src.clkr,
2827	[NSS_CC_UBI0_DIV_CLK_SRC] = &nss_cc_ubi0_div_clk_src.clkr,
2828	[NSS_CC_UBI1_CLK_SRC] = &nss_cc_ubi1_clk_src.clkr,
2829	[NSS_CC_UBI1_DIV_CLK_SRC] = &nss_cc_ubi1_div_clk_src.clkr,
2830	[NSS_CC_UBI2_CLK_SRC] = &nss_cc_ubi2_clk_src.clkr,
2831	[NSS_CC_UBI2_DIV_CLK_SRC] = &nss_cc_ubi2_div_clk_src.clkr,
2832	[NSS_CC_UBI32_AHB0_CLK] = &nss_cc_ubi32_ahb0_clk.clkr,
2833	[NSS_CC_UBI32_AHB1_CLK] = &nss_cc_ubi32_ahb1_clk.clkr,
2834	[NSS_CC_UBI32_AHB2_CLK] = &nss_cc_ubi32_ahb2_clk.clkr,
2835	[NSS_CC_UBI32_AHB3_CLK] = &nss_cc_ubi32_ahb3_clk.clkr,
2836	[NSS_CC_UBI32_AXI0_CLK] = &nss_cc_ubi32_axi0_clk.clkr,
2837	[NSS_CC_UBI32_AXI1_CLK] = &nss_cc_ubi32_axi1_clk.clkr,
2838	[NSS_CC_UBI32_AXI2_CLK] = &nss_cc_ubi32_axi2_clk.clkr,
2839	[NSS_CC_UBI32_AXI3_CLK] = &nss_cc_ubi32_axi3_clk.clkr,
2840	[NSS_CC_UBI32_CORE0_CLK] = &nss_cc_ubi32_core0_clk.clkr,
2841	[NSS_CC_UBI32_CORE1_CLK] = &nss_cc_ubi32_core1_clk.clkr,
2842	[NSS_CC_UBI32_CORE2_CLK] = &nss_cc_ubi32_core2_clk.clkr,
2843	[NSS_CC_UBI32_CORE3_CLK] = &nss_cc_ubi32_core3_clk.clkr,
2844	[NSS_CC_UBI32_INTR0_AHB_CLK] = &nss_cc_ubi32_intr0_ahb_clk.clkr,
2845	[NSS_CC_UBI32_INTR1_AHB_CLK] = &nss_cc_ubi32_intr1_ahb_clk.clkr,
2846	[NSS_CC_UBI32_INTR2_AHB_CLK] = &nss_cc_ubi32_intr2_ahb_clk.clkr,
2847	[NSS_CC_UBI32_INTR3_AHB_CLK] = &nss_cc_ubi32_intr3_ahb_clk.clkr,
2848	[NSS_CC_UBI32_NC_AXI0_CLK] = &nss_cc_ubi32_nc_axi0_clk.clkr,
2849	[NSS_CC_UBI32_NC_AXI1_CLK] = &nss_cc_ubi32_nc_axi1_clk.clkr,
2850	[NSS_CC_UBI32_NC_AXI2_CLK] = &nss_cc_ubi32_nc_axi2_clk.clkr,
2851	[NSS_CC_UBI32_NC_AXI3_CLK] = &nss_cc_ubi32_nc_axi3_clk.clkr,
2852	[NSS_CC_UBI32_UTCM0_CLK] = &nss_cc_ubi32_utcm0_clk.clkr,
2853	[NSS_CC_UBI32_UTCM1_CLK] = &nss_cc_ubi32_utcm1_clk.clkr,
2854	[NSS_CC_UBI32_UTCM2_CLK] = &nss_cc_ubi32_utcm2_clk.clkr,
2855	[NSS_CC_UBI32_UTCM3_CLK] = &nss_cc_ubi32_utcm3_clk.clkr,
2856	[NSS_CC_UBI3_CLK_SRC] = &nss_cc_ubi3_clk_src.clkr,
2857	[NSS_CC_UBI3_DIV_CLK_SRC] = &nss_cc_ubi3_div_clk_src.clkr,
2858	[NSS_CC_UBI_AXI_CLK_SRC] = &nss_cc_ubi_axi_clk_src.clkr,
2859	[NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC] =
2860		&nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr,
2861	[NSS_CC_UNIPHY_PORT1_RX_CLK] = &nss_cc_uniphy_port1_rx_clk.clkr,
2862	[NSS_CC_UNIPHY_PORT1_TX_CLK] = &nss_cc_uniphy_port1_tx_clk.clkr,
2863	[NSS_CC_UNIPHY_PORT2_RX_CLK] = &nss_cc_uniphy_port2_rx_clk.clkr,
2864	[NSS_CC_UNIPHY_PORT2_TX_CLK] = &nss_cc_uniphy_port2_tx_clk.clkr,
2865	[NSS_CC_UNIPHY_PORT3_RX_CLK] = &nss_cc_uniphy_port3_rx_clk.clkr,
2866	[NSS_CC_UNIPHY_PORT3_TX_CLK] = &nss_cc_uniphy_port3_tx_clk.clkr,
2867	[NSS_CC_UNIPHY_PORT4_RX_CLK] = &nss_cc_uniphy_port4_rx_clk.clkr,
2868	[NSS_CC_UNIPHY_PORT4_TX_CLK] = &nss_cc_uniphy_port4_tx_clk.clkr,
2869	[NSS_CC_UNIPHY_PORT5_RX_CLK] = &nss_cc_uniphy_port5_rx_clk.clkr,
2870	[NSS_CC_UNIPHY_PORT5_TX_CLK] = &nss_cc_uniphy_port5_tx_clk.clkr,
2871	[NSS_CC_UNIPHY_PORT6_RX_CLK] = &nss_cc_uniphy_port6_rx_clk.clkr,
2872	[NSS_CC_UNIPHY_PORT6_TX_CLK] = &nss_cc_uniphy_port6_tx_clk.clkr,
2873	[NSS_CC_XGMAC0_PTP_REF_CLK] = &nss_cc_xgmac0_ptp_ref_clk.clkr,
2874	[NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] =
2875		&nss_cc_xgmac0_ptp_ref_div_clk_src.clkr,
2876	[NSS_CC_XGMAC1_PTP_REF_CLK] = &nss_cc_xgmac1_ptp_ref_clk.clkr,
2877	[NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] =
2878		&nss_cc_xgmac1_ptp_ref_div_clk_src.clkr,
2879	[NSS_CC_XGMAC2_PTP_REF_CLK] = &nss_cc_xgmac2_ptp_ref_clk.clkr,
2880	[NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC] =
2881		&nss_cc_xgmac2_ptp_ref_div_clk_src.clkr,
2882	[NSS_CC_XGMAC3_PTP_REF_CLK] = &nss_cc_xgmac3_ptp_ref_clk.clkr,
2883	[NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC] =
2884		&nss_cc_xgmac3_ptp_ref_div_clk_src.clkr,
2885	[NSS_CC_XGMAC4_PTP_REF_CLK] = &nss_cc_xgmac4_ptp_ref_clk.clkr,
2886	[NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC] =
2887		&nss_cc_xgmac4_ptp_ref_div_clk_src.clkr,
2888	[NSS_CC_XGMAC5_PTP_REF_CLK] = &nss_cc_xgmac5_ptp_ref_clk.clkr,
2889	[NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC] =
2890		&nss_cc_xgmac5_ptp_ref_div_clk_src.clkr,
2891	[UBI32_PLL] = &ubi32_pll.clkr,
2892	[UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
2893};
2894
2895static const struct qcom_reset_map nss_cc_ipq9574_resets[] = {
2896	[NSS_CC_CE_BCR] = { 0x28400, 0 },
2897	[NSS_CC_CLC_BCR] = { 0x28600, 0 },
2898	[NSS_CC_EIP197_BCR] = { 0x16004, 0 },
2899	[NSS_CC_HAQ_BCR] = { 0x28300, 0 },
2900	[NSS_CC_IMEM_BCR] = { 0xe004, 0 },
2901	[NSS_CC_MAC_BCR] = { 0x28100, 0 },
2902	[NSS_CC_PPE_BCR] = { 0x28200, 0 },
2903	[NSS_CC_UBI_BCR] = { 0x28700, 0 },
2904	[NSS_CC_UNIPHY_BCR] = { 0x28900, 0 },
2905	[UBI3_CLKRST_CLAMP_ENABLE] = { 0x28a04, 9 },
2906	[UBI3_CORE_CLAMP_ENABLE] = { 0x28a04, 8 },
2907	[UBI2_CLKRST_CLAMP_ENABLE] = { 0x28a04, 7 },
2908	[UBI2_CORE_CLAMP_ENABLE] = { 0x28a04, 6 },
2909	[UBI1_CLKRST_CLAMP_ENABLE] = { 0x28a04, 5 },
2910	[UBI1_CORE_CLAMP_ENABLE] = { 0x28a04, 4 },
2911	[UBI0_CLKRST_CLAMP_ENABLE] = { 0x28a04, 3 },
2912	[UBI0_CORE_CLAMP_ENABLE] = { 0x28a04, 2 },
2913	[NSSNOC_NSS_CSR_ARES] = { 0x28a04, 1 },
2914	[NSS_CSR_ARES] = { 0x28a04, 0 },
2915	[PPE_BTQ_ARES] = { 0x28a08, 20 },
2916	[PPE_IPE_ARES] = { 0x28a08, 19 },
2917	[PPE_ARES] = { 0x28a08, 18 },
2918	[PPE_CFG_ARES] = { 0x28a08, 17 },
2919	[PPE_EDMA_ARES] = { 0x28a08, 16 },
2920	[PPE_EDMA_CFG_ARES] = { 0x28a08, 15 },
2921	[CRY_PPE_ARES] = { 0x28a08, 14 },
2922	[NSSNOC_PPE_ARES] = { 0x28a08, 13 },
2923	[NSSNOC_PPE_CFG_ARES] = { 0x28a08, 12 },
2924	[PORT1_MAC_ARES] = { 0x28a08, 11 },
2925	[PORT2_MAC_ARES] = { 0x28a08, 10 },
2926	[PORT3_MAC_ARES] = { 0x28a08, 9 },
2927	[PORT4_MAC_ARES] = { 0x28a08, 8 },
2928	[PORT5_MAC_ARES] = { 0x28a08, 7 },
2929	[PORT6_MAC_ARES] = { 0x28a08, 6 },
2930	[XGMAC0_PTP_REF_ARES] = { 0x28a08, 5 },
2931	[XGMAC1_PTP_REF_ARES] = { 0x28a08, 4 },
2932	[XGMAC2_PTP_REF_ARES] = { 0x28a08, 3 },
2933	[XGMAC3_PTP_REF_ARES] = { 0x28a08, 2 },
2934	[XGMAC4_PTP_REF_ARES] = { 0x28a08, 1 },
2935	[XGMAC5_PTP_REF_ARES] = { 0x28a08, 0 },
2936	[HAQ_AHB_ARES] = { 0x28a0c, 3 },
2937	[HAQ_AXI_ARES] = { 0x28a0c, 2 },
2938	[NSSNOC_HAQ_AHB_ARES] = { 0x28a0c, 1 },
2939	[NSSNOC_HAQ_AXI_ARES] = { 0x28a0c, 0 },
2940	[CE_APB_ARES] = { 0x28a10, 3 },
2941	[CE_AXI_ARES] = { 0x28a10, 2 },
2942	[NSSNOC_CE_APB_ARES] = { 0x28a10, 1 },
2943	[NSSNOC_CE_AXI_ARES] = { 0x28a10, 0 },
2944	[CRYPTO_ARES] = { 0x28a14, 1 },
2945	[NSSNOC_CRYPTO_ARES] = { 0x28a14, 0 },
2946	[NSSNOC_NC_AXI0_1_ARES] = { 0x28a1c, 28 },
2947	[UBI0_CORE_ARES] = { 0x28a1c, 27 },
2948	[UBI1_CORE_ARES] = { 0x28a1c, 26 },
2949	[UBI2_CORE_ARES] = { 0x28a1c, 25 },
2950	[UBI3_CORE_ARES] = { 0x28a1c, 24 },
2951	[NC_AXI0_ARES] = { 0x28a1c, 23 },
2952	[UTCM0_ARES] = { 0x28a1c, 22 },
2953	[NC_AXI1_ARES] = { 0x28a1c, 21 },
2954	[UTCM1_ARES] = { 0x28a1c, 20 },
2955	[NC_AXI2_ARES] = { 0x28a1c, 19 },
2956	[UTCM2_ARES] = { 0x28a1c, 18 },
2957	[NC_AXI3_ARES] = { 0x28a1c, 17 },
2958	[UTCM3_ARES] = { 0x28a1c, 16 },
2959	[NSSNOC_NC_AXI0_ARES] = { 0x28a1c, 15 },
2960	[AHB0_ARES] = { 0x28a1c, 14 },
2961	[INTR0_AHB_ARES] = { 0x28a1c, 13 },
2962	[AHB1_ARES] = { 0x28a1c, 12 },
2963	[INTR1_AHB_ARES] = { 0x28a1c, 11 },
2964	[AHB2_ARES] = { 0x28a1c, 10 },
2965	[INTR2_AHB_ARES] = { 0x28a1c, 9 },
2966	[AHB3_ARES] = { 0x28a1c, 8 },
2967	[INTR3_AHB_ARES] = { 0x28a1c, 7 },
2968	[NSSNOC_AHB0_ARES] = { 0x28a1c, 6 },
2969	[NSSNOC_INT0_AHB_ARES] = { 0x28a1c, 5 },
2970	[AXI0_ARES] = { 0x28a1c, 4 },
2971	[AXI1_ARES] = { 0x28a1c, 3 },
2972	[AXI2_ARES] = { 0x28a1c, 2 },
2973	[AXI3_ARES] = { 0x28a1c, 1 },
2974	[NSSNOC_AXI0_ARES] = { 0x28a1c, 0 },
2975	[IMEM_QSB_ARES] = { 0x28a20, 3 },
2976	[NSSNOC_IMEM_QSB_ARES] = { 0x28a20, 2 },
2977	[IMEM_AHB_ARES] = { 0x28a20, 1 },
2978	[NSSNOC_IMEM_AHB_ARES] = { 0x28a20, 0 },
2979	[UNIPHY_PORT1_RX_ARES] = { 0x28a24, 23 },
2980	[UNIPHY_PORT1_TX_ARES] = { 0x28a24, 22 },
2981	[UNIPHY_PORT2_RX_ARES] = { 0x28a24, 21 },
2982	[UNIPHY_PORT2_TX_ARES] = { 0x28a24, 20 },
2983	[UNIPHY_PORT3_RX_ARES] = { 0x28a24, 19 },
2984	[UNIPHY_PORT3_TX_ARES] = { 0x28a24, 18 },
2985	[UNIPHY_PORT4_RX_ARES] = { 0x28a24, 17 },
2986	[UNIPHY_PORT4_TX_ARES] = { 0x28a24, 16 },
2987	[UNIPHY_PORT5_RX_ARES] = { 0x28a24, 15 },
2988	[UNIPHY_PORT5_TX_ARES] = { 0x28a24, 14 },
2989	[UNIPHY_PORT6_RX_ARES] = { 0x28a24, 13 },
2990	[UNIPHY_PORT6_TX_ARES] = { 0x28a24, 12 },
2991	[PORT1_RX_ARES] = { 0x28a24, 11 },
2992	[PORT1_TX_ARES] = { 0x28a24, 10 },
2993	[PORT2_RX_ARES] = { 0x28a24, 9 },
2994	[PORT2_TX_ARES] = { 0x28a24, 8 },
2995	[PORT3_RX_ARES] = { 0x28a24, 7 },
2996	[PORT3_TX_ARES] = { 0x28a24, 6 },
2997	[PORT4_RX_ARES] = { 0x28a24, 5 },
2998	[PORT4_TX_ARES] = { 0x28a24, 4 },
2999	[PORT5_RX_ARES] = { 0x28a24, 3 },
3000	[PORT5_TX_ARES] = { 0x28a24, 2 },
3001	[PORT6_RX_ARES] = { 0x28a24, 1 },
3002	[PORT6_TX_ARES] = { 0x28a24, 0 },
3003	[PPE_FULL_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(20, 17) },
3004	[UNIPHY0_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(23, 14) },
3005	[UNIPHY1_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(15, 14) },
3006	[UNIPHY2_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(13, 12) },
3007	[UNIPHY_PORT1_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(23, 22) },
3008	[UNIPHY_PORT2_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(21, 20) },
3009	[UNIPHY_PORT3_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(19, 18) },
3010	[UNIPHY_PORT4_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(17, 16) },
3011	[UNIPHY_PORT5_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(15, 14) },
3012	[UNIPHY_PORT6_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(13, 12) },
3013	[NSSPORT1_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(11, 10) },
3014	[NSSPORT2_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(9, 8) },
3015	[NSSPORT3_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(7, 6) },
3016	[NSSPORT4_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(5, 4) },
3017	[NSSPORT5_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(3, 2) },
3018	[NSSPORT6_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(1, 0) },
3019	[EDMA_HW_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(16, 15) },
3020};
3021
3022static const struct regmap_config nss_cc_ipq9574_regmap_config = {
3023	.reg_bits = 32,
3024	.reg_stride = 4,
3025	.val_bits = 32,
3026	.max_register = 0x28a34,
3027	.fast_io = true,
3028};
3029
3030static struct qcom_icc_hws_data icc_ipq9574_nss_hws[] = {
3031	{ MASTER_NSSNOC_PPE, SLAVE_NSSNOC_PPE, NSS_CC_NSSNOC_PPE_CLK },
3032	{ MASTER_NSSNOC_PPE_CFG, SLAVE_NSSNOC_PPE_CFG, NSS_CC_NSSNOC_PPE_CFG_CLK },
3033	{ MASTER_NSSNOC_NSS_CSR, SLAVE_NSSNOC_NSS_CSR, NSS_CC_NSSNOC_NSS_CSR_CLK },
3034	{ MASTER_NSSNOC_IMEM_QSB, SLAVE_NSSNOC_IMEM_QSB, NSS_CC_NSSNOC_IMEM_QSB_CLK },
3035	{ MASTER_NSSNOC_IMEM_AHB, SLAVE_NSSNOC_IMEM_AHB, NSS_CC_NSSNOC_IMEM_AHB_CLK },
3036};
3037
3038#define IPQ_NSSCC_ID	(9574 * 2) /* some unique value */
3039
3040static const struct qcom_cc_desc nss_cc_ipq9574_desc = {
3041	.config = &nss_cc_ipq9574_regmap_config,
3042	.clks = nss_cc_ipq9574_clocks,
3043	.num_clks = ARRAY_SIZE(nss_cc_ipq9574_clocks),
3044	.resets = nss_cc_ipq9574_resets,
3045	.num_resets = ARRAY_SIZE(nss_cc_ipq9574_resets),
3046	.icc_hws = icc_ipq9574_nss_hws,
3047	.num_icc_hws = ARRAY_SIZE(icc_ipq9574_nss_hws),
3048	.icc_first_node_id = IPQ_NSSCC_ID,
3049};
3050
3051static const struct dev_pm_ops nss_cc_ipq9574_pm_ops = {
3052	SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
3053};
3054
3055static const struct of_device_id nss_cc_ipq9574_match_table[] = {
3056	{ .compatible = "qcom,ipq9574-nsscc" },
3057	{ }
3058};
3059MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
3060
3061static int nss_cc_ipq9574_probe(struct platform_device *pdev)
3062{
3063	struct regmap *regmap;
3064	int ret;
3065
3066	ret = devm_pm_runtime_enable(&pdev->dev);
3067	if (ret)
3068		return dev_err_probe(&pdev->dev, ret, "Fail to enable runtime PM\n");
3069
3070	ret = devm_pm_clk_create(&pdev->dev);
3071	if (ret)
3072		return dev_err_probe(&pdev->dev, ret, "Fail to create PM clock\n");
3073
3074	ret = pm_clk_add(&pdev->dev, "bus");
3075	if (ret)
3076		return dev_err_probe(&pdev->dev, ret, "Fail to add bus clock\n");
3077
3078	ret = pm_runtime_resume_and_get(&pdev->dev);
3079	if (ret)
3080		return dev_err_probe(&pdev->dev, ret, "Fail to resume\n");
3081
3082	regmap = qcom_cc_map(pdev, &nss_cc_ipq9574_desc);
3083	if (IS_ERR(regmap)) {
3084		pm_runtime_put(&pdev->dev);
3085		return dev_err_probe(&pdev->dev, PTR_ERR(regmap),
3086				     "Fail to map clock controller registers\n");
3087	}
3088
3089	clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
3090
3091	ret = qcom_cc_really_probe(&pdev->dev, &nss_cc_ipq9574_desc, regmap);
3092	pm_runtime_put(&pdev->dev);
3093
3094	return ret;
3095}
3096
3097static struct platform_driver nss_cc_ipq9574_driver = {
3098	.probe = nss_cc_ipq9574_probe,
3099	.driver = {
3100		.name = "qcom,nsscc-ipq9574",
3101		.of_match_table = nss_cc_ipq9574_match_table,
3102		.pm = &nss_cc_ipq9574_pm_ops,
3103		.sync_state = icc_sync_state,
3104	},
3105};
3106
3107module_platform_driver(nss_cc_ipq9574_driver);
3108
3109MODULE_DESCRIPTION("Qualcomm Technologies, Inc. NSSCC IPQ9574 Driver");
3110MODULE_LICENSE("GPL");