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mmcc-sdm660.c
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linux-6.19.14/drivers/clk/qcom/mmcc-sdm660.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020, Martin Botka <martin.botka@somainline.org> 5 * Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org> 6 */ 7 8#include <linux/kernel.h> 9#include <linux/bitops.h> 10#include <linux/err.h> 11#include <linux/platform_device.h> 12#include <linux/mod_devicetable.h> 13#include <linux/module.h> 14#include <linux/clk-provider.h> 15#include <linux/regmap.h> 16 17#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 18 19#include "common.h" 20#include "clk-regmap.h" 21#include "clk-regmap-divider.h" 22#include "clk-alpha-pll.h" 23#include "clk-rcg.h" 24#include "clk-branch.h" 25#include "reset.h" 26#include "gdsc.h" 27 28enum { 29 P_XO, 30 P_DSI0PLL_BYTE, 31 P_DSI0PLL, 32 P_DSI1PLL_BYTE, 33 P_DSI1PLL, 34 P_GPLL0, 35 P_GPLL0_DIV, 36 P_MMPLL0, 37 P_MMPLL10, 38 P_MMPLL3, 39 P_MMPLL4, 40 P_MMPLL5, 41 P_MMPLL6, 42 P_MMPLL7, 43 P_MMPLL8, 44 P_SLEEP_CLK, 45 P_DP_PHY_PLL_LINK_CLK, 46 P_DP_PHY_PLL_VCO_DIV, 47}; 48 49static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map[] = { 50 { P_XO, 0 }, 51 { P_MMPLL0, 1 }, 52 { P_MMPLL4, 2 }, 53 { P_MMPLL7, 3 }, 54 { P_MMPLL8, 4 }, 55 { P_GPLL0, 5 }, 56 { P_GPLL0_DIV, 6 }, 57}; 58 59/* Voteable PLL */ 60static struct clk_alpha_pll mmpll0 = { 61 .offset = 0xc000, 62 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 63 .clkr = { 64 .enable_reg = 0x1f0, 65 .enable_mask = BIT(0), 66 .hw.init = &(struct clk_init_data){ 67 .name = "mmpll0", 68 .parent_data = &(const struct clk_parent_data){ 69 .fw_name = "xo", 70 }, 71 .num_parents = 1, 72 .ops = &clk_alpha_pll_ops, 73 }, 74 }, 75}; 76 77static struct clk_alpha_pll mmpll6 = { 78 .offset = 0xf0, 79 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 80 .clkr = { 81 .enable_reg = 0x1f0, 82 .enable_mask = BIT(2), 83 .hw.init = &(struct clk_init_data){ 84 .name = "mmpll6", 85 .parent_data = &(const struct clk_parent_data){ 86 .fw_name = "xo", 87 }, 88 .num_parents = 1, 89 .ops = &clk_alpha_pll_ops, 90 }, 91 }, 92}; 93 94/* APSS controlled PLLs */ 95static const struct pll_vco vco[] = { 96 { 1000000000, 2000000000, 0 }, 97 { 750000000, 1500000000, 1 }, 98 { 500000000, 1000000000, 2 }, 99 { 250000000, 500000000, 3 }, 100}; 101 102static const struct pll_vco mmpll3_vco[] = { 103 { 750000000, 1500000000, 1 }, 104}; 105 106static const struct alpha_pll_config mmpll10_config = { 107 .l = 0x1e, 108 .config_ctl_val = 0x00004289, 109 .main_output_mask = 0x1, 110}; 111 112static struct clk_alpha_pll mmpll10 = { 113 .offset = 0x190, 114 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 115 .clkr = { 116 .hw.init = &(struct clk_init_data){ 117 .name = "mmpll10", 118 .parent_data = &(const struct clk_parent_data){ 119 .fw_name = "xo", 120 }, 121 .num_parents = 1, 122 .ops = &clk_alpha_pll_ops, 123 }, 124 }, 125}; 126 127static const struct alpha_pll_config mmpll3_config = { 128 .l = 0x2e, 129 .config_ctl_val = 0x4001055b, 130 .vco_val = 0x1 << 20, 131 .vco_mask = 0x3 << 20, 132 .main_output_mask = 0x1, 133}; 134 135static struct clk_alpha_pll mmpll3 = { 136 .offset = 0x0, 137 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 138 .vco_table = mmpll3_vco, 139 .num_vco = ARRAY_SIZE(mmpll3_vco), 140 .clkr = { 141 .hw.init = &(struct clk_init_data){ 142 .name = "mmpll3", 143 .parent_data = &(const struct clk_parent_data){ 144 .fw_name = "xo", 145 }, 146 .num_parents = 1, 147 .ops = &clk_alpha_pll_ops, 148 }, 149 }, 150}; 151 152static const struct alpha_pll_config mmpll4_config = { 153 .l = 0x28, 154 .config_ctl_val = 0x4001055b, 155 .vco_val = 0x2 << 20, 156 .vco_mask = 0x3 << 20, 157 .main_output_mask = 0x1, 158}; 159 160static struct clk_alpha_pll mmpll4 = { 161 .offset = 0x50, 162 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 163 .vco_table = vco, 164 .num_vco = ARRAY_SIZE(vco), 165 .clkr = { 166 .hw.init = &(struct clk_init_data){ 167 .name = "mmpll4", 168 .parent_data = &(const struct clk_parent_data){ 169 .fw_name = "xo", 170 }, 171 .num_parents = 1, 172 .ops = &clk_alpha_pll_ops, 173 }, 174 }, 175}; 176 177static const struct alpha_pll_config mmpll5_config = { 178 .l = 0x2a, 179 .config_ctl_val = 0x4001055b, 180 .alpha_hi = 0xf8, 181 .alpha_en_mask = BIT(24), 182 .vco_val = 0x2 << 20, 183 .vco_mask = 0x3 << 20, 184 .main_output_mask = 0x1, 185}; 186 187static struct clk_alpha_pll mmpll5 = { 188 .offset = 0xa0, 189 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 190 .vco_table = vco, 191 .num_vco = ARRAY_SIZE(vco), 192 .clkr = { 193 .hw.init = &(struct clk_init_data){ 194 .name = "mmpll5", 195 .parent_data = &(const struct clk_parent_data){ 196 .fw_name = "xo", 197 }, 198 .num_parents = 1, 199 .ops = &clk_alpha_pll_ops, 200 }, 201 }, 202}; 203 204static const struct alpha_pll_config mmpll7_config = { 205 .l = 0x32, 206 .config_ctl_val = 0x4001055b, 207 .vco_val = 0x2 << 20, 208 .vco_mask = 0x3 << 20, 209 .main_output_mask = 0x1, 210}; 211 212static struct clk_alpha_pll mmpll7 = { 213 .offset = 0x140, 214 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 215 .vco_table = vco, 216 .num_vco = ARRAY_SIZE(vco), 217 .clkr = { 218 .hw.init = &(struct clk_init_data){ 219 .name = "mmpll7", 220 .parent_data = &(const struct clk_parent_data){ 221 .fw_name = "xo", 222 }, 223 .num_parents = 1, 224 .ops = &clk_alpha_pll_ops, 225 }, 226 }, 227}; 228 229static const struct alpha_pll_config mmpll8_config = { 230 .l = 0x30, 231 .alpha_hi = 0x70, 232 .alpha_en_mask = BIT(24), 233 .config_ctl_val = 0x4001055b, 234 .vco_val = 0x2 << 20, 235 .vco_mask = 0x3 << 20, 236 .main_output_mask = 0x1, 237}; 238 239static struct clk_alpha_pll mmpll8 = { 240 .offset = 0x1c0, 241 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 242 .vco_table = vco, 243 .num_vco = ARRAY_SIZE(vco), 244 .clkr = { 245 .hw.init = &(struct clk_init_data){ 246 .name = "mmpll8", 247 .parent_data = &(const struct clk_parent_data){ 248 .fw_name = "xo", 249 }, 250 .num_parents = 1, 251 .ops = &clk_alpha_pll_ops, 252 }, 253 }, 254}; 255 256static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div[] = { 257 { .fw_name = "xo" }, 258 { .hw = &mmpll0.clkr.hw }, 259 { .hw = &mmpll4.clkr.hw }, 260 { .hw = &mmpll7.clkr.hw }, 261 { .hw = &mmpll8.clkr.hw }, 262 { .fw_name = "gpll0" }, 263 { .fw_name = "gpll0_div" }, 264}; 265 266static const struct parent_map mmcc_xo_dsibyte_map[] = { 267 { P_XO, 0 }, 268 { P_DSI0PLL_BYTE, 1 }, 269 { P_DSI1PLL_BYTE, 2 }, 270}; 271 272static const struct clk_parent_data mmcc_xo_dsibyte[] = { 273 { .fw_name = "xo" }, 274 { .fw_name = "dsi0pllbyte" }, 275 { .fw_name = "dsi1pllbyte" }, 276}; 277 278static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = { 279 { P_XO, 0 }, 280 { P_MMPLL0, 1 }, 281 { P_MMPLL4, 2 }, 282 { P_MMPLL7, 3 }, 283 { P_MMPLL10, 4 }, 284 { P_GPLL0, 5 }, 285 { P_GPLL0_DIV, 6 }, 286}; 287 288static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = { 289 { .fw_name = "xo" }, 290 { .hw = &mmpll0.clkr.hw }, 291 { .hw = &mmpll4.clkr.hw }, 292 { .hw = &mmpll7.clkr.hw }, 293 { .hw = &mmpll10.clkr.hw }, 294 { .fw_name = "gpll0" }, 295 { .fw_name = "gpll0_div" }, 296}; 297 298static const struct parent_map mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map[] = { 299 { P_XO, 0 }, 300 { P_MMPLL4, 1 }, 301 { P_MMPLL7, 2 }, 302 { P_MMPLL10, 3 }, 303 { P_SLEEP_CLK, 4 }, 304 { P_GPLL0, 5 }, 305 { P_GPLL0_DIV, 6 }, 306}; 307 308static const struct clk_parent_data mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div[] = { 309 { .fw_name = "xo" }, 310 { .hw = &mmpll4.clkr.hw }, 311 { .hw = &mmpll7.clkr.hw }, 312 { .hw = &mmpll10.clkr.hw }, 313 { .fw_name = "sleep_clk" }, 314 { .fw_name = "gpll0" }, 315 { .fw_name = "gpll0_div" }, 316}; 317 318static const struct parent_map mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map[] = { 319 { P_XO, 0 }, 320 { P_MMPLL0, 1 }, 321 { P_MMPLL7, 2 }, 322 { P_MMPLL10, 3 }, 323 { P_SLEEP_CLK, 4 }, 324 { P_GPLL0, 5 }, 325 { P_GPLL0_DIV, 6 }, 326}; 327 328static const struct clk_parent_data mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div[] = { 329 { .fw_name = "xo" }, 330 { .hw = &mmpll0.clkr.hw }, 331 { .hw = &mmpll7.clkr.hw }, 332 { .hw = &mmpll10.clkr.hw }, 333 { .fw_name = "sleep_clk" }, 334 { .fw_name = "gpll0" }, 335 { .fw_name = "gpll0_div" }, 336}; 337 338static const struct parent_map mmcc_xo_gpll0_gpll0_div_map[] = { 339 { P_XO, 0 }, 340 { P_GPLL0, 5 }, 341 { P_GPLL0_DIV, 6 }, 342}; 343 344static const struct clk_parent_data mmcc_xo_gpll0_gpll0_div[] = { 345 { .fw_name = "xo" }, 346 { .fw_name = "gpll0" }, 347 { .fw_name = "gpll0_div" }, 348}; 349 350static const struct parent_map mmcc_xo_dplink_dpvco_map[] = { 351 { P_XO, 0 }, 352 { P_DP_PHY_PLL_LINK_CLK, 1 }, 353 { P_DP_PHY_PLL_VCO_DIV, 2 }, 354}; 355 356static const struct clk_parent_data mmcc_xo_dplink_dpvco[] = { 357 { .fw_name = "xo" }, 358 { .fw_name = "dp_link_2x_clk_divsel_five" }, 359 { .fw_name = "dp_vco_divided_clk_src_mux" }, 360}; 361 362static const struct parent_map mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map[] = { 363 { P_XO, 0 }, 364 { P_MMPLL0, 1 }, 365 { P_MMPLL5, 2 }, 366 { P_MMPLL7, 3 }, 367 { P_GPLL0, 5 }, 368 { P_GPLL0_DIV, 6 }, 369}; 370 371static const struct clk_parent_data mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div[] = { 372 { .fw_name = "xo" }, 373 { .hw = &mmpll0.clkr.hw }, 374 { .hw = &mmpll5.clkr.hw }, 375 { .hw = &mmpll7.clkr.hw }, 376 { .fw_name = "gpll0" }, 377 { .fw_name = "gpll0_div" }, 378}; 379 380static const struct parent_map mmcc_xo_dsi0pll_dsi1pll_map[] = { 381 { P_XO, 0 }, 382 { P_DSI0PLL, 1 }, 383 { P_DSI1PLL, 2 }, 384}; 385 386static const struct clk_parent_data mmcc_xo_dsi0pll_dsi1pll[] = { 387 { .fw_name = "xo" }, 388 { .fw_name = "dsi0pll" }, 389 { .fw_name = "dsi1pll" }, 390}; 391 392static const struct parent_map mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map[] = { 393 { P_XO, 0 }, 394 { P_MMPLL0, 1 }, 395 { P_MMPLL4, 2 }, 396 { P_MMPLL7, 3 }, 397 { P_MMPLL10, 4 }, 398 { P_MMPLL6, 5 }, 399 { P_GPLL0, 6 }, 400}; 401 402static const struct clk_parent_data mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0[] = { 403 { .fw_name = "xo" }, 404 { .hw = &mmpll0.clkr.hw }, 405 { .hw = &mmpll4.clkr.hw }, 406 { .hw = &mmpll7.clkr.hw }, 407 { .hw = &mmpll10.clkr.hw }, 408 { .hw = &mmpll6.clkr.hw }, 409 { .fw_name = "gpll0" }, 410}; 411 412static const struct parent_map mmcc_xo_mmpll0_gpll0_gpll0_div_map[] = { 413 { P_XO, 0 }, 414 { P_MMPLL0, 1 }, 415 { P_GPLL0, 5 }, 416 { P_GPLL0_DIV, 6 }, 417}; 418 419static const struct clk_parent_data mmcc_xo_mmpll0_gpll0_gpll0_div[] = { 420 { .fw_name = "xo" }, 421 { .hw = &mmpll0.clkr.hw }, 422 { .fw_name = "gpll0" }, 423 { .fw_name = "gpll0_div" }, 424}; 425 426static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6_map[] = { 427 { P_XO, 0 }, 428 { P_MMPLL0, 1 }, 429 { P_MMPLL4, 2 }, 430 { P_MMPLL7, 3 }, 431 { P_MMPLL10, 4 }, 432 { P_GPLL0, 5 }, 433 { P_MMPLL6, 6 }, 434}; 435 436static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6[] = { 437 { .fw_name = "xo" }, 438 { .hw = &mmpll0.clkr.hw }, 439 { .hw = &mmpll4.clkr.hw }, 440 { .hw = &mmpll7.clkr.hw }, 441 { .hw = &mmpll10.clkr.hw }, 442 { .fw_name = "gpll0" }, 443 { .hw = &mmpll6.clkr.hw }, 444}; 445 446static const struct parent_map mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7_map[] = { 447 { P_XO, 0 }, 448 { P_MMPLL0, 1 }, 449 { P_MMPLL8, 2 }, 450 { P_MMPLL3, 3 }, 451 { P_MMPLL6, 4 }, 452 { P_GPLL0, 5 }, 453 { P_MMPLL7, 6 }, 454}; 455 456static const struct clk_parent_data mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7[] = { 457 { .fw_name = "xo" }, 458 { .hw = &mmpll0.clkr.hw }, 459 { .hw = &mmpll8.clkr.hw }, 460 { .hw = &mmpll3.clkr.hw }, 461 { .hw = &mmpll6.clkr.hw }, 462 { .fw_name = "gpll0" }, 463 { .hw = &mmpll7.clkr.hw }, 464}; 465 466static const struct freq_tbl ftbl_ahb_clk_src[] = { 467 F(19200000, P_XO, 1, 0, 0), 468 F(40000000, P_GPLL0_DIV, 7.5, 0, 0), 469 F(80800000, P_MMPLL0, 10, 0, 0), 470 { } 471}; 472 473static struct clk_rcg2 ahb_clk_src = { 474 .cmd_rcgr = 0x5000, 475 .mnd_width = 0, 476 .hid_width = 5, 477 .parent_map = mmcc_xo_mmpll0_gpll0_gpll0_div_map, 478 .freq_tbl = ftbl_ahb_clk_src, 479 .clkr.hw.init = &(struct clk_init_data){ 480 .name = "ahb_clk_src", 481 .parent_data = mmcc_xo_mmpll0_gpll0_gpll0_div, 482 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_gpll0_gpll0_div), 483 .ops = &clk_rcg2_ops, 484 }, 485}; 486 487static struct clk_rcg2 byte0_clk_src = { 488 .cmd_rcgr = 0x2120, 489 .mnd_width = 0, 490 .hid_width = 5, 491 .parent_map = mmcc_xo_dsibyte_map, 492 .clkr.hw.init = &(struct clk_init_data){ 493 .name = "byte0_clk_src", 494 .parent_data = mmcc_xo_dsibyte, 495 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte), 496 .ops = &clk_byte2_ops, 497 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 498 }, 499}; 500 501static struct clk_rcg2 byte1_clk_src = { 502 .cmd_rcgr = 0x2140, 503 .mnd_width = 0, 504 .hid_width = 5, 505 .parent_map = mmcc_xo_dsibyte_map, 506 .clkr.hw.init = &(struct clk_init_data){ 507 .name = "byte1_clk_src", 508 .parent_data = mmcc_xo_dsibyte, 509 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte), 510 .ops = &clk_byte2_ops, 511 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 512 }, 513}; 514 515static const struct freq_tbl ftbl_camss_gp0_clk_src[] = { 516 F(10000, P_XO, 16, 1, 120), 517 F(24000, P_XO, 16, 1, 50), 518 F(6000000, P_GPLL0_DIV, 10, 1, 5), 519 F(12000000, P_GPLL0_DIV, 10, 2, 5), 520 F(13043478, P_GPLL0_DIV, 1, 1, 23), 521 F(24000000, P_GPLL0_DIV, 1, 2, 25), 522 F(50000000, P_GPLL0_DIV, 6, 0, 0), 523 F(100000000, P_GPLL0_DIV, 3, 0, 0), 524 F(200000000, P_GPLL0, 3, 0, 0), 525 { } 526}; 527 528static struct clk_rcg2 camss_gp0_clk_src = { 529 .cmd_rcgr = 0x3420, 530 .mnd_width = 8, 531 .hid_width = 5, 532 .parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map, 533 .freq_tbl = ftbl_camss_gp0_clk_src, 534 .clkr.hw.init = &(struct clk_init_data){ 535 .name = "camss_gp0_clk_src", 536 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div, 537 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div), 538 .ops = &clk_rcg2_ops, 539 }, 540}; 541 542static struct clk_rcg2 camss_gp1_clk_src = { 543 .cmd_rcgr = 0x3450, 544 .mnd_width = 8, 545 .hid_width = 5, 546 .parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map, 547 .freq_tbl = ftbl_camss_gp0_clk_src, 548 .clkr.hw.init = &(struct clk_init_data){ 549 .name = "camss_gp1_clk_src", 550 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div, 551 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div), 552 .ops = &clk_rcg2_ops, 553 }, 554}; 555 556static const struct freq_tbl ftbl_cci_clk_src[] = { 557 F(37500000, P_GPLL0_DIV, 8, 0, 0), 558 F(50000000, P_GPLL0_DIV, 6, 0, 0), 559 F(100000000, P_GPLL0, 6, 0, 0), 560 { } 561}; 562 563static struct clk_rcg2 cci_clk_src = { 564 .cmd_rcgr = 0x3300, 565 .mnd_width = 8, 566 .hid_width = 5, 567 .parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map, 568 .freq_tbl = ftbl_cci_clk_src, 569 .clkr.hw.init = &(struct clk_init_data){ 570 .name = "cci_clk_src", 571 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div, 572 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div), 573 .ops = &clk_rcg2_ops, 574 }, 575}; 576 577static const struct freq_tbl ftbl_cpp_clk_src[] = { 578 F(120000000, P_GPLL0, 5, 0, 0), 579 F(256000000, P_MMPLL4, 3, 0, 0), 580 F(384000000, P_MMPLL4, 2, 0, 0), 581 F(480000000, P_MMPLL7, 2, 0, 0), 582 F(540000000, P_MMPLL6, 2, 0, 0), 583 F(576000000, P_MMPLL10, 1, 0, 0), 584 { } 585}; 586 587static struct clk_rcg2 cpp_clk_src = { 588 .cmd_rcgr = 0x3640, 589 .mnd_width = 0, 590 .hid_width = 5, 591 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6_map, 592 .freq_tbl = ftbl_cpp_clk_src, 593 .clkr.hw.init = &(struct clk_init_data){ 594 .name = "cpp_clk_src", 595 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6, 596 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6), 597 .ops = &clk_rcg2_ops, 598 }, 599}; 600 601static const struct freq_tbl ftbl_csi0_clk_src[] = { 602 F(100000000, P_GPLL0_DIV, 3, 0, 0), 603 F(200000000, P_GPLL0, 3, 0, 0), 604 F(310000000, P_MMPLL8, 3, 0, 0), 605 F(404000000, P_MMPLL0, 2, 0, 0), 606 F(465000000, P_MMPLL8, 2, 0, 0), 607 { } 608}; 609 610static struct clk_rcg2 csi0_clk_src = { 611 .cmd_rcgr = 0x3090, 612 .mnd_width = 0, 613 .hid_width = 5, 614 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map, 615 .freq_tbl = ftbl_csi0_clk_src, 616 .clkr.hw.init = &(struct clk_init_data){ 617 .name = "csi0_clk_src", 618 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, 619 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), 620 .ops = &clk_rcg2_ops, 621 }, 622}; 623 624static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = { 625 F(100000000, P_GPLL0_DIV, 3, 0, 0), 626 F(200000000, P_GPLL0, 3, 0, 0), 627 F(269333333, P_MMPLL0, 3, 0, 0), 628 { } 629}; 630 631static struct clk_rcg2 csi0phytimer_clk_src = { 632 .cmd_rcgr = 0x3000, 633 .mnd_width = 0, 634 .hid_width = 5, 635 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 636 .freq_tbl = ftbl_csi0phytimer_clk_src, 637 .clkr.hw.init = &(struct clk_init_data){ 638 .name = "csi0phytimer_clk_src", 639 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 640 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 641 .ops = &clk_rcg2_ops, 642 }, 643}; 644 645static struct clk_rcg2 csi1_clk_src = { 646 .cmd_rcgr = 0x3100, 647 .mnd_width = 0, 648 .hid_width = 5, 649 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map, 650 .freq_tbl = ftbl_csi0_clk_src, 651 .clkr.hw.init = &(struct clk_init_data){ 652 .name = "csi1_clk_src", 653 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, 654 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), 655 .ops = &clk_rcg2_ops, 656 }, 657}; 658 659static struct clk_rcg2 csi1phytimer_clk_src = { 660 .cmd_rcgr = 0x3030, 661 .mnd_width = 0, 662 .hid_width = 5, 663 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 664 .freq_tbl = ftbl_csi0phytimer_clk_src, 665 .clkr.hw.init = &(struct clk_init_data){ 666 .name = "csi1phytimer_clk_src", 667 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 668 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 669 .ops = &clk_rcg2_ops, 670 }, 671}; 672 673static struct clk_rcg2 csi2_clk_src = { 674 .cmd_rcgr = 0x3160, 675 .mnd_width = 0, 676 .hid_width = 5, 677 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map, 678 .freq_tbl = ftbl_csi0_clk_src, 679 .clkr.hw.init = &(struct clk_init_data){ 680 .name = "csi2_clk_src", 681 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, 682 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), 683 .ops = &clk_rcg2_ops, 684 }, 685}; 686 687static struct clk_rcg2 csi2phytimer_clk_src = { 688 .cmd_rcgr = 0x3060, 689 .mnd_width = 0, 690 .hid_width = 5, 691 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 692 .freq_tbl = ftbl_csi0phytimer_clk_src, 693 .clkr.hw.init = &(struct clk_init_data){ 694 .name = "csi2phytimer_clk_src", 695 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 696 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 697 .ops = &clk_rcg2_ops, 698 }, 699}; 700 701static struct clk_rcg2 csi3_clk_src = { 702 .cmd_rcgr = 0x31c0, 703 .mnd_width = 0, 704 .hid_width = 5, 705 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map, 706 .freq_tbl = ftbl_csi0_clk_src, 707 .clkr.hw.init = &(struct clk_init_data){ 708 .name = "csi3_clk_src", 709 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, 710 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), 711 .ops = &clk_rcg2_ops, 712 }, 713}; 714 715static const struct freq_tbl ftbl_csiphy_clk_src[] = { 716 F(100000000, P_GPLL0_DIV, 3, 0, 0), 717 F(200000000, P_GPLL0, 3, 0, 0), 718 F(269333333, P_MMPLL0, 3, 0, 0), 719 F(320000000, P_MMPLL7, 3, 0, 0), 720 { } 721}; 722 723static struct clk_rcg2 csiphy_clk_src = { 724 .cmd_rcgr = 0x3800, 725 .mnd_width = 0, 726 .hid_width = 5, 727 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map, 728 .freq_tbl = ftbl_csiphy_clk_src, 729 .clkr.hw.init = &(struct clk_init_data){ 730 .name = "csiphy_clk_src", 731 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div, 732 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div), 733 .ops = &clk_rcg2_ops, 734 }, 735}; 736 737static const struct freq_tbl ftbl_dp_aux_clk_src[] = { 738 F(19200000, P_XO, 1, 0, 0), 739 { } 740}; 741 742static struct clk_rcg2 dp_aux_clk_src = { 743 .cmd_rcgr = 0x2260, 744 .mnd_width = 0, 745 .hid_width = 5, 746 .parent_map = mmcc_xo_gpll0_gpll0_div_map, 747 .freq_tbl = ftbl_dp_aux_clk_src, 748 .clkr.hw.init = &(struct clk_init_data){ 749 .name = "dp_aux_clk_src", 750 .parent_data = mmcc_xo_gpll0_gpll0_div, 751 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div), 752 .ops = &clk_rcg2_ops, 753 }, 754}; 755 756static const struct freq_tbl ftbl_dp_crypto_clk_src[] = { 757 F(101250000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), 758 F(168750000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), 759 F(337500000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), 760 { } 761}; 762 763static struct clk_rcg2 dp_crypto_clk_src = { 764 .cmd_rcgr = 0x2220, 765 .mnd_width = 8, 766 .hid_width = 5, 767 .parent_map = mmcc_xo_dplink_dpvco_map, 768 .freq_tbl = ftbl_dp_crypto_clk_src, 769 .clkr.hw.init = &(struct clk_init_data){ 770 .name = "dp_crypto_clk_src", 771 .parent_data = mmcc_xo_dplink_dpvco, 772 .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco), 773 .ops = &clk_rcg2_ops, 774 }, 775}; 776 777static const struct freq_tbl ftbl_dp_gtc_clk_src[] = { 778 F(40000000, P_GPLL0_DIV, 7.5, 0, 0), 779 F(60000000, P_GPLL0, 10, 0, 0), 780 { } 781}; 782 783static struct clk_rcg2 dp_gtc_clk_src = { 784 .cmd_rcgr = 0x2280, 785 .mnd_width = 0, 786 .hid_width = 5, 787 .parent_map = mmcc_xo_gpll0_gpll0_div_map, 788 .freq_tbl = ftbl_dp_gtc_clk_src, 789 .clkr.hw.init = &(struct clk_init_data){ 790 .name = "dp_gtc_clk_src", 791 .parent_data = mmcc_xo_gpll0_gpll0_div, 792 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div), 793 .ops = &clk_rcg2_ops, 794 }, 795}; 796 797static const struct freq_tbl ftbl_dp_link_clk_src[] = { 798 F(162000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), 799 F(270000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), 800 F(540000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), 801 { } 802}; 803 804static struct clk_rcg2 dp_link_clk_src = { 805 .cmd_rcgr = 0x2200, 806 .mnd_width = 0, 807 .hid_width = 5, 808 .parent_map = mmcc_xo_dplink_dpvco_map, 809 .freq_tbl = ftbl_dp_link_clk_src, 810 .clkr.hw.init = &(struct clk_init_data){ 811 .name = "dp_link_clk_src", 812 .parent_data = mmcc_xo_dplink_dpvco, 813 .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco), 814 .ops = &clk_rcg2_ops, 815 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 816 }, 817}; 818 819static struct clk_rcg2 dp_pixel_clk_src = { 820 .cmd_rcgr = 0x2240, 821 .mnd_width = 16, 822 .hid_width = 5, 823 .parent_map = mmcc_xo_dplink_dpvco_map, 824 .clkr.hw.init = &(struct clk_init_data){ 825 .name = "dp_pixel_clk_src", 826 .parent_data = mmcc_xo_dplink_dpvco, 827 .num_parents = ARRAY_SIZE(mmcc_xo_dplink_dpvco), 828 .ops = &clk_dp_ops, 829 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 830 }, 831}; 832 833static struct clk_rcg2 esc0_clk_src = { 834 .cmd_rcgr = 0x2160, 835 .mnd_width = 0, 836 .hid_width = 5, 837 .parent_map = mmcc_xo_dsibyte_map, 838 .clkr.hw.init = &(struct clk_init_data){ 839 .name = "esc0_clk_src", 840 .parent_data = mmcc_xo_dsibyte, 841 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte), 842 .ops = &clk_rcg2_ops, 843 }, 844}; 845 846static struct clk_rcg2 esc1_clk_src = { 847 .cmd_rcgr = 0x2180, 848 .mnd_width = 0, 849 .hid_width = 5, 850 .parent_map = mmcc_xo_dsibyte_map, 851 .clkr.hw.init = &(struct clk_init_data){ 852 .name = "esc1_clk_src", 853 .parent_data = mmcc_xo_dsibyte, 854 .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte), 855 .ops = &clk_rcg2_ops, 856 }, 857}; 858 859static const struct freq_tbl ftbl_jpeg0_clk_src[] = { 860 F(66666667, P_GPLL0_DIV, 4.5, 0, 0), 861 F(133333333, P_GPLL0, 4.5, 0, 0), 862 F(219428571, P_MMPLL4, 3.5, 0, 0), 863 F(320000000, P_MMPLL7, 3, 0, 0), 864 F(480000000, P_MMPLL7, 2, 0, 0), 865 { } 866}; 867 868static struct clk_rcg2 jpeg0_clk_src = { 869 .cmd_rcgr = 0x3500, 870 .mnd_width = 0, 871 .hid_width = 5, 872 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 873 .freq_tbl = ftbl_jpeg0_clk_src, 874 .clkr.hw.init = &(struct clk_init_data){ 875 .name = "jpeg0_clk_src", 876 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 877 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 878 .ops = &clk_rcg2_ops, 879 }, 880}; 881 882static const struct freq_tbl ftbl_mclk0_clk_src[] = { 883 F(4800000, P_XO, 4, 0, 0), 884 F(6000000, P_GPLL0_DIV, 10, 1, 5), 885 F(8000000, P_GPLL0_DIV, 1, 2, 75), 886 F(9600000, P_XO, 2, 0, 0), 887 F(16666667, P_GPLL0_DIV, 2, 1, 9), 888 F(19200000, P_XO, 1, 0, 0), 889 F(24000000, P_MMPLL10, 1, 1, 24), 890 F(33333333, P_GPLL0_DIV, 1, 1, 9), 891 F(48000000, P_GPLL0, 1, 2, 25), 892 F(66666667, P_GPLL0, 1, 1, 9), 893 { } 894}; 895 896static struct clk_rcg2 mclk0_clk_src = { 897 .cmd_rcgr = 0x3360, 898 .mnd_width = 8, 899 .hid_width = 5, 900 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map, 901 .freq_tbl = ftbl_mclk0_clk_src, 902 .clkr.hw.init = &(struct clk_init_data){ 903 .name = "mclk0_clk_src", 904 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div, 905 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div), 906 .ops = &clk_rcg2_ops, 907 }, 908}; 909 910static struct clk_rcg2 mclk1_clk_src = { 911 .cmd_rcgr = 0x3390, 912 .mnd_width = 8, 913 .hid_width = 5, 914 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map, 915 .freq_tbl = ftbl_mclk0_clk_src, 916 .clkr.hw.init = &(struct clk_init_data){ 917 .name = "mclk1_clk_src", 918 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div, 919 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div), 920 .ops = &clk_rcg2_ops, 921 }, 922}; 923 924static struct clk_rcg2 mclk2_clk_src = { 925 .cmd_rcgr = 0x33c0, 926 .mnd_width = 8, 927 .hid_width = 5, 928 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map, 929 .freq_tbl = ftbl_mclk0_clk_src, 930 .clkr.hw.init = &(struct clk_init_data){ 931 .name = "mclk2_clk_src", 932 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div, 933 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div), 934 .ops = &clk_rcg2_ops, 935 }, 936}; 937 938static struct clk_rcg2 mclk3_clk_src = { 939 .cmd_rcgr = 0x33f0, 940 .mnd_width = 8, 941 .hid_width = 5, 942 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map, 943 .freq_tbl = ftbl_mclk0_clk_src, 944 .clkr.hw.init = &(struct clk_init_data){ 945 .name = "mclk3_clk_src", 946 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div, 947 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div), 948 .ops = &clk_rcg2_ops, 949 }, 950}; 951 952static const struct freq_tbl ftbl_mdp_clk_src[] = { 953 F(100000000, P_GPLL0_DIV, 3, 0, 0), 954 F(150000000, P_GPLL0_DIV, 2, 0, 0), 955 F(171428571, P_GPLL0, 3.5, 0, 0), 956 F(200000000, P_GPLL0, 3, 0, 0), 957 F(275000000, P_MMPLL5, 3, 0, 0), 958 F(300000000, P_GPLL0, 2, 0, 0), 959 F(330000000, P_MMPLL5, 2.5, 0, 0), 960 F(412500000, P_MMPLL5, 2, 0, 0), 961 { } 962}; 963 964static struct clk_rcg2 mdp_clk_src = { 965 .cmd_rcgr = 0x2040, 966 .mnd_width = 0, 967 .hid_width = 5, 968 .parent_map = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map, 969 .freq_tbl = ftbl_mdp_clk_src, 970 .clkr.hw.init = &(struct clk_init_data){ 971 .name = "mdp_clk_src", 972 .parent_data = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div, 973 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div), 974 .ops = &clk_rcg2_ops, 975 }, 976}; 977 978static struct clk_rcg2 pclk0_clk_src = { 979 .cmd_rcgr = 0x2000, 980 .mnd_width = 8, 981 .hid_width = 5, 982 .parent_map = mmcc_xo_dsi0pll_dsi1pll_map, 983 .clkr.hw.init = &(struct clk_init_data){ 984 .name = "pclk0_clk_src", 985 .parent_data = mmcc_xo_dsi0pll_dsi1pll, 986 .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll), 987 .ops = &clk_pixel_ops, 988 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 989 }, 990}; 991 992static struct clk_rcg2 pclk1_clk_src = { 993 .cmd_rcgr = 0x2020, 994 .mnd_width = 8, 995 .hid_width = 5, 996 .parent_map = mmcc_xo_dsi0pll_dsi1pll_map, 997 .clkr.hw.init = &(struct clk_init_data){ 998 .name = "pclk1_clk_src", 999 .parent_data = mmcc_xo_dsi0pll_dsi1pll, 1000 .num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll), 1001 .ops = &clk_pixel_ops, 1002 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 1003 }, 1004}; 1005 1006static const struct freq_tbl ftbl_rot_clk_src[] = { 1007 F(171428571, P_GPLL0, 3.5, 0, 0), 1008 F(275000000, P_MMPLL5, 3, 0, 0), 1009 F(300000000, P_GPLL0, 2, 0, 0), 1010 F(330000000, P_MMPLL5, 2.5, 0, 0), 1011 F(412500000, P_MMPLL5, 2, 0, 0), 1012 { } 1013}; 1014 1015static struct clk_rcg2 rot_clk_src = { 1016 .cmd_rcgr = 0x21a0, 1017 .mnd_width = 0, 1018 .hid_width = 5, 1019 .parent_map = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map, 1020 .freq_tbl = ftbl_rot_clk_src, 1021 .clkr.hw.init = &(struct clk_init_data){ 1022 .name = "rot_clk_src", 1023 .parent_data = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div, 1024 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div), 1025 .ops = &clk_rcg2_ops, 1026 }, 1027}; 1028 1029static const struct freq_tbl ftbl_vfe0_clk_src[] = { 1030 F(120000000, P_GPLL0, 5, 0, 0), 1031 F(200000000, P_GPLL0, 3, 0, 0), 1032 F(256000000, P_MMPLL4, 3, 0, 0), 1033 F(300000000, P_GPLL0, 2, 0, 0), 1034 F(404000000, P_MMPLL0, 2, 0, 0), 1035 F(480000000, P_MMPLL7, 2, 0, 0), 1036 F(540000000, P_MMPLL6, 2, 0, 0), 1037 F(576000000, P_MMPLL10, 1, 0, 0), 1038 { } 1039}; 1040 1041static struct clk_rcg2 vfe0_clk_src = { 1042 .cmd_rcgr = 0x3600, 1043 .mnd_width = 0, 1044 .hid_width = 5, 1045 .parent_map = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map, 1046 .freq_tbl = ftbl_vfe0_clk_src, 1047 .clkr.hw.init = &(struct clk_init_data){ 1048 .name = "vfe0_clk_src", 1049 .parent_data = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0, 1050 .num_parents = ARRAY_SIZE(mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0), 1051 .ops = &clk_rcg2_ops, 1052 }, 1053}; 1054 1055static struct clk_rcg2 vfe1_clk_src = { 1056 .cmd_rcgr = 0x3620, 1057 .mnd_width = 0, 1058 .hid_width = 5, 1059 .parent_map = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map, 1060 .freq_tbl = ftbl_vfe0_clk_src, 1061 .clkr.hw.init = &(struct clk_init_data){ 1062 .name = "vfe1_clk_src", 1063 .parent_data = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0, 1064 .num_parents = ARRAY_SIZE(mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0), 1065 .ops = &clk_rcg2_ops, 1066 }, 1067}; 1068 1069static const struct freq_tbl ftbl_video_core_clk_src[] = { 1070 F(133333333, P_GPLL0, 4.5, 0, 0), 1071 F(269333333, P_MMPLL0, 3, 0, 0), 1072 F(320000000, P_MMPLL7, 3, 0, 0), 1073 F(404000000, P_MMPLL0, 2, 0, 0), 1074 F(441600000, P_MMPLL3, 2, 0, 0), 1075 F(518400000, P_MMPLL3, 2, 0, 0), 1076 { } 1077}; 1078 1079static struct clk_rcg2 video_core_clk_src = { 1080 .cmd_rcgr = 0x1000, 1081 .mnd_width = 0, 1082 .hid_width = 5, 1083 .parent_map = mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7_map, 1084 .freq_tbl = ftbl_video_core_clk_src, 1085 .clkr.hw.init = &(struct clk_init_data){ 1086 .name = "video_core_clk_src", 1087 .parent_data = mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7, 1088 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7), 1089 .ops = &clk_rcg2_ops, 1090 .flags = CLK_IS_CRITICAL, 1091 }, 1092}; 1093 1094static struct clk_rcg2 vsync_clk_src = { 1095 .cmd_rcgr = 0x2080, 1096 .mnd_width = 0, 1097 .hid_width = 5, 1098 .parent_map = mmcc_xo_gpll0_gpll0_div_map, 1099 .freq_tbl = ftbl_dp_aux_clk_src, 1100 .clkr.hw.init = &(struct clk_init_data){ 1101 .name = "vsync_clk_src", 1102 .parent_data = mmcc_xo_gpll0_gpll0_div, 1103 .num_parents = ARRAY_SIZE(mmcc_xo_gpll0_gpll0_div), 1104 .ops = &clk_rcg2_ops, 1105 }, 1106}; 1107 1108static struct clk_branch bimc_smmu_ahb_clk = { 1109 .halt_reg = 0xe004, 1110 .halt_check = BRANCH_VOTED, 1111 .hwcg_reg = 0xe004, 1112 .hwcg_bit = 1, 1113 .clkr = { 1114 .enable_reg = 0xe004, 1115 .enable_mask = BIT(0), 1116 .hw.init = &(struct clk_init_data){ 1117 .name = "bimc_smmu_ahb_clk", 1118 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1119 .num_parents = 1, 1120 .ops = &clk_branch2_ops, 1121 }, 1122 }, 1123}; 1124 1125static struct clk_branch bimc_smmu_axi_clk = { 1126 .halt_reg = 0xe008, 1127 .halt_check = BRANCH_VOTED, 1128 .hwcg_reg = 0xe008, 1129 .hwcg_bit = 1, 1130 .clkr = { 1131 .enable_reg = 0xe008, 1132 .enable_mask = BIT(0), 1133 .hw.init = &(struct clk_init_data){ 1134 .name = "bimc_smmu_axi_clk", 1135 .ops = &clk_branch2_ops, 1136 }, 1137 }, 1138}; 1139 1140static struct clk_branch camss_ahb_clk = { 1141 .halt_reg = 0x348c, 1142 .halt_check = BRANCH_HALT, 1143 .hwcg_reg = 0x348c, 1144 .hwcg_bit = 1, 1145 .clkr = { 1146 .enable_reg = 0x348c, 1147 .enable_mask = BIT(0), 1148 .hw.init = &(struct clk_init_data){ 1149 .name = "camss_ahb_clk", 1150 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1151 .num_parents = 1, 1152 .ops = &clk_branch2_ops, 1153 }, 1154 }, 1155}; 1156 1157static struct clk_branch camss_cci_ahb_clk = { 1158 .halt_reg = 0x3348, 1159 .halt_check = BRANCH_HALT, 1160 .clkr = { 1161 .enable_reg = 0x3348, 1162 .enable_mask = BIT(0), 1163 .hw.init = &(struct clk_init_data){ 1164 .name = "camss_cci_ahb_clk", 1165 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1166 .num_parents = 1, 1167 .flags = CLK_SET_RATE_PARENT, 1168 .ops = &clk_branch2_ops, 1169 }, 1170 }, 1171}; 1172 1173static struct clk_branch camss_cci_clk = { 1174 .halt_reg = 0x3344, 1175 .halt_check = BRANCH_HALT, 1176 .clkr = { 1177 .enable_reg = 0x3344, 1178 .enable_mask = BIT(0), 1179 .hw.init = &(struct clk_init_data){ 1180 .name = "camss_cci_clk", 1181 .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw }, 1182 .num_parents = 1, 1183 .flags = CLK_SET_RATE_PARENT, 1184 .ops = &clk_branch2_ops, 1185 }, 1186 }, 1187}; 1188 1189static struct clk_branch camss_cpp_ahb_clk = { 1190 .halt_reg = 0x36b4, 1191 .halt_check = BRANCH_HALT, 1192 .clkr = { 1193 .enable_reg = 0x36b4, 1194 .enable_mask = BIT(0), 1195 .hw.init = &(struct clk_init_data){ 1196 .name = "camss_cpp_ahb_clk", 1197 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1198 .num_parents = 1, 1199 .ops = &clk_branch2_ops, 1200 }, 1201 }, 1202}; 1203 1204static struct clk_branch camss_cpp_axi_clk = { 1205 .halt_reg = 0x36c4, 1206 .halt_check = BRANCH_HALT, 1207 .clkr = { 1208 .enable_reg = 0x36c4, 1209 .enable_mask = BIT(0), 1210 .hw.init = &(struct clk_init_data){ 1211 .name = "camss_cpp_axi_clk", 1212 .ops = &clk_branch2_ops, 1213 }, 1214 }, 1215}; 1216 1217static struct clk_branch camss_cpp_clk = { 1218 .halt_reg = 0x36b0, 1219 .halt_check = BRANCH_HALT, 1220 .clkr = { 1221 .enable_reg = 0x36b0, 1222 .enable_mask = BIT(0), 1223 .hw.init = &(struct clk_init_data){ 1224 .name = "camss_cpp_clk", 1225 .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw }, 1226 .num_parents = 1, 1227 .flags = CLK_SET_RATE_PARENT, 1228 .ops = &clk_branch2_ops, 1229 }, 1230 }, 1231}; 1232 1233static struct clk_branch camss_cpp_vbif_ahb_clk = { 1234 .halt_reg = 0x36c8, 1235 .halt_check = BRANCH_HALT, 1236 .clkr = { 1237 .enable_reg = 0x36c8, 1238 .enable_mask = BIT(0), 1239 .hw.init = &(struct clk_init_data){ 1240 .name = "camss_cpp_vbif_ahb_clk", 1241 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1242 .num_parents = 1, 1243 .ops = &clk_branch2_ops, 1244 }, 1245 }, 1246}; 1247 1248static struct clk_branch camss_csi0_ahb_clk = { 1249 .halt_reg = 0x30bc, 1250 .halt_check = BRANCH_HALT, 1251 .clkr = { 1252 .enable_reg = 0x30bc, 1253 .enable_mask = BIT(0), 1254 .hw.init = &(struct clk_init_data){ 1255 .name = "camss_csi0_ahb_clk", 1256 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1257 .num_parents = 1, 1258 .ops = &clk_branch2_ops, 1259 }, 1260 }, 1261}; 1262 1263static struct clk_branch camss_csi0_clk = { 1264 .halt_reg = 0x30b4, 1265 .halt_check = BRANCH_HALT, 1266 .clkr = { 1267 .enable_reg = 0x30b4, 1268 .enable_mask = BIT(0), 1269 .hw.init = &(struct clk_init_data){ 1270 .name = "camss_csi0_clk", 1271 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw }, 1272 .num_parents = 1, 1273 .flags = CLK_SET_RATE_PARENT, 1274 .ops = &clk_branch2_ops, 1275 }, 1276 }, 1277}; 1278 1279static struct clk_branch camss_csi0phytimer_clk = { 1280 .halt_reg = 0x3024, 1281 .halt_check = BRANCH_HALT, 1282 .clkr = { 1283 .enable_reg = 0x3024, 1284 .enable_mask = BIT(0), 1285 .hw.init = &(struct clk_init_data){ 1286 .name = "camss_csi0phytimer_clk", 1287 .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw }, 1288 .num_parents = 1, 1289 .flags = CLK_SET_RATE_PARENT, 1290 .ops = &clk_branch2_ops, 1291 }, 1292 }, 1293}; 1294 1295static struct clk_branch camss_csi0pix_clk = { 1296 .halt_reg = 0x30e4, 1297 .halt_check = BRANCH_HALT, 1298 .clkr = { 1299 .enable_reg = 0x30e4, 1300 .enable_mask = BIT(0), 1301 .hw.init = &(struct clk_init_data){ 1302 .name = "camss_csi0pix_clk", 1303 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw }, 1304 .num_parents = 1, 1305 .ops = &clk_branch2_ops, 1306 }, 1307 }, 1308}; 1309 1310static struct clk_branch camss_csi0rdi_clk = { 1311 .halt_reg = 0x30d4, 1312 .halt_check = BRANCH_HALT, 1313 .clkr = { 1314 .enable_reg = 0x30d4, 1315 .enable_mask = BIT(0), 1316 .hw.init = &(struct clk_init_data){ 1317 .name = "camss_csi0rdi_clk", 1318 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw }, 1319 .num_parents = 1, 1320 .ops = &clk_branch2_ops, 1321 }, 1322 }, 1323}; 1324 1325static struct clk_branch camss_csi1_ahb_clk = { 1326 .halt_reg = 0x3128, 1327 .halt_check = BRANCH_HALT, 1328 .clkr = { 1329 .enable_reg = 0x3128, 1330 .enable_mask = BIT(0), 1331 .hw.init = &(struct clk_init_data){ 1332 .name = "camss_csi1_ahb_clk", 1333 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1334 .num_parents = 1, 1335 .ops = &clk_branch2_ops, 1336 }, 1337 }, 1338}; 1339 1340static struct clk_branch camss_csi1_clk = { 1341 .halt_reg = 0x3124, 1342 .halt_check = BRANCH_HALT, 1343 .clkr = { 1344 .enable_reg = 0x3124, 1345 .enable_mask = BIT(0), 1346 .hw.init = &(struct clk_init_data){ 1347 .name = "camss_csi1_clk", 1348 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw }, 1349 .num_parents = 1, 1350 .flags = CLK_SET_RATE_PARENT, 1351 .ops = &clk_branch2_ops, 1352 }, 1353 }, 1354}; 1355 1356static struct clk_branch camss_csi1phytimer_clk = { 1357 .halt_reg = 0x3054, 1358 .halt_check = BRANCH_HALT, 1359 .clkr = { 1360 .enable_reg = 0x3054, 1361 .enable_mask = BIT(0), 1362 .hw.init = &(struct clk_init_data){ 1363 .name = "camss_csi1phytimer_clk", 1364 .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw }, 1365 .num_parents = 1, 1366 .flags = CLK_SET_RATE_PARENT, 1367 .ops = &clk_branch2_ops, 1368 }, 1369 }, 1370}; 1371 1372static struct clk_branch camss_csi1pix_clk = { 1373 .halt_reg = 0x3154, 1374 .halt_check = BRANCH_HALT, 1375 .clkr = { 1376 .enable_reg = 0x3154, 1377 .enable_mask = BIT(0), 1378 .hw.init = &(struct clk_init_data){ 1379 .name = "camss_csi1pix_clk", 1380 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw }, 1381 .num_parents = 1, 1382 .ops = &clk_branch2_ops, 1383 }, 1384 }, 1385}; 1386 1387static struct clk_branch camss_csi1rdi_clk = { 1388 .halt_reg = 0x3144, 1389 .halt_check = BRANCH_HALT, 1390 .clkr = { 1391 .enable_reg = 0x3144, 1392 .enable_mask = BIT(0), 1393 .hw.init = &(struct clk_init_data){ 1394 .name = "camss_csi1rdi_clk", 1395 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw }, 1396 .num_parents = 1, 1397 .ops = &clk_branch2_ops, 1398 }, 1399 }, 1400}; 1401 1402static struct clk_branch camss_csi2_ahb_clk = { 1403 .halt_reg = 0x3188, 1404 .halt_check = BRANCH_HALT, 1405 .clkr = { 1406 .enable_reg = 0x3188, 1407 .enable_mask = BIT(0), 1408 .hw.init = &(struct clk_init_data){ 1409 .name = "camss_csi2_ahb_clk", 1410 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1411 .num_parents = 1, 1412 .ops = &clk_branch2_ops, 1413 }, 1414 }, 1415}; 1416 1417static struct clk_branch camss_csi2_clk = { 1418 .halt_reg = 0x3184, 1419 .halt_check = BRANCH_HALT, 1420 .clkr = { 1421 .enable_reg = 0x3184, 1422 .enable_mask = BIT(0), 1423 .hw.init = &(struct clk_init_data){ 1424 .name = "camss_csi2_clk", 1425 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw }, 1426 .num_parents = 1, 1427 .flags = CLK_SET_RATE_PARENT, 1428 .ops = &clk_branch2_ops, 1429 }, 1430 }, 1431}; 1432 1433static struct clk_branch camss_csi2phytimer_clk = { 1434 .halt_reg = 0x3084, 1435 .halt_check = BRANCH_HALT, 1436 .clkr = { 1437 .enable_reg = 0x3084, 1438 .enable_mask = BIT(0), 1439 .hw.init = &(struct clk_init_data){ 1440 .name = "camss_csi2phytimer_clk", 1441 .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw }, 1442 .num_parents = 1, 1443 .flags = CLK_SET_RATE_PARENT, 1444 .ops = &clk_branch2_ops, 1445 }, 1446 }, 1447}; 1448 1449static struct clk_branch camss_csi2pix_clk = { 1450 .halt_reg = 0x31b4, 1451 .halt_check = BRANCH_HALT, 1452 .clkr = { 1453 .enable_reg = 0x31b4, 1454 .enable_mask = BIT(0), 1455 .hw.init = &(struct clk_init_data){ 1456 .name = "camss_csi2pix_clk", 1457 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw }, 1458 .num_parents = 1, 1459 .ops = &clk_branch2_ops, 1460 }, 1461 }, 1462}; 1463 1464static struct clk_branch camss_csi2rdi_clk = { 1465 .halt_reg = 0x31a4, 1466 .halt_check = BRANCH_HALT, 1467 .clkr = { 1468 .enable_reg = 0x31a4, 1469 .enable_mask = BIT(0), 1470 .hw.init = &(struct clk_init_data){ 1471 .name = "camss_csi2rdi_clk", 1472 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw }, 1473 .num_parents = 1, 1474 .ops = &clk_branch2_ops, 1475 }, 1476 }, 1477}; 1478 1479static struct clk_branch camss_csi3_ahb_clk = { 1480 .halt_reg = 0x31e8, 1481 .halt_check = BRANCH_HALT, 1482 .clkr = { 1483 .enable_reg = 0x31e8, 1484 .enable_mask = BIT(0), 1485 .hw.init = &(struct clk_init_data){ 1486 .name = "camss_csi3_ahb_clk", 1487 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1488 .num_parents = 1, 1489 .ops = &clk_branch2_ops, 1490 }, 1491 }, 1492}; 1493 1494static struct clk_branch camss_csi3_clk = { 1495 .halt_reg = 0x31e4, 1496 .halt_check = BRANCH_HALT, 1497 .clkr = { 1498 .enable_reg = 0x31e4, 1499 .enable_mask = BIT(0), 1500 .hw.init = &(struct clk_init_data){ 1501 .name = "camss_csi3_clk", 1502 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw }, 1503 .num_parents = 1, 1504 .flags = CLK_SET_RATE_PARENT, 1505 .ops = &clk_branch2_ops, 1506 }, 1507 }, 1508}; 1509 1510static struct clk_branch camss_csi3pix_clk = { 1511 .halt_reg = 0x3214, 1512 .halt_check = BRANCH_HALT, 1513 .clkr = { 1514 .enable_reg = 0x3214, 1515 .enable_mask = BIT(0), 1516 .hw.init = &(struct clk_init_data){ 1517 .name = "camss_csi3pix_clk", 1518 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw }, 1519 .num_parents = 1, 1520 .ops = &clk_branch2_ops, 1521 }, 1522 }, 1523}; 1524 1525static struct clk_branch camss_csi3rdi_clk = { 1526 .halt_reg = 0x3204, 1527 .halt_check = BRANCH_HALT, 1528 .clkr = { 1529 .enable_reg = 0x3204, 1530 .enable_mask = BIT(0), 1531 .hw.init = &(struct clk_init_data){ 1532 .name = "camss_csi3rdi_clk", 1533 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw }, 1534 .num_parents = 1, 1535 .ops = &clk_branch2_ops, 1536 }, 1537 }, 1538}; 1539 1540static struct clk_branch camss_csi_vfe0_clk = { 1541 .halt_reg = 0x3704, 1542 .halt_check = BRANCH_HALT, 1543 .clkr = { 1544 .enable_reg = 0x3704, 1545 .enable_mask = BIT(0), 1546 .hw.init = &(struct clk_init_data){ 1547 .name = "camss_csi_vfe0_clk", 1548 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw }, 1549 .num_parents = 1, 1550 .ops = &clk_branch2_ops, 1551 }, 1552 }, 1553}; 1554 1555static struct clk_branch camss_csi_vfe1_clk = { 1556 .halt_reg = 0x3714, 1557 .halt_check = BRANCH_HALT, 1558 .clkr = { 1559 .enable_reg = 0x3714, 1560 .enable_mask = BIT(0), 1561 .hw.init = &(struct clk_init_data){ 1562 .name = "camss_csi_vfe1_clk", 1563 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw }, 1564 .num_parents = 1, 1565 .ops = &clk_branch2_ops, 1566 }, 1567 }, 1568}; 1569 1570static struct clk_branch camss_csiphy0_clk = { 1571 .halt_reg = 0x3740, 1572 .halt_check = BRANCH_HALT, 1573 .clkr = { 1574 .enable_reg = 0x3740, 1575 .enable_mask = BIT(0), 1576 .hw.init = &(struct clk_init_data){ 1577 .name = "camss_csiphy0_clk", 1578 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, 1579 .num_parents = 1, 1580 .flags = CLK_SET_RATE_PARENT, 1581 .ops = &clk_branch2_ops, 1582 }, 1583 }, 1584}; 1585 1586static struct clk_branch camss_csiphy1_clk = { 1587 .halt_reg = 0x3744, 1588 .halt_check = BRANCH_HALT, 1589 .clkr = { 1590 .enable_reg = 0x3744, 1591 .enable_mask = BIT(0), 1592 .hw.init = &(struct clk_init_data){ 1593 .name = "camss_csiphy1_clk", 1594 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, 1595 .num_parents = 1, 1596 .flags = CLK_SET_RATE_PARENT, 1597 .ops = &clk_branch2_ops, 1598 }, 1599 }, 1600}; 1601 1602static struct clk_branch camss_csiphy2_clk = { 1603 .halt_reg = 0x3748, 1604 .halt_check = BRANCH_HALT, 1605 .clkr = { 1606 .enable_reg = 0x3748, 1607 .enable_mask = BIT(0), 1608 .hw.init = &(struct clk_init_data){ 1609 .name = "camss_csiphy2_clk", 1610 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, 1611 .num_parents = 1, 1612 .flags = CLK_SET_RATE_PARENT, 1613 .ops = &clk_branch2_ops, 1614 }, 1615 }, 1616}; 1617 1618 1619static struct clk_branch camss_cphy_csid0_clk = { 1620 .halt_reg = 0x3730, 1621 .halt_check = BRANCH_HALT, 1622 .clkr = { 1623 .enable_reg = 0x3730, 1624 .enable_mask = BIT(0), 1625 .hw.init = &(struct clk_init_data){ 1626 .name = "camss_cphy_csid0_clk", 1627 .parent_hws = (const struct clk_hw *[]){ &camss_csiphy0_clk.clkr.hw }, 1628 .num_parents = 1, 1629 .flags = CLK_SET_RATE_PARENT, 1630 .ops = &clk_branch2_ops, 1631 }, 1632 }, 1633}; 1634 1635static struct clk_branch camss_cphy_csid1_clk = { 1636 .halt_reg = 0x3734, 1637 .halt_check = BRANCH_HALT, 1638 .clkr = { 1639 .enable_reg = 0x3734, 1640 .enable_mask = BIT(0), 1641 .hw.init = &(struct clk_init_data){ 1642 .name = "camss_cphy_csid1_clk", 1643 .parent_hws = (const struct clk_hw *[]){ &camss_csiphy1_clk.clkr.hw }, 1644 .num_parents = 1, 1645 .flags = CLK_SET_RATE_PARENT, 1646 .ops = &clk_branch2_ops, 1647 }, 1648 }, 1649}; 1650 1651static struct clk_branch camss_cphy_csid2_clk = { 1652 .halt_reg = 0x3738, 1653 .halt_check = BRANCH_HALT, 1654 .clkr = { 1655 .enable_reg = 0x3738, 1656 .enable_mask = BIT(0), 1657 .hw.init = &(struct clk_init_data){ 1658 .name = "camss_cphy_csid2_clk", 1659 .parent_hws = (const struct clk_hw *[]){ &camss_csiphy2_clk.clkr.hw }, 1660 .num_parents = 1, 1661 .flags = CLK_SET_RATE_PARENT, 1662 .ops = &clk_branch2_ops, 1663 }, 1664 }, 1665}; 1666 1667static struct clk_branch camss_cphy_csid3_clk = { 1668 .halt_reg = 0x373c, 1669 .halt_check = BRANCH_HALT, 1670 .clkr = { 1671 .enable_reg = 0x373c, 1672 .enable_mask = BIT(0), 1673 .hw.init = &(struct clk_init_data){ 1674 .name = "camss_cphy_csid3_clk", 1675 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, 1676 .num_parents = 1, 1677 .flags = CLK_SET_RATE_PARENT, 1678 .ops = &clk_branch2_ops, 1679 }, 1680 }, 1681}; 1682 1683static struct clk_branch camss_gp0_clk = { 1684 .halt_reg = 0x3444, 1685 .halt_check = BRANCH_HALT, 1686 .clkr = { 1687 .enable_reg = 0x3444, 1688 .enable_mask = BIT(0), 1689 .hw.init = &(struct clk_init_data){ 1690 .name = "camss_gp0_clk", 1691 .parent_hws = (const struct clk_hw *[]){ &camss_gp0_clk_src.clkr.hw }, 1692 .num_parents = 1, 1693 .flags = CLK_SET_RATE_PARENT, 1694 .ops = &clk_branch2_ops, 1695 }, 1696 }, 1697}; 1698 1699static struct clk_branch camss_gp1_clk = { 1700 .halt_reg = 0x3474, 1701 .halt_check = BRANCH_HALT, 1702 .clkr = { 1703 .enable_reg = 0x3474, 1704 .enable_mask = BIT(0), 1705 .hw.init = &(struct clk_init_data){ 1706 .name = "camss_gp1_clk", 1707 .parent_hws = (const struct clk_hw *[]){ &camss_gp1_clk_src.clkr.hw }, 1708 .num_parents = 1, 1709 .flags = CLK_SET_RATE_PARENT, 1710 .ops = &clk_branch2_ops, 1711 }, 1712 }, 1713}; 1714 1715static struct clk_branch camss_ispif_ahb_clk = { 1716 .halt_reg = 0x3224, 1717 .halt_check = BRANCH_HALT, 1718 .clkr = { 1719 .enable_reg = 0x3224, 1720 .enable_mask = BIT(0), 1721 .hw.init = &(struct clk_init_data){ 1722 .name = "camss_ispif_ahb_clk", 1723 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1724 .num_parents = 1, 1725 .ops = &clk_branch2_ops, 1726 }, 1727 }, 1728}; 1729 1730static struct clk_branch camss_jpeg0_clk = { 1731 .halt_reg = 0x35a8, 1732 .halt_check = BRANCH_HALT, 1733 .clkr = { 1734 .enable_reg = 0x35a8, 1735 .enable_mask = BIT(0), 1736 .hw.init = &(struct clk_init_data){ 1737 .name = "camss_jpeg0_clk", 1738 .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw }, 1739 .num_parents = 1, 1740 .flags = CLK_SET_RATE_PARENT, 1741 .ops = &clk_branch2_ops, 1742 }, 1743 }, 1744}; 1745 1746static struct clk_branch camss_jpeg_ahb_clk = { 1747 .halt_reg = 0x35b4, 1748 .halt_check = BRANCH_HALT, 1749 .clkr = { 1750 .enable_reg = 0x35b4, 1751 .enable_mask = BIT(0), 1752 .hw.init = &(struct clk_init_data){ 1753 .name = "camss_jpeg_ahb_clk", 1754 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1755 .num_parents = 1, 1756 .ops = &clk_branch2_ops, 1757 }, 1758 }, 1759}; 1760 1761static struct clk_branch camss_jpeg_axi_clk = { 1762 .halt_reg = 0x35b8, 1763 .halt_check = BRANCH_HALT, 1764 .clkr = { 1765 .enable_reg = 0x35b8, 1766 .enable_mask = BIT(0), 1767 .hw.init = &(struct clk_init_data){ 1768 .name = "camss_jpeg_axi_clk", 1769 .ops = &clk_branch2_ops, 1770 }, 1771 }, 1772}; 1773 1774static struct clk_branch throttle_camss_axi_clk = { 1775 .halt_reg = 0x3c3c, 1776 .halt_check = BRANCH_HALT, 1777 .clkr = { 1778 .enable_reg = 0x3c3c, 1779 .enable_mask = BIT(0), 1780 .hw.init = &(struct clk_init_data){ 1781 .name = "throttle_camss_axi_clk", 1782 .ops = &clk_branch2_ops, 1783 }, 1784 }, 1785}; 1786 1787static struct clk_branch camss_mclk0_clk = { 1788 .halt_reg = 0x3384, 1789 .halt_check = BRANCH_HALT, 1790 .clkr = { 1791 .enable_reg = 0x3384, 1792 .enable_mask = BIT(0), 1793 .hw.init = &(struct clk_init_data){ 1794 .name = "camss_mclk0_clk", 1795 .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw }, 1796 .num_parents = 1, 1797 .flags = CLK_SET_RATE_PARENT, 1798 .ops = &clk_branch2_ops, 1799 }, 1800 }, 1801}; 1802 1803static struct clk_branch camss_mclk1_clk = { 1804 .halt_reg = 0x33b4, 1805 .halt_check = BRANCH_HALT, 1806 .clkr = { 1807 .enable_reg = 0x33b4, 1808 .enable_mask = BIT(0), 1809 .hw.init = &(struct clk_init_data){ 1810 .name = "camss_mclk1_clk", 1811 .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw }, 1812 .num_parents = 1, 1813 .flags = CLK_SET_RATE_PARENT, 1814 .ops = &clk_branch2_ops, 1815 }, 1816 }, 1817}; 1818 1819static struct clk_branch camss_mclk2_clk = { 1820 .halt_reg = 0x33e4, 1821 .halt_check = BRANCH_HALT, 1822 .clkr = { 1823 .enable_reg = 0x33e4, 1824 .enable_mask = BIT(0), 1825 .hw.init = &(struct clk_init_data){ 1826 .name = "camss_mclk2_clk", 1827 .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw }, 1828 .num_parents = 1, 1829 .flags = CLK_SET_RATE_PARENT, 1830 .ops = &clk_branch2_ops, 1831 }, 1832 }, 1833}; 1834 1835static struct clk_branch camss_mclk3_clk = { 1836 .halt_reg = 0x3414, 1837 .halt_check = BRANCH_HALT, 1838 .clkr = { 1839 .enable_reg = 0x3414, 1840 .enable_mask = BIT(0), 1841 .hw.init = &(struct clk_init_data){ 1842 .name = "camss_mclk3_clk", 1843 .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw }, 1844 .num_parents = 1, 1845 .flags = CLK_SET_RATE_PARENT, 1846 .ops = &clk_branch2_ops, 1847 }, 1848 }, 1849}; 1850 1851static struct clk_branch camss_micro_ahb_clk = { 1852 .halt_reg = 0x3494, 1853 .halt_check = BRANCH_HALT, 1854 .clkr = { 1855 .enable_reg = 0x3494, 1856 .enable_mask = BIT(0), 1857 .hw.init = &(struct clk_init_data){ 1858 .name = "camss_micro_ahb_clk", 1859 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1860 .num_parents = 1, 1861 .ops = &clk_branch2_ops, 1862 }, 1863 }, 1864}; 1865 1866static struct clk_branch camss_top_ahb_clk = { 1867 .halt_reg = 0x3484, 1868 .halt_check = BRANCH_HALT, 1869 .clkr = { 1870 .enable_reg = 0x3484, 1871 .enable_mask = BIT(0), 1872 .hw.init = &(struct clk_init_data){ 1873 .name = "camss_top_ahb_clk", 1874 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1875 .num_parents = 1, 1876 .ops = &clk_branch2_ops, 1877 }, 1878 }, 1879}; 1880 1881static struct clk_branch camss_vfe0_ahb_clk = { 1882 .halt_reg = 0x3668, 1883 .halt_check = BRANCH_HALT, 1884 .clkr = { 1885 .enable_reg = 0x3668, 1886 .enable_mask = BIT(0), 1887 .hw.init = &(struct clk_init_data){ 1888 .name = "camss_vfe0_ahb_clk", 1889 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1890 .num_parents = 1, 1891 .ops = &clk_branch2_ops, 1892 }, 1893 }, 1894}; 1895 1896static struct clk_branch camss_vfe0_clk = { 1897 .halt_reg = 0x36a8, 1898 .halt_check = BRANCH_HALT, 1899 .clkr = { 1900 .enable_reg = 0x36a8, 1901 .enable_mask = BIT(0), 1902 .hw.init = &(struct clk_init_data){ 1903 .name = "camss_vfe0_clk", 1904 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw }, 1905 .num_parents = 1, 1906 .flags = CLK_SET_RATE_PARENT, 1907 .ops = &clk_branch2_ops, 1908 }, 1909 }, 1910}; 1911 1912static struct clk_branch camss_vfe0_stream_clk = { 1913 .halt_reg = 0x3720, 1914 .halt_check = BRANCH_HALT, 1915 .clkr = { 1916 .enable_reg = 0x3720, 1917 .enable_mask = BIT(0), 1918 .hw.init = &(struct clk_init_data){ 1919 .name = "camss_vfe0_stream_clk", 1920 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw }, 1921 .num_parents = 1, 1922 .ops = &clk_branch2_ops, 1923 }, 1924 }, 1925}; 1926 1927static struct clk_branch camss_vfe1_ahb_clk = { 1928 .halt_reg = 0x3678, 1929 .halt_check = BRANCH_HALT, 1930 .clkr = { 1931 .enable_reg = 0x3678, 1932 .enable_mask = BIT(0), 1933 .hw.init = &(struct clk_init_data){ 1934 .name = "camss_vfe1_ahb_clk", 1935 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1936 .num_parents = 1, 1937 .ops = &clk_branch2_ops, 1938 }, 1939 }, 1940}; 1941 1942static struct clk_branch camss_vfe1_clk = { 1943 .halt_reg = 0x36ac, 1944 .halt_check = BRANCH_HALT, 1945 .clkr = { 1946 .enable_reg = 0x36ac, 1947 .enable_mask = BIT(0), 1948 .hw.init = &(struct clk_init_data){ 1949 .name = "camss_vfe1_clk", 1950 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw }, 1951 .num_parents = 1, 1952 .flags = CLK_SET_RATE_PARENT, 1953 .ops = &clk_branch2_ops, 1954 }, 1955 }, 1956}; 1957 1958static struct clk_branch camss_vfe1_stream_clk = { 1959 .halt_reg = 0x3724, 1960 .halt_check = BRANCH_HALT, 1961 .clkr = { 1962 .enable_reg = 0x3724, 1963 .enable_mask = BIT(0), 1964 .hw.init = &(struct clk_init_data){ 1965 .name = "camss_vfe1_stream_clk", 1966 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw }, 1967 .num_parents = 1, 1968 .ops = &clk_branch2_ops, 1969 }, 1970 }, 1971}; 1972 1973static struct clk_branch camss_vfe_vbif_ahb_clk = { 1974 .halt_reg = 0x36b8, 1975 .halt_check = BRANCH_HALT, 1976 .clkr = { 1977 .enable_reg = 0x36b8, 1978 .enable_mask = BIT(0), 1979 .hw.init = &(struct clk_init_data){ 1980 .name = "camss_vfe_vbif_ahb_clk", 1981 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1982 .num_parents = 1, 1983 .ops = &clk_branch2_ops, 1984 }, 1985 }, 1986}; 1987 1988static struct clk_branch camss_vfe_vbif_axi_clk = { 1989 .halt_reg = 0x36bc, 1990 .halt_check = BRANCH_HALT, 1991 .clkr = { 1992 .enable_reg = 0x36bc, 1993 .enable_mask = BIT(0), 1994 .hw.init = &(struct clk_init_data){ 1995 .name = "camss_vfe_vbif_axi_clk", 1996 .ops = &clk_branch2_ops, 1997 }, 1998 }, 1999}; 2000 2001static struct clk_branch csiphy_ahb2crif_clk = { 2002 .halt_reg = 0x374c, 2003 .halt_check = BRANCH_HALT, 2004 .hwcg_reg = 0x374c, 2005 .hwcg_bit = 1, 2006 .clkr = { 2007 .enable_reg = 0x374c, 2008 .enable_mask = BIT(0), 2009 .hw.init = &(struct clk_init_data){ 2010 .name = "csiphy_ahb2crif_clk", 2011 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2012 .num_parents = 1, 2013 .ops = &clk_branch2_ops, 2014 }, 2015 }, 2016}; 2017 2018static struct clk_branch mdss_ahb_clk = { 2019 .halt_reg = 0x2308, 2020 .halt_check = BRANCH_HALT, 2021 .hwcg_reg = 0x8a004, 2022 .hwcg_bit = 1, 2023 .clkr = { 2024 .enable_reg = 0x2308, 2025 .enable_mask = BIT(0), 2026 .hw.init = &(struct clk_init_data){ 2027 .name = "mdss_ahb_clk", 2028 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2029 .flags = CLK_SET_RATE_PARENT, 2030 .num_parents = 1, 2031 .ops = &clk_branch2_ops, 2032 }, 2033 }, 2034}; 2035 2036static const struct freq_tbl ftbl_axi_clk_src[] = { 2037 F(75000000, P_GPLL0, 8, 0, 0), 2038 F(171428571, P_GPLL0, 3.5, 0, 0), 2039 F(240000000, P_GPLL0, 2.5, 0, 0), 2040 F(323200000, P_MMPLL0, 2.5, 0, 0), 2041 F(406000000, P_MMPLL0, 2, 0, 0), 2042 { } 2043}; 2044 2045/* RO to linux */ 2046static struct clk_rcg2 axi_clk_src = { 2047 .cmd_rcgr = 0xd000, 2048 .hid_width = 5, 2049 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 2050 .freq_tbl = ftbl_axi_clk_src, 2051 .clkr.hw.init = &(struct clk_init_data){ 2052 .name = "axi_clk_src", 2053 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 2054 .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 2055 .ops = &clk_rcg2_ops, 2056 }, 2057}; 2058 2059static struct clk_branch mdss_axi_clk = { 2060 .halt_reg = 0x2310, 2061 .halt_check = BRANCH_HALT, 2062 .clkr = { 2063 .enable_reg = 0x2310, 2064 .enable_mask = BIT(0), 2065 .hw.init = &(struct clk_init_data){ 2066 .name = "mdss_axi_clk", 2067 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw }, 2068 .ops = &clk_branch2_ops, 2069 }, 2070 }, 2071}; 2072 2073static struct clk_branch throttle_mdss_axi_clk = { 2074 .halt_reg = 0x246c, 2075 .halt_check = BRANCH_HALT, 2076 .hwcg_reg = 0x246c, 2077 .hwcg_bit = 1, 2078 .clkr = { 2079 .enable_reg = 0x246c, 2080 .enable_mask = BIT(0), 2081 .hw.init = &(struct clk_init_data){ 2082 .name = "throttle_mdss_axi_clk", 2083 .ops = &clk_branch2_ops, 2084 }, 2085 }, 2086}; 2087 2088static struct clk_branch mdss_byte0_clk = { 2089 .halt_reg = 0x233c, 2090 .halt_check = BRANCH_HALT, 2091 .clkr = { 2092 .enable_reg = 0x233c, 2093 .enable_mask = BIT(0), 2094 .hw.init = &(struct clk_init_data){ 2095 .name = "mdss_byte0_clk", 2096 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw }, 2097 .num_parents = 1, 2098 .flags = CLK_SET_RATE_PARENT, 2099 .ops = &clk_branch2_ops, 2100 }, 2101 }, 2102}; 2103 2104static struct clk_regmap_div mdss_byte0_intf_div_clk = { 2105 .reg = 0x237c, 2106 .shift = 0, 2107 .width = 2, 2108 /* 2109 * NOTE: Op does not work for div-3. Current assumption is that div-3 2110 * is not a recommended setting for this divider. 2111 */ 2112 .clkr = { 2113 .hw.init = &(struct clk_init_data){ 2114 .name = "mdss_byte0_intf_div_clk", 2115 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw }, 2116 .num_parents = 1, 2117 .ops = &clk_regmap_div_ops, 2118 .flags = CLK_GET_RATE_NOCACHE, 2119 }, 2120 }, 2121}; 2122 2123static struct clk_branch mdss_byte0_intf_clk = { 2124 .halt_reg = 0x2374, 2125 .halt_check = BRANCH_HALT, 2126 .clkr = { 2127 .enable_reg = 0x2374, 2128 .enable_mask = BIT(0), 2129 .hw.init = &(struct clk_init_data){ 2130 .name = "mdss_byte0_intf_clk", 2131 .parent_hws = (const struct clk_hw *[]){ &mdss_byte0_intf_div_clk.clkr.hw }, 2132 .num_parents = 1, 2133 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 2134 .ops = &clk_branch2_ops, 2135 }, 2136 }, 2137}; 2138 2139static struct clk_branch mdss_byte1_clk = { 2140 .halt_reg = 0x2340, 2141 .halt_check = BRANCH_HALT, 2142 .clkr = { 2143 .enable_reg = 0x2340, 2144 .enable_mask = BIT(0), 2145 .hw.init = &(struct clk_init_data){ 2146 .name = "mdss_byte1_clk", 2147 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw }, 2148 .num_parents = 1, 2149 .flags = CLK_SET_RATE_PARENT, 2150 .ops = &clk_branch2_ops, 2151 }, 2152 }, 2153}; 2154 2155static struct clk_regmap_div mdss_byte1_intf_div_clk = { 2156 .reg = 0x2380, 2157 .shift = 0, 2158 .width = 2, 2159 /* 2160 * NOTE: Op does not work for div-3. Current assumption is that div-3 2161 * is not a recommended setting for this divider. 2162 */ 2163 .clkr = { 2164 .hw.init = &(struct clk_init_data){ 2165 .name = "mdss_byte1_intf_div_clk", 2166 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw }, 2167 .num_parents = 1, 2168 .ops = &clk_regmap_div_ops, 2169 .flags = CLK_GET_RATE_NOCACHE, 2170 }, 2171 }, 2172}; 2173 2174static struct clk_branch mdss_byte1_intf_clk = { 2175 .halt_reg = 0x2378, 2176 .halt_check = BRANCH_HALT, 2177 .clkr = { 2178 .enable_reg = 0x2378, 2179 .enable_mask = BIT(0), 2180 .hw.init = &(struct clk_init_data){ 2181 .name = "mdss_byte1_intf_clk", 2182 .parent_hws = (const struct clk_hw *[]){ &mdss_byte1_intf_div_clk.clkr.hw }, 2183 .num_parents = 1, 2184 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 2185 .ops = &clk_branch2_ops, 2186 }, 2187 }, 2188}; 2189 2190static struct clk_branch mdss_dp_aux_clk = { 2191 .halt_reg = 0x2364, 2192 .halt_check = BRANCH_HALT, 2193 .clkr = { 2194 .enable_reg = 0x2364, 2195 .enable_mask = BIT(0), 2196 .hw.init = &(struct clk_init_data){ 2197 .name = "mdss_dp_aux_clk", 2198 .parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw }, 2199 .num_parents = 1, 2200 .flags = CLK_SET_RATE_PARENT, 2201 .ops = &clk_branch2_ops, 2202 }, 2203 }, 2204}; 2205 2206static struct clk_branch mdss_dp_crypto_clk = { 2207 .halt_reg = 0x235c, 2208 .halt_check = BRANCH_HALT, 2209 .clkr = { 2210 .enable_reg = 0x235c, 2211 .enable_mask = BIT(0), 2212 .hw.init = &(struct clk_init_data){ 2213 .name = "mdss_dp_crypto_clk", 2214 .parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw }, 2215 .num_parents = 1, 2216 .flags = CLK_SET_RATE_PARENT, 2217 .ops = &clk_branch2_ops, 2218 }, 2219 }, 2220}; 2221 2222static struct clk_branch mdss_dp_gtc_clk = { 2223 .halt_reg = 0x2368, 2224 .halt_check = BRANCH_HALT, 2225 .clkr = { 2226 .enable_reg = 0x2368, 2227 .enable_mask = BIT(0), 2228 .hw.init = &(struct clk_init_data){ 2229 .name = "mdss_dp_gtc_clk", 2230 .parent_hws = (const struct clk_hw *[]){ &dp_gtc_clk_src.clkr.hw }, 2231 .num_parents = 1, 2232 .flags = CLK_SET_RATE_PARENT, 2233 .ops = &clk_branch2_ops, 2234 }, 2235 }, 2236}; 2237 2238static struct clk_branch mdss_dp_link_clk = { 2239 .halt_reg = 0x2354, 2240 .halt_check = BRANCH_HALT, 2241 .clkr = { 2242 .enable_reg = 0x2354, 2243 .enable_mask = BIT(0), 2244 .hw.init = &(struct clk_init_data){ 2245 .name = "mdss_dp_link_clk", 2246 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw }, 2247 .num_parents = 1, 2248 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 2249 .ops = &clk_branch2_ops, 2250 }, 2251 }, 2252}; 2253 2254/* Reset state of MDSS_DP_LINK_INTF_DIV is 0x3 (div-4) */ 2255static struct clk_branch mdss_dp_link_intf_clk = { 2256 .halt_reg = 0x2358, 2257 .halt_check = BRANCH_HALT, 2258 .clkr = { 2259 .enable_reg = 0x2358, 2260 .enable_mask = BIT(0), 2261 .hw.init = &(struct clk_init_data){ 2262 .name = "mdss_dp_link_intf_clk", 2263 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw }, 2264 .num_parents = 1, 2265 .ops = &clk_branch2_ops, 2266 }, 2267 }, 2268}; 2269 2270static struct clk_branch mdss_dp_pixel_clk = { 2271 .halt_reg = 0x2360, 2272 .halt_check = BRANCH_HALT, 2273 .clkr = { 2274 .enable_reg = 0x2360, 2275 .enable_mask = BIT(0), 2276 .hw.init = &(struct clk_init_data){ 2277 .name = "mdss_dp_pixel_clk", 2278 .parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw }, 2279 .num_parents = 1, 2280 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 2281 .ops = &clk_branch2_ops, 2282 }, 2283 }, 2284}; 2285 2286static struct clk_branch mdss_esc0_clk = { 2287 .halt_reg = 0x2344, 2288 .halt_check = BRANCH_HALT, 2289 .clkr = { 2290 .enable_reg = 0x2344, 2291 .enable_mask = BIT(0), 2292 .hw.init = &(struct clk_init_data){ 2293 .name = "mdss_esc0_clk", 2294 .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw }, 2295 .num_parents = 1, 2296 .flags = CLK_SET_RATE_PARENT, 2297 .ops = &clk_branch2_ops, 2298 }, 2299 }, 2300}; 2301 2302static struct clk_branch mdss_esc1_clk = { 2303 .halt_reg = 0x2348, 2304 .halt_check = BRANCH_HALT, 2305 .clkr = { 2306 .enable_reg = 0x2348, 2307 .enable_mask = BIT(0), 2308 .hw.init = &(struct clk_init_data){ 2309 .name = "mdss_esc1_clk", 2310 .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw }, 2311 .num_parents = 1, 2312 .flags = CLK_SET_RATE_PARENT, 2313 .ops = &clk_branch2_ops, 2314 }, 2315 }, 2316}; 2317 2318static struct clk_branch mdss_hdmi_dp_ahb_clk = { 2319 .halt_reg = 0x230c, 2320 .halt_check = BRANCH_HALT, 2321 .clkr = { 2322 .enable_reg = 0x230c, 2323 .enable_mask = BIT(0), 2324 .hw.init = &(struct clk_init_data){ 2325 .name = "mdss_hdmi_dp_ahb_clk", 2326 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2327 .num_parents = 1, 2328 .ops = &clk_branch2_ops, 2329 }, 2330 }, 2331}; 2332 2333static struct clk_branch mdss_mdp_clk = { 2334 .halt_reg = 0x231c, 2335 .halt_check = BRANCH_HALT, 2336 .clkr = { 2337 .enable_reg = 0x231c, 2338 .enable_mask = BIT(0), 2339 .hw.init = &(struct clk_init_data){ 2340 .name = "mdss_mdp_clk", 2341 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw }, 2342 .num_parents = 1, 2343 .flags = CLK_SET_RATE_PARENT, 2344 .ops = &clk_branch2_ops, 2345 }, 2346 }, 2347}; 2348 2349static struct clk_branch mdss_pclk0_clk = { 2350 .halt_reg = 0x2314, 2351 .halt_check = BRANCH_HALT, 2352 .clkr = { 2353 .enable_reg = 0x2314, 2354 .enable_mask = BIT(0), 2355 .hw.init = &(struct clk_init_data){ 2356 .name = "mdss_pclk0_clk", 2357 .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw }, 2358 .num_parents = 1, 2359 .flags = CLK_SET_RATE_PARENT, 2360 .ops = &clk_branch2_ops, 2361 }, 2362 }, 2363}; 2364 2365static struct clk_branch mdss_pclk1_clk = { 2366 .halt_reg = 0x2318, 2367 .halt_check = BRANCH_HALT, 2368 .clkr = { 2369 .enable_reg = 0x2318, 2370 .enable_mask = BIT(0), 2371 .hw.init = &(struct clk_init_data){ 2372 .name = "mdss_pclk1_clk", 2373 .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw }, 2374 .num_parents = 1, 2375 .flags = CLK_SET_RATE_PARENT, 2376 .ops = &clk_branch2_ops, 2377 }, 2378 }, 2379}; 2380 2381static struct clk_branch mdss_rot_clk = { 2382 .halt_reg = 0x2350, 2383 .halt_check = BRANCH_HALT, 2384 .clkr = { 2385 .enable_reg = 0x2350, 2386 .enable_mask = BIT(0), 2387 .hw.init = &(struct clk_init_data){ 2388 .name = "mdss_rot_clk", 2389 .parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw }, 2390 .num_parents = 1, 2391 .flags = CLK_SET_RATE_PARENT, 2392 .ops = &clk_branch2_ops, 2393 }, 2394 }, 2395}; 2396 2397static struct clk_branch mdss_vsync_clk = { 2398 .halt_reg = 0x2328, 2399 .halt_check = BRANCH_HALT, 2400 .clkr = { 2401 .enable_reg = 0x2328, 2402 .enable_mask = BIT(0), 2403 .hw.init = &(struct clk_init_data){ 2404 .name = "mdss_vsync_clk", 2405 .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw }, 2406 .num_parents = 1, 2407 .flags = CLK_SET_RATE_PARENT, 2408 .ops = &clk_branch2_ops, 2409 }, 2410 }, 2411}; 2412 2413static struct clk_branch mnoc_ahb_clk = { 2414 .halt_reg = 0x5024, 2415 .halt_check = BRANCH_VOTED, 2416 .clkr = { 2417 .enable_reg = 0x5024, 2418 .enable_mask = BIT(0), 2419 .hw.init = &(struct clk_init_data){ 2420 .name = "mnoc_ahb_clk", 2421 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2422 .num_parents = 1, 2423 .flags = CLK_SET_RATE_PARENT, 2424 .ops = &clk_branch2_ops, 2425 }, 2426 }, 2427}; 2428 2429static struct clk_branch misc_ahb_clk = { 2430 .halt_reg = 0x328, 2431 .halt_check = BRANCH_HALT, 2432 .hwcg_reg = 0x328, 2433 .hwcg_bit = 1, 2434 .clkr = { 2435 .enable_reg = 0x328, 2436 .enable_mask = BIT(0), 2437 .hw.init = &(struct clk_init_data){ 2438 .name = "misc_ahb_clk", 2439 /* 2440 * Dependency to be enabled before the branch is 2441 * enabled. 2442 */ 2443 .parent_hws = (const struct clk_hw *[]){ &mnoc_ahb_clk.clkr.hw }, 2444 .num_parents = 1, 2445 .ops = &clk_branch2_ops, 2446 }, 2447 }, 2448}; 2449 2450static struct clk_branch misc_cxo_clk = { 2451 .halt_reg = 0x324, 2452 .halt_check = BRANCH_HALT, 2453 .clkr = { 2454 .enable_reg = 0x324, 2455 .enable_mask = BIT(0), 2456 .hw.init = &(struct clk_init_data){ 2457 .name = "misc_cxo_clk", 2458 .parent_data = &(const struct clk_parent_data){ 2459 .fw_name = "xo", 2460 }, 2461 .num_parents = 1, 2462 .ops = &clk_branch2_ops, 2463 }, 2464 }, 2465}; 2466 2467static struct clk_branch snoc_dvm_axi_clk = { 2468 .halt_reg = 0xe040, 2469 .halt_check = BRANCH_HALT, 2470 .clkr = { 2471 .enable_reg = 0xe040, 2472 .enable_mask = BIT(0), 2473 .hw.init = &(struct clk_init_data){ 2474 .name = "snoc_dvm_axi_clk", 2475 .ops = &clk_branch2_ops, 2476 }, 2477 }, 2478}; 2479 2480static struct clk_branch video_ahb_clk = { 2481 .halt_reg = 0x1030, 2482 .halt_check = BRANCH_HALT, 2483 .hwcg_reg = 0x1030, 2484 .hwcg_bit = 1, 2485 .clkr = { 2486 .enable_reg = 0x1030, 2487 .enable_mask = BIT(0), 2488 .hw.init = &(struct clk_init_data){ 2489 .name = "video_ahb_clk", 2490 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2491 .num_parents = 1, 2492 .ops = &clk_branch2_ops, 2493 }, 2494 }, 2495}; 2496 2497static struct clk_branch video_axi_clk = { 2498 .halt_reg = 0x1034, 2499 .halt_check = BRANCH_HALT, 2500 .clkr = { 2501 .enable_reg = 0x1034, 2502 .enable_mask = BIT(0), 2503 .hw.init = &(struct clk_init_data){ 2504 .name = "video_axi_clk", 2505 .ops = &clk_branch2_ops, 2506 }, 2507 }, 2508}; 2509 2510static struct clk_branch throttle_video_axi_clk = { 2511 .halt_reg = 0x118c, 2512 .halt_check = BRANCH_HALT, 2513 .hwcg_reg = 0x118c, 2514 .hwcg_bit = 1, 2515 .clkr = { 2516 .enable_reg = 0x118c, 2517 .enable_mask = BIT(0), 2518 .hw.init = &(struct clk_init_data){ 2519 .name = "throttle_video_axi_clk", 2520 .ops = &clk_branch2_ops, 2521 }, 2522 }, 2523}; 2524 2525static struct clk_branch video_core_clk = { 2526 .halt_reg = 0x1028, 2527 .halt_check = BRANCH_HALT, 2528 .clkr = { 2529 .enable_reg = 0x1028, 2530 .enable_mask = BIT(0), 2531 .hw.init = &(struct clk_init_data){ 2532 .name = "video_core_clk", 2533 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw }, 2534 .num_parents = 1, 2535 .flags = CLK_SET_RATE_PARENT, 2536 .ops = &clk_branch2_ops, 2537 }, 2538 }, 2539}; 2540 2541static struct clk_branch video_subcore0_clk = { 2542 .halt_reg = 0x1048, 2543 .halt_check = BRANCH_HALT_SKIP, 2544 .clkr = { 2545 .enable_reg = 0x1048, 2546 .enable_mask = BIT(0), 2547 .hw.init = &(struct clk_init_data){ 2548 .name = "video_subcore0_clk", 2549 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw }, 2550 .num_parents = 1, 2551 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 2552 .ops = &clk_branch2_ops, 2553 }, 2554 }, 2555}; 2556 2557static struct gdsc venus_gdsc = { 2558 .gdscr = 0x1024, 2559 .cxcs = (unsigned int[]){ 0x1028, 0x1034, 0x1048 }, 2560 .cxc_count = 3, 2561 .pd = { 2562 .name = "venus", 2563 }, 2564 .pwrsts = PWRSTS_OFF_ON, 2565}; 2566 2567static struct gdsc venus_core0_gdsc = { 2568 .gdscr = 0x1040, 2569 .pd = { 2570 .name = "venus_core0", 2571 }, 2572 .parent = &venus_gdsc.pd, 2573 .pwrsts = PWRSTS_OFF_ON, 2574 .flags = HW_CTRL, 2575}; 2576 2577static struct gdsc mdss_gdsc = { 2578 .gdscr = 0x2304, 2579 .pd = { 2580 .name = "mdss", 2581 }, 2582 .cxcs = (unsigned int []){ 0x2040 }, 2583 .cxc_count = 1, 2584 .pwrsts = PWRSTS_OFF_ON, 2585}; 2586 2587static struct gdsc camss_top_gdsc = { 2588 .gdscr = 0x34a0, 2589 .pd = { 2590 .name = "camss_top", 2591 }, 2592 .pwrsts = PWRSTS_OFF_ON, 2593}; 2594 2595static struct gdsc camss_vfe0_gdsc = { 2596 .gdscr = 0x3664, 2597 .pd = { 2598 .name = "camss_vfe0", 2599 }, 2600 .parent = &camss_top_gdsc.pd, 2601 .pwrsts = PWRSTS_OFF_ON, 2602}; 2603 2604static struct gdsc camss_vfe1_gdsc = { 2605 .gdscr = 0x3674, 2606 .pd = { 2607 .name = "camss_vfe1_gdsc", 2608 }, 2609 .parent = &camss_top_gdsc.pd, 2610 .pwrsts = PWRSTS_OFF_ON, 2611}; 2612 2613static struct gdsc camss_cpp_gdsc = { 2614 .gdscr = 0x36d4, 2615 .pd = { 2616 .name = "camss_cpp", 2617 }, 2618 .parent = &camss_top_gdsc.pd, 2619 .pwrsts = PWRSTS_OFF_ON, 2620}; 2621 2622/* This GDSC seems to hang the whole multimedia subsystem. 2623static struct gdsc bimc_smmu_gdsc = { 2624 .gdscr = 0xe020, 2625 .gds_hw_ctrl = 0xe024, 2626 .pd = { 2627 .name = "bimc_smmu", 2628 }, 2629 .pwrsts = PWRSTS_OFF_ON, 2630 .parent = &bimc_smmu_gdsc.pd, 2631 .flags = HW_CTRL, 2632}; 2633*/ 2634 2635static struct clk_regmap *mmcc_660_clocks[] = { 2636 [AHB_CLK_SRC] = &ahb_clk_src.clkr, 2637 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 2638 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, 2639 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 2640 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 2641 [CCI_CLK_SRC] = &cci_clk_src.clkr, 2642 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 2643 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 2644 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 2645 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 2646 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 2647 [CSI2_CLK_SRC] = &csi2_clk_src.clkr, 2648 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, 2649 [CSI3_CLK_SRC] = &csi3_clk_src.clkr, 2650 [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr, 2651 [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr, 2652 [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr, 2653 [DP_GTC_CLK_SRC] = &dp_gtc_clk_src.clkr, 2654 [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr, 2655 [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr, 2656 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 2657 [ESC1_CLK_SRC] = &esc1_clk_src.clkr, 2658 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 2659 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 2660 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 2661 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, 2662 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, 2663 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 2664 [MMPLL0_PLL] = &mmpll0.clkr, 2665 [MMPLL10_PLL] = &mmpll10.clkr, 2666 [MMPLL3_PLL] = &mmpll3.clkr, 2667 [MMPLL4_PLL] = &mmpll4.clkr, 2668 [MMPLL5_PLL] = &mmpll5.clkr, 2669 [MMPLL6_PLL] = &mmpll6.clkr, 2670 [MMPLL7_PLL] = &mmpll7.clkr, 2671 [MMPLL8_PLL] = &mmpll8.clkr, 2672 [BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr, 2673 [BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr, 2674 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr, 2675 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr, 2676 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr, 2677 [CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr, 2678 [CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr, 2679 [CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr, 2680 [CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr, 2681 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr, 2682 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr, 2683 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr, 2684 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr, 2685 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, 2686 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, 2687 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr, 2688 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, 2689 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, 2690 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, 2691 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, 2692 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr, 2693 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, 2694 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, 2695 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, 2696 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, 2697 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr, 2698 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, 2699 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, 2700 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, 2701 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, 2702 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, 2703 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, 2704 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, 2705 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, 2706 [CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr, 2707 [CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr, 2708 [CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr, 2709 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, 2710 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, 2711 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, 2712 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr, 2713 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr, 2714 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr, 2715 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, 2716 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, 2717 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, 2718 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, 2719 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, 2720 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, 2721 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr, 2722 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr, 2723 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr, 2724 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr, 2725 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr, 2726 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr, 2727 [CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr, 2728 [CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr, 2729 [CSIPHY_AHB2CRIF_CLK] = &csiphy_ahb2crif_clk.clkr, 2730 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, 2731 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, 2732 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, 2733 [MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr, 2734 [MDSS_BYTE0_INTF_DIV_CLK] = &mdss_byte0_intf_div_clk.clkr, 2735 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, 2736 [MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr, 2737 [MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr, 2738 [MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr, 2739 [MDSS_DP_GTC_CLK] = &mdss_dp_gtc_clk.clkr, 2740 [MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr, 2741 [MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr, 2742 [MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr, 2743 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, 2744 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, 2745 [MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr, 2746 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, 2747 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, 2748 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, 2749 [MDSS_ROT_CLK] = &mdss_rot_clk.clkr, 2750 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, 2751 [MISC_AHB_CLK] = &misc_ahb_clk.clkr, 2752 [MISC_CXO_CLK] = &misc_cxo_clk.clkr, 2753 [MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr, 2754 [SNOC_DVM_AXI_CLK] = &snoc_dvm_axi_clk.clkr, 2755 [THROTTLE_CAMSS_AXI_CLK] = &throttle_camss_axi_clk.clkr, 2756 [THROTTLE_MDSS_AXI_CLK] = &throttle_mdss_axi_clk.clkr, 2757 [THROTTLE_VIDEO_AXI_CLK] = &throttle_video_axi_clk.clkr, 2758 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr, 2759 [VIDEO_AXI_CLK] = &video_axi_clk.clkr, 2760 [VIDEO_CORE_CLK] = &video_core_clk.clkr, 2761 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr, 2762 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 2763 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, 2764 [ROT_CLK_SRC] = &rot_clk_src.clkr, 2765 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 2766 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, 2767 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, 2768 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 2769 [MDSS_BYTE1_INTF_DIV_CLK] = &mdss_byte1_intf_div_clk.clkr, 2770 [AXI_CLK_SRC] = &axi_clk_src.clkr, 2771}; 2772 2773static struct gdsc *mmcc_sdm660_gdscs[] = { 2774 [VENUS_GDSC] = &venus_gdsc, 2775 [VENUS_CORE0_GDSC] = &venus_core0_gdsc, 2776 [MDSS_GDSC] = &mdss_gdsc, 2777 [CAMSS_TOP_GDSC] = &camss_top_gdsc, 2778 [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc, 2779 [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc, 2780 [CAMSS_CPP_GDSC] = &camss_cpp_gdsc, 2781}; 2782 2783static const struct qcom_reset_map mmcc_660_resets[] = { 2784 [MDSS_BCR] = { 0x2300 }, 2785 [CAMSS_MICRO_BCR] = { 0x3490 }, 2786}; 2787 2788static const struct regmap_config mmcc_660_regmap_config = { 2789 .reg_bits = 32, 2790 .reg_stride = 4, 2791 .val_bits = 32, 2792 .max_register = 0x40000, 2793 .fast_io = true, 2794}; 2795 2796static const struct qcom_cc_desc mmcc_660_desc = { 2797 .config = &mmcc_660_regmap_config, 2798 .clks = mmcc_660_clocks, 2799 .num_clks = ARRAY_SIZE(mmcc_660_clocks), 2800 .resets = mmcc_660_resets, 2801 .num_resets = ARRAY_SIZE(mmcc_660_resets), 2802 .gdscs = mmcc_sdm660_gdscs, 2803 .num_gdscs = ARRAY_SIZE(mmcc_sdm660_gdscs), 2804}; 2805 2806static const struct of_device_id mmcc_660_match_table[] = { 2807 { .compatible = "qcom,mmcc-sdm660" }, 2808 { .compatible = "qcom,mmcc-sdm630", .data = (void *)1UL }, 2809 { } 2810}; 2811MODULE_DEVICE_TABLE(of, mmcc_660_match_table); 2812 2813static void sdm630_clock_override(void) 2814{ 2815 /* SDM630 has only one DSI */ 2816 mmcc_660_desc.clks[BYTE1_CLK_SRC] = NULL; 2817 mmcc_660_desc.clks[MDSS_BYTE1_CLK] = NULL; 2818 mmcc_660_desc.clks[MDSS_BYTE1_INTF_DIV_CLK] = NULL; 2819 mmcc_660_desc.clks[MDSS_BYTE1_INTF_CLK] = NULL; 2820 mmcc_660_desc.clks[ESC1_CLK_SRC] = NULL; 2821 mmcc_660_desc.clks[MDSS_ESC1_CLK] = NULL; 2822 mmcc_660_desc.clks[PCLK1_CLK_SRC] = NULL; 2823 mmcc_660_desc.clks[MDSS_PCLK1_CLK] = NULL; 2824} 2825 2826static int mmcc_660_probe(struct platform_device *pdev) 2827{ 2828 struct regmap *regmap; 2829 bool is_sdm630; 2830 2831 is_sdm630 = !!device_get_match_data(&pdev->dev); 2832 2833 regmap = qcom_cc_map(pdev, &mmcc_660_desc); 2834 if (IS_ERR(regmap)) 2835 return PTR_ERR(regmap); 2836 2837 if (is_sdm630) 2838 sdm630_clock_override(); 2839 2840 clk_alpha_pll_configure(&mmpll3, regmap, &mmpll3_config); 2841 clk_alpha_pll_configure(&mmpll4, regmap, &mmpll4_config); 2842 clk_alpha_pll_configure(&mmpll5, regmap, &mmpll5_config); 2843 clk_alpha_pll_configure(&mmpll7, regmap, &mmpll7_config); 2844 clk_alpha_pll_configure(&mmpll8, regmap, &mmpll8_config); 2845 clk_alpha_pll_configure(&mmpll10, regmap, &mmpll10_config); 2846 2847 return qcom_cc_really_probe(&pdev->dev, &mmcc_660_desc, regmap); 2848} 2849 2850static struct platform_driver mmcc_660_driver = { 2851 .probe = mmcc_660_probe, 2852 .driver = { 2853 .name = "mmcc-sdm660", 2854 .of_match_table = mmcc_660_match_table, 2855 }, 2856}; 2857module_platform_driver(mmcc_660_driver); 2858 2859MODULE_DESCRIPTION("Qualcomm SDM630/SDM660 MMCC driver"); 2860MODULE_LICENSE("GPL v2");
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