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mmcc-msm8998.c
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linux-6.19.14/drivers/clk/qcom/mmcc-msm8998.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/kernel.h> 7#include <linux/bitops.h> 8#include <linux/err.h> 9#include <linux/platform_device.h> 10#include <linux/mod_devicetable.h> 11#include <linux/module.h> 12#include <linux/clk-provider.h> 13#include <linux/regmap.h> 14 15#include <dt-bindings/clock/qcom,mmcc-msm8998.h> 16 17#include "common.h" 18#include "clk-regmap.h" 19#include "clk-regmap-divider.h" 20#include "clk-alpha-pll.h" 21#include "clk-rcg.h" 22#include "clk-branch.h" 23#include "reset.h" 24#include "gdsc.h" 25 26enum { 27 P_XO, 28 P_GPLL0, 29 P_GPLL0_DIV, 30 P_MMPLL0_OUT_EVEN, 31 P_MMPLL1_OUT_EVEN, 32 P_MMPLL3_OUT_EVEN, 33 P_MMPLL4_OUT_EVEN, 34 P_MMPLL5_OUT_EVEN, 35 P_MMPLL6_OUT_EVEN, 36 P_MMPLL7_OUT_EVEN, 37 P_MMPLL10_OUT_EVEN, 38 P_DSI0PLL, 39 P_DSI1PLL, 40 P_DSI0PLL_BYTE, 41 P_DSI1PLL_BYTE, 42 P_HDMIPLL, 43 P_DPVCO, 44 P_DPLINK, 45}; 46 47static const struct clk_div_table post_div_table_fabia_even[] = { 48 { 0x0, 1 }, 49 { 0x1, 2 }, 50 { 0x3, 4 }, 51 { 0x7, 8 }, 52 { } 53}; 54 55static struct clk_alpha_pll mmpll0 = { 56 .offset = 0xc000, 57 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 58 .clkr = { 59 .enable_reg = 0x1e0, 60 .enable_mask = BIT(0), 61 .hw.init = &(struct clk_init_data){ 62 .name = "mmpll0", 63 .parent_data = &(const struct clk_parent_data){ 64 .fw_name = "xo" 65 }, 66 .num_parents = 1, 67 .ops = &clk_alpha_pll_fixed_fabia_ops, 68 }, 69 }, 70}; 71 72static struct clk_alpha_pll_postdiv mmpll0_out_even = { 73 .offset = 0xc000, 74 .post_div_shift = 8, 75 .post_div_table = post_div_table_fabia_even, 76 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 77 .width = 4, 78 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 79 .clkr.hw.init = &(struct clk_init_data){ 80 .name = "mmpll0_out_even", 81 .parent_hws = (const struct clk_hw *[]){ &mmpll0.clkr.hw }, 82 .num_parents = 1, 83 .ops = &clk_alpha_pll_postdiv_fabia_ops, 84 }, 85}; 86 87static struct clk_alpha_pll mmpll1 = { 88 .offset = 0xc050, 89 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 90 .clkr = { 91 .enable_reg = 0x1e0, 92 .enable_mask = BIT(1), 93 .hw.init = &(struct clk_init_data){ 94 .name = "mmpll1", 95 .parent_data = &(const struct clk_parent_data){ 96 .fw_name = "xo" 97 }, 98 .num_parents = 1, 99 .ops = &clk_alpha_pll_fixed_fabia_ops, 100 }, 101 }, 102}; 103 104static struct clk_alpha_pll_postdiv mmpll1_out_even = { 105 .offset = 0xc050, 106 .post_div_shift = 8, 107 .post_div_table = post_div_table_fabia_even, 108 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 109 .width = 4, 110 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 111 .clkr.hw.init = &(struct clk_init_data){ 112 .name = "mmpll1_out_even", 113 .parent_hws = (const struct clk_hw *[]){ &mmpll1.clkr.hw }, 114 .num_parents = 1, 115 .ops = &clk_alpha_pll_postdiv_fabia_ops, 116 }, 117}; 118 119static struct clk_alpha_pll mmpll3 = { 120 .offset = 0x0, 121 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 122 .clkr.hw.init = &(struct clk_init_data){ 123 .name = "mmpll3", 124 .parent_data = &(const struct clk_parent_data){ 125 .fw_name = "xo" 126 }, 127 .num_parents = 1, 128 .ops = &clk_alpha_pll_fixed_fabia_ops, 129 }, 130}; 131 132static struct clk_alpha_pll_postdiv mmpll3_out_even = { 133 .offset = 0x0, 134 .post_div_shift = 8, 135 .post_div_table = post_div_table_fabia_even, 136 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 137 .width = 4, 138 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 139 .clkr.hw.init = &(struct clk_init_data){ 140 .name = "mmpll3_out_even", 141 .parent_hws = (const struct clk_hw *[]){ &mmpll3.clkr.hw }, 142 .num_parents = 1, 143 .ops = &clk_alpha_pll_postdiv_fabia_ops, 144 }, 145}; 146 147static struct clk_alpha_pll mmpll4 = { 148 .offset = 0x50, 149 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 150 .clkr.hw.init = &(struct clk_init_data){ 151 .name = "mmpll4", 152 .parent_data = &(const struct clk_parent_data){ 153 .fw_name = "xo" 154 }, 155 .num_parents = 1, 156 .ops = &clk_alpha_pll_fixed_fabia_ops, 157 }, 158}; 159 160static struct clk_alpha_pll_postdiv mmpll4_out_even = { 161 .offset = 0x50, 162 .post_div_shift = 8, 163 .post_div_table = post_div_table_fabia_even, 164 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 165 .width = 4, 166 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 167 .clkr.hw.init = &(struct clk_init_data){ 168 .name = "mmpll4_out_even", 169 .parent_hws = (const struct clk_hw *[]){ &mmpll4.clkr.hw }, 170 .num_parents = 1, 171 .ops = &clk_alpha_pll_postdiv_fabia_ops, 172 }, 173}; 174 175static struct clk_alpha_pll mmpll5 = { 176 .offset = 0xa0, 177 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 178 .clkr.hw.init = &(struct clk_init_data){ 179 .name = "mmpll5", 180 .parent_data = &(const struct clk_parent_data){ 181 .fw_name = "xo" 182 }, 183 .num_parents = 1, 184 .ops = &clk_alpha_pll_fixed_fabia_ops, 185 }, 186}; 187 188static struct clk_alpha_pll_postdiv mmpll5_out_even = { 189 .offset = 0xa0, 190 .post_div_shift = 8, 191 .post_div_table = post_div_table_fabia_even, 192 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 193 .width = 4, 194 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 195 .clkr.hw.init = &(struct clk_init_data){ 196 .name = "mmpll5_out_even", 197 .parent_hws = (const struct clk_hw *[]){ &mmpll5.clkr.hw }, 198 .num_parents = 1, 199 .ops = &clk_alpha_pll_postdiv_fabia_ops, 200 }, 201}; 202 203static struct clk_alpha_pll mmpll6 = { 204 .offset = 0xf0, 205 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 206 .clkr.hw.init = &(struct clk_init_data){ 207 .name = "mmpll6", 208 .parent_data = &(const struct clk_parent_data){ 209 .fw_name = "xo" 210 }, 211 .num_parents = 1, 212 .ops = &clk_alpha_pll_fixed_fabia_ops, 213 }, 214}; 215 216static struct clk_alpha_pll_postdiv mmpll6_out_even = { 217 .offset = 0xf0, 218 .post_div_shift = 8, 219 .post_div_table = post_div_table_fabia_even, 220 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 221 .width = 4, 222 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 223 .clkr.hw.init = &(struct clk_init_data){ 224 .name = "mmpll6_out_even", 225 .parent_hws = (const struct clk_hw *[]){ &mmpll6.clkr.hw }, 226 .num_parents = 1, 227 .ops = &clk_alpha_pll_postdiv_fabia_ops, 228 }, 229}; 230 231static struct clk_alpha_pll mmpll7 = { 232 .offset = 0x140, 233 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 234 .clkr.hw.init = &(struct clk_init_data){ 235 .name = "mmpll7", 236 .parent_data = &(const struct clk_parent_data){ 237 .fw_name = "xo" 238 }, 239 .num_parents = 1, 240 .ops = &clk_alpha_pll_fixed_fabia_ops, 241 }, 242}; 243 244static struct clk_alpha_pll_postdiv mmpll7_out_even = { 245 .offset = 0x140, 246 .post_div_shift = 8, 247 .post_div_table = post_div_table_fabia_even, 248 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 249 .width = 4, 250 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 251 .clkr.hw.init = &(struct clk_init_data){ 252 .name = "mmpll7_out_even", 253 .parent_hws = (const struct clk_hw *[]){ &mmpll7.clkr.hw }, 254 .num_parents = 1, 255 .ops = &clk_alpha_pll_postdiv_fabia_ops, 256 }, 257}; 258 259static struct clk_alpha_pll mmpll10 = { 260 .offset = 0x190, 261 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 262 .clkr.hw.init = &(struct clk_init_data){ 263 .name = "mmpll10", 264 .parent_data = &(const struct clk_parent_data){ 265 .fw_name = "xo" 266 }, 267 .num_parents = 1, 268 .ops = &clk_alpha_pll_fixed_fabia_ops, 269 }, 270}; 271 272static struct clk_alpha_pll_postdiv mmpll10_out_even = { 273 .offset = 0x190, 274 .post_div_shift = 8, 275 .post_div_table = post_div_table_fabia_even, 276 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even), 277 .width = 4, 278 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 279 .clkr.hw.init = &(struct clk_init_data){ 280 .name = "mmpll10_out_even", 281 .parent_hws = (const struct clk_hw *[]){ &mmpll10.clkr.hw }, 282 .num_parents = 1, 283 .ops = &clk_alpha_pll_postdiv_fabia_ops, 284 }, 285}; 286 287static const struct parent_map mmss_xo_hdmi_map[] = { 288 { P_XO, 0 }, 289 { P_HDMIPLL, 1 }, 290}; 291 292static const struct clk_parent_data mmss_xo_hdmi[] = { 293 { .fw_name = "xo" }, 294 { .fw_name = "hdmipll" }, 295}; 296 297static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { 298 { P_XO, 0 }, 299 { P_DSI0PLL, 1 }, 300 { P_DSI1PLL, 2 }, 301}; 302 303static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = { 304 { .fw_name = "xo" }, 305 { .fw_name = "dsi0dsi" }, 306 { .fw_name = "dsi1dsi" }, 307}; 308 309static const struct parent_map mmss_xo_dsibyte_map[] = { 310 { P_XO, 0 }, 311 { P_DSI0PLL_BYTE, 1 }, 312 { P_DSI1PLL_BYTE, 2 }, 313}; 314 315static const struct clk_parent_data mmss_xo_dsibyte[] = { 316 { .fw_name = "xo" }, 317 { .fw_name = "dsi0byte" }, 318 { .fw_name = "dsi1byte" }, 319}; 320 321static const struct parent_map mmss_xo_dp_map[] = { 322 { P_XO, 0 }, 323 { P_DPLINK, 1 }, 324 { P_DPVCO, 2 }, 325}; 326 327static const struct clk_parent_data mmss_xo_dp[] = { 328 { .fw_name = "xo" }, 329 { .fw_name = "dplink" }, 330 { .fw_name = "dpvco" }, 331}; 332 333static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { 334 { P_XO, 0 }, 335 { P_GPLL0, 5 }, 336 { P_GPLL0_DIV, 6 }, 337}; 338 339static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = { 340 { .fw_name = "xo" }, 341 { .fw_name = "gpll0" }, 342 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, 343}; 344 345static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { 346 { P_XO, 0 }, 347 { P_MMPLL0_OUT_EVEN, 1 }, 348 { P_GPLL0, 5 }, 349 { P_GPLL0_DIV, 6 }, 350}; 351 352static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = { 353 { .fw_name = "xo" }, 354 { .hw = &mmpll0_out_even.clkr.hw }, 355 { .fw_name = "gpll0" }, 356 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, 357}; 358 359static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { 360 { P_XO, 0 }, 361 { P_MMPLL0_OUT_EVEN, 1 }, 362 { P_MMPLL1_OUT_EVEN, 2 }, 363 { P_GPLL0, 5 }, 364 { P_GPLL0_DIV, 6 }, 365}; 366 367static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { 368 { .fw_name = "xo" }, 369 { .hw = &mmpll0_out_even.clkr.hw }, 370 { .hw = &mmpll1_out_even.clkr.hw }, 371 { .fw_name = "gpll0" }, 372 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, 373}; 374 375static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { 376 { P_XO, 0 }, 377 { P_MMPLL0_OUT_EVEN, 1 }, 378 { P_MMPLL5_OUT_EVEN, 2 }, 379 { P_GPLL0, 5 }, 380 { P_GPLL0_DIV, 6 }, 381}; 382 383static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { 384 { .fw_name = "xo" }, 385 { .hw = &mmpll0_out_even.clkr.hw }, 386 { .hw = &mmpll5_out_even.clkr.hw }, 387 { .fw_name = "gpll0" }, 388 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, 389}; 390 391static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = { 392 { P_XO, 0 }, 393 { P_MMPLL0_OUT_EVEN, 1 }, 394 { P_MMPLL3_OUT_EVEN, 3 }, 395 { P_MMPLL6_OUT_EVEN, 4 }, 396 { P_GPLL0, 5 }, 397 { P_GPLL0_DIV, 6 }, 398}; 399 400static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div[] = { 401 { .fw_name = "xo" }, 402 { .hw = &mmpll0_out_even.clkr.hw }, 403 { .hw = &mmpll3_out_even.clkr.hw }, 404 { .hw = &mmpll6_out_even.clkr.hw }, 405 { .fw_name = "gpll0" }, 406 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, 407}; 408 409static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = { 410 { P_XO, 0 }, 411 { P_MMPLL4_OUT_EVEN, 1 }, 412 { P_MMPLL7_OUT_EVEN, 2 }, 413 { P_MMPLL10_OUT_EVEN, 3 }, 414 { P_GPLL0, 5 }, 415 { P_GPLL0_DIV, 6 }, 416}; 417 418static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = { 419 { .fw_name = "xo" }, 420 { .hw = &mmpll4_out_even.clkr.hw }, 421 { .hw = &mmpll7_out_even.clkr.hw }, 422 { .hw = &mmpll10_out_even.clkr.hw }, 423 { .fw_name = "gpll0" }, 424 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, 425}; 426 427static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = { 428 { P_XO, 0 }, 429 { P_MMPLL0_OUT_EVEN, 1 }, 430 { P_MMPLL7_OUT_EVEN, 2 }, 431 { P_MMPLL10_OUT_EVEN, 3 }, 432 { P_GPLL0, 5 }, 433 { P_GPLL0_DIV, 6 }, 434}; 435 436static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div[] = { 437 { .fw_name = "xo" }, 438 { .hw = &mmpll0_out_even.clkr.hw }, 439 { .hw = &mmpll7_out_even.clkr.hw }, 440 { .hw = &mmpll10_out_even.clkr.hw }, 441 { .fw_name = "gpll0" }, 442 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, 443}; 444 445static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = { 446 { P_XO, 0 }, 447 { P_MMPLL0_OUT_EVEN, 1 }, 448 { P_MMPLL4_OUT_EVEN, 2 }, 449 { P_MMPLL7_OUT_EVEN, 3 }, 450 { P_MMPLL10_OUT_EVEN, 4 }, 451 { P_GPLL0, 5 }, 452 { P_GPLL0_DIV, 6 }, 453}; 454 455static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = { 456 { .fw_name = "xo" }, 457 { .hw = &mmpll0_out_even.clkr.hw }, 458 { .hw = &mmpll4_out_even.clkr.hw }, 459 { .hw = &mmpll7_out_even.clkr.hw }, 460 { .hw = &mmpll10_out_even.clkr.hw }, 461 { .fw_name = "gpll0" }, 462 { .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" }, 463}; 464 465static struct clk_rcg2 byte0_clk_src = { 466 .cmd_rcgr = 0x2120, 467 .hid_width = 5, 468 .parent_map = mmss_xo_dsibyte_map, 469 .clkr.hw.init = &(struct clk_init_data){ 470 .name = "byte0_clk_src", 471 .parent_data = mmss_xo_dsibyte, 472 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), 473 .ops = &clk_byte2_ops, 474 .flags = CLK_SET_RATE_PARENT, 475 }, 476}; 477 478static struct clk_rcg2 byte1_clk_src = { 479 .cmd_rcgr = 0x2140, 480 .hid_width = 5, 481 .parent_map = mmss_xo_dsibyte_map, 482 .clkr.hw.init = &(struct clk_init_data){ 483 .name = "byte1_clk_src", 484 .parent_data = mmss_xo_dsibyte, 485 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), 486 .ops = &clk_byte2_ops, 487 .flags = CLK_SET_RATE_PARENT, 488 }, 489}; 490 491static const struct freq_tbl ftbl_cci_clk_src[] = { 492 F(37500000, P_GPLL0, 16, 0, 0), 493 F(50000000, P_GPLL0, 12, 0, 0), 494 F(100000000, P_GPLL0, 6, 0, 0), 495 { } 496}; 497 498static struct clk_rcg2 cci_clk_src = { 499 .cmd_rcgr = 0x3300, 500 .hid_width = 5, 501 .parent_map = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map, 502 .freq_tbl = ftbl_cci_clk_src, 503 .clkr.hw.init = &(struct clk_init_data){ 504 .name = "cci_clk_src", 505 .parent_data = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div, 506 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div), 507 .ops = &clk_rcg2_ops, 508 }, 509}; 510 511static const struct freq_tbl ftbl_cpp_clk_src[] = { 512 F(100000000, P_GPLL0, 6, 0, 0), 513 F(200000000, P_GPLL0, 3, 0, 0), 514 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0), 515 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0), 516 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0), 517 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0), 518 F(600000000, P_GPLL0, 1, 0, 0), 519 { } 520}; 521 522static struct clk_rcg2 cpp_clk_src = { 523 .cmd_rcgr = 0x3640, 524 .hid_width = 5, 525 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 526 .freq_tbl = ftbl_cpp_clk_src, 527 .clkr.hw.init = &(struct clk_init_data){ 528 .name = "cpp_clk_src", 529 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 530 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 531 .ops = &clk_rcg2_ops, 532 }, 533}; 534 535static const struct freq_tbl ftbl_csi_clk_src[] = { 536 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0), 537 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0), 538 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0), 539 F(300000000, P_GPLL0, 2, 0, 0), 540 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0), 541 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0), 542 { } 543}; 544 545static struct clk_rcg2 csi0_clk_src = { 546 .cmd_rcgr = 0x3090, 547 .hid_width = 5, 548 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 549 .freq_tbl = ftbl_csi_clk_src, 550 .clkr.hw.init = &(struct clk_init_data){ 551 .name = "csi0_clk_src", 552 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 553 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 554 .ops = &clk_rcg2_ops, 555 }, 556}; 557 558static struct clk_rcg2 csi1_clk_src = { 559 .cmd_rcgr = 0x3100, 560 .hid_width = 5, 561 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 562 .freq_tbl = ftbl_csi_clk_src, 563 .clkr.hw.init = &(struct clk_init_data){ 564 .name = "csi1_clk_src", 565 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 566 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 567 .ops = &clk_rcg2_ops, 568 }, 569}; 570 571static struct clk_rcg2 csi2_clk_src = { 572 .cmd_rcgr = 0x3160, 573 .hid_width = 5, 574 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 575 .freq_tbl = ftbl_csi_clk_src, 576 .clkr.hw.init = &(struct clk_init_data){ 577 .name = "csi2_clk_src", 578 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 579 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 580 .ops = &clk_rcg2_ops, 581 }, 582}; 583 584static struct clk_rcg2 csi3_clk_src = { 585 .cmd_rcgr = 0x31c0, 586 .hid_width = 5, 587 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 588 .freq_tbl = ftbl_csi_clk_src, 589 .clkr.hw.init = &(struct clk_init_data){ 590 .name = "csi3_clk_src", 591 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 592 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 593 .ops = &clk_rcg2_ops, 594 }, 595}; 596 597static const struct freq_tbl ftbl_csiphy_clk_src[] = { 598 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0), 599 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0), 600 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0), 601 F(300000000, P_GPLL0, 2, 0, 0), 602 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0), 603 { } 604}; 605 606static struct clk_rcg2 csiphy_clk_src = { 607 .cmd_rcgr = 0x3800, 608 .hid_width = 5, 609 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 610 .freq_tbl = ftbl_csiphy_clk_src, 611 .clkr.hw.init = &(struct clk_init_data){ 612 .name = "csiphy_clk_src", 613 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 614 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 615 .ops = &clk_rcg2_ops, 616 }, 617}; 618 619static const struct freq_tbl ftbl_csiphytimer_clk_src[] = { 620 F(200000000, P_GPLL0, 3, 0, 0), 621 F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0), 622 { } 623}; 624 625static struct clk_rcg2 csi0phytimer_clk_src = { 626 .cmd_rcgr = 0x3000, 627 .hid_width = 5, 628 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 629 .freq_tbl = ftbl_csiphytimer_clk_src, 630 .clkr.hw.init = &(struct clk_init_data){ 631 .name = "csi0phytimer_clk_src", 632 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 633 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 634 .ops = &clk_rcg2_ops, 635 }, 636}; 637 638static struct clk_rcg2 csi1phytimer_clk_src = { 639 .cmd_rcgr = 0x3030, 640 .hid_width = 5, 641 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 642 .freq_tbl = ftbl_csiphytimer_clk_src, 643 .clkr.hw.init = &(struct clk_init_data){ 644 .name = "csi1phytimer_clk_src", 645 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 646 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 647 .ops = &clk_rcg2_ops, 648 }, 649}; 650 651static struct clk_rcg2 csi2phytimer_clk_src = { 652 .cmd_rcgr = 0x3060, 653 .hid_width = 5, 654 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 655 .freq_tbl = ftbl_csiphytimer_clk_src, 656 .clkr.hw.init = &(struct clk_init_data){ 657 .name = "csi2phytimer_clk_src", 658 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 659 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 660 .ops = &clk_rcg2_ops, 661 }, 662}; 663 664static const struct freq_tbl ftbl_dp_aux_clk_src[] = { 665 F(19200000, P_XO, 1, 0, 0), 666 { } 667}; 668 669static struct clk_rcg2 dp_aux_clk_src = { 670 .cmd_rcgr = 0x2260, 671 .hid_width = 5, 672 .parent_map = mmss_xo_gpll0_gpll0_div_map, 673 .freq_tbl = ftbl_dp_aux_clk_src, 674 .clkr.hw.init = &(struct clk_init_data){ 675 .name = "dp_aux_clk_src", 676 .parent_data = mmss_xo_gpll0_gpll0_div, 677 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div), 678 .ops = &clk_rcg2_ops, 679 }, 680}; 681 682static const struct freq_tbl ftbl_dp_crypto_clk_src[] = { 683 F(101250, P_DPLINK, 1, 5, 16), 684 F(168750, P_DPLINK, 1, 5, 16), 685 F(337500, P_DPLINK, 1, 5, 16), 686 { } 687}; 688 689static struct clk_rcg2 dp_crypto_clk_src = { 690 .cmd_rcgr = 0x2220, 691 .hid_width = 5, 692 .parent_map = mmss_xo_dp_map, 693 .freq_tbl = ftbl_dp_crypto_clk_src, 694 .clkr.hw.init = &(struct clk_init_data){ 695 .name = "dp_crypto_clk_src", 696 .parent_data = mmss_xo_dp, 697 .num_parents = ARRAY_SIZE(mmss_xo_dp), 698 .ops = &clk_rcg2_ops, 699 }, 700}; 701 702static const struct freq_tbl ftbl_dp_link_clk_src[] = { 703 F(162000, P_DPLINK, 2, 0, 0), 704 F(270000, P_DPLINK, 2, 0, 0), 705 F(540000, P_DPLINK, 2, 0, 0), 706 { } 707}; 708 709static struct clk_rcg2 dp_link_clk_src = { 710 .cmd_rcgr = 0x2200, 711 .hid_width = 5, 712 .parent_map = mmss_xo_dp_map, 713 .freq_tbl = ftbl_dp_link_clk_src, 714 .clkr.hw.init = &(struct clk_init_data){ 715 .name = "dp_link_clk_src", 716 .parent_data = mmss_xo_dp, 717 .num_parents = ARRAY_SIZE(mmss_xo_dp), 718 .ops = &clk_rcg2_ops, 719 }, 720}; 721 722static const struct freq_tbl ftbl_dp_pixel_clk_src[] = { 723 F(154000000, P_DPVCO, 1, 0, 0), 724 F(337500000, P_DPVCO, 2, 0, 0), 725 F(675000000, P_DPVCO, 2, 0, 0), 726 { } 727}; 728 729static struct clk_rcg2 dp_pixel_clk_src = { 730 .cmd_rcgr = 0x2240, 731 .hid_width = 5, 732 .parent_map = mmss_xo_dp_map, 733 .freq_tbl = ftbl_dp_pixel_clk_src, 734 .clkr.hw.init = &(struct clk_init_data){ 735 .name = "dp_pixel_clk_src", 736 .parent_data = mmss_xo_dp, 737 .num_parents = ARRAY_SIZE(mmss_xo_dp), 738 .ops = &clk_rcg2_ops, 739 }, 740}; 741 742static const struct freq_tbl ftbl_esc_clk_src[] = { 743 F(19200000, P_XO, 1, 0, 0), 744 { } 745}; 746 747static struct clk_rcg2 esc0_clk_src = { 748 .cmd_rcgr = 0x2160, 749 .hid_width = 5, 750 .parent_map = mmss_xo_dsibyte_map, 751 .freq_tbl = ftbl_esc_clk_src, 752 .clkr.hw.init = &(struct clk_init_data){ 753 .name = "esc0_clk_src", 754 .parent_data = mmss_xo_dsibyte, 755 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), 756 .ops = &clk_rcg2_ops, 757 }, 758}; 759 760static struct clk_rcg2 esc1_clk_src = { 761 .cmd_rcgr = 0x2180, 762 .hid_width = 5, 763 .parent_map = mmss_xo_dsibyte_map, 764 .freq_tbl = ftbl_esc_clk_src, 765 .clkr.hw.init = &(struct clk_init_data){ 766 .name = "esc1_clk_src", 767 .parent_data = mmss_xo_dsibyte, 768 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), 769 .ops = &clk_rcg2_ops, 770 }, 771}; 772 773static const struct freq_tbl ftbl_extpclk_clk_src[] = { 774 { .src = P_HDMIPLL }, 775 { } 776}; 777 778static struct clk_rcg2 extpclk_clk_src = { 779 .cmd_rcgr = 0x2060, 780 .hid_width = 5, 781 .parent_map = mmss_xo_hdmi_map, 782 .freq_tbl = ftbl_extpclk_clk_src, 783 .clkr.hw.init = &(struct clk_init_data){ 784 .name = "extpclk_clk_src", 785 .parent_data = mmss_xo_hdmi, 786 .num_parents = ARRAY_SIZE(mmss_xo_hdmi), 787 .ops = &clk_byte_ops, 788 .flags = CLK_SET_RATE_PARENT, 789 }, 790}; 791 792static const struct freq_tbl ftbl_fd_core_clk_src[] = { 793 F(100000000, P_GPLL0, 6, 0, 0), 794 F(200000000, P_GPLL0, 3, 0, 0), 795 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0), 796 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0), 797 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0), 798 { } 799}; 800 801static struct clk_rcg2 fd_core_clk_src = { 802 .cmd_rcgr = 0x3b00, 803 .hid_width = 5, 804 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 805 .freq_tbl = ftbl_fd_core_clk_src, 806 .clkr.hw.init = &(struct clk_init_data){ 807 .name = "fd_core_clk_src", 808 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 809 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 810 .ops = &clk_rcg2_ops, 811 }, 812}; 813 814static const struct freq_tbl ftbl_hdmi_clk_src[] = { 815 F(19200000, P_XO, 1, 0, 0), 816 { } 817}; 818 819static struct clk_rcg2 hdmi_clk_src = { 820 .cmd_rcgr = 0x2100, 821 .hid_width = 5, 822 .parent_map = mmss_xo_gpll0_gpll0_div_map, 823 .freq_tbl = ftbl_hdmi_clk_src, 824 .clkr.hw.init = &(struct clk_init_data){ 825 .name = "hdmi_clk_src", 826 .parent_data = mmss_xo_gpll0_gpll0_div, 827 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div), 828 .ops = &clk_rcg2_ops, 829 }, 830}; 831 832static const struct freq_tbl ftbl_jpeg0_clk_src[] = { 833 F(75000000, P_GPLL0, 8, 0, 0), 834 F(150000000, P_GPLL0, 4, 0, 0), 835 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0), 836 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0), 837 { } 838}; 839 840static struct clk_rcg2 jpeg0_clk_src = { 841 .cmd_rcgr = 0x3500, 842 .hid_width = 5, 843 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 844 .freq_tbl = ftbl_jpeg0_clk_src, 845 .clkr.hw.init = &(struct clk_init_data){ 846 .name = "jpeg0_clk_src", 847 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 848 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 849 .ops = &clk_rcg2_ops, 850 }, 851}; 852 853static const struct freq_tbl ftbl_maxi_clk_src[] = { 854 F(19200000, P_XO, 1, 0, 0), 855 F(75000000, P_GPLL0_DIV, 4, 0, 0), 856 F(171428571, P_GPLL0, 3.5, 0, 0), 857 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0), 858 F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0), 859 { } 860}; 861 862static struct clk_rcg2 maxi_clk_src = { 863 .cmd_rcgr = 0xf020, 864 .hid_width = 5, 865 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 866 .freq_tbl = ftbl_maxi_clk_src, 867 .clkr.hw.init = &(struct clk_init_data){ 868 .name = "maxi_clk_src", 869 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 870 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div), 871 .ops = &clk_rcg2_ops, 872 }, 873}; 874 875static const struct freq_tbl ftbl_mclk_clk_src[] = { 876 F(4800000, P_XO, 4, 0, 0), 877 F(6000000, P_GPLL0_DIV, 10, 1, 5), 878 F(8000000, P_GPLL0_DIV, 1, 2, 75), 879 F(9600000, P_XO, 2, 0, 0), 880 F(16666667, P_GPLL0_DIV, 2, 1, 9), 881 F(19200000, P_XO, 1, 0, 0), 882 F(24000000, P_GPLL0_DIV, 1, 2, 25), 883 F(33333333, P_GPLL0_DIV, 1, 2, 9), 884 F(48000000, P_GPLL0, 1, 2, 25), 885 F(66666667, P_GPLL0, 1, 2, 9), 886 { } 887}; 888 889static struct clk_rcg2 mclk0_clk_src = { 890 .cmd_rcgr = 0x3360, 891 .hid_width = 5, 892 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 893 .freq_tbl = ftbl_mclk_clk_src, 894 .clkr.hw.init = &(struct clk_init_data){ 895 .name = "mclk0_clk_src", 896 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 897 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 898 .ops = &clk_rcg2_ops, 899 }, 900}; 901 902static struct clk_rcg2 mclk1_clk_src = { 903 .cmd_rcgr = 0x3390, 904 .hid_width = 5, 905 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 906 .freq_tbl = ftbl_mclk_clk_src, 907 .clkr.hw.init = &(struct clk_init_data){ 908 .name = "mclk1_clk_src", 909 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 910 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 911 .ops = &clk_rcg2_ops, 912 }, 913}; 914 915static struct clk_rcg2 mclk2_clk_src = { 916 .cmd_rcgr = 0x33c0, 917 .hid_width = 5, 918 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 919 .freq_tbl = ftbl_mclk_clk_src, 920 .clkr.hw.init = &(struct clk_init_data){ 921 .name = "mclk2_clk_src", 922 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 923 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 924 .ops = &clk_rcg2_ops, 925 }, 926}; 927 928static struct clk_rcg2 mclk3_clk_src = { 929 .cmd_rcgr = 0x33f0, 930 .hid_width = 5, 931 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 932 .freq_tbl = ftbl_mclk_clk_src, 933 .clkr.hw.init = &(struct clk_init_data){ 934 .name = "mclk3_clk_src", 935 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 936 .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 937 .ops = &clk_rcg2_ops, 938 }, 939}; 940 941static const struct freq_tbl ftbl_mdp_clk_src[] = { 942 F(85714286, P_GPLL0, 7, 0, 0), 943 F(100000000, P_GPLL0, 6, 0, 0), 944 F(150000000, P_GPLL0, 4, 0, 0), 945 F(171428571, P_GPLL0, 3.5, 0, 0), 946 F(200000000, P_GPLL0, 3, 0, 0), 947 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0), 948 F(300000000, P_GPLL0, 2, 0, 0), 949 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0), 950 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0), 951 { } 952}; 953 954static struct clk_rcg2 mdp_clk_src = { 955 .cmd_rcgr = 0x2040, 956 .hid_width = 5, 957 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map, 958 .freq_tbl = ftbl_mdp_clk_src, 959 .clkr.hw.init = &(struct clk_init_data){ 960 .name = "mdp_clk_src", 961 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, 962 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div), 963 .ops = &clk_rcg2_ops, 964 }, 965}; 966 967static const struct freq_tbl ftbl_vsync_clk_src[] = { 968 F(19200000, P_XO, 1, 0, 0), 969 { } 970}; 971 972static struct clk_rcg2 vsync_clk_src = { 973 .cmd_rcgr = 0x2080, 974 .hid_width = 5, 975 .parent_map = mmss_xo_gpll0_gpll0_div_map, 976 .freq_tbl = ftbl_vsync_clk_src, 977 .clkr.hw.init = &(struct clk_init_data){ 978 .name = "vsync_clk_src", 979 .parent_data = mmss_xo_gpll0_gpll0_div, 980 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div), 981 .ops = &clk_rcg2_ops, 982 }, 983}; 984 985static const struct freq_tbl ftbl_ahb_clk_src[] = { 986 F(19200000, P_XO, 1, 0, 0), 987 F(40000000, P_GPLL0, 15, 0, 0), 988 F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0), 989 { } 990}; 991 992static struct clk_rcg2 ahb_clk_src = { 993 .cmd_rcgr = 0x5000, 994 .hid_width = 5, 995 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, 996 .freq_tbl = ftbl_ahb_clk_src, 997 .clkr.hw.init = &(struct clk_init_data){ 998 .name = "ahb_clk_src", 999 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div, 1000 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div), 1001 .ops = &clk_rcg2_ops, 1002 }, 1003}; 1004 1005static const struct freq_tbl ftbl_axi_clk_src[] = { 1006 F(75000000, P_GPLL0, 8, 0, 0), 1007 F(171428571, P_GPLL0, 3.5, 0, 0), 1008 F(240000000, P_GPLL0, 2.5, 0, 0), 1009 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0), 1010 F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0), 1011 { } 1012}; 1013 1014/* RO to linux */ 1015static struct clk_rcg2 axi_clk_src = { 1016 .cmd_rcgr = 0xd000, 1017 .hid_width = 5, 1018 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, 1019 .freq_tbl = ftbl_axi_clk_src, 1020 .clkr.hw.init = &(struct clk_init_data){ 1021 .name = "axi_clk_src", 1022 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 1023 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div), 1024 .ops = &clk_rcg2_ops, 1025 }, 1026}; 1027 1028static struct clk_rcg2 pclk0_clk_src = { 1029 .cmd_rcgr = 0x2000, 1030 .mnd_width = 8, 1031 .hid_width = 5, 1032 .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 1033 .clkr.hw.init = &(struct clk_init_data){ 1034 .name = "pclk0_clk_src", 1035 .parent_data = mmss_xo_dsi0pll_dsi1pll, 1036 .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll), 1037 .ops = &clk_pixel_ops, 1038 .flags = CLK_SET_RATE_PARENT, 1039 }, 1040}; 1041 1042static struct clk_rcg2 pclk1_clk_src = { 1043 .cmd_rcgr = 0x2020, 1044 .mnd_width = 8, 1045 .hid_width = 5, 1046 .parent_map = mmss_xo_dsi0pll_dsi1pll_map, 1047 .clkr.hw.init = &(struct clk_init_data){ 1048 .name = "pclk1_clk_src", 1049 .parent_data = mmss_xo_dsi0pll_dsi1pll, 1050 .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll), 1051 .ops = &clk_pixel_ops, 1052 .flags = CLK_SET_RATE_PARENT, 1053 }, 1054}; 1055 1056static const struct freq_tbl ftbl_rot_clk_src[] = { 1057 F(171428571, P_GPLL0, 3.5, 0, 0), 1058 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0), 1059 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0), 1060 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0), 1061 { } 1062}; 1063 1064static struct clk_rcg2 rot_clk_src = { 1065 .cmd_rcgr = 0x21a0, 1066 .hid_width = 5, 1067 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map, 1068 .freq_tbl = ftbl_rot_clk_src, 1069 .clkr.hw.init = &(struct clk_init_data){ 1070 .name = "rot_clk_src", 1071 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, 1072 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div), 1073 .ops = &clk_rcg2_ops, 1074 }, 1075}; 1076 1077static const struct freq_tbl ftbl_video_core_clk_src[] = { 1078 F(200000000, P_GPLL0, 3, 0, 0), 1079 F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0), 1080 F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0), 1081 F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0), 1082 F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0), 1083 { } 1084}; 1085 1086static struct clk_rcg2 video_core_clk_src = { 1087 .cmd_rcgr = 0x1000, 1088 .hid_width = 5, 1089 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map, 1090 .freq_tbl = ftbl_video_core_clk_src, 1091 .clkr.hw.init = &(struct clk_init_data){ 1092 .name = "video_core_clk_src", 1093 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div, 1094 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div), 1095 .ops = &clk_rcg2_ops, 1096 }, 1097}; 1098 1099static struct clk_rcg2 video_subcore0_clk_src = { 1100 .cmd_rcgr = 0x1060, 1101 .hid_width = 5, 1102 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map, 1103 .freq_tbl = ftbl_video_core_clk_src, 1104 .clkr.hw.init = &(struct clk_init_data){ 1105 .name = "video_subcore0_clk_src", 1106 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div, 1107 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div), 1108 .ops = &clk_rcg2_ops, 1109 }, 1110}; 1111 1112static struct clk_rcg2 video_subcore1_clk_src = { 1113 .cmd_rcgr = 0x1080, 1114 .hid_width = 5, 1115 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map, 1116 .freq_tbl = ftbl_video_core_clk_src, 1117 .clkr.hw.init = &(struct clk_init_data){ 1118 .name = "video_subcore1_clk_src", 1119 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div, 1120 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div), 1121 .ops = &clk_rcg2_ops, 1122 }, 1123}; 1124 1125static const struct freq_tbl ftbl_vfe_clk_src[] = { 1126 F(200000000, P_GPLL0, 3, 0, 0), 1127 F(300000000, P_GPLL0, 2, 0, 0), 1128 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0), 1129 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0), 1130 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0), 1131 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0), 1132 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0), 1133 F(600000000, P_GPLL0, 1, 0, 0), 1134 { } 1135}; 1136 1137static struct clk_rcg2 vfe0_clk_src = { 1138 .cmd_rcgr = 0x3600, 1139 .hid_width = 5, 1140 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 1141 .freq_tbl = ftbl_vfe_clk_src, 1142 .clkr.hw.init = &(struct clk_init_data){ 1143 .name = "vfe0_clk_src", 1144 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 1145 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 1146 .ops = &clk_rcg2_ops, 1147 }, 1148}; 1149 1150static struct clk_rcg2 vfe1_clk_src = { 1151 .cmd_rcgr = 0x3620, 1152 .hid_width = 5, 1153 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, 1154 .freq_tbl = ftbl_vfe_clk_src, 1155 .clkr.hw.init = &(struct clk_init_data){ 1156 .name = "vfe1_clk_src", 1157 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 1158 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 1159 .ops = &clk_rcg2_ops, 1160 }, 1161}; 1162 1163static struct clk_branch misc_ahb_clk = { 1164 .halt_reg = 0x328, 1165 .hwcg_reg = 0x328, 1166 .hwcg_bit = 1, 1167 .clkr = { 1168 .enable_reg = 0x328, 1169 .enable_mask = BIT(0), 1170 .hw.init = &(struct clk_init_data){ 1171 .name = "misc_ahb_clk", 1172 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1173 .num_parents = 1, 1174 .ops = &clk_branch2_ops, 1175 .flags = CLK_SET_RATE_PARENT, 1176 }, 1177 }, 1178}; 1179 1180static struct clk_branch video_core_clk = { 1181 .halt_reg = 0x1028, 1182 .clkr = { 1183 .enable_reg = 0x1028, 1184 .enable_mask = BIT(0), 1185 .hw.init = &(struct clk_init_data){ 1186 .name = "video_core_clk", 1187 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw }, 1188 .num_parents = 1, 1189 .ops = &clk_branch2_ops, 1190 .flags = CLK_SET_RATE_PARENT, 1191 }, 1192 }, 1193}; 1194 1195static struct clk_branch video_ahb_clk = { 1196 .halt_reg = 0x1030, 1197 .hwcg_reg = 0x1030, 1198 .hwcg_bit = 1, 1199 .clkr = { 1200 .enable_reg = 0x1030, 1201 .enable_mask = BIT(0), 1202 .hw.init = &(struct clk_init_data){ 1203 .name = "video_ahb_clk", 1204 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1205 .num_parents = 1, 1206 .ops = &clk_branch2_ops, 1207 .flags = CLK_SET_RATE_PARENT, 1208 }, 1209 }, 1210}; 1211 1212static struct clk_branch video_axi_clk = { 1213 .halt_reg = 0x1034, 1214 .clkr = { 1215 .enable_reg = 0x1034, 1216 .enable_mask = BIT(0), 1217 .hw.init = &(struct clk_init_data){ 1218 .name = "video_axi_clk", 1219 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw }, 1220 .num_parents = 1, 1221 .ops = &clk_branch2_ops, 1222 }, 1223 }, 1224}; 1225 1226static struct clk_branch video_maxi_clk = { 1227 .halt_reg = 0x1038, 1228 .clkr = { 1229 .enable_reg = 0x1038, 1230 .enable_mask = BIT(0), 1231 .hw.init = &(struct clk_init_data){ 1232 .name = "video_maxi_clk", 1233 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw }, 1234 .num_parents = 1, 1235 .ops = &clk_branch2_ops, 1236 .flags = CLK_SET_RATE_PARENT, 1237 }, 1238 }, 1239}; 1240 1241static struct clk_branch video_subcore0_clk = { 1242 .halt_reg = 0x1048, 1243 .clkr = { 1244 .enable_reg = 0x1048, 1245 .enable_mask = BIT(0), 1246 .hw.init = &(struct clk_init_data){ 1247 .name = "video_subcore0_clk", 1248 .parent_hws = (const struct clk_hw *[]){ &video_subcore0_clk_src.clkr.hw }, 1249 .num_parents = 1, 1250 .ops = &clk_branch2_ops, 1251 .flags = CLK_SET_RATE_PARENT, 1252 }, 1253 }, 1254}; 1255 1256static struct clk_branch video_subcore1_clk = { 1257 .halt_reg = 0x104c, 1258 .clkr = { 1259 .enable_reg = 0x104c, 1260 .enable_mask = BIT(0), 1261 .hw.init = &(struct clk_init_data){ 1262 .name = "video_subcore1_clk", 1263 .parent_hws = (const struct clk_hw *[]){ &video_subcore1_clk_src.clkr.hw }, 1264 .num_parents = 1, 1265 .ops = &clk_branch2_ops, 1266 .flags = CLK_SET_RATE_PARENT, 1267 }, 1268 }, 1269}; 1270 1271static struct clk_branch mdss_ahb_clk = { 1272 .halt_reg = 0x2308, 1273 .hwcg_reg = 0x2308, 1274 .hwcg_bit = 1, 1275 .clkr = { 1276 .enable_reg = 0x2308, 1277 .enable_mask = BIT(0), 1278 .hw.init = &(struct clk_init_data){ 1279 .name = "mdss_ahb_clk", 1280 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1281 .num_parents = 1, 1282 .ops = &clk_branch2_ops, 1283 .flags = CLK_SET_RATE_PARENT, 1284 }, 1285 }, 1286}; 1287 1288static struct clk_branch mdss_hdmi_dp_ahb_clk = { 1289 .halt_reg = 0x230c, 1290 .clkr = { 1291 .enable_reg = 0x230c, 1292 .enable_mask = BIT(0), 1293 .hw.init = &(struct clk_init_data){ 1294 .name = "mdss_hdmi_dp_ahb_clk", 1295 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1296 .num_parents = 1, 1297 .ops = &clk_branch2_ops, 1298 .flags = CLK_SET_RATE_PARENT, 1299 }, 1300 }, 1301}; 1302 1303static struct clk_branch mdss_axi_clk = { 1304 .halt_reg = 0x2310, 1305 .clkr = { 1306 .enable_reg = 0x2310, 1307 .enable_mask = BIT(0), 1308 .hw.init = &(struct clk_init_data){ 1309 .name = "mdss_axi_clk", 1310 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw }, 1311 .num_parents = 1, 1312 .ops = &clk_branch2_ops, 1313 }, 1314 }, 1315}; 1316 1317static struct clk_branch mdss_pclk0_clk = { 1318 .halt_reg = 0x2314, 1319 .clkr = { 1320 .enable_reg = 0x2314, 1321 .enable_mask = BIT(0), 1322 .hw.init = &(struct clk_init_data){ 1323 .name = "mdss_pclk0_clk", 1324 .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw }, 1325 .num_parents = 1, 1326 .ops = &clk_branch2_ops, 1327 .flags = CLK_SET_RATE_PARENT, 1328 }, 1329 }, 1330}; 1331 1332static struct clk_branch mdss_pclk1_clk = { 1333 .halt_reg = 0x2318, 1334 .clkr = { 1335 .enable_reg = 0x2318, 1336 .enable_mask = BIT(0), 1337 .hw.init = &(struct clk_init_data){ 1338 .name = "mdss_pclk1_clk", 1339 .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw }, 1340 .num_parents = 1, 1341 .ops = &clk_branch2_ops, 1342 .flags = CLK_SET_RATE_PARENT, 1343 }, 1344 }, 1345}; 1346 1347static struct clk_branch mdss_mdp_clk = { 1348 .halt_reg = 0x231c, 1349 .clkr = { 1350 .enable_reg = 0x231c, 1351 .enable_mask = BIT(0), 1352 .hw.init = &(struct clk_init_data){ 1353 .name = "mdss_mdp_clk", 1354 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw }, 1355 .num_parents = 1, 1356 .ops = &clk_branch2_ops, 1357 .flags = CLK_SET_RATE_PARENT, 1358 }, 1359 }, 1360}; 1361 1362static struct clk_branch mdss_mdp_lut_clk = { 1363 .halt_reg = 0x2320, 1364 .clkr = { 1365 .enable_reg = 0x2320, 1366 .enable_mask = BIT(0), 1367 .hw.init = &(struct clk_init_data){ 1368 .name = "mdss_mdp_lut_clk", 1369 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw }, 1370 .num_parents = 1, 1371 .ops = &clk_branch2_ops, 1372 .flags = CLK_SET_RATE_PARENT, 1373 }, 1374 }, 1375}; 1376 1377static struct clk_branch mdss_extpclk_clk = { 1378 .halt_reg = 0x2324, 1379 .clkr = { 1380 .enable_reg = 0x2324, 1381 .enable_mask = BIT(0), 1382 .hw.init = &(struct clk_init_data){ 1383 .name = "mdss_extpclk_clk", 1384 .parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw }, 1385 .num_parents = 1, 1386 .ops = &clk_branch2_ops, 1387 .flags = CLK_SET_RATE_PARENT, 1388 }, 1389 }, 1390}; 1391 1392static struct clk_branch mdss_vsync_clk = { 1393 .halt_reg = 0x2328, 1394 .clkr = { 1395 .enable_reg = 0x2328, 1396 .enable_mask = BIT(0), 1397 .hw.init = &(struct clk_init_data){ 1398 .name = "mdss_vsync_clk", 1399 .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw }, 1400 .num_parents = 1, 1401 .ops = &clk_branch2_ops, 1402 .flags = CLK_SET_RATE_PARENT, 1403 }, 1404 }, 1405}; 1406 1407static struct clk_branch mdss_hdmi_clk = { 1408 .halt_reg = 0x2338, 1409 .clkr = { 1410 .enable_reg = 0x2338, 1411 .enable_mask = BIT(0), 1412 .hw.init = &(struct clk_init_data){ 1413 .name = "mdss_hdmi_clk", 1414 .parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw }, 1415 .num_parents = 1, 1416 .ops = &clk_branch2_ops, 1417 .flags = CLK_SET_RATE_PARENT, 1418 }, 1419 }, 1420}; 1421 1422static struct clk_branch mdss_byte0_clk = { 1423 .halt_reg = 0x233c, 1424 .clkr = { 1425 .enable_reg = 0x233c, 1426 .enable_mask = BIT(0), 1427 .hw.init = &(struct clk_init_data){ 1428 .name = "mdss_byte0_clk", 1429 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw }, 1430 .num_parents = 1, 1431 .ops = &clk_branch2_ops, 1432 .flags = CLK_SET_RATE_PARENT, 1433 }, 1434 }, 1435}; 1436 1437static struct clk_branch mdss_byte1_clk = { 1438 .halt_reg = 0x2340, 1439 .clkr = { 1440 .enable_reg = 0x2340, 1441 .enable_mask = BIT(0), 1442 .hw.init = &(struct clk_init_data){ 1443 .name = "mdss_byte1_clk", 1444 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw }, 1445 .num_parents = 1, 1446 .ops = &clk_branch2_ops, 1447 .flags = CLK_SET_RATE_PARENT, 1448 }, 1449 }, 1450}; 1451 1452static struct clk_branch mdss_esc0_clk = { 1453 .halt_reg = 0x2344, 1454 .clkr = { 1455 .enable_reg = 0x2344, 1456 .enable_mask = BIT(0), 1457 .hw.init = &(struct clk_init_data){ 1458 .name = "mdss_esc0_clk", 1459 .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw }, 1460 .num_parents = 1, 1461 .ops = &clk_branch2_ops, 1462 .flags = CLK_SET_RATE_PARENT, 1463 }, 1464 }, 1465}; 1466 1467static struct clk_branch mdss_esc1_clk = { 1468 .halt_reg = 0x2348, 1469 .clkr = { 1470 .enable_reg = 0x2348, 1471 .enable_mask = BIT(0), 1472 .hw.init = &(struct clk_init_data){ 1473 .name = "mdss_esc1_clk", 1474 .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw }, 1475 .num_parents = 1, 1476 .ops = &clk_branch2_ops, 1477 .flags = CLK_SET_RATE_PARENT, 1478 }, 1479 }, 1480}; 1481 1482static struct clk_branch mdss_rot_clk = { 1483 .halt_reg = 0x2350, 1484 .clkr = { 1485 .enable_reg = 0x2350, 1486 .enable_mask = BIT(0), 1487 .hw.init = &(struct clk_init_data){ 1488 .name = "mdss_rot_clk", 1489 .parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw }, 1490 .num_parents = 1, 1491 .ops = &clk_branch2_ops, 1492 .flags = CLK_SET_RATE_PARENT, 1493 }, 1494 }, 1495}; 1496 1497static struct clk_branch mdss_dp_link_clk = { 1498 .halt_reg = 0x2354, 1499 .clkr = { 1500 .enable_reg = 0x2354, 1501 .enable_mask = BIT(0), 1502 .hw.init = &(struct clk_init_data){ 1503 .name = "mdss_dp_link_clk", 1504 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw }, 1505 .num_parents = 1, 1506 .ops = &clk_branch2_ops, 1507 .flags = CLK_SET_RATE_PARENT, 1508 }, 1509 }, 1510}; 1511 1512static struct clk_branch mdss_dp_link_intf_clk = { 1513 .halt_reg = 0x2358, 1514 .clkr = { 1515 .enable_reg = 0x2358, 1516 .enable_mask = BIT(0), 1517 .hw.init = &(struct clk_init_data){ 1518 .name = "mdss_dp_link_intf_clk", 1519 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw }, 1520 .num_parents = 1, 1521 .ops = &clk_branch2_ops, 1522 .flags = CLK_SET_RATE_PARENT, 1523 }, 1524 }, 1525}; 1526 1527static struct clk_branch mdss_dp_crypto_clk = { 1528 .halt_reg = 0x235c, 1529 .clkr = { 1530 .enable_reg = 0x235c, 1531 .enable_mask = BIT(0), 1532 .hw.init = &(struct clk_init_data){ 1533 .name = "mdss_dp_crypto_clk", 1534 .parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw }, 1535 .num_parents = 1, 1536 .ops = &clk_branch2_ops, 1537 .flags = CLK_SET_RATE_PARENT, 1538 }, 1539 }, 1540}; 1541 1542static struct clk_branch mdss_dp_pixel_clk = { 1543 .halt_reg = 0x2360, 1544 .clkr = { 1545 .enable_reg = 0x2360, 1546 .enable_mask = BIT(0), 1547 .hw.init = &(struct clk_init_data){ 1548 .name = "mdss_dp_pixel_clk", 1549 .parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw }, 1550 .num_parents = 1, 1551 .ops = &clk_branch2_ops, 1552 .flags = CLK_SET_RATE_PARENT, 1553 }, 1554 }, 1555}; 1556 1557static struct clk_branch mdss_dp_aux_clk = { 1558 .halt_reg = 0x2364, 1559 .clkr = { 1560 .enable_reg = 0x2364, 1561 .enable_mask = BIT(0), 1562 .hw.init = &(struct clk_init_data){ 1563 .name = "mdss_dp_aux_clk", 1564 .parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw }, 1565 .num_parents = 1, 1566 .ops = &clk_branch2_ops, 1567 .flags = CLK_SET_RATE_PARENT, 1568 }, 1569 }, 1570}; 1571 1572static struct clk_branch mdss_byte0_intf_clk = { 1573 .halt_reg = 0x2374, 1574 .clkr = { 1575 .enable_reg = 0x2374, 1576 .enable_mask = BIT(0), 1577 .hw.init = &(struct clk_init_data){ 1578 .name = "mdss_byte0_intf_clk", 1579 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw }, 1580 .num_parents = 1, 1581 .ops = &clk_branch2_ops, 1582 .flags = CLK_SET_RATE_PARENT, 1583 }, 1584 }, 1585}; 1586 1587static struct clk_branch mdss_byte1_intf_clk = { 1588 .halt_reg = 0x2378, 1589 .clkr = { 1590 .enable_reg = 0x2378, 1591 .enable_mask = BIT(0), 1592 .hw.init = &(struct clk_init_data){ 1593 .name = "mdss_byte1_intf_clk", 1594 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw }, 1595 .num_parents = 1, 1596 .ops = &clk_branch2_ops, 1597 .flags = CLK_SET_RATE_PARENT, 1598 }, 1599 }, 1600}; 1601 1602static struct clk_branch camss_csi0phytimer_clk = { 1603 .halt_reg = 0x3024, 1604 .clkr = { 1605 .enable_reg = 0x3024, 1606 .enable_mask = BIT(0), 1607 .hw.init = &(struct clk_init_data){ 1608 .name = "camss_csi0phytimer_clk", 1609 .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw }, 1610 .num_parents = 1, 1611 .ops = &clk_branch2_ops, 1612 .flags = CLK_SET_RATE_PARENT, 1613 }, 1614 }, 1615}; 1616 1617static struct clk_branch camss_csi1phytimer_clk = { 1618 .halt_reg = 0x3054, 1619 .clkr = { 1620 .enable_reg = 0x3054, 1621 .enable_mask = BIT(0), 1622 .hw.init = &(struct clk_init_data){ 1623 .name = "camss_csi1phytimer_clk", 1624 .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw }, 1625 .num_parents = 1, 1626 .ops = &clk_branch2_ops, 1627 .flags = CLK_SET_RATE_PARENT, 1628 }, 1629 }, 1630}; 1631 1632static struct clk_branch camss_csi2phytimer_clk = { 1633 .halt_reg = 0x3084, 1634 .clkr = { 1635 .enable_reg = 0x3084, 1636 .enable_mask = BIT(0), 1637 .hw.init = &(struct clk_init_data){ 1638 .name = "camss_csi2phytimer_clk", 1639 .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw }, 1640 .num_parents = 1, 1641 .ops = &clk_branch2_ops, 1642 .flags = CLK_SET_RATE_PARENT, 1643 }, 1644 }, 1645}; 1646 1647static struct clk_branch camss_csi0_clk = { 1648 .halt_reg = 0x30b4, 1649 .clkr = { 1650 .enable_reg = 0x30b4, 1651 .enable_mask = BIT(0), 1652 .hw.init = &(struct clk_init_data){ 1653 .name = "camss_csi0_clk", 1654 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw }, 1655 .num_parents = 1, 1656 .ops = &clk_branch2_ops, 1657 .flags = CLK_SET_RATE_PARENT, 1658 }, 1659 }, 1660}; 1661 1662static struct clk_branch camss_csi0_ahb_clk = { 1663 .halt_reg = 0x30bc, 1664 .clkr = { 1665 .enable_reg = 0x30bc, 1666 .enable_mask = BIT(0), 1667 .hw.init = &(struct clk_init_data){ 1668 .name = "camss_csi0_ahb_clk", 1669 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1670 .num_parents = 1, 1671 .ops = &clk_branch2_ops, 1672 .flags = CLK_SET_RATE_PARENT, 1673 }, 1674 }, 1675}; 1676 1677static struct clk_branch camss_csi0rdi_clk = { 1678 .halt_reg = 0x30d4, 1679 .clkr = { 1680 .enable_reg = 0x30d4, 1681 .enable_mask = BIT(0), 1682 .hw.init = &(struct clk_init_data){ 1683 .name = "camss_csi0rdi_clk", 1684 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw }, 1685 .num_parents = 1, 1686 .ops = &clk_branch2_ops, 1687 .flags = CLK_SET_RATE_PARENT, 1688 }, 1689 }, 1690}; 1691 1692static struct clk_branch camss_csi0pix_clk = { 1693 .halt_reg = 0x30e4, 1694 .clkr = { 1695 .enable_reg = 0x30e4, 1696 .enable_mask = BIT(0), 1697 .hw.init = &(struct clk_init_data){ 1698 .name = "camss_csi0pix_clk", 1699 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw }, 1700 .num_parents = 1, 1701 .ops = &clk_branch2_ops, 1702 .flags = CLK_SET_RATE_PARENT, 1703 }, 1704 }, 1705}; 1706 1707static struct clk_branch camss_csi1_clk = { 1708 .halt_reg = 0x3124, 1709 .clkr = { 1710 .enable_reg = 0x3124, 1711 .enable_mask = BIT(0), 1712 .hw.init = &(struct clk_init_data){ 1713 .name = "camss_csi1_clk", 1714 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw }, 1715 .num_parents = 1, 1716 .ops = &clk_branch2_ops, 1717 .flags = CLK_SET_RATE_PARENT, 1718 }, 1719 }, 1720}; 1721 1722static struct clk_branch camss_csi1_ahb_clk = { 1723 .halt_reg = 0x3128, 1724 .clkr = { 1725 .enable_reg = 0x3128, 1726 .enable_mask = BIT(0), 1727 .hw.init = &(struct clk_init_data){ 1728 .name = "camss_csi1_ahb_clk", 1729 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1730 .num_parents = 1, 1731 .ops = &clk_branch2_ops, 1732 .flags = CLK_SET_RATE_PARENT, 1733 }, 1734 }, 1735}; 1736 1737static struct clk_branch camss_csi1rdi_clk = { 1738 .halt_reg = 0x3144, 1739 .clkr = { 1740 .enable_reg = 0x3144, 1741 .enable_mask = BIT(0), 1742 .hw.init = &(struct clk_init_data){ 1743 .name = "camss_csi1rdi_clk", 1744 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw }, 1745 .num_parents = 1, 1746 .ops = &clk_branch2_ops, 1747 .flags = CLK_SET_RATE_PARENT, 1748 }, 1749 }, 1750}; 1751 1752static struct clk_branch camss_csi1pix_clk = { 1753 .halt_reg = 0x3154, 1754 .clkr = { 1755 .enable_reg = 0x3154, 1756 .enable_mask = BIT(0), 1757 .hw.init = &(struct clk_init_data){ 1758 .name = "camss_csi1pix_clk", 1759 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw }, 1760 .num_parents = 1, 1761 .ops = &clk_branch2_ops, 1762 .flags = CLK_SET_RATE_PARENT, 1763 }, 1764 }, 1765}; 1766 1767static struct clk_branch camss_csi2_clk = { 1768 .halt_reg = 0x3184, 1769 .clkr = { 1770 .enable_reg = 0x3184, 1771 .enable_mask = BIT(0), 1772 .hw.init = &(struct clk_init_data){ 1773 .name = "camss_csi2_clk", 1774 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw }, 1775 .num_parents = 1, 1776 .ops = &clk_branch2_ops, 1777 .flags = CLK_SET_RATE_PARENT, 1778 }, 1779 }, 1780}; 1781 1782static struct clk_branch camss_csi2_ahb_clk = { 1783 .halt_reg = 0x3188, 1784 .clkr = { 1785 .enable_reg = 0x3188, 1786 .enable_mask = BIT(0), 1787 .hw.init = &(struct clk_init_data){ 1788 .name = "camss_csi2_ahb_clk", 1789 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1790 .num_parents = 1, 1791 .ops = &clk_branch2_ops, 1792 .flags = CLK_SET_RATE_PARENT, 1793 }, 1794 }, 1795}; 1796 1797static struct clk_branch camss_csi2rdi_clk = { 1798 .halt_reg = 0x31a4, 1799 .clkr = { 1800 .enable_reg = 0x31a4, 1801 .enable_mask = BIT(0), 1802 .hw.init = &(struct clk_init_data){ 1803 .name = "camss_csi2rdi_clk", 1804 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw }, 1805 .num_parents = 1, 1806 .ops = &clk_branch2_ops, 1807 .flags = CLK_SET_RATE_PARENT, 1808 }, 1809 }, 1810}; 1811 1812static struct clk_branch camss_csi2pix_clk = { 1813 .halt_reg = 0x31b4, 1814 .clkr = { 1815 .enable_reg = 0x31b4, 1816 .enable_mask = BIT(0), 1817 .hw.init = &(struct clk_init_data){ 1818 .name = "camss_csi2pix_clk", 1819 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw }, 1820 .num_parents = 1, 1821 .ops = &clk_branch2_ops, 1822 .flags = CLK_SET_RATE_PARENT, 1823 }, 1824 }, 1825}; 1826 1827static struct clk_branch camss_csi3_clk = { 1828 .halt_reg = 0x31e4, 1829 .clkr = { 1830 .enable_reg = 0x31e4, 1831 .enable_mask = BIT(0), 1832 .hw.init = &(struct clk_init_data){ 1833 .name = "camss_csi3_clk", 1834 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw }, 1835 .num_parents = 1, 1836 .ops = &clk_branch2_ops, 1837 .flags = CLK_SET_RATE_PARENT, 1838 }, 1839 }, 1840}; 1841 1842static struct clk_branch camss_csi3_ahb_clk = { 1843 .halt_reg = 0x31e8, 1844 .clkr = { 1845 .enable_reg = 0x31e8, 1846 .enable_mask = BIT(0), 1847 .hw.init = &(struct clk_init_data){ 1848 .name = "camss_csi3_ahb_clk", 1849 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1850 .num_parents = 1, 1851 .ops = &clk_branch2_ops, 1852 .flags = CLK_SET_RATE_PARENT, 1853 }, 1854 }, 1855}; 1856 1857static struct clk_branch camss_csi3rdi_clk = { 1858 .halt_reg = 0x3204, 1859 .clkr = { 1860 .enable_reg = 0x3204, 1861 .enable_mask = BIT(0), 1862 .hw.init = &(struct clk_init_data){ 1863 .name = "camss_csi3rdi_clk", 1864 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw }, 1865 .num_parents = 1, 1866 .ops = &clk_branch2_ops, 1867 .flags = CLK_SET_RATE_PARENT, 1868 }, 1869 }, 1870}; 1871 1872static struct clk_branch camss_csi3pix_clk = { 1873 .halt_reg = 0x3214, 1874 .clkr = { 1875 .enable_reg = 0x3214, 1876 .enable_mask = BIT(0), 1877 .hw.init = &(struct clk_init_data){ 1878 .name = "camss_csi3pix_clk", 1879 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw }, 1880 .num_parents = 1, 1881 .ops = &clk_branch2_ops, 1882 .flags = CLK_SET_RATE_PARENT, 1883 }, 1884 }, 1885}; 1886 1887static struct clk_branch camss_ispif_ahb_clk = { 1888 .halt_reg = 0x3224, 1889 .clkr = { 1890 .enable_reg = 0x3224, 1891 .enable_mask = BIT(0), 1892 .hw.init = &(struct clk_init_data){ 1893 .name = "camss_ispif_ahb_clk", 1894 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1895 .num_parents = 1, 1896 .ops = &clk_branch2_ops, 1897 .flags = CLK_SET_RATE_PARENT, 1898 }, 1899 }, 1900}; 1901 1902static struct clk_branch camss_cci_clk = { 1903 .halt_reg = 0x3344, 1904 .clkr = { 1905 .enable_reg = 0x3344, 1906 .enable_mask = BIT(0), 1907 .hw.init = &(struct clk_init_data){ 1908 .name = "camss_cci_clk", 1909 .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw }, 1910 .num_parents = 1, 1911 .ops = &clk_branch2_ops, 1912 .flags = CLK_SET_RATE_PARENT, 1913 }, 1914 }, 1915}; 1916 1917static struct clk_branch camss_cci_ahb_clk = { 1918 .halt_reg = 0x3348, 1919 .clkr = { 1920 .enable_reg = 0x3348, 1921 .enable_mask = BIT(0), 1922 .hw.init = &(struct clk_init_data){ 1923 .name = "camss_cci_ahb_clk", 1924 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 1925 .num_parents = 1, 1926 .ops = &clk_branch2_ops, 1927 .flags = CLK_SET_RATE_PARENT, 1928 }, 1929 }, 1930}; 1931 1932static struct clk_branch camss_mclk0_clk = { 1933 .halt_reg = 0x3384, 1934 .clkr = { 1935 .enable_reg = 0x3384, 1936 .enable_mask = BIT(0), 1937 .hw.init = &(struct clk_init_data){ 1938 .name = "camss_mclk0_clk", 1939 .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw }, 1940 .num_parents = 1, 1941 .ops = &clk_branch2_ops, 1942 .flags = CLK_SET_RATE_PARENT, 1943 }, 1944 }, 1945}; 1946 1947static struct clk_branch camss_mclk1_clk = { 1948 .halt_reg = 0x33b4, 1949 .clkr = { 1950 .enable_reg = 0x33b4, 1951 .enable_mask = BIT(0), 1952 .hw.init = &(struct clk_init_data){ 1953 .name = "camss_mclk1_clk", 1954 .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw }, 1955 .num_parents = 1, 1956 .ops = &clk_branch2_ops, 1957 .flags = CLK_SET_RATE_PARENT, 1958 }, 1959 }, 1960}; 1961 1962static struct clk_branch camss_mclk2_clk = { 1963 .halt_reg = 0x33e4, 1964 .clkr = { 1965 .enable_reg = 0x33e4, 1966 .enable_mask = BIT(0), 1967 .hw.init = &(struct clk_init_data){ 1968 .name = "camss_mclk2_clk", 1969 .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw }, 1970 .num_parents = 1, 1971 .ops = &clk_branch2_ops, 1972 .flags = CLK_SET_RATE_PARENT, 1973 }, 1974 }, 1975}; 1976 1977static struct clk_branch camss_mclk3_clk = { 1978 .halt_reg = 0x3414, 1979 .clkr = { 1980 .enable_reg = 0x3414, 1981 .enable_mask = BIT(0), 1982 .hw.init = &(struct clk_init_data){ 1983 .name = "camss_mclk3_clk", 1984 .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw }, 1985 .num_parents = 1, 1986 .ops = &clk_branch2_ops, 1987 .flags = CLK_SET_RATE_PARENT, 1988 }, 1989 }, 1990}; 1991 1992static struct clk_branch camss_top_ahb_clk = { 1993 .halt_reg = 0x3484, 1994 .clkr = { 1995 .enable_reg = 0x3484, 1996 .enable_mask = BIT(0), 1997 .hw.init = &(struct clk_init_data){ 1998 .name = "camss_top_ahb_clk", 1999 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2000 .num_parents = 1, 2001 .ops = &clk_branch2_ops, 2002 .flags = CLK_SET_RATE_PARENT, 2003 }, 2004 }, 2005}; 2006 2007static struct clk_branch camss_ahb_clk = { 2008 .halt_reg = 0x348c, 2009 .clkr = { 2010 .enable_reg = 0x348c, 2011 .enable_mask = BIT(0), 2012 .hw.init = &(struct clk_init_data){ 2013 .name = "camss_ahb_clk", 2014 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2015 .num_parents = 1, 2016 .ops = &clk_branch2_ops, 2017 .flags = CLK_SET_RATE_PARENT, 2018 }, 2019 }, 2020}; 2021 2022static struct clk_branch camss_micro_ahb_clk = { 2023 .halt_reg = 0x3494, 2024 .clkr = { 2025 .enable_reg = 0x3494, 2026 .enable_mask = BIT(0), 2027 .hw.init = &(struct clk_init_data){ 2028 .name = "camss_micro_ahb_clk", 2029 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2030 .num_parents = 1, 2031 .ops = &clk_branch2_ops, 2032 .flags = CLK_SET_RATE_PARENT, 2033 }, 2034 }, 2035}; 2036 2037static struct clk_branch camss_jpeg0_clk = { 2038 .halt_reg = 0x35a8, 2039 .clkr = { 2040 .enable_reg = 0x35a8, 2041 .enable_mask = BIT(0), 2042 .hw.init = &(struct clk_init_data){ 2043 .name = "camss_jpeg0_clk", 2044 .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw }, 2045 .num_parents = 1, 2046 .ops = &clk_branch2_ops, 2047 .flags = CLK_SET_RATE_PARENT, 2048 }, 2049 }, 2050}; 2051 2052static struct clk_branch camss_jpeg_ahb_clk = { 2053 .halt_reg = 0x35b4, 2054 .clkr = { 2055 .enable_reg = 0x35b4, 2056 .enable_mask = BIT(0), 2057 .hw.init = &(struct clk_init_data){ 2058 .name = "camss_jpeg_ahb_clk", 2059 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2060 .num_parents = 1, 2061 .ops = &clk_branch2_ops, 2062 .flags = CLK_SET_RATE_PARENT, 2063 }, 2064 }, 2065}; 2066 2067static struct clk_branch camss_jpeg_axi_clk = { 2068 .halt_reg = 0x35b8, 2069 .clkr = { 2070 .enable_reg = 0x35b8, 2071 .enable_mask = BIT(0), 2072 .hw.init = &(struct clk_init_data){ 2073 .name = "camss_jpeg_axi_clk", 2074 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw }, 2075 .num_parents = 1, 2076 .ops = &clk_branch2_ops, 2077 }, 2078 }, 2079}; 2080 2081static struct clk_branch camss_vfe0_ahb_clk = { 2082 .halt_reg = 0x3668, 2083 .clkr = { 2084 .enable_reg = 0x3668, 2085 .enable_mask = BIT(0), 2086 .hw.init = &(struct clk_init_data){ 2087 .name = "camss_vfe0_ahb_clk", 2088 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2089 .num_parents = 1, 2090 .ops = &clk_branch2_ops, 2091 .flags = CLK_SET_RATE_PARENT, 2092 }, 2093 }, 2094}; 2095 2096static struct clk_branch camss_vfe1_ahb_clk = { 2097 .halt_reg = 0x3678, 2098 .clkr = { 2099 .enable_reg = 0x3678, 2100 .enable_mask = BIT(0), 2101 .hw.init = &(struct clk_init_data){ 2102 .name = "camss_vfe1_ahb_clk", 2103 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2104 .num_parents = 1, 2105 .ops = &clk_branch2_ops, 2106 .flags = CLK_SET_RATE_PARENT, 2107 }, 2108 }, 2109}; 2110 2111static struct clk_branch camss_vfe0_clk = { 2112 .halt_reg = 0x36a8, 2113 .clkr = { 2114 .enable_reg = 0x36a8, 2115 .enable_mask = BIT(0), 2116 .hw.init = &(struct clk_init_data){ 2117 .name = "camss_vfe0_clk", 2118 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw }, 2119 .num_parents = 1, 2120 .ops = &clk_branch2_ops, 2121 .flags = CLK_SET_RATE_PARENT, 2122 }, 2123 }, 2124}; 2125 2126static struct clk_branch camss_vfe1_clk = { 2127 .halt_reg = 0x36ac, 2128 .clkr = { 2129 .enable_reg = 0x36ac, 2130 .enable_mask = BIT(0), 2131 .hw.init = &(struct clk_init_data){ 2132 .name = "camss_vfe1_clk", 2133 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw }, 2134 .num_parents = 1, 2135 .ops = &clk_branch2_ops, 2136 .flags = CLK_SET_RATE_PARENT, 2137 }, 2138 }, 2139}; 2140 2141static struct clk_branch camss_cpp_clk = { 2142 .halt_reg = 0x36b0, 2143 .clkr = { 2144 .enable_reg = 0x36b0, 2145 .enable_mask = BIT(0), 2146 .hw.init = &(struct clk_init_data){ 2147 .name = "camss_cpp_clk", 2148 .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw }, 2149 .num_parents = 1, 2150 .ops = &clk_branch2_ops, 2151 .flags = CLK_SET_RATE_PARENT, 2152 }, 2153 }, 2154}; 2155 2156static struct clk_branch camss_cpp_ahb_clk = { 2157 .halt_reg = 0x36b4, 2158 .clkr = { 2159 .enable_reg = 0x36b4, 2160 .enable_mask = BIT(0), 2161 .hw.init = &(struct clk_init_data){ 2162 .name = "camss_cpp_ahb_clk", 2163 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2164 .num_parents = 1, 2165 .ops = &clk_branch2_ops, 2166 .flags = CLK_SET_RATE_PARENT, 2167 }, 2168 }, 2169}; 2170 2171static struct clk_branch camss_vfe_vbif_ahb_clk = { 2172 .halt_reg = 0x36b8, 2173 .clkr = { 2174 .enable_reg = 0x36b8, 2175 .enable_mask = BIT(0), 2176 .hw.init = &(struct clk_init_data){ 2177 .name = "camss_vfe_vbif_ahb_clk", 2178 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2179 .num_parents = 1, 2180 .ops = &clk_branch2_ops, 2181 .flags = CLK_SET_RATE_PARENT, 2182 }, 2183 }, 2184}; 2185 2186static struct clk_branch camss_vfe_vbif_axi_clk = { 2187 .halt_reg = 0x36bc, 2188 .clkr = { 2189 .enable_reg = 0x36bc, 2190 .enable_mask = BIT(0), 2191 .hw.init = &(struct clk_init_data){ 2192 .name = "camss_vfe_vbif_axi_clk", 2193 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw }, 2194 .num_parents = 1, 2195 .ops = &clk_branch2_ops, 2196 }, 2197 }, 2198}; 2199 2200static struct clk_branch camss_cpp_axi_clk = { 2201 .halt_reg = 0x36c4, 2202 .clkr = { 2203 .enable_reg = 0x36c4, 2204 .enable_mask = BIT(0), 2205 .hw.init = &(struct clk_init_data){ 2206 .name = "camss_cpp_axi_clk", 2207 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw }, 2208 .num_parents = 1, 2209 .ops = &clk_branch2_ops, 2210 }, 2211 }, 2212}; 2213 2214static struct clk_branch camss_cpp_vbif_ahb_clk = { 2215 .halt_reg = 0x36c8, 2216 .clkr = { 2217 .enable_reg = 0x36c8, 2218 .enable_mask = BIT(0), 2219 .hw.init = &(struct clk_init_data){ 2220 .name = "camss_cpp_vbif_ahb_clk", 2221 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2222 .num_parents = 1, 2223 .ops = &clk_branch2_ops, 2224 .flags = CLK_SET_RATE_PARENT, 2225 }, 2226 }, 2227}; 2228 2229static struct clk_branch camss_csi_vfe0_clk = { 2230 .halt_reg = 0x3704, 2231 .clkr = { 2232 .enable_reg = 0x3704, 2233 .enable_mask = BIT(0), 2234 .hw.init = &(struct clk_init_data){ 2235 .name = "camss_csi_vfe0_clk", 2236 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw }, 2237 .num_parents = 1, 2238 .ops = &clk_branch2_ops, 2239 .flags = CLK_SET_RATE_PARENT, 2240 }, 2241 }, 2242}; 2243 2244static struct clk_branch camss_csi_vfe1_clk = { 2245 .halt_reg = 0x3714, 2246 .clkr = { 2247 .enable_reg = 0x3714, 2248 .enable_mask = BIT(0), 2249 .hw.init = &(struct clk_init_data){ 2250 .name = "camss_csi_vfe1_clk", 2251 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw }, 2252 .num_parents = 1, 2253 .ops = &clk_branch2_ops, 2254 .flags = CLK_SET_RATE_PARENT, 2255 }, 2256 }, 2257}; 2258 2259static struct clk_branch camss_vfe0_stream_clk = { 2260 .halt_reg = 0x3720, 2261 .clkr = { 2262 .enable_reg = 0x3720, 2263 .enable_mask = BIT(0), 2264 .hw.init = &(struct clk_init_data){ 2265 .name = "camss_vfe0_stream_clk", 2266 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw }, 2267 .num_parents = 1, 2268 .ops = &clk_branch2_ops, 2269 .flags = CLK_SET_RATE_PARENT, 2270 }, 2271 }, 2272}; 2273 2274static struct clk_branch camss_vfe1_stream_clk = { 2275 .halt_reg = 0x3724, 2276 .clkr = { 2277 .enable_reg = 0x3724, 2278 .enable_mask = BIT(0), 2279 .hw.init = &(struct clk_init_data){ 2280 .name = "camss_vfe1_stream_clk", 2281 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw }, 2282 .num_parents = 1, 2283 .ops = &clk_branch2_ops, 2284 .flags = CLK_SET_RATE_PARENT, 2285 }, 2286 }, 2287}; 2288 2289static struct clk_branch camss_cphy_csid0_clk = { 2290 .halt_reg = 0x3730, 2291 .clkr = { 2292 .enable_reg = 0x3730, 2293 .enable_mask = BIT(0), 2294 .hw.init = &(struct clk_init_data){ 2295 .name = "camss_cphy_csid0_clk", 2296 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, 2297 .num_parents = 1, 2298 .ops = &clk_branch2_ops, 2299 .flags = CLK_SET_RATE_PARENT, 2300 }, 2301 }, 2302}; 2303 2304static struct clk_branch camss_cphy_csid1_clk = { 2305 .halt_reg = 0x3734, 2306 .clkr = { 2307 .enable_reg = 0x3734, 2308 .enable_mask = BIT(0), 2309 .hw.init = &(struct clk_init_data){ 2310 .name = "camss_cphy_csid1_clk", 2311 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, 2312 .num_parents = 1, 2313 .ops = &clk_branch2_ops, 2314 .flags = CLK_SET_RATE_PARENT, 2315 }, 2316 }, 2317}; 2318 2319static struct clk_branch camss_cphy_csid2_clk = { 2320 .halt_reg = 0x3738, 2321 .clkr = { 2322 .enable_reg = 0x3738, 2323 .enable_mask = BIT(0), 2324 .hw.init = &(struct clk_init_data){ 2325 .name = "camss_cphy_csid2_clk", 2326 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, 2327 .num_parents = 1, 2328 .ops = &clk_branch2_ops, 2329 .flags = CLK_SET_RATE_PARENT, 2330 }, 2331 }, 2332}; 2333 2334static struct clk_branch camss_cphy_csid3_clk = { 2335 .halt_reg = 0x373c, 2336 .clkr = { 2337 .enable_reg = 0x373c, 2338 .enable_mask = BIT(0), 2339 .hw.init = &(struct clk_init_data){ 2340 .name = "camss_cphy_csid3_clk", 2341 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, 2342 .num_parents = 1, 2343 .ops = &clk_branch2_ops, 2344 .flags = CLK_SET_RATE_PARENT, 2345 }, 2346 }, 2347}; 2348 2349static struct clk_branch camss_csiphy0_clk = { 2350 .halt_reg = 0x3740, 2351 .clkr = { 2352 .enable_reg = 0x3740, 2353 .enable_mask = BIT(0), 2354 .hw.init = &(struct clk_init_data){ 2355 .name = "camss_csiphy0_clk", 2356 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, 2357 .num_parents = 1, 2358 .ops = &clk_branch2_ops, 2359 .flags = CLK_SET_RATE_PARENT, 2360 }, 2361 }, 2362}; 2363 2364static struct clk_branch camss_csiphy1_clk = { 2365 .halt_reg = 0x3744, 2366 .clkr = { 2367 .enable_reg = 0x3744, 2368 .enable_mask = BIT(0), 2369 .hw.init = &(struct clk_init_data){ 2370 .name = "camss_csiphy1_clk", 2371 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, 2372 .num_parents = 1, 2373 .ops = &clk_branch2_ops, 2374 .flags = CLK_SET_RATE_PARENT, 2375 }, 2376 }, 2377}; 2378 2379static struct clk_branch camss_csiphy2_clk = { 2380 .halt_reg = 0x3748, 2381 .clkr = { 2382 .enable_reg = 0x3748, 2383 .enable_mask = BIT(0), 2384 .hw.init = &(struct clk_init_data){ 2385 .name = "camss_csiphy2_clk", 2386 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, 2387 .num_parents = 1, 2388 .ops = &clk_branch2_ops, 2389 .flags = CLK_SET_RATE_PARENT, 2390 }, 2391 }, 2392}; 2393 2394static struct clk_branch fd_core_clk = { 2395 .halt_reg = 0x3b68, 2396 .clkr = { 2397 .enable_reg = 0x3b68, 2398 .enable_mask = BIT(0), 2399 .hw.init = &(struct clk_init_data){ 2400 .name = "fd_core_clk", 2401 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw }, 2402 .num_parents = 1, 2403 .ops = &clk_branch2_ops, 2404 .flags = CLK_SET_RATE_PARENT, 2405 }, 2406 }, 2407}; 2408 2409static struct clk_branch fd_core_uar_clk = { 2410 .halt_reg = 0x3b6c, 2411 .clkr = { 2412 .enable_reg = 0x3b6c, 2413 .enable_mask = BIT(0), 2414 .hw.init = &(struct clk_init_data){ 2415 .name = "fd_core_uar_clk", 2416 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw }, 2417 .num_parents = 1, 2418 .ops = &clk_branch2_ops, 2419 .flags = CLK_SET_RATE_PARENT, 2420 }, 2421 }, 2422}; 2423 2424static struct clk_branch fd_ahb_clk = { 2425 .halt_reg = 0x3b74, 2426 .clkr = { 2427 .enable_reg = 0x3b74, 2428 .enable_mask = BIT(0), 2429 .hw.init = &(struct clk_init_data){ 2430 .name = "fd_ahb_clk", 2431 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2432 .num_parents = 1, 2433 .ops = &clk_branch2_ops, 2434 .flags = CLK_SET_RATE_PARENT, 2435 }, 2436 }, 2437}; 2438 2439static struct clk_branch mnoc_ahb_clk = { 2440 .halt_reg = 0x5024, 2441 .halt_check = BRANCH_HALT_SKIP, 2442 .clkr = { 2443 .enable_reg = 0x5024, 2444 .enable_mask = BIT(0), 2445 .hw.init = &(struct clk_init_data){ 2446 .name = "mnoc_ahb_clk", 2447 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2448 .num_parents = 1, 2449 .ops = &clk_branch2_ops, 2450 .flags = CLK_SET_RATE_PARENT, 2451 }, 2452 }, 2453}; 2454 2455static struct clk_branch bimc_smmu_ahb_clk = { 2456 .halt_reg = 0xe004, 2457 .halt_check = BRANCH_HALT_SKIP, 2458 .hwcg_reg = 0xe004, 2459 .hwcg_bit = 1, 2460 .clkr = { 2461 .enable_reg = 0xe004, 2462 .enable_mask = BIT(0), 2463 .hw.init = &(struct clk_init_data){ 2464 .name = "bimc_smmu_ahb_clk", 2465 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2466 .num_parents = 1, 2467 .ops = &clk_branch2_ops, 2468 .flags = CLK_SET_RATE_PARENT, 2469 }, 2470 }, 2471}; 2472 2473static struct clk_branch bimc_smmu_axi_clk = { 2474 .halt_reg = 0xe008, 2475 .halt_check = BRANCH_HALT_SKIP, 2476 .hwcg_reg = 0xe008, 2477 .hwcg_bit = 1, 2478 .clkr = { 2479 .enable_reg = 0xe008, 2480 .enable_mask = BIT(0), 2481 .hw.init = &(struct clk_init_data){ 2482 .name = "bimc_smmu_axi_clk", 2483 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw }, 2484 .num_parents = 1, 2485 .ops = &clk_branch2_ops, 2486 }, 2487 }, 2488}; 2489 2490static struct clk_branch mnoc_maxi_clk = { 2491 .halt_reg = 0xf004, 2492 .clkr = { 2493 .enable_reg = 0xf004, 2494 .enable_mask = BIT(0), 2495 .hw.init = &(struct clk_init_data){ 2496 .name = "mnoc_maxi_clk", 2497 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw }, 2498 .num_parents = 1, 2499 .ops = &clk_branch2_ops, 2500 .flags = CLK_SET_RATE_PARENT, 2501 }, 2502 }, 2503}; 2504 2505static struct clk_branch vmem_maxi_clk = { 2506 .halt_reg = 0xf064, 2507 .clkr = { 2508 .enable_reg = 0xf064, 2509 .enable_mask = BIT(0), 2510 .hw.init = &(struct clk_init_data){ 2511 .name = "vmem_maxi_clk", 2512 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw }, 2513 .num_parents = 1, 2514 .ops = &clk_branch2_ops, 2515 .flags = CLK_SET_RATE_PARENT, 2516 }, 2517 }, 2518}; 2519 2520static struct clk_branch vmem_ahb_clk = { 2521 .halt_reg = 0xf068, 2522 .clkr = { 2523 .enable_reg = 0xf068, 2524 .enable_mask = BIT(0), 2525 .hw.init = &(struct clk_init_data){ 2526 .name = "vmem_ahb_clk", 2527 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, 2528 .num_parents = 1, 2529 .ops = &clk_branch2_ops, 2530 .flags = CLK_SET_RATE_PARENT, 2531 }, 2532 }, 2533}; 2534 2535static struct gdsc video_top_gdsc = { 2536 .gdscr = 0x1024, 2537 .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 }, 2538 .cxc_count = 3, 2539 .pd = { 2540 .name = "video_top", 2541 }, 2542 .pwrsts = PWRSTS_OFF_ON, 2543}; 2544 2545static struct gdsc video_subcore0_gdsc = { 2546 .gdscr = 0x1040, 2547 .cxcs = (unsigned int []){ 0x1048 }, 2548 .cxc_count = 1, 2549 .pd = { 2550 .name = "video_subcore0", 2551 }, 2552 .parent = &video_top_gdsc.pd, 2553 .pwrsts = PWRSTS_OFF_ON, 2554 .flags = HW_CTRL, 2555}; 2556 2557static struct gdsc video_subcore1_gdsc = { 2558 .gdscr = 0x1044, 2559 .cxcs = (unsigned int []){ 0x104c }, 2560 .cxc_count = 1, 2561 .pd = { 2562 .name = "video_subcore1", 2563 }, 2564 .parent = &video_top_gdsc.pd, 2565 .pwrsts = PWRSTS_OFF_ON, 2566 .flags = HW_CTRL, 2567}; 2568 2569static struct gdsc mdss_gdsc = { 2570 .gdscr = 0x2304, 2571 .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 }, 2572 .cxc_count = 4, 2573 .pd = { 2574 .name = "mdss", 2575 }, 2576 .pwrsts = PWRSTS_OFF_ON, 2577}; 2578 2579static struct gdsc camss_top_gdsc = { 2580 .gdscr = 0x34a0, 2581 .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494, 2582 0x35a8, 0x3868 }, 2583 .cxc_count = 7, 2584 .pd = { 2585 .name = "camss_top", 2586 }, 2587 .pwrsts = PWRSTS_OFF_ON, 2588}; 2589 2590static struct gdsc camss_vfe0_gdsc = { 2591 .gdscr = 0x3664, 2592 .pd = { 2593 .name = "camss_vfe0", 2594 }, 2595 .parent = &camss_top_gdsc.pd, 2596 .pwrsts = PWRSTS_OFF_ON, 2597}; 2598 2599static struct gdsc camss_vfe1_gdsc = { 2600 .gdscr = 0x3674, 2601 .pd = { 2602 .name = "camss_vfe1_gdsc", 2603 }, 2604 .parent = &camss_top_gdsc.pd, 2605 .pwrsts = PWRSTS_OFF_ON, 2606}; 2607 2608static struct gdsc camss_cpp_gdsc = { 2609 .gdscr = 0x36d4, 2610 .pd = { 2611 .name = "camss_cpp", 2612 }, 2613 .parent = &camss_top_gdsc.pd, 2614 .pwrsts = PWRSTS_OFF_ON, 2615}; 2616 2617static struct gdsc bimc_smmu_gdsc = { 2618 .gdscr = 0xe020, 2619 .gds_hw_ctrl = 0xe024, 2620 .cxcs = (unsigned int []){ 0xe008 }, 2621 .cxc_count = 1, 2622 .pd = { 2623 .name = "bimc_smmu", 2624 }, 2625 .pwrsts = PWRSTS_OFF_ON, 2626 .flags = VOTABLE, 2627}; 2628 2629static struct clk_regmap *mmcc_msm8998_clocks[] = { 2630 [MMPLL0] = &mmpll0.clkr, 2631 [MMPLL0_OUT_EVEN] = &mmpll0_out_even.clkr, 2632 [MMPLL1] = &mmpll1.clkr, 2633 [MMPLL1_OUT_EVEN] = &mmpll1_out_even.clkr, 2634 [MMPLL3] = &mmpll3.clkr, 2635 [MMPLL3_OUT_EVEN] = &mmpll3_out_even.clkr, 2636 [MMPLL4] = &mmpll4.clkr, 2637 [MMPLL4_OUT_EVEN] = &mmpll4_out_even.clkr, 2638 [MMPLL5] = &mmpll5.clkr, 2639 [MMPLL5_OUT_EVEN] = &mmpll5_out_even.clkr, 2640 [MMPLL6] = &mmpll6.clkr, 2641 [MMPLL6_OUT_EVEN] = &mmpll6_out_even.clkr, 2642 [MMPLL7] = &mmpll7.clkr, 2643 [MMPLL7_OUT_EVEN] = &mmpll7_out_even.clkr, 2644 [MMPLL10] = &mmpll10.clkr, 2645 [MMPLL10_OUT_EVEN] = &mmpll10_out_even.clkr, 2646 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 2647 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, 2648 [CCI_CLK_SRC] = &cci_clk_src.clkr, 2649 [CPP_CLK_SRC] = &cpp_clk_src.clkr, 2650 [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 2651 [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 2652 [CSI2_CLK_SRC] = &csi2_clk_src.clkr, 2653 [CSI3_CLK_SRC] = &csi3_clk_src.clkr, 2654 [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr, 2655 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 2656 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, 2657 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, 2658 [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr, 2659 [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr, 2660 [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr, 2661 [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr, 2662 [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 2663 [ESC1_CLK_SRC] = &esc1_clk_src.clkr, 2664 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, 2665 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr, 2666 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, 2667 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, 2668 [MAXI_CLK_SRC] = &maxi_clk_src.clkr, 2669 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 2670 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 2671 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, 2672 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, 2673 [MDP_CLK_SRC] = &mdp_clk_src.clkr, 2674 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 2675 [AHB_CLK_SRC] = &ahb_clk_src.clkr, 2676 [AXI_CLK_SRC] = &axi_clk_src.clkr, 2677 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 2678 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, 2679 [ROT_CLK_SRC] = &rot_clk_src.clkr, 2680 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, 2681 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr, 2682 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr, 2683 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 2684 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, 2685 [MISC_AHB_CLK] = &misc_ahb_clk.clkr, 2686 [VIDEO_CORE_CLK] = &video_core_clk.clkr, 2687 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr, 2688 [VIDEO_AXI_CLK] = &video_axi_clk.clkr, 2689 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr, 2690 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr, 2691 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr, 2692 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, 2693 [MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr, 2694 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, 2695 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, 2696 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, 2697 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, 2698 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr, 2699 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, 2700 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, 2701 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, 2702 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, 2703 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, 2704 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, 2705 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, 2706 [MDSS_ROT_CLK] = &mdss_rot_clk.clkr, 2707 [MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr, 2708 [MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr, 2709 [MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr, 2710 [MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr, 2711 [MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr, 2712 [MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr, 2713 [MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr, 2714 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr, 2715 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr, 2716 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr, 2717 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, 2718 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, 2719 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, 2720 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, 2721 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, 2722 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, 2723 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, 2724 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, 2725 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, 2726 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, 2727 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, 2728 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, 2729 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, 2730 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, 2731 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, 2732 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, 2733 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, 2734 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr, 2735 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr, 2736 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, 2737 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, 2738 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, 2739 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, 2740 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, 2741 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr, 2742 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, 2743 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr, 2744 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr, 2745 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr, 2746 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr, 2747 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr, 2748 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr, 2749 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr, 2750 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr, 2751 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr, 2752 [CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr, 2753 [CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr, 2754 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr, 2755 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr, 2756 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, 2757 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, 2758 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr, 2759 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr, 2760 [CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr, 2761 [CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr, 2762 [CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr, 2763 [CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr, 2764 [CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr, 2765 [CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr, 2766 [CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr, 2767 [FD_CORE_CLK] = &fd_core_clk.clkr, 2768 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr, 2769 [FD_AHB_CLK] = &fd_ahb_clk.clkr, 2770 [MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr, 2771 [BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr, 2772 [BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr, 2773 [MNOC_MAXI_CLK] = &mnoc_maxi_clk.clkr, 2774 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr, 2775 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr, 2776}; 2777 2778static struct gdsc *mmcc_msm8998_gdscs[] = { 2779 [VIDEO_TOP_GDSC] = &video_top_gdsc, 2780 [VIDEO_SUBCORE0_GDSC] = &video_subcore0_gdsc, 2781 [VIDEO_SUBCORE1_GDSC] = &video_subcore1_gdsc, 2782 [MDSS_GDSC] = &mdss_gdsc, 2783 [CAMSS_TOP_GDSC] = &camss_top_gdsc, 2784 [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc, 2785 [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc, 2786 [CAMSS_CPP_GDSC] = &camss_cpp_gdsc, 2787 [BIMC_SMMU_GDSC] = &bimc_smmu_gdsc, 2788}; 2789 2790static const struct qcom_reset_map mmcc_msm8998_resets[] = { 2791 [SPDM_BCR] = { 0x200 }, 2792 [SPDM_RM_BCR] = { 0x300 }, 2793 [MISC_BCR] = { 0x320 }, 2794 [VIDEO_TOP_BCR] = { 0x1020 }, 2795 [THROTTLE_VIDEO_BCR] = { 0x1180 }, 2796 [MDSS_BCR] = { 0x2300 }, 2797 [THROTTLE_MDSS_BCR] = { 0x2460 }, 2798 [CAMSS_PHY0_BCR] = { 0x3020 }, 2799 [CAMSS_PHY1_BCR] = { 0x3050 }, 2800 [CAMSS_PHY2_BCR] = { 0x3080 }, 2801 [CAMSS_CSI0_BCR] = { 0x30b0 }, 2802 [CAMSS_CSI0RDI_BCR] = { 0x30d0 }, 2803 [CAMSS_CSI0PIX_BCR] = { 0x30e0 }, 2804 [CAMSS_CSI1_BCR] = { 0x3120 }, 2805 [CAMSS_CSI1RDI_BCR] = { 0x3140 }, 2806 [CAMSS_CSI1PIX_BCR] = { 0x3150 }, 2807 [CAMSS_CSI2_BCR] = { 0x3180 }, 2808 [CAMSS_CSI2RDI_BCR] = { 0x31a0 }, 2809 [CAMSS_CSI2PIX_BCR] = { 0x31b0 }, 2810 [CAMSS_CSI3_BCR] = { 0x31e0 }, 2811 [CAMSS_CSI3RDI_BCR] = { 0x3200 }, 2812 [CAMSS_CSI3PIX_BCR] = { 0x3210 }, 2813 [CAMSS_ISPIF_BCR] = { 0x3220 }, 2814 [CAMSS_CCI_BCR] = { 0x3340 }, 2815 [CAMSS_TOP_BCR] = { 0x3480 }, 2816 [CAMSS_AHB_BCR] = { 0x3488 }, 2817 [CAMSS_MICRO_BCR] = { 0x3490 }, 2818 [CAMSS_JPEG_BCR] = { 0x35a0 }, 2819 [CAMSS_VFE0_BCR] = { 0x3660 }, 2820 [CAMSS_VFE1_BCR] = { 0x3670 }, 2821 [CAMSS_VFE_VBIF_BCR] = { 0x36a0 }, 2822 [CAMSS_CPP_TOP_BCR] = { 0x36c0 }, 2823 [CAMSS_CPP_BCR] = { 0x36d0 }, 2824 [CAMSS_CSI_VFE0_BCR] = { 0x3700 }, 2825 [CAMSS_CSI_VFE1_BCR] = { 0x3710 }, 2826 [CAMSS_FD_BCR] = { 0x3b60 }, 2827 [THROTTLE_CAMSS_BCR] = { 0x3c30 }, 2828 [MNOCAHB_BCR] = { 0x5020 }, 2829 [MNOCAXI_BCR] = { 0xd020 }, 2830 [BMIC_SMMU_BCR] = { 0xe000 }, 2831 [MNOC_MAXI_BCR] = { 0xf000 }, 2832 [VMEM_BCR] = { 0xf060 }, 2833 [BTO_BCR] = { 0x10004 }, 2834}; 2835 2836static const struct regmap_config mmcc_msm8998_regmap_config = { 2837 .reg_bits = 32, 2838 .reg_stride = 4, 2839 .val_bits = 32, 2840 .max_register = 0x10004, 2841 .fast_io = true, 2842}; 2843 2844static const struct qcom_cc_desc mmcc_msm8998_desc = { 2845 .config = &mmcc_msm8998_regmap_config, 2846 .clks = mmcc_msm8998_clocks, 2847 .num_clks = ARRAY_SIZE(mmcc_msm8998_clocks), 2848 .resets = mmcc_msm8998_resets, 2849 .num_resets = ARRAY_SIZE(mmcc_msm8998_resets), 2850 .gdscs = mmcc_msm8998_gdscs, 2851 .num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs), 2852}; 2853 2854static const struct of_device_id mmcc_msm8998_match_table[] = { 2855 { .compatible = "qcom,mmcc-msm8998" }, 2856 { } 2857}; 2858MODULE_DEVICE_TABLE(of, mmcc_msm8998_match_table); 2859 2860static int mmcc_msm8998_probe(struct platform_device *pdev) 2861{ 2862 struct regmap *regmap; 2863 2864 regmap = qcom_cc_map(pdev, &mmcc_msm8998_desc); 2865 if (IS_ERR(regmap)) 2866 return PTR_ERR(regmap); 2867 2868 return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8998_desc, regmap); 2869} 2870 2871static struct platform_driver mmcc_msm8998_driver = { 2872 .probe = mmcc_msm8998_probe, 2873 .driver = { 2874 .name = "mmcc-msm8998", 2875 .of_match_table = mmcc_msm8998_match_table, 2876 }, 2877}; 2878module_platform_driver(mmcc_msm8998_driver); 2879 2880MODULE_DESCRIPTION("QCOM MMCC MSM8998 Driver"); 2881MODULE_LICENSE("GPL v2");
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