mmcc-msm8996.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*x
   3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/kernel.h>
   7#include <linux/bitops.h>
   8#include <linux/err.h>
   9#include <linux/platform_device.h>
  10#include <linux/mod_devicetable.h>
  11#include <linux/module.h>
  12#include <linux/clk-provider.h>
  13#include <linux/regmap.h>
  14
  15#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
  16
  17#include "common.h"
  18#include "clk-regmap.h"
  19#include "clk-regmap-divider.h"
  20#include "clk-alpha-pll.h"
  21#include "clk-rcg.h"
  22#include "clk-branch.h"
  23#include "reset.h"
  24#include "gdsc.h"
  25
  26enum {
  27	P_XO,
  28	P_MMPLL0,
  29	P_GPLL0,
  30	P_GPLL0_DIV,
  31	P_MMPLL1,
  32	P_MMPLL9,
  33	P_MMPLL2,
  34	P_MMPLL8,
  35	P_MMPLL3,
  36	P_DSI0PLL,
  37	P_DSI1PLL,
  38	P_MMPLL5,
  39	P_HDMIPLL,
  40	P_DSI0PLL_BYTE,
  41	P_DSI1PLL_BYTE,
  42	P_MMPLL4,
  43};
  44
  45static struct clk_fixed_factor gpll0_div = {
  46	.mult = 1,
  47	.div = 2,
  48	.hw.init = &(struct clk_init_data){
  49		.name = "gpll0_div",
  50		.parent_data = (const struct clk_parent_data[]){
  51			{ .fw_name = "gpll0", .name = "gpll0" },
  52		},
  53		.num_parents = 1,
  54		.ops = &clk_fixed_factor_ops,
  55	},
  56};
  57
  58static const struct pll_vco mmpll_p_vco[] = {
  59	{ 250000000, 500000000, 3 },
  60	{ 500000000, 1000000000, 2 },
  61	{ 1000000000, 1500000000, 1 },
  62	{ 1500000000, 2000000000, 0 },
  63};
  64
  65static const struct pll_vco mmpll_gfx_vco[] = {
  66	{ 400000000, 1000000000, 2 },
  67	{ 1000000000, 1500000000, 1 },
  68	{ 1500000000, 2000000000, 0 },
  69};
  70
  71static const struct pll_vco mmpll_t_vco[] = {
  72	{ 500000000, 1500000000, 0 },
  73};
  74
  75static struct clk_alpha_pll mmpll0_early = {
  76	.offset = 0x0,
  77	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  78	.vco_table = mmpll_p_vco,
  79	.num_vco = ARRAY_SIZE(mmpll_p_vco),
  80	.clkr = {
  81		.enable_reg = 0x100,
  82		.enable_mask = BIT(0),
  83		.hw.init = &(struct clk_init_data){
  84			.name = "mmpll0_early",
  85			.parent_data = (const struct clk_parent_data[]){
  86				{ .fw_name = "xo", .name = "xo_board" },
  87			},
  88			.num_parents = 1,
  89			.ops = &clk_alpha_pll_ops,
  90		},
  91	},
  92};
  93
  94static struct clk_alpha_pll_postdiv mmpll0 = {
  95	.offset = 0x0,
  96	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  97	.width = 4,
  98	.clkr.hw.init = &(struct clk_init_data){
  99		.name = "mmpll0",
 100		.parent_hws = (const struct clk_hw*[]){
 101			&mmpll0_early.clkr.hw
 102		},
 103		.num_parents = 1,
 104		.ops = &clk_alpha_pll_postdiv_ops,
 105		.flags = CLK_SET_RATE_PARENT,
 106	},
 107};
 108
 109static struct clk_alpha_pll mmpll1_early = {
 110	.offset = 0x30,
 111	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 112	.vco_table = mmpll_p_vco,
 113	.num_vco = ARRAY_SIZE(mmpll_p_vco),
 114	.clkr = {
 115		.enable_reg = 0x100,
 116		.enable_mask = BIT(1),
 117		.hw.init = &(struct clk_init_data){
 118			.name = "mmpll1_early",
 119			.parent_data = (const struct clk_parent_data[]){
 120				{ .fw_name = "xo", .name = "xo_board" },
 121			},
 122			.num_parents = 1,
 123			.ops = &clk_alpha_pll_ops,
 124		}
 125	},
 126};
 127
 128static struct clk_alpha_pll_postdiv mmpll1 = {
 129	.offset = 0x30,
 130	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 131	.width = 4,
 132	.clkr.hw.init = &(struct clk_init_data){
 133		.name = "mmpll1",
 134		.parent_hws = (const struct clk_hw*[]){
 135			&mmpll1_early.clkr.hw
 136		},
 137		.num_parents = 1,
 138		.ops = &clk_alpha_pll_postdiv_ops,
 139		.flags = CLK_SET_RATE_PARENT,
 140	},
 141};
 142
 143static struct clk_alpha_pll mmpll2_early = {
 144	.offset = 0x4100,
 145	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 146	.vco_table = mmpll_gfx_vco,
 147	.num_vco = ARRAY_SIZE(mmpll_gfx_vco),
 148	.clkr.hw.init = &(struct clk_init_data){
 149		.name = "mmpll2_early",
 150		.parent_data = (const struct clk_parent_data[]){
 151			{ .fw_name = "xo", .name = "xo_board" },
 152		},
 153		.num_parents = 1,
 154		.ops = &clk_alpha_pll_ops,
 155	},
 156};
 157
 158static struct clk_alpha_pll_postdiv mmpll2 = {
 159	.offset = 0x4100,
 160	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 161	.width = 4,
 162	.clkr.hw.init = &(struct clk_init_data){
 163		.name = "mmpll2",
 164		.parent_hws = (const struct clk_hw*[]){
 165			&mmpll2_early.clkr.hw
 166		},
 167		.num_parents = 1,
 168		.ops = &clk_alpha_pll_postdiv_ops,
 169		.flags = CLK_SET_RATE_PARENT,
 170	},
 171};
 172
 173static struct clk_alpha_pll mmpll3_early = {
 174	.offset = 0x60,
 175	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 176	.vco_table = mmpll_p_vco,
 177	.num_vco = ARRAY_SIZE(mmpll_p_vco),
 178	.clkr.hw.init = &(struct clk_init_data){
 179		.name = "mmpll3_early",
 180		.parent_data = (const struct clk_parent_data[]){
 181			{ .fw_name = "xo", .name = "xo_board" },
 182		},
 183		.num_parents = 1,
 184		.ops = &clk_alpha_pll_ops,
 185	},
 186};
 187
 188static struct clk_alpha_pll_postdiv mmpll3 = {
 189	.offset = 0x60,
 190	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 191	.width = 4,
 192	.clkr.hw.init = &(struct clk_init_data){
 193		.name = "mmpll3",
 194		.parent_hws = (const struct clk_hw*[]){
 195			&mmpll3_early.clkr.hw
 196		},
 197		.num_parents = 1,
 198		.ops = &clk_alpha_pll_postdiv_ops,
 199		.flags = CLK_SET_RATE_PARENT,
 200	},
 201};
 202
 203static struct clk_alpha_pll mmpll4_early = {
 204	.offset = 0x90,
 205	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 206	.vco_table = mmpll_t_vco,
 207	.num_vco = ARRAY_SIZE(mmpll_t_vco),
 208	.clkr.hw.init = &(struct clk_init_data){
 209		.name = "mmpll4_early",
 210		.parent_data = (const struct clk_parent_data[]){
 211			{ .fw_name = "xo", .name = "xo_board" },
 212		},
 213		.num_parents = 1,
 214		.ops = &clk_alpha_pll_ops,
 215	},
 216};
 217
 218static struct clk_alpha_pll_postdiv mmpll4 = {
 219	.offset = 0x90,
 220	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 221	.width = 2,
 222	.clkr.hw.init = &(struct clk_init_data){
 223		.name = "mmpll4",
 224		.parent_hws = (const struct clk_hw*[]){
 225			&mmpll4_early.clkr.hw
 226		},
 227		.num_parents = 1,
 228		.ops = &clk_alpha_pll_postdiv_ops,
 229		.flags = CLK_SET_RATE_PARENT,
 230	},
 231};
 232
 233static struct clk_alpha_pll mmpll5_early = {
 234	.offset = 0xc0,
 235	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 236	.vco_table = mmpll_p_vco,
 237	.num_vco = ARRAY_SIZE(mmpll_p_vco),
 238	.clkr.hw.init = &(struct clk_init_data){
 239		.name = "mmpll5_early",
 240		.parent_data = (const struct clk_parent_data[]){
 241			{ .fw_name = "xo", .name = "xo_board" },
 242		},
 243		.num_parents = 1,
 244		.ops = &clk_alpha_pll_ops,
 245	},
 246};
 247
 248static struct clk_alpha_pll_postdiv mmpll5 = {
 249	.offset = 0xc0,
 250	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 251	.width = 4,
 252	.clkr.hw.init = &(struct clk_init_data){
 253		.name = "mmpll5",
 254		.parent_hws = (const struct clk_hw*[]){
 255			&mmpll5_early.clkr.hw
 256		},
 257		.num_parents = 1,
 258		.ops = &clk_alpha_pll_postdiv_ops,
 259		.flags = CLK_SET_RATE_PARENT,
 260	},
 261};
 262
 263static struct clk_alpha_pll mmpll8_early = {
 264	.offset = 0x4130,
 265	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 266	.vco_table = mmpll_gfx_vco,
 267	.num_vco = ARRAY_SIZE(mmpll_gfx_vco),
 268	.clkr.hw.init = &(struct clk_init_data){
 269		.name = "mmpll8_early",
 270		.parent_data = (const struct clk_parent_data[]){
 271			{ .fw_name = "xo", .name = "xo_board" },
 272		},
 273		.num_parents = 1,
 274		.ops = &clk_alpha_pll_ops,
 275	},
 276};
 277
 278static struct clk_alpha_pll_postdiv mmpll8 = {
 279	.offset = 0x4130,
 280	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 281	.width = 4,
 282	.clkr.hw.init = &(struct clk_init_data){
 283		.name = "mmpll8",
 284		.parent_hws = (const struct clk_hw*[]){
 285			&mmpll8_early.clkr.hw
 286		},
 287		.num_parents = 1,
 288		.ops = &clk_alpha_pll_postdiv_ops,
 289		.flags = CLK_SET_RATE_PARENT,
 290	},
 291};
 292
 293static struct clk_alpha_pll mmpll9_early = {
 294	.offset = 0x4200,
 295	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 296	.vco_table = mmpll_t_vco,
 297	.num_vco = ARRAY_SIZE(mmpll_t_vco),
 298	.clkr.hw.init = &(struct clk_init_data){
 299		.name = "mmpll9_early",
 300		.parent_data = (const struct clk_parent_data[]){
 301			{ .fw_name = "xo", .name = "xo_board" },
 302		},
 303		.num_parents = 1,
 304		.ops = &clk_alpha_pll_ops,
 305	},
 306};
 307
 308static struct clk_alpha_pll_postdiv mmpll9 = {
 309	.offset = 0x4200,
 310	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 311	.width = 2,
 312	.clkr.hw.init = &(struct clk_init_data){
 313		.name = "mmpll9",
 314		.parent_hws = (const struct clk_hw*[]){
 315			&mmpll9_early.clkr.hw
 316		},
 317		.num_parents = 1,
 318		.ops = &clk_alpha_pll_postdiv_ops,
 319		.flags = CLK_SET_RATE_PARENT,
 320	},
 321};
 322
 323static const struct parent_map mmss_xo_hdmi_map[] = {
 324	{ P_XO, 0 },
 325	{ P_HDMIPLL, 1 }
 326};
 327
 328static const struct clk_parent_data mmss_xo_hdmi[] = {
 329	{ .fw_name = "xo", .name = "xo_board" },
 330	{ .fw_name = "hdmipll", .name = "hdmipll" }
 331};
 332
 333static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
 334	{ P_XO, 0 },
 335	{ P_DSI0PLL, 1 },
 336	{ P_DSI1PLL, 2 }
 337};
 338
 339static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
 340	{ .fw_name = "xo", .name = "xo_board" },
 341	{ .fw_name = "dsi0pll", .name = "dsi0pll" },
 342	{ .fw_name = "dsi1pll", .name = "dsi1pll" }
 343};
 344
 345static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
 346	{ P_XO, 0 },
 347	{ P_GPLL0, 5 },
 348	{ P_GPLL0_DIV, 6 }
 349};
 350
 351static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
 352	{ .fw_name = "xo", .name = "xo_board" },
 353	{ .fw_name = "gpll0", .name = "gpll0" },
 354	{ .hw = &gpll0_div.hw }
 355};
 356
 357static const struct parent_map mmss_xo_dsibyte_map[] = {
 358	{ P_XO, 0 },
 359	{ P_DSI0PLL_BYTE, 1 },
 360	{ P_DSI1PLL_BYTE, 2 }
 361};
 362
 363static const struct clk_parent_data mmss_xo_dsibyte[] = {
 364	{ .fw_name = "xo", .name = "xo_board" },
 365	{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 366	{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" }
 367};
 368
 369static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
 370	{ P_XO, 0 },
 371	{ P_MMPLL0, 1 },
 372	{ P_GPLL0, 5 },
 373	{ P_GPLL0_DIV, 6 }
 374};
 375
 376static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
 377	{ .fw_name = "xo", .name = "xo_board" },
 378	{ .hw = &mmpll0.clkr.hw },
 379	{ .fw_name = "gpll0", .name = "gpll0" },
 380	{ .hw = &gpll0_div.hw }
 381};
 382
 383static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
 384	{ P_XO, 0 },
 385	{ P_MMPLL0, 1 },
 386	{ P_MMPLL1, 2 },
 387	{ P_GPLL0, 5 },
 388	{ P_GPLL0_DIV, 6 }
 389};
 390
 391static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
 392	{ .fw_name = "xo", .name = "xo_board" },
 393	{ .hw = &mmpll0.clkr.hw },
 394	{ .hw = &mmpll1.clkr.hw },
 395	{ .fw_name = "gpll0", .name = "gpll0" },
 396	{ .hw = &gpll0_div.hw }
 397};
 398
 399static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = {
 400	{ P_XO, 0 },
 401	{ P_MMPLL0, 1 },
 402	{ P_MMPLL3, 3 },
 403	{ P_GPLL0, 5 },
 404	{ P_GPLL0_DIV, 6 }
 405};
 406
 407static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = {
 408	{ .fw_name = "xo", .name = "xo_board" },
 409	{ .hw = &mmpll0.clkr.hw },
 410	{ .hw = &mmpll3.clkr.hw },
 411	{ .fw_name = "gpll0", .name = "gpll0" },
 412	{ .hw = &gpll0_div.hw }
 413};
 414
 415static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
 416	{ P_XO, 0 },
 417	{ P_MMPLL0, 1 },
 418	{ P_MMPLL5, 2 },
 419	{ P_GPLL0, 5 },
 420	{ P_GPLL0_DIV, 6 }
 421};
 422
 423static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
 424	{ .fw_name = "xo", .name = "xo_board" },
 425	{ .hw = &mmpll0.clkr.hw },
 426	{ .hw = &mmpll5.clkr.hw },
 427	{ .fw_name = "gpll0", .name = "gpll0" },
 428	{ .hw = &gpll0_div.hw }
 429};
 430
 431static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = {
 432	{ P_XO, 0 },
 433	{ P_MMPLL0, 1 },
 434	{ P_MMPLL4, 3 },
 435	{ P_GPLL0, 5 },
 436	{ P_GPLL0_DIV, 6 }
 437};
 438
 439static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = {
 440	{ .fw_name = "xo", .name = "xo_board" },
 441	{ .hw = &mmpll0.clkr.hw },
 442	{ .hw = &mmpll4.clkr.hw },
 443	{ .fw_name = "gpll0", .name = "gpll0" },
 444	{ .hw = &gpll0_div.hw }
 445};
 446
 447static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = {
 448	{ P_XO, 0 },
 449	{ P_MMPLL0, 1 },
 450	{ P_MMPLL9, 2 },
 451	{ P_MMPLL2, 3 },
 452	{ P_MMPLL8, 4 },
 453	{ P_GPLL0, 5 }
 454};
 455
 456static const struct clk_parent_data mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = {
 457	{ .fw_name = "xo", .name = "xo_board" },
 458	{ .hw = &mmpll0.clkr.hw },
 459	{ .hw = &mmpll9.clkr.hw },
 460	{ .hw = &mmpll2.clkr.hw },
 461	{ .hw = &mmpll8.clkr.hw },
 462	{ .fw_name = "gpll0", .name = "gpll0" },
 463};
 464
 465static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = {
 466	{ P_XO, 0 },
 467	{ P_MMPLL0, 1 },
 468	{ P_MMPLL9, 2 },
 469	{ P_MMPLL2, 3 },
 470	{ P_MMPLL8, 4 },
 471	{ P_GPLL0, 5 },
 472	{ P_GPLL0_DIV, 6 }
 473};
 474
 475static const struct clk_parent_data mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = {
 476	{ .fw_name = "xo", .name = "xo_board" },
 477	{ .hw = &mmpll0.clkr.hw },
 478	{ .hw = &mmpll9.clkr.hw },
 479	{ .hw = &mmpll2.clkr.hw },
 480	{ .hw = &mmpll8.clkr.hw },
 481	{ .fw_name = "gpll0", .name = "gpll0" },
 482	{ .hw = &gpll0_div.hw }
 483};
 484
 485static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = {
 486	{ P_XO, 0 },
 487	{ P_MMPLL0, 1 },
 488	{ P_MMPLL1, 2 },
 489	{ P_MMPLL4, 3 },
 490	{ P_MMPLL3, 4 },
 491	{ P_GPLL0, 5 },
 492	{ P_GPLL0_DIV, 6 }
 493};
 494
 495static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = {
 496	{ .fw_name = "xo", .name = "xo_board" },
 497	{ .hw = &mmpll0.clkr.hw },
 498	{ .hw = &mmpll1.clkr.hw },
 499	{ .hw = &mmpll4.clkr.hw },
 500	{ .hw = &mmpll3.clkr.hw },
 501	{ .fw_name = "gpll0", .name = "gpll0" },
 502	{ .hw = &gpll0_div.hw }
 503};
 504
 505static const struct freq_tbl ftbl_ahb_clk_src[] = {
 506	F(19200000, P_XO, 1, 0, 0),
 507	F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
 508	F(80000000, P_MMPLL0, 10, 0, 0),
 509	{ }
 510};
 511
 512static struct clk_rcg2 ahb_clk_src = {
 513	.cmd_rcgr = 0x5000,
 514	.hid_width = 5,
 515	.parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
 516	.freq_tbl = ftbl_ahb_clk_src,
 517	.clkr.hw.init = &(struct clk_init_data){
 518		.name = "ahb_clk_src",
 519		.parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
 520		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
 521		.ops = &clk_rcg2_ops,
 522	},
 523};
 524
 525static const struct freq_tbl ftbl_axi_clk_src[] = {
 526	F(19200000, P_XO, 1, 0, 0),
 527	F(75000000, P_GPLL0_DIV, 4, 0, 0),
 528	F(100000000, P_GPLL0, 6, 0, 0),
 529	F(171430000, P_GPLL0, 3.5, 0, 0),
 530	F(200000000, P_GPLL0, 3, 0, 0),
 531	F(320000000, P_MMPLL0, 2.5, 0, 0),
 532	F(400000000, P_MMPLL0, 2, 0, 0),
 533	{ }
 534};
 535
 536static struct clk_rcg2 axi_clk_src = {
 537	.cmd_rcgr = 0x5040,
 538	.hid_width = 5,
 539	.parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
 540	.freq_tbl = ftbl_axi_clk_src,
 541	.clkr.hw.init = &(struct clk_init_data){
 542		.name = "axi_clk_src",
 543		.parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
 544		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
 545		.ops = &clk_rcg2_ops,
 546	},
 547};
 548
 549static struct clk_rcg2 maxi_clk_src = {
 550	.cmd_rcgr = 0x5090,
 551	.hid_width = 5,
 552	.parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
 553	.freq_tbl = ftbl_axi_clk_src,
 554	.clkr.hw.init = &(struct clk_init_data){
 555		.name = "maxi_clk_src",
 556		.parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
 557		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
 558		.ops = &clk_rcg2_ops,
 559	},
 560};
 561
 562static struct clk_rcg2_gfx3d gfx3d_clk_src = {
 563	.rcg = {
 564		.cmd_rcgr = 0x4000,
 565		.hid_width = 5,
 566		.parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
 567		.clkr.hw.init = &(struct clk_init_data){
 568			.name = "gfx3d_clk_src",
 569			.parent_data = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
 570			.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0),
 571			.ops = &clk_gfx3d_ops,
 572			.flags = CLK_SET_RATE_PARENT,
 573		},
 574	},
 575	.hws = (struct clk_hw*[]) {
 576		&mmpll9.clkr.hw,
 577		&mmpll2.clkr.hw,
 578		&mmpll8.clkr.hw
 579	},
 580};
 581
 582static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
 583	F(19200000, P_XO, 1, 0, 0),
 584	{ }
 585};
 586
 587static struct clk_rcg2 rbbmtimer_clk_src = {
 588	.cmd_rcgr = 0x4090,
 589	.hid_width = 5,
 590	.parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
 591	.freq_tbl = ftbl_rbbmtimer_clk_src,
 592	.clkr.hw.init = &(struct clk_init_data){
 593		.name = "rbbmtimer_clk_src",
 594		.parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
 595		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
 596		.ops = &clk_rcg2_ops,
 597	},
 598};
 599
 600static struct clk_rcg2 isense_clk_src = {
 601	.cmd_rcgr = 0x4010,
 602	.hid_width = 5,
 603	.parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map,
 604	.clkr.hw.init = &(struct clk_init_data){
 605		.name = "isense_clk_src",
 606		.parent_data = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div,
 607		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div),
 608		.ops = &clk_rcg2_ops,
 609	},
 610};
 611
 612static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
 613	F(19200000, P_XO, 1, 0, 0),
 614	F(50000000, P_GPLL0, 12, 0, 0),
 615	{ }
 616};
 617
 618static struct clk_rcg2 rbcpr_clk_src = {
 619	.cmd_rcgr = 0x4060,
 620	.hid_width = 5,
 621	.parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
 622	.freq_tbl = ftbl_rbcpr_clk_src,
 623	.clkr.hw.init = &(struct clk_init_data){
 624		.name = "rbcpr_clk_src",
 625		.parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
 626		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
 627		.ops = &clk_rcg2_ops,
 628	},
 629};
 630
 631static const struct freq_tbl ftbl_video_core_clk_src[] = {
 632	F(75000000, P_GPLL0_DIV, 4, 0, 0),
 633	F(150000000, P_GPLL0, 4, 0, 0),
 634	F(346666667, P_MMPLL3, 3, 0, 0),
 635	F(520000000, P_MMPLL3, 2, 0, 0),
 636	{ }
 637};
 638
 639static struct clk_rcg2 video_core_clk_src = {
 640	.cmd_rcgr = 0x1000,
 641	.mnd_width = 8,
 642	.hid_width = 5,
 643	.parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
 644	.freq_tbl = ftbl_video_core_clk_src,
 645	.clkr.hw.init = &(struct clk_init_data){
 646		.name = "video_core_clk_src",
 647		.parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
 648		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
 649		.ops = &clk_rcg2_ops,
 650	},
 651};
 652
 653static struct clk_rcg2 video_subcore0_clk_src = {
 654	.cmd_rcgr = 0x1060,
 655	.mnd_width = 8,
 656	.hid_width = 5,
 657	.parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
 658	.freq_tbl = ftbl_video_core_clk_src,
 659	.clkr.hw.init = &(struct clk_init_data){
 660		.name = "video_subcore0_clk_src",
 661		.parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
 662		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
 663		.ops = &clk_rcg2_ops,
 664	},
 665};
 666
 667static struct clk_rcg2 video_subcore1_clk_src = {
 668	.cmd_rcgr = 0x1080,
 669	.mnd_width = 8,
 670	.hid_width = 5,
 671	.parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
 672	.freq_tbl = ftbl_video_core_clk_src,
 673	.clkr.hw.init = &(struct clk_init_data){
 674		.name = "video_subcore1_clk_src",
 675		.parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
 676		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
 677		.ops = &clk_rcg2_ops,
 678	},
 679};
 680
 681static struct clk_rcg2 pclk0_clk_src = {
 682	.cmd_rcgr = 0x2000,
 683	.mnd_width = 8,
 684	.hid_width = 5,
 685	.parent_map = mmss_xo_dsi0pll_dsi1pll_map,
 686	.clkr.hw.init = &(struct clk_init_data){
 687		.name = "pclk0_clk_src",
 688		.parent_data = mmss_xo_dsi0pll_dsi1pll,
 689		.num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
 690		.ops = &clk_pixel_ops,
 691		.flags = CLK_SET_RATE_PARENT,
 692	},
 693};
 694
 695static struct clk_rcg2 pclk1_clk_src = {
 696	.cmd_rcgr = 0x2020,
 697	.mnd_width = 8,
 698	.hid_width = 5,
 699	.parent_map = mmss_xo_dsi0pll_dsi1pll_map,
 700	.clkr.hw.init = &(struct clk_init_data){
 701		.name = "pclk1_clk_src",
 702		.parent_data = mmss_xo_dsi0pll_dsi1pll,
 703		.num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
 704		.ops = &clk_pixel_ops,
 705		.flags = CLK_SET_RATE_PARENT,
 706	},
 707};
 708
 709static const struct freq_tbl ftbl_mdp_clk_src[] = {
 710	F(85714286, P_GPLL0, 7, 0, 0),
 711	F(100000000, P_GPLL0, 6, 0, 0),
 712	F(150000000, P_GPLL0, 4, 0, 0),
 713	F(171428571, P_GPLL0, 3.5, 0, 0),
 714	F(200000000, P_GPLL0, 3, 0, 0),
 715	F(275000000, P_MMPLL5, 3, 0, 0),
 716	F(300000000, P_GPLL0, 2, 0, 0),
 717	F(330000000, P_MMPLL5, 2.5, 0, 0),
 718	F(412500000, P_MMPLL5, 2, 0, 0),
 719	{ }
 720};
 721
 722static struct clk_rcg2 mdp_clk_src = {
 723	.cmd_rcgr = 0x2040,
 724	.hid_width = 5,
 725	.parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
 726	.freq_tbl = ftbl_mdp_clk_src,
 727	.clkr.hw.init = &(struct clk_init_data){
 728		.name = "mdp_clk_src",
 729		.parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
 730		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
 731		.ops = &clk_rcg2_ops,
 732	},
 733};
 734
 735static const struct freq_tbl extpclk_freq_tbl[] = {
 736	{ .src = P_HDMIPLL },
 737	{ }
 738};
 739
 740static struct clk_rcg2 extpclk_clk_src = {
 741	.cmd_rcgr = 0x2060,
 742	.hid_width = 5,
 743	.parent_map = mmss_xo_hdmi_map,
 744	.freq_tbl = extpclk_freq_tbl,
 745	.clkr.hw.init = &(struct clk_init_data){
 746		.name = "extpclk_clk_src",
 747		.parent_data = mmss_xo_hdmi,
 748		.num_parents = ARRAY_SIZE(mmss_xo_hdmi),
 749		.ops = &clk_byte_ops,
 750		.flags = CLK_SET_RATE_PARENT,
 751	},
 752};
 753
 754static const struct freq_tbl ftbl_mdss_vsync_clk[] = {
 755	F(19200000, P_XO, 1, 0, 0),
 756	{ }
 757};
 758
 759static struct clk_rcg2 vsync_clk_src = {
 760	.cmd_rcgr = 0x2080,
 761	.hid_width = 5,
 762	.parent_map = mmss_xo_gpll0_gpll0_div_map,
 763	.freq_tbl = ftbl_mdss_vsync_clk,
 764	.clkr.hw.init = &(struct clk_init_data){
 765		.name = "vsync_clk_src",
 766		.parent_data = mmss_xo_gpll0_gpll0_div,
 767		.num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
 768		.ops = &clk_rcg2_ops,
 769	},
 770};
 771
 772static const struct freq_tbl ftbl_mdss_hdmi_clk[] = {
 773	F(19200000, P_XO, 1, 0, 0),
 774	{ }
 775};
 776
 777static struct clk_rcg2 hdmi_clk_src = {
 778	.cmd_rcgr = 0x2100,
 779	.hid_width = 5,
 780	.parent_map = mmss_xo_gpll0_gpll0_div_map,
 781	.freq_tbl = ftbl_mdss_hdmi_clk,
 782	.clkr.hw.init = &(struct clk_init_data){
 783		.name = "hdmi_clk_src",
 784		.parent_data = mmss_xo_gpll0_gpll0_div,
 785		.num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
 786		.ops = &clk_rcg2_ops,
 787	},
 788};
 789
 790static struct clk_rcg2 byte0_clk_src = {
 791	.cmd_rcgr = 0x2120,
 792	.hid_width = 5,
 793	.parent_map = mmss_xo_dsibyte_map,
 794	.clkr.hw.init = &(struct clk_init_data){
 795		.name = "byte0_clk_src",
 796		.parent_data = mmss_xo_dsibyte,
 797		.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
 798		.ops = &clk_byte2_ops,
 799		.flags = CLK_SET_RATE_PARENT,
 800	},
 801};
 802
 803static struct clk_rcg2 byte1_clk_src = {
 804	.cmd_rcgr = 0x2140,
 805	.hid_width = 5,
 806	.parent_map = mmss_xo_dsibyte_map,
 807	.clkr.hw.init = &(struct clk_init_data){
 808		.name = "byte1_clk_src",
 809		.parent_data = mmss_xo_dsibyte,
 810		.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
 811		.ops = &clk_byte2_ops,
 812		.flags = CLK_SET_RATE_PARENT,
 813	},
 814};
 815
 816static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
 817	F(19200000, P_XO, 1, 0, 0),
 818	{ }
 819};
 820
 821static struct clk_rcg2 esc0_clk_src = {
 822	.cmd_rcgr = 0x2160,
 823	.hid_width = 5,
 824	.parent_map = mmss_xo_dsibyte_map,
 825	.freq_tbl = ftbl_mdss_esc0_1_clk,
 826	.clkr.hw.init = &(struct clk_init_data){
 827		.name = "esc0_clk_src",
 828		.parent_data = mmss_xo_dsibyte,
 829		.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
 830		.ops = &clk_rcg2_ops,
 831	},
 832};
 833
 834static struct clk_rcg2 esc1_clk_src = {
 835	.cmd_rcgr = 0x2180,
 836	.hid_width = 5,
 837	.parent_map = mmss_xo_dsibyte_map,
 838	.freq_tbl = ftbl_mdss_esc0_1_clk,
 839	.clkr.hw.init = &(struct clk_init_data){
 840		.name = "esc1_clk_src",
 841		.parent_data = mmss_xo_dsibyte,
 842		.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
 843		.ops = &clk_rcg2_ops,
 844	},
 845};
 846
 847static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
 848	F(10000, P_XO, 16, 1, 120),
 849	F(24000, P_XO, 16, 1, 50),
 850	F(6000000, P_GPLL0_DIV, 10, 1, 5),
 851	F(12000000, P_GPLL0_DIV, 1, 1, 25),
 852	F(13000000, P_GPLL0_DIV, 2, 13, 150),
 853	F(24000000, P_GPLL0_DIV, 1, 2, 25),
 854	{ }
 855};
 856
 857static struct clk_rcg2 camss_gp0_clk_src = {
 858	.cmd_rcgr = 0x3420,
 859	.mnd_width = 8,
 860	.hid_width = 5,
 861	.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 862	.freq_tbl = ftbl_camss_gp0_clk_src,
 863	.clkr.hw.init = &(struct clk_init_data){
 864		.name = "camss_gp0_clk_src",
 865		.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 866		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
 867		.ops = &clk_rcg2_ops,
 868	},
 869};
 870
 871static struct clk_rcg2 camss_gp1_clk_src = {
 872	.cmd_rcgr = 0x3450,
 873	.mnd_width = 8,
 874	.hid_width = 5,
 875	.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 876	.freq_tbl = ftbl_camss_gp0_clk_src,
 877	.clkr.hw.init = &(struct clk_init_data){
 878		.name = "camss_gp1_clk_src",
 879		.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 880		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
 881		.ops = &clk_rcg2_ops,
 882	},
 883};
 884
 885static const struct freq_tbl ftbl_mclk0_clk_src[] = {
 886	F(4800000, P_XO, 4, 0, 0),
 887	F(6000000, P_GPLL0_DIV, 10, 1, 5),
 888	F(8000000, P_GPLL0_DIV, 1, 2, 75),
 889	F(9600000, P_XO, 2, 0, 0),
 890	F(16666667, P_GPLL0_DIV, 2, 1, 9),
 891	F(19200000, P_XO, 1, 0, 0),
 892	F(24000000, P_GPLL0_DIV, 1, 2, 25),
 893	F(33333333, P_GPLL0_DIV, 1, 1, 9),
 894	F(48000000, P_GPLL0, 1, 2, 25),
 895	F(66666667, P_GPLL0, 1, 1, 9),
 896	{ }
 897};
 898
 899static struct clk_rcg2 mclk0_clk_src = {
 900	.cmd_rcgr = 0x3360,
 901	.mnd_width = 8,
 902	.hid_width = 5,
 903	.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 904	.freq_tbl = ftbl_mclk0_clk_src,
 905	.clkr.hw.init = &(struct clk_init_data){
 906		.name = "mclk0_clk_src",
 907		.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 908		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
 909		.ops = &clk_rcg2_ops,
 910	},
 911};
 912
 913static struct clk_rcg2 mclk1_clk_src = {
 914	.cmd_rcgr = 0x3390,
 915	.mnd_width = 8,
 916	.hid_width = 5,
 917	.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 918	.freq_tbl = ftbl_mclk0_clk_src,
 919	.clkr.hw.init = &(struct clk_init_data){
 920		.name = "mclk1_clk_src",
 921		.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 922		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
 923		.ops = &clk_rcg2_ops,
 924	},
 925};
 926
 927static struct clk_rcg2 mclk2_clk_src = {
 928	.cmd_rcgr = 0x33c0,
 929	.mnd_width = 8,
 930	.hid_width = 5,
 931	.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 932	.freq_tbl = ftbl_mclk0_clk_src,
 933	.clkr.hw.init = &(struct clk_init_data){
 934		.name = "mclk2_clk_src",
 935		.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 936		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
 937		.ops = &clk_rcg2_ops,
 938	},
 939};
 940
 941static struct clk_rcg2 mclk3_clk_src = {
 942	.cmd_rcgr = 0x33f0,
 943	.mnd_width = 8,
 944	.hid_width = 5,
 945	.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 946	.freq_tbl = ftbl_mclk0_clk_src,
 947	.clkr.hw.init = &(struct clk_init_data){
 948		.name = "mclk3_clk_src",
 949		.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 950		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
 951		.ops = &clk_rcg2_ops,
 952	},
 953};
 954
 955static const struct freq_tbl ftbl_cci_clk_src[] = {
 956	F(19200000, P_XO, 1, 0, 0),
 957	F(37500000, P_GPLL0, 16, 0, 0),
 958	F(50000000, P_GPLL0, 12, 0, 0),
 959	F(100000000, P_GPLL0, 6, 0, 0),
 960	{ }
 961};
 962
 963static struct clk_rcg2 cci_clk_src = {
 964	.cmd_rcgr = 0x3300,
 965	.mnd_width = 8,
 966	.hid_width = 5,
 967	.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
 968	.freq_tbl = ftbl_cci_clk_src,
 969	.clkr.hw.init = &(struct clk_init_data){
 970		.name = "cci_clk_src",
 971		.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
 972		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
 973		.ops = &clk_rcg2_ops,
 974	},
 975};
 976
 977static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
 978	F(100000000, P_GPLL0_DIV, 3, 0, 0),
 979	F(200000000, P_GPLL0, 3, 0, 0),
 980	F(266666667, P_MMPLL0, 3, 0, 0),
 981	{ }
 982};
 983
 984static struct clk_rcg2 csi0phytimer_clk_src = {
 985	.cmd_rcgr = 0x3000,
 986	.hid_width = 5,
 987	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
 988	.freq_tbl = ftbl_csi0phytimer_clk_src,
 989	.clkr.hw.init = &(struct clk_init_data){
 990		.name = "csi0phytimer_clk_src",
 991		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
 992		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
 993		.ops = &clk_rcg2_ops,
 994	},
 995};
 996
 997static struct clk_rcg2 csi1phytimer_clk_src = {
 998	.cmd_rcgr = 0x3030,
 999	.hid_width = 5,
1000	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1001	.freq_tbl = ftbl_csi0phytimer_clk_src,
1002	.clkr.hw.init = &(struct clk_init_data){
1003		.name = "csi1phytimer_clk_src",
1004		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1005		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1006		.ops = &clk_rcg2_ops,
1007	},
1008};
1009
1010static struct clk_rcg2 csi2phytimer_clk_src = {
1011	.cmd_rcgr = 0x3060,
1012	.hid_width = 5,
1013	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1014	.freq_tbl = ftbl_csi0phytimer_clk_src,
1015	.clkr.hw.init = &(struct clk_init_data){
1016		.name = "csi2phytimer_clk_src",
1017		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1018		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1019		.ops = &clk_rcg2_ops,
1020	},
1021};
1022
1023static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = {
1024	F(100000000, P_GPLL0_DIV, 3, 0, 0),
1025	F(200000000, P_GPLL0, 3, 0, 0),
1026	F(320000000, P_MMPLL4, 3, 0, 0),
1027	F(384000000, P_MMPLL4, 2.5, 0, 0),
1028	{ }
1029};
1030
1031static struct clk_rcg2 csiphy0_3p_clk_src = {
1032	.cmd_rcgr = 0x3240,
1033	.hid_width = 5,
1034	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1035	.freq_tbl = ftbl_csiphy0_3p_clk_src,
1036	.clkr.hw.init = &(struct clk_init_data){
1037		.name = "csiphy0_3p_clk_src",
1038		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1039		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1040		.ops = &clk_rcg2_ops,
1041	},
1042};
1043
1044static struct clk_rcg2 csiphy1_3p_clk_src = {
1045	.cmd_rcgr = 0x3260,
1046	.hid_width = 5,
1047	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1048	.freq_tbl = ftbl_csiphy0_3p_clk_src,
1049	.clkr.hw.init = &(struct clk_init_data){
1050		.name = "csiphy1_3p_clk_src",
1051		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1052		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1053		.ops = &clk_rcg2_ops,
1054	},
1055};
1056
1057static struct clk_rcg2 csiphy2_3p_clk_src = {
1058	.cmd_rcgr = 0x3280,
1059	.hid_width = 5,
1060	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1061	.freq_tbl = ftbl_csiphy0_3p_clk_src,
1062	.clkr.hw.init = &(struct clk_init_data){
1063		.name = "csiphy2_3p_clk_src",
1064		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1065		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1066		.ops = &clk_rcg2_ops,
1067	},
1068};
1069
1070static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
1071	F(75000000, P_GPLL0_DIV, 4, 0, 0),
1072	F(150000000, P_GPLL0, 4, 0, 0),
1073	F(228571429, P_MMPLL0, 3.5, 0, 0),
1074	F(266666667, P_MMPLL0, 3, 0, 0),
1075	F(320000000, P_MMPLL0, 2.5, 0, 0),
1076	F(480000000, P_MMPLL4, 2, 0, 0),
1077	{ }
1078};
1079
1080static struct clk_rcg2 jpeg0_clk_src = {
1081	.cmd_rcgr = 0x3500,
1082	.hid_width = 5,
1083	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1084	.freq_tbl = ftbl_jpeg0_clk_src,
1085	.clkr.hw.init = &(struct clk_init_data){
1086		.name = "jpeg0_clk_src",
1087		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1088		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1089		.ops = &clk_rcg2_ops,
1090	},
1091};
1092
1093static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
1094	F(75000000, P_GPLL0_DIV, 4, 0, 0),
1095	F(150000000, P_GPLL0, 4, 0, 0),
1096	F(228571429, P_MMPLL0, 3.5, 0, 0),
1097	F(266666667, P_MMPLL0, 3, 0, 0),
1098	F(320000000, P_MMPLL0, 2.5, 0, 0),
1099	{ }
1100};
1101
1102static struct clk_rcg2 jpeg2_clk_src = {
1103	.cmd_rcgr = 0x3540,
1104	.hid_width = 5,
1105	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1106	.freq_tbl = ftbl_jpeg2_clk_src,
1107	.clkr.hw.init = &(struct clk_init_data){
1108		.name = "jpeg2_clk_src",
1109		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1110		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1111		.ops = &clk_rcg2_ops,
1112	},
1113};
1114
1115static struct clk_rcg2 jpeg_dma_clk_src = {
1116	.cmd_rcgr = 0x3560,
1117	.hid_width = 5,
1118	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1119	.freq_tbl = ftbl_jpeg0_clk_src,
1120	.clkr.hw.init = &(struct clk_init_data){
1121		.name = "jpeg_dma_clk_src",
1122		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1123		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1124		.ops = &clk_rcg2_ops,
1125	},
1126};
1127
1128static const struct freq_tbl ftbl_vfe0_clk_src[] = {
1129	F(75000000, P_GPLL0_DIV, 4, 0, 0),
1130	F(100000000, P_GPLL0_DIV, 3, 0, 0),
1131	F(300000000, P_GPLL0, 2, 0, 0),
1132	F(320000000, P_MMPLL0, 2.5, 0, 0),
1133	F(480000000, P_MMPLL4, 2, 0, 0),
1134	F(600000000, P_GPLL0, 1, 0, 0),
1135	{ }
1136};
1137
1138static struct clk_rcg2 vfe0_clk_src = {
1139	.cmd_rcgr = 0x3600,
1140	.hid_width = 5,
1141	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1142	.freq_tbl = ftbl_vfe0_clk_src,
1143	.clkr.hw.init = &(struct clk_init_data){
1144		.name = "vfe0_clk_src",
1145		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1146		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1147		.ops = &clk_rcg2_ops,
1148	},
1149};
1150
1151static struct clk_rcg2 vfe1_clk_src = {
1152	.cmd_rcgr = 0x3620,
1153	.hid_width = 5,
1154	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1155	.freq_tbl = ftbl_vfe0_clk_src,
1156	.clkr.hw.init = &(struct clk_init_data){
1157		.name = "vfe1_clk_src",
1158		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1159		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1160		.ops = &clk_rcg2_ops,
1161	},
1162};
1163
1164static const struct freq_tbl ftbl_cpp_clk_src[] = {
1165	F(100000000, P_GPLL0_DIV, 3, 0, 0),
1166	F(200000000, P_GPLL0, 3, 0, 0),
1167	F(320000000, P_MMPLL0, 2.5, 0, 0),
1168	F(480000000, P_MMPLL4, 2, 0, 0),
1169	F(640000000, P_MMPLL4, 1.5, 0, 0),
1170	{ }
1171};
1172
1173static struct clk_rcg2 cpp_clk_src = {
1174	.cmd_rcgr = 0x3640,
1175	.hid_width = 5,
1176	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1177	.freq_tbl = ftbl_cpp_clk_src,
1178	.clkr.hw.init = &(struct clk_init_data){
1179		.name = "cpp_clk_src",
1180		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1181		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1182		.ops = &clk_rcg2_ops,
1183	},
1184};
1185
1186static const struct freq_tbl ftbl_csi0_clk_src[] = {
1187	F(100000000, P_GPLL0_DIV, 3, 0, 0),
1188	F(200000000, P_GPLL0, 3, 0, 0),
1189	F(266666667, P_MMPLL0, 3, 0, 0),
1190	F(480000000, P_MMPLL4, 2, 0, 0),
1191	F(600000000, P_GPLL0, 1, 0, 0),
1192	{ }
1193};
1194
1195static struct clk_rcg2 csi0_clk_src = {
1196	.cmd_rcgr = 0x3090,
1197	.hid_width = 5,
1198	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1199	.freq_tbl = ftbl_csi0_clk_src,
1200	.clkr.hw.init = &(struct clk_init_data){
1201		.name = "csi0_clk_src",
1202		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1203		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1204		.ops = &clk_rcg2_ops,
1205	},
1206};
1207
1208static struct clk_rcg2 csi1_clk_src = {
1209	.cmd_rcgr = 0x3100,
1210	.hid_width = 5,
1211	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1212	.freq_tbl = ftbl_csi0_clk_src,
1213	.clkr.hw.init = &(struct clk_init_data){
1214		.name = "csi1_clk_src",
1215		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1216		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1217		.ops = &clk_rcg2_ops,
1218	},
1219};
1220
1221static struct clk_rcg2 csi2_clk_src = {
1222	.cmd_rcgr = 0x3160,
1223	.hid_width = 5,
1224	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1225	.freq_tbl = ftbl_csi0_clk_src,
1226	.clkr.hw.init = &(struct clk_init_data){
1227		.name = "csi2_clk_src",
1228		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1229		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1230		.ops = &clk_rcg2_ops,
1231	},
1232};
1233
1234static struct clk_rcg2 csi3_clk_src = {
1235	.cmd_rcgr = 0x31c0,
1236	.hid_width = 5,
1237	.parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1238	.freq_tbl = ftbl_csi0_clk_src,
1239	.clkr.hw.init = &(struct clk_init_data){
1240		.name = "csi3_clk_src",
1241		.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1242		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1243		.ops = &clk_rcg2_ops,
1244	},
1245};
1246
1247static const struct freq_tbl ftbl_fd_core_clk_src[] = {
1248	F(100000000, P_GPLL0_DIV, 3, 0, 0),
1249	F(200000000, P_GPLL0, 3, 0, 0),
1250	F(400000000, P_MMPLL0, 2, 0, 0),
1251	{ }
1252};
1253
1254static struct clk_rcg2 fd_core_clk_src = {
1255	.cmd_rcgr = 0x3b00,
1256	.hid_width = 5,
1257	.parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
1258	.freq_tbl = ftbl_fd_core_clk_src,
1259	.clkr.hw.init = &(struct clk_init_data){
1260		.name = "fd_core_clk_src",
1261		.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
1262		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
1263		.ops = &clk_rcg2_ops,
1264	},
1265};
1266
1267static struct clk_branch mmss_mmagic_ahb_clk = {
1268	.halt_reg = 0x5024,
1269	.clkr = {
1270		.enable_reg = 0x5024,
1271		.enable_mask = BIT(0),
1272		.hw.init = &(struct clk_init_data){
1273			.name = "mmss_mmagic_ahb_clk",
1274			.parent_hws = (const struct clk_hw*[]){
1275				&ahb_clk_src.clkr.hw
1276			},
1277			.num_parents = 1,
1278			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1279			.ops = &clk_branch2_ops,
1280		},
1281	},
1282};
1283
1284static struct clk_branch mmss_mmagic_cfg_ahb_clk = {
1285	.halt_reg = 0x5054,
1286	.clkr = {
1287		.enable_reg = 0x5054,
1288		.enable_mask = BIT(0),
1289		.hw.init = &(struct clk_init_data){
1290			.name = "mmss_mmagic_cfg_ahb_clk",
1291			.parent_hws = (const struct clk_hw*[]){
1292				&ahb_clk_src.clkr.hw
1293			},
1294			.num_parents = 1,
1295			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1296			.ops = &clk_branch2_ops,
1297		},
1298	},
1299};
1300
1301static struct clk_branch mmss_misc_ahb_clk = {
1302	.halt_reg = 0x5018,
1303	.clkr = {
1304		.enable_reg = 0x5018,
1305		.enable_mask = BIT(0),
1306		.hw.init = &(struct clk_init_data){
1307			.name = "mmss_misc_ahb_clk",
1308			.parent_hws = (const struct clk_hw*[]){
1309				&ahb_clk_src.clkr.hw
1310			},
1311			.num_parents = 1,
1312			.flags = CLK_SET_RATE_PARENT,
1313			.ops = &clk_branch2_ops,
1314		},
1315	},
1316};
1317
1318static struct clk_branch mmss_misc_cxo_clk = {
1319	.halt_reg = 0x5014,
1320	.clkr = {
1321		.enable_reg = 0x5014,
1322		.enable_mask = BIT(0),
1323		.hw.init = &(struct clk_init_data){
1324			.name = "mmss_misc_cxo_clk",
1325			.parent_data = (const struct clk_parent_data[]){
1326				{ .fw_name = "xo", .name = "xo_board" },
1327			},
1328			.num_parents = 1,
1329			.ops = &clk_branch2_ops,
1330		},
1331	},
1332};
1333
1334static struct clk_branch mmss_mmagic_maxi_clk = {
1335	.halt_reg = 0x5074,
1336	.clkr = {
1337		.enable_reg = 0x5074,
1338		.enable_mask = BIT(0),
1339		.hw.init = &(struct clk_init_data){
1340			.name = "mmss_mmagic_maxi_clk",
1341			.parent_hws = (const struct clk_hw*[]){
1342				&maxi_clk_src.clkr.hw
1343			},
1344			.num_parents = 1,
1345			.flags = CLK_SET_RATE_PARENT,
1346			.ops = &clk_branch2_ops,
1347		},
1348	},
1349};
1350
1351static struct clk_branch mmagic_camss_axi_clk = {
1352	.halt_reg = 0x3c44,
1353	.clkr = {
1354		.enable_reg = 0x3c44,
1355		.enable_mask = BIT(0),
1356		.hw.init = &(struct clk_init_data){
1357			.name = "mmagic_camss_axi_clk",
1358			.parent_hws = (const struct clk_hw*[]){
1359				&axi_clk_src.clkr.hw
1360			},
1361			.num_parents = 1,
1362			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1363			.ops = &clk_branch2_ops,
1364		},
1365	},
1366};
1367
1368static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = {
1369	.halt_reg = 0x3c48,
1370	.clkr = {
1371		.enable_reg = 0x3c48,
1372		.enable_mask = BIT(0),
1373		.hw.init = &(struct clk_init_data){
1374			.name = "mmagic_camss_noc_cfg_ahb_clk",
1375			.parent_data = (const struct clk_parent_data[]){
1376				{ .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1377			},
1378			.num_parents = 1,
1379			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1380			.ops = &clk_branch2_ops,
1381		},
1382	},
1383};
1384
1385static struct clk_branch smmu_vfe_ahb_clk = {
1386	.halt_reg = 0x3c04,
1387	.clkr = {
1388		.enable_reg = 0x3c04,
1389		.enable_mask = BIT(0),
1390		.hw.init = &(struct clk_init_data){
1391			.name = "smmu_vfe_ahb_clk",
1392			.parent_hws = (const struct clk_hw*[]){
1393				&ahb_clk_src.clkr.hw
1394			},
1395			.num_parents = 1,
1396			.flags = CLK_SET_RATE_PARENT,
1397			.ops = &clk_branch2_ops,
1398		},
1399	},
1400};
1401
1402static struct clk_branch smmu_vfe_axi_clk = {
1403	.halt_reg = 0x3c08,
1404	.clkr = {
1405		.enable_reg = 0x3c08,
1406		.enable_mask = BIT(0),
1407		.hw.init = &(struct clk_init_data){
1408			.name = "smmu_vfe_axi_clk",
1409			.parent_hws = (const struct clk_hw*[]){
1410				&axi_clk_src.clkr.hw
1411			},
1412			.num_parents = 1,
1413			.flags = CLK_SET_RATE_PARENT,
1414			.ops = &clk_branch2_ops,
1415		},
1416	},
1417};
1418
1419static struct clk_branch smmu_cpp_ahb_clk = {
1420	.halt_reg = 0x3c14,
1421	.clkr = {
1422		.enable_reg = 0x3c14,
1423		.enable_mask = BIT(0),
1424		.hw.init = &(struct clk_init_data){
1425			.name = "smmu_cpp_ahb_clk",
1426			.parent_hws = (const struct clk_hw*[]){
1427				&ahb_clk_src.clkr.hw
1428			},
1429			.num_parents = 1,
1430			.flags = CLK_SET_RATE_PARENT,
1431			.ops = &clk_branch2_ops,
1432		},
1433	},
1434};
1435
1436static struct clk_branch smmu_cpp_axi_clk = {
1437	.halt_reg = 0x3c18,
1438	.clkr = {
1439		.enable_reg = 0x3c18,
1440		.enable_mask = BIT(0),
1441		.hw.init = &(struct clk_init_data){
1442			.name = "smmu_cpp_axi_clk",
1443			.parent_hws = (const struct clk_hw*[]){
1444				&axi_clk_src.clkr.hw
1445			},
1446			.num_parents = 1,
1447			.flags = CLK_SET_RATE_PARENT,
1448			.ops = &clk_branch2_ops,
1449		},
1450	},
1451};
1452
1453static struct clk_branch smmu_jpeg_ahb_clk = {
1454	.halt_reg = 0x3c24,
1455	.clkr = {
1456		.enable_reg = 0x3c24,
1457		.enable_mask = BIT(0),
1458		.hw.init = &(struct clk_init_data){
1459			.name = "smmu_jpeg_ahb_clk",
1460			.parent_hws = (const struct clk_hw*[]){
1461				&ahb_clk_src.clkr.hw
1462			},
1463			.num_parents = 1,
1464			.flags = CLK_SET_RATE_PARENT,
1465			.ops = &clk_branch2_ops,
1466		},
1467	},
1468};
1469
1470static struct clk_branch smmu_jpeg_axi_clk = {
1471	.halt_reg = 0x3c28,
1472	.clkr = {
1473		.enable_reg = 0x3c28,
1474		.enable_mask = BIT(0),
1475		.hw.init = &(struct clk_init_data){
1476			.name = "smmu_jpeg_axi_clk",
1477			.parent_hws = (const struct clk_hw*[]){
1478				&axi_clk_src.clkr.hw
1479			},
1480			.num_parents = 1,
1481			.flags = CLK_SET_RATE_PARENT,
1482			.ops = &clk_branch2_ops,
1483		},
1484	},
1485};
1486
1487static struct clk_branch mmagic_mdss_axi_clk = {
1488	.halt_reg = 0x2474,
1489	.clkr = {
1490		.enable_reg = 0x2474,
1491		.enable_mask = BIT(0),
1492		.hw.init = &(struct clk_init_data){
1493			.name = "mmagic_mdss_axi_clk",
1494			.parent_hws = (const struct clk_hw*[]){
1495				&axi_clk_src.clkr.hw
1496			},
1497			.num_parents = 1,
1498			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1499			.ops = &clk_branch2_ops,
1500		},
1501	},
1502};
1503
1504static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = {
1505	.halt_reg = 0x2478,
1506	.clkr = {
1507		.enable_reg = 0x2478,
1508		.enable_mask = BIT(0),
1509		.hw.init = &(struct clk_init_data){
1510			.name = "mmagic_mdss_noc_cfg_ahb_clk",
1511			.parent_data = (const struct clk_parent_data[]){
1512				{ .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1513			},
1514			.num_parents = 1,
1515			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1516			.ops = &clk_branch2_ops,
1517		},
1518	},
1519};
1520
1521static struct clk_branch smmu_rot_ahb_clk = {
1522	.halt_reg = 0x2444,
1523	.clkr = {
1524		.enable_reg = 0x2444,
1525		.enable_mask = BIT(0),
1526		.hw.init = &(struct clk_init_data){
1527			.name = "smmu_rot_ahb_clk",
1528			.parent_hws = (const struct clk_hw*[]){
1529				&ahb_clk_src.clkr.hw
1530			},
1531			.num_parents = 1,
1532			.flags = CLK_SET_RATE_PARENT,
1533			.ops = &clk_branch2_ops,
1534		},
1535	},
1536};
1537
1538static struct clk_branch smmu_rot_axi_clk = {
1539	.halt_reg = 0x2448,
1540	.clkr = {
1541		.enable_reg = 0x2448,
1542		.enable_mask = BIT(0),
1543		.hw.init = &(struct clk_init_data){
1544			.name = "smmu_rot_axi_clk",
1545			.parent_hws = (const struct clk_hw*[]){
1546				&axi_clk_src.clkr.hw
1547			},
1548			.num_parents = 1,
1549			.flags = CLK_SET_RATE_PARENT,
1550			.ops = &clk_branch2_ops,
1551		},
1552	},
1553};
1554
1555static struct clk_branch smmu_mdp_ahb_clk = {
1556	.halt_reg = 0x2454,
1557	.clkr = {
1558		.enable_reg = 0x2454,
1559		.enable_mask = BIT(0),
1560		.hw.init = &(struct clk_init_data){
1561			.name = "smmu_mdp_ahb_clk",
1562			.parent_hws = (const struct clk_hw*[]){
1563				&ahb_clk_src.clkr.hw
1564			},
1565			.num_parents = 1,
1566			.flags = CLK_SET_RATE_PARENT,
1567			.ops = &clk_branch2_ops,
1568		},
1569	},
1570};
1571
1572static struct clk_branch smmu_mdp_axi_clk = {
1573	.halt_reg = 0x2458,
1574	.clkr = {
1575		.enable_reg = 0x2458,
1576		.enable_mask = BIT(0),
1577		.hw.init = &(struct clk_init_data){
1578			.name = "smmu_mdp_axi_clk",
1579			.parent_hws = (const struct clk_hw*[]){
1580				&axi_clk_src.clkr.hw
1581			},
1582			.num_parents = 1,
1583			.flags = CLK_SET_RATE_PARENT,
1584			.ops = &clk_branch2_ops,
1585		},
1586	},
1587};
1588
1589static struct clk_branch mmagic_video_axi_clk = {
1590	.halt_reg = 0x1194,
1591	.clkr = {
1592		.enable_reg = 0x1194,
1593		.enable_mask = BIT(0),
1594		.hw.init = &(struct clk_init_data){
1595			.name = "mmagic_video_axi_clk",
1596			.parent_hws = (const struct clk_hw*[]){
1597				&axi_clk_src.clkr.hw
1598			},
1599			.num_parents = 1,
1600			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1601			.ops = &clk_branch2_ops,
1602		},
1603	},
1604};
1605
1606static struct clk_branch mmagic_video_noc_cfg_ahb_clk = {
1607	.halt_reg = 0x1198,
1608	.clkr = {
1609		.enable_reg = 0x1198,
1610		.enable_mask = BIT(0),
1611		.hw.init = &(struct clk_init_data){
1612			.name = "mmagic_video_noc_cfg_ahb_clk",
1613			.parent_data = (const struct clk_parent_data[]){
1614				{ .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1615			},
1616			.num_parents = 1,
1617			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1618			.ops = &clk_branch2_ops,
1619		},
1620	},
1621};
1622
1623static struct clk_branch smmu_video_ahb_clk = {
1624	.halt_reg = 0x1174,
1625	.clkr = {
1626		.enable_reg = 0x1174,
1627		.enable_mask = BIT(0),
1628		.hw.init = &(struct clk_init_data){
1629			.name = "smmu_video_ahb_clk",
1630			.parent_hws = (const struct clk_hw*[]){
1631				&ahb_clk_src.clkr.hw
1632			},
1633			.num_parents = 1,
1634			.flags = CLK_SET_RATE_PARENT,
1635			.ops = &clk_branch2_ops,
1636		},
1637	},
1638};
1639
1640static struct clk_branch smmu_video_axi_clk = {
1641	.halt_reg = 0x1178,
1642	.clkr = {
1643		.enable_reg = 0x1178,
1644		.enable_mask = BIT(0),
1645		.hw.init = &(struct clk_init_data){
1646			.name = "smmu_video_axi_clk",
1647			.parent_hws = (const struct clk_hw*[]){
1648				&axi_clk_src.clkr.hw
1649			},
1650			.num_parents = 1,
1651			.flags = CLK_SET_RATE_PARENT,
1652			.ops = &clk_branch2_ops,
1653		},
1654	},
1655};
1656
1657static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = {
1658	.halt_reg = 0x5298,
1659	.clkr = {
1660		.enable_reg = 0x5298,
1661		.enable_mask = BIT(0),
1662		.hw.init = &(struct clk_init_data){
1663			.name = "mmagic_bimc_noc_cfg_ahb_clk",
1664			.parent_data = (const struct clk_parent_data[]){
1665				{ .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1666			},
1667			.num_parents = 1,
1668			.flags = CLK_SET_RATE_PARENT,
1669			.ops = &clk_branch2_ops,
1670		},
1671	},
1672};
1673
1674static struct clk_branch gpu_gx_gfx3d_clk = {
1675	.halt_reg = 0x4028,
1676	.clkr = {
1677		.enable_reg = 0x4028,
1678		.enable_mask = BIT(0),
1679		.hw.init = &(struct clk_init_data){
1680			.name = "gpu_gx_gfx3d_clk",
1681			.parent_hws = (const struct clk_hw*[]){
1682				&gfx3d_clk_src.rcg.clkr.hw
1683			},
1684			.num_parents = 1,
1685			.flags = CLK_SET_RATE_PARENT,
1686			.ops = &clk_branch2_ops,
1687		},
1688	},
1689};
1690
1691static struct clk_branch gpu_gx_rbbmtimer_clk = {
1692	.halt_reg = 0x40b0,
1693	.clkr = {
1694		.enable_reg = 0x40b0,
1695		.enable_mask = BIT(0),
1696		.hw.init = &(struct clk_init_data){
1697			.name = "gpu_gx_rbbmtimer_clk",
1698			.parent_hws = (const struct clk_hw*[]){
1699				&rbbmtimer_clk_src.clkr.hw
1700			},
1701			.num_parents = 1,
1702			.flags = CLK_SET_RATE_PARENT,
1703			.ops = &clk_branch2_ops,
1704		},
1705	},
1706};
1707
1708static struct clk_branch gpu_ahb_clk = {
1709	.halt_reg = 0x403c,
1710	.clkr = {
1711		.enable_reg = 0x403c,
1712		.enable_mask = BIT(0),
1713		.hw.init = &(struct clk_init_data){
1714			.name = "gpu_ahb_clk",
1715			.parent_hws = (const struct clk_hw*[]){
1716				&ahb_clk_src.clkr.hw
1717			},
1718			.num_parents = 1,
1719			.flags = CLK_SET_RATE_PARENT,
1720			.ops = &clk_branch2_ops,
1721		},
1722	},
1723};
1724
1725static struct clk_branch gpu_aon_isense_clk = {
1726	.halt_reg = 0x4044,
1727	.clkr = {
1728		.enable_reg = 0x4044,
1729		.enable_mask = BIT(0),
1730		.hw.init = &(struct clk_init_data){
1731			.name = "gpu_aon_isense_clk",
1732			.parent_hws = (const struct clk_hw*[]){
1733				&isense_clk_src.clkr.hw
1734			},
1735			.num_parents = 1,
1736			.flags = CLK_SET_RATE_PARENT,
1737			.ops = &clk_branch2_ops,
1738		},
1739	},
1740};
1741
1742static struct clk_branch vmem_maxi_clk = {
1743	.halt_reg = 0x1204,
1744	.clkr = {
1745		.enable_reg = 0x1204,
1746		.enable_mask = BIT(0),
1747		.hw.init = &(struct clk_init_data){
1748			.name = "vmem_maxi_clk",
1749			.parent_hws = (const struct clk_hw*[]){
1750				&maxi_clk_src.clkr.hw
1751			},
1752			.num_parents = 1,
1753			.flags = CLK_SET_RATE_PARENT,
1754			.ops = &clk_branch2_ops,
1755		},
1756	},
1757};
1758
1759static struct clk_branch vmem_ahb_clk = {
1760	.halt_reg = 0x1208,
1761	.clkr = {
1762		.enable_reg = 0x1208,
1763		.enable_mask = BIT(0),
1764		.hw.init = &(struct clk_init_data){
1765			.name = "vmem_ahb_clk",
1766			.parent_hws = (const struct clk_hw*[]){
1767				&ahb_clk_src.clkr.hw
1768			},
1769			.num_parents = 1,
1770			.flags = CLK_SET_RATE_PARENT,
1771			.ops = &clk_branch2_ops,
1772		},
1773	},
1774};
1775
1776static struct clk_branch mmss_rbcpr_clk = {
1777	.halt_reg = 0x4084,
1778	.clkr = {
1779		.enable_reg = 0x4084,
1780		.enable_mask = BIT(0),
1781		.hw.init = &(struct clk_init_data){
1782			.name = "mmss_rbcpr_clk",
1783			.parent_hws = (const struct clk_hw*[]){
1784				&rbcpr_clk_src.clkr.hw
1785			},
1786			.num_parents = 1,
1787			.flags = CLK_SET_RATE_PARENT,
1788			.ops = &clk_branch2_ops,
1789		},
1790	},
1791};
1792
1793static struct clk_branch mmss_rbcpr_ahb_clk = {
1794	.halt_reg = 0x4088,
1795	.clkr = {
1796		.enable_reg = 0x4088,
1797		.enable_mask = BIT(0),
1798		.hw.init = &(struct clk_init_data){
1799			.name = "mmss_rbcpr_ahb_clk",
1800			.parent_hws = (const struct clk_hw*[]){
1801				&ahb_clk_src.clkr.hw
1802			},
1803			.num_parents = 1,
1804			.flags = CLK_SET_RATE_PARENT,
1805			.ops = &clk_branch2_ops,
1806		},
1807	},
1808};
1809
1810static struct clk_branch video_core_clk = {
1811	.halt_reg = 0x1028,
1812	.clkr = {
1813		.enable_reg = 0x1028,
1814		.enable_mask = BIT(0),
1815		.hw.init = &(struct clk_init_data){
1816			.name = "video_core_clk",
1817			.parent_hws = (const struct clk_hw*[]){
1818				&video_core_clk_src.clkr.hw
1819			},
1820			.num_parents = 1,
1821			.flags = CLK_SET_RATE_PARENT,
1822			.ops = &clk_branch2_ops,
1823		},
1824	},
1825};
1826
1827static struct clk_branch video_axi_clk = {
1828	.halt_reg = 0x1034,
1829	.clkr = {
1830		.enable_reg = 0x1034,
1831		.enable_mask = BIT(0),
1832		.hw.init = &(struct clk_init_data){
1833			.name = "video_axi_clk",
1834			.parent_hws = (const struct clk_hw*[]){
1835				&axi_clk_src.clkr.hw
1836			},
1837			.num_parents = 1,
1838			.flags = CLK_SET_RATE_PARENT,
1839			.ops = &clk_branch2_ops,
1840		},
1841	},
1842};
1843
1844static struct clk_branch video_maxi_clk = {
1845	.halt_reg = 0x1038,
1846	.clkr = {
1847		.enable_reg = 0x1038,
1848		.enable_mask = BIT(0),
1849		.hw.init = &(struct clk_init_data){
1850			.name = "video_maxi_clk",
1851			.parent_hws = (const struct clk_hw*[]){
1852				&maxi_clk_src.clkr.hw
1853			},
1854			.num_parents = 1,
1855			.flags = CLK_SET_RATE_PARENT,
1856			.ops = &clk_branch2_ops,
1857		},
1858	},
1859};
1860
1861static struct clk_branch video_ahb_clk = {
1862	.halt_reg = 0x1030,
1863	.clkr = {
1864		.enable_reg = 0x1030,
1865		.enable_mask = BIT(0),
1866		.hw.init = &(struct clk_init_data){
1867			.name = "video_ahb_clk",
1868			.parent_hws = (const struct clk_hw*[]){
1869				&ahb_clk_src.clkr.hw
1870			},
1871			.num_parents = 1,
1872			.flags = CLK_SET_RATE_PARENT,
1873			.ops = &clk_branch2_ops,
1874		},
1875	},
1876};
1877
1878static struct clk_branch video_subcore0_clk = {
1879	.halt_reg = 0x1048,
1880	.clkr = {
1881		.enable_reg = 0x1048,
1882		.enable_mask = BIT(0),
1883		.hw.init = &(struct clk_init_data){
1884			.name = "video_subcore0_clk",
1885			.parent_hws = (const struct clk_hw*[]){
1886				&video_subcore0_clk_src.clkr.hw
1887			},
1888			.num_parents = 1,
1889			.flags = CLK_SET_RATE_PARENT,
1890			.ops = &clk_branch2_ops,
1891		},
1892	},
1893};
1894
1895static struct clk_branch video_subcore1_clk = {
1896	.halt_reg = 0x104c,
1897	.clkr = {
1898		.enable_reg = 0x104c,
1899		.enable_mask = BIT(0),
1900		.hw.init = &(struct clk_init_data){
1901			.name = "video_subcore1_clk",
1902			.parent_hws = (const struct clk_hw*[]){
1903				&video_subcore1_clk_src.clkr.hw
1904			},
1905			.num_parents = 1,
1906			.flags = CLK_SET_RATE_PARENT,
1907			.ops = &clk_branch2_ops,
1908		},
1909	},
1910};
1911
1912static struct clk_branch mdss_ahb_clk = {
1913	.halt_reg = 0x2308,
1914	.clkr = {
1915		.enable_reg = 0x2308,
1916		.enable_mask = BIT(0),
1917		.hw.init = &(struct clk_init_data){
1918			.name = "mdss_ahb_clk",
1919			.parent_hws = (const struct clk_hw*[]){
1920				&ahb_clk_src.clkr.hw
1921			},
1922			.num_parents = 1,
1923			.flags = CLK_SET_RATE_PARENT,
1924			.ops = &clk_branch2_ops,
1925		},
1926	},
1927};
1928
1929static struct clk_branch mdss_hdmi_ahb_clk = {
1930	.halt_reg = 0x230c,
1931	.clkr = {
1932		.enable_reg = 0x230c,
1933		.enable_mask = BIT(0),
1934		.hw.init = &(struct clk_init_data){
1935			.name = "mdss_hdmi_ahb_clk",
1936			.parent_hws = (const struct clk_hw*[]){
1937				&ahb_clk_src.clkr.hw
1938			},
1939			.num_parents = 1,
1940			.flags = CLK_SET_RATE_PARENT,
1941			.ops = &clk_branch2_ops,
1942		},
1943	},
1944};
1945
1946static struct clk_branch mdss_axi_clk = {
1947	.halt_reg = 0x2310,
1948	.clkr = {
1949		.enable_reg = 0x2310,
1950		.enable_mask = BIT(0),
1951		.hw.init = &(struct clk_init_data){
1952			.name = "mdss_axi_clk",
1953			.parent_hws = (const struct clk_hw*[]){
1954				&axi_clk_src.clkr.hw
1955			},
1956			.num_parents = 1,
1957			.flags = CLK_SET_RATE_PARENT,
1958			.ops = &clk_branch2_ops,
1959		},
1960	},
1961};
1962
1963static struct clk_branch mdss_pclk0_clk = {
1964	.halt_reg = 0x2314,
1965	.clkr = {
1966		.enable_reg = 0x2314,
1967		.enable_mask = BIT(0),
1968		.hw.init = &(struct clk_init_data){
1969			.name = "mdss_pclk0_clk",
1970			.parent_hws = (const struct clk_hw*[]){
1971				&pclk0_clk_src.clkr.hw
1972			},
1973			.num_parents = 1,
1974			.flags = CLK_SET_RATE_PARENT,
1975			.ops = &clk_branch2_ops,
1976		},
1977	},
1978};
1979
1980static struct clk_branch mdss_pclk1_clk = {
1981	.halt_reg = 0x2318,
1982	.clkr = {
1983		.enable_reg = 0x2318,
1984		.enable_mask = BIT(0),
1985		.hw.init = &(struct clk_init_data){
1986			.name = "mdss_pclk1_clk",
1987			.parent_hws = (const struct clk_hw*[]){
1988				&pclk1_clk_src.clkr.hw
1989			},
1990			.num_parents = 1,
1991			.flags = CLK_SET_RATE_PARENT,
1992			.ops = &clk_branch2_ops,
1993		},
1994	},
1995};
1996
1997static struct clk_branch mdss_mdp_clk = {
1998	.halt_reg = 0x231c,
1999	.clkr = {
2000		.enable_reg = 0x231c,
2001		.enable_mask = BIT(0),
2002		.hw.init = &(struct clk_init_data){
2003			.name = "mdss_mdp_clk",
2004			.parent_hws = (const struct clk_hw*[]){
2005				&mdp_clk_src.clkr.hw
2006			},
2007			.num_parents = 1,
2008			.flags = CLK_SET_RATE_PARENT,
2009			.ops = &clk_branch2_ops,
2010		},
2011	},
2012};
2013
2014static struct clk_branch mdss_extpclk_clk = {
2015	.halt_reg = 0x2324,
2016	.clkr = {
2017		.enable_reg = 0x2324,
2018		.enable_mask = BIT(0),
2019		.hw.init = &(struct clk_init_data){
2020			.name = "mdss_extpclk_clk",
2021			.parent_hws = (const struct clk_hw*[]){
2022				&extpclk_clk_src.clkr.hw
2023			},
2024			.num_parents = 1,
2025			.flags = CLK_SET_RATE_PARENT,
2026			.ops = &clk_branch2_ops,
2027		},
2028	},
2029};
2030
2031static struct clk_branch mdss_vsync_clk = {
2032	.halt_reg = 0x2328,
2033	.clkr = {
2034		.enable_reg = 0x2328,
2035		.enable_mask = BIT(0),
2036		.hw.init = &(struct clk_init_data){
2037			.name = "mdss_vsync_clk",
2038			.parent_hws = (const struct clk_hw*[]){
2039				&vsync_clk_src.clkr.hw
2040			},
2041			.num_parents = 1,
2042			.flags = CLK_SET_RATE_PARENT,
2043			.ops = &clk_branch2_ops,
2044		},
2045	},
2046};
2047
2048static struct clk_branch mdss_hdmi_clk = {
2049	.halt_reg = 0x2338,
2050	.clkr = {
2051		.enable_reg = 0x2338,
2052		.enable_mask = BIT(0),
2053		.hw.init = &(struct clk_init_data){
2054			.name = "mdss_hdmi_clk",
2055			.parent_hws = (const struct clk_hw*[]){
2056				&hdmi_clk_src.clkr.hw
2057			},
2058			.num_parents = 1,
2059			.flags = CLK_SET_RATE_PARENT,
2060			.ops = &clk_branch2_ops,
2061		},
2062	},
2063};
2064
2065static struct clk_branch mdss_byte0_clk = {
2066	.halt_reg = 0x233c,
2067	.clkr = {
2068		.enable_reg = 0x233c,
2069		.enable_mask = BIT(0),
2070		.hw.init = &(struct clk_init_data){
2071			.name = "mdss_byte0_clk",
2072			.parent_hws = (const struct clk_hw*[]){
2073				&byte0_clk_src.clkr.hw
2074			},
2075			.num_parents = 1,
2076			.flags = CLK_SET_RATE_PARENT,
2077			.ops = &clk_branch2_ops,
2078		},
2079	},
2080};
2081
2082static struct clk_branch mdss_byte1_clk = {
2083	.halt_reg = 0x2340,
2084	.clkr = {
2085		.enable_reg = 0x2340,
2086		.enable_mask = BIT(0),
2087		.hw.init = &(struct clk_init_data){
2088			.name = "mdss_byte1_clk",
2089			.parent_hws = (const struct clk_hw*[]){
2090				&byte1_clk_src.clkr.hw
2091			},
2092			.num_parents = 1,
2093			.flags = CLK_SET_RATE_PARENT,
2094			.ops = &clk_branch2_ops,
2095		},
2096	},
2097};
2098
2099static struct clk_branch mdss_esc0_clk = {
2100	.halt_reg = 0x2344,
2101	.clkr = {
2102		.enable_reg = 0x2344,
2103		.enable_mask = BIT(0),
2104		.hw.init = &(struct clk_init_data){
2105			.name = "mdss_esc0_clk",
2106			.parent_hws = (const struct clk_hw*[]){
2107				&esc0_clk_src.clkr.hw
2108			},
2109			.num_parents = 1,
2110			.flags = CLK_SET_RATE_PARENT,
2111			.ops = &clk_branch2_ops,
2112		},
2113	},
2114};
2115
2116static struct clk_branch mdss_esc1_clk = {
2117	.halt_reg = 0x2348,
2118	.clkr = {
2119		.enable_reg = 0x2348,
2120		.enable_mask = BIT(0),
2121		.hw.init = &(struct clk_init_data){
2122			.name = "mdss_esc1_clk",
2123			.parent_hws = (const struct clk_hw*[]){
2124				&esc1_clk_src.clkr.hw
2125			},
2126			.num_parents = 1,
2127			.flags = CLK_SET_RATE_PARENT,
2128			.ops = &clk_branch2_ops,
2129		},
2130	},
2131};
2132
2133static struct clk_branch camss_top_ahb_clk = {
2134	.halt_reg = 0x3484,
2135	.clkr = {
2136		.enable_reg = 0x3484,
2137		.enable_mask = BIT(0),
2138		.hw.init = &(struct clk_init_data){
2139			.name = "camss_top_ahb_clk",
2140			.parent_hws = (const struct clk_hw*[]){
2141				&ahb_clk_src.clkr.hw
2142			},
2143			.num_parents = 1,
2144			.flags = CLK_SET_RATE_PARENT,
2145			.ops = &clk_branch2_ops,
2146		},
2147	},
2148};
2149
2150static struct clk_branch camss_ahb_clk = {
2151	.halt_reg = 0x348c,
2152	.clkr = {
2153		.enable_reg = 0x348c,
2154		.enable_mask = BIT(0),
2155		.hw.init = &(struct clk_init_data){
2156			.name = "camss_ahb_clk",
2157			.parent_hws = (const struct clk_hw*[]){
2158				&ahb_clk_src.clkr.hw
2159			},
2160			.num_parents = 1,
2161			.flags = CLK_SET_RATE_PARENT,
2162			.ops = &clk_branch2_ops,
2163		},
2164	},
2165};
2166
2167static struct clk_branch camss_micro_ahb_clk = {
2168	.halt_reg = 0x3494,
2169	.clkr = {
2170		.enable_reg = 0x3494,
2171		.enable_mask = BIT(0),
2172		.hw.init = &(struct clk_init_data){
2173			.name = "camss_micro_ahb_clk",
2174			.parent_hws = (const struct clk_hw*[]){
2175				&ahb_clk_src.clkr.hw
2176			},
2177			.num_parents = 1,
2178			.flags = CLK_SET_RATE_PARENT,
2179			.ops = &clk_branch2_ops,
2180		},
2181	},
2182};
2183
2184static struct clk_branch camss_gp0_clk = {
2185	.halt_reg = 0x3444,
2186	.clkr = {
2187		.enable_reg = 0x3444,
2188		.enable_mask = BIT(0),
2189		.hw.init = &(struct clk_init_data){
2190			.name = "camss_gp0_clk",
2191			.parent_hws = (const struct clk_hw*[]){
2192				&camss_gp0_clk_src.clkr.hw
2193			},
2194			.num_parents = 1,
2195			.flags = CLK_SET_RATE_PARENT,
2196			.ops = &clk_branch2_ops,
2197		},
2198	},
2199};
2200
2201static struct clk_branch camss_gp1_clk = {
2202	.halt_reg = 0x3474,
2203	.clkr = {
2204		.enable_reg = 0x3474,
2205		.enable_mask = BIT(0),
2206		.hw.init = &(struct clk_init_data){
2207			.name = "camss_gp1_clk",
2208			.parent_hws = (const struct clk_hw*[]){
2209				&camss_gp1_clk_src.clkr.hw
2210			},
2211			.num_parents = 1,
2212			.flags = CLK_SET_RATE_PARENT,
2213			.ops = &clk_branch2_ops,
2214		},
2215	},
2216};
2217
2218static struct clk_branch camss_mclk0_clk = {
2219	.halt_reg = 0x3384,
2220	.clkr = {
2221		.enable_reg = 0x3384,
2222		.enable_mask = BIT(0),
2223		.hw.init = &(struct clk_init_data){
2224			.name = "camss_mclk0_clk",
2225			.parent_hws = (const struct clk_hw*[]){
2226				&mclk0_clk_src.clkr.hw
2227			},
2228			.num_parents = 1,
2229			.flags = CLK_SET_RATE_PARENT,
2230			.ops = &clk_branch2_ops,
2231		},
2232	},
2233};
2234
2235static struct clk_branch camss_mclk1_clk = {
2236	.halt_reg = 0x33b4,
2237	.clkr = {
2238		.enable_reg = 0x33b4,
2239		.enable_mask = BIT(0),
2240		.hw.init = &(struct clk_init_data){
2241			.name = "camss_mclk1_clk",
2242			.parent_hws = (const struct clk_hw*[]){
2243				&mclk1_clk_src.clkr.hw
2244			},
2245			.num_parents = 1,
2246			.flags = CLK_SET_RATE_PARENT,
2247			.ops = &clk_branch2_ops,
2248		},
2249	},
2250};
2251
2252static struct clk_branch camss_mclk2_clk = {
2253	.halt_reg = 0x33e4,
2254	.clkr = {
2255		.enable_reg = 0x33e4,
2256		.enable_mask = BIT(0),
2257		.hw.init = &(struct clk_init_data){
2258			.name = "camss_mclk2_clk",
2259			.parent_hws = (const struct clk_hw*[]){
2260				&mclk2_clk_src.clkr.hw
2261			},
2262			.num_parents = 1,
2263			.flags = CLK_SET_RATE_PARENT,
2264			.ops = &clk_branch2_ops,
2265		},
2266	},
2267};
2268
2269static struct clk_branch camss_mclk3_clk = {
2270	.halt_reg = 0x3414,
2271	.clkr = {
2272		.enable_reg = 0x3414,
2273		.enable_mask = BIT(0),
2274		.hw.init = &(struct clk_init_data){
2275			.name = "camss_mclk3_clk",
2276			.parent_hws = (const struct clk_hw*[]){
2277				&mclk3_clk_src.clkr.hw
2278			},
2279			.num_parents = 1,
2280			.flags = CLK_SET_RATE_PARENT,
2281			.ops = &clk_branch2_ops,
2282		},
2283	},
2284};
2285
2286static struct clk_branch camss_cci_clk = {
2287	.halt_reg = 0x3344,
2288	.clkr = {
2289		.enable_reg = 0x3344,
2290		.enable_mask = BIT(0),
2291		.hw.init = &(struct clk_init_data){
2292			.name = "camss_cci_clk",
2293			.parent_hws = (const struct clk_hw*[]){
2294				&cci_clk_src.clkr.hw
2295			},
2296			.num_parents = 1,
2297			.flags = CLK_SET_RATE_PARENT,
2298			.ops = &clk_branch2_ops,
2299		},
2300	},
2301};
2302
2303static struct clk_branch camss_cci_ahb_clk = {
2304	.halt_reg = 0x3348,
2305	.clkr = {
2306		.enable_reg = 0x3348,
2307		.enable_mask = BIT(0),
2308		.hw.init = &(struct clk_init_data){
2309			.name = "camss_cci_ahb_clk",
2310			.parent_hws = (const struct clk_hw*[]){
2311				&ahb_clk_src.clkr.hw
2312			},
2313			.num_parents = 1,
2314			.flags = CLK_SET_RATE_PARENT,
2315			.ops = &clk_branch2_ops,
2316		},
2317	},
2318};
2319
2320static struct clk_branch camss_csi0phytimer_clk = {
2321	.halt_reg = 0x3024,
2322	.clkr = {
2323		.enable_reg = 0x3024,
2324		.enable_mask = BIT(0),
2325		.hw.init = &(struct clk_init_data){
2326			.name = "camss_csi0phytimer_clk",
2327			.parent_hws = (const struct clk_hw*[]){
2328				&csi0phytimer_clk_src.clkr.hw
2329			},
2330			.num_parents = 1,
2331			.flags = CLK_SET_RATE_PARENT,
2332			.ops = &clk_branch2_ops,
2333		},
2334	},
2335};
2336
2337static struct clk_branch camss_csi1phytimer_clk = {
2338	.halt_reg = 0x3054,
2339	.clkr = {
2340		.enable_reg = 0x3054,
2341		.enable_mask = BIT(0),
2342		.hw.init = &(struct clk_init_data){
2343			.name = "camss_csi1phytimer_clk",
2344			.parent_hws = (const struct clk_hw*[]){
2345				&csi1phytimer_clk_src.clkr.hw
2346			},
2347			.num_parents = 1,
2348			.flags = CLK_SET_RATE_PARENT,
2349			.ops = &clk_branch2_ops,
2350		},
2351	},
2352};
2353
2354static struct clk_branch camss_csi2phytimer_clk = {
2355	.halt_reg = 0x3084,
2356	.clkr = {
2357		.enable_reg = 0x3084,
2358		.enable_mask = BIT(0),
2359		.hw.init = &(struct clk_init_data){
2360			.name = "camss_csi2phytimer_clk",
2361			.parent_hws = (const struct clk_hw*[]){
2362				&csi2phytimer_clk_src.clkr.hw
2363			},
2364			.num_parents = 1,
2365			.flags = CLK_SET_RATE_PARENT,
2366			.ops = &clk_branch2_ops,
2367		},
2368	},
2369};
2370
2371static struct clk_branch camss_csiphy0_3p_clk = {
2372	.halt_reg = 0x3234,
2373	.clkr = {
2374		.enable_reg = 0x3234,
2375		.enable_mask = BIT(0),
2376		.hw.init = &(struct clk_init_data){
2377			.name = "camss_csiphy0_3p_clk",
2378			.parent_hws = (const struct clk_hw*[]){
2379				&csiphy0_3p_clk_src.clkr.hw
2380			},
2381			.num_parents = 1,
2382			.flags = CLK_SET_RATE_PARENT,
2383			.ops = &clk_branch2_ops,
2384		},
2385	},
2386};
2387
2388static struct clk_branch camss_csiphy1_3p_clk = {
2389	.halt_reg = 0x3254,
2390	.clkr = {
2391		.enable_reg = 0x3254,
2392		.enable_mask = BIT(0),
2393		.hw.init = &(struct clk_init_data){
2394			.name = "camss_csiphy1_3p_clk",
2395			.parent_hws = (const struct clk_hw*[]){
2396				&csiphy1_3p_clk_src.clkr.hw
2397			},
2398			.num_parents = 1,
2399			.flags = CLK_SET_RATE_PARENT,
2400			.ops = &clk_branch2_ops,
2401		},
2402	},
2403};
2404
2405static struct clk_branch camss_csiphy2_3p_clk = {
2406	.halt_reg = 0x3274,
2407	.clkr = {
2408		.enable_reg = 0x3274,
2409		.enable_mask = BIT(0),
2410		.hw.init = &(struct clk_init_data){
2411			.name = "camss_csiphy2_3p_clk",
2412			.parent_hws = (const struct clk_hw*[]){
2413				&csiphy2_3p_clk_src.clkr.hw
2414			},
2415			.num_parents = 1,
2416			.flags = CLK_SET_RATE_PARENT,
2417			.ops = &clk_branch2_ops,
2418		},
2419	},
2420};
2421
2422static struct clk_branch camss_jpeg0_clk = {
2423	.halt_reg = 0x35a8,
2424	.clkr = {
2425		.enable_reg = 0x35a8,
2426		.enable_mask = BIT(0),
2427		.hw.init = &(struct clk_init_data){
2428			.name = "camss_jpeg0_clk",
2429			.parent_hws = (const struct clk_hw*[]){
2430				&jpeg0_clk_src.clkr.hw
2431			},
2432			.num_parents = 1,
2433			.flags = CLK_SET_RATE_PARENT,
2434			.ops = &clk_branch2_ops,
2435		},
2436	},
2437};
2438
2439static struct clk_branch camss_jpeg2_clk = {
2440	.halt_reg = 0x35b0,
2441	.clkr = {
2442		.enable_reg = 0x35b0,
2443		.enable_mask = BIT(0),
2444		.hw.init = &(struct clk_init_data){
2445			.name = "camss_jpeg2_clk",
2446			.parent_hws = (const struct clk_hw*[]){
2447				&jpeg2_clk_src.clkr.hw
2448			},
2449			.num_parents = 1,
2450			.flags = CLK_SET_RATE_PARENT,
2451			.ops = &clk_branch2_ops,
2452		},
2453	},
2454};
2455
2456static struct clk_branch camss_jpeg_dma_clk = {
2457	.halt_reg = 0x35c0,
2458	.clkr = {
2459		.enable_reg = 0x35c0,
2460		.enable_mask = BIT(0),
2461		.hw.init = &(struct clk_init_data){
2462			.name = "camss_jpeg_dma_clk",
2463			.parent_hws = (const struct clk_hw*[]){
2464				&jpeg_dma_clk_src.clkr.hw
2465			},
2466			.num_parents = 1,
2467			.flags = CLK_SET_RATE_PARENT,
2468			.ops = &clk_branch2_ops,
2469		},
2470	},
2471};
2472
2473static struct clk_branch camss_jpeg_ahb_clk = {
2474	.halt_reg = 0x35b4,
2475	.clkr = {
2476		.enable_reg = 0x35b4,
2477		.enable_mask = BIT(0),
2478		.hw.init = &(struct clk_init_data){
2479			.name = "camss_jpeg_ahb_clk",
2480			.parent_hws = (const struct clk_hw*[]){
2481				&ahb_clk_src.clkr.hw
2482			},
2483			.num_parents = 1,
2484			.flags = CLK_SET_RATE_PARENT,
2485			.ops = &clk_branch2_ops,
2486		},
2487	},
2488};
2489
2490static struct clk_branch camss_jpeg_axi_clk = {
2491	.halt_reg = 0x35b8,
2492	.clkr = {
2493		.enable_reg = 0x35b8,
2494		.enable_mask = BIT(0),
2495		.hw.init = &(struct clk_init_data){
2496			.name = "camss_jpeg_axi_clk",
2497			.parent_hws = (const struct clk_hw*[]){
2498				&axi_clk_src.clkr.hw
2499			},
2500			.num_parents = 1,
2501			.flags = CLK_SET_RATE_PARENT,
2502			.ops = &clk_branch2_ops,
2503		},
2504	},
2505};
2506
2507static struct clk_branch camss_vfe_ahb_clk = {
2508	.halt_reg = 0x36b8,
2509	.clkr = {
2510		.enable_reg = 0x36b8,
2511		.enable_mask = BIT(0),
2512		.hw.init = &(struct clk_init_data){
2513			.name = "camss_vfe_ahb_clk",
2514			.parent_hws = (const struct clk_hw*[]){
2515				&ahb_clk_src.clkr.hw
2516			},
2517			.num_parents = 1,
2518			.flags = CLK_SET_RATE_PARENT,
2519			.ops = &clk_branch2_ops,
2520		},
2521	},
2522};
2523
2524static struct clk_branch camss_vfe_axi_clk = {
2525	.halt_reg = 0x36bc,
2526	.clkr = {
2527		.enable_reg = 0x36bc,
2528		.enable_mask = BIT(0),
2529		.hw.init = &(struct clk_init_data){
2530			.name = "camss_vfe_axi_clk",
2531			.parent_hws = (const struct clk_hw*[]){
2532				&axi_clk_src.clkr.hw
2533			},
2534			.num_parents = 1,
2535			.flags = CLK_SET_RATE_PARENT,
2536			.ops = &clk_branch2_ops,
2537		},
2538	},
2539};
2540
2541static struct clk_branch camss_vfe0_clk = {
2542	.halt_reg = 0x36a8,
2543	.clkr = {
2544		.enable_reg = 0x36a8,
2545		.enable_mask = BIT(0),
2546		.hw.init = &(struct clk_init_data){
2547			.name = "camss_vfe0_clk",
2548			.parent_hws = (const struct clk_hw*[]){
2549				&vfe0_clk_src.clkr.hw
2550			},
2551			.num_parents = 1,
2552			.flags = CLK_SET_RATE_PARENT,
2553			.ops = &clk_branch2_ops,
2554		},
2555	},
2556};
2557
2558static struct clk_branch camss_vfe0_stream_clk = {
2559	.halt_reg = 0x3720,
2560	.clkr = {
2561		.enable_reg = 0x3720,
2562		.enable_mask = BIT(0),
2563		.hw.init = &(struct clk_init_data){
2564			.name = "camss_vfe0_stream_clk",
2565			.parent_hws = (const struct clk_hw*[]){
2566				&vfe0_clk_src.clkr.hw
2567			},
2568			.num_parents = 1,
2569			.flags = CLK_SET_RATE_PARENT,
2570			.ops = &clk_branch2_ops,
2571		},
2572	},
2573};
2574
2575static struct clk_branch camss_vfe0_ahb_clk = {
2576	.halt_reg = 0x3668,
2577	.clkr = {
2578		.enable_reg = 0x3668,
2579		.enable_mask = BIT(0),
2580		.hw.init = &(struct clk_init_data){
2581			.name = "camss_vfe0_ahb_clk",
2582			.parent_hws = (const struct clk_hw*[]){
2583				&ahb_clk_src.clkr.hw
2584			},
2585			.num_parents = 1,
2586			.flags = CLK_SET_RATE_PARENT,
2587			.ops = &clk_branch2_ops,
2588		},
2589	},
2590};
2591
2592static struct clk_branch camss_vfe1_clk = {
2593	.halt_reg = 0x36ac,
2594	.clkr = {
2595		.enable_reg = 0x36ac,
2596		.enable_mask = BIT(0),
2597		.hw.init = &(struct clk_init_data){
2598			.name = "camss_vfe1_clk",
2599			.parent_hws = (const struct clk_hw*[]){
2600				&vfe1_clk_src.clkr.hw
2601			},
2602			.num_parents = 1,
2603			.flags = CLK_SET_RATE_PARENT,
2604			.ops = &clk_branch2_ops,
2605		},
2606	},
2607};
2608
2609static struct clk_branch camss_vfe1_stream_clk = {
2610	.halt_reg = 0x3724,
2611	.clkr = {
2612		.enable_reg = 0x3724,
2613		.enable_mask = BIT(0),
2614		.hw.init = &(struct clk_init_data){
2615			.name = "camss_vfe1_stream_clk",
2616			.parent_hws = (const struct clk_hw*[]){
2617				&vfe1_clk_src.clkr.hw
2618			},
2619			.num_parents = 1,
2620			.flags = CLK_SET_RATE_PARENT,
2621			.ops = &clk_branch2_ops,
2622		},
2623	},
2624};
2625
2626static struct clk_branch camss_vfe1_ahb_clk = {
2627	.halt_reg = 0x3678,
2628	.clkr = {
2629		.enable_reg = 0x3678,
2630		.enable_mask = BIT(0),
2631		.hw.init = &(struct clk_init_data){
2632			.name = "camss_vfe1_ahb_clk",
2633			.parent_hws = (const struct clk_hw*[]){
2634				&ahb_clk_src.clkr.hw
2635			},
2636			.num_parents = 1,
2637			.flags = CLK_SET_RATE_PARENT,
2638			.ops = &clk_branch2_ops,
2639		},
2640	},
2641};
2642
2643static struct clk_branch camss_csi_vfe0_clk = {
2644	.halt_reg = 0x3704,
2645	.clkr = {
2646		.enable_reg = 0x3704,
2647		.enable_mask = BIT(0),
2648		.hw.init = &(struct clk_init_data){
2649			.name = "camss_csi_vfe0_clk",
2650			.parent_hws = (const struct clk_hw*[]){
2651				&vfe0_clk_src.clkr.hw
2652			},
2653			.num_parents = 1,
2654			.flags = CLK_SET_RATE_PARENT,
2655			.ops = &clk_branch2_ops,
2656		},
2657	},
2658};
2659
2660static struct clk_branch camss_csi_vfe1_clk = {
2661	.halt_reg = 0x3714,
2662	.clkr = {
2663		.enable_reg = 0x3714,
2664		.enable_mask = BIT(0),
2665		.hw.init = &(struct clk_init_data){
2666			.name = "camss_csi_vfe1_clk",
2667			.parent_hws = (const struct clk_hw*[]){
2668				&vfe1_clk_src.clkr.hw
2669			},
2670			.num_parents = 1,
2671			.flags = CLK_SET_RATE_PARENT,
2672			.ops = &clk_branch2_ops,
2673		},
2674	},
2675};
2676
2677static struct clk_branch camss_cpp_vbif_ahb_clk = {
2678	.halt_reg = 0x36c8,
2679	.clkr = {
2680		.enable_reg = 0x36c8,
2681		.enable_mask = BIT(0),
2682		.hw.init = &(struct clk_init_data){
2683			.name = "camss_cpp_vbif_ahb_clk",
2684			.parent_hws = (const struct clk_hw*[]){
2685				&ahb_clk_src.clkr.hw
2686			},
2687			.num_parents = 1,
2688			.flags = CLK_SET_RATE_PARENT,
2689			.ops = &clk_branch2_ops,
2690		},
2691	},
2692};
2693
2694static struct clk_branch camss_cpp_axi_clk = {
2695	.halt_reg = 0x36c4,
2696	.clkr = {
2697		.enable_reg = 0x36c4,
2698		.enable_mask = BIT(0),
2699		.hw.init = &(struct clk_init_data){
2700			.name = "camss_cpp_axi_clk",
2701			.parent_hws = (const struct clk_hw*[]){
2702				&axi_clk_src.clkr.hw
2703			},
2704			.num_parents = 1,
2705			.flags = CLK_SET_RATE_PARENT,
2706			.ops = &clk_branch2_ops,
2707		},
2708	},
2709};
2710
2711static struct clk_branch camss_cpp_clk = {
2712	.halt_reg = 0x36b0,
2713	.clkr = {
2714		.enable_reg = 0x36b0,
2715		.enable_mask = BIT(0),
2716		.hw.init = &(struct clk_init_data){
2717			.name = "camss_cpp_clk",
2718			.parent_hws = (const struct clk_hw*[]){
2719				&cpp_clk_src.clkr.hw
2720			},
2721			.num_parents = 1,
2722			.flags = CLK_SET_RATE_PARENT,
2723			.ops = &clk_branch2_ops,
2724		},
2725	},
2726};
2727
2728static struct clk_branch camss_cpp_ahb_clk = {
2729	.halt_reg = 0x36b4,
2730	.clkr = {
2731		.enable_reg = 0x36b4,
2732		.enable_mask = BIT(0),
2733		.hw.init = &(struct clk_init_data){
2734			.name = "camss_cpp_ahb_clk",
2735			.parent_hws = (const struct clk_hw*[]){
2736				&ahb_clk_src.clkr.hw
2737			},
2738			.num_parents = 1,
2739			.flags = CLK_SET_RATE_PARENT,
2740			.ops = &clk_branch2_ops,
2741		},
2742	},
2743};
2744
2745static struct clk_branch camss_csi0_clk = {
2746	.halt_reg = 0x30b4,
2747	.clkr = {
2748		.enable_reg = 0x30b4,
2749		.enable_mask = BIT(0),
2750		.hw.init = &(struct clk_init_data){
2751			.name = "camss_csi0_clk",
2752			.parent_hws = (const struct clk_hw*[]){
2753				&csi0_clk_src.clkr.hw
2754			},
2755			.num_parents = 1,
2756			.flags = CLK_SET_RATE_PARENT,
2757			.ops = &clk_branch2_ops,
2758		},
2759	},
2760};
2761
2762static struct clk_branch camss_csi0_ahb_clk = {
2763	.halt_reg = 0x30bc,
2764	.clkr = {
2765		.enable_reg = 0x30bc,
2766		.enable_mask = BIT(0),
2767		.hw.init = &(struct clk_init_data){
2768			.name = "camss_csi0_ahb_clk",
2769			.parent_hws = (const struct clk_hw*[]){
2770				&ahb_clk_src.clkr.hw
2771			},
2772			.num_parents = 1,
2773			.flags = CLK_SET_RATE_PARENT,
2774			.ops = &clk_branch2_ops,
2775		},
2776	},
2777};
2778
2779static struct clk_branch camss_csi0phy_clk = {
2780	.halt_reg = 0x30c4,
2781	.clkr = {
2782		.enable_reg = 0x30c4,
2783		.enable_mask = BIT(0),
2784		.hw.init = &(struct clk_init_data){
2785			.name = "camss_csi0phy_clk",
2786			.parent_hws = (const struct clk_hw*[]){
2787				&csi0_clk_src.clkr.hw
2788			},
2789			.num_parents = 1,
2790			.flags = CLK_SET_RATE_PARENT,
2791			.ops = &clk_branch2_ops,
2792		},
2793	},
2794};
2795
2796static struct clk_branch camss_csi0rdi_clk = {
2797	.halt_reg = 0x30d4,
2798	.clkr = {
2799		.enable_reg = 0x30d4,
2800		.enable_mask = BIT(0),
2801		.hw.init = &(struct clk_init_data){
2802			.name = "camss_csi0rdi_clk",
2803			.parent_hws = (const struct clk_hw*[]){
2804				&csi0_clk_src.clkr.hw
2805			},
2806			.num_parents = 1,
2807			.flags = CLK_SET_RATE_PARENT,
2808			.ops = &clk_branch2_ops,
2809		},
2810	},
2811};
2812
2813static struct clk_branch camss_csi0pix_clk = {
2814	.halt_reg = 0x30e4,
2815	.clkr = {
2816		.enable_reg = 0x30e4,
2817		.enable_mask = BIT(0),
2818		.hw.init = &(struct clk_init_data){
2819			.name = "camss_csi0pix_clk",
2820			.parent_hws = (const struct clk_hw*[]){
2821				&csi0_clk_src.clkr.hw
2822			},
2823			.num_parents = 1,
2824			.flags = CLK_SET_RATE_PARENT,
2825			.ops = &clk_branch2_ops,
2826		},
2827	},
2828};
2829
2830static struct clk_branch camss_csi1_clk = {
2831	.halt_reg = 0x3124,
2832	.clkr = {
2833		.enable_reg = 0x3124,
2834		.enable_mask = BIT(0),
2835		.hw.init = &(struct clk_init_data){
2836			.name = "camss_csi1_clk",
2837			.parent_hws = (const struct clk_hw*[]){
2838				&csi1_clk_src.clkr.hw
2839			},
2840			.num_parents = 1,
2841			.flags = CLK_SET_RATE_PARENT,
2842			.ops = &clk_branch2_ops,
2843		},
2844	},
2845};
2846
2847static struct clk_branch camss_csi1_ahb_clk = {
2848	.halt_reg = 0x3128,
2849	.clkr = {
2850		.enable_reg = 0x3128,
2851		.enable_mask = BIT(0),
2852		.hw.init = &(struct clk_init_data){
2853			.name = "camss_csi1_ahb_clk",
2854			.parent_hws = (const struct clk_hw*[]){
2855				&ahb_clk_src.clkr.hw
2856			},
2857			.num_parents = 1,
2858			.flags = CLK_SET_RATE_PARENT,
2859			.ops = &clk_branch2_ops,
2860		},
2861	},
2862};
2863
2864static struct clk_branch camss_csi1phy_clk = {
2865	.halt_reg = 0x3134,
2866	.clkr = {
2867		.enable_reg = 0x3134,
2868		.enable_mask = BIT(0),
2869		.hw.init = &(struct clk_init_data){
2870			.name = "camss_csi1phy_clk",
2871			.parent_hws = (const struct clk_hw*[]){
2872				&csi1_clk_src.clkr.hw
2873			},
2874			.num_parents = 1,
2875			.flags = CLK_SET_RATE_PARENT,
2876			.ops = &clk_branch2_ops,
2877		},
2878	},
2879};
2880
2881static struct clk_branch camss_csi1rdi_clk = {
2882	.halt_reg = 0x3144,
2883	.clkr = {
2884		.enable_reg = 0x3144,
2885		.enable_mask = BIT(0),
2886		.hw.init = &(struct clk_init_data){
2887			.name = "camss_csi1rdi_clk",
2888			.parent_hws = (const struct clk_hw*[]){
2889				&csi1_clk_src.clkr.hw
2890			},
2891			.num_parents = 1,
2892			.flags = CLK_SET_RATE_PARENT,
2893			.ops = &clk_branch2_ops,
2894		},
2895	},
2896};
2897
2898static struct clk_branch camss_csi1pix_clk = {
2899	.halt_reg = 0x3154,
2900	.clkr = {
2901		.enable_reg = 0x3154,
2902		.enable_mask = BIT(0),
2903		.hw.init = &(struct clk_init_data){
2904			.name = "camss_csi1pix_clk",
2905			.parent_hws = (const struct clk_hw*[]){
2906				&csi1_clk_src.clkr.hw
2907			},
2908			.num_parents = 1,
2909			.flags = CLK_SET_RATE_PARENT,
2910			.ops = &clk_branch2_ops,
2911		},
2912	},
2913};
2914
2915static struct clk_branch camss_csi2_clk = {
2916	.halt_reg = 0x3184,
2917	.clkr = {
2918		.enable_reg = 0x3184,
2919		.enable_mask = BIT(0),
2920		.hw.init = &(struct clk_init_data){
2921			.name = "camss_csi2_clk",
2922			.parent_hws = (const struct clk_hw*[]){
2923				&csi2_clk_src.clkr.hw
2924			},
2925			.num_parents = 1,
2926			.flags = CLK_SET_RATE_PARENT,
2927			.ops = &clk_branch2_ops,
2928		},
2929	},
2930};
2931
2932static struct clk_branch camss_csi2_ahb_clk = {
2933	.halt_reg = 0x3188,
2934	.clkr = {
2935		.enable_reg = 0x3188,
2936		.enable_mask = BIT(0),
2937		.hw.init = &(struct clk_init_data){
2938			.name = "camss_csi2_ahb_clk",
2939			.parent_hws = (const struct clk_hw*[]){
2940				&ahb_clk_src.clkr.hw
2941			},
2942			.num_parents = 1,
2943			.flags = CLK_SET_RATE_PARENT,
2944			.ops = &clk_branch2_ops,
2945		},
2946	},
2947};
2948
2949static struct clk_branch camss_csi2phy_clk = {
2950	.halt_reg = 0x3194,
2951	.clkr = {
2952		.enable_reg = 0x3194,
2953		.enable_mask = BIT(0),
2954		.hw.init = &(struct clk_init_data){
2955			.name = "camss_csi2phy_clk",
2956			.parent_hws = (const struct clk_hw*[]){
2957				&csi2_clk_src.clkr.hw
2958			},
2959			.num_parents = 1,
2960			.flags = CLK_SET_RATE_PARENT,
2961			.ops = &clk_branch2_ops,
2962		},
2963	},
2964};
2965
2966static struct clk_branch camss_csi2rdi_clk = {
2967	.halt_reg = 0x31a4,
2968	.clkr = {
2969		.enable_reg = 0x31a4,
2970		.enable_mask = BIT(0),
2971		.hw.init = &(struct clk_init_data){
2972			.name = "camss_csi2rdi_clk",
2973			.parent_hws = (const struct clk_hw*[]){
2974				&csi2_clk_src.clkr.hw
2975			},
2976			.num_parents = 1,
2977			.flags = CLK_SET_RATE_PARENT,
2978			.ops = &clk_branch2_ops,
2979		},
2980	},
2981};
2982
2983static struct clk_branch camss_csi2pix_clk = {
2984	.halt_reg = 0x31b4,
2985	.clkr = {
2986		.enable_reg = 0x31b4,
2987		.enable_mask = BIT(0),
2988		.hw.init = &(struct clk_init_data){
2989			.name = "camss_csi2pix_clk",
2990			.parent_hws = (const struct clk_hw*[]){
2991				&csi2_clk_src.clkr.hw
2992			},
2993			.num_parents = 1,
2994			.flags = CLK_SET_RATE_PARENT,
2995			.ops = &clk_branch2_ops,
2996		},
2997	},
2998};
2999
3000static struct clk_branch camss_csi3_clk = {
3001	.halt_reg = 0x31e4,
3002	.clkr = {
3003		.enable_reg = 0x31e4,
3004		.enable_mask = BIT(0),
3005		.hw.init = &(struct clk_init_data){
3006			.name = "camss_csi3_clk",
3007			.parent_hws = (const struct clk_hw*[]){
3008				&csi3_clk_src.clkr.hw
3009			},
3010			.num_parents = 1,
3011			.flags = CLK_SET_RATE_PARENT,
3012			.ops = &clk_branch2_ops,
3013		},
3014	},
3015};
3016
3017static struct clk_branch camss_csi3_ahb_clk = {
3018	.halt_reg = 0x31e8,
3019	.clkr = {
3020		.enable_reg = 0x31e8,
3021		.enable_mask = BIT(0),
3022		.hw.init = &(struct clk_init_data){
3023			.name = "camss_csi3_ahb_clk",
3024			.parent_hws = (const struct clk_hw*[]){
3025				&ahb_clk_src.clkr.hw
3026			},
3027			.num_parents = 1,
3028			.flags = CLK_SET_RATE_PARENT,
3029			.ops = &clk_branch2_ops,
3030		},
3031	},
3032};
3033
3034static struct clk_branch camss_csi3phy_clk = {
3035	.halt_reg = 0x31f4,
3036	.clkr = {
3037		.enable_reg = 0x31f4,
3038		.enable_mask = BIT(0),
3039		.hw.init = &(struct clk_init_data){
3040			.name = "camss_csi3phy_clk",
3041			.parent_hws = (const struct clk_hw*[]){
3042				&csi3_clk_src.clkr.hw
3043			},
3044			.num_parents = 1,
3045			.flags = CLK_SET_RATE_PARENT,
3046			.ops = &clk_branch2_ops,
3047		},
3048	},
3049};
3050
3051static struct clk_branch camss_csi3rdi_clk = {
3052	.halt_reg = 0x3204,
3053	.clkr = {
3054		.enable_reg = 0x3204,
3055		.enable_mask = BIT(0),
3056		.hw.init = &(struct clk_init_data){
3057			.name = "camss_csi3rdi_clk",
3058			.parent_hws = (const struct clk_hw*[]){
3059				&csi3_clk_src.clkr.hw
3060			},
3061			.num_parents = 1,
3062			.flags = CLK_SET_RATE_PARENT,
3063			.ops = &clk_branch2_ops,
3064		},
3065	},
3066};
3067
3068static struct clk_branch camss_csi3pix_clk = {
3069	.halt_reg = 0x3214,
3070	.clkr = {
3071		.enable_reg = 0x3214,
3072		.enable_mask = BIT(0),
3073		.hw.init = &(struct clk_init_data){
3074			.name = "camss_csi3pix_clk",
3075			.parent_hws = (const struct clk_hw*[]){
3076				&csi3_clk_src.clkr.hw
3077			},
3078			.num_parents = 1,
3079			.flags = CLK_SET_RATE_PARENT,
3080			.ops = &clk_branch2_ops,
3081		},
3082	},
3083};
3084
3085static struct clk_branch camss_ispif_ahb_clk = {
3086	.halt_reg = 0x3224,
3087	.clkr = {
3088		.enable_reg = 0x3224,
3089		.enable_mask = BIT(0),
3090		.hw.init = &(struct clk_init_data){
3091			.name = "camss_ispif_ahb_clk",
3092			.parent_hws = (const struct clk_hw*[]){
3093				&ahb_clk_src.clkr.hw
3094			},
3095			.num_parents = 1,
3096			.flags = CLK_SET_RATE_PARENT,
3097			.ops = &clk_branch2_ops,
3098		},
3099	},
3100};
3101
3102static struct clk_branch fd_core_clk = {
3103	.halt_reg = 0x3b68,
3104	.clkr = {
3105		.enable_reg = 0x3b68,
3106		.enable_mask = BIT(0),
3107		.hw.init = &(struct clk_init_data){
3108			.name = "fd_core_clk",
3109			.parent_hws = (const struct clk_hw*[]){
3110				&fd_core_clk_src.clkr.hw
3111			},
3112			.num_parents = 1,
3113			.flags = CLK_SET_RATE_PARENT,
3114			.ops = &clk_branch2_ops,
3115		},
3116	},
3117};
3118
3119static struct clk_branch fd_core_uar_clk = {
3120	.halt_reg = 0x3b6c,
3121	.clkr = {
3122		.enable_reg = 0x3b6c,
3123		.enable_mask = BIT(0),
3124		.hw.init = &(struct clk_init_data){
3125			.name = "fd_core_uar_clk",
3126			.parent_hws = (const struct clk_hw*[]){
3127				&fd_core_clk_src.clkr.hw
3128			},
3129			.num_parents = 1,
3130			.flags = CLK_SET_RATE_PARENT,
3131			.ops = &clk_branch2_ops,
3132		},
3133	},
3134};
3135
3136static struct clk_branch fd_ahb_clk = {
3137	.halt_reg = 0x3ba74,
3138	.clkr = {
3139		.enable_reg = 0x3ba74,
3140		.enable_mask = BIT(0),
3141		.hw.init = &(struct clk_init_data){
3142			.name = "fd_ahb_clk",
3143			.parent_hws = (const struct clk_hw*[]){
3144				&ahb_clk_src.clkr.hw
3145			},
3146			.num_parents = 1,
3147			.flags = CLK_SET_RATE_PARENT,
3148			.ops = &clk_branch2_ops,
3149		},
3150	},
3151};
3152
3153static struct clk_hw *mmcc_msm8996_hws[] = {
3154	&gpll0_div.hw,
3155};
3156
3157static struct gdsc mmagic_bimc_gdsc = {
3158	.gdscr = 0x529c,
3159	.pd = {
3160		.name = "mmagic_bimc",
3161	},
3162	.pwrsts = PWRSTS_OFF_ON,
3163	.flags = ALWAYS_ON,
3164};
3165
3166static struct gdsc mmagic_video_gdsc = {
3167	.gdscr = 0x119c,
3168	.gds_hw_ctrl = 0x120c,
3169	.pd = {
3170		.name = "mmagic_video",
3171	},
3172	.pwrsts = PWRSTS_OFF_ON,
3173	.flags = VOTABLE | ALWAYS_ON,
3174};
3175
3176static struct gdsc mmagic_mdss_gdsc = {
3177	.gdscr = 0x247c,
3178	.gds_hw_ctrl = 0x2480,
3179	.pd = {
3180		.name = "mmagic_mdss",
3181	},
3182	.pwrsts = PWRSTS_OFF_ON,
3183	.flags = VOTABLE | ALWAYS_ON,
3184};
3185
3186static struct gdsc mmagic_camss_gdsc = {
3187	.gdscr = 0x3c4c,
3188	.gds_hw_ctrl = 0x3c50,
3189	.pd = {
3190		.name = "mmagic_camss",
3191	},
3192	.pwrsts = PWRSTS_OFF_ON,
3193	.flags = VOTABLE | ALWAYS_ON,
3194};
3195
3196static struct gdsc venus_gdsc = {
3197	.gdscr = 0x1024,
3198	.cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
3199	.cxc_count = 3,
3200	.pd = {
3201		.name = "venus",
3202	},
3203	.parent = &mmagic_video_gdsc.pd,
3204	.pwrsts = PWRSTS_OFF_ON,
3205};
3206
3207static struct gdsc venus_core0_gdsc = {
3208	.gdscr = 0x1040,
3209	.cxcs = (unsigned int []){ 0x1048 },
3210	.cxc_count = 1,
3211	.pd = {
3212		.name = "venus_core0",
3213	},
3214	.parent = &venus_gdsc.pd,
3215	.pwrsts = PWRSTS_OFF_ON,
3216	.flags = HW_CTRL,
3217};
3218
3219static struct gdsc venus_core1_gdsc = {
3220	.gdscr = 0x1044,
3221	.cxcs = (unsigned int []){ 0x104c },
3222	.cxc_count = 1,
3223	.pd = {
3224		.name = "venus_core1",
3225	},
3226	.parent = &venus_gdsc.pd,
3227	.pwrsts = PWRSTS_OFF_ON,
3228	.flags = HW_CTRL,
3229};
3230
3231static struct gdsc camss_gdsc = {
3232	.gdscr = 0x34a0,
3233	.cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
3234	.cxc_count = 2,
3235	.pd = {
3236		.name = "camss",
3237	},
3238	.parent = &mmagic_camss_gdsc.pd,
3239	.pwrsts = PWRSTS_OFF_ON,
3240};
3241
3242static struct gdsc vfe0_gdsc = {
3243	.gdscr = 0x3664,
3244	.cxcs = (unsigned int []){ 0x36a8 },
3245	.cxc_count = 1,
3246	.pd = {
3247		.name = "vfe0",
3248	},
3249	.parent = &camss_gdsc.pd,
3250	.pwrsts = PWRSTS_OFF_ON,
3251};
3252
3253static struct gdsc vfe1_gdsc = {
3254	.gdscr = 0x3674,
3255	.cxcs = (unsigned int []){ 0x36ac },
3256	.cxc_count = 1,
3257	.pd = {
3258		.name = "vfe1",
3259	},
3260	.parent = &camss_gdsc.pd,
3261	.pwrsts = PWRSTS_OFF_ON,
3262};
3263
3264static struct gdsc jpeg_gdsc = {
3265	.gdscr = 0x35a4,
3266	.cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
3267	.cxc_count = 4,
3268	.pd = {
3269		.name = "jpeg",
3270	},
3271	.parent = &camss_gdsc.pd,
3272	.pwrsts = PWRSTS_OFF_ON,
3273};
3274
3275static struct gdsc cpp_gdsc = {
3276	.gdscr = 0x36d4,
3277	.cxcs = (unsigned int []){ 0x36b0 },
3278	.cxc_count = 1,
3279	.pd = {
3280		.name = "cpp",
3281	},
3282	.parent = &camss_gdsc.pd,
3283	.pwrsts = PWRSTS_OFF_ON,
3284};
3285
3286static struct gdsc fd_gdsc = {
3287	.gdscr = 0x3b64,
3288	.cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
3289	.cxc_count = 2,
3290	.pd = {
3291		.name = "fd",
3292	},
3293	.parent = &camss_gdsc.pd,
3294	.pwrsts = PWRSTS_OFF_ON,
3295};
3296
3297static struct gdsc mdss_gdsc = {
3298	.gdscr = 0x2304,
3299	.cxcs = (unsigned int []){ 0x2310, 0x231c },
3300	.cxc_count = 2,
3301	.pd = {
3302		.name = "mdss",
3303	},
3304	.parent = &mmagic_mdss_gdsc.pd,
3305	.pwrsts = PWRSTS_OFF_ON,
3306};
3307
3308static struct gdsc gpu_gdsc = {
3309	.gdscr = 0x4034,
3310	.gds_hw_ctrl = 0x4038,
3311	.pd = {
3312		.name = "gpu",
3313	},
3314	.pwrsts = PWRSTS_OFF_ON,
3315	.flags = VOTABLE,
3316};
3317
3318static struct gdsc gpu_gx_gdsc = {
3319	.gdscr = 0x4024,
3320	.clamp_io_ctrl = 0x4300,
3321	.cxcs = (unsigned int []){ 0x4028 },
3322	.cxc_count = 1,
3323	.pd = {
3324		.name = "gpu_gx",
3325	},
3326	.pwrsts = PWRSTS_OFF_ON,
3327	.parent = &gpu_gdsc.pd,
3328	.flags = CLAMP_IO,
3329	.supply = "vdd-gfx",
3330};
3331
3332static struct clk_regmap *mmcc_msm8996_clocks[] = {
3333	[MMPLL0_EARLY] = &mmpll0_early.clkr,
3334	[MMPLL0_PLL] = &mmpll0.clkr,
3335	[MMPLL1_EARLY] = &mmpll1_early.clkr,
3336	[MMPLL1_PLL] = &mmpll1.clkr,
3337	[MMPLL2_EARLY] = &mmpll2_early.clkr,
3338	[MMPLL2_PLL] = &mmpll2.clkr,
3339	[MMPLL3_EARLY] = &mmpll3_early.clkr,
3340	[MMPLL3_PLL] = &mmpll3.clkr,
3341	[MMPLL4_EARLY] = &mmpll4_early.clkr,
3342	[MMPLL4_PLL] = &mmpll4.clkr,
3343	[MMPLL5_EARLY] = &mmpll5_early.clkr,
3344	[MMPLL5_PLL] = &mmpll5.clkr,
3345	[MMPLL8_EARLY] = &mmpll8_early.clkr,
3346	[MMPLL8_PLL] = &mmpll8.clkr,
3347	[MMPLL9_EARLY] = &mmpll9_early.clkr,
3348	[MMPLL9_PLL] = &mmpll9.clkr,
3349	[AHB_CLK_SRC] = &ahb_clk_src.clkr,
3350	[AXI_CLK_SRC] = &axi_clk_src.clkr,
3351	[MAXI_CLK_SRC] = &maxi_clk_src.clkr,
3352	[GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
3353	[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3354	[ISENSE_CLK_SRC] = &isense_clk_src.clkr,
3355	[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3356	[VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
3357	[VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
3358	[VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
3359	[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3360	[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3361	[MDP_CLK_SRC] = &mdp_clk_src.clkr,
3362	[EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3363	[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3364	[HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3365	[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3366	[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3367	[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3368	[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3369	[CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3370	[CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3371	[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3372	[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3373	[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3374	[MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3375	[CCI_CLK_SRC] = &cci_clk_src.clkr,
3376	[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3377	[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3378	[CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3379	[CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr,
3380	[CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr,
3381	[CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr,
3382	[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3383	[JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3384	[JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
3385	[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3386	[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3387	[CPP_CLK_SRC] = &cpp_clk_src.clkr,
3388	[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3389	[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3390	[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3391	[CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3392	[FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
3393	[MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr,
3394	[MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr,
3395	[MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3396	[MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr,
3397	[MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr,
3398	[MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr,
3399	[MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr,
3400	[SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr,
3401	[SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr,
3402	[SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr,
3403	[SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr,
3404	[SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr,
3405	[SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr,
3406	[MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr,
3407	[MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr,
3408	[SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr,
3409	[SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr,
3410	[SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr,
3411	[SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr,
3412	[MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr,
3413	[MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr,
3414	[SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr,
3415	[SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr,
3416	[MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr,
3417	[GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr,
3418	[GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr,
3419	[GPU_AHB_CLK] = &gpu_ahb_clk.clkr,
3420	[GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr,
3421	[VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
3422	[VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
3423	[MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3424	[MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3425	[VIDEO_CORE_CLK] = &video_core_clk.clkr,
3426	[VIDEO_AXI_CLK] = &video_axi_clk.clkr,
3427	[VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
3428	[VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
3429	[VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
3430	[VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
3431	[MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3432	[MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3433	[MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3434	[MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3435	[MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3436	[MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3437	[MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3438	[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3439	[MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3440	[MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3441	[MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3442	[MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3443	[MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3444	[CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3445	[CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3446	[CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3447	[CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3448	[CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3449	[CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3450	[CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3451	[CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3452	[CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3453	[CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
3454	[CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
3455	[CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
3456	[CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
3457	[CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
3458	[CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr,
3459	[CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr,
3460	[CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr,
3461	[CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
3462	[CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr,
3463	[CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
3464	[CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
3465	[CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
3466	[CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr,
3467	[CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr,
3468	[CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
3469	[CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
3470	[CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
3471	[CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
3472	[CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
3473	[CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
3474	[CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3475	[CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3476	[CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
3477	[CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
3478	[CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
3479	[CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
3480	[CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3481	[CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3482	[CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3483	[CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3484	[CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3485	[CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3486	[CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3487	[CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3488	[CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3489	[CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3490	[CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3491	[CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3492	[CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3493	[CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3494	[CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3495	[CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3496	[CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3497	[CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3498	[CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3499	[CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3500	[CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3501	[FD_CORE_CLK] = &fd_core_clk.clkr,
3502	[FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
3503	[FD_AHB_CLK] = &fd_ahb_clk.clkr,
3504};
3505
3506static struct gdsc *mmcc_msm8996_gdscs[] = {
3507	[MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc,
3508	[MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc,
3509	[MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc,
3510	[MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc,
3511	[VENUS_GDSC] = &venus_gdsc,
3512	[VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3513	[VENUS_CORE1_GDSC] = &venus_core1_gdsc,
3514	[CAMSS_GDSC] = &camss_gdsc,
3515	[VFE0_GDSC] = &vfe0_gdsc,
3516	[VFE1_GDSC] = &vfe1_gdsc,
3517	[JPEG_GDSC] = &jpeg_gdsc,
3518	[CPP_GDSC] = &cpp_gdsc,
3519	[FD_GDSC] = &fd_gdsc,
3520	[MDSS_GDSC] = &mdss_gdsc,
3521	[GPU_GDSC] = &gpu_gdsc,
3522	[GPU_GX_GDSC] = &gpu_gx_gdsc,
3523};
3524
3525static const struct qcom_reset_map mmcc_msm8996_resets[] = {
3526	[MMAGICAHB_BCR] = { 0x5020 },
3527	[MMAGIC_CFG_BCR] = { 0x5050 },
3528	[MISC_BCR] = { 0x5010 },
3529	[BTO_BCR] = { 0x5030 },
3530	[MMAGICAXI_BCR] = { 0x5060 },
3531	[MMAGICMAXI_BCR] = { 0x5070 },
3532	[DSA_BCR] = { 0x50a0 },
3533	[MMAGIC_CAMSS_BCR] = { 0x3c40 },
3534	[THROTTLE_CAMSS_BCR] = { 0x3c30 },
3535	[SMMU_VFE_BCR] = { 0x3c00 },
3536	[SMMU_CPP_BCR] = { 0x3c10 },
3537	[SMMU_JPEG_BCR] = { 0x3c20 },
3538	[MMAGIC_MDSS_BCR] = { 0x2470 },
3539	[THROTTLE_MDSS_BCR] = { 0x2460 },
3540	[SMMU_ROT_BCR] = { 0x2440 },
3541	[SMMU_MDP_BCR] = { 0x2450 },
3542	[MMAGIC_VIDEO_BCR] = { 0x1190 },
3543	[THROTTLE_VIDEO_BCR] = { 0x1180 },
3544	[SMMU_VIDEO_BCR] = { 0x1170 },
3545	[MMAGIC_BIMC_BCR] = { 0x5290 },
3546	[GPU_GX_BCR] = { 0x4020 },
3547	[GPU_BCR] = { 0x4030 },
3548	[GPU_AON_BCR] = { 0x4040 },
3549	[VMEM_BCR] = { 0x1200 },
3550	[MMSS_RBCPR_BCR] = { 0x4080 },
3551	[VIDEO_BCR] = { 0x1020 },
3552	[MDSS_BCR] = { 0x2300 },
3553	[CAMSS_TOP_BCR] = { 0x3480 },
3554	[CAMSS_AHB_BCR] = { 0x3488 },
3555	[CAMSS_MICRO_BCR] = { 0x3490 },
3556	[CAMSS_CCI_BCR] = { 0x3340 },
3557	[CAMSS_PHY0_BCR] = { 0x3020 },
3558	[CAMSS_PHY1_BCR] = { 0x3050 },
3559	[CAMSS_PHY2_BCR] = { 0x3080 },
3560	[CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
3561	[CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
3562	[CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
3563	[CAMSS_JPEG_BCR] = { 0x35a0 },
3564	[CAMSS_VFE_BCR] = { 0x36a0 },
3565	[CAMSS_VFE0_BCR] = { 0x3660 },
3566	[CAMSS_VFE1_BCR] = { 0x3670 },
3567	[CAMSS_CSI_VFE0_BCR] = { 0x3700 },
3568	[CAMSS_CSI_VFE1_BCR] = { 0x3710 },
3569	[CAMSS_CPP_TOP_BCR] = { 0x36c0 },
3570	[CAMSS_CPP_BCR] = { 0x36d0 },
3571	[CAMSS_CSI0_BCR] = { 0x30b0 },
3572	[CAMSS_CSI0RDI_BCR] = { 0x30d0 },
3573	[CAMSS_CSI0PIX_BCR] = { 0x30e0 },
3574	[CAMSS_CSI1_BCR] = { 0x3120 },
3575	[CAMSS_CSI1RDI_BCR] = { 0x3140 },
3576	[CAMSS_CSI1PIX_BCR] = { 0x3150 },
3577	[CAMSS_CSI2_BCR] = { 0x3180 },
3578	[CAMSS_CSI2RDI_BCR] = { 0x31a0 },
3579	[CAMSS_CSI2PIX_BCR] = { 0x31b0 },
3580	[CAMSS_CSI3_BCR] = { 0x31e0 },
3581	[CAMSS_CSI3RDI_BCR] = { 0x3200 },
3582	[CAMSS_CSI3PIX_BCR] = { 0x3210 },
3583	[CAMSS_ISPIF_BCR] = { 0x3220 },
3584	[FD_BCR] = { 0x3b60 },
3585	[MMSS_SPDM_RM_BCR] = { 0x300 },
3586};
3587
3588static const struct regmap_config mmcc_msm8996_regmap_config = {
3589	.reg_bits	= 32,
3590	.reg_stride	= 4,
3591	.val_bits	= 32,
3592	.max_register	= 0xb008,
3593	.fast_io	= true,
3594};
3595
3596static const struct qcom_cc_desc mmcc_msm8996_desc = {
3597	.config = &mmcc_msm8996_regmap_config,
3598	.clks = mmcc_msm8996_clocks,
3599	.num_clks = ARRAY_SIZE(mmcc_msm8996_clocks),
3600	.resets = mmcc_msm8996_resets,
3601	.num_resets = ARRAY_SIZE(mmcc_msm8996_resets),
3602	.gdscs = mmcc_msm8996_gdscs,
3603	.num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs),
3604	.clk_hws = mmcc_msm8996_hws,
3605	.num_clk_hws = ARRAY_SIZE(mmcc_msm8996_hws),
3606};
3607
3608static const struct of_device_id mmcc_msm8996_match_table[] = {
3609	{ .compatible = "qcom,mmcc-msm8996" },
3610	{ }
3611};
3612MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table);
3613
3614static int mmcc_msm8996_probe(struct platform_device *pdev)
3615{
3616	struct regmap *regmap;
3617
3618	regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc);
3619	if (IS_ERR(regmap))
3620		return PTR_ERR(regmap);
3621
3622	/* Disable the AHB DCD */
3623	regmap_update_bits(regmap, 0x50d8, BIT(31), 0);
3624	/* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */
3625	regmap_update_bits(regmap, 0x5054, BIT(15), 0);
3626
3627	return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8996_desc, regmap);
3628}
3629
3630static struct platform_driver mmcc_msm8996_driver = {
3631	.probe		= mmcc_msm8996_probe,
3632	.driver		= {
3633		.name	= "mmcc-msm8996",
3634		.of_match_table = mmcc_msm8996_match_table,
3635	},
3636};
3637module_platform_driver(mmcc_msm8996_driver);
3638
3639MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver");
3640MODULE_LICENSE("GPL v2");
3641MODULE_ALIAS("platform:mmcc-msm8996");