mmcc-msm8994.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
   4 */
   5
   6#include <linux/kernel.h>
   7#include <linux/bitops.h>
   8#include <linux/err.h>
   9#include <linux/platform_device.h>
  10#include <linux/mod_devicetable.h>
  11#include <linux/module.h>
  12#include <linux/of.h>
  13#include <linux/clk-provider.h>
  14#include <linux/regmap.h>
  15
  16#include <dt-bindings/clock/qcom,mmcc-msm8994.h>
  17
  18#include "common.h"
  19#include "clk-regmap.h"
  20#include "clk-regmap-divider.h"
  21#include "clk-alpha-pll.h"
  22#include "clk-rcg.h"
  23#include "clk-branch.h"
  24#include "reset.h"
  25#include "gdsc.h"
  26
  27
  28enum {
  29	P_XO,
  30	P_GPLL0,
  31	P_MMPLL0,
  32	P_MMPLL1,
  33	P_MMPLL3,
  34	P_MMPLL4,
  35	P_MMPLL5, /* Is this one even used by anything? Downstream doesn't tell. */
  36	P_DSI0PLL,
  37	P_DSI1PLL,
  38	P_DSI0PLL_BYTE,
  39	P_DSI1PLL_BYTE,
  40	P_HDMIPLL,
  41};
  42static const struct parent_map mmcc_xo_gpll0_map[] = {
  43	{ P_XO, 0 },
  44	{ P_GPLL0, 5 }
  45};
  46
  47static const struct clk_parent_data mmcc_xo_gpll0[] = {
  48	{ .fw_name = "xo" },
  49	{ .fw_name = "gpll0" },
  50};
  51
  52static const struct parent_map mmss_xo_hdmi_map[] = {
  53	{ P_XO, 0 },
  54	{ P_HDMIPLL, 3 }
  55};
  56
  57static const struct clk_parent_data mmss_xo_hdmi[] = {
  58	{ .fw_name = "xo" },
  59	{ .fw_name = "hdmipll" },
  60};
  61
  62static const struct parent_map mmcc_xo_dsi0pll_dsi1pll_map[] = {
  63	{ P_XO, 0 },
  64	{ P_DSI0PLL, 1 },
  65	{ P_DSI1PLL, 2 }
  66};
  67
  68static const struct clk_parent_data mmcc_xo_dsi0pll_dsi1pll[] = {
  69	{ .fw_name = "xo" },
  70	{ .fw_name = "dsi0pll" },
  71	{ .fw_name = "dsi1pll" },
  72};
  73
  74static const struct parent_map mmcc_xo_dsibyte_map[] = {
  75	{ P_XO, 0 },
  76	{ P_DSI0PLL_BYTE, 1 },
  77	{ P_DSI1PLL_BYTE, 2 }
  78};
  79
  80static const struct clk_parent_data mmcc_xo_dsibyte[] = {
  81	{ .fw_name = "xo" },
  82	{ .fw_name = "dsi0pllbyte" },
  83	{ .fw_name = "dsi1pllbyte" },
  84};
  85
  86static const struct pll_vco mmpll_p_vco[] = {
  87	{ 250000000, 500000000, 3 },
  88	{ 500000000, 1000000000, 2 },
  89	{ 1000000000, 1500000000, 1 },
  90	{ 1500000000, 2000000000, 0 },
  91};
  92
  93static const struct pll_vco mmpll_t_vco[] = {
  94	{ 500000000, 1500000000, 0 },
  95};
  96
  97static const struct alpha_pll_config mmpll_p_config = {
  98	.post_div_mask = 0xf00,
  99};
 100
 101static struct clk_alpha_pll mmpll0_early = {
 102	.offset = 0x0,
 103	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 104	.vco_table = mmpll_p_vco,
 105	.num_vco = ARRAY_SIZE(mmpll_p_vco),
 106	.clkr = {
 107		.enable_reg = 0x100,
 108		.enable_mask = BIT(0),
 109		.hw.init = &(struct clk_init_data){
 110			.name = "mmpll0_early",
 111			.parent_data = &(const struct clk_parent_data){
 112				.fw_name = "xo",
 113			},
 114			.num_parents = 1,
 115			.ops = &clk_alpha_pll_ops,
 116		},
 117	},
 118};
 119
 120static struct clk_alpha_pll_postdiv mmpll0 = {
 121	.offset = 0x0,
 122	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 123	.width = 4,
 124	.clkr.hw.init = &(struct clk_init_data){
 125		.name = "mmpll0",
 126		.parent_hws = (const struct clk_hw *[]){ &mmpll0_early.clkr.hw },
 127		.num_parents = 1,
 128		.ops = &clk_alpha_pll_postdiv_ops,
 129		.flags = CLK_SET_RATE_PARENT,
 130	},
 131};
 132
 133static struct clk_alpha_pll mmpll1_early = {
 134	.offset = 0x30,
 135	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 136	.vco_table = mmpll_p_vco,
 137	.num_vco = ARRAY_SIZE(mmpll_p_vco),
 138	.clkr = {
 139		.enable_reg = 0x100,
 140		.enable_mask = BIT(1),
 141		.hw.init = &(struct clk_init_data){
 142			.name = "mmpll1_early",
 143			.parent_data = &(const struct clk_parent_data){
 144				.fw_name = "xo",
 145			},
 146			.num_parents = 1,
 147			.ops = &clk_alpha_pll_ops,
 148		}
 149	},
 150};
 151
 152static struct clk_alpha_pll_postdiv mmpll1 = {
 153	.offset = 0x30,
 154	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 155	.width = 4,
 156	.clkr.hw.init = &(struct clk_init_data){
 157		.name = "mmpll1",
 158		.parent_hws = (const struct clk_hw *[]){ &mmpll1_early.clkr.hw },
 159		.num_parents = 1,
 160		.ops = &clk_alpha_pll_postdiv_ops,
 161		.flags = CLK_SET_RATE_PARENT,
 162	},
 163};
 164
 165static struct clk_alpha_pll mmpll3_early = {
 166	.offset = 0x60,
 167	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 168	.vco_table = mmpll_p_vco,
 169	.num_vco = ARRAY_SIZE(mmpll_p_vco),
 170	.clkr.hw.init = &(struct clk_init_data){
 171		.name = "mmpll3_early",
 172		.parent_data = &(const struct clk_parent_data){
 173				.fw_name = "xo",
 174		},
 175		.num_parents = 1,
 176		.ops = &clk_alpha_pll_ops,
 177	},
 178};
 179
 180static struct clk_alpha_pll_postdiv mmpll3 = {
 181	.offset = 0x60,
 182	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 183	.width = 4,
 184	.clkr.hw.init = &(struct clk_init_data){
 185		.name = "mmpll3",
 186		.parent_hws = (const struct clk_hw *[]){ &mmpll3_early.clkr.hw },
 187		.num_parents = 1,
 188		.ops = &clk_alpha_pll_postdiv_ops,
 189		.flags = CLK_SET_RATE_PARENT,
 190	},
 191};
 192
 193static struct clk_alpha_pll mmpll4_early = {
 194	.offset = 0x90,
 195	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 196	.vco_table = mmpll_t_vco,
 197	.num_vco = ARRAY_SIZE(mmpll_t_vco),
 198	.clkr.hw.init = &(struct clk_init_data){
 199		.name = "mmpll4_early",
 200		.parent_data = &(const struct clk_parent_data){
 201				.fw_name = "xo",
 202		},
 203		.num_parents = 1,
 204		.ops = &clk_alpha_pll_ops,
 205	},
 206};
 207
 208static struct clk_alpha_pll_postdiv mmpll4 = {
 209	.offset = 0x90,
 210	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 211	.width = 2,
 212	.clkr.hw.init = &(struct clk_init_data){
 213		.name = "mmpll4",
 214		.parent_hws = (const struct clk_hw *[]){ &mmpll4_early.clkr.hw },
 215		.num_parents = 1,
 216		.ops = &clk_alpha_pll_postdiv_ops,
 217		.flags = CLK_SET_RATE_PARENT,
 218	},
 219};
 220
 221static const struct parent_map mmcc_xo_gpll0_mmpll1_map[] = {
 222	{ P_XO, 0 },
 223	{ P_GPLL0, 5 },
 224	{ P_MMPLL1, 2 }
 225};
 226
 227static const struct clk_parent_data mmcc_xo_gpll0_mmpll1[] = {
 228	{ .fw_name = "xo" },
 229	{ .fw_name = "gpll0" },
 230	{ .hw = &mmpll1.clkr.hw },
 231};
 232
 233static const struct parent_map mmcc_xo_gpll0_mmpll0_map[] = {
 234	{ P_XO, 0 },
 235	{ P_GPLL0, 5 },
 236	{ P_MMPLL0, 1 }
 237};
 238
 239static const struct clk_parent_data mmcc_xo_gpll0_mmpll0[] = {
 240	{ .fw_name = "xo" },
 241	{ .fw_name = "gpll0" },
 242	{ .hw = &mmpll0.clkr.hw },
 243};
 244
 245static const struct parent_map mmcc_xo_gpll0_mmpll0_mmpll3_map[] = {
 246	{ P_XO, 0 },
 247	{ P_GPLL0, 5 },
 248	{ P_MMPLL0, 1 },
 249	{ P_MMPLL3, 3 }
 250};
 251
 252static const struct clk_parent_data mmcc_xo_gpll0_mmpll0_mmpll3[] = {
 253	{ .fw_name = "xo" },
 254	{ .fw_name = "gpll0" },
 255	{ .hw = &mmpll0.clkr.hw },
 256	{ .hw = &mmpll3.clkr.hw },
 257};
 258
 259static const struct parent_map mmcc_xo_gpll0_mmpll0_mmpll4_map[] = {
 260	{ P_XO, 0 },
 261	{ P_GPLL0, 5 },
 262	{ P_MMPLL0, 1 },
 263	{ P_MMPLL4, 3 }
 264};
 265
 266static const struct clk_parent_data mmcc_xo_gpll0_mmpll0_mmpll4[] = {
 267	{ .fw_name = "xo" },
 268	{ .fw_name = "gpll0" },
 269	{ .hw = &mmpll0.clkr.hw },
 270	{ .hw = &mmpll4.clkr.hw },
 271};
 272
 273static struct clk_alpha_pll mmpll5_early = {
 274	.offset = 0xc0,
 275	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 276	.vco_table = mmpll_p_vco,
 277	.num_vco = ARRAY_SIZE(mmpll_p_vco),
 278	.clkr.hw.init = &(struct clk_init_data){
 279		.name = "mmpll5_early",
 280		.parent_data = &(const struct clk_parent_data){
 281				.fw_name = "xo",
 282		},
 283		.num_parents = 1,
 284		.ops = &clk_alpha_pll_ops,
 285	},
 286};
 287
 288static struct clk_alpha_pll_postdiv mmpll5 = {
 289	.offset = 0xc0,
 290	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 291	.width = 4,
 292	.clkr.hw.init = &(struct clk_init_data){
 293		.name = "mmpll5",
 294		.parent_hws = (const struct clk_hw *[]){ &mmpll5_early.clkr.hw },
 295		.num_parents = 1,
 296		.ops = &clk_alpha_pll_postdiv_ops,
 297		.flags = CLK_SET_RATE_PARENT,
 298	},
 299};
 300
 301static const struct freq_tbl ftbl_ahb_clk_src[] = {
 302	/* Note: There might be more frequencies desired here. */
 303	F(19200000, P_XO, 1, 0, 0),
 304	F(40000000, P_GPLL0, 15, 0, 0),
 305	F(80000000, P_MMPLL0, 10, 0, 0),
 306	{ }
 307};
 308
 309static struct clk_rcg2 ahb_clk_src = {
 310	.cmd_rcgr = 0x5000,
 311	.hid_width = 5,
 312	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 313	.freq_tbl = ftbl_ahb_clk_src,
 314	.clkr.hw.init = &(struct clk_init_data){
 315		.name = "ahb_clk_src",
 316		.parent_data = mmcc_xo_gpll0_mmpll0,
 317		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 318		.ops = &clk_rcg2_ops,
 319	},
 320};
 321
 322static const struct freq_tbl ftbl_axi_clk_src[] = {
 323	F(75000000, P_GPLL0, 8, 0, 0),
 324	F(150000000, P_GPLL0, 4, 0, 0),
 325	F(333430000, P_MMPLL1, 3.5, 0, 0),
 326	F(466800000, P_MMPLL1, 2.5, 0, 0),
 327	{ }
 328};
 329
 330static const struct freq_tbl ftbl_axi_clk_src_8992[] = {
 331	F(75000000, P_GPLL0, 8, 0, 0),
 332	F(150000000, P_GPLL0, 4, 0, 0),
 333	F(300000000, P_GPLL0, 2, 0, 0),
 334	F(404000000, P_MMPLL1, 2, 0, 0),
 335	{ }
 336};
 337
 338static struct clk_rcg2 axi_clk_src = {
 339	.cmd_rcgr = 0x5040,
 340	.hid_width = 5,
 341	.parent_map = mmcc_xo_gpll0_mmpll1_map,
 342	.freq_tbl = ftbl_axi_clk_src,
 343	.clkr.hw.init = &(struct clk_init_data){
 344		.name = "axi_clk_src",
 345		.parent_data = mmcc_xo_gpll0_mmpll1,
 346		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll1),
 347		.ops = &clk_rcg2_ops,
 348	},
 349};
 350
 351static const struct freq_tbl ftbl_csi0_1_2_3_clk_src[] = {
 352	F(100000000, P_GPLL0, 6, 0, 0),
 353	F(240000000, P_GPLL0, 2.5, 0, 0),
 354	F(266670000, P_MMPLL0, 3, 0, 0),
 355	{ }
 356};
 357
 358static const struct freq_tbl ftbl_csi0_1_2_3_clk_src_8992[] = {
 359	F(100000000, P_GPLL0, 6, 0, 0),
 360	F(266670000, P_MMPLL0, 3, 0, 0),
 361	{ }
 362};
 363
 364static struct clk_rcg2 csi0_clk_src = {
 365	.cmd_rcgr = 0x3090,
 366	.hid_width = 5,
 367	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 368	.freq_tbl = ftbl_csi0_1_2_3_clk_src,
 369	.clkr.hw.init = &(struct clk_init_data){
 370		.name = "csi0_clk_src",
 371		.parent_data = mmcc_xo_gpll0_mmpll0,
 372		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 373		.ops = &clk_rcg2_ops,
 374	},
 375};
 376
 377static const struct freq_tbl ftbl_vcodec0_clk_src[] = {
 378	F(66670000, P_GPLL0, 9, 0, 0),
 379	F(100000000, P_GPLL0, 6, 0, 0),
 380	F(133330000, P_GPLL0, 4.5, 0, 0),
 381	F(150000000, P_GPLL0, 4, 0, 0),
 382	F(200000000, P_MMPLL0, 4, 0, 0),
 383	F(240000000, P_GPLL0, 2.5, 0, 0),
 384	F(266670000, P_MMPLL0, 3, 0, 0),
 385	F(320000000, P_MMPLL0, 2.5, 0, 0),
 386	F(510000000, P_MMPLL3, 2, 0, 0),
 387	{ }
 388};
 389
 390static const struct freq_tbl ftbl_vcodec0_clk_src_8992[] = {
 391	F(66670000, P_GPLL0, 9, 0, 0),
 392	F(100000000, P_GPLL0, 6, 0, 0),
 393	F(133330000, P_GPLL0, 4.5, 0, 0),
 394	F(200000000, P_MMPLL0, 4, 0, 0),
 395	F(320000000, P_MMPLL0, 2.5, 0, 0),
 396	F(510000000, P_MMPLL3, 2, 0, 0),
 397	{ }
 398};
 399
 400static struct clk_rcg2 vcodec0_clk_src = {
 401	.cmd_rcgr = 0x1000,
 402	.mnd_width = 8,
 403	.hid_width = 5,
 404	.parent_map = mmcc_xo_gpll0_mmpll0_mmpll3_map,
 405	.freq_tbl = ftbl_vcodec0_clk_src,
 406	.clkr.hw.init = &(struct clk_init_data){
 407		.name = "vcodec0_clk_src",
 408		.parent_data = mmcc_xo_gpll0_mmpll0_mmpll3,
 409		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll3),
 410		.ops = &clk_rcg2_ops,
 411	},
 412};
 413
 414static struct clk_rcg2 csi1_clk_src = {
 415	.cmd_rcgr = 0x3100,
 416	.hid_width = 5,
 417	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 418	.freq_tbl = ftbl_csi0_1_2_3_clk_src,
 419	.clkr.hw.init = &(struct clk_init_data){
 420		.name = "csi1_clk_src",
 421		.parent_data = mmcc_xo_gpll0_mmpll0,
 422		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 423		.ops = &clk_rcg2_ops,
 424	},
 425};
 426
 427static struct clk_rcg2 csi2_clk_src = {
 428	.cmd_rcgr = 0x3160,
 429	.hid_width = 5,
 430	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 431	.freq_tbl = ftbl_csi0_1_2_3_clk_src,
 432	.clkr.hw.init = &(struct clk_init_data){
 433		.name = "csi2_clk_src",
 434		.parent_data = mmcc_xo_gpll0_mmpll0,
 435		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 436		.ops = &clk_rcg2_ops,
 437	},
 438};
 439
 440static struct clk_rcg2 csi3_clk_src = {
 441	.cmd_rcgr = 0x31c0,
 442	.hid_width = 5,
 443	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 444	.freq_tbl = ftbl_csi0_1_2_3_clk_src,
 445	.clkr.hw.init = &(struct clk_init_data){
 446		.name = "csi3_clk_src",
 447		.parent_data = mmcc_xo_gpll0_mmpll0,
 448		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 449		.ops = &clk_rcg2_ops,
 450	},
 451};
 452
 453static const struct freq_tbl ftbl_vfe0_clk_src[] = {
 454	F(80000000, P_GPLL0, 7.5, 0, 0),
 455	F(100000000, P_GPLL0, 6, 0, 0),
 456	F(200000000, P_GPLL0, 3, 0, 0),
 457	F(320000000, P_MMPLL0, 2.5, 0, 0),
 458	F(400000000, P_MMPLL0, 2, 0, 0),
 459	F(480000000, P_MMPLL4, 2, 0, 0),
 460	F(533330000, P_MMPLL0, 1.5, 0, 0),
 461	F(600000000, P_GPLL0, 1, 0, 0),
 462	{ }
 463};
 464
 465static const struct freq_tbl ftbl_vfe0_1_clk_src_8992[] = {
 466	F(80000000, P_GPLL0, 7.5, 0, 0),
 467	F(100000000, P_GPLL0, 6, 0, 0),
 468	F(200000000, P_GPLL0, 3, 0, 0),
 469	F(320000000, P_MMPLL0, 2.5, 0, 0),
 470	F(480000000, P_MMPLL4, 2, 0, 0),
 471	F(600000000, P_GPLL0, 1, 0, 0),
 472	{ }
 473};
 474
 475static struct clk_rcg2 vfe0_clk_src = {
 476	.cmd_rcgr = 0x3600,
 477	.hid_width = 5,
 478	.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
 479	.freq_tbl = ftbl_vfe0_clk_src,
 480	.clkr.hw.init = &(struct clk_init_data){
 481		.name = "vfe0_clk_src",
 482		.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
 483		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
 484		.ops = &clk_rcg2_ops,
 485	},
 486};
 487
 488static const struct freq_tbl ftbl_vfe1_clk_src[] = {
 489	F(80000000, P_GPLL0, 7.5, 0, 0),
 490	F(100000000, P_GPLL0, 6, 0, 0),
 491	F(200000000, P_GPLL0, 3, 0, 0),
 492	F(320000000, P_MMPLL0, 2.5, 0, 0),
 493	F(400000000, P_MMPLL0, 2, 0, 0),
 494	F(533330000, P_MMPLL0, 1.5, 0, 0),
 495	{ }
 496};
 497
 498static struct clk_rcg2 vfe1_clk_src = {
 499	.cmd_rcgr = 0x3620,
 500	.hid_width = 5,
 501	.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
 502	.freq_tbl = ftbl_vfe1_clk_src,
 503	.clkr.hw.init = &(struct clk_init_data){
 504		.name = "vfe1_clk_src",
 505		.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
 506		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
 507		.ops = &clk_rcg2_ops,
 508	},
 509};
 510
 511static const struct freq_tbl ftbl_cpp_clk_src[] = {
 512	F(100000000, P_GPLL0, 6, 0, 0),
 513	F(200000000, P_GPLL0, 3, 0, 0),
 514	F(320000000, P_MMPLL0, 2.5, 0, 0),
 515	F(480000000, P_MMPLL4, 2, 0, 0),
 516	F(600000000, P_GPLL0, 1, 0, 0),
 517	F(640000000, P_MMPLL4, 1.5, 0, 0),
 518	{ }
 519};
 520
 521static const struct freq_tbl ftbl_cpp_clk_src_8992[] = {
 522	F(100000000, P_GPLL0, 6, 0, 0),
 523	F(200000000, P_GPLL0, 3, 0, 0),
 524	F(320000000, P_MMPLL0, 2.5, 0, 0),
 525	F(480000000, P_MMPLL4, 2, 0, 0),
 526	F(640000000, P_MMPLL4, 1.5, 0, 0),
 527	{ }
 528};
 529
 530static struct clk_rcg2 cpp_clk_src = {
 531	.cmd_rcgr = 0x3640,
 532	.hid_width = 5,
 533	.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
 534	.freq_tbl = ftbl_cpp_clk_src,
 535	.clkr.hw.init = &(struct clk_init_data){
 536		.name = "cpp_clk_src",
 537		.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
 538		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
 539		.ops = &clk_rcg2_ops,
 540	},
 541};
 542
 543static const struct freq_tbl ftbl_jpeg0_1_clk_src[] = {
 544	F(75000000, P_GPLL0, 8, 0, 0),
 545	F(150000000, P_GPLL0, 4, 0, 0),
 546	F(228570000, P_MMPLL0, 3.5, 0, 0),
 547	F(266670000, P_MMPLL0, 3, 0, 0),
 548	F(320000000, P_MMPLL0, 2.5, 0, 0),
 549	F(480000000, P_MMPLL4, 2, 0, 0),
 550	{ }
 551};
 552
 553static struct clk_rcg2 jpeg1_clk_src = {
 554	.cmd_rcgr = 0x3520,
 555	.hid_width = 5,
 556	.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
 557	.freq_tbl = ftbl_jpeg0_1_clk_src,
 558	.clkr.hw.init = &(struct clk_init_data){
 559		.name = "jpeg1_clk_src",
 560		.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
 561		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
 562		.ops = &clk_rcg2_ops,
 563	},
 564};
 565
 566static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
 567	F(75000000, P_GPLL0, 8, 0, 0),
 568	F(133330000, P_GPLL0, 4.5, 0, 0),
 569	F(150000000, P_GPLL0, 4, 0, 0),
 570	F(228570000, P_MMPLL0, 3.5, 0, 0),
 571	F(266670000, P_MMPLL0, 3, 0, 0),
 572	F(320000000, P_MMPLL0, 2.5, 0, 0),
 573	{ }
 574};
 575
 576static struct clk_rcg2 jpeg2_clk_src = {
 577	.cmd_rcgr = 0x3540,
 578	.hid_width = 5,
 579	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 580	.freq_tbl = ftbl_jpeg2_clk_src,
 581	.clkr.hw.init = &(struct clk_init_data){
 582		.name = "jpeg2_clk_src",
 583		.parent_data = mmcc_xo_gpll0_mmpll0,
 584		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 585		.ops = &clk_rcg2_ops,
 586	},
 587};
 588
 589static const struct freq_tbl ftbl_csi2phytimer_clk_src[] = {
 590	F(50000000, P_GPLL0, 12, 0, 0),
 591	F(100000000, P_GPLL0, 6, 0, 0),
 592	F(200000000, P_MMPLL0, 4, 0, 0),
 593	{ }
 594};
 595
 596static struct clk_rcg2 csi2phytimer_clk_src = {
 597	.cmd_rcgr = 0x3060,
 598	.hid_width = 5,
 599	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 600	.freq_tbl = ftbl_csi2phytimer_clk_src,
 601	.clkr.hw.init = &(struct clk_init_data){
 602		.name = "csi2phytimer_clk_src",
 603		.parent_data = mmcc_xo_gpll0_mmpll0,
 604		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 605		.ops = &clk_rcg2_ops,
 606	},
 607};
 608
 609static const struct freq_tbl ftbl_fd_core_clk_src[] = {
 610	F(60000000, P_GPLL0, 10, 0, 0),
 611	F(200000000, P_GPLL0, 3, 0, 0),
 612	F(320000000, P_MMPLL0, 2.5, 0, 0),
 613	F(400000000, P_MMPLL0, 2, 0, 0),
 614	{ }
 615};
 616
 617static struct clk_rcg2 fd_core_clk_src = {
 618	.cmd_rcgr = 0x3b00,
 619	.hid_width = 5,
 620	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 621	.freq_tbl = ftbl_fd_core_clk_src,
 622	.clkr.hw.init = &(struct clk_init_data){
 623		.name = "fd_core_clk_src",
 624		.parent_data = mmcc_xo_gpll0_mmpll0,
 625		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 626		.ops = &clk_rcg2_ops,
 627	},
 628};
 629
 630static const struct freq_tbl ftbl_mdp_clk_src[] = {
 631	F(85710000, P_GPLL0, 7, 0, 0),
 632	F(100000000, P_GPLL0, 6, 0, 0),
 633	F(120000000, P_GPLL0, 5, 0, 0),
 634	F(150000000, P_GPLL0, 4, 0, 0),
 635	F(171430000, P_GPLL0, 3.5, 0, 0),
 636	F(200000000, P_GPLL0, 3, 0, 0),
 637	F(240000000, P_GPLL0, 2.5, 0, 0),
 638	F(266670000, P_MMPLL0, 3, 0, 0),
 639	F(300000000, P_GPLL0, 2, 0, 0),
 640	F(320000000, P_MMPLL0, 2.5, 0, 0),
 641	F(400000000, P_MMPLL0, 2, 0, 0),
 642	{ }
 643};
 644
 645static const struct freq_tbl ftbl_mdp_clk_src_8992[] = {
 646	F(85710000, P_GPLL0, 7, 0, 0),
 647	F(171430000, P_GPLL0, 3.5, 0, 0),
 648	F(200000000, P_GPLL0, 3, 0, 0),
 649	F(240000000, P_GPLL0, 2.5, 0, 0),
 650	F(266670000, P_MMPLL0, 3, 0, 0),
 651	F(320000000, P_MMPLL0, 2.5, 0, 0),
 652	F(400000000, P_MMPLL0, 2, 0, 0),
 653	{ }
 654};
 655
 656static struct clk_rcg2 mdp_clk_src = {
 657	.cmd_rcgr = 0x2040,
 658	.hid_width = 5,
 659	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 660	.freq_tbl = ftbl_mdp_clk_src,
 661	.clkr.hw.init = &(struct clk_init_data){
 662		.name = "mdp_clk_src",
 663		.parent_data = mmcc_xo_gpll0_mmpll0,
 664		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 665		.ops = &clk_rcg2_ops,
 666	},
 667};
 668
 669static struct clk_rcg2 pclk0_clk_src = {
 670	.cmd_rcgr = 0x2000,
 671	.mnd_width = 8,
 672	.hid_width = 5,
 673	.parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
 674	.clkr.hw.init = &(struct clk_init_data){
 675		.name = "pclk0_clk_src",
 676		.parent_data = mmcc_xo_dsi0pll_dsi1pll,
 677		.num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
 678		.ops = &clk_pixel_ops,
 679		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 680	},
 681};
 682
 683static struct clk_rcg2 pclk1_clk_src = {
 684	.cmd_rcgr = 0x2020,
 685	.mnd_width = 8,
 686	.hid_width = 5,
 687	.parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
 688	.clkr.hw.init = &(struct clk_init_data){
 689		.name = "pclk1_clk_src",
 690		.parent_data = mmcc_xo_dsi0pll_dsi1pll,
 691		.num_parents = ARRAY_SIZE(mmcc_xo_dsi0pll_dsi1pll),
 692		.ops = &clk_pixel_ops,
 693		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 694	},
 695};
 696
 697static const struct freq_tbl ftbl_ocmemnoc_clk_src[] = {
 698	F(19200000, P_XO, 1, 0, 0),
 699	F(75000000, P_GPLL0, 8, 0, 0),
 700	F(100000000, P_GPLL0, 6, 0, 0),
 701	F(150000000, P_GPLL0, 4, 0, 0),
 702	F(228570000, P_MMPLL0, 3.5, 0, 0),
 703	F(266670000, P_MMPLL0, 3, 0, 0),
 704	F(320000000, P_MMPLL0, 2.5, 0, 0),
 705	F(400000000, P_MMPLL0, 2, 0, 0),
 706	{ }
 707};
 708
 709static const struct freq_tbl ftbl_ocmemnoc_clk_src_8992[] = {
 710	F(19200000, P_XO, 1, 0, 0),
 711	F(75000000, P_GPLL0, 8, 0, 0),
 712	F(100000000, P_GPLL0, 6, 0, 0),
 713	F(150000000, P_GPLL0, 4, 0, 0),
 714	F(320000000, P_MMPLL0, 2.5, 0, 0),
 715	F(400000000, P_MMPLL0, 2, 0, 0),
 716	{ }
 717};
 718
 719static struct clk_rcg2 ocmemnoc_clk_src = {
 720	.cmd_rcgr = 0x5090,
 721	.hid_width = 5,
 722	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 723	.freq_tbl = ftbl_ocmemnoc_clk_src,
 724	.clkr.hw.init = &(struct clk_init_data){
 725		.name = "ocmemnoc_clk_src",
 726		.parent_data = mmcc_xo_gpll0_mmpll0,
 727		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 728		.ops = &clk_rcg2_ops,
 729	},
 730};
 731
 732static const struct freq_tbl ftbl_cci_clk_src[] = {
 733	F(19200000, P_XO, 1, 0, 0),
 734	F(37500000, P_GPLL0, 16, 0, 0),
 735	F(50000000, P_GPLL0, 12, 0, 0),
 736	F(100000000, P_GPLL0, 6, 0, 0),
 737	{ }
 738};
 739
 740static struct clk_rcg2 cci_clk_src = {
 741	.cmd_rcgr = 0x3300,
 742	.mnd_width = 8,
 743	.hid_width = 5,
 744	.parent_map = mmcc_xo_gpll0_map,
 745	.freq_tbl = ftbl_cci_clk_src,
 746	.clkr.hw.init = &(struct clk_init_data){
 747		.name = "cci_clk_src",
 748		.parent_data = mmcc_xo_gpll0,
 749		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
 750		.ops = &clk_rcg2_ops,
 751	},
 752};
 753
 754static const struct freq_tbl ftbl_mmss_gp0_1_clk_src[] = {
 755	F(10000, P_XO, 16, 10, 120),
 756	F(24000, P_GPLL0, 16, 1, 50),
 757	F(6000000, P_GPLL0, 10, 1, 10),
 758	F(12000000, P_GPLL0, 10, 1, 5),
 759	F(13000000, P_GPLL0, 4, 13, 150),
 760	F(24000000, P_GPLL0, 5, 1, 5),
 761	{ }
 762};
 763
 764static struct clk_rcg2 mmss_gp0_clk_src = {
 765	.cmd_rcgr = 0x3420,
 766	.mnd_width = 8,
 767	.hid_width = 5,
 768	.parent_map = mmcc_xo_gpll0_map,
 769	.freq_tbl = ftbl_mmss_gp0_1_clk_src,
 770	.clkr.hw.init = &(struct clk_init_data){
 771		.name = "mmss_gp0_clk_src",
 772		.parent_data = mmcc_xo_gpll0,
 773		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
 774		.ops = &clk_rcg2_ops,
 775	},
 776};
 777
 778static struct clk_rcg2 mmss_gp1_clk_src = {
 779	.cmd_rcgr = 0x3450,
 780	.mnd_width = 8,
 781	.hid_width = 5,
 782	.parent_map = mmcc_xo_gpll0_map,
 783	.freq_tbl = ftbl_mmss_gp0_1_clk_src,
 784	.clkr.hw.init = &(struct clk_init_data){
 785		.name = "mmss_gp1_clk_src",
 786		.parent_data = mmcc_xo_gpll0,
 787		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
 788		.ops = &clk_rcg2_ops,
 789	},
 790};
 791
 792static struct clk_rcg2 jpeg0_clk_src = {
 793	.cmd_rcgr = 0x3500,
 794	.hid_width = 5,
 795	.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
 796	.freq_tbl = ftbl_jpeg0_1_clk_src,
 797	.clkr.hw.init = &(struct clk_init_data){
 798		.name = "jpeg0_clk_src",
 799		.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
 800		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
 801		.ops = &clk_rcg2_ops,
 802	},
 803};
 804
 805static struct clk_rcg2 jpeg_dma_clk_src = {
 806	.cmd_rcgr = 0x3560,
 807	.hid_width = 5,
 808	.parent_map = mmcc_xo_gpll0_mmpll0_mmpll4_map,
 809	.freq_tbl = ftbl_jpeg0_1_clk_src,
 810	.clkr.hw.init = &(struct clk_init_data){
 811		.name = "jpeg_dma_clk_src",
 812		.parent_data = mmcc_xo_gpll0_mmpll0_mmpll4,
 813		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0_mmpll4),
 814		.ops = &clk_rcg2_ops,
 815	},
 816};
 817
 818static const struct freq_tbl ftbl_mclk0_1_2_3_clk_src[] = {
 819	F(4800000, P_XO, 4, 0, 0),
 820	F(6000000, P_GPLL0, 10, 1, 10),
 821	F(8000000, P_GPLL0, 15, 1, 5),
 822	F(9600000, P_XO, 2, 0, 0),
 823	F(16000000, P_MMPLL0, 10, 1, 5),
 824	F(19200000, P_XO, 1, 0, 0),
 825	F(24000000, P_GPLL0, 5, 1, 5),
 826	F(32000000, P_MMPLL0, 5, 1, 5),
 827	F(48000000, P_GPLL0, 12.5, 0, 0),
 828	F(64000000, P_MMPLL0, 12.5, 0, 0),
 829	{ }
 830};
 831
 832static const struct freq_tbl ftbl_mclk0_clk_src_8992[] = {
 833	F(4800000, P_XO, 4, 0, 0),
 834	F(6000000, P_MMPLL4, 10, 1, 16),
 835	F(8000000, P_MMPLL4, 10, 1, 12),
 836	F(9600000, P_XO, 2, 0, 0),
 837	F(12000000, P_MMPLL4, 10, 1, 8),
 838	F(16000000, P_MMPLL4, 10, 1, 6),
 839	F(19200000, P_XO, 1, 0, 0),
 840	F(24000000, P_MMPLL4, 10, 1, 4),
 841	F(32000000, P_MMPLL4, 10, 1, 3),
 842	F(48000000, P_MMPLL4, 10, 1, 2),
 843	F(64000000, P_MMPLL4, 15, 0, 0),
 844	{ }
 845};
 846
 847static const struct freq_tbl ftbl_mclk1_2_3_clk_src_8992[] = {
 848	F(4800000, P_XO, 4, 0, 0),
 849	F(6000000, P_MMPLL4, 10, 1, 16),
 850	F(8000000, P_MMPLL4, 10, 1, 12),
 851	F(9600000, P_XO, 2, 0, 0),
 852	F(16000000, P_MMPLL4, 10, 1, 6),
 853	F(19200000, P_XO, 1, 0, 0),
 854	F(24000000, P_MMPLL4, 10, 1, 4),
 855	F(32000000, P_MMPLL4, 10, 1, 3),
 856	F(48000000, P_MMPLL4, 10, 1, 2),
 857	F(64000000, P_MMPLL4, 15, 0, 0),
 858	{ }
 859};
 860
 861static struct clk_rcg2 mclk0_clk_src = {
 862	.cmd_rcgr = 0x3360,
 863	.mnd_width = 8,
 864	.hid_width = 5,
 865	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 866	.freq_tbl = ftbl_mclk0_1_2_3_clk_src,
 867	.clkr.hw.init = &(struct clk_init_data){
 868		.name = "mclk0_clk_src",
 869		.parent_data = mmcc_xo_gpll0_mmpll0,
 870		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 871		.ops = &clk_rcg2_ops,
 872	},
 873};
 874
 875static struct clk_rcg2 mclk1_clk_src = {
 876	.cmd_rcgr = 0x3390,
 877	.mnd_width = 8,
 878	.hid_width = 5,
 879	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 880	.freq_tbl = ftbl_mclk0_1_2_3_clk_src,
 881	.clkr.hw.init = &(struct clk_init_data){
 882		.name = "mclk1_clk_src",
 883		.parent_data = mmcc_xo_gpll0_mmpll0,
 884		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 885		.ops = &clk_rcg2_ops,
 886	},
 887};
 888
 889static struct clk_rcg2 mclk2_clk_src = {
 890	.cmd_rcgr = 0x33c0,
 891	.mnd_width = 8,
 892	.hid_width = 5,
 893	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 894	.freq_tbl = ftbl_mclk0_1_2_3_clk_src,
 895	.clkr.hw.init = &(struct clk_init_data){
 896		.name = "mclk2_clk_src",
 897		.parent_data = mmcc_xo_gpll0_mmpll0,
 898		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 899		.ops = &clk_rcg2_ops,
 900	},
 901};
 902
 903static struct clk_rcg2 mclk3_clk_src = {
 904	.cmd_rcgr = 0x33f0,
 905	.mnd_width = 8,
 906	.hid_width = 5,
 907	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 908	.freq_tbl = ftbl_mclk0_1_2_3_clk_src,
 909	.clkr.hw.init = &(struct clk_init_data){
 910		.name = "mclk3_clk_src",
 911		.parent_data = mmcc_xo_gpll0_mmpll0,
 912		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 913		.ops = &clk_rcg2_ops,
 914	},
 915};
 916
 917static const struct freq_tbl ftbl_csi0_1phytimer_clk_src[] = {
 918	F(50000000, P_GPLL0, 12, 0, 0),
 919	F(100000000, P_GPLL0, 6, 0, 0),
 920	F(200000000, P_MMPLL0, 4, 0, 0),
 921	{ }
 922};
 923
 924static struct clk_rcg2 csi0phytimer_clk_src = {
 925	.cmd_rcgr = 0x3000,
 926	.hid_width = 5,
 927	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 928	.freq_tbl = ftbl_csi0_1phytimer_clk_src,
 929	.clkr.hw.init = &(struct clk_init_data){
 930		.name = "csi0phytimer_clk_src",
 931		.parent_data = mmcc_xo_gpll0_mmpll0,
 932		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 933		.ops = &clk_rcg2_ops,
 934	},
 935};
 936
 937static struct clk_rcg2 csi1phytimer_clk_src = {
 938	.cmd_rcgr = 0x3030,
 939	.hid_width = 5,
 940	.parent_map = mmcc_xo_gpll0_mmpll0_map,
 941	.freq_tbl = ftbl_csi0_1phytimer_clk_src,
 942	.clkr.hw.init = &(struct clk_init_data){
 943		.name = "csi1phytimer_clk_src",
 944		.parent_data = mmcc_xo_gpll0_mmpll0,
 945		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0_mmpll0),
 946		.ops = &clk_rcg2_ops,
 947	},
 948};
 949
 950static struct clk_rcg2 byte0_clk_src = {
 951	.cmd_rcgr = 0x2120,
 952	.hid_width = 5,
 953	.parent_map = mmcc_xo_dsibyte_map,
 954	.clkr.hw.init = &(struct clk_init_data){
 955		.name = "byte0_clk_src",
 956		.parent_data = mmcc_xo_dsibyte,
 957		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
 958		.ops = &clk_byte2_ops,
 959		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 960	},
 961};
 962
 963static struct clk_rcg2 byte1_clk_src = {
 964	.cmd_rcgr = 0x2140,
 965	.hid_width = 5,
 966	.parent_map = mmcc_xo_dsibyte_map,
 967	.clkr.hw.init = &(struct clk_init_data){
 968		.name = "byte1_clk_src",
 969		.parent_data = mmcc_xo_dsibyte,
 970		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
 971		.ops = &clk_byte2_ops,
 972		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 973	},
 974};
 975
 976static const struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
 977	F(19200000, P_XO, 1, 0, 0),
 978	{ }
 979};
 980
 981static struct clk_rcg2 esc0_clk_src = {
 982	.cmd_rcgr = 0x2160,
 983	.hid_width = 5,
 984	.parent_map = mmcc_xo_dsibyte_map,
 985	.freq_tbl = ftbl_mdss_esc0_1_clk,
 986	.clkr.hw.init = &(struct clk_init_data){
 987		.name = "esc0_clk_src",
 988		.parent_data = mmcc_xo_dsibyte,
 989		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
 990		.ops = &clk_rcg2_ops,
 991	},
 992};
 993
 994static struct clk_rcg2 esc1_clk_src = {
 995	.cmd_rcgr = 0x2180,
 996	.hid_width = 5,
 997	.parent_map = mmcc_xo_dsibyte_map,
 998	.freq_tbl = ftbl_mdss_esc0_1_clk,
 999	.clkr.hw.init = &(struct clk_init_data){
1000		.name = "esc1_clk_src",
1001		.parent_data = mmcc_xo_dsibyte,
1002		.num_parents = ARRAY_SIZE(mmcc_xo_dsibyte),
1003		.ops = &clk_rcg2_ops,
1004	},
1005};
1006
1007static const struct freq_tbl extpclk_freq_tbl[] = {
1008	{ .src = P_HDMIPLL },
1009	{ }
1010};
1011
1012static struct clk_rcg2 extpclk_clk_src = {
1013	.cmd_rcgr = 0x2060,
1014	.hid_width = 5,
1015	.parent_map = mmss_xo_hdmi_map,
1016	.freq_tbl = extpclk_freq_tbl,
1017	.clkr.hw.init = &(struct clk_init_data){
1018		.name = "extpclk_clk_src",
1019		.parent_data = mmss_xo_hdmi,
1020		.num_parents = ARRAY_SIZE(mmss_xo_hdmi),
1021		.ops = &clk_rcg2_ops,
1022		.flags = CLK_SET_RATE_PARENT,
1023	},
1024};
1025
1026static const struct freq_tbl ftbl_hdmi_clk_src[] = {
1027	F(19200000, P_XO, 1, 0, 0),
1028	{ }
1029};
1030
1031static struct clk_rcg2 hdmi_clk_src = {
1032	.cmd_rcgr = 0x2100,
1033	.hid_width = 5,
1034	.parent_map = mmcc_xo_gpll0_map,
1035	.freq_tbl = ftbl_hdmi_clk_src,
1036	.clkr.hw.init = &(struct clk_init_data){
1037		.name = "hdmi_clk_src",
1038		.parent_data = mmcc_xo_gpll0,
1039		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1040		.ops = &clk_rcg2_ops,
1041	},
1042};
1043
1044static const struct freq_tbl ftbl_mdss_vsync_clk[] = {
1045	F(19200000, P_XO, 1, 0, 0),
1046	{ }
1047};
1048
1049static struct clk_rcg2 vsync_clk_src = {
1050	.cmd_rcgr = 0x2080,
1051	.hid_width = 5,
1052	.parent_map = mmcc_xo_gpll0_map,
1053	.freq_tbl = ftbl_mdss_vsync_clk,
1054	.clkr.hw.init = &(struct clk_init_data){
1055		.name = "vsync_clk_src",
1056		.parent_data = mmcc_xo_gpll0,
1057		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1058		.ops = &clk_rcg2_ops,
1059	},
1060};
1061
1062static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
1063	F(19200000, P_XO, 1, 0, 0),
1064	{ }
1065};
1066
1067static struct clk_rcg2 rbbmtimer_clk_src = {
1068	.cmd_rcgr = 0x4090,
1069	.hid_width = 5,
1070	.parent_map = mmcc_xo_gpll0_map,
1071	.freq_tbl = ftbl_rbbmtimer_clk_src,
1072	.clkr.hw.init = &(struct clk_init_data){
1073		.name = "rbbmtimer_clk_src",
1074		.parent_data = mmcc_xo_gpll0,
1075		.num_parents = ARRAY_SIZE(mmcc_xo_gpll0),
1076		.ops = &clk_rcg2_ops,
1077	},
1078};
1079
1080static struct clk_branch camss_ahb_clk = {
1081	.halt_reg = 0x348c,
1082	.clkr = {
1083		.enable_reg = 0x348c,
1084		.enable_mask = BIT(0),
1085		.hw.init = &(struct clk_init_data){
1086			.name = "camss_ahb_clk",
1087			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1088			.num_parents = 1,
1089			.flags = CLK_SET_RATE_PARENT,
1090			.ops = &clk_branch2_ops,
1091		},
1092	},
1093};
1094
1095static struct clk_branch camss_cci_cci_ahb_clk = {
1096	.halt_reg = 0x3348,
1097	.clkr = {
1098		.enable_reg = 0x3348,
1099		.enable_mask = BIT(0),
1100		.hw.init = &(struct clk_init_data){
1101			.name = "camss_cci_cci_ahb_clk",
1102			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1103			.num_parents = 1,
1104			.flags = CLK_SET_RATE_PARENT,
1105			.ops = &clk_branch2_ops,
1106		},
1107	},
1108};
1109
1110static struct clk_branch camss_cci_cci_clk = {
1111	.halt_reg = 0x3344,
1112	.clkr = {
1113		.enable_reg = 0x3344,
1114		.enable_mask = BIT(0),
1115		.hw.init = &(struct clk_init_data){
1116			.name = "camss_cci_cci_clk",
1117			.parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1118			.num_parents = 1,
1119			.ops = &clk_branch2_ops,
1120		},
1121	},
1122};
1123
1124static struct clk_branch camss_vfe_cpp_ahb_clk = {
1125	.halt_reg = 0x36b4,
1126	.clkr = {
1127		.enable_reg = 0x36b4,
1128		.enable_mask = BIT(0),
1129		.hw.init = &(struct clk_init_data){
1130			.name = "camss_vfe_cpp_ahb_clk",
1131			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1132			.num_parents = 1,
1133			.flags = CLK_SET_RATE_PARENT,
1134			.ops = &clk_branch2_ops,
1135		},
1136	},
1137};
1138
1139static struct clk_branch camss_vfe_cpp_axi_clk = {
1140	.halt_reg = 0x36c4,
1141	.clkr = {
1142		.enable_reg = 0x36c4,
1143		.enable_mask = BIT(0),
1144		.hw.init = &(struct clk_init_data){
1145			.name = "camss_vfe_cpp_axi_clk",
1146			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1147			.num_parents = 1,
1148			.ops = &clk_branch2_ops,
1149		},
1150	},
1151};
1152
1153static struct clk_branch camss_vfe_cpp_clk = {
1154	.halt_reg = 0x36b0,
1155	.clkr = {
1156		.enable_reg = 0x36b0,
1157		.enable_mask = BIT(0),
1158		.hw.init = &(struct clk_init_data){
1159			.name = "camss_vfe_cpp_clk",
1160			.parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
1161			.num_parents = 1,
1162			.ops = &clk_branch2_ops,
1163		},
1164	},
1165};
1166
1167static struct clk_branch camss_csi0_ahb_clk = {
1168	.halt_reg = 0x30bc,
1169	.clkr = {
1170		.enable_reg = 0x30bc,
1171		.enable_mask = BIT(0),
1172		.hw.init = &(struct clk_init_data){
1173			.name = "camss_csi0_ahb_clk",
1174			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1175			.num_parents = 1,
1176			.flags = CLK_SET_RATE_PARENT,
1177			.ops = &clk_branch2_ops,
1178		},
1179	},
1180};
1181
1182static struct clk_branch camss_csi0_clk = {
1183	.halt_reg = 0x30b4,
1184	.clkr = {
1185		.enable_reg = 0x30b4,
1186		.enable_mask = BIT(0),
1187		.hw.init = &(struct clk_init_data){
1188			.name = "camss_csi0_clk",
1189			.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1190			.num_parents = 1,
1191			.ops = &clk_branch2_ops,
1192		},
1193	},
1194};
1195
1196static struct clk_branch camss_csi0phy_clk = {
1197	.halt_reg = 0x30c4,
1198	.clkr = {
1199		.enable_reg = 0x30c4,
1200		.enable_mask = BIT(0),
1201		.hw.init = &(struct clk_init_data){
1202			.name = "camss_csi0phy_clk",
1203			.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1204			.num_parents = 1,
1205			.ops = &clk_branch2_ops,
1206		},
1207	},
1208};
1209
1210static struct clk_branch camss_csi0pix_clk = {
1211	.halt_reg = 0x30e4,
1212	.clkr = {
1213		.enable_reg = 0x30e4,
1214		.enable_mask = BIT(0),
1215		.hw.init = &(struct clk_init_data){
1216			.name = "camss_csi0pix_clk",
1217			.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1218			.num_parents = 1,
1219			.ops = &clk_branch2_ops,
1220		},
1221	},
1222};
1223
1224static struct clk_branch camss_csi0rdi_clk = {
1225	.halt_reg = 0x30d4,
1226	.clkr = {
1227		.enable_reg = 0x30d4,
1228		.enable_mask = BIT(0),
1229		.hw.init = &(struct clk_init_data){
1230			.name = "camss_csi0rdi_clk",
1231			.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1232			.num_parents = 1,
1233			.ops = &clk_branch2_ops,
1234		},
1235	},
1236};
1237
1238static struct clk_branch camss_csi1_ahb_clk = {
1239	.halt_reg = 0x3128,
1240	.clkr = {
1241		.enable_reg = 0x3128,
1242		.enable_mask = BIT(0),
1243		.hw.init = &(struct clk_init_data){
1244			.name = "camss_csi1_ahb_clk",
1245			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1246			.num_parents = 1,
1247			.flags = CLK_SET_RATE_PARENT,
1248			.ops = &clk_branch2_ops,
1249		},
1250	},
1251};
1252
1253static struct clk_branch camss_csi1_clk = {
1254	.halt_reg = 0x3124,
1255	.clkr = {
1256		.enable_reg = 0x3124,
1257		.enable_mask = BIT(0),
1258		.hw.init = &(struct clk_init_data){
1259			.name = "camss_csi1_clk",
1260			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1261			.num_parents = 1,
1262			.ops = &clk_branch2_ops,
1263		},
1264	},
1265};
1266
1267static struct clk_branch camss_csi1phy_clk = {
1268	.halt_reg = 0x3134,
1269	.clkr = {
1270		.enable_reg = 0x3134,
1271		.enable_mask = BIT(0),
1272		.hw.init = &(struct clk_init_data){
1273			.name = "camss_csi1phy_clk",
1274			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1275			.num_parents = 1,
1276			.ops = &clk_branch2_ops,
1277		},
1278	},
1279};
1280
1281static struct clk_branch camss_csi1pix_clk = {
1282	.halt_reg = 0x3154,
1283	.clkr = {
1284		.enable_reg = 0x3154,
1285		.enable_mask = BIT(0),
1286		.hw.init = &(struct clk_init_data){
1287			.name = "camss_csi1pix_clk",
1288			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1289			.num_parents = 1,
1290			.ops = &clk_branch2_ops,
1291		},
1292	},
1293};
1294
1295static struct clk_branch camss_csi1rdi_clk = {
1296	.halt_reg = 0x3144,
1297	.clkr = {
1298		.enable_reg = 0x3144,
1299		.enable_mask = BIT(0),
1300		.hw.init = &(struct clk_init_data){
1301			.name = "camss_csi1rdi_clk",
1302			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1303			.num_parents = 1,
1304			.ops = &clk_branch2_ops,
1305		},
1306	},
1307};
1308
1309static struct clk_branch camss_csi2_ahb_clk = {
1310	.halt_reg = 0x3188,
1311	.clkr = {
1312		.enable_reg = 0x3188,
1313		.enable_mask = BIT(0),
1314		.hw.init = &(struct clk_init_data){
1315			.name = "camss_csi2_ahb_clk",
1316			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1317			.num_parents = 1,
1318			.flags = CLK_SET_RATE_PARENT,
1319			.ops = &clk_branch2_ops,
1320		},
1321	},
1322};
1323
1324static struct clk_branch camss_csi2_clk = {
1325	.halt_reg = 0x3184,
1326	.clkr = {
1327		.enable_reg = 0x3184,
1328		.enable_mask = BIT(0),
1329		.hw.init = &(struct clk_init_data){
1330			.name = "camss_csi2_clk",
1331			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1332			.num_parents = 1,
1333			.ops = &clk_branch2_ops,
1334		},
1335	},
1336};
1337
1338static struct clk_branch camss_csi2phy_clk = {
1339	.halt_reg = 0x3194,
1340	.clkr = {
1341		.enable_reg = 0x3194,
1342		.enable_mask = BIT(0),
1343		.hw.init = &(struct clk_init_data){
1344			.name = "camss_csi2phy_clk",
1345			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1346			.num_parents = 1,
1347			.ops = &clk_branch2_ops,
1348		},
1349	},
1350};
1351
1352static struct clk_branch camss_csi2pix_clk = {
1353	.halt_reg = 0x31b4,
1354	.clkr = {
1355		.enable_reg = 0x31b4,
1356		.enable_mask = BIT(0),
1357		.hw.init = &(struct clk_init_data){
1358			.name = "camss_csi2pix_clk",
1359			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1360			.num_parents = 1,
1361			.ops = &clk_branch2_ops,
1362		},
1363	},
1364};
1365
1366static struct clk_branch camss_csi2rdi_clk = {
1367	.halt_reg = 0x31a4,
1368	.clkr = {
1369		.enable_reg = 0x31a4,
1370		.enable_mask = BIT(0),
1371		.hw.init = &(struct clk_init_data){
1372			.name = "camss_csi2rdi_clk",
1373			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1374			.num_parents = 1,
1375			.ops = &clk_branch2_ops,
1376		},
1377	},
1378};
1379
1380static struct clk_branch camss_csi3_ahb_clk = {
1381	.halt_reg = 0x31e8,
1382	.clkr = {
1383		.enable_reg = 0x31e8,
1384		.enable_mask = BIT(0),
1385		.hw.init = &(struct clk_init_data){
1386			.name = "camss_csi3_ahb_clk",
1387			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1388			.num_parents = 1,
1389			.flags = CLK_SET_RATE_PARENT,
1390			.ops = &clk_branch2_ops,
1391		},
1392	},
1393};
1394
1395static struct clk_branch camss_csi3_clk = {
1396	.halt_reg = 0x31e4,
1397	.clkr = {
1398		.enable_reg = 0x31e4,
1399		.enable_mask = BIT(0),
1400		.hw.init = &(struct clk_init_data){
1401			.name = "camss_csi3_clk",
1402			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1403			.num_parents = 1,
1404			.ops = &clk_branch2_ops,
1405		},
1406	},
1407};
1408
1409static struct clk_branch camss_csi3phy_clk = {
1410	.halt_reg = 0x31f4,
1411	.clkr = {
1412		.enable_reg = 0x31f4,
1413		.enable_mask = BIT(0),
1414		.hw.init = &(struct clk_init_data){
1415			.name = "camss_csi3phy_clk",
1416			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1417			.num_parents = 1,
1418			.ops = &clk_branch2_ops,
1419		},
1420	},
1421};
1422
1423static struct clk_branch camss_csi3pix_clk = {
1424	.halt_reg = 0x3214,
1425	.clkr = {
1426		.enable_reg = 0x3214,
1427		.enable_mask = BIT(0),
1428		.hw.init = &(struct clk_init_data){
1429			.name = "camss_csi3pix_clk",
1430			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1431			.num_parents = 1,
1432			.ops = &clk_branch2_ops,
1433		},
1434	},
1435};
1436
1437static struct clk_branch camss_csi3rdi_clk = {
1438	.halt_reg = 0x3204,
1439	.clkr = {
1440		.enable_reg = 0x3204,
1441		.enable_mask = BIT(0),
1442		.hw.init = &(struct clk_init_data){
1443			.name = "camss_csi3rdi_clk",
1444			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1445			.num_parents = 1,
1446			.ops = &clk_branch2_ops,
1447		},
1448	},
1449};
1450
1451static struct clk_branch camss_csi_vfe0_clk = {
1452	.halt_reg = 0x3704,
1453	.clkr = {
1454		.enable_reg = 0x3704,
1455		.enable_mask = BIT(0),
1456		.hw.init = &(struct clk_init_data){
1457			.name = "camss_csi_vfe0_clk",
1458			.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1459			.num_parents = 1,
1460			.ops = &clk_branch2_ops,
1461		},
1462	},
1463};
1464
1465static struct clk_branch camss_csi_vfe1_clk = {
1466	.halt_reg = 0x3714,
1467	.clkr = {
1468		.enable_reg = 0x3714,
1469		.enable_mask = BIT(0),
1470		.hw.init = &(struct clk_init_data){
1471			.name = "camss_csi_vfe1_clk",
1472			.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1473			.num_parents = 1,
1474			.ops = &clk_branch2_ops,
1475		},
1476	},
1477};
1478
1479static struct clk_branch camss_gp0_clk = {
1480	.halt_reg = 0x3444,
1481	.clkr = {
1482		.enable_reg = 0x3444,
1483		.enable_mask = BIT(0),
1484		.hw.init = &(struct clk_init_data){
1485			.name = "camss_gp0_clk",
1486			.parent_hws = (const struct clk_hw *[]){ &mmss_gp0_clk_src.clkr.hw },
1487			.num_parents = 1,
1488			.ops = &clk_branch2_ops,
1489		},
1490	},
1491};
1492
1493static struct clk_branch camss_gp1_clk = {
1494	.halt_reg = 0x3474,
1495	.clkr = {
1496		.enable_reg = 0x3474,
1497		.enable_mask = BIT(0),
1498		.hw.init = &(struct clk_init_data){
1499			.name = "camss_gp1_clk",
1500			.parent_hws = (const struct clk_hw *[]){ &mmss_gp1_clk_src.clkr.hw },
1501			.num_parents = 1,
1502			.ops = &clk_branch2_ops,
1503		},
1504	},
1505};
1506
1507static struct clk_branch camss_ispif_ahb_clk = {
1508	.halt_reg = 0x3224,
1509	.clkr = {
1510		.enable_reg = 0x3224,
1511		.enable_mask = BIT(0),
1512		.hw.init = &(struct clk_init_data){
1513			.name = "camss_ispif_ahb_clk",
1514			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1515			.num_parents = 1,
1516			.flags = CLK_SET_RATE_PARENT,
1517			.ops = &clk_branch2_ops,
1518		},
1519	},
1520};
1521
1522static struct clk_branch camss_jpeg_dma_clk = {
1523	.halt_reg = 0x35c0,
1524	.clkr = {
1525		.enable_reg = 0x35c0,
1526		.enable_mask = BIT(0),
1527		.hw.init = &(struct clk_init_data){
1528			.name = "camss_jpeg_dma_clk",
1529			.parent_hws = (const struct clk_hw *[]){ &jpeg_dma_clk_src.clkr.hw },
1530			.num_parents = 1,
1531			.ops = &clk_branch2_ops,
1532		},
1533	},
1534};
1535
1536static struct clk_branch camss_jpeg_jpeg0_clk = {
1537	.halt_reg = 0x35a8,
1538	.clkr = {
1539		.enable_reg = 0x35a8,
1540		.enable_mask = BIT(0),
1541		.hw.init = &(struct clk_init_data){
1542			.name = "camss_jpeg_jpeg0_clk",
1543			.parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
1544			.num_parents = 1,
1545			.ops = &clk_branch2_ops,
1546		},
1547	},
1548};
1549
1550static struct clk_branch camss_jpeg_jpeg1_clk = {
1551	.halt_reg = 0x35ac,
1552	.clkr = {
1553		.enable_reg = 0x35ac,
1554		.enable_mask = BIT(0),
1555		.hw.init = &(struct clk_init_data){
1556			.name = "camss_jpeg_jpeg1_clk",
1557			.parent_hws = (const struct clk_hw *[]){ &jpeg1_clk_src.clkr.hw },
1558			.num_parents = 1,
1559			.ops = &clk_branch2_ops,
1560		},
1561	},
1562};
1563
1564static struct clk_branch camss_jpeg_jpeg2_clk = {
1565	.halt_reg = 0x35b0,
1566	.clkr = {
1567		.enable_reg = 0x35b0,
1568		.enable_mask = BIT(0),
1569		.hw.init = &(struct clk_init_data){
1570			.name = "camss_jpeg_jpeg2_clk",
1571			.parent_hws = (const struct clk_hw *[]){ &jpeg2_clk_src.clkr.hw },
1572			.num_parents = 1,
1573			.ops = &clk_branch2_ops,
1574		},
1575	},
1576};
1577
1578static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1579	.halt_reg = 0x35b4,
1580	.clkr = {
1581		.enable_reg = 0x35b4,
1582		.enable_mask = BIT(0),
1583		.hw.init = &(struct clk_init_data){
1584			.name = "camss_jpeg_jpeg_ahb_clk",
1585			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1586			.num_parents = 1,
1587			.flags = CLK_SET_RATE_PARENT,
1588			.ops = &clk_branch2_ops,
1589		},
1590	},
1591};
1592
1593static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1594	.halt_reg = 0x35b8,
1595	.clkr = {
1596		.enable_reg = 0x35b8,
1597		.enable_mask = BIT(0),
1598		.hw.init = &(struct clk_init_data){
1599			.name = "camss_jpeg_jpeg_axi_clk",
1600			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1601			.num_parents = 1,
1602			.ops = &clk_branch2_ops,
1603		},
1604	},
1605};
1606
1607static struct clk_branch camss_mclk0_clk = {
1608	.halt_reg = 0x3384,
1609	.clkr = {
1610		.enable_reg = 0x3384,
1611		.enable_mask = BIT(0),
1612		.hw.init = &(struct clk_init_data){
1613			.name = "camss_mclk0_clk",
1614			.parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1615			.num_parents = 1,
1616			.ops = &clk_branch2_ops,
1617		},
1618	},
1619};
1620
1621static struct clk_branch camss_mclk1_clk = {
1622	.halt_reg = 0x33b4,
1623	.clkr = {
1624		.enable_reg = 0x33b4,
1625		.enable_mask = BIT(0),
1626		.hw.init = &(struct clk_init_data){
1627			.name = "camss_mclk1_clk",
1628			.parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1629			.num_parents = 1,
1630			.ops = &clk_branch2_ops,
1631		},
1632	},
1633};
1634
1635static struct clk_branch camss_mclk2_clk = {
1636	.halt_reg = 0x33e4,
1637	.clkr = {
1638		.enable_reg = 0x33e4,
1639		.enable_mask = BIT(0),
1640		.hw.init = &(struct clk_init_data){
1641			.name = "camss_mclk2_clk",
1642			.parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
1643			.num_parents = 1,
1644			.ops = &clk_branch2_ops,
1645		},
1646	},
1647};
1648
1649static struct clk_branch camss_mclk3_clk = {
1650	.halt_reg = 0x3414,
1651	.clkr = {
1652		.enable_reg = 0x3414,
1653		.enable_mask = BIT(0),
1654		.hw.init = &(struct clk_init_data){
1655			.name = "camss_mclk3_clk",
1656			.parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
1657			.num_parents = 1,
1658			.ops = &clk_branch2_ops,
1659		},
1660	},
1661};
1662
1663static struct clk_branch camss_micro_ahb_clk = {
1664	.halt_reg = 0x3494,
1665	.clkr = {
1666		.enable_reg = 0x3494,
1667		.enable_mask = BIT(0),
1668		.hw.init = &(struct clk_init_data){
1669			.name = "camss_micro_ahb_clk",
1670			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1671			.num_parents = 1,
1672			.flags = CLK_SET_RATE_PARENT,
1673			.ops = &clk_branch2_ops,
1674		},
1675	},
1676};
1677
1678static struct clk_branch camss_phy0_csi0phytimer_clk = {
1679	.halt_reg = 0x3024,
1680	.clkr = {
1681		.enable_reg = 0x3024,
1682		.enable_mask = BIT(0),
1683		.hw.init = &(struct clk_init_data){
1684			.name = "camss_phy0_csi0phytimer_clk",
1685			.parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1686			.num_parents = 1,
1687			.ops = &clk_branch2_ops,
1688		},
1689	},
1690};
1691
1692static struct clk_branch camss_phy1_csi1phytimer_clk = {
1693	.halt_reg = 0x3054,
1694	.clkr = {
1695		.enable_reg = 0x3054,
1696		.enable_mask = BIT(0),
1697		.hw.init = &(struct clk_init_data){
1698			.name = "camss_phy1_csi1phytimer_clk",
1699			.parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1700			.num_parents = 1,
1701			.ops = &clk_branch2_ops,
1702		},
1703	},
1704};
1705
1706static struct clk_branch camss_phy2_csi2phytimer_clk = {
1707	.halt_reg = 0x3084,
1708	.clkr = {
1709		.enable_reg = 0x3084,
1710		.enable_mask = BIT(0),
1711		.hw.init = &(struct clk_init_data){
1712			.name = "camss_phy2_csi2phytimer_clk",
1713			.parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1714			.num_parents = 1,
1715			.ops = &clk_branch2_ops,
1716		},
1717	},
1718};
1719
1720static struct clk_branch camss_top_ahb_clk = {
1721	.halt_reg = 0x3484,
1722	.clkr = {
1723		.enable_reg = 0x3484,
1724		.enable_mask = BIT(0),
1725		.hw.init = &(struct clk_init_data){
1726			.name = "camss_top_ahb_clk",
1727			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1728			.num_parents = 1,
1729			.flags = CLK_SET_RATE_PARENT,
1730			.ops = &clk_branch2_ops,
1731		},
1732	},
1733};
1734
1735static struct clk_branch camss_vfe_vfe0_clk = {
1736	.halt_reg = 0x36a8,
1737	.clkr = {
1738		.enable_reg = 0x36a8,
1739		.enable_mask = BIT(0),
1740		.hw.init = &(struct clk_init_data){
1741			.name = "camss_vfe_vfe0_clk",
1742			.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1743			.num_parents = 1,
1744			.ops = &clk_branch2_ops,
1745		},
1746	},
1747};
1748
1749static struct clk_branch camss_vfe_vfe1_clk = {
1750	.halt_reg = 0x36ac,
1751	.clkr = {
1752		.enable_reg = 0x36ac,
1753		.enable_mask = BIT(0),
1754		.hw.init = &(struct clk_init_data){
1755			.name = "camss_vfe_vfe1_clk",
1756			.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1757			.num_parents = 1,
1758			.ops = &clk_branch2_ops,
1759		},
1760	},
1761};
1762
1763static struct clk_branch camss_vfe_vfe_ahb_clk = {
1764	.halt_reg = 0x36b8,
1765	.clkr = {
1766		.enable_reg = 0x36b8,
1767		.enable_mask = BIT(0),
1768		.hw.init = &(struct clk_init_data){
1769			.name = "camss_vfe_vfe_ahb_clk",
1770			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1771			.num_parents = 1,
1772			.flags = CLK_SET_RATE_PARENT,
1773			.ops = &clk_branch2_ops,
1774		},
1775	},
1776};
1777
1778static struct clk_branch camss_vfe_vfe_axi_clk = {
1779	.halt_reg = 0x36bc,
1780	.clkr = {
1781		.enable_reg = 0x36bc,
1782		.enable_mask = BIT(0),
1783		.hw.init = &(struct clk_init_data){
1784			.name = "camss_vfe_vfe_axi_clk",
1785			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1786			.num_parents = 1,
1787			.ops = &clk_branch2_ops,
1788		},
1789	},
1790};
1791
1792static struct clk_branch fd_ahb_clk = {
1793	.halt_reg = 0x3b74,
1794	.clkr = {
1795		.enable_reg = 0x3b74,
1796		.enable_mask = BIT(0),
1797		.hw.init = &(struct clk_init_data){
1798			.name = "fd_ahb_clk",
1799			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1800			.num_parents = 1,
1801			.ops = &clk_branch2_ops,
1802		},
1803	},
1804};
1805
1806static struct clk_branch fd_axi_clk = {
1807	.halt_reg = 0x3b70,
1808	.clkr = {
1809		.enable_reg = 0x3b70,
1810		.enable_mask = BIT(0),
1811		.hw.init = &(struct clk_init_data){
1812			.name = "fd_axi_clk",
1813			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1814			.num_parents = 1,
1815			.ops = &clk_branch2_ops,
1816		},
1817	},
1818};
1819
1820static struct clk_branch fd_core_clk = {
1821	.halt_reg = 0x3b68,
1822	.clkr = {
1823		.enable_reg = 0x3b68,
1824		.enable_mask = BIT(0),
1825		.hw.init = &(struct clk_init_data){
1826			.name = "fd_core_clk",
1827			.parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
1828			.num_parents = 1,
1829			.ops = &clk_branch2_ops,
1830		},
1831	},
1832};
1833
1834static struct clk_branch fd_core_uar_clk = {
1835	.halt_reg = 0x3b6c,
1836	.clkr = {
1837		.enable_reg = 0x3b6c,
1838		.enable_mask = BIT(0),
1839		.hw.init = &(struct clk_init_data){
1840			.name = "fd_core_uar_clk",
1841			.parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
1842			.num_parents = 1,
1843			.ops = &clk_branch2_ops,
1844		},
1845	},
1846};
1847
1848static struct clk_branch mdss_ahb_clk = {
1849	.halt_reg = 0x2308,
1850	.halt_check = BRANCH_HALT,
1851	.clkr = {
1852		.enable_reg = 0x2308,
1853		.enable_mask = BIT(0),
1854		.hw.init = &(struct clk_init_data){
1855			.name = "mdss_ahb_clk",
1856			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1857			.num_parents = 1,
1858			.flags = CLK_SET_RATE_PARENT,
1859			.ops = &clk_branch2_ops,
1860		},
1861	},
1862};
1863
1864static struct clk_branch mdss_axi_clk = {
1865	.halt_reg = 0x2310,
1866	.clkr = {
1867		.enable_reg = 0x2310,
1868		.enable_mask = BIT(0),
1869		.hw.init = &(struct clk_init_data){
1870			.name = "mdss_axi_clk",
1871			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1872			.num_parents = 1,
1873			.flags = CLK_SET_RATE_PARENT,
1874			.ops = &clk_branch2_ops,
1875		},
1876	},
1877};
1878
1879static struct clk_branch mdss_byte0_clk = {
1880	.halt_reg = 0x233c,
1881	.clkr = {
1882		.enable_reg = 0x233c,
1883		.enable_mask = BIT(0),
1884		.hw.init = &(struct clk_init_data){
1885			.name = "mdss_byte0_clk",
1886			.parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1887			.num_parents = 1,
1888			.flags = CLK_SET_RATE_PARENT,
1889			.ops = &clk_branch2_ops,
1890		},
1891	},
1892};
1893
1894static struct clk_branch mdss_byte1_clk = {
1895	.halt_reg = 0x2340,
1896	.clkr = {
1897		.enable_reg = 0x2340,
1898		.enable_mask = BIT(0),
1899		.hw.init = &(struct clk_init_data){
1900			.name = "mdss_byte1_clk",
1901			.parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1902			.num_parents = 1,
1903			.flags = CLK_SET_RATE_PARENT,
1904			.ops = &clk_branch2_ops,
1905		},
1906	},
1907};
1908
1909static struct clk_branch mdss_esc0_clk = {
1910	.halt_reg = 0x2344,
1911	.clkr = {
1912		.enable_reg = 0x2344,
1913		.enable_mask = BIT(0),
1914		.hw.init = &(struct clk_init_data){
1915			.name = "mdss_esc0_clk",
1916			.parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
1917			.num_parents = 1,
1918			.flags = CLK_SET_RATE_PARENT,
1919			.ops = &clk_branch2_ops,
1920		},
1921	},
1922};
1923
1924static struct clk_branch mdss_esc1_clk = {
1925	.halt_reg = 0x2348,
1926	.clkr = {
1927		.enable_reg = 0x2348,
1928		.enable_mask = BIT(0),
1929		.hw.init = &(struct clk_init_data){
1930			.name = "mdss_esc1_clk",
1931			.parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
1932			.num_parents = 1,
1933			.flags = CLK_SET_RATE_PARENT,
1934			.ops = &clk_branch2_ops,
1935		},
1936	},
1937};
1938
1939static struct clk_branch mdss_extpclk_clk = {
1940	.halt_reg = 0x2324,
1941	.clkr = {
1942		.enable_reg = 0x2324,
1943		.enable_mask = BIT(0),
1944		.hw.init = &(struct clk_init_data){
1945			.name = "mdss_extpclk_clk",
1946			.parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
1947			.num_parents = 1,
1948			.flags = CLK_SET_RATE_PARENT,
1949			.ops = &clk_branch2_ops,
1950		},
1951	},
1952};
1953
1954static struct clk_branch mdss_hdmi_ahb_clk = {
1955	.halt_reg = 0x230c,
1956	.clkr = {
1957		.enable_reg = 0x230c,
1958		.enable_mask = BIT(0),
1959		.hw.init = &(struct clk_init_data){
1960			.name = "mdss_hdmi_ahb_clk",
1961			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1962			.num_parents = 1,
1963			.flags = CLK_SET_RATE_PARENT,
1964			.ops = &clk_branch2_ops,
1965		},
1966	},
1967};
1968
1969static struct clk_branch mdss_hdmi_clk = {
1970	.halt_reg = 0x2338,
1971	.clkr = {
1972		.enable_reg = 0x2338,
1973		.enable_mask = BIT(0),
1974		.hw.init = &(struct clk_init_data){
1975			.name = "mdss_hdmi_clk",
1976			.parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
1977			.num_parents = 1,
1978			.flags = CLK_SET_RATE_PARENT,
1979			.ops = &clk_branch2_ops,
1980		},
1981	},
1982};
1983
1984static struct clk_branch mdss_mdp_clk = {
1985	.halt_reg = 0x231c,
1986	.clkr = {
1987		.enable_reg = 0x231c,
1988		.enable_mask = BIT(0),
1989		.hw.init = &(struct clk_init_data){
1990			.name = "mdss_mdp_clk",
1991			.parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1992			.num_parents = 1,
1993			.flags = CLK_SET_RATE_PARENT,
1994			.ops = &clk_branch2_ops,
1995		},
1996	},
1997};
1998
1999static struct clk_branch mdss_pclk0_clk = {
2000	.halt_reg = 0x2314,
2001	.clkr = {
2002		.enable_reg = 0x2314,
2003		.enable_mask = BIT(0),
2004		.hw.init = &(struct clk_init_data){
2005			.name = "mdss_pclk0_clk",
2006			.parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
2007			.num_parents = 1,
2008			.flags = CLK_SET_RATE_PARENT,
2009			.ops = &clk_branch2_ops,
2010		},
2011	},
2012};
2013
2014static struct clk_branch mdss_pclk1_clk = {
2015	.halt_reg = 0x2318,
2016	.clkr = {
2017		.enable_reg = 0x2318,
2018		.enable_mask = BIT(0),
2019		.hw.init = &(struct clk_init_data){
2020			.name = "mdss_pclk1_clk",
2021			.parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
2022			.num_parents = 1,
2023			.flags = CLK_SET_RATE_PARENT,
2024			.ops = &clk_branch2_ops,
2025		},
2026	},
2027};
2028
2029static struct clk_branch mdss_vsync_clk = {
2030	.halt_reg = 0x2328,
2031	.clkr = {
2032		.enable_reg = 0x2328,
2033		.enable_mask = BIT(0),
2034		.hw.init = &(struct clk_init_data){
2035			.name = "mdss_vsync_clk",
2036			.parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
2037			.num_parents = 1,
2038			.flags = CLK_SET_RATE_PARENT,
2039			.ops = &clk_branch2_ops,
2040		},
2041	},
2042};
2043
2044static struct clk_branch mmss_misc_ahb_clk = {
2045	.halt_reg = 0x502c,
2046	.clkr = {
2047		.enable_reg = 0x502c,
2048		.enable_mask = BIT(0),
2049		.hw.init = &(struct clk_init_data){
2050			.name = "mmss_misc_ahb_clk",
2051			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2052			.num_parents = 1,
2053			.flags = CLK_SET_RATE_PARENT,
2054			.ops = &clk_branch2_ops,
2055		},
2056	},
2057};
2058
2059static struct clk_branch mmss_mmssnoc_axi_clk = {
2060	.halt_reg = 0x506c,
2061	.clkr = {
2062		.enable_reg = 0x506c,
2063		.enable_mask = BIT(0),
2064		.hw.init = &(struct clk_init_data){
2065			.name = "mmss_mmssnoc_axi_clk",
2066			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2067			.num_parents = 1,
2068			/* Gating this clock will wreck havoc among MMSS! */
2069			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2070			.ops = &clk_branch2_ops,
2071		},
2072	},
2073};
2074
2075static struct clk_branch mmss_s0_axi_clk = {
2076	.halt_reg = 0x5064,
2077	.clkr = {
2078		.enable_reg = 0x5064,
2079		.enable_mask = BIT(0),
2080		.hw.init = &(struct clk_init_data){
2081			.name = "mmss_s0_axi_clk",
2082			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw, },
2083			.num_parents = 1,
2084			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2085			.ops = &clk_branch2_ops,
2086		},
2087	},
2088};
2089
2090static struct clk_branch ocmemcx_ocmemnoc_clk = {
2091	.halt_reg = 0x4058,
2092	.clkr = {
2093		.enable_reg = 0x4058,
2094		.enable_mask = BIT(0),
2095		.hw.init = &(struct clk_init_data){
2096			.name = "ocmemcx_ocmemnoc_clk",
2097			.parent_hws = (const struct clk_hw *[]){ &ocmemnoc_clk_src.clkr.hw },
2098			.num_parents = 1,
2099			.flags = CLK_SET_RATE_PARENT,
2100			.ops = &clk_branch2_ops,
2101		},
2102	},
2103};
2104
2105static struct clk_branch oxili_gfx3d_clk = {
2106	.halt_reg = 0x4028,
2107	.clkr = {
2108		.enable_reg = 0x4028,
2109		.enable_mask = BIT(0),
2110		.hw.init = &(struct clk_init_data){
2111			.name = "oxili_gfx3d_clk",
2112			.parent_data = &(const struct clk_parent_data){
2113				.fw_name = "oxili_gfx3d_clk_src",
2114				.name = "oxili_gfx3d_clk_src"
2115			},
2116			.num_parents = 1,
2117			.flags = CLK_SET_RATE_PARENT,
2118			.ops = &clk_branch2_ops,
2119		},
2120	},
2121};
2122
2123static struct clk_branch oxili_rbbmtimer_clk = {
2124	.halt_reg = 0x40b0,
2125	.clkr = {
2126		.enable_reg = 0x40b0,
2127		.enable_mask = BIT(0),
2128		.hw.init = &(struct clk_init_data){
2129			.name = "oxili_rbbmtimer_clk",
2130			.parent_hws = (const struct clk_hw *[]){ &rbbmtimer_clk_src.clkr.hw },
2131			.num_parents = 1,
2132			.flags = CLK_SET_RATE_PARENT,
2133			.ops = &clk_branch2_ops,
2134		},
2135	},
2136};
2137
2138static struct clk_branch oxilicx_ahb_clk = {
2139	.halt_reg = 0x403c,
2140	.clkr = {
2141		.enable_reg = 0x403c,
2142		.enable_mask = BIT(0),
2143		.hw.init = &(struct clk_init_data){
2144			.name = "oxilicx_ahb_clk",
2145			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2146			.num_parents = 1,
2147			.flags = CLK_SET_RATE_PARENT,
2148			.ops = &clk_branch2_ops,
2149		},
2150	},
2151};
2152
2153static struct clk_branch venus0_ahb_clk = {
2154	.halt_reg = 0x1030,
2155	.clkr = {
2156		.enable_reg = 0x1030,
2157		.enable_mask = BIT(0),
2158		.hw.init = &(struct clk_init_data){
2159			.name = "venus0_ahb_clk",
2160			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2161			.num_parents = 1,
2162			.flags = CLK_SET_RATE_PARENT,
2163			.ops = &clk_branch2_ops,
2164		},
2165	},
2166};
2167
2168static struct clk_branch venus0_axi_clk = {
2169	.halt_reg = 0x1034,
2170	.clkr = {
2171		.enable_reg = 0x1034,
2172		.enable_mask = BIT(0),
2173		.hw.init = &(struct clk_init_data){
2174			.name = "venus0_axi_clk",
2175			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2176			.num_parents = 1,
2177			.ops = &clk_branch2_ops,
2178		},
2179	},
2180};
2181
2182static struct clk_branch venus0_ocmemnoc_clk = {
2183	.halt_reg = 0x1038,
2184	.clkr = {
2185		.enable_reg = 0x1038,
2186		.enable_mask = BIT(0),
2187		.hw.init = &(struct clk_init_data){
2188			.name = "venus0_ocmemnoc_clk",
2189			.parent_hws = (const struct clk_hw *[]){ &ocmemnoc_clk_src.clkr.hw },
2190			.num_parents = 1,
2191			.flags = CLK_SET_RATE_PARENT,
2192			.ops = &clk_branch2_ops,
2193		},
2194	},
2195};
2196
2197static struct clk_branch venus0_vcodec0_clk = {
2198	.halt_reg = 0x1028,
2199	.clkr = {
2200		.enable_reg = 0x1028,
2201		.enable_mask = BIT(0),
2202		.hw.init = &(struct clk_init_data){
2203			.name = "venus0_vcodec0_clk",
2204			.parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2205			.num_parents = 1,
2206			.flags = CLK_SET_RATE_PARENT,
2207			.ops = &clk_branch2_ops,
2208		},
2209	},
2210};
2211
2212static struct clk_branch venus0_core0_vcodec_clk = {
2213	.halt_reg = 0x1048,
2214	.clkr = {
2215		.enable_reg = 0x1048,
2216		.enable_mask = BIT(0),
2217		.hw.init = &(struct clk_init_data){
2218			.name = "venus0_core0_vcodec_clk",
2219			.parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2220			.num_parents = 1,
2221			.flags = CLK_SET_RATE_PARENT,
2222			.ops = &clk_branch2_ops,
2223		},
2224	},
2225};
2226
2227static struct clk_branch venus0_core1_vcodec_clk = {
2228	.halt_reg = 0x104c,
2229	.clkr = {
2230		.enable_reg = 0x104c,
2231		.enable_mask = BIT(0),
2232		.hw.init = &(struct clk_init_data){
2233			.name = "venus0_core1_vcodec_clk",
2234			.parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2235			.num_parents = 1,
2236			.flags = CLK_SET_RATE_PARENT,
2237			.ops = &clk_branch2_ops,
2238		},
2239	},
2240};
2241
2242static struct clk_branch venus0_core2_vcodec_clk = {
2243	.halt_reg = 0x1054,
2244	.clkr = {
2245		.enable_reg = 0x1054,
2246		.enable_mask = BIT(0),
2247		.hw.init = &(struct clk_init_data){
2248			.name = "venus0_core2_vcodec_clk",
2249			.parent_hws = (const struct clk_hw *[]){ &vcodec0_clk_src.clkr.hw },
2250			.num_parents = 1,
2251			.flags = CLK_SET_RATE_PARENT,
2252			.ops = &clk_branch2_ops,
2253		},
2254	},
2255};
2256
2257static struct gdsc venus_gdsc = {
2258	.gdscr = 0x1024,
2259	.cxcs = (unsigned int []){ 0x1038, 0x1034, 0x1048 },
2260	.cxc_count = 3,
2261	.pd = {
2262		.name = "venus_gdsc",
2263	},
2264	.pwrsts = PWRSTS_OFF_ON,
2265};
2266
2267static struct gdsc venus_core0_gdsc = {
2268	.gdscr = 0x1040,
2269	.cxcs = (unsigned int []){ 0x1048 },
2270	.cxc_count = 1,
2271	.pd = {
2272		.name = "venus_core0_gdsc",
2273	},
2274	.pwrsts = PWRSTS_OFF_ON,
2275	.flags = HW_CTRL,
2276};
2277
2278static struct gdsc venus_core1_gdsc = {
2279	.gdscr = 0x1044,
2280	.cxcs = (unsigned int []){ 0x104c },
2281	.cxc_count = 1,
2282	.pd = {
2283	.name = "venus_core1_gdsc",
2284	},
2285	.pwrsts = PWRSTS_OFF_ON,
2286	.flags = HW_CTRL,
2287};
2288
2289static struct gdsc venus_core2_gdsc = {
2290	.gdscr = 0x1050,
2291	.cxcs = (unsigned int []){ 0x1054 },
2292	.cxc_count = 1,
2293	.pd = {
2294		.name = "venus_core2_gdsc",
2295	},
2296	.pwrsts = PWRSTS_OFF_ON,
2297	.flags = HW_CTRL,
2298};
2299
2300static struct gdsc mdss_gdsc = {
2301	.gdscr = 0x2304,
2302	.cxcs = (unsigned int []){ 0x2310, 0x231c },
2303	.cxc_count = 2,
2304	.pd = {
2305		.name = "mdss_gdsc",
2306	},
2307	.pwrsts = PWRSTS_OFF_ON,
2308};
2309
2310static struct gdsc camss_top_gdsc = {
2311	.gdscr = 0x34a0,
2312	.cxcs = (unsigned int []){ 0x3704, 0x3714, 0x3494 },
2313	.cxc_count = 3,
2314	.pd = {
2315		.name = "camss_top_gdsc",
2316	},
2317	.pwrsts = PWRSTS_OFF_ON,
2318};
2319
2320static struct gdsc jpeg_gdsc = {
2321	.gdscr = 0x35a4,
2322	.cxcs = (unsigned int []){ 0x35a8 },
2323	.cxc_count = 1,
2324	.pd = {
2325		.name = "jpeg_gdsc",
2326	},
2327	.parent = &camss_top_gdsc.pd,
2328	.pwrsts = PWRSTS_OFF_ON,
2329};
2330
2331static struct gdsc vfe_gdsc = {
2332	.gdscr = 0x36a4,
2333	.cxcs = (unsigned int []){ 0x36bc },
2334	.cxc_count = 1,
2335	.pd = {
2336		.name = "vfe_gdsc",
2337	},
2338	.parent = &camss_top_gdsc.pd,
2339	.pwrsts = PWRSTS_OFF_ON,
2340};
2341
2342static struct gdsc cpp_gdsc = {
2343	.gdscr = 0x36d4,
2344	.cxcs = (unsigned int []){ 0x36c4, 0x36b0 },
2345	.cxc_count = 2,
2346	.pd = {
2347		.name = "cpp_gdsc",
2348	},
2349	.parent = &camss_top_gdsc.pd,
2350	.pwrsts = PWRSTS_OFF_ON,
2351};
2352
2353static struct gdsc fd_gdsc = {
2354	.gdscr = 0x3b64,
2355	.cxcs = (unsigned int []){ 0x3b70, 0x3b68 },
2356	.pd = {
2357		.name = "fd_gdsc",
2358	},
2359	.pwrsts = PWRSTS_OFF_ON,
2360};
2361
2362static struct gdsc oxili_cx_gdsc = {
2363	.gdscr = 0x4034,
2364	.pd = {
2365		.name = "oxili_cx_gdsc",
2366	},
2367	.pwrsts = PWRSTS_OFF_ON,
2368	.flags = VOTABLE,
2369};
2370
2371static struct gdsc oxili_gx_gdsc = {
2372	.gdscr = 0x4024,
2373	.cxcs = (unsigned int []){ 0x4028 },
2374	.cxc_count = 1,
2375	.pd = {
2376		.name = "oxili_gx_gdsc",
2377	},
2378	.pwrsts = PWRSTS_OFF_ON,
2379	.parent = &oxili_cx_gdsc.pd,
2380	.flags = CLAMP_IO,
2381	.supply = "VDD_GFX",
2382};
2383
2384static struct clk_regmap *mmcc_msm8994_clocks[] = {
2385	[MMPLL0_EARLY] = &mmpll0_early.clkr,
2386	[MMPLL0_PLL] = &mmpll0.clkr,
2387	[MMPLL1_EARLY] = &mmpll1_early.clkr,
2388	[MMPLL1_PLL] = &mmpll1.clkr,
2389	[MMPLL3_EARLY] = &mmpll3_early.clkr,
2390	[MMPLL3_PLL] = &mmpll3.clkr,
2391	[MMPLL4_EARLY] = &mmpll4_early.clkr,
2392	[MMPLL4_PLL] = &mmpll4.clkr,
2393	[MMPLL5_EARLY] = &mmpll5_early.clkr,
2394	[MMPLL5_PLL] = &mmpll5.clkr,
2395	[AHB_CLK_SRC] = &ahb_clk_src.clkr,
2396	[AXI_CLK_SRC] = &axi_clk_src.clkr,
2397	[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2398	[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2399	[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2400	[CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2401	[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2402	[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2403	[CPP_CLK_SRC] = &cpp_clk_src.clkr,
2404	[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2405	[JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2406	[JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2407	[CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2408	[FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2409	[MDP_CLK_SRC] = &mdp_clk_src.clkr,
2410	[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2411	[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2412	[OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2413	[CCI_CLK_SRC] = &cci_clk_src.clkr,
2414	[MMSS_GP0_CLK_SRC] = &mmss_gp0_clk_src.clkr,
2415	[MMSS_GP1_CLK_SRC] = &mmss_gp1_clk_src.clkr,
2416	[JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
2417	[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2418	[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2419	[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2420	[MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2421	[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2422	[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2423	[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2424	[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2425	[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2426	[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2427	[MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2428	[MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2429	[EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2430	[HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2431	[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2432	[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
2433	[CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2434	[CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2435	[CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2436	[CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2437	[CAMSS_VFE_CPP_AXI_CLK] = &camss_vfe_cpp_axi_clk.clkr,
2438	[CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2439	[CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2440	[CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2441	[CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2442	[CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2443	[CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2444	[CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2445	[CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2446	[CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2447	[CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2448	[CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2449	[CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2450	[CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2451	[CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2452	[CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2453	[CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2454	[CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2455	[CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2456	[CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2457	[CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2458	[CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2459	[CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2460	[CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2461	[CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2462	[CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2463	[CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2464	[CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
2465	[CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2466	[CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2467	[CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2468	[CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2469	[CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2470	[CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2471	[CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2472	[CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2473	[CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2474	[CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2475	[CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2476	[CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2477	[CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2478	[CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2479	[CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2480	[CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2481	[CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2482	[CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2483	[FD_AHB_CLK] = &fd_ahb_clk.clkr,
2484	[FD_AXI_CLK] = &fd_axi_clk.clkr,
2485	[FD_CORE_CLK] = &fd_core_clk.clkr,
2486	[FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
2487	[MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2488	[MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2489	[MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2490	[MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2491	[MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2492	[MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2493	[MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2494	[MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2495	[MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2496	[MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2497	[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2498	[MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2499	[MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2500	[MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2501	[OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2502	[OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2503	[OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
2504	[OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2505	[VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2506	[VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2507	[VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2508	[VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2509	[VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
2510	[VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
2511	[VENUS0_CORE2_VCODEC_CLK] = &venus0_core2_vcodec_clk.clkr,
2512};
2513
2514static struct gdsc *mmcc_msm8994_gdscs[] = {
2515	[VENUS_GDSC] = &venus_gdsc,
2516	[VENUS_CORE0_GDSC] = &venus_core0_gdsc,
2517	[VENUS_CORE1_GDSC] = &venus_core1_gdsc,
2518	[VENUS_CORE2_GDSC] = &venus_core2_gdsc,
2519	[CAMSS_TOP_GDSC] = &camss_top_gdsc,
2520	[MDSS_GDSC] = &mdss_gdsc,
2521	[JPEG_GDSC] = &jpeg_gdsc,
2522	[VFE_GDSC] = &vfe_gdsc,
2523	[CPP_GDSC] = &cpp_gdsc,
2524	[OXILI_GX_GDSC] = &oxili_gx_gdsc,
2525	[OXILI_CX_GDSC] = &oxili_cx_gdsc,
2526	[FD_GDSC] = &fd_gdsc,
2527};
2528
2529static const struct qcom_reset_map mmcc_msm8994_resets[] = {
2530	[CAMSS_MICRO_BCR] = { 0x3490 },
2531};
2532
2533static const struct regmap_config mmcc_msm8994_regmap_config = {
2534	.reg_bits	= 32,
2535	.reg_stride	= 4,
2536	.val_bits	= 32,
2537	.max_register	= 0x5200,
2538	.fast_io	= true,
2539};
2540
2541static const struct qcom_cc_desc mmcc_msm8994_desc = {
2542	.config = &mmcc_msm8994_regmap_config,
2543	.clks = mmcc_msm8994_clocks,
2544	.num_clks = ARRAY_SIZE(mmcc_msm8994_clocks),
2545	.resets = mmcc_msm8994_resets,
2546	.num_resets = ARRAY_SIZE(mmcc_msm8994_resets),
2547	.gdscs = mmcc_msm8994_gdscs,
2548	.num_gdscs = ARRAY_SIZE(mmcc_msm8994_gdscs),
2549};
2550
2551static const struct of_device_id mmcc_msm8994_match_table[] = {
2552	{ .compatible = "qcom,mmcc-msm8992" },
2553	{ .compatible = "qcom,mmcc-msm8994" }, /* V2 and V2.1 */
2554	{ }
2555};
2556MODULE_DEVICE_TABLE(of, mmcc_msm8994_match_table);
2557
2558static int mmcc_msm8994_probe(struct platform_device *pdev)
2559{
2560	struct regmap *regmap;
2561
2562	if (of_device_is_compatible(pdev->dev.of_node, "qcom,mmcc-msm8992")) {
2563		/* MSM8992 features less clocks and some have different freq tables */
2564		mmcc_msm8994_desc.clks[CAMSS_JPEG_JPEG1_CLK] = NULL;
2565		mmcc_msm8994_desc.clks[CAMSS_JPEG_JPEG2_CLK] = NULL;
2566		mmcc_msm8994_desc.clks[FD_CORE_CLK_SRC] = NULL;
2567		mmcc_msm8994_desc.clks[FD_CORE_CLK] = NULL;
2568		mmcc_msm8994_desc.clks[FD_CORE_UAR_CLK] = NULL;
2569		mmcc_msm8994_desc.clks[FD_AXI_CLK] = NULL;
2570		mmcc_msm8994_desc.clks[FD_AHB_CLK] = NULL;
2571		mmcc_msm8994_desc.clks[JPEG1_CLK_SRC] = NULL;
2572		mmcc_msm8994_desc.clks[JPEG2_CLK_SRC] = NULL;
2573		mmcc_msm8994_desc.clks[VENUS0_CORE2_VCODEC_CLK] = NULL;
2574
2575		mmcc_msm8994_desc.gdscs[FD_GDSC] = NULL;
2576		mmcc_msm8994_desc.gdscs[VENUS_CORE2_GDSC] = NULL;
2577
2578		axi_clk_src.freq_tbl = ftbl_axi_clk_src_8992;
2579		cpp_clk_src.freq_tbl = ftbl_cpp_clk_src_8992;
2580		csi0_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2581		csi1_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2582		csi2_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2583		csi3_clk_src.freq_tbl = ftbl_csi0_1_2_3_clk_src_8992;
2584		mclk0_clk_src.freq_tbl = ftbl_mclk0_clk_src_8992;
2585		mclk1_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2586		mclk2_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2587		mclk3_clk_src.freq_tbl = ftbl_mclk1_2_3_clk_src_8992;
2588		mdp_clk_src.freq_tbl = ftbl_mdp_clk_src_8992;
2589		ocmemnoc_clk_src.freq_tbl = ftbl_ocmemnoc_clk_src_8992;
2590		vcodec0_clk_src.freq_tbl = ftbl_vcodec0_clk_src_8992;
2591		vfe0_clk_src.freq_tbl = ftbl_vfe0_1_clk_src_8992;
2592		vfe1_clk_src.freq_tbl = ftbl_vfe0_1_clk_src_8992;
2593	}
2594
2595	regmap = qcom_cc_map(pdev, &mmcc_msm8994_desc);
2596	if (IS_ERR(regmap))
2597		return PTR_ERR(regmap);
2598
2599	clk_alpha_pll_configure(&mmpll0_early, regmap, &mmpll_p_config);
2600	clk_alpha_pll_configure(&mmpll1_early, regmap, &mmpll_p_config);
2601	clk_alpha_pll_configure(&mmpll3_early, regmap, &mmpll_p_config);
2602	clk_alpha_pll_configure(&mmpll5_early, regmap, &mmpll_p_config);
2603
2604	return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8994_desc, regmap);
2605}
2606
2607static struct platform_driver mmcc_msm8994_driver = {
2608	.probe		= mmcc_msm8994_probe,
2609	.driver		= {
2610		.name	= "mmcc-msm8994",
2611		.of_match_table = mmcc_msm8994_match_table,
2612	},
2613};
2614module_platform_driver(mmcc_msm8994_driver);
2615
2616MODULE_DESCRIPTION("QCOM MMCC MSM8994 Driver");
2617MODULE_LICENSE("GPL v2");
2618MODULE_ALIAS("platform:mmcc-msm8994");