gpucc-sm8350.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
  4 * Copyright (c) 2022, Linaro Limited
  5 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  6 */
  7
  8#include <linux/clk.h>
  9#include <linux/err.h>
 10#include <linux/kernel.h>
 11#include <linux/mod_devicetable.h>
 12#include <linux/module.h>
 13#include <linux/platform_device.h>
 14#include <linux/regmap.h>
 15
 16#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
 17
 18#include "clk-alpha-pll.h"
 19#include "clk-branch.h"
 20#include "clk-pll.h"
 21#include "clk-rcg.h"
 22#include "clk-regmap.h"
 23#include "common.h"
 24#include "clk-regmap-mux.h"
 25#include "clk-regmap-divider.h"
 26#include "gdsc.h"
 27#include "reset.h"
 28
 29enum {
 30	P_BI_TCXO,
 31	P_GPLL0_OUT_MAIN,
 32	P_GPLL0_OUT_MAIN_DIV,
 33	P_GPU_CC_PLL0_OUT_MAIN,
 34	P_GPU_CC_PLL1_OUT_MAIN,
 35};
 36
 37static const struct pll_vco lucid_5lpe_vco[] = {
 38	{ 249600000, 1750000000, 0 },
 39};
 40
 41static const struct alpha_pll_config gpu_cc_pll0_config = {
 42	.l = 0x18,
 43	.alpha = 0x6000,
 44	.config_ctl_val = 0x20485699,
 45	.config_ctl_hi_val = 0x00002261,
 46	.config_ctl_hi1_val = 0x2a9a699c,
 47	.test_ctl_val = 0x00000000,
 48	.test_ctl_hi_val = 0x00000000,
 49	.test_ctl_hi1_val = 0x01800000,
 50	.user_ctl_val = 0x00000000,
 51	.user_ctl_hi_val = 0x00000805,
 52	.user_ctl_hi1_val = 0x00000000,
 53};
 54
 55static const struct clk_parent_data gpu_cc_parent = {
 56	.fw_name = "bi_tcxo",
 57};
 58
 59static struct clk_alpha_pll gpu_cc_pll0 = {
 60	.offset = 0x0,
 61	.vco_table = lucid_5lpe_vco,
 62	.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
 63	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 64	.clkr = {
 65		.hw.init = &(const struct clk_init_data){
 66			.name = "gpu_cc_pll0",
 67			.parent_data = &gpu_cc_parent,
 68			.num_parents = 1,
 69			.ops = &clk_alpha_pll_lucid_5lpe_ops,
 70		},
 71	},
 72};
 73
 74static const struct alpha_pll_config gpu_cc_pll1_config = {
 75	.l = 0x1a,
 76	.alpha = 0xaaa,
 77	.config_ctl_val = 0x20485699,
 78	.config_ctl_hi_val = 0x00002261,
 79	.config_ctl_hi1_val = 0x2a9a699c,
 80	.test_ctl_val = 0x00000000,
 81	.test_ctl_hi_val = 0x00000000,
 82	.test_ctl_hi1_val = 0x01800000,
 83	.user_ctl_val = 0x00000000,
 84	.user_ctl_hi_val = 0x00000805,
 85	.user_ctl_hi1_val = 0x00000000,
 86};
 87
 88static struct clk_alpha_pll gpu_cc_pll1 = {
 89	.offset = 0x100,
 90	.vco_table = lucid_5lpe_vco,
 91	.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
 92	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 93	.clkr = {
 94		.hw.init = &(struct clk_init_data){
 95			.name = "gpu_cc_pll1",
 96			.parent_data = &gpu_cc_parent,
 97			.num_parents = 1,
 98			.ops = &clk_alpha_pll_lucid_5lpe_ops,
 99		},
100	},
101};
102
103static const struct parent_map gpu_cc_parent_map_0[] = {
104	{ P_BI_TCXO, 0 },
105	{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
106	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
107	{ P_GPLL0_OUT_MAIN, 5 },
108	{ P_GPLL0_OUT_MAIN_DIV, 6 },
109};
110
111static const struct clk_parent_data gpu_cc_parent_data_0[] = {
112	{ .fw_name = "bi_tcxo" },
113	{ .hw = &gpu_cc_pll0.clkr.hw },
114	{ .hw = &gpu_cc_pll1.clkr.hw },
115	{ .fw_name = "gcc_gpu_gpll0_clk_src" },
116	{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
117};
118
119static const struct parent_map gpu_cc_parent_map_1[] = {
120	{ P_BI_TCXO, 0 },
121	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
122	{ P_GPLL0_OUT_MAIN, 5 },
123	{ P_GPLL0_OUT_MAIN_DIV, 6 },
124};
125
126static const struct clk_parent_data gpu_cc_parent_data_1[] = {
127	{ .fw_name = "bi_tcxo" },
128	{ .hw = &gpu_cc_pll1.clkr.hw },
129	{ .fw_name = "gcc_gpu_gpll0_clk_src" },
130	{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
131};
132
133static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
134	F(19200000, P_BI_TCXO, 1, 0, 0),
135	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
136	F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
137	{ }
138};
139
140static struct clk_rcg2 gpu_cc_gmu_clk_src = {
141	.cmd_rcgr = 0x1120,
142	.mnd_width = 0,
143	.hid_width = 5,
144	.parent_map = gpu_cc_parent_map_0,
145	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
146	.clkr.hw.init = &(struct clk_init_data){
147		.name = "gpu_cc_gmu_clk_src",
148		.parent_data = gpu_cc_parent_data_0,
149		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
150		.flags = CLK_SET_RATE_PARENT,
151		.ops = &clk_rcg2_shared_ops,
152	},
153};
154
155static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
156	F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
157	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
158	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
159	{ }
160};
161
162static struct clk_rcg2 gpu_cc_hub_clk_src = {
163	.cmd_rcgr = 0x117c,
164	.mnd_width = 0,
165	.hid_width = 5,
166	.parent_map = gpu_cc_parent_map_1,
167	.freq_tbl = ftbl_gpu_cc_hub_clk_src,
168	.clkr.hw.init = &(struct clk_init_data){
169		.name = "gpu_cc_hub_clk_src",
170		.parent_data = gpu_cc_parent_data_1,
171		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
172		.flags = CLK_SET_RATE_PARENT,
173		.ops = &clk_rcg2_shared_ops,
174	},
175};
176
177static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
178	.reg = 0x11c0,
179	.shift = 0,
180	.width = 4,
181	.clkr.hw.init = &(struct clk_init_data) {
182		.name = "gpu_cc_hub_ahb_div_clk_src",
183		.parent_hws = (const struct clk_hw*[]){
184			&gpu_cc_hub_clk_src.clkr.hw,
185		},
186		.num_parents = 1,
187		.flags = CLK_SET_RATE_PARENT,
188		.ops = &clk_regmap_div_ro_ops,
189	},
190};
191
192static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
193	.reg = 0x11bc,
194	.shift = 0,
195	.width = 4,
196	.clkr.hw.init = &(struct clk_init_data) {
197		.name = "gpu_cc_hub_cx_int_div_clk_src",
198		.parent_hws = (const struct clk_hw*[]){
199			&gpu_cc_hub_clk_src.clkr.hw,
200		},
201		.num_parents = 1,
202		.flags = CLK_SET_RATE_PARENT,
203		.ops = &clk_regmap_div_ro_ops,
204	},
205};
206
207static struct clk_branch gpu_cc_ahb_clk = {
208	.halt_reg = 0x1078,
209	.halt_check = BRANCH_HALT_DELAY,
210	.clkr = {
211		.enable_reg = 0x1078,
212		.enable_mask = BIT(0),
213		.hw.init = &(struct clk_init_data){
214			.name = "gpu_cc_ahb_clk",
215			.parent_hws = (const struct clk_hw*[]){
216				&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
217			},
218			.num_parents = 1,
219			.flags = CLK_SET_RATE_PARENT,
220			.ops = &clk_branch2_ops,
221		},
222	},
223};
224
225static struct clk_branch gpu_cc_cb_clk = {
226	.halt_reg = 0x1170,
227	.halt_check = BRANCH_HALT,
228	.clkr = {
229		.enable_reg = 0x1170,
230		.enable_mask = BIT(0),
231		.hw.init = &(struct clk_init_data){
232			.name = "gpu_cc_cb_clk",
233			.ops = &clk_branch2_ops,
234		},
235	},
236};
237
238static struct clk_branch gpu_cc_crc_ahb_clk = {
239	.halt_reg = 0x107c,
240	.halt_check = BRANCH_HALT_VOTED,
241	.clkr = {
242		.enable_reg = 0x107c,
243		.enable_mask = BIT(0),
244		.hw.init = &(struct clk_init_data){
245			.name = "gpu_cc_crc_ahb_clk",
246			.parent_hws = (const struct clk_hw*[]){
247				&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
248			},
249			.num_parents = 1,
250			.flags = CLK_SET_RATE_PARENT,
251			.ops = &clk_branch2_ops,
252		},
253	},
254};
255
256static struct clk_branch gpu_cc_cx_apb_clk = {
257	.halt_reg = 0x1088,
258	.halt_check = BRANCH_HALT_VOTED,
259	.clkr = {
260		.enable_reg = 0x1088,
261		.enable_mask = BIT(0),
262		.hw.init = &(struct clk_init_data){
263			.name = "gpu_cc_cx_apb_clk",
264			.ops = &clk_branch2_ops,
265		},
266	},
267};
268
269static struct clk_branch gpu_cc_cx_gmu_clk = {
270	.halt_reg = 0x1098,
271	.halt_check = BRANCH_HALT,
272	.clkr = {
273		.enable_reg = 0x1098,
274		.enable_mask = BIT(0),
275		.hw.init = &(struct clk_init_data){
276			.name = "gpu_cc_cx_gmu_clk",
277			.parent_hws = (const struct clk_hw*[]){
278				&gpu_cc_gmu_clk_src.clkr.hw,
279			},
280			.num_parents = 1,
281			.flags = CLK_SET_RATE_PARENT,
282			.ops = &clk_branch2_aon_ops,
283		},
284	},
285};
286
287static struct clk_branch gpu_cc_cx_qdss_at_clk = {
288	.halt_reg = 0x1080,
289	.halt_check = BRANCH_HALT_VOTED,
290	.clkr = {
291		.enable_reg = 0x1080,
292		.enable_mask = BIT(0),
293		.hw.init = &(struct clk_init_data){
294			.name = "gpu_cc_cx_qdss_at_clk",
295			.ops = &clk_branch2_ops,
296		},
297	},
298};
299
300static struct clk_branch gpu_cc_cx_qdss_trig_clk = {
301	.halt_reg = 0x1094,
302	.halt_check = BRANCH_HALT_VOTED,
303	.clkr = {
304		.enable_reg = 0x1094,
305		.enable_mask = BIT(0),
306		.hw.init = &(struct clk_init_data){
307			.name = "gpu_cc_cx_qdss_trig_clk",
308			.ops = &clk_branch2_ops,
309		},
310	},
311};
312
313static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = {
314	.halt_reg = 0x1084,
315	.halt_check = BRANCH_HALT_VOTED,
316	.clkr = {
317		.enable_reg = 0x1084,
318		.enable_mask = BIT(0),
319		.hw.init = &(struct clk_init_data){
320			.name = "gpu_cc_cx_qdss_tsctr_clk",
321			.ops = &clk_branch2_ops,
322		},
323	},
324};
325
326static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
327	.halt_reg = 0x108c,
328	.halt_check = BRANCH_HALT_VOTED,
329	.clkr = {
330		.enable_reg = 0x108c,
331		.enable_mask = BIT(0),
332		.hw.init = &(struct clk_init_data){
333			.name = "gpu_cc_cx_snoc_dvm_clk",
334			.ops = &clk_branch2_ops,
335		},
336	},
337};
338
339static struct clk_branch gpu_cc_cxo_aon_clk = {
340	.halt_reg = 0x1004,
341	.halt_check = BRANCH_HALT_VOTED,
342	.clkr = {
343		.enable_reg = 0x1004,
344		.enable_mask = BIT(0),
345		.hw.init = &(struct clk_init_data){
346			.name = "gpu_cc_cxo_aon_clk",
347			.ops = &clk_branch2_ops,
348		},
349	},
350};
351
352static struct clk_branch gpu_cc_cxo_clk = {
353	.halt_reg = 0x109c,
354	.halt_check = BRANCH_HALT,
355	.clkr = {
356		.enable_reg = 0x109c,
357		.enable_mask = BIT(0),
358		.hw.init = &(struct clk_init_data){
359			.name = "gpu_cc_cxo_clk",
360			.ops = &clk_branch2_ops,
361		},
362	},
363};
364
365static struct clk_branch gpu_cc_freq_measure_clk = {
366	.halt_reg = 0x120c,
367	.halt_check = BRANCH_HALT,
368	.clkr = {
369		.enable_reg = 0x120c,
370		.enable_mask = BIT(0),
371		.hw.init = &(struct clk_init_data){
372			.name = "gpu_cc_freq_measure_clk",
373			.ops = &clk_branch2_ops,
374		},
375	},
376};
377
378static struct clk_branch gpu_cc_gx_gmu_clk = {
379	.halt_reg = 0x1064,
380	.halt_check = BRANCH_HALT,
381	.clkr = {
382		.enable_reg = 0x1064,
383		.enable_mask = BIT(0),
384		.hw.init = &(struct clk_init_data){
385			.name = "gpu_cc_gx_gmu_clk",
386			.parent_hws = (const struct clk_hw*[]){
387				&gpu_cc_gmu_clk_src.clkr.hw,
388			},
389			.num_parents = 1,
390			.flags = CLK_SET_RATE_PARENT,
391			.ops = &clk_branch2_ops,
392		},
393	},
394};
395
396static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = {
397	.halt_reg = 0x105c,
398	.halt_check = BRANCH_HALT_VOTED,
399	.clkr = {
400		.enable_reg = 0x105c,
401		.enable_mask = BIT(0),
402		.hw.init = &(struct clk_init_data){
403			.name = "gpu_cc_gx_qdss_tsctr_clk",
404			.ops = &clk_branch2_ops,
405		},
406	},
407};
408
409static struct clk_branch gpu_cc_gx_vsense_clk = {
410	.halt_reg = 0x1058,
411	.halt_check = BRANCH_HALT_VOTED,
412	.clkr = {
413		.enable_reg = 0x1058,
414		.enable_mask = BIT(0),
415		.hw.init = &(struct clk_init_data){
416			.name = "gpu_cc_gx_vsense_clk",
417			.ops = &clk_branch2_ops,
418		},
419	},
420};
421
422static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
423	.halt_reg = 0x5000,
424	.halt_check = BRANCH_HALT_VOTED,
425	.clkr = {
426		.enable_reg = 0x5000,
427		.enable_mask = BIT(0),
428		.hw.init = &(struct clk_init_data){
429			.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
430			.ops = &clk_branch2_ops,
431		},
432	},
433};
434
435static struct clk_branch gpu_cc_hub_aon_clk = {
436	.halt_reg = 0x1178,
437	.halt_check = BRANCH_HALT,
438	.clkr = {
439		.enable_reg = 0x1178,
440		.enable_mask = BIT(0),
441		.hw.init = &(struct clk_init_data){
442			.name = "gpu_cc_hub_aon_clk",
443			.parent_hws = (const struct clk_hw*[]){
444				&gpu_cc_hub_clk_src.clkr.hw,
445			},
446			.num_parents = 1,
447			.flags = CLK_SET_RATE_PARENT,
448			.ops = &clk_branch2_aon_ops,
449		},
450	},
451};
452
453static struct clk_branch gpu_cc_hub_cx_int_clk = {
454	.halt_reg = 0x1204,
455	.halt_check = BRANCH_HALT,
456	.clkr = {
457		.enable_reg = 0x1204,
458		.enable_mask = BIT(0),
459		.hw.init = &(struct clk_init_data){
460			.name = "gpu_cc_hub_cx_int_clk",
461			.parent_hws = (const struct clk_hw*[]){
462				&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
463			},
464			.num_parents = 1,
465			.flags = CLK_SET_RATE_PARENT,
466			.ops = &clk_branch2_aon_ops,
467		},
468	},
469};
470
471static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
472	.halt_reg = 0x802c,
473	.halt_check = BRANCH_HALT,
474	.clkr = {
475		.enable_reg = 0x802c,
476		.enable_mask = BIT(0),
477		.hw.init = &(struct clk_init_data){
478			.name = "gpu_cc_mnd1x_0_gfx3d_clk",
479			.ops = &clk_branch2_ops,
480		},
481	},
482};
483
484static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
485	.halt_reg = 0x8030,
486	.halt_check = BRANCH_HALT,
487	.clkr = {
488		.enable_reg = 0x8030,
489		.enable_mask = BIT(0),
490		.hw.init = &(struct clk_init_data){
491			.name = "gpu_cc_mnd1x_1_gfx3d_clk",
492			.ops = &clk_branch2_ops,
493		},
494	},
495};
496
497static struct clk_branch gpu_cc_sleep_clk = {
498	.halt_reg = 0x1090,
499	.halt_check = BRANCH_HALT_VOTED,
500	.clkr = {
501		.enable_reg = 0x1090,
502		.enable_mask = BIT(0),
503		.hw.init = &(struct clk_init_data){
504			.name = "gpu_cc_sleep_clk",
505			.ops = &clk_branch2_ops,
506		},
507	},
508};
509
510static struct gdsc gpu_cx_gdsc = {
511	.gdscr = 0x106c,
512	.gds_hw_ctrl = 0x1540,
513	.pd = {
514		.name = "gpu_cx_gdsc",
515	},
516	.pwrsts = PWRSTS_OFF_ON,
517	.flags = VOTABLE,
518};
519
520static struct gdsc gpu_gx_gdsc = {
521	.gdscr = 0x100c,
522	.clamp_io_ctrl = 0x1508,
523	.pd = {
524		.name = "gpu_gx_gdsc",
525		.power_on = gdsc_gx_do_nothing_enable,
526	},
527	.pwrsts = PWRSTS_OFF_ON,
528	.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
529};
530
531static struct clk_regmap *gpu_cc_sm8350_clocks[] = {
532	[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
533	[GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr,
534	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
535	[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
536	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
537	[GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr,
538	[GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr,
539	[GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr,
540	[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
541	[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
542	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
543	[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
544	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
545	[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
546	[GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr,
547	[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
548	[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
549	[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
550	[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
551	[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
552	[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
553	[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
554	[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
555	[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
556	[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
557	[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
558	[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
559};
560
561static const struct qcom_reset_map gpu_cc_sm8350_resets[] = {
562	[GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
563	[GPUCC_GPU_CC_CB_BCR] = { 0x116c },
564	[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
565	[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 },
566	[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
567	[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
568	[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
569	[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
570};
571
572static struct gdsc *gpu_cc_sm8350_gdscs[] = {
573	[GPU_CX_GDSC] = &gpu_cx_gdsc,
574	[GPU_GX_GDSC] = &gpu_gx_gdsc,
575};
576
577static const struct regmap_config gpu_cc_sm8350_regmap_config = {
578	.reg_bits = 32,
579	.reg_stride = 4,
580	.val_bits = 32,
581	.max_register = 0x8030,
582	.fast_io = true,
583};
584
585static const struct qcom_cc_desc gpu_cc_sm8350_desc = {
586	.config = &gpu_cc_sm8350_regmap_config,
587	.clks = gpu_cc_sm8350_clocks,
588	.num_clks = ARRAY_SIZE(gpu_cc_sm8350_clocks),
589	.resets = gpu_cc_sm8350_resets,
590	.num_resets = ARRAY_SIZE(gpu_cc_sm8350_resets),
591	.gdscs = gpu_cc_sm8350_gdscs,
592	.num_gdscs = ARRAY_SIZE(gpu_cc_sm8350_gdscs),
593};
594
595static int gpu_cc_sm8350_probe(struct platform_device *pdev)
596{
597	struct regmap *regmap;
598
599	regmap = qcom_cc_map(pdev, &gpu_cc_sm8350_desc);
600	if (IS_ERR(regmap)) {
601		dev_err(&pdev->dev, "Failed to map gpu cc registers\n");
602		return PTR_ERR(regmap);
603	}
604
605	clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
606	clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
607
608	return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8350_desc, regmap);
609}
610
611static const struct of_device_id gpu_cc_sm8350_match_table[] = {
612	{ .compatible = "qcom,sm8350-gpucc" },
613	{ }
614};
615MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table);
616
617static struct platform_driver gpu_cc_sm8350_driver = {
618	.probe = gpu_cc_sm8350_probe,
619	.driver = {
620		.name = "sm8350-gpucc",
621		.of_match_table = gpu_cc_sm8350_match_table,
622	},
623};
624
625module_platform_driver(gpu_cc_sm8350_driver);
626
627MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver");
628MODULE_LICENSE("GPL v2");