gpucc-sdm845.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  4 */
  5
  6#include <linux/clk-provider.h>
  7#include <linux/mod_devicetable.h>
  8#include <linux/module.h>
  9#include <linux/platform_device.h>
 10#include <linux/regmap.h>
 11
 12#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
 13
 14#include "common.h"
 15#include "clk-alpha-pll.h"
 16#include "clk-branch.h"
 17#include "clk-pll.h"
 18#include "clk-rcg.h"
 19#include "clk-regmap.h"
 20#include "gdsc.h"
 21
 22#define CX_GMU_CBCR_SLEEP_MASK		0xf
 23#define CX_GMU_CBCR_SLEEP_SHIFT		4
 24#define CX_GMU_CBCR_WAKE_MASK		0xf
 25#define CX_GMU_CBCR_WAKE_SHIFT		8
 26
 27enum {
 28	P_BI_TCXO,
 29	P_GPLL0_OUT_MAIN,
 30	P_GPLL0_OUT_MAIN_DIV,
 31	P_GPU_CC_PLL1_OUT_MAIN,
 32};
 33
 34static const struct alpha_pll_config gpu_cc_pll1_config = {
 35	.l = 0x1a,
 36	.alpha = 0xaab,
 37};
 38
 39static struct clk_alpha_pll gpu_cc_pll1 = {
 40	.offset = 0x100,
 41	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 42	.clkr = {
 43		.hw.init = &(struct clk_init_data){
 44			.name = "gpu_cc_pll1",
 45			.parent_data = &(const struct clk_parent_data){
 46				.fw_name = "bi_tcxo", .name = "bi_tcxo",
 47			},
 48			.num_parents = 1,
 49			.ops = &clk_alpha_pll_fabia_ops,
 50		},
 51	},
 52};
 53
 54static const struct parent_map gpu_cc_parent_map_0[] = {
 55	{ P_BI_TCXO, 0 },
 56	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
 57	{ P_GPLL0_OUT_MAIN, 5 },
 58	{ P_GPLL0_OUT_MAIN_DIV, 6 },
 59};
 60
 61static const struct clk_parent_data gpu_cc_parent_data_0[] = {
 62	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 63	{ .hw = &gpu_cc_pll1.clkr.hw },
 64	{ .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" },
 65	{ .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" },
 66};
 67
 68static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
 69	F(19200000, P_BI_TCXO, 1, 0, 0),
 70	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
 71	F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
 72	{ }
 73};
 74
 75static struct clk_rcg2 gpu_cc_gmu_clk_src = {
 76	.cmd_rcgr = 0x1120,
 77	.mnd_width = 0,
 78	.hid_width = 5,
 79	.parent_map = gpu_cc_parent_map_0,
 80	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
 81	.clkr.hw.init = &(struct clk_init_data){
 82		.name = "gpu_cc_gmu_clk_src",
 83		.parent_data = gpu_cc_parent_data_0,
 84		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
 85		.ops = &clk_rcg2_shared_ops,
 86	},
 87};
 88
 89static struct clk_branch gpu_cc_cx_gmu_clk = {
 90	.halt_reg = 0x1098,
 91	.halt_check = BRANCH_HALT,
 92	.clkr = {
 93		.enable_reg = 0x1098,
 94		.enable_mask = BIT(0),
 95		.hw.init = &(struct clk_init_data){
 96			.name = "gpu_cc_cx_gmu_clk",
 97			.parent_hws = (const struct clk_hw*[]){
 98				&gpu_cc_gmu_clk_src.clkr.hw,
 99			},
100			.num_parents = 1,
101			.flags = CLK_SET_RATE_PARENT,
102			.ops = &clk_branch2_ops,
103		},
104	},
105};
106
107static struct clk_branch gpu_cc_cxo_clk = {
108	.halt_reg = 0x109c,
109	.halt_check = BRANCH_HALT,
110	.clkr = {
111		.enable_reg = 0x109c,
112		.enable_mask = BIT(0),
113		.hw.init = &(struct clk_init_data){
114			.name = "gpu_cc_cxo_clk",
115			.ops = &clk_branch2_ops,
116		},
117	},
118};
119
120static struct gdsc gpu_cx_gdsc = {
121	.gdscr = 0x106c,
122	.gds_hw_ctrl = 0x1540,
123	.clk_dis_wait_val = 0x8,
124	.pd = {
125		.name = "gpu_cx_gdsc",
126	},
127	.pwrsts = PWRSTS_OFF_ON,
128	.flags = VOTABLE,
129};
130
131static struct gdsc gpu_gx_gdsc = {
132	.gdscr = 0x100c,
133	.clamp_io_ctrl = 0x1508,
134	.pd = {
135		.name = "gpu_gx_gdsc",
136		.power_on = gdsc_gx_do_nothing_enable,
137	},
138	.pwrsts = PWRSTS_OFF_ON,
139	.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
140};
141
142static struct clk_regmap *gpu_cc_sdm845_clocks[] = {
143	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
144	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
145	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
146	[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
147};
148
149static struct gdsc *gpu_cc_sdm845_gdscs[] = {
150	[GPU_CX_GDSC] = &gpu_cx_gdsc,
151	[GPU_GX_GDSC] = &gpu_gx_gdsc,
152};
153
154static const struct regmap_config gpu_cc_sdm845_regmap_config = {
155	.reg_bits	= 32,
156	.reg_stride	= 4,
157	.val_bits	= 32,
158	.max_register	= 0x8008,
159	.fast_io	= true,
160};
161
162static const struct qcom_cc_desc gpu_cc_sdm845_desc = {
163	.config = &gpu_cc_sdm845_regmap_config,
164	.clks = gpu_cc_sdm845_clocks,
165	.num_clks = ARRAY_SIZE(gpu_cc_sdm845_clocks),
166	.gdscs = gpu_cc_sdm845_gdscs,
167	.num_gdscs = ARRAY_SIZE(gpu_cc_sdm845_gdscs),
168};
169
170static const struct of_device_id gpu_cc_sdm845_match_table[] = {
171	{ .compatible = "qcom,sdm845-gpucc" },
172	{ }
173};
174MODULE_DEVICE_TABLE(of, gpu_cc_sdm845_match_table);
175
176static int gpu_cc_sdm845_probe(struct platform_device *pdev)
177{
178	struct regmap *regmap;
179	unsigned int value, mask;
180
181	regmap = qcom_cc_map(pdev, &gpu_cc_sdm845_desc);
182	if (IS_ERR(regmap))
183		return PTR_ERR(regmap);
184
185	clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
186
187	/*
188	 * Configure gpu_cc_cx_gmu_clk with recommended
189	 * wakeup/sleep settings
190	 */
191	mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
192	mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
193	value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
194	regmap_update_bits(regmap, 0x1098, mask, value);
195
196	return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sdm845_desc, regmap);
197}
198
199static struct platform_driver gpu_cc_sdm845_driver = {
200	.probe = gpu_cc_sdm845_probe,
201	.driver = {
202		.name = "sdm845-gpucc",
203		.of_match_table = gpu_cc_sdm845_match_table,
204	},
205};
206
207module_platform_driver(gpu_cc_sdm845_driver);
208
209MODULE_DESCRIPTION("QTI GPUCC SDM845 Driver");
210MODULE_LICENSE("GPL v2");