gpucc-qcm2290.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
  4 * Copyright (c) 2024, Linaro Limited
  5 */
  6
  7#include <linux/clk-provider.h>
  8#include <linux/mod_devicetable.h>
  9#include <linux/module.h>
 10#include <linux/platform_device.h>
 11#include <linux/pm_clock.h>
 12#include <linux/pm_runtime.h>
 13#include <linux/regmap.h>
 14
 15#include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
 16
 17#include "clk-alpha-pll.h"
 18#include "clk-branch.h"
 19#include "clk-rcg.h"
 20#include "clk-regmap.h"
 21#include "clk-regmap-divider.h"
 22#include "clk-regmap-mux.h"
 23#include "clk-regmap-phy-mux.h"
 24#include "gdsc.h"
 25#include "reset.h"
 26
 27enum {
 28	DT_GCC_AHB_CLK,
 29	DT_BI_TCXO,
 30	DT_GCC_GPU_GPLL0_CLK_SRC,
 31	DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
 32};
 33
 34enum {
 35	P_BI_TCXO,
 36	P_GPLL0_OUT_MAIN,
 37	P_GPLL0_OUT_MAIN_DIV,
 38	P_GPU_CC_PLL0_2X_DIV_CLK_SRC,
 39	P_GPU_CC_PLL0_OUT_AUX,
 40	P_GPU_CC_PLL0_OUT_AUX2,
 41	P_GPU_CC_PLL0_OUT_MAIN,
 42};
 43
 44static const struct pll_vco huayra_vco[] = {
 45	{ 600000000, 3300000000, 0 },
 46	{ 600000000, 2200000000, 1 },
 47};
 48
 49static const struct alpha_pll_config gpu_cc_pll0_config = {
 50	.l = 0x25,
 51	.config_ctl_val = 0x200d4828,
 52	.config_ctl_hi_val = 0x6,
 53	.test_ctl_val = GENMASK(28, 26),
 54	.test_ctl_hi_val = BIT(14),
 55	.user_ctl_val = 0xf,
 56};
 57
 58static struct clk_alpha_pll gpu_cc_pll0 = {
 59	.offset = 0x0,
 60	.vco_table = huayra_vco,
 61	.num_vco = ARRAY_SIZE(huayra_vco),
 62	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290],
 63	.clkr = {
 64		.hw.init = &(struct clk_init_data){
 65			.name = "gpu_cc_pll0",
 66			.parent_data = &(const struct clk_parent_data) {
 67				.index = DT_BI_TCXO,
 68			},
 69			.num_parents = 1,
 70			.ops = &clk_alpha_pll_huayra_ops,
 71		},
 72	},
 73};
 74
 75static const struct parent_map gpu_cc_parent_map_0[] = {
 76	{ P_BI_TCXO, 0 },
 77	{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
 78	{ P_GPLL0_OUT_MAIN, 5 },
 79	{ P_GPLL0_OUT_MAIN_DIV, 6 },
 80};
 81
 82static const struct clk_parent_data gpu_cc_parent_data_0[] = {
 83	{ .index = DT_BI_TCXO, },
 84	{ .hw = &gpu_cc_pll0.clkr.hw, },
 85	{ .index = DT_GCC_GPU_GPLL0_CLK_SRC, },
 86	{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC, },
 87};
 88
 89static const struct parent_map gpu_cc_parent_map_1[] = {
 90	{ P_BI_TCXO, 0 },
 91	{ P_GPU_CC_PLL0_2X_DIV_CLK_SRC, 1 },
 92	{ P_GPU_CC_PLL0_OUT_AUX2, 2 },
 93	{ P_GPU_CC_PLL0_OUT_AUX, 3 },
 94	{ P_GPLL0_OUT_MAIN, 5 },
 95};
 96
 97static const struct clk_parent_data gpu_cc_parent_data_1[] = {
 98	{ .index = DT_BI_TCXO, },
 99	{ .hw = &gpu_cc_pll0.clkr.hw, },
100	{ .hw = &gpu_cc_pll0.clkr.hw, },
101	{ .hw = &gpu_cc_pll0.clkr.hw, },
102	{ .index = DT_GCC_GPU_GPLL0_CLK_SRC, },
103};
104
105static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
106	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
107	{ }
108};
109
110static struct clk_rcg2 gpu_cc_gmu_clk_src = {
111	.cmd_rcgr = 0x1120,
112	.mnd_width = 0,
113	.hid_width = 5,
114	.parent_map = gpu_cc_parent_map_0,
115	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
116	.clkr.hw.init = &(struct clk_init_data){
117		.name = "gpu_cc_gmu_clk_src",
118		.parent_data = gpu_cc_parent_data_0,
119		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
120		.flags = CLK_SET_RATE_PARENT,
121		.ops = &clk_rcg2_shared_ops,
122	},
123};
124
125static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
126	F(355200000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0),
127	F(537600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
128	F(672000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
129	F(844800000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
130	F(921600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
131	F(1017600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
132	F(1123200000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
133	{ }
134};
135
136static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
137	.cmd_rcgr = 0x101c,
138	.mnd_width = 0,
139	.hid_width = 5,
140	.parent_map = gpu_cc_parent_map_1,
141	.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
142	.clkr.hw.init = &(struct clk_init_data){
143		.name = "gpu_cc_gx_gfx3d_clk_src",
144		.parent_data = gpu_cc_parent_data_1,
145		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
146		.flags = CLK_SET_RATE_PARENT,
147		.ops = &clk_rcg2_ops,
148	},
149};
150
151static struct clk_branch gpu_cc_ahb_clk = {
152	.halt_reg = 0x1078,
153	.halt_check = BRANCH_HALT_DELAY,
154	.clkr = {
155		.enable_reg = 0x1078,
156		.enable_mask = BIT(0),
157		.hw.init = &(struct clk_init_data){
158			.name = "gpu_cc_ahb_clk",
159			.flags = CLK_IS_CRITICAL,
160			.ops = &clk_branch2_ops,
161		},
162	},
163};
164
165static struct clk_branch gpu_cc_crc_ahb_clk = {
166	.halt_reg = 0x107c,
167	.halt_check = BRANCH_HALT_DELAY,
168	.clkr = {
169		.enable_reg = 0x107c,
170		.enable_mask = BIT(0),
171		.hw.init = &(struct clk_init_data){
172			.name = "gpu_cc_crc_ahb_clk",
173			.ops = &clk_branch2_ops,
174		},
175	},
176};
177
178static struct clk_branch gpu_cc_cx_gfx3d_clk = {
179	.halt_reg = 0x10a4,
180	.halt_check = BRANCH_HALT_DELAY,
181	.clkr = {
182		.enable_reg = 0x10a4,
183		.enable_mask = BIT(0),
184		.hw.init = &(struct clk_init_data){
185			.name = "gpu_cc_cx_gfx3d_clk",
186			.parent_data = &(const struct clk_parent_data){
187				.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
188			},
189			.num_parents = 1,
190			.flags = CLK_SET_RATE_PARENT,
191			.ops = &clk_branch2_ops,
192		},
193	},
194};
195
196static struct clk_branch gpu_cc_cx_gmu_clk = {
197	.halt_reg = 0x1098,
198	.halt_check = BRANCH_HALT,
199	.clkr = {
200		.enable_reg = 0x1098,
201		.enable_mask = BIT(0),
202		.hw.init = &(struct clk_init_data){
203			.name = "gpu_cc_cx_gmu_clk",
204			.parent_data = &(const struct clk_parent_data){
205				.hw = &gpu_cc_gmu_clk_src.clkr.hw,
206			},
207			.num_parents = 1,
208			.flags = CLK_SET_RATE_PARENT,
209			.ops = &clk_branch2_ops,
210		},
211	},
212};
213
214static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
215	.halt_reg = 0x108c,
216	.halt_check = BRANCH_HALT_DELAY,
217	.clkr = {
218		.enable_reg = 0x108c,
219		.enable_mask = BIT(0),
220		.hw.init = &(struct clk_init_data){
221			.name = "gpu_cc_cx_snoc_dvm_clk",
222			.ops = &clk_branch2_ops,
223		},
224	},
225};
226
227static struct clk_branch gpu_cc_cxo_aon_clk = {
228	.halt_reg = 0x1004,
229	.halt_check = BRANCH_HALT_DELAY,
230	.clkr = {
231		.enable_reg = 0x1004,
232		.enable_mask = BIT(0),
233		.hw.init = &(struct clk_init_data){
234			.name = "gpu_cc_cxo_aon_clk",
235			.ops = &clk_branch2_ops,
236		},
237	},
238};
239
240static struct clk_branch gpu_cc_cxo_clk = {
241	.halt_reg = 0x109c,
242	.halt_check = BRANCH_HALT,
243	.clkr = {
244		.enable_reg = 0x109c,
245		.enable_mask = BIT(0),
246		.hw.init = &(struct clk_init_data){
247			.name = "gpu_cc_cxo_clk",
248			.ops = &clk_branch2_ops,
249		},
250	},
251};
252
253static struct clk_branch gpu_cc_gx_gfx3d_clk = {
254	.halt_reg = 0x1054,
255	.halt_check = BRANCH_HALT_DELAY,
256	.clkr = {
257		.enable_reg = 0x1054,
258		.enable_mask = BIT(0),
259		.hw.init = &(struct clk_init_data){
260			.name = "gpu_cc_gx_gfx3d_clk",
261			.parent_data = &(const struct clk_parent_data){
262				.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
263			},
264			.num_parents = 1,
265			.flags = CLK_SET_RATE_PARENT,
266			.ops = &clk_branch2_ops,
267		},
268	},
269};
270
271static struct clk_branch gpu_cc_sleep_clk = {
272	.halt_reg = 0x1090,
273	.halt_check = BRANCH_VOTED,
274	.clkr = {
275		.enable_reg = 0x1090,
276		.enable_mask = BIT(0),
277		.hw.init = &(struct clk_init_data){
278			.name = "gpu_cc_sleep_clk",
279			.ops = &clk_branch2_ops,
280		},
281	},
282};
283
284static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
285	.halt_reg = 0x5000,
286	.halt_check = BRANCH_VOTED,
287	.clkr = {
288		.enable_reg = 0x5000,
289		.enable_mask = BIT(0),
290		.hw.init = &(struct clk_init_data){
291			 .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
292			 .ops = &clk_branch2_ops,
293		},
294	},
295};
296
297static struct gdsc gpu_cx_gdsc = {
298	.gdscr = 0x106c,
299	.gds_hw_ctrl = 0x1540,
300	.pd = {
301		.name = "gpu_cx_gdsc",
302	},
303	.pwrsts = PWRSTS_OFF_ON,
304	.flags = VOTABLE,
305};
306
307static struct gdsc gpu_gx_gdsc = {
308	.gdscr = 0x100c,
309	.clamp_io_ctrl = 0x1508,
310	.resets = (unsigned int []){ GPU_GX_BCR },
311	.reset_count = 1,
312	.pd = {
313		.name = "gpu_gx_gdsc",
314	},
315	.parent = &gpu_cx_gdsc.pd,
316	.pwrsts = PWRSTS_OFF_ON,
317	.flags = CLAMP_IO | AON_RESET | SW_RESET,
318};
319
320static struct clk_regmap *gpu_cc_qcm2290_clocks[] = {
321	[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
322	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
323	[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
324	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
325	[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
326	[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
327	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
328	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
329	[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
330	[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
331	[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
332	[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
333	[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
334};
335
336static const struct qcom_reset_map gpu_cc_qcm2290_resets[] = {
337	[GPU_GX_BCR] = { 0x1008 },
338};
339
340static struct gdsc *gpu_cc_qcm2290_gdscs[] = {
341	[GPU_CX_GDSC] = &gpu_cx_gdsc,
342	[GPU_GX_GDSC] = &gpu_gx_gdsc,
343};
344
345static const struct regmap_config gpu_cc_qcm2290_regmap_config = {
346	.reg_bits = 32,
347	.reg_stride = 4,
348	.val_bits = 32,
349	.max_register = 0x9000,
350	.fast_io = true,
351};
352
353
354static const struct qcom_cc_desc gpu_cc_qcm2290_desc = {
355	.config = &gpu_cc_qcm2290_regmap_config,
356	.clks = gpu_cc_qcm2290_clocks,
357	.num_clks = ARRAY_SIZE(gpu_cc_qcm2290_clocks),
358	.resets = gpu_cc_qcm2290_resets,
359	.num_resets = ARRAY_SIZE(gpu_cc_qcm2290_resets),
360	.gdscs = gpu_cc_qcm2290_gdscs,
361	.num_gdscs = ARRAY_SIZE(gpu_cc_qcm2290_gdscs),
362};
363
364static const struct of_device_id gpu_cc_qcm2290_match_table[] = {
365	{ .compatible = "qcom,qcm2290-gpucc" },
366	{ }
367};
368MODULE_DEVICE_TABLE(of, gpu_cc_qcm2290_match_table);
369
370static int gpu_cc_qcm2290_probe(struct platform_device *pdev)
371{
372	struct regmap *regmap;
373	int ret;
374
375	regmap = qcom_cc_map(pdev, &gpu_cc_qcm2290_desc);
376	if (IS_ERR(regmap))
377		return PTR_ERR(regmap);
378
379	ret = devm_pm_runtime_enable(&pdev->dev);
380	if (ret)
381		return ret;
382
383	ret = devm_pm_clk_create(&pdev->dev);
384	if (ret)
385		return ret;
386
387	ret = pm_clk_add(&pdev->dev, NULL);
388	if (ret < 0) {
389		dev_err(&pdev->dev, "failed to acquire ahb clock\n");
390		return ret;
391	}
392
393	ret = pm_runtime_resume_and_get(&pdev->dev);
394	if (ret)
395		return ret;
396
397	clk_huayra_2290_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
398
399	regmap_update_bits(regmap, 0x1060, BIT(0), BIT(0)); /* GPU_CC_GX_CXO_CLK */
400
401	ret = qcom_cc_really_probe(&pdev->dev, &gpu_cc_qcm2290_desc, regmap);
402	if (ret) {
403		dev_err(&pdev->dev, "Failed to register display clock controller\n");
404		goto out_pm_runtime_put;
405	}
406
407out_pm_runtime_put:
408	pm_runtime_put_sync(&pdev->dev);
409
410	return 0;
411}
412
413static struct platform_driver gpu_cc_qcm2290_driver = {
414	.probe = gpu_cc_qcm2290_probe,
415	.driver = {
416		.name = "gpucc-qcm2290",
417		.of_match_table = gpu_cc_qcm2290_match_table,
418	},
419};
420module_platform_driver(gpu_cc_qcm2290_driver);
421
422MODULE_DESCRIPTION("QTI QCM2290 GPU clock controller driver");
423MODULE_LICENSE("GPL");