gcc-x1e80100.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/mod_devicetable.h>
   8#include <linux/module.h>
   9#include <linux/platform_device.h>
  10#include <linux/regmap.h>
  11
  12#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
  13
  14#include "clk-alpha-pll.h"
  15#include "clk-branch.h"
  16#include "clk-rcg.h"
  17#include "clk-regmap.h"
  18#include "clk-regmap-divider.h"
  19#include "clk-regmap-mux.h"
  20#include "clk-regmap-phy-mux.h"
  21#include "gdsc.h"
  22#include "reset.h"
  23
  24enum {
  25	DT_BI_TCXO,
  26	DT_SLEEP_CLK,
  27	DT_PCIE_3_PIPE,
  28	DT_PCIE_4_PIPE,
  29	DT_PCIE_5_PIPE,
  30	DT_PCIE_6A_PIPE,
  31	DT_PCIE_6B_PIPE,
  32	DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE,
  33	DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE,
  34	DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE,
  35	DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
  36	DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
  37	DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
  38	DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
  39	DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
  40	DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC,
  41	DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC,
  42	DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
  43	DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
  44	DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
  45	DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
  46	DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
  47	DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
  48	DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
  49	DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
  50	DT_QUSB4PHY_0_GCC_USB4_RX0_CLK,
  51	DT_QUSB4PHY_0_GCC_USB4_RX1_CLK,
  52	DT_QUSB4PHY_1_GCC_USB4_RX0_CLK,
  53	DT_QUSB4PHY_1_GCC_USB4_RX1_CLK,
  54	DT_QUSB4PHY_2_GCC_USB4_RX0_CLK,
  55	DT_QUSB4PHY_2_GCC_USB4_RX1_CLK,
  56	DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
  57	DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
  58	DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
  59	DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
  60	DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
  61	DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
  62};
  63
  64enum {
  65	P_BI_TCXO,
  66	P_GCC_GPLL0_OUT_EVEN,
  67	P_GCC_GPLL0_OUT_MAIN,
  68	P_GCC_GPLL4_OUT_MAIN,
  69	P_GCC_GPLL7_OUT_MAIN,
  70	P_GCC_GPLL8_OUT_MAIN,
  71	P_GCC_GPLL9_OUT_MAIN,
  72	P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC,
  73	P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC,
  74	P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC,
  75	P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
  76	P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
  77	P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
  78	P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
  79	P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
  80	P_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC,
  81	P_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC,
  82	P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
  83	P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
  84	P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
  85	P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
  86	P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
  87	P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
  88	P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
  89	P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
  90	P_QUSB4PHY_0_GCC_USB4_RX0_CLK,
  91	P_QUSB4PHY_0_GCC_USB4_RX1_CLK,
  92	P_QUSB4PHY_1_GCC_USB4_RX0_CLK,
  93	P_QUSB4PHY_1_GCC_USB4_RX1_CLK,
  94	P_QUSB4PHY_2_GCC_USB4_RX0_CLK,
  95	P_QUSB4PHY_2_GCC_USB4_RX1_CLK,
  96	P_SLEEP_CLK,
  97	P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,
  98	P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,
  99	P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,
 100	P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
 101	P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
 102	P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
 103	P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
 104	P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
 105	P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
 106};
 107
 108static struct clk_alpha_pll gcc_gpll0 = {
 109	.offset = 0x0,
 110	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 111	.clkr = {
 112		.enable_reg = 0x52030,
 113		.enable_mask = BIT(0),
 114		.hw.init = &(const struct clk_init_data) {
 115			.name = "gcc_gpll0",
 116			.parent_data = &(const struct clk_parent_data) {
 117				.index = DT_BI_TCXO,
 118			},
 119			.num_parents = 1,
 120			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 121		},
 122	},
 123};
 124
 125static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
 126	{ 0x1, 2 },
 127	{ }
 128};
 129
 130static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
 131	.offset = 0x0,
 132	.post_div_shift = 10,
 133	.post_div_table = post_div_table_gcc_gpll0_out_even,
 134	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
 135	.width = 4,
 136	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 137	.clkr.hw.init = &(const struct clk_init_data) {
 138		.name = "gcc_gpll0_out_even",
 139		.parent_hws = (const struct clk_hw*[]) {
 140			&gcc_gpll0.clkr.hw,
 141		},
 142		.num_parents = 1,
 143		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 144	},
 145};
 146
 147static struct clk_alpha_pll gcc_gpll4 = {
 148	.offset = 0x4000,
 149	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 150	.clkr = {
 151		.enable_reg = 0x52030,
 152		.enable_mask = BIT(4),
 153		.hw.init = &(const struct clk_init_data) {
 154			.name = "gcc_gpll4",
 155			.parent_data = &(const struct clk_parent_data) {
 156				.index = DT_BI_TCXO,
 157			},
 158			.num_parents = 1,
 159			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 160		},
 161	},
 162};
 163
 164static struct clk_alpha_pll gcc_gpll7 = {
 165	.offset = 0x7000,
 166	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 167	.clkr = {
 168		.enable_reg = 0x52030,
 169		.enable_mask = BIT(7),
 170		.hw.init = &(const struct clk_init_data) {
 171			.name = "gcc_gpll7",
 172			.parent_data = &(const struct clk_parent_data) {
 173				.index = DT_BI_TCXO,
 174			},
 175			.num_parents = 1,
 176			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 177		},
 178	},
 179};
 180
 181static struct clk_alpha_pll gcc_gpll8 = {
 182	.offset = 0x8000,
 183	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 184	.clkr = {
 185		.enable_reg = 0x52030,
 186		.enable_mask = BIT(8),
 187		.hw.init = &(const struct clk_init_data) {
 188			.name = "gcc_gpll8",
 189			.parent_data = &(const struct clk_parent_data) {
 190				.index = DT_BI_TCXO,
 191			},
 192			.num_parents = 1,
 193			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 194		},
 195	},
 196};
 197
 198static struct clk_alpha_pll gcc_gpll9 = {
 199	.offset = 0x9000,
 200	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 201	.clkr = {
 202		.enable_reg = 0x52030,
 203		.enable_mask = BIT(9),
 204		.hw.init = &(const struct clk_init_data) {
 205			.name = "gcc_gpll9",
 206			.parent_data = &(const struct clk_parent_data) {
 207				.index = DT_BI_TCXO,
 208			},
 209			.num_parents = 1,
 210			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 211		},
 212	},
 213};
 214
 215static const struct parent_map gcc_parent_map_0[] = {
 216	{ P_BI_TCXO, 0 },
 217	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 218	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 219};
 220
 221static const struct clk_parent_data gcc_parent_data_0[] = {
 222	{ .index = DT_BI_TCXO },
 223	{ .hw = &gcc_gpll0.clkr.hw },
 224	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 225};
 226
 227static const struct parent_map gcc_parent_map_1[] = {
 228	{ P_BI_TCXO, 0 },
 229	{ P_SLEEP_CLK, 5 },
 230};
 231
 232static const struct clk_parent_data gcc_parent_data_1[] = {
 233	{ .index = DT_BI_TCXO },
 234	{ .index = DT_SLEEP_CLK },
 235};
 236
 237static const struct parent_map gcc_parent_map_2[] = {
 238	{ P_BI_TCXO, 0 },
 239	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 240	{ P_SLEEP_CLK, 5 },
 241	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 242};
 243
 244static const struct clk_parent_data gcc_parent_data_2[] = {
 245	{ .index = DT_BI_TCXO },
 246	{ .hw = &gcc_gpll0.clkr.hw },
 247	{ .index = DT_SLEEP_CLK },
 248	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 249};
 250
 251static const struct parent_map gcc_parent_map_3[] = {
 252	{ P_BI_TCXO, 0 },
 253};
 254
 255static const struct clk_parent_data gcc_parent_data_3[] = {
 256	{ .index = DT_BI_TCXO },
 257};
 258
 259static const struct parent_map gcc_parent_map_4[] = {
 260	{ P_BI_TCXO, 0 },
 261	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 262	{ P_GCC_GPLL8_OUT_MAIN, 2 },
 263	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 264};
 265
 266static const struct clk_parent_data gcc_parent_data_4[] = {
 267	{ .index = DT_BI_TCXO },
 268	{ .hw = &gcc_gpll0.clkr.hw },
 269	{ .hw = &gcc_gpll8.clkr.hw },
 270	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 271};
 272
 273static const struct parent_map gcc_parent_map_5[] = {
 274	{ P_BI_TCXO, 0 },
 275	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 276	{ P_GCC_GPLL7_OUT_MAIN, 2 },
 277	{ P_SLEEP_CLK, 5 },
 278};
 279
 280static const struct clk_parent_data gcc_parent_data_5[] = {
 281	{ .index = DT_BI_TCXO },
 282	{ .hw = &gcc_gpll0.clkr.hw },
 283	{ .hw = &gcc_gpll7.clkr.hw },
 284	{ .index = DT_SLEEP_CLK },
 285};
 286
 287static const struct parent_map gcc_parent_map_6[] = {
 288	{ P_BI_TCXO, 0 },
 289	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 290	{ P_GCC_GPLL7_OUT_MAIN, 2 },
 291};
 292
 293static const struct clk_parent_data gcc_parent_data_6[] = {
 294	{ .index = DT_BI_TCXO },
 295	{ .hw = &gcc_gpll0.clkr.hw },
 296	{ .hw = &gcc_gpll7.clkr.hw },
 297};
 298
 299static const struct parent_map gcc_parent_map_7[] = {
 300	{ P_BI_TCXO, 0 },
 301	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 302	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 303	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 304};
 305
 306static const struct clk_parent_data gcc_parent_data_7[] = {
 307	{ .index = DT_BI_TCXO },
 308	{ .hw = &gcc_gpll0.clkr.hw },
 309	{ .hw = &gcc_gpll4.clkr.hw },
 310	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 311};
 312
 313static const struct parent_map gcc_parent_map_8[] = {
 314	{ P_BI_TCXO, 0 },
 315	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 316	{ P_GCC_GPLL7_OUT_MAIN, 2 },
 317	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 318};
 319
 320static const struct clk_parent_data gcc_parent_data_8[] = {
 321	{ .index = DT_BI_TCXO },
 322	{ .hw = &gcc_gpll0.clkr.hw },
 323	{ .hw = &gcc_gpll7.clkr.hw },
 324	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 325};
 326
 327static const struct parent_map gcc_parent_map_9[] = {
 328	{ P_BI_TCXO, 0 },
 329	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 330	{ P_GCC_GPLL9_OUT_MAIN, 2 },
 331	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 332	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 333};
 334
 335static const struct clk_parent_data gcc_parent_data_10[] = {
 336	{ .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE },
 337	{ .index = DT_BI_TCXO },
 338};
 339
 340static const struct parent_map gcc_parent_map_10[] = {
 341	{ P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 342	{ P_BI_TCXO, 2 },
 343};
 344
 345static const struct clk_parent_data gcc_parent_data_11[] = {
 346	{ .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE },
 347	{ .index = DT_BI_TCXO },
 348};
 349
 350static const struct parent_map gcc_parent_map_11[] = {
 351	{ P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 352	{ P_BI_TCXO, 2 },
 353};
 354
 355static const struct clk_parent_data gcc_parent_data_12[] = {
 356	{ .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE },
 357	{ .index = DT_BI_TCXO },
 358};
 359
 360static const struct parent_map gcc_parent_map_12[] = {
 361	{ P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 362	{ P_BI_TCXO, 2 },
 363};
 364
 365static const struct clk_parent_data gcc_parent_data_9[] = {
 366	{ .index = DT_BI_TCXO },
 367	{ .hw = &gcc_gpll0.clkr.hw },
 368	{ .hw = &gcc_gpll9.clkr.hw },
 369	{ .hw = &gcc_gpll4.clkr.hw },
 370	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 371};
 372
 373static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 374	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 375	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 376	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
 377	{ }
 378};
 379
 380static const struct clk_parent_data gcc_parent_data_13[] = {
 381	{ .index = DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC },
 382	{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 383};
 384
 385static const struct clk_parent_data gcc_parent_data_14[] = {
 386	{ .index = DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC },
 387	{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 388};
 389
 390static const struct clk_parent_data gcc_parent_data_15[] = {
 391	{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
 392	{ .index = DT_BI_TCXO },
 393};
 394
 395static const struct clk_parent_data gcc_parent_data_16[] = {
 396	{ .index = DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC },
 397	{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
 398};
 399
 400static const struct clk_parent_data gcc_parent_data_17[] = {
 401	{ .index = DT_QUSB4PHY_0_GCC_USB4_RX0_CLK },
 402	{ .index = DT_BI_TCXO },
 403};
 404
 405static const struct clk_parent_data gcc_parent_data_18[] = {
 406	{ .index = DT_QUSB4PHY_0_GCC_USB4_RX1_CLK },
 407	{ .index = DT_BI_TCXO },
 408};
 409
 410static const struct clk_parent_data gcc_parent_data_19[] = {
 411	{ .index = DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC },
 412	{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
 413};
 414
 415static const struct clk_parent_data gcc_parent_data_20[] = {
 416	{ .index = DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC },
 417	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 418};
 419
 420static const struct clk_parent_data gcc_parent_data_21[] = {
 421	{ .index = DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC },
 422	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 423};
 424
 425static const struct clk_parent_data gcc_parent_data_22[] = {
 426	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
 427	{ .index = DT_BI_TCXO },
 428};
 429
 430static const struct clk_parent_data gcc_parent_data_23[] = {
 431	{ .index = DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC },
 432	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
 433};
 434
 435static const struct clk_parent_data gcc_parent_data_24[] = {
 436	{ .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK },
 437	{ .index = DT_BI_TCXO },
 438};
 439
 440static const struct clk_parent_data gcc_parent_data_25[] = {
 441	{ .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK },
 442	{ .index = DT_BI_TCXO },
 443};
 444
 445static const struct clk_parent_data gcc_parent_data_26[] = {
 446	{ .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },
 447	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
 448};
 449
 450static const struct clk_parent_data gcc_parent_data_27[] = {
 451	{ .index = DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC },
 452	{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 453};
 454
 455static const struct clk_parent_data gcc_parent_data_28[] = {
 456	{ .index = DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC },
 457	{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 458};
 459
 460static const struct clk_parent_data gcc_parent_data_29[] = {
 461	{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
 462	{ .index = DT_BI_TCXO },
 463};
 464
 465static const struct clk_parent_data gcc_parent_data_30[] = {
 466	{ .index = DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC },
 467	{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
 468};
 469
 470static const struct clk_parent_data gcc_parent_data_31[] = {
 471	{ .index = DT_QUSB4PHY_2_GCC_USB4_RX0_CLK },
 472	{ .index = DT_BI_TCXO },
 473};
 474
 475static const struct clk_parent_data gcc_parent_data_32[] = {
 476	{ .index = DT_QUSB4PHY_2_GCC_USB4_RX1_CLK },
 477	{ .index = DT_BI_TCXO },
 478};
 479
 480static const struct clk_parent_data gcc_parent_data_33[] = {
 481	{ .index = DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC },
 482	{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
 483};
 484
 485static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp0_clk_src = {
 486	.reg = 0x9f06c,
 487	.clkr = {
 488		.hw.init = &(const struct clk_init_data) {
 489			.name = "gcc_usb4_0_phy_dp0_clk_src",
 490			.parent_data = gcc_parent_data_13,
 491			.ops = &clk_regmap_phy_mux_ops,
 492		},
 493	},
 494};
 495
 496static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp1_clk_src = {
 497	.reg = 0x9f114,
 498	.clkr = {
 499		.hw.init = &(const struct clk_init_data) {
 500			.name = "gcc_usb4_0_phy_dp1_clk_src",
 501			.parent_data = gcc_parent_data_14,
 502			.ops = &clk_regmap_phy_mux_ops,
 503		},
 504	},
 505};
 506
 507static struct clk_regmap_phy_mux gcc_usb4_0_phy_p2rr2p_pipe_clk_src = {
 508	.reg = 0x9f0d4,
 509	.clkr = {
 510		.hw.init = &(const struct clk_init_data) {
 511			.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk_src",
 512			.parent_data = gcc_parent_data_15,
 513			.ops = &clk_regmap_phy_mux_ops,
 514		},
 515	},
 516};
 517
 518static struct clk_regmap_phy_mux gcc_usb4_0_phy_pcie_pipe_mux_clk_src = {
 519	.reg = 0x9f104,
 520	.clkr = {
 521		.hw.init = &(const struct clk_init_data) {
 522			.name = "gcc_usb4_0_phy_pcie_pipe_mux_clk_src",
 523			.parent_data = gcc_parent_data_16,
 524			.ops = &clk_regmap_phy_mux_ops,
 525		},
 526	},
 527};
 528
 529static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx0_clk_src = {
 530	.reg = 0x9f0ac,
 531	.clkr = {
 532		.hw.init = &(const struct clk_init_data) {
 533			.name = "gcc_usb4_0_phy_rx0_clk_src",
 534			.parent_data = gcc_parent_data_17,
 535			.ops = &clk_regmap_phy_mux_ops,
 536		},
 537	},
 538};
 539
 540static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx1_clk_src = {
 541	.reg = 0x9f0bc,
 542	.clkr = {
 543		.hw.init = &(const struct clk_init_data) {
 544			.name = "gcc_usb4_0_phy_rx1_clk_src",
 545			.parent_data = gcc_parent_data_18,
 546			.ops = &clk_regmap_phy_mux_ops,
 547		},
 548	},
 549};
 550
 551static struct clk_regmap_phy_mux gcc_usb4_0_phy_sys_clk_src = {
 552	.reg = 0x9f0e4,
 553	.clkr = {
 554		.hw.init = &(const struct clk_init_data) {
 555			.name = "gcc_usb4_0_phy_sys_clk_src",
 556			.parent_data = gcc_parent_data_19,
 557			.ops = &clk_regmap_phy_mux_ops,
 558		},
 559	},
 560};
 561
 562static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp0_clk_src = {
 563	.reg = 0x2b06c,
 564	.clkr = {
 565		.hw.init = &(const struct clk_init_data) {
 566			.name = "gcc_usb4_1_phy_dp0_clk_src",
 567			.parent_data = gcc_parent_data_20,
 568			.ops = &clk_regmap_phy_mux_ops,
 569		},
 570	},
 571};
 572
 573static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp1_clk_src = {
 574	.reg = 0x2b114,
 575	.clkr = {
 576		.hw.init = &(const struct clk_init_data) {
 577			.name = "gcc_usb4_1_phy_dp1_clk_src",
 578			.parent_data = gcc_parent_data_21,
 579			.ops = &clk_regmap_phy_mux_ops,
 580		},
 581	},
 582};
 583
 584static struct clk_regmap_phy_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = {
 585	.reg = 0x2b0d4,
 586	.clkr = {
 587		.hw.init = &(const struct clk_init_data) {
 588			.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src",
 589			.parent_data = gcc_parent_data_22,
 590			.ops = &clk_regmap_phy_mux_ops,
 591		},
 592	},
 593};
 594
 595static struct clk_regmap_phy_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = {
 596	.reg = 0x2b104,
 597	.clkr = {
 598		.hw.init = &(const struct clk_init_data) {
 599			.name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src",
 600			.parent_data = gcc_parent_data_23,
 601			.ops = &clk_regmap_phy_mux_ops,
 602		},
 603	},
 604};
 605
 606static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx0_clk_src = {
 607	.reg = 0x2b0ac,
 608	.clkr = {
 609		.hw.init = &(const struct clk_init_data) {
 610			.name = "gcc_usb4_1_phy_rx0_clk_src",
 611			.parent_data = gcc_parent_data_24,
 612			.ops = &clk_regmap_phy_mux_ops,
 613		},
 614	},
 615};
 616
 617static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx1_clk_src = {
 618	.reg = 0x2b0bc,
 619	.clkr = {
 620		.hw.init = &(const struct clk_init_data) {
 621			.name = "gcc_usb4_1_phy_rx1_clk_src",
 622			.parent_data = gcc_parent_data_25,
 623			.ops = &clk_regmap_phy_mux_ops,
 624		},
 625	},
 626};
 627
 628static struct clk_regmap_phy_mux gcc_usb4_1_phy_sys_clk_src = {
 629	.reg = 0x2b0e4,
 630	.clkr = {
 631		.hw.init = &(const struct clk_init_data) {
 632			.name = "gcc_usb4_1_phy_sys_clk_src",
 633			.parent_data = gcc_parent_data_26,
 634			.ops = &clk_regmap_phy_mux_ops,
 635		},
 636	},
 637};
 638
 639static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp0_clk_src = {
 640	.reg = 0x1106c,
 641	.clkr = {
 642		.hw.init = &(const struct clk_init_data) {
 643			.name = "gcc_usb4_2_phy_dp0_clk_src",
 644			.parent_data = gcc_parent_data_27,
 645			.ops = &clk_regmap_phy_mux_ops,
 646		},
 647	},
 648};
 649
 650static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp1_clk_src = {
 651	.reg = 0x11114,
 652	.clkr = {
 653		.hw.init = &(const struct clk_init_data) {
 654			.name = "gcc_usb4_2_phy_dp1_clk_src",
 655			.parent_data = gcc_parent_data_28,
 656			.ops = &clk_regmap_phy_mux_ops,
 657		},
 658	},
 659};
 660
 661static struct clk_regmap_phy_mux gcc_usb4_2_phy_p2rr2p_pipe_clk_src = {
 662	.reg = 0x110d4,
 663	.clkr = {
 664		.hw.init = &(const struct clk_init_data) {
 665			.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk_src",
 666			.parent_data = gcc_parent_data_29,
 667			.ops = &clk_regmap_phy_mux_ops,
 668		},
 669	},
 670};
 671
 672static struct clk_regmap_phy_mux gcc_usb4_2_phy_pcie_pipe_mux_clk_src = {
 673	.reg = 0x11104,
 674	.clkr = {
 675		.hw.init = &(const struct clk_init_data) {
 676			.name = "gcc_usb4_2_phy_pcie_pipe_mux_clk_src",
 677			.parent_data = gcc_parent_data_30,
 678			.ops = &clk_regmap_phy_mux_ops,
 679		},
 680	},
 681};
 682
 683static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx0_clk_src = {
 684	.reg = 0x110ac,
 685	.clkr = {
 686		.hw.init = &(const struct clk_init_data) {
 687			.name = "gcc_usb4_2_phy_rx0_clk_src",
 688			.parent_data = gcc_parent_data_31,
 689			.ops = &clk_regmap_phy_mux_ops,
 690		},
 691	},
 692};
 693
 694static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx1_clk_src = {
 695	.reg = 0x110bc,
 696	.clkr = {
 697		.hw.init = &(const struct clk_init_data) {
 698			.name = "gcc_usb4_2_phy_rx1_clk_src",
 699			.parent_data = gcc_parent_data_32,
 700			.ops = &clk_regmap_phy_mux_ops,
 701		},
 702	},
 703};
 704
 705static struct clk_regmap_phy_mux gcc_usb4_2_phy_sys_clk_src = {
 706	.reg = 0x110e4,
 707	.clkr = {
 708		.hw.init = &(const struct clk_init_data) {
 709			.name = "gcc_usb4_2_phy_sys_clk_src",
 710			.parent_data = gcc_parent_data_33,
 711			.ops = &clk_regmap_phy_mux_ops,
 712		},
 713	},
 714};
 715
 716static struct clk_rcg2 gcc_gp1_clk_src = {
 717	.cmd_rcgr = 0x64004,
 718	.mnd_width = 16,
 719	.hid_width = 5,
 720	.parent_map = gcc_parent_map_2,
 721	.freq_tbl = ftbl_gcc_gp1_clk_src,
 722	.clkr.hw.init = &(const struct clk_init_data) {
 723		.name = "gcc_gp1_clk_src",
 724		.parent_data = gcc_parent_data_2,
 725		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 726		.flags = CLK_SET_RATE_PARENT,
 727		.ops = &clk_rcg2_shared_ops,
 728	},
 729};
 730
 731static struct clk_rcg2 gcc_gp2_clk_src = {
 732	.cmd_rcgr = 0x65004,
 733	.mnd_width = 16,
 734	.hid_width = 5,
 735	.parent_map = gcc_parent_map_2,
 736	.freq_tbl = ftbl_gcc_gp1_clk_src,
 737	.clkr.hw.init = &(const struct clk_init_data) {
 738		.name = "gcc_gp2_clk_src",
 739		.parent_data = gcc_parent_data_2,
 740		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 741		.flags = CLK_SET_RATE_PARENT,
 742		.ops = &clk_rcg2_shared_ops,
 743	},
 744};
 745
 746static struct clk_rcg2 gcc_gp3_clk_src = {
 747	.cmd_rcgr = 0x66004,
 748	.mnd_width = 16,
 749	.hid_width = 5,
 750	.parent_map = gcc_parent_map_2,
 751	.freq_tbl = ftbl_gcc_gp1_clk_src,
 752	.clkr.hw.init = &(const struct clk_init_data) {
 753		.name = "gcc_gp3_clk_src",
 754		.parent_data = gcc_parent_data_2,
 755		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 756		.flags = CLK_SET_RATE_PARENT,
 757		.ops = &clk_rcg2_shared_ops,
 758	},
 759};
 760
 761static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 762	F(19200000, P_BI_TCXO, 1, 0, 0),
 763	{ }
 764};
 765
 766static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 767	.cmd_rcgr = 0xa0180,
 768	.mnd_width = 16,
 769	.hid_width = 5,
 770	.parent_map = gcc_parent_map_1,
 771	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 772	.clkr.hw.init = &(const struct clk_init_data) {
 773		.name = "gcc_pcie_0_aux_clk_src",
 774		.parent_data = gcc_parent_data_1,
 775		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 776		.flags = CLK_SET_RATE_PARENT,
 777		.ops = &clk_rcg2_shared_ops,
 778	},
 779};
 780
 781static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
 782	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 783	{ }
 784};
 785
 786static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
 787	.cmd_rcgr = 0xa0054,
 788	.mnd_width = 0,
 789	.hid_width = 5,
 790	.parent_map = gcc_parent_map_0,
 791	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 792	.clkr.hw.init = &(const struct clk_init_data) {
 793		.name = "gcc_pcie_0_phy_rchng_clk_src",
 794		.parent_data = gcc_parent_data_0,
 795		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 796		.flags = CLK_SET_RATE_PARENT,
 797		.ops = &clk_rcg2_shared_ops,
 798	},
 799};
 800
 801static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 802	.cmd_rcgr = 0x2c180,
 803	.mnd_width = 16,
 804	.hid_width = 5,
 805	.parent_map = gcc_parent_map_1,
 806	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 807	.clkr.hw.init = &(const struct clk_init_data) {
 808		.name = "gcc_pcie_1_aux_clk_src",
 809		.parent_data = gcc_parent_data_1,
 810		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 811		.flags = CLK_SET_RATE_PARENT,
 812		.ops = &clk_rcg2_shared_ops,
 813	},
 814};
 815
 816static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
 817	.cmd_rcgr = 0x2c054,
 818	.mnd_width = 0,
 819	.hid_width = 5,
 820	.parent_map = gcc_parent_map_0,
 821	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 822	.clkr.hw.init = &(const struct clk_init_data) {
 823		.name = "gcc_pcie_1_phy_rchng_clk_src",
 824		.parent_data = gcc_parent_data_0,
 825		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 826		.flags = CLK_SET_RATE_PARENT,
 827		.ops = &clk_rcg2_shared_ops,
 828	},
 829};
 830
 831static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
 832	.cmd_rcgr = 0x13180,
 833	.mnd_width = 16,
 834	.hid_width = 5,
 835	.parent_map = gcc_parent_map_1,
 836	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 837	.clkr.hw.init = &(const struct clk_init_data) {
 838		.name = "gcc_pcie_2_aux_clk_src",
 839		.parent_data = gcc_parent_data_1,
 840		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 841		.flags = CLK_SET_RATE_PARENT,
 842		.ops = &clk_rcg2_shared_ops,
 843	},
 844};
 845
 846static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = {
 847	.cmd_rcgr = 0x13054,
 848	.mnd_width = 0,
 849	.hid_width = 5,
 850	.parent_map = gcc_parent_map_0,
 851	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 852	.clkr.hw.init = &(const struct clk_init_data) {
 853		.name = "gcc_pcie_2_phy_rchng_clk_src",
 854		.parent_data = gcc_parent_data_0,
 855		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 856		.flags = CLK_SET_RATE_PARENT,
 857		.ops = &clk_rcg2_shared_ops,
 858	},
 859};
 860
 861static struct clk_rcg2 gcc_pcie_3_aux_clk_src = {
 862	.cmd_rcgr = 0x5808c,
 863	.mnd_width = 16,
 864	.hid_width = 5,
 865	.parent_map = gcc_parent_map_1,
 866	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 867	.clkr.hw.init = &(const struct clk_init_data) {
 868		.name = "gcc_pcie_3_aux_clk_src",
 869		.parent_data = gcc_parent_data_1,
 870		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 871		.flags = CLK_SET_RATE_PARENT,
 872		.ops = &clk_rcg2_shared_ops,
 873	},
 874};
 875
 876static struct clk_rcg2 gcc_pcie_3_phy_rchng_clk_src = {
 877	.cmd_rcgr = 0x58070,
 878	.mnd_width = 0,
 879	.hid_width = 5,
 880	.parent_map = gcc_parent_map_0,
 881	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 882	.clkr.hw.init = &(const struct clk_init_data) {
 883		.name = "gcc_pcie_3_phy_rchng_clk_src",
 884		.parent_data = gcc_parent_data_0,
 885		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 886		.flags = CLK_SET_RATE_PARENT,
 887		.ops = &clk_rcg2_shared_ops,
 888	},
 889};
 890
 891static struct clk_rcg2 gcc_pcie_4_aux_clk_src = {
 892	.cmd_rcgr = 0x6b080,
 893	.mnd_width = 16,
 894	.hid_width = 5,
 895	.parent_map = gcc_parent_map_1,
 896	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 897	.clkr.hw.init = &(const struct clk_init_data) {
 898		.name = "gcc_pcie_4_aux_clk_src",
 899		.parent_data = gcc_parent_data_1,
 900		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 901		.flags = CLK_SET_RATE_PARENT,
 902		.ops = &clk_rcg2_shared_ops,
 903	},
 904};
 905
 906static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = {
 907	.cmd_rcgr = 0x6b064,
 908	.mnd_width = 0,
 909	.hid_width = 5,
 910	.parent_map = gcc_parent_map_0,
 911	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 912	.clkr.hw.init = &(const struct clk_init_data) {
 913		.name = "gcc_pcie_4_phy_rchng_clk_src",
 914		.parent_data = gcc_parent_data_0,
 915		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 916		.flags = CLK_SET_RATE_PARENT,
 917		.ops = &clk_rcg2_shared_ops,
 918	},
 919};
 920
 921static struct clk_rcg2 gcc_pcie_5_aux_clk_src = {
 922	.cmd_rcgr = 0x2f080,
 923	.mnd_width = 16,
 924	.hid_width = 5,
 925	.parent_map = gcc_parent_map_1,
 926	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 927	.clkr.hw.init = &(const struct clk_init_data) {
 928		.name = "gcc_pcie_5_aux_clk_src",
 929		.parent_data = gcc_parent_data_1,
 930		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 931		.flags = CLK_SET_RATE_PARENT,
 932		.ops = &clk_rcg2_shared_ops,
 933	},
 934};
 935
 936static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = {
 937	.cmd_rcgr = 0x2f064,
 938	.mnd_width = 0,
 939	.hid_width = 5,
 940	.parent_map = gcc_parent_map_0,
 941	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 942	.clkr.hw.init = &(const struct clk_init_data) {
 943		.name = "gcc_pcie_5_phy_rchng_clk_src",
 944		.parent_data = gcc_parent_data_0,
 945		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 946		.flags = CLK_SET_RATE_PARENT,
 947		.ops = &clk_rcg2_shared_ops,
 948	},
 949};
 950
 951static struct clk_rcg2 gcc_pcie_6a_aux_clk_src = {
 952	.cmd_rcgr = 0x3108c,
 953	.mnd_width = 16,
 954	.hid_width = 5,
 955	.parent_map = gcc_parent_map_1,
 956	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 957	.clkr.hw.init = &(const struct clk_init_data) {
 958		.name = "gcc_pcie_6a_aux_clk_src",
 959		.parent_data = gcc_parent_data_1,
 960		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 961		.flags = CLK_SET_RATE_PARENT,
 962		.ops = &clk_rcg2_shared_ops,
 963	},
 964};
 965
 966static struct clk_rcg2 gcc_pcie_6a_phy_rchng_clk_src = {
 967	.cmd_rcgr = 0x31070,
 968	.mnd_width = 0,
 969	.hid_width = 5,
 970	.parent_map = gcc_parent_map_0,
 971	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 972	.clkr.hw.init = &(const struct clk_init_data) {
 973		.name = "gcc_pcie_6a_phy_rchng_clk_src",
 974		.parent_data = gcc_parent_data_0,
 975		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 976		.flags = CLK_SET_RATE_PARENT,
 977		.ops = &clk_rcg2_shared_ops,
 978	},
 979};
 980
 981static struct clk_rcg2 gcc_pcie_6b_aux_clk_src = {
 982	.cmd_rcgr = 0x8d08c,
 983	.mnd_width = 16,
 984	.hid_width = 5,
 985	.parent_map = gcc_parent_map_1,
 986	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 987	.clkr.hw.init = &(const struct clk_init_data) {
 988		.name = "gcc_pcie_6b_aux_clk_src",
 989		.parent_data = gcc_parent_data_1,
 990		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 991		.flags = CLK_SET_RATE_PARENT,
 992		.ops = &clk_rcg2_shared_ops,
 993	},
 994};
 995
 996static struct clk_rcg2 gcc_pcie_6b_phy_rchng_clk_src = {
 997	.cmd_rcgr = 0x8d070,
 998	.mnd_width = 0,
 999	.hid_width = 5,
1000	.parent_map = gcc_parent_map_0,
1001	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1002	.clkr.hw.init = &(const struct clk_init_data) {
1003		.name = "gcc_pcie_6b_phy_rchng_clk_src",
1004		.parent_data = gcc_parent_data_0,
1005		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1006		.flags = CLK_SET_RATE_PARENT,
1007		.ops = &clk_rcg2_shared_ops,
1008	},
1009};
1010
1011static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = {
1012	.cmd_rcgr = 0xa400c,
1013	.mnd_width = 0,
1014	.hid_width = 5,
1015	.parent_map = gcc_parent_map_3,
1016	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1017	.clkr.hw.init = &(const struct clk_init_data) {
1018		.name = "gcc_pcie_rscc_xo_clk_src",
1019		.parent_data = gcc_parent_data_3,
1020		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1021		.flags = CLK_SET_RATE_PARENT,
1022		.ops = &clk_rcg2_shared_ops,
1023	},
1024};
1025
1026static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
1027	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
1028	{ }
1029};
1030
1031static struct clk_rcg2 gcc_pdm2_clk_src = {
1032	.cmd_rcgr = 0x33010,
1033	.mnd_width = 0,
1034	.hid_width = 5,
1035	.parent_map = gcc_parent_map_0,
1036	.freq_tbl = ftbl_gcc_pdm2_clk_src,
1037	.clkr.hw.init = &(const struct clk_init_data) {
1038		.name = "gcc_pdm2_clk_src",
1039		.parent_data = gcc_parent_data_0,
1040		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1041		.flags = CLK_SET_RATE_PARENT,
1042		.ops = &clk_rcg2_shared_ops,
1043	},
1044};
1045
1046static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
1047	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1048	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1049	F(19200000, P_BI_TCXO, 1, 0, 0),
1050	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1051	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1052	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1053	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1054	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1055	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1056	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1057	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1058	{ }
1059};
1060
1061static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
1062	.name = "gcc_qupv3_wrap0_s0_clk_src",
1063	.parent_data = gcc_parent_data_0,
1064	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1065	.flags = CLK_SET_RATE_PARENT,
1066	.ops = &clk_rcg2_ops,
1067};
1068
1069static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
1070	.cmd_rcgr = 0x42010,
1071	.mnd_width = 16,
1072	.hid_width = 5,
1073	.parent_map = gcc_parent_map_0,
1074	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1075	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
1076};
1077
1078static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
1079	.name = "gcc_qupv3_wrap0_s1_clk_src",
1080	.parent_data = gcc_parent_data_0,
1081	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1082	.flags = CLK_SET_RATE_PARENT,
1083	.ops = &clk_rcg2_ops,
1084};
1085
1086static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
1087	.cmd_rcgr = 0x42148,
1088	.mnd_width = 16,
1089	.hid_width = 5,
1090	.parent_map = gcc_parent_map_0,
1091	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1092	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
1093};
1094
1095static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
1096	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1097	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1098	F(19200000, P_BI_TCXO, 1, 0, 0),
1099	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1100	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1101	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1102	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1103	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1104	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1105	F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1106	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1107	{ }
1108};
1109
1110static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
1111	.name = "gcc_qupv3_wrap0_s2_clk_src",
1112	.parent_data = gcc_parent_data_0,
1113	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1114	.flags = CLK_SET_RATE_PARENT,
1115	.ops = &clk_rcg2_ops,
1116};
1117
1118static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
1119	.cmd_rcgr = 0x42288,
1120	.mnd_width = 16,
1121	.hid_width = 5,
1122	.parent_map = gcc_parent_map_0,
1123	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1124	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
1125};
1126
1127static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
1128	.name = "gcc_qupv3_wrap0_s3_clk_src",
1129	.parent_data = gcc_parent_data_0,
1130	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1131	.flags = CLK_SET_RATE_PARENT,
1132	.ops = &clk_rcg2_ops,
1133};
1134
1135static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
1136	.cmd_rcgr = 0x423c8,
1137	.mnd_width = 16,
1138	.hid_width = 5,
1139	.parent_map = gcc_parent_map_0,
1140	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1141	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
1142};
1143
1144static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = {
1145	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1146	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1147	F(19200000, P_BI_TCXO, 1, 0, 0),
1148	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1149	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1150	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1151	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1152	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1153	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1154	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1155	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1156	{ }
1157};
1158
1159static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
1160	.name = "gcc_qupv3_wrap0_s4_clk_src",
1161	.parent_data = gcc_parent_data_0,
1162	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1163	.flags = CLK_SET_RATE_PARENT,
1164	.ops = &clk_rcg2_ops,
1165};
1166
1167static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
1168	.cmd_rcgr = 0x42500,
1169	.mnd_width = 16,
1170	.hid_width = 5,
1171	.parent_map = gcc_parent_map_0,
1172	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1173	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
1174};
1175
1176static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
1177	.name = "gcc_qupv3_wrap0_s5_clk_src",
1178	.parent_data = gcc_parent_data_0,
1179	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1180	.flags = CLK_SET_RATE_PARENT,
1181	.ops = &clk_rcg2_ops,
1182};
1183
1184static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
1185	.cmd_rcgr = 0x42638,
1186	.mnd_width = 16,
1187	.hid_width = 5,
1188	.parent_map = gcc_parent_map_0,
1189	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1190	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
1191};
1192
1193static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
1194	.name = "gcc_qupv3_wrap0_s6_clk_src",
1195	.parent_data = gcc_parent_data_0,
1196	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1197	.flags = CLK_SET_RATE_PARENT,
1198	.ops = &clk_rcg2_ops,
1199};
1200
1201static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
1202	.cmd_rcgr = 0x42770,
1203	.mnd_width = 16,
1204	.hid_width = 5,
1205	.parent_map = gcc_parent_map_0,
1206	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1207	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
1208};
1209
1210static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
1211	.name = "gcc_qupv3_wrap0_s7_clk_src",
1212	.parent_data = gcc_parent_data_0,
1213	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1214	.flags = CLK_SET_RATE_PARENT,
1215	.ops = &clk_rcg2_ops,
1216};
1217
1218static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
1219	.cmd_rcgr = 0x428a8,
1220	.mnd_width = 16,
1221	.hid_width = 5,
1222	.parent_map = gcc_parent_map_0,
1223	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1224	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
1225};
1226
1227static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
1228	.name = "gcc_qupv3_wrap1_s0_clk_src",
1229	.parent_data = gcc_parent_data_0,
1230	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1231	.flags = CLK_SET_RATE_PARENT,
1232	.ops = &clk_rcg2_ops,
1233};
1234
1235static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
1236	.cmd_rcgr = 0x18010,
1237	.mnd_width = 16,
1238	.hid_width = 5,
1239	.parent_map = gcc_parent_map_0,
1240	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1241	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
1242};
1243
1244static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
1245	.name = "gcc_qupv3_wrap1_s1_clk_src",
1246	.parent_data = gcc_parent_data_0,
1247	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1248	.flags = CLK_SET_RATE_PARENT,
1249	.ops = &clk_rcg2_ops,
1250};
1251
1252static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
1253	.cmd_rcgr = 0x18148,
1254	.mnd_width = 16,
1255	.hid_width = 5,
1256	.parent_map = gcc_parent_map_0,
1257	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1258	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
1259};
1260
1261static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
1262	.name = "gcc_qupv3_wrap1_s2_clk_src",
1263	.parent_data = gcc_parent_data_0,
1264	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1265	.flags = CLK_SET_RATE_PARENT,
1266	.ops = &clk_rcg2_ops,
1267};
1268
1269static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
1270	.cmd_rcgr = 0x18288,
1271	.mnd_width = 16,
1272	.hid_width = 5,
1273	.parent_map = gcc_parent_map_0,
1274	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1275	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
1276};
1277
1278static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
1279	.name = "gcc_qupv3_wrap1_s3_clk_src",
1280	.parent_data = gcc_parent_data_0,
1281	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1282	.flags = CLK_SET_RATE_PARENT,
1283	.ops = &clk_rcg2_ops,
1284};
1285
1286static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
1287	.cmd_rcgr = 0x183c8,
1288	.mnd_width = 16,
1289	.hid_width = 5,
1290	.parent_map = gcc_parent_map_0,
1291	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1292	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
1293};
1294
1295static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
1296	.name = "gcc_qupv3_wrap1_s4_clk_src",
1297	.parent_data = gcc_parent_data_0,
1298	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1299	.flags = CLK_SET_RATE_PARENT,
1300	.ops = &clk_rcg2_ops,
1301};
1302
1303static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
1304	.cmd_rcgr = 0x18500,
1305	.mnd_width = 16,
1306	.hid_width = 5,
1307	.parent_map = gcc_parent_map_0,
1308	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1309	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
1310};
1311
1312static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
1313	.name = "gcc_qupv3_wrap1_s5_clk_src",
1314	.parent_data = gcc_parent_data_0,
1315	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1316	.flags = CLK_SET_RATE_PARENT,
1317	.ops = &clk_rcg2_ops,
1318};
1319
1320static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
1321	.cmd_rcgr = 0x18638,
1322	.mnd_width = 16,
1323	.hid_width = 5,
1324	.parent_map = gcc_parent_map_0,
1325	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1326	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
1327};
1328
1329static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
1330	.name = "gcc_qupv3_wrap1_s6_clk_src",
1331	.parent_data = gcc_parent_data_0,
1332	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1333	.flags = CLK_SET_RATE_PARENT,
1334	.ops = &clk_rcg2_ops,
1335};
1336
1337static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
1338	.cmd_rcgr = 0x18770,
1339	.mnd_width = 16,
1340	.hid_width = 5,
1341	.parent_map = gcc_parent_map_0,
1342	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1343	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
1344};
1345
1346static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
1347	.name = "gcc_qupv3_wrap1_s7_clk_src",
1348	.parent_data = gcc_parent_data_0,
1349	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1350	.flags = CLK_SET_RATE_PARENT,
1351	.ops = &clk_rcg2_ops,
1352};
1353
1354static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
1355	.cmd_rcgr = 0x188a8,
1356	.mnd_width = 16,
1357	.hid_width = 5,
1358	.parent_map = gcc_parent_map_0,
1359	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1360	.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
1361};
1362
1363static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
1364	.name = "gcc_qupv3_wrap2_s0_clk_src",
1365	.parent_data = gcc_parent_data_0,
1366	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1367	.flags = CLK_SET_RATE_PARENT,
1368	.ops = &clk_rcg2_ops,
1369};
1370
1371static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
1372	.cmd_rcgr = 0x1e010,
1373	.mnd_width = 16,
1374	.hid_width = 5,
1375	.parent_map = gcc_parent_map_0,
1376	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1377	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
1378};
1379
1380static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
1381	.name = "gcc_qupv3_wrap2_s1_clk_src",
1382	.parent_data = gcc_parent_data_0,
1383	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1384	.flags = CLK_SET_RATE_PARENT,
1385	.ops = &clk_rcg2_ops,
1386};
1387
1388static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
1389	.cmd_rcgr = 0x1e148,
1390	.mnd_width = 16,
1391	.hid_width = 5,
1392	.parent_map = gcc_parent_map_0,
1393	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1394	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
1395};
1396
1397static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
1398	.name = "gcc_qupv3_wrap2_s2_clk_src",
1399	.parent_data = gcc_parent_data_0,
1400	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1401	.flags = CLK_SET_RATE_PARENT,
1402	.ops = &clk_rcg2_ops,
1403};
1404
1405static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
1406	.cmd_rcgr = 0x1e288,
1407	.mnd_width = 16,
1408	.hid_width = 5,
1409	.parent_map = gcc_parent_map_0,
1410	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1411	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
1412};
1413
1414static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
1415	.name = "gcc_qupv3_wrap2_s3_clk_src",
1416	.parent_data = gcc_parent_data_0,
1417	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1418	.flags = CLK_SET_RATE_PARENT,
1419	.ops = &clk_rcg2_ops,
1420};
1421
1422static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
1423	.cmd_rcgr = 0x1e3c8,
1424	.mnd_width = 16,
1425	.hid_width = 5,
1426	.parent_map = gcc_parent_map_0,
1427	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1428	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
1429};
1430
1431static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
1432	.name = "gcc_qupv3_wrap2_s4_clk_src",
1433	.parent_data = gcc_parent_data_0,
1434	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1435	.flags = CLK_SET_RATE_PARENT,
1436	.ops = &clk_rcg2_ops,
1437};
1438
1439static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
1440	.cmd_rcgr = 0x1e500,
1441	.mnd_width = 16,
1442	.hid_width = 5,
1443	.parent_map = gcc_parent_map_0,
1444	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1445	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
1446};
1447
1448static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
1449	.name = "gcc_qupv3_wrap2_s5_clk_src",
1450	.parent_data = gcc_parent_data_0,
1451	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1452	.flags = CLK_SET_RATE_PARENT,
1453	.ops = &clk_rcg2_ops,
1454};
1455
1456static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
1457	.cmd_rcgr = 0x1e638,
1458	.mnd_width = 16,
1459	.hid_width = 5,
1460	.parent_map = gcc_parent_map_0,
1461	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1462	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
1463};
1464
1465static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
1466	.name = "gcc_qupv3_wrap2_s6_clk_src",
1467	.parent_data = gcc_parent_data_8,
1468	.num_parents = ARRAY_SIZE(gcc_parent_data_8),
1469	.flags = CLK_SET_RATE_PARENT,
1470	.ops = &clk_rcg2_ops,
1471};
1472
1473static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
1474	.cmd_rcgr = 0x1e770,
1475	.mnd_width = 16,
1476	.hid_width = 5,
1477	.parent_map = gcc_parent_map_8,
1478	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1479	.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
1480};
1481
1482static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
1483	.name = "gcc_qupv3_wrap2_s7_clk_src",
1484	.parent_data = gcc_parent_data_0,
1485	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1486	.flags = CLK_SET_RATE_PARENT,
1487	.ops = &clk_rcg2_ops,
1488};
1489
1490static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
1491	.cmd_rcgr = 0x1e8a8,
1492	.mnd_width = 16,
1493	.hid_width = 5,
1494	.parent_map = gcc_parent_map_0,
1495	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1496	.clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
1497};
1498
1499static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1500	F(400000, P_BI_TCXO, 12, 1, 4),
1501	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1502	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1503	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1504	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1505	{ }
1506};
1507
1508static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1509	.cmd_rcgr = 0x14018,
1510	.mnd_width = 8,
1511	.hid_width = 5,
1512	.parent_map = gcc_parent_map_9,
1513	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1514	.clkr.hw.init = &(const struct clk_init_data) {
1515		.name = "gcc_sdcc2_apps_clk_src",
1516		.parent_data = gcc_parent_data_9,
1517		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
1518		.flags = CLK_SET_RATE_PARENT,
1519		.ops = &clk_rcg2_shared_floor_ops,
1520	},
1521};
1522
1523static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
1524	F(400000, P_BI_TCXO, 12, 1, 4),
1525	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1526	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1527	{ }
1528};
1529
1530static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
1531	.cmd_rcgr = 0x16018,
1532	.mnd_width = 8,
1533	.hid_width = 5,
1534	.parent_map = gcc_parent_map_0,
1535	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
1536	.clkr.hw.init = &(const struct clk_init_data) {
1537		.name = "gcc_sdcc4_apps_clk_src",
1538		.parent_data = gcc_parent_data_0,
1539		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1540		.flags = CLK_SET_RATE_PARENT,
1541		.ops = &clk_rcg2_shared_floor_ops,
1542	},
1543};
1544
1545static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1546	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1547	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1548	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1549	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1550	{ }
1551};
1552
1553static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1554	.cmd_rcgr = 0x77030,
1555	.mnd_width = 8,
1556	.hid_width = 5,
1557	.parent_map = gcc_parent_map_0,
1558	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1559	.clkr.hw.init = &(const struct clk_init_data) {
1560		.name = "gcc_ufs_phy_axi_clk_src",
1561		.parent_data = gcc_parent_data_0,
1562		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1563		.flags = CLK_SET_RATE_PARENT,
1564		.ops = &clk_rcg2_shared_ops,
1565	},
1566};
1567
1568static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1569	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1570	F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1571	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1572	{ }
1573};
1574
1575static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1576	.cmd_rcgr = 0x77080,
1577	.mnd_width = 0,
1578	.hid_width = 5,
1579	.parent_map = gcc_parent_map_7,
1580	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1581	.clkr.hw.init = &(const struct clk_init_data) {
1582		.name = "gcc_ufs_phy_ice_core_clk_src",
1583		.parent_data = gcc_parent_data_7,
1584		.num_parents = ARRAY_SIZE(gcc_parent_data_7),
1585		.flags = CLK_SET_RATE_PARENT,
1586		.ops = &clk_rcg2_shared_ops,
1587	},
1588};
1589
1590static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1591	.cmd_rcgr = 0x770b4,
1592	.mnd_width = 0,
1593	.hid_width = 5,
1594	.parent_map = gcc_parent_map_3,
1595	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1596	.clkr.hw.init = &(const struct clk_init_data) {
1597		.name = "gcc_ufs_phy_phy_aux_clk_src",
1598		.parent_data = gcc_parent_data_3,
1599		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1600		.flags = CLK_SET_RATE_PARENT,
1601		.ops = &clk_rcg2_shared_ops,
1602	},
1603};
1604
1605static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
1606	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1607	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1608	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1609	{ }
1610};
1611
1612static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1613	.cmd_rcgr = 0x77098,
1614	.mnd_width = 0,
1615	.hid_width = 5,
1616	.parent_map = gcc_parent_map_0,
1617	.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
1618	.clkr.hw.init = &(const struct clk_init_data) {
1619		.name = "gcc_ufs_phy_unipro_core_clk_src",
1620		.parent_data = gcc_parent_data_0,
1621		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1622		.flags = CLK_SET_RATE_PARENT,
1623		.ops = &clk_rcg2_shared_ops,
1624	},
1625};
1626
1627static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
1628	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
1629	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1630	{ }
1631};
1632
1633static struct clk_rcg2 gcc_usb20_master_clk_src = {
1634	.cmd_rcgr = 0x2902c,
1635	.mnd_width = 8,
1636	.hid_width = 5,
1637	.parent_map = gcc_parent_map_0,
1638	.freq_tbl = ftbl_gcc_usb20_master_clk_src,
1639	.clkr.hw.init = &(const struct clk_init_data) {
1640		.name = "gcc_usb20_master_clk_src",
1641		.parent_data = gcc_parent_data_0,
1642		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1643		.flags = CLK_SET_RATE_PARENT,
1644		.ops = &clk_rcg2_shared_ops,
1645	},
1646};
1647
1648static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = {
1649	.cmd_rcgr = 0x29158,
1650	.mnd_width = 0,
1651	.hid_width = 5,
1652	.parent_map = gcc_parent_map_0,
1653	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1654	.clkr.hw.init = &(const struct clk_init_data) {
1655		.name = "gcc_usb20_mock_utmi_clk_src",
1656		.parent_data = gcc_parent_data_0,
1657		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1658		.flags = CLK_SET_RATE_PARENT,
1659		.ops = &clk_rcg2_shared_ops,
1660	},
1661};
1662
1663static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {
1664	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1665	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1666	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1667	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1668	{ }
1669};
1670
1671static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {
1672	.cmd_rcgr = 0x1702c,
1673	.mnd_width = 8,
1674	.hid_width = 5,
1675	.parent_map = gcc_parent_map_0,
1676	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1677	.clkr.hw.init = &(const struct clk_init_data) {
1678		.name = "gcc_usb30_mp_master_clk_src",
1679		.parent_data = gcc_parent_data_0,
1680		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1681		.flags = CLK_SET_RATE_PARENT,
1682		.ops = &clk_rcg2_shared_ops,
1683	},
1684};
1685
1686static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
1687	.cmd_rcgr = 0x17158,
1688	.mnd_width = 0,
1689	.hid_width = 5,
1690	.parent_map = gcc_parent_map_0,
1691	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1692	.clkr.hw.init = &(const struct clk_init_data) {
1693		.name = "gcc_usb30_mp_mock_utmi_clk_src",
1694		.parent_data = gcc_parent_data_0,
1695		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1696		.flags = CLK_SET_RATE_PARENT,
1697		.ops = &clk_rcg2_shared_ops,
1698	},
1699};
1700
1701static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1702	.cmd_rcgr = 0x3902c,
1703	.mnd_width = 8,
1704	.hid_width = 5,
1705	.parent_map = gcc_parent_map_0,
1706	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1707	.clkr.hw.init = &(const struct clk_init_data) {
1708		.name = "gcc_usb30_prim_master_clk_src",
1709		.parent_data = gcc_parent_data_0,
1710		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1711		.flags = CLK_SET_RATE_PARENT,
1712		.ops = &clk_rcg2_shared_ops,
1713	},
1714};
1715
1716static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1717	.cmd_rcgr = 0x39044,
1718	.mnd_width = 0,
1719	.hid_width = 5,
1720	.parent_map = gcc_parent_map_0,
1721	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1722	.clkr.hw.init = &(const struct clk_init_data) {
1723		.name = "gcc_usb30_prim_mock_utmi_clk_src",
1724		.parent_data = gcc_parent_data_0,
1725		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1726		.flags = CLK_SET_RATE_PARENT,
1727		.ops = &clk_rcg2_shared_ops,
1728	},
1729};
1730
1731static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1732	.cmd_rcgr = 0xa102c,
1733	.mnd_width = 8,
1734	.hid_width = 5,
1735	.parent_map = gcc_parent_map_0,
1736	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1737	.clkr.hw.init = &(const struct clk_init_data) {
1738		.name = "gcc_usb30_sec_master_clk_src",
1739		.parent_data = gcc_parent_data_0,
1740		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1741		.flags = CLK_SET_RATE_PARENT,
1742		.ops = &clk_rcg2_shared_ops,
1743	},
1744};
1745
1746static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1747	.cmd_rcgr = 0xa1044,
1748	.mnd_width = 0,
1749	.hid_width = 5,
1750	.parent_map = gcc_parent_map_0,
1751	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1752	.clkr.hw.init = &(const struct clk_init_data) {
1753		.name = "gcc_usb30_sec_mock_utmi_clk_src",
1754		.parent_data = gcc_parent_data_0,
1755		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1756		.flags = CLK_SET_RATE_PARENT,
1757		.ops = &clk_rcg2_shared_ops,
1758	},
1759};
1760
1761static struct clk_rcg2 gcc_usb30_tert_master_clk_src = {
1762	.cmd_rcgr = 0xa202c,
1763	.mnd_width = 8,
1764	.hid_width = 5,
1765	.parent_map = gcc_parent_map_0,
1766	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1767	.clkr.hw.init = &(const struct clk_init_data) {
1768		.name = "gcc_usb30_tert_master_clk_src",
1769		.parent_data = gcc_parent_data_0,
1770		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1771		.flags = CLK_SET_RATE_PARENT,
1772		.ops = &clk_rcg2_shared_ops,
1773	},
1774};
1775
1776static struct clk_rcg2 gcc_usb30_tert_mock_utmi_clk_src = {
1777	.cmd_rcgr = 0xa2044,
1778	.mnd_width = 0,
1779	.hid_width = 5,
1780	.parent_map = gcc_parent_map_0,
1781	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1782	.clkr.hw.init = &(const struct clk_init_data) {
1783		.name = "gcc_usb30_tert_mock_utmi_clk_src",
1784		.parent_data = gcc_parent_data_0,
1785		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1786		.flags = CLK_SET_RATE_PARENT,
1787		.ops = &clk_rcg2_shared_ops,
1788	},
1789};
1790
1791static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {
1792	.cmd_rcgr = 0x172a0,
1793	.mnd_width = 0,
1794	.hid_width = 5,
1795	.parent_map = gcc_parent_map_1,
1796	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1797	.clkr.hw.init = &(const struct clk_init_data) {
1798		.name = "gcc_usb3_mp_phy_aux_clk_src",
1799		.parent_data = gcc_parent_data_1,
1800		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1801		.flags = CLK_SET_RATE_PARENT,
1802		.ops = &clk_rcg2_shared_ops,
1803	},
1804};
1805
1806static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1807	.cmd_rcgr = 0x39074,
1808	.mnd_width = 0,
1809	.hid_width = 5,
1810	.parent_map = gcc_parent_map_1,
1811	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1812	.clkr.hw.init = &(const struct clk_init_data) {
1813		.name = "gcc_usb3_prim_phy_aux_clk_src",
1814		.parent_data = gcc_parent_data_1,
1815		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1816		.flags = CLK_SET_RATE_PARENT,
1817		.ops = &clk_rcg2_shared_ops,
1818	},
1819};
1820
1821static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1822	.cmd_rcgr = 0xa1074,
1823	.mnd_width = 0,
1824	.hid_width = 5,
1825	.parent_map = gcc_parent_map_1,
1826	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1827	.clkr.hw.init = &(const struct clk_init_data) {
1828		.name = "gcc_usb3_sec_phy_aux_clk_src",
1829		.parent_data = gcc_parent_data_1,
1830		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1831		.flags = CLK_SET_RATE_PARENT,
1832		.ops = &clk_rcg2_shared_ops,
1833	},
1834};
1835
1836static struct clk_rcg2 gcc_usb3_tert_phy_aux_clk_src = {
1837	.cmd_rcgr = 0xa2074,
1838	.mnd_width = 0,
1839	.hid_width = 5,
1840	.parent_map = gcc_parent_map_1,
1841	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1842	.clkr.hw.init = &(const struct clk_init_data) {
1843		.name = "gcc_usb3_tert_phy_aux_clk_src",
1844		.parent_data = gcc_parent_data_1,
1845		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1846		.flags = CLK_SET_RATE_PARENT,
1847		.ops = &clk_rcg2_shared_ops,
1848	},
1849};
1850
1851static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] = {
1852	F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
1853	F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
1854	{ }
1855};
1856
1857static struct clk_rcg2 gcc_usb4_0_master_clk_src = {
1858	.cmd_rcgr = 0x9f024,
1859	.mnd_width = 8,
1860	.hid_width = 5,
1861	.parent_map = gcc_parent_map_4,
1862	.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
1863	.clkr.hw.init = &(const struct clk_init_data) {
1864		.name = "gcc_usb4_0_master_clk_src",
1865		.parent_data = gcc_parent_data_4,
1866		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
1867		.flags = CLK_SET_RATE_PARENT,
1868		.ops = &clk_rcg2_shared_ops,
1869	},
1870};
1871
1872static const struct freq_tbl ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src[] = {
1873	F(19200000, P_BI_TCXO, 1, 0, 0),
1874	F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
1875	F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
1876	{ }
1877};
1878
1879static struct clk_rcg2 gcc_usb4_0_phy_pcie_pipe_clk_src = {
1880	.cmd_rcgr = 0x9f0e8,
1881	.mnd_width = 0,
1882	.hid_width = 5,
1883	.parent_map = gcc_parent_map_5,
1884	.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
1885	.clkr.hw.init = &(const struct clk_init_data) {
1886		.name = "gcc_usb4_0_phy_pcie_pipe_clk_src",
1887		.parent_data = gcc_parent_data_5,
1888		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
1889		.flags = CLK_SET_RATE_PARENT,
1890		.ops = &clk_rcg2_shared_ops,
1891	},
1892};
1893
1894static struct clk_rcg2 gcc_usb4_0_sb_if_clk_src = {
1895	.cmd_rcgr = 0x9f08c,
1896	.mnd_width = 0,
1897	.hid_width = 5,
1898	.parent_map = gcc_parent_map_3,
1899	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1900	.clkr.hw.init = &(const struct clk_init_data) {
1901		.name = "gcc_usb4_0_sb_if_clk_src",
1902		.parent_data = gcc_parent_data_3,
1903		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1904		.flags = CLK_SET_RATE_PARENT,
1905		.ops = &clk_rcg2_shared_ops,
1906	},
1907};
1908
1909static const struct freq_tbl ftbl_gcc_usb4_0_tmu_clk_src[] = {
1910	F(19200000, P_BI_TCXO, 1, 0, 0),
1911	F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
1912	{ }
1913};
1914
1915static struct clk_rcg2 gcc_usb4_0_tmu_clk_src = {
1916	.cmd_rcgr = 0x9f070,
1917	.mnd_width = 0,
1918	.hid_width = 5,
1919	.parent_map = gcc_parent_map_6,
1920	.freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,
1921	.clkr.hw.init = &(const struct clk_init_data) {
1922		.name = "gcc_usb4_0_tmu_clk_src",
1923		.parent_data = gcc_parent_data_6,
1924		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
1925		.flags = CLK_SET_RATE_PARENT,
1926		.ops = &clk_rcg2_shared_ops,
1927	},
1928};
1929
1930static struct clk_rcg2 gcc_usb4_1_master_clk_src = {
1931	.cmd_rcgr = 0x2b024,
1932	.mnd_width = 8,
1933	.hid_width = 5,
1934	.parent_map = gcc_parent_map_4,
1935	.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
1936	.clkr.hw.init = &(const struct clk_init_data) {
1937		.name = "gcc_usb4_1_master_clk_src",
1938		.parent_data = gcc_parent_data_4,
1939		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
1940		.flags = CLK_SET_RATE_PARENT,
1941		.ops = &clk_rcg2_shared_ops,
1942	},
1943};
1944
1945static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = {
1946	.cmd_rcgr = 0x2b0e8,
1947	.mnd_width = 0,
1948	.hid_width = 5,
1949	.parent_map = gcc_parent_map_5,
1950	.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
1951	.clkr.hw.init = &(const struct clk_init_data) {
1952		.name = "gcc_usb4_1_phy_pcie_pipe_clk_src",
1953		.parent_data = gcc_parent_data_5,
1954		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
1955		.flags = CLK_SET_RATE_PARENT,
1956		.ops = &clk_rcg2_shared_ops,
1957	},
1958};
1959
1960static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = {
1961	.cmd_rcgr = 0x2b08c,
1962	.mnd_width = 0,
1963	.hid_width = 5,
1964	.parent_map = gcc_parent_map_3,
1965	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1966	.clkr.hw.init = &(const struct clk_init_data) {
1967		.name = "gcc_usb4_1_sb_if_clk_src",
1968		.parent_data = gcc_parent_data_3,
1969		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1970		.flags = CLK_SET_RATE_PARENT,
1971		.ops = &clk_rcg2_shared_ops,
1972	},
1973};
1974
1975static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = {
1976	.cmd_rcgr = 0x2b070,
1977	.mnd_width = 0,
1978	.hid_width = 5,
1979	.parent_map = gcc_parent_map_6,
1980	.freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,
1981	.clkr.hw.init = &(const struct clk_init_data) {
1982		.name = "gcc_usb4_1_tmu_clk_src",
1983		.parent_data = gcc_parent_data_6,
1984		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
1985		.flags = CLK_SET_RATE_PARENT,
1986		.ops = &clk_rcg2_shared_ops,
1987	},
1988};
1989
1990static struct clk_rcg2 gcc_usb4_2_master_clk_src = {
1991	.cmd_rcgr = 0x11024,
1992	.mnd_width = 8,
1993	.hid_width = 5,
1994	.parent_map = gcc_parent_map_4,
1995	.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
1996	.clkr.hw.init = &(const struct clk_init_data) {
1997		.name = "gcc_usb4_2_master_clk_src",
1998		.parent_data = gcc_parent_data_4,
1999		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
2000		.flags = CLK_SET_RATE_PARENT,
2001		.ops = &clk_rcg2_shared_ops,
2002	},
2003};
2004
2005static struct clk_rcg2 gcc_usb4_2_phy_pcie_pipe_clk_src = {
2006	.cmd_rcgr = 0x110e8,
2007	.mnd_width = 0,
2008	.hid_width = 5,
2009	.parent_map = gcc_parent_map_5,
2010	.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
2011	.clkr.hw.init = &(const struct clk_init_data) {
2012		.name = "gcc_usb4_2_phy_pcie_pipe_clk_src",
2013		.parent_data = gcc_parent_data_5,
2014		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
2015		.flags = CLK_SET_RATE_PARENT,
2016		.ops = &clk_rcg2_shared_ops,
2017	},
2018};
2019
2020static struct clk_rcg2 gcc_usb4_2_sb_if_clk_src = {
2021	.cmd_rcgr = 0x1108c,
2022	.mnd_width = 0,
2023	.hid_width = 5,
2024	.parent_map = gcc_parent_map_3,
2025	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2026	.clkr.hw.init = &(const struct clk_init_data) {
2027		.name = "gcc_usb4_2_sb_if_clk_src",
2028		.parent_data = gcc_parent_data_3,
2029		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
2030		.flags = CLK_SET_RATE_PARENT,
2031		.ops = &clk_rcg2_shared_ops,
2032	},
2033};
2034
2035static struct clk_rcg2 gcc_usb4_2_tmu_clk_src = {
2036	.cmd_rcgr = 0x11070,
2037	.mnd_width = 0,
2038	.hid_width = 5,
2039	.parent_map = gcc_parent_map_6,
2040	.freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,
2041	.clkr.hw.init = &(const struct clk_init_data) {
2042		.name = "gcc_usb4_2_tmu_clk_src",
2043		.parent_data = gcc_parent_data_6,
2044		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
2045		.flags = CLK_SET_RATE_PARENT,
2046		.ops = &clk_rcg2_shared_ops,
2047	},
2048};
2049
2050static struct clk_regmap_phy_mux gcc_pcie_3_pipe_clk_src = {
2051	.reg = 0x58088,
2052	.clkr = {
2053		.hw.init = &(struct clk_init_data){
2054			.name = "gcc_pcie_3_pipe_clk_src",
2055			.parent_data = &(const struct clk_parent_data){
2056				.index = DT_PCIE_3_PIPE,
2057			},
2058			.num_parents = 1,
2059			.ops = &clk_regmap_phy_mux_ops,
2060		},
2061	},
2062};
2063
2064static struct clk_regmap_div gcc_pcie_3_pipe_div_clk_src = {
2065	.reg = 0x5806c,
2066	.shift = 0,
2067	.width = 4,
2068	.clkr.hw.init = &(const struct clk_init_data) {
2069		.name = "gcc_pcie_3_pipe_div_clk_src",
2070		.parent_hws = (const struct clk_hw*[]) {
2071			&gcc_pcie_3_pipe_clk_src.clkr.hw,
2072		},
2073		.num_parents = 1,
2074		.ops = &clk_regmap_div_ro_ops,
2075	},
2076};
2077
2078static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = {
2079	.reg = 0x6b07c,
2080	.clkr = {
2081		.hw.init = &(struct clk_init_data){
2082			.name = "gcc_pcie_4_pipe_clk_src",
2083			.parent_data = &(const struct clk_parent_data){
2084				.index = DT_PCIE_4_PIPE,
2085			},
2086			.num_parents = 1,
2087			.ops = &clk_regmap_phy_mux_ops,
2088		},
2089	},
2090};
2091
2092static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = {
2093	.reg = 0x6b060,
2094	.shift = 0,
2095	.width = 4,
2096	.clkr.hw.init = &(const struct clk_init_data) {
2097		.name = "gcc_pcie_4_pipe_div_clk_src",
2098		.parent_hws = (const struct clk_hw*[]) {
2099			&gcc_pcie_4_pipe_clk_src.clkr.hw,
2100		},
2101		.num_parents = 1,
2102		.ops = &clk_regmap_div_ro_ops,
2103	},
2104};
2105
2106static struct clk_regmap_phy_mux gcc_pcie_5_pipe_clk_src = {
2107	.reg = 0x2f07c,
2108	.clkr = {
2109		.hw.init = &(struct clk_init_data){
2110			.name = "gcc_pcie_5_pipe_clk_src",
2111			.parent_data = &(const struct clk_parent_data){
2112				.index = DT_PCIE_5_PIPE,
2113			},
2114			.num_parents = 1,
2115			.ops = &clk_regmap_phy_mux_ops,
2116		},
2117	},
2118};
2119
2120static struct clk_regmap_div gcc_pcie_5_pipe_div_clk_src = {
2121	.reg = 0x2f060,
2122	.shift = 0,
2123	.width = 4,
2124	.clkr.hw.init = &(const struct clk_init_data) {
2125		.name = "gcc_pcie_5_pipe_div_clk_src",
2126		.parent_hws = (const struct clk_hw*[]) {
2127			&gcc_pcie_5_pipe_clk_src.clkr.hw,
2128		},
2129		.num_parents = 1,
2130		.ops = &clk_regmap_div_ro_ops,
2131	},
2132};
2133
2134static struct clk_regmap_phy_mux gcc_pcie_6a_pipe_clk_src = {
2135	.reg = 0x31088,
2136	.clkr = {
2137		.hw.init = &(struct clk_init_data){
2138			.name = "gcc_pcie_6a_pipe_clk_src",
2139			.parent_data = &(const struct clk_parent_data){
2140				.index = DT_PCIE_6A_PIPE,
2141			},
2142			.num_parents = 1,
2143			.ops = &clk_regmap_phy_mux_ops,
2144		},
2145	},
2146};
2147
2148static struct clk_regmap_div gcc_pcie_6a_pipe_div_clk_src = {
2149	.reg = 0x3106c,
2150	.shift = 0,
2151	.width = 4,
2152	.clkr.hw.init = &(const struct clk_init_data) {
2153		.name = "gcc_pcie_6a_pipe_div_clk_src",
2154		.parent_hws = (const struct clk_hw*[]) {
2155			&gcc_pcie_6a_pipe_clk_src.clkr.hw,
2156		},
2157		.num_parents = 1,
2158		.ops = &clk_regmap_div_ro_ops,
2159	},
2160};
2161
2162static struct clk_regmap_phy_mux gcc_pcie_6b_pipe_clk_src = {
2163	.reg = 0x8d088,
2164	.clkr = {
2165		.hw.init = &(struct clk_init_data){
2166			.name = "gcc_pcie_6b_pipe_clk_src",
2167			.parent_data = &(const struct clk_parent_data){
2168				.index = DT_PCIE_6B_PIPE,
2169			},
2170			.num_parents = 1,
2171			.ops = &clk_regmap_phy_mux_ops,
2172		},
2173	},
2174};
2175
2176static struct clk_regmap_div gcc_pcie_6b_pipe_div_clk_src = {
2177	.reg = 0x8d06c,
2178	.shift = 0,
2179	.width = 4,
2180	.clkr.hw.init = &(const struct clk_init_data) {
2181		.name = "gcc_pcie_6b_pipe_div_clk_src",
2182		.parent_hws = (const struct clk_hw*[]) {
2183			&gcc_pcie_6b_pipe_clk_src.clkr.hw,
2184		},
2185		.num_parents = 1,
2186		.ops = &clk_regmap_div_ro_ops,
2187	},
2188};
2189
2190static struct clk_regmap_div gcc_qupv3_wrap0_s2_div_clk_src = {
2191	.reg = 0x42284,
2192	.shift = 0,
2193	.width = 4,
2194	.clkr.hw.init = &(const struct clk_init_data) {
2195		.name = "gcc_qupv3_wrap0_s2_div_clk_src",
2196		.parent_hws = (const struct clk_hw*[]) {
2197			&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2198		},
2199		.num_parents = 1,
2200		.flags = CLK_SET_RATE_PARENT,
2201		.ops = &clk_regmap_div_ro_ops,
2202	},
2203};
2204
2205static struct clk_regmap_div gcc_qupv3_wrap0_s3_div_clk_src = {
2206	.reg = 0x423c4,
2207	.shift = 0,
2208	.width = 4,
2209	.clkr.hw.init = &(const struct clk_init_data) {
2210		.name = "gcc_qupv3_wrap0_s3_div_clk_src",
2211		.parent_hws = (const struct clk_hw*[]) {
2212			&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2213		},
2214		.num_parents = 1,
2215		.flags = CLK_SET_RATE_PARENT,
2216		.ops = &clk_regmap_div_ro_ops,
2217	},
2218};
2219
2220static struct clk_regmap_div gcc_qupv3_wrap1_s2_div_clk_src = {
2221	.reg = 0x18284,
2222	.shift = 0,
2223	.width = 4,
2224	.clkr.hw.init = &(const struct clk_init_data) {
2225		.name = "gcc_qupv3_wrap1_s2_div_clk_src",
2226		.parent_hws = (const struct clk_hw*[]) {
2227			&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2228		},
2229		.num_parents = 1,
2230		.flags = CLK_SET_RATE_PARENT,
2231		.ops = &clk_regmap_div_ro_ops,
2232	},
2233};
2234
2235static struct clk_regmap_div gcc_qupv3_wrap1_s3_div_clk_src = {
2236	.reg = 0x183c4,
2237	.shift = 0,
2238	.width = 4,
2239	.clkr.hw.init = &(const struct clk_init_data) {
2240		.name = "gcc_qupv3_wrap1_s3_div_clk_src",
2241		.parent_hws = (const struct clk_hw*[]) {
2242			&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2243		},
2244		.num_parents = 1,
2245		.flags = CLK_SET_RATE_PARENT,
2246		.ops = &clk_regmap_div_ro_ops,
2247	},
2248};
2249
2250static struct clk_regmap_div gcc_qupv3_wrap2_s2_div_clk_src = {
2251	.reg = 0x1e284,
2252	.shift = 0,
2253	.width = 4,
2254	.clkr.hw.init = &(const struct clk_init_data) {
2255		.name = "gcc_qupv3_wrap2_s2_div_clk_src",
2256		.parent_hws = (const struct clk_hw*[]) {
2257			&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2258		},
2259		.num_parents = 1,
2260		.flags = CLK_SET_RATE_PARENT,
2261		.ops = &clk_regmap_div_ro_ops,
2262	},
2263};
2264
2265static struct clk_regmap_div gcc_qupv3_wrap2_s3_div_clk_src = {
2266	.reg = 0x1e3c4,
2267	.shift = 0,
2268	.width = 4,
2269	.clkr.hw.init = &(const struct clk_init_data) {
2270		.name = "gcc_qupv3_wrap2_s3_div_clk_src",
2271		.parent_hws = (const struct clk_hw*[]) {
2272			&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2273		},
2274		.num_parents = 1,
2275		.flags = CLK_SET_RATE_PARENT,
2276		.ops = &clk_regmap_div_ro_ops,
2277	},
2278};
2279
2280static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = {
2281	.reg = 0x29284,
2282	.shift = 0,
2283	.width = 4,
2284	.clkr.hw.init = &(const struct clk_init_data) {
2285		.name = "gcc_usb20_mock_utmi_postdiv_clk_src",
2286		.parent_hws = (const struct clk_hw*[]) {
2287			&gcc_usb20_mock_utmi_clk_src.clkr.hw,
2288		},
2289		.num_parents = 1,
2290		.flags = CLK_SET_RATE_PARENT,
2291		.ops = &clk_regmap_div_ro_ops,
2292	},
2293};
2294
2295static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = {
2296	.reg = 0x17284,
2297	.shift = 0,
2298	.width = 4,
2299	.clkr.hw.init = &(const struct clk_init_data) {
2300		.name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src",
2301		.parent_hws = (const struct clk_hw*[]) {
2302			&gcc_usb30_mp_mock_utmi_clk_src.clkr.hw,
2303		},
2304		.num_parents = 1,
2305		.flags = CLK_SET_RATE_PARENT,
2306		.ops = &clk_regmap_div_ro_ops,
2307	},
2308};
2309
2310static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
2311	.reg = 0x3905c,
2312	.shift = 0,
2313	.width = 4,
2314	.clkr.hw.init = &(const struct clk_init_data) {
2315		.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
2316		.parent_hws = (const struct clk_hw*[]) {
2317			&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
2318		},
2319		.num_parents = 1,
2320		.flags = CLK_SET_RATE_PARENT,
2321		.ops = &clk_regmap_div_ro_ops,
2322	},
2323};
2324
2325static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
2326	.reg = 0xa105c,
2327	.shift = 0,
2328	.width = 4,
2329	.clkr.hw.init = &(const struct clk_init_data) {
2330		.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
2331		.parent_hws = (const struct clk_hw*[]) {
2332			&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
2333		},
2334		.num_parents = 1,
2335		.flags = CLK_SET_RATE_PARENT,
2336		.ops = &clk_regmap_div_ro_ops,
2337	},
2338};
2339
2340static struct clk_regmap_div gcc_usb30_tert_mock_utmi_postdiv_clk_src = {
2341	.reg = 0xa205c,
2342	.shift = 0,
2343	.width = 4,
2344	.clkr.hw.init = &(const struct clk_init_data) {
2345		.name = "gcc_usb30_tert_mock_utmi_postdiv_clk_src",
2346		.parent_hws = (const struct clk_hw*[]) {
2347			&gcc_usb30_tert_mock_utmi_clk_src.clkr.hw,
2348		},
2349		.num_parents = 1,
2350		.flags = CLK_SET_RATE_PARENT,
2351		.ops = &clk_regmap_div_ro_ops,
2352	},
2353};
2354
2355static struct clk_branch gcc_aggre_noc_usb_north_axi_clk = {
2356	.halt_reg = 0x2d17c,
2357	.halt_check = BRANCH_HALT_VOTED,
2358	.hwcg_reg = 0x2d17c,
2359	.hwcg_bit = 1,
2360	.clkr = {
2361		.enable_reg = 0x2d17c,
2362		.enable_mask = BIT(0),
2363		.hw.init = &(const struct clk_init_data) {
2364			.name = "gcc_aggre_noc_usb_north_axi_clk",
2365			.ops = &clk_branch2_ops,
2366		},
2367	},
2368};
2369
2370static struct clk_branch gcc_aggre_noc_usb_south_axi_clk = {
2371	.halt_reg = 0x2d174,
2372	.halt_check = BRANCH_HALT_VOTED,
2373	.hwcg_reg = 0x2d174,
2374	.hwcg_bit = 1,
2375	.clkr = {
2376		.enable_reg = 0x2d174,
2377		.enable_mask = BIT(0),
2378		.hw.init = &(const struct clk_init_data) {
2379			.name = "gcc_aggre_noc_usb_south_axi_clk",
2380			.ops = &clk_branch2_ops,
2381		},
2382	},
2383};
2384
2385static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
2386	.halt_reg = 0x770e4,
2387	.halt_check = BRANCH_HALT_VOTED,
2388	.hwcg_reg = 0x770e4,
2389	.hwcg_bit = 1,
2390	.clkr = {
2391		.enable_reg = 0x770e4,
2392		.enable_mask = BIT(0),
2393		.hw.init = &(const struct clk_init_data) {
2394			.name = "gcc_aggre_ufs_phy_axi_clk",
2395			.parent_hws = (const struct clk_hw*[]) {
2396				&gcc_ufs_phy_axi_clk_src.clkr.hw,
2397			},
2398			.num_parents = 1,
2399			.flags = CLK_SET_RATE_PARENT,
2400			.ops = &clk_branch2_ops,
2401		},
2402	},
2403};
2404
2405static struct clk_branch gcc_aggre_usb2_prim_axi_clk = {
2406	.halt_reg = 0x2928c,
2407	.halt_check = BRANCH_HALT_VOTED,
2408	.hwcg_reg = 0x2928c,
2409	.hwcg_bit = 1,
2410	.clkr = {
2411		.enable_reg = 0x2928c,
2412		.enable_mask = BIT(0),
2413		.hw.init = &(const struct clk_init_data) {
2414			.name = "gcc_aggre_usb2_prim_axi_clk",
2415			.parent_hws = (const struct clk_hw*[]) {
2416				&gcc_usb20_master_clk_src.clkr.hw,
2417			},
2418			.num_parents = 1,
2419			.flags = CLK_SET_RATE_PARENT,
2420			.ops = &clk_branch2_ops,
2421		},
2422	},
2423};
2424
2425static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {
2426	.halt_reg = 0x173d0,
2427	.halt_check = BRANCH_HALT_VOTED,
2428	.hwcg_reg = 0x173d0,
2429	.hwcg_bit = 1,
2430	.clkr = {
2431		.enable_reg = 0x173d0,
2432		.enable_mask = BIT(0),
2433		.hw.init = &(const struct clk_init_data) {
2434			.name = "gcc_aggre_usb3_mp_axi_clk",
2435			.parent_hws = (const struct clk_hw*[]) {
2436				&gcc_usb30_mp_master_clk_src.clkr.hw,
2437			},
2438			.num_parents = 1,
2439			.flags = CLK_SET_RATE_PARENT,
2440			.ops = &clk_branch2_ops,
2441		},
2442	},
2443};
2444
2445static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
2446	.halt_reg = 0x39090,
2447	.halt_check = BRANCH_HALT_VOTED,
2448	.hwcg_reg = 0x39090,
2449	.hwcg_bit = 1,
2450	.clkr = {
2451		.enable_reg = 0x39090,
2452		.enable_mask = BIT(0),
2453		.hw.init = &(const struct clk_init_data) {
2454			.name = "gcc_aggre_usb3_prim_axi_clk",
2455			.parent_hws = (const struct clk_hw*[]) {
2456				&gcc_usb30_prim_master_clk_src.clkr.hw,
2457			},
2458			.num_parents = 1,
2459			.flags = CLK_SET_RATE_PARENT,
2460			.ops = &clk_branch2_ops,
2461		},
2462	},
2463};
2464
2465static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
2466	.halt_reg = 0xa1090,
2467	.halt_check = BRANCH_HALT_VOTED,
2468	.hwcg_reg = 0xa1090,
2469	.hwcg_bit = 1,
2470	.clkr = {
2471		.enable_reg = 0xa1090,
2472		.enable_mask = BIT(0),
2473		.hw.init = &(const struct clk_init_data) {
2474			.name = "gcc_aggre_usb3_sec_axi_clk",
2475			.parent_hws = (const struct clk_hw*[]) {
2476				&gcc_usb30_sec_master_clk_src.clkr.hw,
2477			},
2478			.num_parents = 1,
2479			.flags = CLK_SET_RATE_PARENT,
2480			.ops = &clk_branch2_ops,
2481		},
2482	},
2483};
2484
2485static struct clk_branch gcc_aggre_usb3_tert_axi_clk = {
2486	.halt_reg = 0xa2090,
2487	.halt_check = BRANCH_HALT_VOTED,
2488	.hwcg_reg = 0xa2090,
2489	.hwcg_bit = 1,
2490	.clkr = {
2491		.enable_reg = 0xa2090,
2492		.enable_mask = BIT(0),
2493		.hw.init = &(const struct clk_init_data) {
2494			.name = "gcc_aggre_usb3_tert_axi_clk",
2495			.parent_hws = (const struct clk_hw*[]) {
2496				&gcc_usb30_tert_master_clk_src.clkr.hw,
2497			},
2498			.num_parents = 1,
2499			.flags = CLK_SET_RATE_PARENT,
2500			.ops = &clk_branch2_ops,
2501		},
2502	},
2503};
2504
2505static struct clk_branch gcc_aggre_usb4_0_axi_clk = {
2506	.halt_reg = 0x9f118,
2507	.halt_check = BRANCH_HALT_VOTED,
2508	.hwcg_reg = 0x9f118,
2509	.hwcg_bit = 1,
2510	.clkr = {
2511		.enable_reg = 0x9f118,
2512		.enable_mask = BIT(0),
2513		.hw.init = &(const struct clk_init_data) {
2514			.name = "gcc_aggre_usb4_0_axi_clk",
2515			.parent_hws = (const struct clk_hw*[]) {
2516				&gcc_usb4_0_master_clk_src.clkr.hw,
2517			},
2518			.num_parents = 1,
2519			.flags = CLK_SET_RATE_PARENT,
2520			.ops = &clk_branch2_ops,
2521		},
2522	},
2523};
2524
2525static struct clk_branch gcc_aggre_usb4_1_axi_clk = {
2526	.halt_reg = 0x2b118,
2527	.halt_check = BRANCH_HALT_VOTED,
2528	.hwcg_reg = 0x2b118,
2529	.hwcg_bit = 1,
2530	.clkr = {
2531		.enable_reg = 0x2b118,
2532		.enable_mask = BIT(0),
2533		.hw.init = &(const struct clk_init_data) {
2534			.name = "gcc_aggre_usb4_1_axi_clk",
2535			.parent_hws = (const struct clk_hw*[]) {
2536				&gcc_usb4_1_master_clk_src.clkr.hw,
2537			},
2538			.num_parents = 1,
2539			.flags = CLK_SET_RATE_PARENT,
2540			.ops = &clk_branch2_ops,
2541		},
2542	},
2543};
2544
2545static struct clk_branch gcc_aggre_usb4_2_axi_clk = {
2546	.halt_reg = 0x11118,
2547	.halt_check = BRANCH_HALT_VOTED,
2548	.hwcg_reg = 0x11118,
2549	.hwcg_bit = 1,
2550	.clkr = {
2551		.enable_reg = 0x11118,
2552		.enable_mask = BIT(0),
2553		.hw.init = &(const struct clk_init_data) {
2554			.name = "gcc_aggre_usb4_2_axi_clk",
2555			.parent_hws = (const struct clk_hw*[]) {
2556				&gcc_usb4_2_master_clk_src.clkr.hw,
2557			},
2558			.num_parents = 1,
2559			.flags = CLK_SET_RATE_PARENT,
2560			.ops = &clk_branch2_ops,
2561		},
2562	},
2563};
2564
2565static struct clk_branch gcc_aggre_usb_noc_axi_clk = {
2566	.halt_reg = 0x2d034,
2567	.halt_check = BRANCH_HALT_VOTED,
2568	.hwcg_reg = 0x2d034,
2569	.hwcg_bit = 1,
2570	.clkr = {
2571		.enable_reg = 0x2d034,
2572		.enable_mask = BIT(0),
2573		.hw.init = &(const struct clk_init_data) {
2574			.name = "gcc_aggre_usb_noc_axi_clk",
2575			.ops = &clk_branch2_ops,
2576		},
2577	},
2578};
2579
2580static struct clk_branch gcc_av1e_ahb_clk = {
2581	.halt_reg = 0x4a004,
2582	.halt_check = BRANCH_HALT_VOTED,
2583	.hwcg_reg = 0x4a004,
2584	.hwcg_bit = 1,
2585	.clkr = {
2586		.enable_reg = 0x4a004,
2587		.enable_mask = BIT(0),
2588		.hw.init = &(const struct clk_init_data) {
2589			.name = "gcc_av1e_ahb_clk",
2590			.ops = &clk_branch2_ops,
2591		},
2592	},
2593};
2594
2595static struct clk_branch gcc_av1e_axi_clk = {
2596	.halt_reg = 0x4a008,
2597	.halt_check = BRANCH_HALT_SKIP,
2598	.hwcg_reg = 0x4a008,
2599	.hwcg_bit = 1,
2600	.clkr = {
2601		.enable_reg = 0x4a008,
2602		.enable_mask = BIT(0),
2603		.hw.init = &(const struct clk_init_data) {
2604			.name = "gcc_av1e_axi_clk",
2605			.ops = &clk_branch2_ops,
2606		},
2607	},
2608};
2609
2610static struct clk_branch gcc_av1e_xo_clk = {
2611	.halt_reg = 0x4a014,
2612	.halt_check = BRANCH_HALT,
2613	.clkr = {
2614		.enable_reg = 0x4a014,
2615		.enable_mask = BIT(0),
2616		.hw.init = &(const struct clk_init_data) {
2617			.name = "gcc_av1e_xo_clk",
2618			.ops = &clk_branch2_ops,
2619		},
2620	},
2621};
2622
2623static struct clk_branch gcc_boot_rom_ahb_clk = {
2624	.halt_reg = 0x38004,
2625	.halt_check = BRANCH_HALT_VOTED,
2626	.hwcg_reg = 0x38004,
2627	.hwcg_bit = 1,
2628	.clkr = {
2629		.enable_reg = 0x52000,
2630		.enable_mask = BIT(10),
2631		.hw.init = &(const struct clk_init_data) {
2632			.name = "gcc_boot_rom_ahb_clk",
2633			.ops = &clk_branch2_ops,
2634		},
2635	},
2636};
2637
2638static struct clk_branch gcc_camera_hf_axi_clk = {
2639	.halt_reg = 0x26010,
2640	.halt_check = BRANCH_HALT_SKIP,
2641	.hwcg_reg = 0x26010,
2642	.hwcg_bit = 1,
2643	.clkr = {
2644		.enable_reg = 0x26010,
2645		.enable_mask = BIT(0),
2646		.hw.init = &(const struct clk_init_data) {
2647			.name = "gcc_camera_hf_axi_clk",
2648			.ops = &clk_branch2_ops,
2649		},
2650	},
2651};
2652
2653static struct clk_branch gcc_camera_sf_axi_clk = {
2654	.halt_reg = 0x2601c,
2655	.halt_check = BRANCH_HALT_SKIP,
2656	.hwcg_reg = 0x2601c,
2657	.hwcg_bit = 1,
2658	.clkr = {
2659		.enable_reg = 0x2601c,
2660		.enable_mask = BIT(0),
2661		.hw.init = &(const struct clk_init_data) {
2662			.name = "gcc_camera_sf_axi_clk",
2663			.ops = &clk_branch2_ops,
2664		},
2665	},
2666};
2667
2668static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
2669	.halt_reg = 0x10028,
2670	.halt_check = BRANCH_HALT_VOTED,
2671	.hwcg_reg = 0x10028,
2672	.hwcg_bit = 1,
2673	.clkr = {
2674		.enable_reg = 0x52028,
2675		.enable_mask = BIT(20),
2676		.hw.init = &(const struct clk_init_data) {
2677			.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
2678			.ops = &clk_branch2_ops,
2679		},
2680	},
2681};
2682
2683static struct clk_branch gcc_cfg_noc_pcie_anoc_north_ahb_clk = {
2684	.halt_reg = 0x1002c,
2685	.halt_check = BRANCH_HALT_VOTED,
2686	.hwcg_reg = 0x1002c,
2687	.hwcg_bit = 1,
2688	.clkr = {
2689		.enable_reg = 0x52028,
2690		.enable_mask = BIT(22),
2691		.hw.init = &(const struct clk_init_data) {
2692			.name = "gcc_cfg_noc_pcie_anoc_north_ahb_clk",
2693			.ops = &clk_branch2_ops,
2694		},
2695	},
2696};
2697
2698static struct clk_branch gcc_cfg_noc_pcie_anoc_south_ahb_clk = {
2699	.halt_reg = 0x10030,
2700	.halt_check = BRANCH_HALT_VOTED,
2701	.hwcg_reg = 0x10030,
2702	.hwcg_bit = 1,
2703	.clkr = {
2704		.enable_reg = 0x52000,
2705		.enable_mask = BIT(20),
2706		.hw.init = &(const struct clk_init_data) {
2707			.name = "gcc_cfg_noc_pcie_anoc_south_ahb_clk",
2708			.ops = &clk_branch2_ops,
2709		},
2710	},
2711};
2712
2713static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = {
2714	.halt_reg = 0x29288,
2715	.halt_check = BRANCH_HALT_VOTED,
2716	.hwcg_reg = 0x29288,
2717	.hwcg_bit = 1,
2718	.clkr = {
2719		.enable_reg = 0x29288,
2720		.enable_mask = BIT(0),
2721		.hw.init = &(const struct clk_init_data) {
2722			.name = "gcc_cfg_noc_usb2_prim_axi_clk",
2723			.parent_hws = (const struct clk_hw*[]) {
2724				&gcc_usb20_master_clk_src.clkr.hw,
2725			},
2726			.num_parents = 1,
2727			.flags = CLK_SET_RATE_PARENT,
2728			.ops = &clk_branch2_ops,
2729		},
2730	},
2731};
2732
2733static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {
2734	.halt_reg = 0x173cc,
2735	.halt_check = BRANCH_HALT_VOTED,
2736	.hwcg_reg = 0x173cc,
2737	.hwcg_bit = 1,
2738	.clkr = {
2739		.enable_reg = 0x173cc,
2740		.enable_mask = BIT(0),
2741		.hw.init = &(const struct clk_init_data) {
2742			.name = "gcc_cfg_noc_usb3_mp_axi_clk",
2743			.parent_hws = (const struct clk_hw*[]) {
2744				&gcc_usb30_mp_master_clk_src.clkr.hw,
2745			},
2746			.num_parents = 1,
2747			.flags = CLK_SET_RATE_PARENT,
2748			.ops = &clk_branch2_ops,
2749		},
2750	},
2751};
2752
2753static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
2754	.halt_reg = 0x3908c,
2755	.halt_check = BRANCH_HALT_VOTED,
2756	.hwcg_reg = 0x3908c,
2757	.hwcg_bit = 1,
2758	.clkr = {
2759		.enable_reg = 0x3908c,
2760		.enable_mask = BIT(0),
2761		.hw.init = &(const struct clk_init_data) {
2762			.name = "gcc_cfg_noc_usb3_prim_axi_clk",
2763			.parent_hws = (const struct clk_hw*[]) {
2764				&gcc_usb30_prim_master_clk_src.clkr.hw,
2765			},
2766			.num_parents = 1,
2767			.flags = CLK_SET_RATE_PARENT,
2768			.ops = &clk_branch2_ops,
2769		},
2770	},
2771};
2772
2773static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
2774	.halt_reg = 0xa108c,
2775	.halt_check = BRANCH_HALT_VOTED,
2776	.hwcg_reg = 0xa108c,
2777	.hwcg_bit = 1,
2778	.clkr = {
2779		.enable_reg = 0xa108c,
2780		.enable_mask = BIT(0),
2781		.hw.init = &(const struct clk_init_data) {
2782			.name = "gcc_cfg_noc_usb3_sec_axi_clk",
2783			.parent_hws = (const struct clk_hw*[]) {
2784				&gcc_usb30_sec_master_clk_src.clkr.hw,
2785			},
2786			.num_parents = 1,
2787			.flags = CLK_SET_RATE_PARENT,
2788			.ops = &clk_branch2_ops,
2789		},
2790	},
2791};
2792
2793static struct clk_branch gcc_cfg_noc_usb3_tert_axi_clk = {
2794	.halt_reg = 0xa208c,
2795	.halt_check = BRANCH_HALT_VOTED,
2796	.hwcg_reg = 0xa208c,
2797	.hwcg_bit = 1,
2798	.clkr = {
2799		.enable_reg = 0xa208c,
2800		.enable_mask = BIT(0),
2801		.hw.init = &(const struct clk_init_data) {
2802			.name = "gcc_cfg_noc_usb3_tert_axi_clk",
2803			.parent_hws = (const struct clk_hw*[]) {
2804				&gcc_usb30_tert_master_clk_src.clkr.hw,
2805			},
2806			.num_parents = 1,
2807			.flags = CLK_SET_RATE_PARENT,
2808			.ops = &clk_branch2_ops,
2809		},
2810	},
2811};
2812
2813static struct clk_branch gcc_cfg_noc_usb_anoc_ahb_clk = {
2814	.halt_reg = 0x2d024,
2815	.halt_check = BRANCH_HALT_VOTED,
2816	.hwcg_reg = 0x2d024,
2817	.hwcg_bit = 1,
2818	.clkr = {
2819		.enable_reg = 0x52028,
2820		.enable_mask = BIT(21),
2821		.hw.init = &(const struct clk_init_data) {
2822			.name = "gcc_cfg_noc_usb_anoc_ahb_clk",
2823			.ops = &clk_branch2_ops,
2824		},
2825	},
2826};
2827
2828static struct clk_branch gcc_cfg_noc_usb_anoc_north_ahb_clk = {
2829	.halt_reg = 0x2d028,
2830	.halt_check = BRANCH_HALT_VOTED,
2831	.hwcg_reg = 0x2d028,
2832	.hwcg_bit = 1,
2833	.clkr = {
2834		.enable_reg = 0x52028,
2835		.enable_mask = BIT(23),
2836		.hw.init = &(const struct clk_init_data) {
2837			.name = "gcc_cfg_noc_usb_anoc_north_ahb_clk",
2838			.ops = &clk_branch2_ops,
2839		},
2840	},
2841};
2842
2843static struct clk_branch gcc_cfg_noc_usb_anoc_south_ahb_clk = {
2844	.halt_reg = 0x2d02c,
2845	.halt_check = BRANCH_HALT_VOTED,
2846	.hwcg_reg = 0x2d02c,
2847	.hwcg_bit = 1,
2848	.clkr = {
2849		.enable_reg = 0x52018,
2850		.enable_mask = BIT(7),
2851		.hw.init = &(const struct clk_init_data) {
2852			.name = "gcc_cfg_noc_usb_anoc_south_ahb_clk",
2853			.ops = &clk_branch2_ops,
2854		},
2855	},
2856};
2857
2858static struct clk_branch gcc_cnoc_pcie1_tunnel_clk = {
2859	.halt_reg = 0x2c2b4,
2860	.halt_check = BRANCH_HALT_VOTED,
2861	.clkr = {
2862		.enable_reg = 0x52010,
2863		.enable_mask = BIT(30),
2864		.hw.init = &(const struct clk_init_data) {
2865			.name = "gcc_cnoc_pcie1_tunnel_clk",
2866			.ops = &clk_branch2_ops,
2867		},
2868	},
2869};
2870
2871static struct clk_branch gcc_cnoc_pcie2_tunnel_clk = {
2872	.halt_reg = 0x132b4,
2873	.halt_check = BRANCH_HALT_VOTED,
2874	.clkr = {
2875		.enable_reg = 0x52010,
2876		.enable_mask = BIT(31),
2877		.hw.init = &(const struct clk_init_data) {
2878			.name = "gcc_cnoc_pcie2_tunnel_clk",
2879			.ops = &clk_branch2_ops,
2880		},
2881	},
2882};
2883
2884static struct clk_branch gcc_cnoc_pcie_north_sf_axi_clk = {
2885	.halt_reg = 0x10014,
2886	.halt_check = BRANCH_HALT_VOTED,
2887	.hwcg_reg = 0x10014,
2888	.hwcg_bit = 1,
2889	.clkr = {
2890		.enable_reg = 0x52008,
2891		.enable_mask = BIT(6),
2892		.hw.init = &(const struct clk_init_data) {
2893			.name = "gcc_cnoc_pcie_north_sf_axi_clk",
2894			.ops = &clk_branch2_ops,
2895		},
2896	},
2897};
2898
2899static struct clk_branch gcc_cnoc_pcie_south_sf_axi_clk = {
2900	.halt_reg = 0x10018,
2901	.halt_check = BRANCH_HALT_VOTED,
2902	.hwcg_reg = 0x10018,
2903	.hwcg_bit = 1,
2904	.clkr = {
2905		.enable_reg = 0x52028,
2906		.enable_mask = BIT(12),
2907		.hw.init = &(const struct clk_init_data) {
2908			.name = "gcc_cnoc_pcie_south_sf_axi_clk",
2909			.ops = &clk_branch2_ops,
2910		},
2911	},
2912};
2913
2914static struct clk_branch gcc_cnoc_pcie_tunnel_clk = {
2915	.halt_reg = 0xa02b4,
2916	.halt_check = BRANCH_HALT_VOTED,
2917	.hwcg_reg = 0xa02b4,
2918	.hwcg_bit = 1,
2919	.clkr = {
2920		.enable_reg = 0x52010,
2921		.enable_mask = BIT(29),
2922		.hw.init = &(const struct clk_init_data) {
2923			.name = "gcc_cnoc_pcie_tunnel_clk",
2924			.ops = &clk_branch2_ops,
2925		},
2926	},
2927};
2928
2929static struct clk_branch gcc_ddrss_gpu_axi_clk = {
2930	.halt_reg = 0x7115c,
2931	.halt_check = BRANCH_HALT_SKIP,
2932	.hwcg_reg = 0x7115c,
2933	.hwcg_bit = 1,
2934	.clkr = {
2935		.enable_reg = 0x7115c,
2936		.enable_mask = BIT(0),
2937		.hw.init = &(const struct clk_init_data) {
2938			.name = "gcc_ddrss_gpu_axi_clk",
2939			.ops = &clk_branch2_ops,
2940		},
2941	},
2942};
2943
2944static struct clk_branch gcc_disp_hf_axi_clk = {
2945	.halt_reg = 0x2700c,
2946	.halt_check = BRANCH_HALT_SKIP,
2947	.hwcg_reg = 0x2700c,
2948	.hwcg_bit = 1,
2949	.clkr = {
2950		.enable_reg = 0x2700c,
2951		.enable_mask = BIT(0),
2952		.hw.init = &(const struct clk_init_data) {
2953			.name = "gcc_disp_hf_axi_clk",
2954			.ops = &clk_branch2_ops,
2955		},
2956	},
2957};
2958
2959static struct clk_branch gcc_gp1_clk = {
2960	.halt_reg = 0x64000,
2961	.halt_check = BRANCH_HALT,
2962	.clkr = {
2963		.enable_reg = 0x64000,
2964		.enable_mask = BIT(0),
2965		.hw.init = &(const struct clk_init_data) {
2966			.name = "gcc_gp1_clk",
2967			.parent_hws = (const struct clk_hw*[]) {
2968				&gcc_gp1_clk_src.clkr.hw,
2969			},
2970			.num_parents = 1,
2971			.flags = CLK_SET_RATE_PARENT,
2972			.ops = &clk_branch2_ops,
2973		},
2974	},
2975};
2976
2977static struct clk_branch gcc_gp2_clk = {
2978	.halt_reg = 0x65000,
2979	.halt_check = BRANCH_HALT,
2980	.clkr = {
2981		.enable_reg = 0x65000,
2982		.enable_mask = BIT(0),
2983		.hw.init = &(const struct clk_init_data) {
2984			.name = "gcc_gp2_clk",
2985			.parent_hws = (const struct clk_hw*[]) {
2986				&gcc_gp2_clk_src.clkr.hw,
2987			},
2988			.num_parents = 1,
2989			.flags = CLK_SET_RATE_PARENT,
2990			.ops = &clk_branch2_ops,
2991		},
2992	},
2993};
2994
2995static struct clk_branch gcc_gp3_clk = {
2996	.halt_reg = 0x66000,
2997	.halt_check = BRANCH_HALT,
2998	.clkr = {
2999		.enable_reg = 0x66000,
3000		.enable_mask = BIT(0),
3001		.hw.init = &(const struct clk_init_data) {
3002			.name = "gcc_gp3_clk",
3003			.parent_hws = (const struct clk_hw*[]) {
3004				&gcc_gp3_clk_src.clkr.hw,
3005			},
3006			.num_parents = 1,
3007			.flags = CLK_SET_RATE_PARENT,
3008			.ops = &clk_branch2_ops,
3009		},
3010	},
3011};
3012
3013static struct clk_branch gcc_gpu_gpll0_cph_clk_src = {
3014	.halt_check = BRANCH_HALT_DELAY,
3015	.clkr = {
3016		.enable_reg = 0x52000,
3017		.enable_mask = BIT(15),
3018		.hw.init = &(const struct clk_init_data) {
3019			.name = "gcc_gpu_gpll0_cph_clk_src",
3020			.parent_hws = (const struct clk_hw*[]) {
3021				&gcc_gpll0.clkr.hw,
3022			},
3023			.num_parents = 1,
3024			.flags = CLK_SET_RATE_PARENT,
3025			.ops = &clk_branch2_ops,
3026		},
3027	},
3028};
3029
3030static struct clk_branch gcc_gpu_gpll0_div_cph_clk_src = {
3031	.halt_check = BRANCH_HALT_DELAY,
3032	.clkr = {
3033		.enable_reg = 0x52000,
3034		.enable_mask = BIT(16),
3035		.hw.init = &(const struct clk_init_data) {
3036			.name = "gcc_gpu_gpll0_div_cph_clk_src",
3037			.parent_hws = (const struct clk_hw*[]) {
3038				&gcc_gpll0_out_even.clkr.hw,
3039			},
3040			.num_parents = 1,
3041			.flags = CLK_SET_RATE_PARENT,
3042			.ops = &clk_branch2_ops,
3043		},
3044	},
3045};
3046
3047static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
3048	.halt_reg = 0x71010,
3049	.halt_check = BRANCH_HALT_VOTED,
3050	.hwcg_reg = 0x71010,
3051	.hwcg_bit = 1,
3052	.clkr = {
3053		.enable_reg = 0x71010,
3054		.enable_mask = BIT(0),
3055		.hw.init = &(const struct clk_init_data) {
3056			.name = "gcc_gpu_memnoc_gfx_clk",
3057			.ops = &clk_branch2_ops,
3058		},
3059	},
3060};
3061
3062static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
3063	.halt_reg = 0x71018,
3064	.halt_check = BRANCH_HALT,
3065	.clkr = {
3066		.enable_reg = 0x71018,
3067		.enable_mask = BIT(0),
3068		.hw.init = &(const struct clk_init_data) {
3069			.name = "gcc_gpu_snoc_dvm_gfx_clk",
3070			.ops = &clk_branch2_ops,
3071		},
3072	},
3073};
3074
3075static struct clk_branch gcc_pcie0_phy_rchng_clk = {
3076	.halt_reg = 0xa0050,
3077	.halt_check = BRANCH_HALT_VOTED,
3078	.clkr = {
3079		.enable_reg = 0x52010,
3080		.enable_mask = BIT(26),
3081		.hw.init = &(const struct clk_init_data) {
3082			.name = "gcc_pcie0_phy_rchng_clk",
3083			.parent_hws = (const struct clk_hw*[]) {
3084				&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
3085			},
3086			.num_parents = 1,
3087			.flags = CLK_SET_RATE_PARENT,
3088			.ops = &clk_branch2_ops,
3089		},
3090	},
3091};
3092
3093static struct clk_branch gcc_pcie1_phy_rchng_clk = {
3094	.halt_reg = 0x2c050,
3095	.halt_check = BRANCH_HALT_VOTED,
3096	.clkr = {
3097		.enable_reg = 0x52020,
3098		.enable_mask = BIT(31),
3099		.hw.init = &(const struct clk_init_data) {
3100			.name = "gcc_pcie1_phy_rchng_clk",
3101			.parent_hws = (const struct clk_hw*[]) {
3102				&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
3103			},
3104			.num_parents = 1,
3105			.flags = CLK_SET_RATE_PARENT,
3106			.ops = &clk_branch2_ops,
3107		},
3108	},
3109};
3110
3111static struct clk_branch gcc_pcie2_phy_rchng_clk = {
3112	.halt_reg = 0x13050,
3113	.halt_check = BRANCH_HALT_VOTED,
3114	.clkr = {
3115		.enable_reg = 0x52020,
3116		.enable_mask = BIT(24),
3117		.hw.init = &(const struct clk_init_data) {
3118			.name = "gcc_pcie2_phy_rchng_clk",
3119			.parent_hws = (const struct clk_hw*[]) {
3120				&gcc_pcie_2_phy_rchng_clk_src.clkr.hw,
3121			},
3122			.num_parents = 1,
3123			.flags = CLK_SET_RATE_PARENT,
3124			.ops = &clk_branch2_ops,
3125		},
3126	},
3127};
3128
3129static struct clk_branch gcc_pcie_0_aux_clk = {
3130	.halt_reg = 0xa0038,
3131	.halt_check = BRANCH_HALT_VOTED,
3132	.clkr = {
3133		.enable_reg = 0x52010,
3134		.enable_mask = BIT(24),
3135		.hw.init = &(const struct clk_init_data) {
3136			.name = "gcc_pcie_0_aux_clk",
3137			.parent_hws = (const struct clk_hw*[]) {
3138				&gcc_pcie_0_aux_clk_src.clkr.hw,
3139			},
3140			.num_parents = 1,
3141			.flags = CLK_SET_RATE_PARENT,
3142			.ops = &clk_branch2_ops,
3143		},
3144	},
3145};
3146
3147static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
3148	.halt_reg = 0xa0034,
3149	.halt_check = BRANCH_HALT_VOTED,
3150	.hwcg_reg = 0xa0034,
3151	.hwcg_bit = 1,
3152	.clkr = {
3153		.enable_reg = 0x52010,
3154		.enable_mask = BIT(23),
3155		.hw.init = &(const struct clk_init_data) {
3156			.name = "gcc_pcie_0_cfg_ahb_clk",
3157			.ops = &clk_branch2_ops,
3158		},
3159	},
3160};
3161
3162static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
3163	.halt_reg = 0xa0028,
3164	.halt_check = BRANCH_HALT_SKIP,
3165	.hwcg_reg = 0xa0028,
3166	.hwcg_bit = 1,
3167	.clkr = {
3168		.enable_reg = 0x52010,
3169		.enable_mask = BIT(22),
3170		.hw.init = &(const struct clk_init_data) {
3171			.name = "gcc_pcie_0_mstr_axi_clk",
3172			.ops = &clk_branch2_ops,
3173		},
3174	},
3175};
3176
3177static struct clk_branch gcc_pcie_0_pipe_clk = {
3178	.halt_reg = 0xa0044,
3179	.halt_check = BRANCH_HALT_SKIP,
3180	.clkr = {
3181		.enable_reg = 0x52010,
3182		.enable_mask = BIT(25),
3183		.hw.init = &(const struct clk_init_data) {
3184			.name = "gcc_pcie_0_pipe_clk",
3185			.parent_hws = (const struct clk_hw*[]) {
3186				&gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
3187			},
3188			.num_parents = 1,
3189			.flags = CLK_SET_RATE_PARENT,
3190			.ops = &clk_branch2_ops,
3191		},
3192	},
3193};
3194
3195static struct clk_branch gcc_pcie_0_slv_axi_clk = {
3196	.halt_reg = 0xa001c,
3197	.halt_check = BRANCH_HALT_VOTED,
3198	.hwcg_reg = 0xa001c,
3199	.hwcg_bit = 1,
3200	.clkr = {
3201		.enable_reg = 0x52010,
3202		.enable_mask = BIT(21),
3203		.hw.init = &(const struct clk_init_data) {
3204			.name = "gcc_pcie_0_slv_axi_clk",
3205			.ops = &clk_branch2_ops,
3206		},
3207	},
3208};
3209
3210static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
3211	.halt_reg = 0xa0018,
3212	.halt_check = BRANCH_HALT_VOTED,
3213	.clkr = {
3214		.enable_reg = 0x52010,
3215		.enable_mask = BIT(20),
3216		.hw.init = &(const struct clk_init_data) {
3217			.name = "gcc_pcie_0_slv_q2a_axi_clk",
3218			.ops = &clk_branch2_ops,
3219		},
3220	},
3221};
3222
3223static struct clk_branch gcc_pcie_1_aux_clk = {
3224	.halt_reg = 0x2c038,
3225	.halt_check = BRANCH_HALT_VOTED,
3226	.clkr = {
3227		.enable_reg = 0x52020,
3228		.enable_mask = BIT(29),
3229		.hw.init = &(const struct clk_init_data) {
3230			.name = "gcc_pcie_1_aux_clk",
3231			.parent_hws = (const struct clk_hw*[]) {
3232				&gcc_pcie_1_aux_clk_src.clkr.hw,
3233			},
3234			.num_parents = 1,
3235			.flags = CLK_SET_RATE_PARENT,
3236			.ops = &clk_branch2_ops,
3237		},
3238	},
3239};
3240
3241static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
3242	.halt_reg = 0x2c034,
3243	.halt_check = BRANCH_HALT_VOTED,
3244	.hwcg_reg = 0x2c034,
3245	.hwcg_bit = 1,
3246	.clkr = {
3247		.enable_reg = 0x52020,
3248		.enable_mask = BIT(28),
3249		.hw.init = &(const struct clk_init_data) {
3250			.name = "gcc_pcie_1_cfg_ahb_clk",
3251			.ops = &clk_branch2_ops,
3252		},
3253	},
3254};
3255
3256static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
3257	.halt_reg = 0x2c028,
3258	.halt_check = BRANCH_HALT_SKIP,
3259	.hwcg_reg = 0x2c028,
3260	.hwcg_bit = 1,
3261	.clkr = {
3262		.enable_reg = 0x52020,
3263		.enable_mask = BIT(27),
3264		.hw.init = &(const struct clk_init_data) {
3265			.name = "gcc_pcie_1_mstr_axi_clk",
3266			.ops = &clk_branch2_ops,
3267		},
3268	},
3269};
3270
3271static struct clk_branch gcc_pcie_1_pipe_clk = {
3272	.halt_reg = 0x2c044,
3273	.halt_check = BRANCH_HALT_SKIP,
3274	.clkr = {
3275		.enable_reg = 0x52020,
3276		.enable_mask = BIT(30),
3277		.hw.init = &(const struct clk_init_data) {
3278			.name = "gcc_pcie_1_pipe_clk",
3279			.parent_hws = (const struct clk_hw*[]) {
3280				&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
3281			},
3282			.num_parents = 1,
3283			.flags = CLK_SET_RATE_PARENT,
3284			.ops = &clk_branch2_ops,
3285		},
3286	},
3287};
3288
3289static struct clk_branch gcc_pcie_1_slv_axi_clk = {
3290	.halt_reg = 0x2c01c,
3291	.halt_check = BRANCH_HALT_VOTED,
3292	.hwcg_reg = 0x2c01c,
3293	.hwcg_bit = 1,
3294	.clkr = {
3295		.enable_reg = 0x52020,
3296		.enable_mask = BIT(26),
3297		.hw.init = &(const struct clk_init_data) {
3298			.name = "gcc_pcie_1_slv_axi_clk",
3299			.ops = &clk_branch2_ops,
3300		},
3301	},
3302};
3303
3304static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
3305	.halt_reg = 0x2c018,
3306	.halt_check = BRANCH_HALT_VOTED,
3307	.clkr = {
3308		.enable_reg = 0x52020,
3309		.enable_mask = BIT(25),
3310		.hw.init = &(const struct clk_init_data) {
3311			.name = "gcc_pcie_1_slv_q2a_axi_clk",
3312			.ops = &clk_branch2_ops,
3313		},
3314	},
3315};
3316
3317static struct clk_branch gcc_pcie_2_aux_clk = {
3318	.halt_reg = 0x13038,
3319	.halt_check = BRANCH_HALT_VOTED,
3320	.clkr = {
3321		.enable_reg = 0x52020,
3322		.enable_mask = BIT(22),
3323		.hw.init = &(const struct clk_init_data) {
3324			.name = "gcc_pcie_2_aux_clk",
3325			.parent_hws = (const struct clk_hw*[]) {
3326				&gcc_pcie_2_aux_clk_src.clkr.hw,
3327			},
3328			.num_parents = 1,
3329			.flags = CLK_SET_RATE_PARENT,
3330			.ops = &clk_branch2_ops,
3331		},
3332	},
3333};
3334
3335static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
3336	.halt_reg = 0x13034,
3337	.halt_check = BRANCH_HALT_VOTED,
3338	.hwcg_reg = 0x13034,
3339	.hwcg_bit = 1,
3340	.clkr = {
3341		.enable_reg = 0x52020,
3342		.enable_mask = BIT(21),
3343		.hw.init = &(const struct clk_init_data) {
3344			.name = "gcc_pcie_2_cfg_ahb_clk",
3345			.ops = &clk_branch2_ops,
3346		},
3347	},
3348};
3349
3350static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
3351	.halt_reg = 0x13028,
3352	.halt_check = BRANCH_HALT_SKIP,
3353	.hwcg_reg = 0x13028,
3354	.hwcg_bit = 1,
3355	.clkr = {
3356		.enable_reg = 0x52020,
3357		.enable_mask = BIT(20),
3358		.hw.init = &(const struct clk_init_data) {
3359			.name = "gcc_pcie_2_mstr_axi_clk",
3360			.ops = &clk_branch2_ops,
3361		},
3362	},
3363};
3364
3365static struct clk_branch gcc_pcie_2_pipe_clk = {
3366	.halt_reg = 0x13044,
3367	.halt_check = BRANCH_HALT_SKIP,
3368	.clkr = {
3369		.enable_reg = 0x52020,
3370		.enable_mask = BIT(23),
3371		.hw.init = &(const struct clk_init_data) {
3372			.name = "gcc_pcie_2_pipe_clk",
3373			.parent_hws = (const struct clk_hw*[]) {
3374				&gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
3375			},
3376			.num_parents = 1,
3377			.flags = CLK_SET_RATE_PARENT,
3378			.ops = &clk_branch2_ops,
3379		},
3380	},
3381};
3382
3383static struct clk_branch gcc_pcie_2_slv_axi_clk = {
3384	.halt_reg = 0x1301c,
3385	.halt_check = BRANCH_HALT_VOTED,
3386	.hwcg_reg = 0x1301c,
3387	.hwcg_bit = 1,
3388	.clkr = {
3389		.enable_reg = 0x52020,
3390		.enable_mask = BIT(19),
3391		.hw.init = &(const struct clk_init_data) {
3392			.name = "gcc_pcie_2_slv_axi_clk",
3393			.ops = &clk_branch2_ops,
3394		},
3395	},
3396};
3397
3398static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
3399	.halt_reg = 0x13018,
3400	.halt_check = BRANCH_HALT_VOTED,
3401	.clkr = {
3402		.enable_reg = 0x52020,
3403		.enable_mask = BIT(18),
3404		.hw.init = &(const struct clk_init_data) {
3405			.name = "gcc_pcie_2_slv_q2a_axi_clk",
3406			.ops = &clk_branch2_ops,
3407		},
3408	},
3409};
3410
3411static struct clk_branch gcc_pcie_3_aux_clk = {
3412	.halt_reg = 0x58038,
3413	.halt_check = BRANCH_HALT_VOTED,
3414	.clkr = {
3415		.enable_reg = 0x52020,
3416		.enable_mask = BIT(1),
3417		.hw.init = &(const struct clk_init_data) {
3418			.name = "gcc_pcie_3_aux_clk",
3419			.parent_hws = (const struct clk_hw*[]) {
3420				&gcc_pcie_3_aux_clk_src.clkr.hw,
3421			},
3422			.num_parents = 1,
3423			.flags = CLK_SET_RATE_PARENT,
3424			.ops = &clk_branch2_ops,
3425		},
3426	},
3427};
3428
3429static struct clk_branch gcc_pcie_3_cfg_ahb_clk = {
3430	.halt_reg = 0x58034,
3431	.halt_check = BRANCH_HALT_VOTED,
3432	.hwcg_reg = 0x58034,
3433	.hwcg_bit = 1,
3434	.clkr = {
3435		.enable_reg = 0x52020,
3436		.enable_mask = BIT(0),
3437		.hw.init = &(const struct clk_init_data) {
3438			.name = "gcc_pcie_3_cfg_ahb_clk",
3439			.ops = &clk_branch2_ops,
3440		},
3441	},
3442};
3443
3444static struct clk_branch gcc_pcie_3_mstr_axi_clk = {
3445	.halt_reg = 0x58028,
3446	.halt_check = BRANCH_HALT_SKIP,
3447	.hwcg_reg = 0x58028,
3448	.hwcg_bit = 1,
3449	.clkr = {
3450		.enable_reg = 0x52018,
3451		.enable_mask = BIT(31),
3452		.hw.init = &(const struct clk_init_data) {
3453			.name = "gcc_pcie_3_mstr_axi_clk",
3454			.ops = &clk_branch2_ops,
3455		},
3456	},
3457};
3458
3459static struct clk_branch gcc_pcie_3_phy_aux_clk = {
3460	.halt_reg = 0x58044,
3461	.halt_check = BRANCH_HALT_VOTED,
3462	.clkr = {
3463		.enable_reg = 0x52020,
3464		.enable_mask = BIT(2),
3465		.hw.init = &(const struct clk_init_data) {
3466			.name = "gcc_pcie_3_phy_aux_clk",
3467			.ops = &clk_branch2_ops,
3468		},
3469	},
3470};
3471
3472static struct clk_branch gcc_pcie_3_phy_rchng_clk = {
3473	.halt_reg = 0x5805c,
3474	.halt_check = BRANCH_HALT_VOTED,
3475	.clkr = {
3476		.enable_reg = 0x52020,
3477		.enable_mask = BIT(4),
3478		.hw.init = &(const struct clk_init_data) {
3479			.name = "gcc_pcie_3_phy_rchng_clk",
3480			.parent_hws = (const struct clk_hw*[]) {
3481				&gcc_pcie_3_phy_rchng_clk_src.clkr.hw,
3482			},
3483			.num_parents = 1,
3484			.flags = CLK_SET_RATE_PARENT,
3485			.ops = &clk_branch2_ops,
3486		},
3487	},
3488};
3489
3490static struct clk_branch gcc_pcie_3_pipe_clk = {
3491	.halt_reg = 0x58050,
3492	.halt_check = BRANCH_HALT_SKIP,
3493	.clkr = {
3494		.enable_reg = 0x52020,
3495		.enable_mask = BIT(3),
3496		.hw.init = &(const struct clk_init_data) {
3497			.name = "gcc_pcie_3_pipe_clk",
3498			.ops = &clk_branch2_ops,
3499		},
3500	},
3501};
3502
3503static struct clk_branch gcc_pcie_3_pipediv2_clk = {
3504	.halt_reg = 0x58060,
3505	.halt_check = BRANCH_HALT_SKIP,
3506	.clkr = {
3507		.enable_reg = 0x52020,
3508		.enable_mask = BIT(5),
3509		.hw.init = &(const struct clk_init_data) {
3510			.name = "gcc_pcie_3_pipediv2_clk",
3511			.parent_hws = (const struct clk_hw*[]) {
3512				&gcc_pcie_3_pipe_div_clk_src.clkr.hw,
3513			},
3514			.num_parents = 1,
3515			.flags = CLK_SET_RATE_PARENT,
3516			.ops = &clk_branch2_ops,
3517		},
3518	},
3519};
3520
3521static struct clk_branch gcc_pcie_3_slv_axi_clk = {
3522	.halt_reg = 0x5801c,
3523	.halt_check = BRANCH_HALT_VOTED,
3524	.hwcg_reg = 0x5801c,
3525	.hwcg_bit = 1,
3526	.clkr = {
3527		.enable_reg = 0x52018,
3528		.enable_mask = BIT(30),
3529		.hw.init = &(const struct clk_init_data) {
3530			.name = "gcc_pcie_3_slv_axi_clk",
3531			.ops = &clk_branch2_ops,
3532		},
3533	},
3534};
3535
3536static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk = {
3537	.halt_reg = 0x58018,
3538	.halt_check = BRANCH_HALT_VOTED,
3539	.clkr = {
3540		.enable_reg = 0x52018,
3541		.enable_mask = BIT(29),
3542		.hw.init = &(const struct clk_init_data) {
3543			.name = "gcc_pcie_3_slv_q2a_axi_clk",
3544			.ops = &clk_branch2_ops,
3545		},
3546	},
3547};
3548
3549static struct clk_branch gcc_pcie_4_aux_clk = {
3550	.halt_reg = 0x6b038,
3551	.halt_check = BRANCH_HALT_VOTED,
3552	.clkr = {
3553		.enable_reg = 0x52008,
3554		.enable_mask = BIT(3),
3555		.hw.init = &(const struct clk_init_data) {
3556			.name = "gcc_pcie_4_aux_clk",
3557			.parent_hws = (const struct clk_hw*[]) {
3558				&gcc_pcie_4_aux_clk_src.clkr.hw,
3559			},
3560			.num_parents = 1,
3561			.flags = CLK_SET_RATE_PARENT,
3562			.ops = &clk_branch2_ops,
3563		},
3564	},
3565};
3566
3567static struct clk_branch gcc_pcie_4_cfg_ahb_clk = {
3568	.halt_reg = 0x6b034,
3569	.halt_check = BRANCH_HALT_VOTED,
3570	.hwcg_reg = 0x6b034,
3571	.hwcg_bit = 1,
3572	.clkr = {
3573		.enable_reg = 0x52008,
3574		.enable_mask = BIT(2),
3575		.hw.init = &(const struct clk_init_data) {
3576			.name = "gcc_pcie_4_cfg_ahb_clk",
3577			.ops = &clk_branch2_ops,
3578		},
3579	},
3580};
3581
3582static struct clk_branch gcc_pcie_4_mstr_axi_clk = {
3583	.halt_reg = 0x6b028,
3584	.halt_check = BRANCH_HALT_SKIP,
3585	.hwcg_reg = 0x6b028,
3586	.hwcg_bit = 1,
3587	.clkr = {
3588		.enable_reg = 0x52008,
3589		.enable_mask = BIT(1),
3590		.hw.init = &(const struct clk_init_data) {
3591			.name = "gcc_pcie_4_mstr_axi_clk",
3592			.ops = &clk_branch2_ops,
3593		},
3594	},
3595};
3596
3597static struct clk_branch gcc_pcie_4_phy_rchng_clk = {
3598	.halt_reg = 0x6b050,
3599	.halt_check = BRANCH_HALT_VOTED,
3600	.clkr = {
3601		.enable_reg = 0x52000,
3602		.enable_mask = BIT(22),
3603		.hw.init = &(const struct clk_init_data) {
3604			.name = "gcc_pcie_4_phy_rchng_clk",
3605			.parent_hws = (const struct clk_hw*[]) {
3606				&gcc_pcie_4_phy_rchng_clk_src.clkr.hw,
3607			},
3608			.num_parents = 1,
3609			.flags = CLK_SET_RATE_PARENT,
3610			.ops = &clk_branch2_ops,
3611		},
3612	},
3613};
3614
3615static struct clk_branch gcc_pcie_4_pipe_clk = {
3616	.halt_reg = 0x6b044,
3617	.halt_check = BRANCH_HALT_SKIP,
3618	.clkr = {
3619		.enable_reg = 0x52008,
3620		.enable_mask = BIT(4),
3621		.hw.init = &(const struct clk_init_data) {
3622			.name = "gcc_pcie_4_pipe_clk",
3623			.ops = &clk_branch2_ops,
3624		},
3625	},
3626};
3627
3628static struct clk_branch gcc_pcie_4_pipediv2_clk = {
3629	.halt_reg = 0x6b054,
3630	.halt_check = BRANCH_HALT_SKIP,
3631	.clkr = {
3632		.enable_reg = 0x52010,
3633		.enable_mask = BIT(27),
3634		.hw.init = &(const struct clk_init_data) {
3635			.name = "gcc_pcie_4_pipediv2_clk",
3636			.parent_hws = (const struct clk_hw*[]) {
3637				&gcc_pcie_4_pipe_div_clk_src.clkr.hw,
3638			},
3639			.num_parents = 1,
3640			.flags = CLK_SET_RATE_PARENT,
3641			.ops = &clk_branch2_ops,
3642		},
3643	},
3644};
3645
3646static struct clk_branch gcc_pcie_4_slv_axi_clk = {
3647	.halt_reg = 0x6b01c,
3648	.halt_check = BRANCH_HALT_VOTED,
3649	.hwcg_reg = 0x6b01c,
3650	.hwcg_bit = 1,
3651	.clkr = {
3652		.enable_reg = 0x52008,
3653		.enable_mask = BIT(0),
3654		.hw.init = &(const struct clk_init_data) {
3655			.name = "gcc_pcie_4_slv_axi_clk",
3656			.ops = &clk_branch2_ops,
3657		},
3658	},
3659};
3660
3661static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = {
3662	.halt_reg = 0x6b018,
3663	.halt_check = BRANCH_HALT_VOTED,
3664	.clkr = {
3665		.enable_reg = 0x52008,
3666		.enable_mask = BIT(5),
3667		.hw.init = &(const struct clk_init_data) {
3668			.name = "gcc_pcie_4_slv_q2a_axi_clk",
3669			.ops = &clk_branch2_ops,
3670		},
3671	},
3672};
3673
3674static struct clk_branch gcc_pcie_5_aux_clk = {
3675	.halt_reg = 0x2f038,
3676	.halt_check = BRANCH_HALT_VOTED,
3677	.clkr = {
3678		.enable_reg = 0x52018,
3679		.enable_mask = BIT(16),
3680		.hw.init = &(const struct clk_init_data) {
3681			.name = "gcc_pcie_5_aux_clk",
3682			.parent_hws = (const struct clk_hw*[]) {
3683				&gcc_pcie_5_aux_clk_src.clkr.hw,
3684			},
3685			.num_parents = 1,
3686			.flags = CLK_SET_RATE_PARENT,
3687			.ops = &clk_branch2_ops,
3688		},
3689	},
3690};
3691
3692static struct clk_branch gcc_pcie_5_cfg_ahb_clk = {
3693	.halt_reg = 0x2f034,
3694	.halt_check = BRANCH_HALT_VOTED,
3695	.hwcg_reg = 0x2f034,
3696	.hwcg_bit = 1,
3697	.clkr = {
3698		.enable_reg = 0x52018,
3699		.enable_mask = BIT(15),
3700		.hw.init = &(const struct clk_init_data) {
3701			.name = "gcc_pcie_5_cfg_ahb_clk",
3702			.ops = &clk_branch2_ops,
3703		},
3704	},
3705};
3706
3707static struct clk_branch gcc_pcie_5_mstr_axi_clk = {
3708	.halt_reg = 0x2f028,
3709	.halt_check = BRANCH_HALT_SKIP,
3710	.hwcg_reg = 0x2f028,
3711	.hwcg_bit = 1,
3712	.clkr = {
3713		.enable_reg = 0x52018,
3714		.enable_mask = BIT(14),
3715		.hw.init = &(const struct clk_init_data) {
3716			.name = "gcc_pcie_5_mstr_axi_clk",
3717			.ops = &clk_branch2_ops,
3718		},
3719	},
3720};
3721
3722static struct clk_branch gcc_pcie_5_phy_rchng_clk = {
3723	.halt_reg = 0x2f050,
3724	.halt_check = BRANCH_HALT_VOTED,
3725	.clkr = {
3726		.enable_reg = 0x52018,
3727		.enable_mask = BIT(18),
3728		.hw.init = &(const struct clk_init_data) {
3729			.name = "gcc_pcie_5_phy_rchng_clk",
3730			.parent_hws = (const struct clk_hw*[]) {
3731				&gcc_pcie_5_phy_rchng_clk_src.clkr.hw,
3732			},
3733			.num_parents = 1,
3734			.flags = CLK_SET_RATE_PARENT,
3735			.ops = &clk_branch2_ops,
3736		},
3737	},
3738};
3739
3740static struct clk_branch gcc_pcie_5_pipe_clk = {
3741	.halt_reg = 0x2f044,
3742	.halt_check = BRANCH_HALT_SKIP,
3743	.clkr = {
3744		.enable_reg = 0x52018,
3745		.enable_mask = BIT(17),
3746		.hw.init = &(const struct clk_init_data) {
3747			.name = "gcc_pcie_5_pipe_clk",
3748			.ops = &clk_branch2_ops,
3749		},
3750	},
3751};
3752
3753static struct clk_branch gcc_pcie_5_pipediv2_clk = {
3754	.halt_reg = 0x2f054,
3755	.halt_check = BRANCH_HALT_SKIP,
3756	.clkr = {
3757		.enable_reg = 0x52018,
3758		.enable_mask = BIT(19),
3759		.hw.init = &(const struct clk_init_data) {
3760			.name = "gcc_pcie_5_pipediv2_clk",
3761			.parent_hws = (const struct clk_hw*[]) {
3762				&gcc_pcie_5_pipe_div_clk_src.clkr.hw,
3763			},
3764			.num_parents = 1,
3765			.flags = CLK_SET_RATE_PARENT,
3766			.ops = &clk_branch2_ops,
3767		},
3768	},
3769};
3770
3771static struct clk_branch gcc_pcie_5_slv_axi_clk = {
3772	.halt_reg = 0x2f01c,
3773	.halt_check = BRANCH_HALT_VOTED,
3774	.hwcg_reg = 0x2f01c,
3775	.hwcg_bit = 1,
3776	.clkr = {
3777		.enable_reg = 0x52018,
3778		.enable_mask = BIT(13),
3779		.hw.init = &(const struct clk_init_data) {
3780			.name = "gcc_pcie_5_slv_axi_clk",
3781			.ops = &clk_branch2_ops,
3782		},
3783	},
3784};
3785
3786static struct clk_branch gcc_pcie_5_slv_q2a_axi_clk = {
3787	.halt_reg = 0x2f018,
3788	.halt_check = BRANCH_HALT_VOTED,
3789	.clkr = {
3790		.enable_reg = 0x52018,
3791		.enable_mask = BIT(12),
3792		.hw.init = &(const struct clk_init_data) {
3793			.name = "gcc_pcie_5_slv_q2a_axi_clk",
3794			.ops = &clk_branch2_ops,
3795		},
3796	},
3797};
3798
3799static struct clk_branch gcc_pcie_6a_aux_clk = {
3800	.halt_reg = 0x31038,
3801	.halt_check = BRANCH_HALT_VOTED,
3802	.clkr = {
3803		.enable_reg = 0x52018,
3804		.enable_mask = BIT(24),
3805		.hw.init = &(const struct clk_init_data) {
3806			.name = "gcc_pcie_6a_aux_clk",
3807			.parent_hws = (const struct clk_hw*[]) {
3808				&gcc_pcie_6a_aux_clk_src.clkr.hw,
3809			},
3810			.num_parents = 1,
3811			.flags = CLK_SET_RATE_PARENT,
3812			.ops = &clk_branch2_ops,
3813		},
3814	},
3815};
3816
3817static struct clk_branch gcc_pcie_6a_cfg_ahb_clk = {
3818	.halt_reg = 0x31034,
3819	.halt_check = BRANCH_HALT_VOTED,
3820	.hwcg_reg = 0x31034,
3821	.hwcg_bit = 1,
3822	.clkr = {
3823		.enable_reg = 0x52018,
3824		.enable_mask = BIT(23),
3825		.hw.init = &(const struct clk_init_data) {
3826			.name = "gcc_pcie_6a_cfg_ahb_clk",
3827			.ops = &clk_branch2_ops,
3828		},
3829	},
3830};
3831
3832static struct clk_branch gcc_pcie_6a_mstr_axi_clk = {
3833	.halt_reg = 0x31028,
3834	.halt_check = BRANCH_HALT_SKIP,
3835	.hwcg_reg = 0x31028,
3836	.hwcg_bit = 1,
3837	.clkr = {
3838		.enable_reg = 0x52018,
3839		.enable_mask = BIT(22),
3840		.hw.init = &(const struct clk_init_data) {
3841			.name = "gcc_pcie_6a_mstr_axi_clk",
3842			.ops = &clk_branch2_ops,
3843		},
3844	},
3845};
3846
3847static struct clk_branch gcc_pcie_6a_phy_aux_clk = {
3848	.halt_reg = 0x31044,
3849	.halt_check = BRANCH_HALT_VOTED,
3850	.clkr = {
3851		.enable_reg = 0x52018,
3852		.enable_mask = BIT(25),
3853		.hw.init = &(const struct clk_init_data) {
3854			.name = "gcc_pcie_6a_phy_aux_clk",
3855			.ops = &clk_branch2_ops,
3856		},
3857	},
3858};
3859
3860static struct clk_branch gcc_pcie_6a_phy_rchng_clk = {
3861	.halt_reg = 0x3105c,
3862	.halt_check = BRANCH_HALT_VOTED,
3863	.clkr = {
3864		.enable_reg = 0x52018,
3865		.enable_mask = BIT(27),
3866		.hw.init = &(const struct clk_init_data) {
3867			.name = "gcc_pcie_6a_phy_rchng_clk",
3868			.parent_hws = (const struct clk_hw*[]) {
3869				&gcc_pcie_6a_phy_rchng_clk_src.clkr.hw,
3870			},
3871			.num_parents = 1,
3872			.flags = CLK_SET_RATE_PARENT,
3873			.ops = &clk_branch2_ops,
3874		},
3875	},
3876};
3877
3878static struct clk_branch gcc_pcie_6a_pipe_clk = {
3879	.halt_reg = 0x31050,
3880	.halt_check = BRANCH_HALT_SKIP,
3881	.clkr = {
3882		.enable_reg = 0x52018,
3883		.enable_mask = BIT(26),
3884		.hw.init = &(const struct clk_init_data) {
3885			.name = "gcc_pcie_6a_pipe_clk",
3886			.ops = &clk_branch2_ops,
3887		},
3888	},
3889};
3890
3891static struct clk_branch gcc_pcie_6a_pipediv2_clk = {
3892	.halt_reg = 0x31060,
3893	.halt_check = BRANCH_HALT_SKIP,
3894	.clkr = {
3895		.enable_reg = 0x52018,
3896		.enable_mask = BIT(28),
3897		.hw.init = &(const struct clk_init_data) {
3898			.name = "gcc_pcie_6a_pipediv2_clk",
3899			.parent_hws = (const struct clk_hw*[]) {
3900				&gcc_pcie_6a_pipe_div_clk_src.clkr.hw,
3901			},
3902			.num_parents = 1,
3903			.flags = CLK_SET_RATE_PARENT,
3904			.ops = &clk_branch2_ops,
3905		},
3906	},
3907};
3908
3909static struct clk_branch gcc_pcie_6a_slv_axi_clk = {
3910	.halt_reg = 0x3101c,
3911	.halt_check = BRANCH_HALT_VOTED,
3912	.hwcg_reg = 0x3101c,
3913	.hwcg_bit = 1,
3914	.clkr = {
3915		.enable_reg = 0x52018,
3916		.enable_mask = BIT(21),
3917		.hw.init = &(const struct clk_init_data) {
3918			.name = "gcc_pcie_6a_slv_axi_clk",
3919			.ops = &clk_branch2_ops,
3920		},
3921	},
3922};
3923
3924static struct clk_branch gcc_pcie_6a_slv_q2a_axi_clk = {
3925	.halt_reg = 0x31018,
3926	.halt_check = BRANCH_HALT_VOTED,
3927	.clkr = {
3928		.enable_reg = 0x52018,
3929		.enable_mask = BIT(20),
3930		.hw.init = &(const struct clk_init_data) {
3931			.name = "gcc_pcie_6a_slv_q2a_axi_clk",
3932			.ops = &clk_branch2_ops,
3933		},
3934	},
3935};
3936
3937static struct clk_branch gcc_pcie_6b_aux_clk = {
3938	.halt_reg = 0x8d038,
3939	.halt_check = BRANCH_HALT_VOTED,
3940	.clkr = {
3941		.enable_reg = 0x52000,
3942		.enable_mask = BIT(29),
3943		.hw.init = &(const struct clk_init_data) {
3944			.name = "gcc_pcie_6b_aux_clk",
3945			.parent_hws = (const struct clk_hw*[]) {
3946				&gcc_pcie_6b_aux_clk_src.clkr.hw,
3947			},
3948			.num_parents = 1,
3949			.flags = CLK_SET_RATE_PARENT,
3950			.ops = &clk_branch2_ops,
3951		},
3952	},
3953};
3954
3955static struct clk_branch gcc_pcie_6b_cfg_ahb_clk = {
3956	.halt_reg = 0x8d034,
3957	.halt_check = BRANCH_HALT_VOTED,
3958	.hwcg_reg = 0x8d034,
3959	.hwcg_bit = 1,
3960	.clkr = {
3961		.enable_reg = 0x52000,
3962		.enable_mask = BIT(28),
3963		.hw.init = &(const struct clk_init_data) {
3964			.name = "gcc_pcie_6b_cfg_ahb_clk",
3965			.ops = &clk_branch2_ops,
3966		},
3967	},
3968};
3969
3970static struct clk_branch gcc_pcie_6b_mstr_axi_clk = {
3971	.halt_reg = 0x8d028,
3972	.halt_check = BRANCH_HALT_SKIP,
3973	.hwcg_reg = 0x8d028,
3974	.hwcg_bit = 1,
3975	.clkr = {
3976		.enable_reg = 0x52000,
3977		.enable_mask = BIT(27),
3978		.hw.init = &(const struct clk_init_data) {
3979			.name = "gcc_pcie_6b_mstr_axi_clk",
3980			.ops = &clk_branch2_ops,
3981		},
3982	},
3983};
3984
3985static struct clk_branch gcc_pcie_6b_phy_aux_clk = {
3986	.halt_reg = 0x8d044,
3987	.halt_check = BRANCH_HALT_VOTED,
3988	.clkr = {
3989		.enable_reg = 0x52000,
3990		.enable_mask = BIT(24),
3991		.hw.init = &(const struct clk_init_data) {
3992			.name = "gcc_pcie_6b_phy_aux_clk",
3993			.ops = &clk_branch2_ops,
3994		},
3995	},
3996};
3997
3998static struct clk_branch gcc_pcie_6b_phy_rchng_clk = {
3999	.halt_reg = 0x8d05c,
4000	.halt_check = BRANCH_HALT_VOTED,
4001	.clkr = {
4002		.enable_reg = 0x52000,
4003		.enable_mask = BIT(23),
4004		.hw.init = &(const struct clk_init_data) {
4005			.name = "gcc_pcie_6b_phy_rchng_clk",
4006			.parent_hws = (const struct clk_hw*[]) {
4007				&gcc_pcie_6b_phy_rchng_clk_src.clkr.hw,
4008			},
4009			.num_parents = 1,
4010			.flags = CLK_SET_RATE_PARENT,
4011			.ops = &clk_branch2_ops,
4012		},
4013	},
4014};
4015
4016static struct clk_branch gcc_pcie_6b_pipe_clk = {
4017	.halt_reg = 0x8d050,
4018	.halt_check = BRANCH_HALT_SKIP,
4019	.clkr = {
4020		.enable_reg = 0x52000,
4021		.enable_mask = BIT(30),
4022		.hw.init = &(const struct clk_init_data) {
4023			.name = "gcc_pcie_6b_pipe_clk",
4024			.ops = &clk_branch2_ops,
4025		},
4026	},
4027};
4028
4029static struct clk_branch gcc_pcie_6b_pipediv2_clk = {
4030	.halt_reg = 0x8d060,
4031	.halt_check = BRANCH_HALT_SKIP,
4032	.clkr = {
4033		.enable_reg = 0x52010,
4034		.enable_mask = BIT(28),
4035		.hw.init = &(const struct clk_init_data) {
4036			.name = "gcc_pcie_6b_pipediv2_clk",
4037			.parent_hws = (const struct clk_hw*[]) {
4038				&gcc_pcie_6b_pipe_div_clk_src.clkr.hw,
4039			},
4040			.num_parents = 1,
4041			.flags = CLK_SET_RATE_PARENT,
4042			.ops = &clk_branch2_ops,
4043		},
4044	},
4045};
4046
4047static struct clk_branch gcc_pcie_6b_slv_axi_clk = {
4048	.halt_reg = 0x8d01c,
4049	.halt_check = BRANCH_HALT_VOTED,
4050	.hwcg_reg = 0x8d01c,
4051	.hwcg_bit = 1,
4052	.clkr = {
4053		.enable_reg = 0x52000,
4054		.enable_mask = BIT(26),
4055		.hw.init = &(const struct clk_init_data) {
4056			.name = "gcc_pcie_6b_slv_axi_clk",
4057			.ops = &clk_branch2_ops,
4058		},
4059	},
4060};
4061
4062static struct clk_branch gcc_pcie_6b_slv_q2a_axi_clk = {
4063	.halt_reg = 0x8d018,
4064	.halt_check = BRANCH_HALT_VOTED,
4065	.clkr = {
4066		.enable_reg = 0x52000,
4067		.enable_mask = BIT(25),
4068		.hw.init = &(const struct clk_init_data) {
4069			.name = "gcc_pcie_6b_slv_q2a_axi_clk",
4070			.ops = &clk_branch2_ops,
4071		},
4072	},
4073};
4074
4075static struct clk_branch gcc_pcie_rscc_ahb_clk = {
4076	.halt_reg = 0xa4008,
4077	.halt_check = BRANCH_HALT_VOTED,
4078	.hwcg_reg = 0xa4008,
4079	.hwcg_bit = 1,
4080	.clkr = {
4081		.enable_reg = 0x52028,
4082		.enable_mask = BIT(18),
4083		.hw.init = &(const struct clk_init_data) {
4084			.name = "gcc_pcie_rscc_ahb_clk",
4085			.ops = &clk_branch2_ops,
4086		},
4087	},
4088};
4089
4090static struct clk_branch gcc_pcie_rscc_xo_clk = {
4091	.halt_reg = 0xa4004,
4092	.halt_check = BRANCH_HALT_VOTED,
4093	.clkr = {
4094		.enable_reg = 0x52028,
4095		.enable_mask = BIT(17),
4096		.hw.init = &(const struct clk_init_data) {
4097			.name = "gcc_pcie_rscc_xo_clk",
4098			.parent_hws = (const struct clk_hw*[]) {
4099				&gcc_pcie_rscc_xo_clk_src.clkr.hw,
4100			},
4101			.num_parents = 1,
4102			.flags = CLK_SET_RATE_PARENT,
4103			.ops = &clk_branch2_ops,
4104		},
4105	},
4106};
4107
4108static struct clk_branch gcc_pdm2_clk = {
4109	.halt_reg = 0x3300c,
4110	.halt_check = BRANCH_HALT,
4111	.clkr = {
4112		.enable_reg = 0x3300c,
4113		.enable_mask = BIT(0),
4114		.hw.init = &(const struct clk_init_data) {
4115			.name = "gcc_pdm2_clk",
4116			.parent_hws = (const struct clk_hw*[]) {
4117				&gcc_pdm2_clk_src.clkr.hw,
4118			},
4119			.num_parents = 1,
4120			.flags = CLK_SET_RATE_PARENT,
4121			.ops = &clk_branch2_ops,
4122		},
4123	},
4124};
4125
4126static struct clk_branch gcc_pdm_ahb_clk = {
4127	.halt_reg = 0x33004,
4128	.halt_check = BRANCH_HALT_VOTED,
4129	.hwcg_reg = 0x33004,
4130	.hwcg_bit = 1,
4131	.clkr = {
4132		.enable_reg = 0x33004,
4133		.enable_mask = BIT(0),
4134		.hw.init = &(const struct clk_init_data) {
4135			.name = "gcc_pdm_ahb_clk",
4136			.ops = &clk_branch2_ops,
4137		},
4138	},
4139};
4140
4141static struct clk_branch gcc_pdm_xo4_clk = {
4142	.halt_reg = 0x33008,
4143	.halt_check = BRANCH_HALT,
4144	.clkr = {
4145		.enable_reg = 0x33008,
4146		.enable_mask = BIT(0),
4147		.hw.init = &(const struct clk_init_data) {
4148			.name = "gcc_pdm_xo4_clk",
4149			.ops = &clk_branch2_ops,
4150		},
4151	},
4152};
4153
4154static struct clk_branch gcc_qmip_av1e_ahb_clk = {
4155	.halt_reg = 0x4a018,
4156	.halt_check = BRANCH_HALT_VOTED,
4157	.hwcg_reg = 0x4a018,
4158	.hwcg_bit = 1,
4159	.clkr = {
4160		.enable_reg = 0x4a018,
4161		.enable_mask = BIT(0),
4162		.hw.init = &(const struct clk_init_data) {
4163			.name = "gcc_qmip_av1e_ahb_clk",
4164			.ops = &clk_branch2_ops,
4165		},
4166	},
4167};
4168
4169static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
4170	.halt_reg = 0x26008,
4171	.halt_check = BRANCH_HALT_VOTED,
4172	.hwcg_reg = 0x26008,
4173	.hwcg_bit = 1,
4174	.clkr = {
4175		.enable_reg = 0x26008,
4176		.enable_mask = BIT(0),
4177		.hw.init = &(const struct clk_init_data) {
4178			.name = "gcc_qmip_camera_nrt_ahb_clk",
4179			.ops = &clk_branch2_ops,
4180		},
4181	},
4182};
4183
4184static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
4185	.halt_reg = 0x2600c,
4186	.halt_check = BRANCH_HALT_VOTED,
4187	.hwcg_reg = 0x2600c,
4188	.hwcg_bit = 1,
4189	.clkr = {
4190		.enable_reg = 0x2600c,
4191		.enable_mask = BIT(0),
4192		.hw.init = &(const struct clk_init_data) {
4193			.name = "gcc_qmip_camera_rt_ahb_clk",
4194			.ops = &clk_branch2_ops,
4195		},
4196	},
4197};
4198
4199static struct clk_branch gcc_qmip_disp_ahb_clk = {
4200	.halt_reg = 0x27008,
4201	.halt_check = BRANCH_HALT_VOTED,
4202	.hwcg_reg = 0x27008,
4203	.hwcg_bit = 1,
4204	.clkr = {
4205		.enable_reg = 0x27008,
4206		.enable_mask = BIT(0),
4207		.hw.init = &(const struct clk_init_data) {
4208			.name = "gcc_qmip_disp_ahb_clk",
4209			.ops = &clk_branch2_ops,
4210		},
4211	},
4212};
4213
4214static struct clk_branch gcc_qmip_gpu_ahb_clk = {
4215	.halt_reg = 0x71008,
4216	.halt_check = BRANCH_HALT_VOTED,
4217	.hwcg_reg = 0x71008,
4218	.hwcg_bit = 1,
4219	.clkr = {
4220		.enable_reg = 0x71008,
4221		.enable_mask = BIT(0),
4222		.hw.init = &(const struct clk_init_data) {
4223			.name = "gcc_qmip_gpu_ahb_clk",
4224			.ops = &clk_branch2_ops,
4225		},
4226	},
4227};
4228
4229static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
4230	.halt_reg = 0x32014,
4231	.halt_check = BRANCH_HALT_VOTED,
4232	.hwcg_reg = 0x32014,
4233	.hwcg_bit = 1,
4234	.clkr = {
4235		.enable_reg = 0x32014,
4236		.enable_mask = BIT(0),
4237		.hw.init = &(const struct clk_init_data) {
4238			.name = "gcc_qmip_video_cv_cpu_ahb_clk",
4239			.ops = &clk_branch2_ops,
4240		},
4241	},
4242};
4243
4244static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
4245	.halt_reg = 0x32008,
4246	.halt_check = BRANCH_HALT_VOTED,
4247	.hwcg_reg = 0x32008,
4248	.hwcg_bit = 1,
4249	.clkr = {
4250		.enable_reg = 0x32008,
4251		.enable_mask = BIT(0),
4252		.hw.init = &(const struct clk_init_data) {
4253			.name = "gcc_qmip_video_cvp_ahb_clk",
4254			.ops = &clk_branch2_ops,
4255		},
4256	},
4257};
4258
4259static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
4260	.halt_reg = 0x32010,
4261	.halt_check = BRANCH_HALT_VOTED,
4262	.hwcg_reg = 0x32010,
4263	.hwcg_bit = 1,
4264	.clkr = {
4265		.enable_reg = 0x32010,
4266		.enable_mask = BIT(0),
4267		.hw.init = &(const struct clk_init_data) {
4268			.name = "gcc_qmip_video_v_cpu_ahb_clk",
4269			.ops = &clk_branch2_ops,
4270		},
4271	},
4272};
4273
4274static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
4275	.halt_reg = 0x3200c,
4276	.halt_check = BRANCH_HALT_VOTED,
4277	.hwcg_reg = 0x3200c,
4278	.hwcg_bit = 1,
4279	.clkr = {
4280		.enable_reg = 0x3200c,
4281		.enable_mask = BIT(0),
4282		.hw.init = &(const struct clk_init_data) {
4283			.name = "gcc_qmip_video_vcodec_ahb_clk",
4284			.ops = &clk_branch2_ops,
4285		},
4286	},
4287};
4288
4289static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
4290	.halt_reg = 0x23018,
4291	.halt_check = BRANCH_HALT_VOTED,
4292	.clkr = {
4293		.enable_reg = 0x52020,
4294		.enable_mask = BIT(9),
4295		.hw.init = &(const struct clk_init_data) {
4296			.name = "gcc_qupv3_wrap0_core_2x_clk",
4297			.ops = &clk_branch2_ops,
4298		},
4299	},
4300};
4301
4302static struct clk_branch gcc_qupv3_wrap0_core_clk = {
4303	.halt_reg = 0x23008,
4304	.halt_check = BRANCH_HALT_VOTED,
4305	.clkr = {
4306		.enable_reg = 0x52020,
4307		.enable_mask = BIT(8),
4308		.hw.init = &(const struct clk_init_data) {
4309			.name = "gcc_qupv3_wrap0_core_clk",
4310			.ops = &clk_branch2_ops,
4311		},
4312	},
4313};
4314
4315static struct clk_branch gcc_qupv3_wrap0_qspi_s2_clk = {
4316	.halt_reg = 0x42280,
4317	.halt_check = BRANCH_HALT_VOTED,
4318	.clkr = {
4319		.enable_reg = 0x52028,
4320		.enable_mask = BIT(2),
4321		.hw.init = &(const struct clk_init_data) {
4322			.name = "gcc_qupv3_wrap0_qspi_s2_clk",
4323			.parent_hws = (const struct clk_hw*[]) {
4324				&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
4325			},
4326			.num_parents = 1,
4327			.flags = CLK_SET_RATE_PARENT,
4328			.ops = &clk_branch2_ops,
4329		},
4330	},
4331};
4332
4333static struct clk_branch gcc_qupv3_wrap0_qspi_s3_clk = {
4334	.halt_reg = 0x423c0,
4335	.halt_check = BRANCH_HALT_VOTED,
4336	.clkr = {
4337		.enable_reg = 0x52028,
4338		.enable_mask = BIT(3),
4339		.hw.init = &(const struct clk_init_data) {
4340			.name = "gcc_qupv3_wrap0_qspi_s3_clk",
4341			.parent_hws = (const struct clk_hw*[]) {
4342				&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
4343			},
4344			.num_parents = 1,
4345			.flags = CLK_SET_RATE_PARENT,
4346			.ops = &clk_branch2_ops,
4347		},
4348	},
4349};
4350
4351static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
4352	.halt_reg = 0x42004,
4353	.halt_check = BRANCH_HALT_VOTED,
4354	.clkr = {
4355		.enable_reg = 0x52020,
4356		.enable_mask = BIT(10),
4357		.hw.init = &(const struct clk_init_data) {
4358			.name = "gcc_qupv3_wrap0_s0_clk",
4359			.parent_hws = (const struct clk_hw*[]) {
4360				&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
4361			},
4362			.num_parents = 1,
4363			.flags = CLK_SET_RATE_PARENT,
4364			.ops = &clk_branch2_ops,
4365		},
4366	},
4367};
4368
4369static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
4370	.halt_reg = 0x4213c,
4371	.halt_check = BRANCH_HALT_VOTED,
4372	.clkr = {
4373		.enable_reg = 0x52020,
4374		.enable_mask = BIT(11),
4375		.hw.init = &(const struct clk_init_data) {
4376			.name = "gcc_qupv3_wrap0_s1_clk",
4377			.parent_hws = (const struct clk_hw*[]) {
4378				&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
4379			},
4380			.num_parents = 1,
4381			.flags = CLK_SET_RATE_PARENT,
4382			.ops = &clk_branch2_ops,
4383		},
4384	},
4385};
4386
4387static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
4388	.halt_reg = 0x42274,
4389	.halt_check = BRANCH_HALT_VOTED,
4390	.clkr = {
4391		.enable_reg = 0x52020,
4392		.enable_mask = BIT(12),
4393		.hw.init = &(const struct clk_init_data) {
4394			.name = "gcc_qupv3_wrap0_s2_clk",
4395			.parent_hws = (const struct clk_hw*[]) {
4396				&gcc_qupv3_wrap0_s2_div_clk_src.clkr.hw,
4397			},
4398			.num_parents = 1,
4399			.flags = CLK_SET_RATE_PARENT,
4400			.ops = &clk_branch2_ops,
4401		},
4402	},
4403};
4404
4405static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
4406	.halt_reg = 0x423b4,
4407	.halt_check = BRANCH_HALT_VOTED,
4408	.clkr = {
4409		.enable_reg = 0x52020,
4410		.enable_mask = BIT(13),
4411		.hw.init = &(const struct clk_init_data) {
4412			.name = "gcc_qupv3_wrap0_s3_clk",
4413			.parent_hws = (const struct clk_hw*[]) {
4414				&gcc_qupv3_wrap0_s3_div_clk_src.clkr.hw,
4415			},
4416			.num_parents = 1,
4417			.flags = CLK_SET_RATE_PARENT,
4418			.ops = &clk_branch2_ops,
4419		},
4420	},
4421};
4422
4423static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
4424	.halt_reg = 0x424f4,
4425	.halt_check = BRANCH_HALT_VOTED,
4426	.clkr = {
4427		.enable_reg = 0x52020,
4428		.enable_mask = BIT(14),
4429		.hw.init = &(const struct clk_init_data) {
4430			.name = "gcc_qupv3_wrap0_s4_clk",
4431			.parent_hws = (const struct clk_hw*[]) {
4432				&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
4433			},
4434			.num_parents = 1,
4435			.flags = CLK_SET_RATE_PARENT,
4436			.ops = &clk_branch2_ops,
4437		},
4438	},
4439};
4440
4441static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
4442	.halt_reg = 0x4262c,
4443	.halt_check = BRANCH_HALT_VOTED,
4444	.clkr = {
4445		.enable_reg = 0x52020,
4446		.enable_mask = BIT(15),
4447		.hw.init = &(const struct clk_init_data) {
4448			.name = "gcc_qupv3_wrap0_s5_clk",
4449			.parent_hws = (const struct clk_hw*[]) {
4450				&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
4451			},
4452			.num_parents = 1,
4453			.flags = CLK_SET_RATE_PARENT,
4454			.ops = &clk_branch2_ops,
4455		},
4456	},
4457};
4458
4459static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
4460	.halt_reg = 0x42764,
4461	.halt_check = BRANCH_HALT_VOTED,
4462	.clkr = {
4463		.enable_reg = 0x52020,
4464		.enable_mask = BIT(16),
4465		.hw.init = &(const struct clk_init_data) {
4466			.name = "gcc_qupv3_wrap0_s6_clk",
4467			.parent_hws = (const struct clk_hw*[]) {
4468				&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
4469			},
4470			.num_parents = 1,
4471			.flags = CLK_SET_RATE_PARENT,
4472			.ops = &clk_branch2_ops,
4473		},
4474	},
4475};
4476
4477static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
4478	.halt_reg = 0x4289c,
4479	.halt_check = BRANCH_HALT_VOTED,
4480	.clkr = {
4481		.enable_reg = 0x52020,
4482		.enable_mask = BIT(17),
4483		.hw.init = &(const struct clk_init_data) {
4484			.name = "gcc_qupv3_wrap0_s7_clk",
4485			.parent_hws = (const struct clk_hw*[]) {
4486				&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
4487			},
4488			.num_parents = 1,
4489			.flags = CLK_SET_RATE_PARENT,
4490			.ops = &clk_branch2_ops,
4491		},
4492	},
4493};
4494
4495static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
4496	.halt_reg = 0x23168,
4497	.halt_check = BRANCH_HALT_VOTED,
4498	.clkr = {
4499		.enable_reg = 0x52008,
4500		.enable_mask = BIT(18),
4501		.hw.init = &(const struct clk_init_data) {
4502			.name = "gcc_qupv3_wrap1_core_2x_clk",
4503			.ops = &clk_branch2_ops,
4504		},
4505	},
4506};
4507
4508static struct clk_branch gcc_qupv3_wrap1_core_clk = {
4509	.halt_reg = 0x23158,
4510	.halt_check = BRANCH_HALT_VOTED,
4511	.clkr = {
4512		.enable_reg = 0x52008,
4513		.enable_mask = BIT(19),
4514		.hw.init = &(const struct clk_init_data) {
4515			.name = "gcc_qupv3_wrap1_core_clk",
4516			.ops = &clk_branch2_ops,
4517		},
4518	},
4519};
4520
4521static struct clk_branch gcc_qupv3_wrap1_qspi_s2_clk = {
4522	.halt_reg = 0x18280,
4523	.halt_check = BRANCH_HALT_VOTED,
4524	.clkr = {
4525		.enable_reg = 0x52028,
4526		.enable_mask = BIT(4),
4527		.hw.init = &(const struct clk_init_data) {
4528			.name = "gcc_qupv3_wrap1_qspi_s2_clk",
4529			.parent_hws = (const struct clk_hw*[]) {
4530				&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
4531			},
4532			.num_parents = 1,
4533			.flags = CLK_SET_RATE_PARENT,
4534			.ops = &clk_branch2_ops,
4535		},
4536	},
4537};
4538
4539static struct clk_branch gcc_qupv3_wrap1_qspi_s3_clk = {
4540	.halt_reg = 0x183c0,
4541	.halt_check = BRANCH_HALT_VOTED,
4542	.clkr = {
4543		.enable_reg = 0x52028,
4544		.enable_mask = BIT(5),
4545		.hw.init = &(const struct clk_init_data) {
4546			.name = "gcc_qupv3_wrap1_qspi_s3_clk",
4547			.parent_hws = (const struct clk_hw*[]) {
4548				&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
4549			},
4550			.num_parents = 1,
4551			.flags = CLK_SET_RATE_PARENT,
4552			.ops = &clk_branch2_ops,
4553		},
4554	},
4555};
4556
4557static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
4558	.halt_reg = 0x18004,
4559	.halt_check = BRANCH_HALT_VOTED,
4560	.clkr = {
4561		.enable_reg = 0x52008,
4562		.enable_mask = BIT(22),
4563		.hw.init = &(const struct clk_init_data) {
4564			.name = "gcc_qupv3_wrap1_s0_clk",
4565			.parent_hws = (const struct clk_hw*[]) {
4566				&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
4567			},
4568			.num_parents = 1,
4569			.flags = CLK_SET_RATE_PARENT,
4570			.ops = &clk_branch2_ops,
4571		},
4572	},
4573};
4574
4575static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
4576	.halt_reg = 0x1813c,
4577	.halt_check = BRANCH_HALT_VOTED,
4578	.clkr = {
4579		.enable_reg = 0x52008,
4580		.enable_mask = BIT(23),
4581		.hw.init = &(const struct clk_init_data) {
4582			.name = "gcc_qupv3_wrap1_s1_clk",
4583			.parent_hws = (const struct clk_hw*[]) {
4584				&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
4585			},
4586			.num_parents = 1,
4587			.flags = CLK_SET_RATE_PARENT,
4588			.ops = &clk_branch2_ops,
4589		},
4590	},
4591};
4592
4593static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
4594	.halt_reg = 0x18274,
4595	.halt_check = BRANCH_HALT_VOTED,
4596	.clkr = {
4597		.enable_reg = 0x52008,
4598		.enable_mask = BIT(24),
4599		.hw.init = &(const struct clk_init_data) {
4600			.name = "gcc_qupv3_wrap1_s2_clk",
4601			.parent_hws = (const struct clk_hw*[]) {
4602				&gcc_qupv3_wrap1_s2_div_clk_src.clkr.hw,
4603			},
4604			.num_parents = 1,
4605			.flags = CLK_SET_RATE_PARENT,
4606			.ops = &clk_branch2_ops,
4607		},
4608	},
4609};
4610
4611static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
4612	.halt_reg = 0x183b4,
4613	.halt_check = BRANCH_HALT_VOTED,
4614	.clkr = {
4615		.enable_reg = 0x52008,
4616		.enable_mask = BIT(25),
4617		.hw.init = &(const struct clk_init_data) {
4618			.name = "gcc_qupv3_wrap1_s3_clk",
4619			.parent_hws = (const struct clk_hw*[]) {
4620				&gcc_qupv3_wrap1_s3_div_clk_src.clkr.hw,
4621			},
4622			.num_parents = 1,
4623			.flags = CLK_SET_RATE_PARENT,
4624			.ops = &clk_branch2_ops,
4625		},
4626	},
4627};
4628
4629static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
4630	.halt_reg = 0x184f4,
4631	.halt_check = BRANCH_HALT_VOTED,
4632	.clkr = {
4633		.enable_reg = 0x52008,
4634		.enable_mask = BIT(26),
4635		.hw.init = &(const struct clk_init_data) {
4636			.name = "gcc_qupv3_wrap1_s4_clk",
4637			.parent_hws = (const struct clk_hw*[]) {
4638				&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
4639			},
4640			.num_parents = 1,
4641			.flags = CLK_SET_RATE_PARENT,
4642			.ops = &clk_branch2_ops,
4643		},
4644	},
4645};
4646
4647static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
4648	.halt_reg = 0x1862c,
4649	.halt_check = BRANCH_HALT_VOTED,
4650	.clkr = {
4651		.enable_reg = 0x52008,
4652		.enable_mask = BIT(27),
4653		.hw.init = &(const struct clk_init_data) {
4654			.name = "gcc_qupv3_wrap1_s5_clk",
4655			.parent_hws = (const struct clk_hw*[]) {
4656				&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
4657			},
4658			.num_parents = 1,
4659			.flags = CLK_SET_RATE_PARENT,
4660			.ops = &clk_branch2_ops,
4661		},
4662	},
4663};
4664
4665static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
4666	.halt_reg = 0x18764,
4667	.halt_check = BRANCH_HALT_VOTED,
4668	.clkr = {
4669		.enable_reg = 0x52008,
4670		.enable_mask = BIT(28),
4671		.hw.init = &(const struct clk_init_data) {
4672			.name = "gcc_qupv3_wrap1_s6_clk",
4673			.parent_hws = (const struct clk_hw*[]) {
4674				&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
4675			},
4676			.num_parents = 1,
4677			.flags = CLK_SET_RATE_PARENT,
4678			.ops = &clk_branch2_ops,
4679		},
4680	},
4681};
4682
4683static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
4684	.halt_reg = 0x1889c,
4685	.halt_check = BRANCH_HALT_VOTED,
4686	.clkr = {
4687		.enable_reg = 0x52010,
4688		.enable_mask = BIT(16),
4689		.hw.init = &(const struct clk_init_data) {
4690			.name = "gcc_qupv3_wrap1_s7_clk",
4691			.parent_hws = (const struct clk_hw*[]) {
4692				&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
4693			},
4694			.num_parents = 1,
4695			.flags = CLK_SET_RATE_PARENT,
4696			.ops = &clk_branch2_ops,
4697		},
4698	},
4699};
4700
4701static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
4702	.halt_reg = 0x232b8,
4703	.halt_check = BRANCH_HALT_VOTED,
4704	.clkr = {
4705		.enable_reg = 0x52010,
4706		.enable_mask = BIT(3),
4707		.hw.init = &(const struct clk_init_data) {
4708			.name = "gcc_qupv3_wrap2_core_2x_clk",
4709			.ops = &clk_branch2_ops,
4710		},
4711	},
4712};
4713
4714static struct clk_branch gcc_qupv3_wrap2_core_clk = {
4715	.halt_reg = 0x232a8,
4716	.halt_check = BRANCH_HALT_VOTED,
4717	.clkr = {
4718		.enable_reg = 0x52010,
4719		.enable_mask = BIT(0),
4720		.hw.init = &(const struct clk_init_data) {
4721			.name = "gcc_qupv3_wrap2_core_clk",
4722			.ops = &clk_branch2_ops,
4723		},
4724	},
4725};
4726
4727static struct clk_branch gcc_qupv3_wrap2_qspi_s2_clk = {
4728	.halt_reg = 0x1e280,
4729	.halt_check = BRANCH_HALT_VOTED,
4730	.clkr = {
4731		.enable_reg = 0x52028,
4732		.enable_mask = BIT(6),
4733		.hw.init = &(const struct clk_init_data) {
4734			.name = "gcc_qupv3_wrap2_qspi_s2_clk",
4735			.parent_hws = (const struct clk_hw*[]) {
4736				&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
4737			},
4738			.num_parents = 1,
4739			.flags = CLK_SET_RATE_PARENT,
4740			.ops = &clk_branch2_ops,
4741		},
4742	},
4743};
4744
4745static struct clk_branch gcc_qupv3_wrap2_qspi_s3_clk = {
4746	.halt_reg = 0x1e3c0,
4747	.halt_check = BRANCH_HALT_VOTED,
4748	.clkr = {
4749		.enable_reg = 0x52028,
4750		.enable_mask = BIT(7),
4751		.hw.init = &(const struct clk_init_data) {
4752			.name = "gcc_qupv3_wrap2_qspi_s3_clk",
4753			.parent_hws = (const struct clk_hw*[]) {
4754				&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
4755			},
4756			.num_parents = 1,
4757			.flags = CLK_SET_RATE_PARENT,
4758			.ops = &clk_branch2_ops,
4759		},
4760	},
4761};
4762
4763static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
4764	.halt_reg = 0x1e004,
4765	.halt_check = BRANCH_HALT_VOTED,
4766	.clkr = {
4767		.enable_reg = 0x52010,
4768		.enable_mask = BIT(4),
4769		.hw.init = &(const struct clk_init_data) {
4770			.name = "gcc_qupv3_wrap2_s0_clk",
4771			.parent_hws = (const struct clk_hw*[]) {
4772				&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
4773			},
4774			.num_parents = 1,
4775			.flags = CLK_SET_RATE_PARENT,
4776			.ops = &clk_branch2_ops,
4777		},
4778	},
4779};
4780
4781static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
4782	.halt_reg = 0x1e13c,
4783	.halt_check = BRANCH_HALT_VOTED,
4784	.clkr = {
4785		.enable_reg = 0x52010,
4786		.enable_mask = BIT(5),
4787		.hw.init = &(const struct clk_init_data) {
4788			.name = "gcc_qupv3_wrap2_s1_clk",
4789			.parent_hws = (const struct clk_hw*[]) {
4790				&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
4791			},
4792			.num_parents = 1,
4793			.flags = CLK_SET_RATE_PARENT,
4794			.ops = &clk_branch2_ops,
4795		},
4796	},
4797};
4798
4799static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
4800	.halt_reg = 0x1e274,
4801	.halt_check = BRANCH_HALT_VOTED,
4802	.clkr = {
4803		.enable_reg = 0x52010,
4804		.enable_mask = BIT(6),
4805		.hw.init = &(const struct clk_init_data) {
4806			.name = "gcc_qupv3_wrap2_s2_clk",
4807			.parent_hws = (const struct clk_hw*[]) {
4808				&gcc_qupv3_wrap2_s2_div_clk_src.clkr.hw,
4809			},
4810			.num_parents = 1,
4811			.flags = CLK_SET_RATE_PARENT,
4812			.ops = &clk_branch2_ops,
4813		},
4814	},
4815};
4816
4817static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
4818	.halt_reg = 0x1e3b4,
4819	.halt_check = BRANCH_HALT_VOTED,
4820	.clkr = {
4821		.enable_reg = 0x52010,
4822		.enable_mask = BIT(7),
4823		.hw.init = &(const struct clk_init_data) {
4824			.name = "gcc_qupv3_wrap2_s3_clk",
4825			.parent_hws = (const struct clk_hw*[]) {
4826				&gcc_qupv3_wrap2_s3_div_clk_src.clkr.hw,
4827			},
4828			.num_parents = 1,
4829			.flags = CLK_SET_RATE_PARENT,
4830			.ops = &clk_branch2_ops,
4831		},
4832	},
4833};
4834
4835static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
4836	.halt_reg = 0x1e4f4,
4837	.halt_check = BRANCH_HALT_VOTED,
4838	.clkr = {
4839		.enable_reg = 0x52010,
4840		.enable_mask = BIT(8),
4841		.hw.init = &(const struct clk_init_data) {
4842			.name = "gcc_qupv3_wrap2_s4_clk",
4843			.parent_hws = (const struct clk_hw*[]) {
4844				&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
4845			},
4846			.num_parents = 1,
4847			.flags = CLK_SET_RATE_PARENT,
4848			.ops = &clk_branch2_ops,
4849		},
4850	},
4851};
4852
4853static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
4854	.halt_reg = 0x1e62c,
4855	.halt_check = BRANCH_HALT_VOTED,
4856	.clkr = {
4857		.enable_reg = 0x52010,
4858		.enable_mask = BIT(9),
4859		.hw.init = &(const struct clk_init_data) {
4860			.name = "gcc_qupv3_wrap2_s5_clk",
4861			.parent_hws = (const struct clk_hw*[]) {
4862				&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
4863			},
4864			.num_parents = 1,
4865			.flags = CLK_SET_RATE_PARENT,
4866			.ops = &clk_branch2_ops,
4867		},
4868	},
4869};
4870
4871static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
4872	.halt_reg = 0x1e764,
4873	.halt_check = BRANCH_HALT_VOTED,
4874	.clkr = {
4875		.enable_reg = 0x52010,
4876		.enable_mask = BIT(10),
4877		.hw.init = &(const struct clk_init_data) {
4878			.name = "gcc_qupv3_wrap2_s6_clk",
4879			.parent_hws = (const struct clk_hw*[]) {
4880				&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
4881			},
4882			.num_parents = 1,
4883			.flags = CLK_SET_RATE_PARENT,
4884			.ops = &clk_branch2_ops,
4885		},
4886	},
4887};
4888
4889static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
4890	.halt_reg = 0x1e89c,
4891	.halt_check = BRANCH_HALT_VOTED,
4892	.clkr = {
4893		.enable_reg = 0x52010,
4894		.enable_mask = BIT(17),
4895		.hw.init = &(const struct clk_init_data) {
4896			.name = "gcc_qupv3_wrap2_s7_clk",
4897			.parent_hws = (const struct clk_hw*[]) {
4898				&gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
4899			},
4900			.num_parents = 1,
4901			.flags = CLK_SET_RATE_PARENT,
4902			.ops = &clk_branch2_ops,
4903		},
4904	},
4905};
4906
4907static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
4908	.halt_reg = 0x23000,
4909	.halt_check = BRANCH_HALT_VOTED,
4910	.hwcg_reg = 0x23000,
4911	.hwcg_bit = 1,
4912	.clkr = {
4913		.enable_reg = 0x52020,
4914		.enable_mask = BIT(6),
4915		.hw.init = &(const struct clk_init_data) {
4916			.name = "gcc_qupv3_wrap_0_m_ahb_clk",
4917			.ops = &clk_branch2_ops,
4918		},
4919	},
4920};
4921
4922static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
4923	.halt_reg = 0x23004,
4924	.halt_check = BRANCH_HALT_VOTED,
4925	.hwcg_reg = 0x23004,
4926	.hwcg_bit = 1,
4927	.clkr = {
4928		.enable_reg = 0x52020,
4929		.enable_mask = BIT(7),
4930		.hw.init = &(const struct clk_init_data) {
4931			.name = "gcc_qupv3_wrap_0_s_ahb_clk",
4932			.ops = &clk_branch2_ops,
4933		},
4934	},
4935};
4936
4937static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
4938	.halt_reg = 0x23150,
4939	.halt_check = BRANCH_HALT_VOTED,
4940	.hwcg_reg = 0x23150,
4941	.hwcg_bit = 1,
4942	.clkr = {
4943		.enable_reg = 0x52008,
4944		.enable_mask = BIT(20),
4945		.hw.init = &(const struct clk_init_data) {
4946			.name = "gcc_qupv3_wrap_1_m_ahb_clk",
4947			.ops = &clk_branch2_ops,
4948		},
4949	},
4950};
4951
4952static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
4953	.halt_reg = 0x23154,
4954	.halt_check = BRANCH_HALT_VOTED,
4955	.hwcg_reg = 0x23154,
4956	.hwcg_bit = 1,
4957	.clkr = {
4958		.enable_reg = 0x52008,
4959		.enable_mask = BIT(21),
4960		.hw.init = &(const struct clk_init_data) {
4961			.name = "gcc_qupv3_wrap_1_s_ahb_clk",
4962			.ops = &clk_branch2_ops,
4963		},
4964	},
4965};
4966
4967static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
4968	.halt_reg = 0x232a0,
4969	.halt_check = BRANCH_HALT_VOTED,
4970	.hwcg_reg = 0x232a0,
4971	.hwcg_bit = 1,
4972	.clkr = {
4973		.enable_reg = 0x52010,
4974		.enable_mask = BIT(2),
4975		.hw.init = &(const struct clk_init_data) {
4976			.name = "gcc_qupv3_wrap_2_m_ahb_clk",
4977			.ops = &clk_branch2_ops,
4978		},
4979	},
4980};
4981
4982static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
4983	.halt_reg = 0x232a4,
4984	.halt_check = BRANCH_HALT_VOTED,
4985	.hwcg_reg = 0x232a4,
4986	.hwcg_bit = 1,
4987	.clkr = {
4988		.enable_reg = 0x52010,
4989		.enable_mask = BIT(1),
4990		.hw.init = &(const struct clk_init_data) {
4991			.name = "gcc_qupv3_wrap_2_s_ahb_clk",
4992			.ops = &clk_branch2_ops,
4993		},
4994	},
4995};
4996
4997static struct clk_branch gcc_sdcc2_ahb_clk = {
4998	.halt_reg = 0x14010,
4999	.halt_check = BRANCH_HALT,
5000	.clkr = {
5001		.enable_reg = 0x14010,
5002		.enable_mask = BIT(0),
5003		.hw.init = &(const struct clk_init_data) {
5004			.name = "gcc_sdcc2_ahb_clk",
5005			.ops = &clk_branch2_ops,
5006		},
5007	},
5008};
5009
5010static struct clk_branch gcc_sdcc2_apps_clk = {
5011	.halt_reg = 0x14004,
5012	.halt_check = BRANCH_HALT,
5013	.clkr = {
5014		.enable_reg = 0x14004,
5015		.enable_mask = BIT(0),
5016		.hw.init = &(const struct clk_init_data) {
5017			.name = "gcc_sdcc2_apps_clk",
5018			.parent_hws = (const struct clk_hw*[]) {
5019				&gcc_sdcc2_apps_clk_src.clkr.hw,
5020			},
5021			.num_parents = 1,
5022			.flags = CLK_SET_RATE_PARENT,
5023			.ops = &clk_branch2_ops,
5024		},
5025	},
5026};
5027
5028static struct clk_branch gcc_sdcc4_ahb_clk = {
5029	.halt_reg = 0x16010,
5030	.halt_check = BRANCH_HALT,
5031	.clkr = {
5032		.enable_reg = 0x16010,
5033		.enable_mask = BIT(0),
5034		.hw.init = &(const struct clk_init_data) {
5035			.name = "gcc_sdcc4_ahb_clk",
5036			.ops = &clk_branch2_ops,
5037		},
5038	},
5039};
5040
5041static struct clk_branch gcc_sdcc4_apps_clk = {
5042	.halt_reg = 0x16004,
5043	.halt_check = BRANCH_HALT,
5044	.clkr = {
5045		.enable_reg = 0x16004,
5046		.enable_mask = BIT(0),
5047		.hw.init = &(const struct clk_init_data) {
5048			.name = "gcc_sdcc4_apps_clk",
5049			.parent_hws = (const struct clk_hw*[]) {
5050				&gcc_sdcc4_apps_clk_src.clkr.hw,
5051			},
5052			.num_parents = 1,
5053			.flags = CLK_SET_RATE_PARENT,
5054			.ops = &clk_branch2_ops,
5055		},
5056	},
5057};
5058
5059static struct clk_branch gcc_sys_noc_usb_axi_clk = {
5060	.halt_reg = 0x2d014,
5061	.halt_check = BRANCH_HALT_VOTED,
5062	.hwcg_reg = 0x2d014,
5063	.hwcg_bit = 1,
5064	.clkr = {
5065		.enable_reg = 0x2d014,
5066		.enable_mask = BIT(0),
5067		.hw.init = &(const struct clk_init_data) {
5068			.name = "gcc_sys_noc_usb_axi_clk",
5069			.ops = &clk_branch2_ops,
5070		},
5071	},
5072};
5073
5074static struct clk_branch gcc_ufs_phy_ahb_clk = {
5075	.halt_reg = 0x77024,
5076	.halt_check = BRANCH_HALT_VOTED,
5077	.hwcg_reg = 0x77024,
5078	.hwcg_bit = 1,
5079	.clkr = {
5080		.enable_reg = 0x77024,
5081		.enable_mask = BIT(0),
5082		.hw.init = &(const struct clk_init_data) {
5083			.name = "gcc_ufs_phy_ahb_clk",
5084			.ops = &clk_branch2_ops,
5085		},
5086	},
5087};
5088
5089static struct clk_branch gcc_ufs_phy_axi_clk = {
5090	.halt_reg = 0x77018,
5091	.halt_check = BRANCH_HALT_VOTED,
5092	.hwcg_reg = 0x77018,
5093	.hwcg_bit = 1,
5094	.clkr = {
5095		.enable_reg = 0x77018,
5096		.enable_mask = BIT(0),
5097		.hw.init = &(const struct clk_init_data) {
5098			.name = "gcc_ufs_phy_axi_clk",
5099			.parent_hws = (const struct clk_hw*[]) {
5100				&gcc_ufs_phy_axi_clk_src.clkr.hw,
5101			},
5102			.num_parents = 1,
5103			.flags = CLK_SET_RATE_PARENT,
5104			.ops = &clk_branch2_ops,
5105		},
5106	},
5107};
5108
5109static struct clk_branch gcc_ufs_phy_ice_core_clk = {
5110	.halt_reg = 0x77074,
5111	.halt_check = BRANCH_HALT_VOTED,
5112	.hwcg_reg = 0x77074,
5113	.hwcg_bit = 1,
5114	.clkr = {
5115		.enable_reg = 0x77074,
5116		.enable_mask = BIT(0),
5117		.hw.init = &(const struct clk_init_data) {
5118			.name = "gcc_ufs_phy_ice_core_clk",
5119			.parent_hws = (const struct clk_hw*[]) {
5120				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
5121			},
5122			.num_parents = 1,
5123			.flags = CLK_SET_RATE_PARENT,
5124			.ops = &clk_branch2_ops,
5125		},
5126	},
5127};
5128
5129static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
5130	.halt_reg = 0x770b0,
5131	.halt_check = BRANCH_HALT_VOTED,
5132	.hwcg_reg = 0x770b0,
5133	.hwcg_bit = 1,
5134	.clkr = {
5135		.enable_reg = 0x770b0,
5136		.enable_mask = BIT(0),
5137		.hw.init = &(const struct clk_init_data) {
5138			.name = "gcc_ufs_phy_phy_aux_clk",
5139			.parent_hws = (const struct clk_hw*[]) {
5140				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
5141			},
5142			.num_parents = 1,
5143			.flags = CLK_SET_RATE_PARENT,
5144			.ops = &clk_branch2_ops,
5145		},
5146	},
5147};
5148
5149static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
5150	.halt_reg = 0x7702c,
5151	.halt_check = BRANCH_HALT,
5152	.clkr = {
5153		.enable_reg = 0x7702c,
5154		.enable_mask = BIT(0),
5155		.hw.init = &(const struct clk_init_data) {
5156			.name = "gcc_ufs_phy_rx_symbol_0_clk",
5157			.ops = &clk_branch2_ops,
5158		},
5159	},
5160};
5161
5162static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
5163	.halt_reg = 0x770cc,
5164	.halt_check = BRANCH_HALT,
5165	.clkr = {
5166		.enable_reg = 0x770cc,
5167		.enable_mask = BIT(0),
5168		.hw.init = &(const struct clk_init_data) {
5169			.name = "gcc_ufs_phy_rx_symbol_1_clk",
5170			.ops = &clk_branch2_ops,
5171		},
5172	},
5173};
5174
5175static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
5176	.halt_reg = 0x77028,
5177	.halt_check = BRANCH_HALT,
5178	.clkr = {
5179		.enable_reg = 0x77028,
5180		.enable_mask = BIT(0),
5181		.hw.init = &(const struct clk_init_data) {
5182			.name = "gcc_ufs_phy_tx_symbol_0_clk",
5183			.ops = &clk_branch2_ops,
5184		},
5185	},
5186};
5187
5188static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
5189	.halt_reg = 0x77068,
5190	.halt_check = BRANCH_HALT_VOTED,
5191	.hwcg_reg = 0x77068,
5192	.hwcg_bit = 1,
5193	.clkr = {
5194		.enable_reg = 0x77068,
5195		.enable_mask = BIT(0),
5196		.hw.init = &(const struct clk_init_data) {
5197			.name = "gcc_ufs_phy_unipro_core_clk",
5198			.parent_hws = (const struct clk_hw*[]) {
5199				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
5200			},
5201			.num_parents = 1,
5202			.flags = CLK_SET_RATE_PARENT,
5203			.ops = &clk_branch2_ops,
5204		},
5205	},
5206};
5207
5208static struct clk_branch gcc_usb20_master_clk = {
5209	.halt_reg = 0x29018,
5210	.halt_check = BRANCH_HALT,
5211	.clkr = {
5212		.enable_reg = 0x29018,
5213		.enable_mask = BIT(0),
5214		.hw.init = &(const struct clk_init_data) {
5215			.name = "gcc_usb20_master_clk",
5216			.parent_hws = (const struct clk_hw*[]) {
5217				&gcc_usb20_master_clk_src.clkr.hw,
5218			},
5219			.num_parents = 1,
5220			.flags = CLK_SET_RATE_PARENT,
5221			.ops = &clk_branch2_ops,
5222		},
5223	},
5224};
5225
5226static struct clk_branch gcc_usb20_mock_utmi_clk = {
5227	.halt_reg = 0x29028,
5228	.halt_check = BRANCH_HALT,
5229	.clkr = {
5230		.enable_reg = 0x29028,
5231		.enable_mask = BIT(0),
5232		.hw.init = &(const struct clk_init_data) {
5233			.name = "gcc_usb20_mock_utmi_clk",
5234			.parent_hws = (const struct clk_hw*[]) {
5235				&gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw,
5236			},
5237			.num_parents = 1,
5238			.flags = CLK_SET_RATE_PARENT,
5239			.ops = &clk_branch2_ops,
5240		},
5241	},
5242};
5243
5244static struct clk_branch gcc_usb20_sleep_clk = {
5245	.halt_reg = 0x29024,
5246	.halt_check = BRANCH_HALT,
5247	.clkr = {
5248		.enable_reg = 0x29024,
5249		.enable_mask = BIT(0),
5250		.hw.init = &(const struct clk_init_data) {
5251			.name = "gcc_usb20_sleep_clk",
5252			.ops = &clk_branch2_ops,
5253		},
5254	},
5255};
5256
5257static struct clk_branch gcc_usb30_mp_master_clk = {
5258	.halt_reg = 0x17018,
5259	.halt_check = BRANCH_HALT,
5260	.clkr = {
5261		.enable_reg = 0x17018,
5262		.enable_mask = BIT(0),
5263		.hw.init = &(const struct clk_init_data) {
5264			.name = "gcc_usb30_mp_master_clk",
5265			.parent_hws = (const struct clk_hw*[]) {
5266				&gcc_usb30_mp_master_clk_src.clkr.hw,
5267			},
5268			.num_parents = 1,
5269			.flags = CLK_SET_RATE_PARENT,
5270			.ops = &clk_branch2_ops,
5271		},
5272	},
5273};
5274
5275static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {
5276	.halt_reg = 0x17028,
5277	.halt_check = BRANCH_HALT,
5278	.clkr = {
5279		.enable_reg = 0x17028,
5280		.enable_mask = BIT(0),
5281		.hw.init = &(const struct clk_init_data) {
5282			.name = "gcc_usb30_mp_mock_utmi_clk",
5283			.parent_hws = (const struct clk_hw*[]) {
5284				&gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw,
5285			},
5286			.num_parents = 1,
5287			.flags = CLK_SET_RATE_PARENT,
5288			.ops = &clk_branch2_ops,
5289		},
5290	},
5291};
5292
5293static struct clk_branch gcc_usb30_mp_sleep_clk = {
5294	.halt_reg = 0x17024,
5295	.halt_check = BRANCH_HALT,
5296	.clkr = {
5297		.enable_reg = 0x17024,
5298		.enable_mask = BIT(0),
5299		.hw.init = &(const struct clk_init_data) {
5300			.name = "gcc_usb30_mp_sleep_clk",
5301			.ops = &clk_branch2_ops,
5302		},
5303	},
5304};
5305
5306static struct clk_branch gcc_usb30_prim_master_clk = {
5307	.halt_reg = 0x39018,
5308	.halt_check = BRANCH_HALT,
5309	.clkr = {
5310		.enable_reg = 0x39018,
5311		.enable_mask = BIT(0),
5312		.hw.init = &(const struct clk_init_data) {
5313			.name = "gcc_usb30_prim_master_clk",
5314			.parent_hws = (const struct clk_hw*[]) {
5315				&gcc_usb30_prim_master_clk_src.clkr.hw,
5316			},
5317			.num_parents = 1,
5318			.flags = CLK_SET_RATE_PARENT,
5319			.ops = &clk_branch2_ops,
5320		},
5321	},
5322};
5323
5324static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
5325	.halt_reg = 0x39028,
5326	.halt_check = BRANCH_HALT,
5327	.clkr = {
5328		.enable_reg = 0x39028,
5329		.enable_mask = BIT(0),
5330		.hw.init = &(const struct clk_init_data) {
5331			.name = "gcc_usb30_prim_mock_utmi_clk",
5332			.parent_hws = (const struct clk_hw*[]) {
5333				&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
5334			},
5335			.num_parents = 1,
5336			.flags = CLK_SET_RATE_PARENT,
5337			.ops = &clk_branch2_ops,
5338		},
5339	},
5340};
5341
5342static struct clk_branch gcc_usb30_prim_sleep_clk = {
5343	.halt_reg = 0x39024,
5344	.halt_check = BRANCH_HALT,
5345	.clkr = {
5346		.enable_reg = 0x39024,
5347		.enable_mask = BIT(0),
5348		.hw.init = &(const struct clk_init_data) {
5349			.name = "gcc_usb30_prim_sleep_clk",
5350			.ops = &clk_branch2_ops,
5351		},
5352	},
5353};
5354
5355static struct clk_branch gcc_usb30_sec_master_clk = {
5356	.halt_reg = 0xa1018,
5357	.halt_check = BRANCH_HALT,
5358	.clkr = {
5359		.enable_reg = 0xa1018,
5360		.enable_mask = BIT(0),
5361		.hw.init = &(const struct clk_init_data) {
5362			.name = "gcc_usb30_sec_master_clk",
5363			.parent_hws = (const struct clk_hw*[]) {
5364				&gcc_usb30_sec_master_clk_src.clkr.hw,
5365			},
5366			.num_parents = 1,
5367			.flags = CLK_SET_RATE_PARENT,
5368			.ops = &clk_branch2_ops,
5369		},
5370	},
5371};
5372
5373static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
5374	.halt_reg = 0xa1028,
5375	.halt_check = BRANCH_HALT,
5376	.clkr = {
5377		.enable_reg = 0xa1028,
5378		.enable_mask = BIT(0),
5379		.hw.init = &(const struct clk_init_data) {
5380			.name = "gcc_usb30_sec_mock_utmi_clk",
5381			.parent_hws = (const struct clk_hw*[]) {
5382				&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
5383			},
5384			.num_parents = 1,
5385			.flags = CLK_SET_RATE_PARENT,
5386			.ops = &clk_branch2_ops,
5387		},
5388	},
5389};
5390
5391static struct clk_branch gcc_usb30_sec_sleep_clk = {
5392	.halt_reg = 0xa1024,
5393	.halt_check = BRANCH_HALT,
5394	.clkr = {
5395		.enable_reg = 0xa1024,
5396		.enable_mask = BIT(0),
5397		.hw.init = &(const struct clk_init_data) {
5398			.name = "gcc_usb30_sec_sleep_clk",
5399			.ops = &clk_branch2_ops,
5400		},
5401	},
5402};
5403
5404static struct clk_branch gcc_usb30_tert_master_clk = {
5405	.halt_reg = 0xa2018,
5406	.halt_check = BRANCH_HALT,
5407	.clkr = {
5408		.enable_reg = 0xa2018,
5409		.enable_mask = BIT(0),
5410		.hw.init = &(const struct clk_init_data) {
5411			.name = "gcc_usb30_tert_master_clk",
5412			.parent_hws = (const struct clk_hw*[]) {
5413				&gcc_usb30_tert_master_clk_src.clkr.hw,
5414			},
5415			.num_parents = 1,
5416			.flags = CLK_SET_RATE_PARENT,
5417			.ops = &clk_branch2_ops,
5418		},
5419	},
5420};
5421
5422static struct clk_branch gcc_usb30_tert_mock_utmi_clk = {
5423	.halt_reg = 0xa2028,
5424	.halt_check = BRANCH_HALT,
5425	.clkr = {
5426		.enable_reg = 0xa2028,
5427		.enable_mask = BIT(0),
5428		.hw.init = &(const struct clk_init_data) {
5429			.name = "gcc_usb30_tert_mock_utmi_clk",
5430			.parent_hws = (const struct clk_hw*[]) {
5431				&gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr.hw,
5432			},
5433			.num_parents = 1,
5434			.flags = CLK_SET_RATE_PARENT,
5435			.ops = &clk_branch2_ops,
5436		},
5437	},
5438};
5439
5440static struct clk_branch gcc_usb30_tert_sleep_clk = {
5441	.halt_reg = 0xa2024,
5442	.halt_check = BRANCH_HALT,
5443	.clkr = {
5444		.enable_reg = 0xa2024,
5445		.enable_mask = BIT(0),
5446		.hw.init = &(const struct clk_init_data) {
5447			.name = "gcc_usb30_tert_sleep_clk",
5448			.ops = &clk_branch2_ops,
5449		},
5450	},
5451};
5452
5453static struct clk_branch gcc_usb3_mp_phy_aux_clk = {
5454	.halt_reg = 0x17288,
5455	.halt_check = BRANCH_HALT,
5456	.clkr = {
5457		.enable_reg = 0x17288,
5458		.enable_mask = BIT(0),
5459		.hw.init = &(const struct clk_init_data) {
5460			.name = "gcc_usb3_mp_phy_aux_clk",
5461			.parent_hws = (const struct clk_hw*[]) {
5462				&gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
5463			},
5464			.num_parents = 1,
5465			.flags = CLK_SET_RATE_PARENT,
5466			.ops = &clk_branch2_ops,
5467		},
5468	},
5469};
5470
5471static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {
5472	.halt_reg = 0x1728c,
5473	.halt_check = BRANCH_HALT,
5474	.clkr = {
5475		.enable_reg = 0x1728c,
5476		.enable_mask = BIT(0),
5477		.hw.init = &(const struct clk_init_data) {
5478			.name = "gcc_usb3_mp_phy_com_aux_clk",
5479			.parent_hws = (const struct clk_hw*[]) {
5480				&gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
5481			},
5482			.num_parents = 1,
5483			.flags = CLK_SET_RATE_PARENT,
5484			.ops = &clk_branch2_ops,
5485		},
5486	},
5487};
5488
5489static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {
5490	.halt_reg = 0x17290,
5491	.halt_check = BRANCH_HALT_SKIP,
5492	.clkr = {
5493		.enable_reg = 0x17290,
5494		.enable_mask = BIT(0),
5495		.hw.init = &(const struct clk_init_data) {
5496			.name = "gcc_usb3_mp_phy_pipe_0_clk",
5497			.ops = &clk_branch2_ops,
5498		},
5499	},
5500};
5501
5502static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {
5503	.halt_reg = 0x17298,
5504	.halt_check = BRANCH_HALT_SKIP,
5505	.clkr = {
5506		.enable_reg = 0x17298,
5507		.enable_mask = BIT(0),
5508		.hw.init = &(const struct clk_init_data) {
5509			.name = "gcc_usb3_mp_phy_pipe_1_clk",
5510			.ops = &clk_branch2_ops,
5511		},
5512	},
5513};
5514
5515static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
5516	.halt_reg = 0x39060,
5517	.halt_check = BRANCH_HALT,
5518	.clkr = {
5519		.enable_reg = 0x39060,
5520		.enable_mask = BIT(0),
5521		.hw.init = &(const struct clk_init_data) {
5522			.name = "gcc_usb3_prim_phy_aux_clk",
5523			.parent_hws = (const struct clk_hw*[]) {
5524				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
5525			},
5526			.num_parents = 1,
5527			.flags = CLK_SET_RATE_PARENT,
5528			.ops = &clk_branch2_ops,
5529		},
5530	},
5531};
5532
5533static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
5534	.halt_reg = 0x39064,
5535	.halt_check = BRANCH_HALT,
5536	.clkr = {
5537		.enable_reg = 0x39064,
5538		.enable_mask = BIT(0),
5539		.hw.init = &(const struct clk_init_data) {
5540			.name = "gcc_usb3_prim_phy_com_aux_clk",
5541			.parent_hws = (const struct clk_hw*[]) {
5542				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
5543			},
5544			.num_parents = 1,
5545			.flags = CLK_SET_RATE_PARENT,
5546			.ops = &clk_branch2_ops,
5547		},
5548	},
5549};
5550
5551static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
5552	.reg = 0x3906c,
5553	.shift = 0,
5554	.width = 2,
5555	.parent_map = gcc_parent_map_10,
5556	.clkr = {
5557		.hw.init = &(struct clk_init_data){
5558			.name = "gcc_usb3_prim_phy_pipe_clk_src",
5559			.parent_data = gcc_parent_data_10,
5560			.num_parents = ARRAY_SIZE(gcc_parent_data_10),
5561			.ops = &clk_regmap_mux_closest_ops,
5562		},
5563	},
5564};
5565
5566static const struct parent_map gcc_parent_map_34[] = {
5567	{ P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },
5568	{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
5569	{ P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 3 },
5570};
5571
5572static const struct clk_parent_data gcc_parent_data_34[] = {
5573	{ .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw },
5574	{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
5575	{ .index = DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC },
5576};
5577
5578static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = {
5579	.reg = 0x39070,
5580	.shift = 0,
5581	.width = 2,
5582	.parent_map = gcc_parent_map_34,
5583	.clkr = {
5584		.hw.init = &(const struct clk_init_data) {
5585			.name = "gcc_usb34_prim_phy_pipe_clk_src",
5586			.parent_data = gcc_parent_data_34,
5587			.num_parents = ARRAY_SIZE(gcc_parent_data_34),
5588			.ops = &clk_regmap_mux_closest_ops,
5589		},
5590	},
5591};
5592
5593static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
5594	.halt_reg = 0x39068,
5595	.halt_check = BRANCH_HALT_SKIP,
5596	.hwcg_reg = 0x39068,
5597	.hwcg_bit = 1,
5598	.clkr = {
5599		.enable_reg = 0x39068,
5600		.enable_mask = BIT(0),
5601		.hw.init = &(const struct clk_init_data) {
5602			.name = "gcc_usb3_prim_phy_pipe_clk",
5603			.parent_hws = (const struct clk_hw*[]) {
5604				&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
5605			},
5606			.num_parents = 1,
5607			.flags = CLK_SET_RATE_PARENT,
5608			.ops = &clk_branch2_ops,
5609		},
5610	},
5611};
5612
5613static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
5614	.halt_reg = 0xa1060,
5615	.halt_check = BRANCH_HALT,
5616	.clkr = {
5617		.enable_reg = 0xa1060,
5618		.enable_mask = BIT(0),
5619		.hw.init = &(const struct clk_init_data) {
5620			.name = "gcc_usb3_sec_phy_aux_clk",
5621			.parent_hws = (const struct clk_hw*[]) {
5622				&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
5623			},
5624			.num_parents = 1,
5625			.flags = CLK_SET_RATE_PARENT,
5626			.ops = &clk_branch2_ops,
5627		},
5628	},
5629};
5630
5631static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
5632	.halt_reg = 0xa1064,
5633	.halt_check = BRANCH_HALT,
5634	.clkr = {
5635		.enable_reg = 0xa1064,
5636		.enable_mask = BIT(0),
5637		.hw.init = &(const struct clk_init_data) {
5638			.name = "gcc_usb3_sec_phy_com_aux_clk",
5639			.parent_hws = (const struct clk_hw*[]) {
5640				&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
5641			},
5642			.num_parents = 1,
5643			.flags = CLK_SET_RATE_PARENT,
5644			.ops = &clk_branch2_ops,
5645		},
5646	},
5647};
5648
5649static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
5650	.reg = 0xa106c,
5651	.shift = 0,
5652	.width = 2,
5653	.parent_map = gcc_parent_map_11,
5654	.clkr = {
5655		.hw.init = &(struct clk_init_data){
5656			.name = "gcc_usb3_sec_phy_pipe_clk_src",
5657			.parent_data = gcc_parent_data_11,
5658			.num_parents = ARRAY_SIZE(gcc_parent_data_11),
5659			.ops = &clk_regmap_mux_closest_ops,
5660		},
5661	},
5662};
5663
5664static const struct parent_map gcc_parent_map_35[] = {
5665	{ P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 },
5666	{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
5667	{ P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 },
5668};
5669
5670static const struct clk_parent_data gcc_parent_data_35[] = {
5671	{ .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw },
5672	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
5673	{ .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC },
5674};
5675
5676static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = {
5677	.reg = 0xa1070,
5678	.shift = 0,
5679	.width = 2,
5680	.parent_map = gcc_parent_map_35,
5681	.clkr = {
5682		.hw.init = &(const struct clk_init_data) {
5683			.name = "gcc_usb34_sec_phy_pipe_clk_src",
5684			.parent_data = gcc_parent_data_35,
5685			.num_parents = ARRAY_SIZE(gcc_parent_data_35),
5686			.ops = &clk_regmap_mux_closest_ops,
5687		},
5688	},
5689};
5690
5691static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
5692	.halt_reg = 0xa1068,
5693	.halt_check = BRANCH_HALT_SKIP,
5694	.hwcg_reg = 0xa1068,
5695	.hwcg_bit = 1,
5696	.clkr = {
5697		.enable_reg = 0xa1068,
5698		.enable_mask = BIT(0),
5699		.hw.init = &(const struct clk_init_data) {
5700			.name = "gcc_usb3_sec_phy_pipe_clk",
5701			.parent_hws = (const struct clk_hw*[]) {
5702				&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
5703			},
5704			.num_parents = 1,
5705			.flags = CLK_SET_RATE_PARENT,
5706			.ops = &clk_branch2_ops,
5707		},
5708	},
5709};
5710
5711static struct clk_branch gcc_usb3_tert_phy_aux_clk = {
5712	.halt_reg = 0xa2060,
5713	.halt_check = BRANCH_HALT,
5714	.clkr = {
5715		.enable_reg = 0xa2060,
5716		.enable_mask = BIT(0),
5717		.hw.init = &(const struct clk_init_data) {
5718			.name = "gcc_usb3_tert_phy_aux_clk",
5719			.parent_hws = (const struct clk_hw*[]) {
5720				&gcc_usb3_tert_phy_aux_clk_src.clkr.hw,
5721			},
5722			.num_parents = 1,
5723			.flags = CLK_SET_RATE_PARENT,
5724			.ops = &clk_branch2_ops,
5725		},
5726	},
5727};
5728
5729static struct clk_branch gcc_usb3_tert_phy_com_aux_clk = {
5730	.halt_reg = 0xa2064,
5731	.halt_check = BRANCH_HALT,
5732	.clkr = {
5733		.enable_reg = 0xa2064,
5734		.enable_mask = BIT(0),
5735		.hw.init = &(const struct clk_init_data) {
5736			.name = "gcc_usb3_tert_phy_com_aux_clk",
5737			.parent_hws = (const struct clk_hw*[]) {
5738				&gcc_usb3_tert_phy_aux_clk_src.clkr.hw,
5739			},
5740			.num_parents = 1,
5741			.flags = CLK_SET_RATE_PARENT,
5742			.ops = &clk_branch2_ops,
5743		},
5744	},
5745};
5746
5747static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = {
5748	.reg = 0xa206c,
5749	.shift = 0,
5750	.width = 2,
5751	.parent_map = gcc_parent_map_12,
5752	.clkr = {
5753		.hw.init = &(struct clk_init_data){
5754			.name = "gcc_usb3_tert_phy_pipe_clk_src",
5755			.parent_data = gcc_parent_data_12,
5756			.num_parents = ARRAY_SIZE(gcc_parent_data_12),
5757			.ops = &clk_regmap_mux_closest_ops,
5758		},
5759	},
5760};
5761
5762static const struct parent_map gcc_parent_map_36[] = {
5763	{ P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 0 },
5764	{ P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
5765	{ P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 3 },
5766};
5767
5768static const struct clk_parent_data gcc_parent_data_36[] = {
5769	{ .hw = &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw },
5770	{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
5771	{ .index = DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC },
5772};
5773
5774static struct clk_regmap_mux gcc_usb34_tert_phy_pipe_clk_src = {
5775	.reg = 0xa2070,
5776	.shift = 0,
5777	.width = 2,
5778	.parent_map = gcc_parent_map_36,
5779	.clkr = {
5780		.hw.init = &(const struct clk_init_data) {
5781			.name = "gcc_usb34_tert_phy_pipe_clk_src",
5782			.parent_data = gcc_parent_data_36,
5783			.num_parents = ARRAY_SIZE(gcc_parent_data_36),
5784			.ops = &clk_regmap_mux_closest_ops,
5785		},
5786	},
5787};
5788
5789static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
5790	.halt_reg = 0xa2068,
5791	.halt_check = BRANCH_HALT_SKIP,
5792	.hwcg_reg = 0xa2068,
5793	.hwcg_bit = 1,
5794	.clkr = {
5795		.enable_reg = 0xa2068,
5796		.enable_mask = BIT(0),
5797		.hw.init = &(const struct clk_init_data) {
5798			.name = "gcc_usb3_tert_phy_pipe_clk",
5799			.parent_hws = (const struct clk_hw*[]) {
5800				&gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
5801			},
5802			.num_parents = 1,
5803			.flags = CLK_SET_RATE_PARENT,
5804			.ops = &clk_branch2_ops,
5805		},
5806	},
5807};
5808
5809static struct clk_branch gcc_usb4_0_cfg_ahb_clk = {
5810	.halt_reg = 0x9f0a8,
5811	.halt_check = BRANCH_HALT_VOTED,
5812	.hwcg_reg = 0x9f0a8,
5813	.hwcg_bit = 1,
5814	.clkr = {
5815		.enable_reg = 0x9f0a8,
5816		.enable_mask = BIT(0),
5817		.hw.init = &(const struct clk_init_data) {
5818			.name = "gcc_usb4_0_cfg_ahb_clk",
5819			.ops = &clk_branch2_ops,
5820		},
5821	},
5822};
5823
5824static struct clk_branch gcc_usb4_0_dp0_clk = {
5825	.halt_reg = 0x9f060,
5826	.halt_check = BRANCH_HALT_SKIP,
5827	.clkr = {
5828		.enable_reg = 0x9f060,
5829		.enable_mask = BIT(0),
5830		.hw.init = &(const struct clk_init_data) {
5831			.name = "gcc_usb4_0_dp0_clk",
5832			.parent_hws = (const struct clk_hw*[]) {
5833				&gcc_usb4_0_phy_dp0_clk_src.clkr.hw,
5834			},
5835			.num_parents = 1,
5836			.flags = CLK_SET_RATE_PARENT,
5837			.ops = &clk_branch2_ops,
5838		},
5839	},
5840};
5841
5842static struct clk_branch gcc_usb4_0_dp1_clk = {
5843	.halt_reg = 0x9f108,
5844	.halt_check = BRANCH_HALT_SKIP,
5845	.clkr = {
5846		.enable_reg = 0x9f108,
5847		.enable_mask = BIT(0),
5848		.hw.init = &(const struct clk_init_data) {
5849			.name = "gcc_usb4_0_dp1_clk",
5850			.parent_hws = (const struct clk_hw*[]) {
5851				&gcc_usb4_0_phy_dp1_clk_src.clkr.hw,
5852			},
5853			.num_parents = 1,
5854			.flags = CLK_SET_RATE_PARENT,
5855			.ops = &clk_branch2_ops,
5856		},
5857	},
5858};
5859
5860static struct clk_branch gcc_usb4_0_master_clk = {
5861	.halt_reg = 0x9f018,
5862	.halt_check = BRANCH_HALT,
5863	.clkr = {
5864		.enable_reg = 0x9f018,
5865		.enable_mask = BIT(0),
5866		.hw.init = &(const struct clk_init_data) {
5867			.name = "gcc_usb4_0_master_clk",
5868			.parent_hws = (const struct clk_hw*[]) {
5869				&gcc_usb4_0_master_clk_src.clkr.hw,
5870			},
5871			.num_parents = 1,
5872			.flags = CLK_SET_RATE_PARENT,
5873			.ops = &clk_branch2_ops,
5874		},
5875	},
5876};
5877
5878static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = {
5879	.halt_reg = 0x9f0d8,
5880	.halt_check = BRANCH_HALT_SKIP,
5881	.clkr = {
5882		.enable_reg = 0x9f0d8,
5883		.enable_mask = BIT(0),
5884		.hw.init = &(const struct clk_init_data) {
5885			.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk",
5886			.parent_hws = (const struct clk_hw*[]) {
5887				&gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr.hw,
5888			},
5889			.num_parents = 1,
5890			.flags = CLK_SET_RATE_PARENT,
5891			.ops = &clk_branch2_ops,
5892		},
5893	},
5894};
5895
5896static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = {
5897	.halt_reg = 0x9f048,
5898	.halt_check = BRANCH_HALT_SKIP,
5899	.clkr = {
5900		.enable_reg = 0x52010,
5901		.enable_mask = BIT(19),
5902		.hw.init = &(const struct clk_init_data) {
5903			.name = "gcc_usb4_0_phy_pcie_pipe_clk",
5904			.parent_hws = (const struct clk_hw*[]) {
5905				&gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
5906			},
5907			.num_parents = 1,
5908			.flags = CLK_SET_RATE_PARENT,
5909			.ops = &clk_branch2_ops,
5910		},
5911	},
5912};
5913
5914static struct clk_branch gcc_usb4_0_phy_rx0_clk = {
5915	.halt_reg = 0x9f0b0,
5916	.halt_check = BRANCH_HALT_SKIP,
5917	.clkr = {
5918		.enable_reg = 0x9f0b0,
5919		.enable_mask = BIT(0),
5920		.hw.init = &(const struct clk_init_data) {
5921			.name = "gcc_usb4_0_phy_rx0_clk",
5922			.parent_hws = (const struct clk_hw*[]) {
5923				&gcc_usb4_0_phy_rx0_clk_src.clkr.hw,
5924			},
5925			.num_parents = 1,
5926			.flags = CLK_SET_RATE_PARENT,
5927			.ops = &clk_branch2_ops,
5928		},
5929	},
5930};
5931
5932static struct clk_branch gcc_usb4_0_phy_rx1_clk = {
5933	.halt_reg = 0x9f0c0,
5934	.halt_check = BRANCH_HALT_SKIP,
5935	.clkr = {
5936		.enable_reg = 0x9f0c0,
5937		.enable_mask = BIT(0),
5938		.hw.init = &(const struct clk_init_data) {
5939			.name = "gcc_usb4_0_phy_rx1_clk",
5940			.parent_hws = (const struct clk_hw*[]) {
5941				&gcc_usb4_0_phy_rx1_clk_src.clkr.hw,
5942			},
5943			.num_parents = 1,
5944			.flags = CLK_SET_RATE_PARENT,
5945			.ops = &clk_branch2_ops,
5946		},
5947	},
5948};
5949
5950static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = {
5951	.halt_reg = 0x9f0a4,
5952	.halt_check = BRANCH_HALT_SKIP,
5953	.hwcg_reg = 0x9f0a4,
5954	.hwcg_bit = 1,
5955	.clkr = {
5956		.enable_reg = 0x9f0a4,
5957		.enable_mask = BIT(0),
5958		.hw.init = &(const struct clk_init_data) {
5959			.name = "gcc_usb4_0_phy_usb_pipe_clk",
5960			.parent_hws = (const struct clk_hw*[]) {
5961				&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
5962			},
5963			.num_parents = 1,
5964			.flags = CLK_SET_RATE_PARENT,
5965			.ops = &clk_branch2_ops,
5966		},
5967	},
5968};
5969
5970static struct clk_branch gcc_usb4_0_sb_if_clk = {
5971	.halt_reg = 0x9f044,
5972	.halt_check = BRANCH_HALT,
5973	.clkr = {
5974		.enable_reg = 0x9f044,
5975		.enable_mask = BIT(0),
5976		.hw.init = &(const struct clk_init_data) {
5977			.name = "gcc_usb4_0_sb_if_clk",
5978			.parent_hws = (const struct clk_hw*[]) {
5979				&gcc_usb4_0_sb_if_clk_src.clkr.hw,
5980			},
5981			.num_parents = 1,
5982			.flags = CLK_SET_RATE_PARENT,
5983			.ops = &clk_branch2_ops,
5984		},
5985	},
5986};
5987
5988static struct clk_branch gcc_usb4_0_sys_clk = {
5989	.halt_reg = 0x9f054,
5990	.halt_check = BRANCH_HALT,
5991	.clkr = {
5992		.enable_reg = 0x9f054,
5993		.enable_mask = BIT(0),
5994		.hw.init = &(const struct clk_init_data) {
5995			.name = "gcc_usb4_0_sys_clk",
5996			.parent_hws = (const struct clk_hw*[]) {
5997				&gcc_usb4_0_phy_sys_clk_src.clkr.hw,
5998			},
5999			.num_parents = 1,
6000			.flags = CLK_SET_RATE_PARENT,
6001			.ops = &clk_branch2_ops,
6002		},
6003	},
6004};
6005
6006static struct clk_branch gcc_usb4_0_tmu_clk = {
6007	.halt_reg = 0x9f088,
6008	.halt_check = BRANCH_HALT_VOTED,
6009	.hwcg_reg = 0x9f088,
6010	.hwcg_bit = 1,
6011	.clkr = {
6012		.enable_reg = 0x9f088,
6013		.enable_mask = BIT(0),
6014		.hw.init = &(const struct clk_init_data) {
6015			.name = "gcc_usb4_0_tmu_clk",
6016			.parent_hws = (const struct clk_hw*[]) {
6017				&gcc_usb4_0_tmu_clk_src.clkr.hw,
6018			},
6019			.num_parents = 1,
6020			.flags = CLK_SET_RATE_PARENT,
6021			.ops = &clk_branch2_ops,
6022		},
6023	},
6024};
6025
6026static struct clk_branch gcc_usb4_1_cfg_ahb_clk = {
6027	.halt_reg = 0x2b0a8,
6028	.halt_check = BRANCH_HALT_VOTED,
6029	.hwcg_reg = 0x2b0a8,
6030	.hwcg_bit = 1,
6031	.clkr = {
6032		.enable_reg = 0x2b0a8,
6033		.enable_mask = BIT(0),
6034		.hw.init = &(const struct clk_init_data) {
6035			.name = "gcc_usb4_1_cfg_ahb_clk",
6036			.ops = &clk_branch2_ops,
6037		},
6038	},
6039};
6040
6041static struct clk_branch gcc_usb4_1_dp0_clk = {
6042	.halt_reg = 0x2b060,
6043	.halt_check = BRANCH_HALT_SKIP,
6044	.clkr = {
6045		.enable_reg = 0x2b060,
6046		.enable_mask = BIT(0),
6047		.hw.init = &(const struct clk_init_data) {
6048			.name = "gcc_usb4_1_dp0_clk",
6049			.parent_hws = (const struct clk_hw*[]) {
6050				&gcc_usb4_1_phy_dp0_clk_src.clkr.hw,
6051			},
6052			.num_parents = 1,
6053			.flags = CLK_SET_RATE_PARENT,
6054			.ops = &clk_branch2_ops,
6055		},
6056	},
6057};
6058
6059static struct clk_branch gcc_usb4_1_dp1_clk = {
6060	.halt_reg = 0x2b108,
6061	.halt_check = BRANCH_HALT_SKIP,
6062	.clkr = {
6063		.enable_reg = 0x2b108,
6064		.enable_mask = BIT(0),
6065		.hw.init = &(const struct clk_init_data) {
6066			.name = "gcc_usb4_1_dp1_clk",
6067			.parent_hws = (const struct clk_hw*[]) {
6068				&gcc_usb4_1_phy_dp1_clk_src.clkr.hw,
6069			},
6070			.num_parents = 1,
6071			.flags = CLK_SET_RATE_PARENT,
6072			.ops = &clk_branch2_ops,
6073		},
6074	},
6075};
6076
6077static struct clk_branch gcc_usb4_1_master_clk = {
6078	.halt_reg = 0x2b018,
6079	.halt_check = BRANCH_HALT,
6080	.clkr = {
6081		.enable_reg = 0x2b018,
6082		.enable_mask = BIT(0),
6083		.hw.init = &(const struct clk_init_data) {
6084			.name = "gcc_usb4_1_master_clk",
6085			.parent_hws = (const struct clk_hw*[]) {
6086				&gcc_usb4_1_master_clk_src.clkr.hw,
6087			},
6088			.num_parents = 1,
6089			.flags = CLK_SET_RATE_PARENT,
6090			.ops = &clk_branch2_ops,
6091		},
6092	},
6093};
6094
6095static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
6096	.halt_reg = 0x2b0d8,
6097	.halt_check = BRANCH_HALT_SKIP,
6098	.clkr = {
6099		.enable_reg = 0x2b0d8,
6100		.enable_mask = BIT(0),
6101		.hw.init = &(const struct clk_init_data) {
6102			.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk",
6103			.parent_hws = (const struct clk_hw*[]) {
6104				&gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw,
6105			},
6106			.num_parents = 1,
6107			.flags = CLK_SET_RATE_PARENT,
6108			.ops = &clk_branch2_ops,
6109		},
6110	},
6111};
6112
6113static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
6114	.halt_reg = 0x2b048,
6115	.halt_check = BRANCH_HALT_SKIP,
6116	.clkr = {
6117		.enable_reg = 0x52028,
6118		.enable_mask = BIT(0),
6119		.hw.init = &(const struct clk_init_data) {
6120			.name = "gcc_usb4_1_phy_pcie_pipe_clk",
6121			.parent_hws = (const struct clk_hw*[]) {
6122				&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
6123			},
6124			.num_parents = 1,
6125			.flags = CLK_SET_RATE_PARENT,
6126			.ops = &clk_branch2_ops,
6127		},
6128	},
6129};
6130
6131static struct clk_branch gcc_usb4_1_phy_rx0_clk = {
6132	.halt_reg = 0x2b0b0,
6133	.halt_check = BRANCH_HALT_SKIP,
6134	.clkr = {
6135		.enable_reg = 0x2b0b0,
6136		.enable_mask = BIT(0),
6137		.hw.init = &(const struct clk_init_data) {
6138			.name = "gcc_usb4_1_phy_rx0_clk",
6139			.parent_hws = (const struct clk_hw*[]) {
6140				&gcc_usb4_1_phy_rx0_clk_src.clkr.hw,
6141			},
6142			.num_parents = 1,
6143			.flags = CLK_SET_RATE_PARENT,
6144			.ops = &clk_branch2_ops,
6145		},
6146	},
6147};
6148
6149static struct clk_branch gcc_usb4_1_phy_rx1_clk = {
6150	.halt_reg = 0x2b0c0,
6151	.halt_check = BRANCH_HALT_SKIP,
6152	.clkr = {
6153		.enable_reg = 0x2b0c0,
6154		.enable_mask = BIT(0),
6155		.hw.init = &(const struct clk_init_data) {
6156			.name = "gcc_usb4_1_phy_rx1_clk",
6157			.parent_hws = (const struct clk_hw*[]) {
6158				&gcc_usb4_1_phy_rx1_clk_src.clkr.hw,
6159			},
6160			.num_parents = 1,
6161			.flags = CLK_SET_RATE_PARENT,
6162			.ops = &clk_branch2_ops,
6163		},
6164	},
6165};
6166
6167static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {
6168	.halt_reg = 0x2b0a4,
6169	.halt_check = BRANCH_HALT_SKIP,
6170	.hwcg_reg = 0x2b0a4,
6171	.hwcg_bit = 1,
6172	.clkr = {
6173		.enable_reg = 0x2b0a4,
6174		.enable_mask = BIT(0),
6175		.hw.init = &(const struct clk_init_data) {
6176			.name = "gcc_usb4_1_phy_usb_pipe_clk",
6177			.parent_hws = (const struct clk_hw*[]) {
6178				&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
6179			},
6180			.num_parents = 1,
6181			.flags = CLK_SET_RATE_PARENT,
6182			.ops = &clk_branch2_ops,
6183		},
6184	},
6185};
6186
6187static struct clk_branch gcc_usb4_1_sb_if_clk = {
6188	.halt_reg = 0x2b044,
6189	.halt_check = BRANCH_HALT,
6190	.clkr = {
6191		.enable_reg = 0x2b044,
6192		.enable_mask = BIT(0),
6193		.hw.init = &(const struct clk_init_data) {
6194			.name = "gcc_usb4_1_sb_if_clk",
6195			.parent_hws = (const struct clk_hw*[]) {
6196				&gcc_usb4_1_sb_if_clk_src.clkr.hw,
6197			},
6198			.num_parents = 1,
6199			.flags = CLK_SET_RATE_PARENT,
6200			.ops = &clk_branch2_ops,
6201		},
6202	},
6203};
6204
6205static struct clk_branch gcc_usb4_1_sys_clk = {
6206	.halt_reg = 0x2b054,
6207	.halt_check = BRANCH_HALT,
6208	.clkr = {
6209		.enable_reg = 0x2b054,
6210		.enable_mask = BIT(0),
6211		.hw.init = &(const struct clk_init_data) {
6212			.name = "gcc_usb4_1_sys_clk",
6213			.parent_hws = (const struct clk_hw*[]) {
6214				&gcc_usb4_1_phy_sys_clk_src.clkr.hw,
6215			},
6216			.num_parents = 1,
6217			.flags = CLK_SET_RATE_PARENT,
6218			.ops = &clk_branch2_ops,
6219		},
6220	},
6221};
6222
6223static struct clk_branch gcc_usb4_1_tmu_clk = {
6224	.halt_reg = 0x2b088,
6225	.halt_check = BRANCH_HALT_VOTED,
6226	.hwcg_reg = 0x2b088,
6227	.hwcg_bit = 1,
6228	.clkr = {
6229		.enable_reg = 0x2b088,
6230		.enable_mask = BIT(0),
6231		.hw.init = &(const struct clk_init_data) {
6232			.name = "gcc_usb4_1_tmu_clk",
6233			.parent_hws = (const struct clk_hw*[]) {
6234				&gcc_usb4_1_tmu_clk_src.clkr.hw,
6235			},
6236			.num_parents = 1,
6237			.flags = CLK_SET_RATE_PARENT,
6238			.ops = &clk_branch2_ops,
6239		},
6240	},
6241};
6242
6243static struct clk_branch gcc_usb4_2_cfg_ahb_clk = {
6244	.halt_reg = 0x110a8,
6245	.halt_check = BRANCH_HALT_VOTED,
6246	.hwcg_reg = 0x110a8,
6247	.hwcg_bit = 1,
6248	.clkr = {
6249		.enable_reg = 0x110a8,
6250		.enable_mask = BIT(0),
6251		.hw.init = &(const struct clk_init_data) {
6252			.name = "gcc_usb4_2_cfg_ahb_clk",
6253			.ops = &clk_branch2_ops,
6254		},
6255	},
6256};
6257
6258static struct clk_branch gcc_usb4_2_dp0_clk = {
6259	.halt_reg = 0x11060,
6260	.halt_check = BRANCH_HALT_SKIP,
6261	.clkr = {
6262		.enable_reg = 0x11060,
6263		.enable_mask = BIT(0),
6264		.hw.init = &(const struct clk_init_data) {
6265			.name = "gcc_usb4_2_dp0_clk",
6266			.parent_hws = (const struct clk_hw*[]) {
6267				&gcc_usb4_2_phy_dp0_clk_src.clkr.hw,
6268			},
6269			.num_parents = 1,
6270			.flags = CLK_SET_RATE_PARENT,
6271			.ops = &clk_branch2_ops,
6272		},
6273	},
6274};
6275
6276static struct clk_branch gcc_usb4_2_dp1_clk = {
6277	.halt_reg = 0x11108,
6278	.halt_check = BRANCH_HALT_SKIP,
6279	.clkr = {
6280		.enable_reg = 0x11108,
6281		.enable_mask = BIT(0),
6282		.hw.init = &(const struct clk_init_data) {
6283			.name = "gcc_usb4_2_dp1_clk",
6284			.parent_hws = (const struct clk_hw*[]) {
6285				&gcc_usb4_2_phy_dp1_clk_src.clkr.hw,
6286			},
6287			.num_parents = 1,
6288			.flags = CLK_SET_RATE_PARENT,
6289			.ops = &clk_branch2_ops,
6290		},
6291	},
6292};
6293
6294static struct clk_branch gcc_usb4_2_master_clk = {
6295	.halt_reg = 0x11018,
6296	.halt_check = BRANCH_HALT,
6297	.clkr = {
6298		.enable_reg = 0x11018,
6299		.enable_mask = BIT(0),
6300		.hw.init = &(const struct clk_init_data) {
6301			.name = "gcc_usb4_2_master_clk",
6302			.parent_hws = (const struct clk_hw*[]) {
6303				&gcc_usb4_2_master_clk_src.clkr.hw,
6304			},
6305			.num_parents = 1,
6306			.flags = CLK_SET_RATE_PARENT,
6307			.ops = &clk_branch2_ops,
6308		},
6309	},
6310};
6311
6312static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = {
6313	.halt_reg = 0x110d8,
6314	.halt_check = BRANCH_HALT_SKIP,
6315	.clkr = {
6316		.enable_reg = 0x110d8,
6317		.enable_mask = BIT(0),
6318		.hw.init = &(const struct clk_init_data) {
6319			.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk",
6320			.parent_hws = (const struct clk_hw*[]) {
6321				&gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr.hw,
6322			},
6323			.num_parents = 1,
6324			.flags = CLK_SET_RATE_PARENT,
6325			.ops = &clk_branch2_ops,
6326		},
6327	},
6328};
6329
6330static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = {
6331	.halt_reg = 0x11048,
6332	.halt_check = BRANCH_HALT_SKIP,
6333	.clkr = {
6334		.enable_reg = 0x52028,
6335		.enable_mask = BIT(1),
6336		.hw.init = &(const struct clk_init_data) {
6337			.name = "gcc_usb4_2_phy_pcie_pipe_clk",
6338			.parent_hws = (const struct clk_hw*[]) {
6339				&gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
6340			},
6341			.num_parents = 1,
6342			.flags = CLK_SET_RATE_PARENT,
6343			.ops = &clk_branch2_ops,
6344		},
6345	},
6346};
6347
6348static struct clk_branch gcc_usb4_2_phy_rx0_clk = {
6349	.halt_reg = 0x110b0,
6350	.halt_check = BRANCH_HALT_SKIP,
6351	.clkr = {
6352		.enable_reg = 0x110b0,
6353		.enable_mask = BIT(0),
6354		.hw.init = &(const struct clk_init_data) {
6355			.name = "gcc_usb4_2_phy_rx0_clk",
6356			.parent_hws = (const struct clk_hw*[]) {
6357				&gcc_usb4_2_phy_rx0_clk_src.clkr.hw,
6358			},
6359			.num_parents = 1,
6360			.flags = CLK_SET_RATE_PARENT,
6361			.ops = &clk_branch2_ops,
6362		},
6363	},
6364};
6365
6366static struct clk_branch gcc_usb4_2_phy_rx1_clk = {
6367	.halt_reg = 0x110c0,
6368	.halt_check = BRANCH_HALT_SKIP,
6369	.clkr = {
6370		.enable_reg = 0x110c0,
6371		.enable_mask = BIT(0),
6372		.hw.init = &(const struct clk_init_data) {
6373			.name = "gcc_usb4_2_phy_rx1_clk",
6374			.parent_hws = (const struct clk_hw*[]) {
6375				&gcc_usb4_2_phy_rx1_clk_src.clkr.hw,
6376			},
6377			.num_parents = 1,
6378			.flags = CLK_SET_RATE_PARENT,
6379			.ops = &clk_branch2_ops,
6380		},
6381	},
6382};
6383
6384static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = {
6385	.halt_reg = 0x110a4,
6386	.halt_check = BRANCH_HALT_SKIP,
6387	.hwcg_reg = 0x110a4,
6388	.hwcg_bit = 1,
6389	.clkr = {
6390		.enable_reg = 0x110a4,
6391		.enable_mask = BIT(0),
6392		.hw.init = &(const struct clk_init_data) {
6393			.name = "gcc_usb4_2_phy_usb_pipe_clk",
6394			.parent_hws = (const struct clk_hw*[]) {
6395				&gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
6396			},
6397			.num_parents = 1,
6398			.flags = CLK_SET_RATE_PARENT,
6399			.ops = &clk_branch2_ops,
6400		},
6401	},
6402};
6403
6404static struct clk_branch gcc_usb4_2_sb_if_clk = {
6405	.halt_reg = 0x11044,
6406	.halt_check = BRANCH_HALT,
6407	.clkr = {
6408		.enable_reg = 0x11044,
6409		.enable_mask = BIT(0),
6410		.hw.init = &(const struct clk_init_data) {
6411			.name = "gcc_usb4_2_sb_if_clk",
6412			.parent_hws = (const struct clk_hw*[]) {
6413				&gcc_usb4_2_sb_if_clk_src.clkr.hw,
6414			},
6415			.num_parents = 1,
6416			.flags = CLK_SET_RATE_PARENT,
6417			.ops = &clk_branch2_ops,
6418		},
6419	},
6420};
6421
6422static struct clk_branch gcc_usb4_2_sys_clk = {
6423	.halt_reg = 0x11054,
6424	.halt_check = BRANCH_HALT,
6425	.clkr = {
6426		.enable_reg = 0x11054,
6427		.enable_mask = BIT(0),
6428		.hw.init = &(const struct clk_init_data) {
6429			.name = "gcc_usb4_2_sys_clk",
6430			.ops = &clk_branch2_ops,
6431		},
6432	},
6433};
6434
6435static struct clk_branch gcc_usb4_2_tmu_clk = {
6436	.halt_reg = 0x11088,
6437	.halt_check = BRANCH_HALT_VOTED,
6438	.hwcg_reg = 0x11088,
6439	.hwcg_bit = 1,
6440	.clkr = {
6441		.enable_reg = 0x11088,
6442		.enable_mask = BIT(0),
6443		.hw.init = &(const struct clk_init_data) {
6444			.name = "gcc_usb4_2_tmu_clk",
6445			.parent_hws = (const struct clk_hw*[]) {
6446				&gcc_usb4_2_tmu_clk_src.clkr.hw,
6447			},
6448			.num_parents = 1,
6449			.flags = CLK_SET_RATE_PARENT,
6450			.ops = &clk_branch2_ops,
6451		},
6452	},
6453};
6454
6455static struct clk_branch gcc_video_axi0_clk = {
6456	.halt_reg = 0x32018,
6457	.halt_check = BRANCH_HALT_SKIP,
6458	.hwcg_reg = 0x32018,
6459	.hwcg_bit = 1,
6460	.clkr = {
6461		.enable_reg = 0x32018,
6462		.enable_mask = BIT(0),
6463		.hw.init = &(const struct clk_init_data) {
6464			.name = "gcc_video_axi0_clk",
6465			.ops = &clk_branch2_ops,
6466		},
6467	},
6468};
6469
6470static struct clk_branch gcc_video_axi1_clk = {
6471	.halt_reg = 0x32024,
6472	.halt_check = BRANCH_HALT_SKIP,
6473	.hwcg_reg = 0x32024,
6474	.hwcg_bit = 1,
6475	.clkr = {
6476		.enable_reg = 0x32024,
6477		.enable_mask = BIT(0),
6478		.hw.init = &(const struct clk_init_data) {
6479			.name = "gcc_video_axi1_clk",
6480			.ops = &clk_branch2_ops,
6481		},
6482	},
6483};
6484
6485static struct gdsc gcc_pcie_0_tunnel_gdsc = {
6486	.gdscr = 0xa0004,
6487	.en_rest_wait_val = 0x2,
6488	.en_few_wait_val = 0x2,
6489	.clk_dis_wait_val = 0xf,
6490	.pd = {
6491		.name = "gcc_pcie_0_tunnel_gdsc",
6492	},
6493	.pwrsts = PWRSTS_OFF_ON,
6494	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6495};
6496
6497static struct gdsc gcc_pcie_1_tunnel_gdsc = {
6498	.gdscr = 0x2c004,
6499	.en_rest_wait_val = 0x2,
6500	.en_few_wait_val = 0x2,
6501	.clk_dis_wait_val = 0xf,
6502	.pd = {
6503		.name = "gcc_pcie_1_tunnel_gdsc",
6504	},
6505	.pwrsts = PWRSTS_OFF_ON,
6506	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6507};
6508
6509static struct gdsc gcc_pcie_2_tunnel_gdsc = {
6510	.gdscr = 0x13004,
6511	.en_rest_wait_val = 0x2,
6512	.en_few_wait_val = 0x2,
6513	.clk_dis_wait_val = 0xf,
6514	.pd = {
6515		.name = "gcc_pcie_2_tunnel_gdsc",
6516	},
6517	.pwrsts = PWRSTS_OFF_ON,
6518	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6519};
6520
6521static struct gdsc gcc_pcie_3_gdsc = {
6522	.gdscr = 0x58004,
6523	.en_rest_wait_val = 0x2,
6524	.en_few_wait_val = 0x2,
6525	.clk_dis_wait_val = 0xf,
6526	.pd = {
6527		.name = "gcc_pcie_3_gdsc",
6528	},
6529	.pwrsts = PWRSTS_OFF_ON,
6530	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6531};
6532
6533static struct gdsc gcc_pcie_3_phy_gdsc = {
6534	.gdscr = 0x3e000,
6535	.en_rest_wait_val = 0x2,
6536	.en_few_wait_val = 0x2,
6537	.clk_dis_wait_val = 0x2,
6538	.pd = {
6539		.name = "gcc_pcie_3_phy_gdsc",
6540	},
6541	.pwrsts = PWRSTS_OFF_ON,
6542	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6543};
6544
6545static struct gdsc gcc_pcie_4_gdsc = {
6546	.gdscr = 0x6b004,
6547	.en_rest_wait_val = 0x2,
6548	.en_few_wait_val = 0x2,
6549	.clk_dis_wait_val = 0xf,
6550	.pd = {
6551		.name = "gcc_pcie_4_gdsc",
6552	},
6553	.pwrsts = PWRSTS_OFF_ON,
6554	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6555};
6556
6557static struct gdsc gcc_pcie_4_phy_gdsc = {
6558	.gdscr = 0x6c000,
6559	.en_rest_wait_val = 0x2,
6560	.en_few_wait_val = 0x2,
6561	.clk_dis_wait_val = 0x2,
6562	.pd = {
6563		.name = "gcc_pcie_4_phy_gdsc",
6564	},
6565	.pwrsts = PWRSTS_OFF_ON,
6566	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6567};
6568
6569static struct gdsc gcc_pcie_5_gdsc = {
6570	.gdscr = 0x2f004,
6571	.en_rest_wait_val = 0x2,
6572	.en_few_wait_val = 0x2,
6573	.clk_dis_wait_val = 0xf,
6574	.pd = {
6575		.name = "gcc_pcie_5_gdsc",
6576	},
6577	.pwrsts = PWRSTS_OFF_ON,
6578	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6579};
6580
6581static struct gdsc gcc_pcie_5_phy_gdsc = {
6582	.gdscr = 0x30000,
6583	.en_rest_wait_val = 0x2,
6584	.en_few_wait_val = 0x2,
6585	.clk_dis_wait_val = 0x2,
6586	.pd = {
6587		.name = "gcc_pcie_5_phy_gdsc",
6588	},
6589	.pwrsts = PWRSTS_OFF_ON,
6590	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6591};
6592
6593static struct gdsc gcc_pcie_6_phy_gdsc = {
6594	.gdscr = 0x8e000,
6595	.en_rest_wait_val = 0x2,
6596	.en_few_wait_val = 0x2,
6597	.clk_dis_wait_val = 0x2,
6598	.pd = {
6599		.name = "gcc_pcie_6_phy_gdsc",
6600	},
6601	.pwrsts = PWRSTS_OFF_ON,
6602	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6603};
6604
6605static struct gdsc gcc_pcie_6a_gdsc = {
6606	.gdscr = 0x31004,
6607	.en_rest_wait_val = 0x2,
6608	.en_few_wait_val = 0x2,
6609	.clk_dis_wait_val = 0xf,
6610	.pd = {
6611		.name = "gcc_pcie_6a_gdsc",
6612	},
6613	.pwrsts = PWRSTS_OFF_ON,
6614	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6615};
6616
6617static struct gdsc gcc_pcie_6b_gdsc = {
6618	.gdscr = 0x8d004,
6619	.en_rest_wait_val = 0x2,
6620	.en_few_wait_val = 0x2,
6621	.clk_dis_wait_val = 0xf,
6622	.pd = {
6623		.name = "gcc_pcie_6b_gdsc",
6624	},
6625	.pwrsts = PWRSTS_OFF_ON,
6626	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6627};
6628
6629static struct gdsc gcc_ufs_mem_phy_gdsc = {
6630	.gdscr = 0x9e000,
6631	.en_rest_wait_val = 0x2,
6632	.en_few_wait_val = 0x2,
6633	.clk_dis_wait_val = 0x2,
6634	.pd = {
6635		.name = "gcc_ufs_mem_phy_gdsc",
6636	},
6637	.pwrsts = PWRSTS_OFF_ON,
6638	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6639};
6640
6641static struct gdsc gcc_ufs_phy_gdsc = {
6642	.gdscr = 0x77004,
6643	.en_rest_wait_val = 0x2,
6644	.en_few_wait_val = 0x2,
6645	.clk_dis_wait_val = 0xf,
6646	.pd = {
6647		.name = "gcc_ufs_phy_gdsc",
6648	},
6649	.pwrsts = PWRSTS_OFF_ON,
6650	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6651};
6652
6653static struct gdsc gcc_usb20_prim_gdsc = {
6654	.gdscr = 0x29004,
6655	.en_rest_wait_val = 0x2,
6656	.en_few_wait_val = 0x2,
6657	.clk_dis_wait_val = 0xf,
6658	.pd = {
6659		.name = "gcc_usb20_prim_gdsc",
6660	},
6661	.pwrsts = PWRSTS_RET_ON,
6662	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6663};
6664
6665static struct gdsc gcc_usb30_mp_gdsc = {
6666	.gdscr = 0x17004,
6667	.en_rest_wait_val = 0x2,
6668	.en_few_wait_val = 0x2,
6669	.clk_dis_wait_val = 0xf,
6670	.pd = {
6671		.name = "gcc_usb30_mp_gdsc",
6672	},
6673	.pwrsts = PWRSTS_RET_ON,
6674	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6675};
6676
6677static struct gdsc gcc_usb30_prim_gdsc = {
6678	.gdscr = 0x39004,
6679	.en_rest_wait_val = 0x2,
6680	.en_few_wait_val = 0x2,
6681	.clk_dis_wait_val = 0xf,
6682	.pd = {
6683		.name = "gcc_usb30_prim_gdsc",
6684	},
6685	.pwrsts = PWRSTS_RET_ON,
6686	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6687};
6688
6689static struct gdsc gcc_usb30_sec_gdsc = {
6690	.gdscr = 0xa1004,
6691	.en_rest_wait_val = 0x2,
6692	.en_few_wait_val = 0x2,
6693	.clk_dis_wait_val = 0xf,
6694	.pd = {
6695		.name = "gcc_usb30_sec_gdsc",
6696	},
6697	.pwrsts = PWRSTS_RET_ON,
6698	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6699};
6700
6701static struct gdsc gcc_usb30_tert_gdsc = {
6702	.gdscr = 0xa2004,
6703	.en_rest_wait_val = 0x2,
6704	.en_few_wait_val = 0x2,
6705	.clk_dis_wait_val = 0xf,
6706	.pd = {
6707		.name = "gcc_usb30_tert_gdsc",
6708	},
6709	.pwrsts = PWRSTS_RET_ON,
6710	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6711};
6712
6713static struct gdsc gcc_usb3_mp_ss0_phy_gdsc = {
6714	.gdscr = 0x1900c,
6715	.en_rest_wait_val = 0x2,
6716	.en_few_wait_val = 0x2,
6717	.clk_dis_wait_val = 0x2,
6718	.pd = {
6719		.name = "gcc_usb3_mp_ss0_phy_gdsc",
6720	},
6721	.pwrsts = PWRSTS_RET_ON,
6722	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6723};
6724
6725static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = {
6726	.gdscr = 0x5400c,
6727	.en_rest_wait_val = 0x2,
6728	.en_few_wait_val = 0x2,
6729	.clk_dis_wait_val = 0x2,
6730	.pd = {
6731		.name = "gcc_usb3_mp_ss1_phy_gdsc",
6732	},
6733	.pwrsts = PWRSTS_RET_ON,
6734	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6735};
6736
6737static struct gdsc gcc_usb4_0_gdsc = {
6738	.gdscr = 0x9f004,
6739	.en_rest_wait_val = 0x2,
6740	.en_few_wait_val = 0x2,
6741	.clk_dis_wait_val = 0xf,
6742	.pd = {
6743		.name = "gcc_usb4_0_gdsc",
6744	},
6745	.pwrsts = PWRSTS_OFF_ON,
6746	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6747};
6748
6749static struct gdsc gcc_usb4_1_gdsc = {
6750	.gdscr = 0x2b004,
6751	.en_rest_wait_val = 0x2,
6752	.en_few_wait_val = 0x2,
6753	.clk_dis_wait_val = 0xf,
6754	.pd = {
6755		.name = "gcc_usb4_1_gdsc",
6756	},
6757	.pwrsts = PWRSTS_OFF_ON,
6758	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6759};
6760
6761static struct gdsc gcc_usb4_2_gdsc = {
6762	.gdscr = 0x11004,
6763	.en_rest_wait_val = 0x2,
6764	.en_few_wait_val = 0x2,
6765	.clk_dis_wait_val = 0xf,
6766	.pd = {
6767		.name = "gcc_usb4_2_gdsc",
6768	},
6769	.pwrsts = PWRSTS_OFF_ON,
6770	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6771};
6772
6773static struct gdsc gcc_usb_0_phy_gdsc = {
6774	.gdscr = 0x50024,
6775	.en_rest_wait_val = 0x2,
6776	.en_few_wait_val = 0x2,
6777	.clk_dis_wait_val = 0x2,
6778	.pd = {
6779		.name = "gcc_usb_0_phy_gdsc",
6780	},
6781	.pwrsts = PWRSTS_RET_ON,
6782	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6783};
6784
6785static struct gdsc gcc_usb_1_phy_gdsc = {
6786	.gdscr = 0x2a024,
6787	.en_rest_wait_val = 0x2,
6788	.en_few_wait_val = 0x2,
6789	.clk_dis_wait_val = 0x2,
6790	.pd = {
6791		.name = "gcc_usb_1_phy_gdsc",
6792	},
6793	.pwrsts = PWRSTS_RET_ON,
6794	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6795};
6796
6797static struct gdsc gcc_usb_2_phy_gdsc = {
6798	.gdscr = 0xa3024,
6799	.en_rest_wait_val = 0x2,
6800	.en_few_wait_val = 0x2,
6801	.clk_dis_wait_val = 0x2,
6802	.pd = {
6803		.name = "gcc_usb_2_phy_gdsc",
6804	},
6805	.pwrsts = PWRSTS_RET_ON,
6806	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6807};
6808
6809static struct clk_regmap *gcc_x1e80100_clocks[] = {
6810	[GCC_AGGRE_NOC_USB_NORTH_AXI_CLK] = &gcc_aggre_noc_usb_north_axi_clk.clkr,
6811	[GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK] = &gcc_aggre_noc_usb_south_axi_clk.clkr,
6812	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
6813	[GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr,
6814	[GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr,
6815	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
6816	[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
6817	[GCC_AGGRE_USB3_TERT_AXI_CLK] = &gcc_aggre_usb3_tert_axi_clk.clkr,
6818	[GCC_AGGRE_USB4_0_AXI_CLK] = &gcc_aggre_usb4_0_axi_clk.clkr,
6819	[GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr,
6820	[GCC_AGGRE_USB4_2_AXI_CLK] = &gcc_aggre_usb4_2_axi_clk.clkr,
6821	[GCC_AGGRE_USB_NOC_AXI_CLK] = &gcc_aggre_usb_noc_axi_clk.clkr,
6822	[GCC_AV1E_AHB_CLK] = &gcc_av1e_ahb_clk.clkr,
6823	[GCC_AV1E_AXI_CLK] = &gcc_av1e_axi_clk.clkr,
6824	[GCC_AV1E_XO_CLK] = &gcc_av1e_xo_clk.clkr,
6825	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
6826	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
6827	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
6828	[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
6829	[GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_north_ahb_clk.clkr,
6830	[GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_south_ahb_clk.clkr,
6831	[GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr,
6832	[GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
6833	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
6834	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
6835	[GCC_CFG_NOC_USB3_TERT_AXI_CLK] = &gcc_cfg_noc_usb3_tert_axi_clk.clkr,
6836	[GCC_CFG_NOC_USB_ANOC_AHB_CLK] = &gcc_cfg_noc_usb_anoc_ahb_clk.clkr,
6837	[GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_north_ahb_clk.clkr,
6838	[GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_south_ahb_clk.clkr,
6839	[GCC_CNOC_PCIE1_TUNNEL_CLK] = &gcc_cnoc_pcie1_tunnel_clk.clkr,
6840	[GCC_CNOC_PCIE2_TUNNEL_CLK] = &gcc_cnoc_pcie2_tunnel_clk.clkr,
6841	[GCC_CNOC_PCIE_NORTH_SF_AXI_CLK] = &gcc_cnoc_pcie_north_sf_axi_clk.clkr,
6842	[GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK] = &gcc_cnoc_pcie_south_sf_axi_clk.clkr,
6843	[GCC_CNOC_PCIE_TUNNEL_CLK] = &gcc_cnoc_pcie_tunnel_clk.clkr,
6844	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
6845	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
6846	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
6847	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
6848	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
6849	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
6850	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
6851	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
6852	[GCC_GPLL0] = &gcc_gpll0.clkr,
6853	[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
6854	[GCC_GPLL4] = &gcc_gpll4.clkr,
6855	[GCC_GPLL7] = &gcc_gpll7.clkr,
6856	[GCC_GPLL8] = &gcc_gpll8.clkr,
6857	[GCC_GPLL9] = &gcc_gpll9.clkr,
6858	[GCC_GPU_GPLL0_CPH_CLK_SRC] = &gcc_gpu_gpll0_cph_clk_src.clkr,
6859	[GCC_GPU_GPLL0_DIV_CPH_CLK_SRC] = &gcc_gpu_gpll0_div_cph_clk_src.clkr,
6860	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
6861	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
6862	[GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
6863	[GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
6864	[GCC_PCIE2_PHY_RCHNG_CLK] = &gcc_pcie2_phy_rchng_clk.clkr,
6865	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
6866	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
6867	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
6868	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
6869	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
6870	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
6871	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
6872	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
6873	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
6874	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
6875	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
6876	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
6877	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
6878	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
6879	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
6880	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
6881	[GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
6882	[GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,
6883	[GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
6884	[GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
6885	[GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr,
6886	[GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
6887	[GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
6888	[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
6889	[GCC_PCIE_3_AUX_CLK] = &gcc_pcie_3_aux_clk.clkr,
6890	[GCC_PCIE_3_AUX_CLK_SRC] = &gcc_pcie_3_aux_clk_src.clkr,
6891	[GCC_PCIE_3_CFG_AHB_CLK] = &gcc_pcie_3_cfg_ahb_clk.clkr,
6892	[GCC_PCIE_3_MSTR_AXI_CLK] = &gcc_pcie_3_mstr_axi_clk.clkr,
6893	[GCC_PCIE_3_PHY_AUX_CLK] = &gcc_pcie_3_phy_aux_clk.clkr,
6894	[GCC_PCIE_3_PHY_RCHNG_CLK] = &gcc_pcie_3_phy_rchng_clk.clkr,
6895	[GCC_PCIE_3_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3_phy_rchng_clk_src.clkr,
6896	[GCC_PCIE_3_PIPE_CLK] = &gcc_pcie_3_pipe_clk.clkr,
6897	[GCC_PCIE_3_PIPE_CLK_SRC] = &gcc_pcie_3_pipe_clk_src.clkr,
6898	[GCC_PCIE_3_PIPE_DIV_CLK_SRC] = &gcc_pcie_3_pipe_div_clk_src.clkr,
6899	[GCC_PCIE_3_PIPEDIV2_CLK] = &gcc_pcie_3_pipediv2_clk.clkr,
6900	[GCC_PCIE_3_SLV_AXI_CLK] = &gcc_pcie_3_slv_axi_clk.clkr,
6901	[GCC_PCIE_3_SLV_Q2A_AXI_CLK] = &gcc_pcie_3_slv_q2a_axi_clk.clkr,
6902	[GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr,
6903	[GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr,
6904	[GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr,
6905	[GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr,
6906	[GCC_PCIE_4_PHY_RCHNG_CLK] = &gcc_pcie_4_phy_rchng_clk.clkr,
6907	[GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr,
6908	[GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr,
6909	[GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr,
6910	[GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr,
6911	[GCC_PCIE_4_PIPEDIV2_CLK] = &gcc_pcie_4_pipediv2_clk.clkr,
6912	[GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr,
6913	[GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr,
6914	[GCC_PCIE_5_AUX_CLK] = &gcc_pcie_5_aux_clk.clkr,
6915	[GCC_PCIE_5_AUX_CLK_SRC] = &gcc_pcie_5_aux_clk_src.clkr,
6916	[GCC_PCIE_5_CFG_AHB_CLK] = &gcc_pcie_5_cfg_ahb_clk.clkr,
6917	[GCC_PCIE_5_MSTR_AXI_CLK] = &gcc_pcie_5_mstr_axi_clk.clkr,
6918	[GCC_PCIE_5_PHY_RCHNG_CLK] = &gcc_pcie_5_phy_rchng_clk.clkr,
6919	[GCC_PCIE_5_PHY_RCHNG_CLK_SRC] = &gcc_pcie_5_phy_rchng_clk_src.clkr,
6920	[GCC_PCIE_5_PIPE_CLK] = &gcc_pcie_5_pipe_clk.clkr,
6921	[GCC_PCIE_5_PIPE_CLK_SRC] = &gcc_pcie_5_pipe_clk_src.clkr,
6922	[GCC_PCIE_5_PIPE_DIV_CLK_SRC] = &gcc_pcie_5_pipe_div_clk_src.clkr,
6923	[GCC_PCIE_5_PIPEDIV2_CLK] = &gcc_pcie_5_pipediv2_clk.clkr,
6924	[GCC_PCIE_5_SLV_AXI_CLK] = &gcc_pcie_5_slv_axi_clk.clkr,
6925	[GCC_PCIE_5_SLV_Q2A_AXI_CLK] = &gcc_pcie_5_slv_q2a_axi_clk.clkr,
6926	[GCC_PCIE_6A_AUX_CLK] = &gcc_pcie_6a_aux_clk.clkr,
6927	[GCC_PCIE_6A_AUX_CLK_SRC] = &gcc_pcie_6a_aux_clk_src.clkr,
6928	[GCC_PCIE_6A_CFG_AHB_CLK] = &gcc_pcie_6a_cfg_ahb_clk.clkr,
6929	[GCC_PCIE_6A_MSTR_AXI_CLK] = &gcc_pcie_6a_mstr_axi_clk.clkr,
6930	[GCC_PCIE_6A_PHY_AUX_CLK] = &gcc_pcie_6a_phy_aux_clk.clkr,
6931	[GCC_PCIE_6A_PHY_RCHNG_CLK] = &gcc_pcie_6a_phy_rchng_clk.clkr,
6932	[GCC_PCIE_6A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6a_phy_rchng_clk_src.clkr,
6933	[GCC_PCIE_6A_PIPE_CLK] = &gcc_pcie_6a_pipe_clk.clkr,
6934	[GCC_PCIE_6A_PIPE_CLK_SRC] = &gcc_pcie_6a_pipe_clk_src.clkr,
6935	[GCC_PCIE_6A_PIPE_DIV_CLK_SRC] = &gcc_pcie_6a_pipe_div_clk_src.clkr,
6936	[GCC_PCIE_6A_PIPEDIV2_CLK] = &gcc_pcie_6a_pipediv2_clk.clkr,
6937	[GCC_PCIE_6A_SLV_AXI_CLK] = &gcc_pcie_6a_slv_axi_clk.clkr,
6938	[GCC_PCIE_6A_SLV_Q2A_AXI_CLK] = &gcc_pcie_6a_slv_q2a_axi_clk.clkr,
6939	[GCC_PCIE_6B_AUX_CLK] = &gcc_pcie_6b_aux_clk.clkr,
6940	[GCC_PCIE_6B_AUX_CLK_SRC] = &gcc_pcie_6b_aux_clk_src.clkr,
6941	[GCC_PCIE_6B_CFG_AHB_CLK] = &gcc_pcie_6b_cfg_ahb_clk.clkr,
6942	[GCC_PCIE_6B_MSTR_AXI_CLK] = &gcc_pcie_6b_mstr_axi_clk.clkr,
6943	[GCC_PCIE_6B_PHY_AUX_CLK] = &gcc_pcie_6b_phy_aux_clk.clkr,
6944	[GCC_PCIE_6B_PHY_RCHNG_CLK] = &gcc_pcie_6b_phy_rchng_clk.clkr,
6945	[GCC_PCIE_6B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6b_phy_rchng_clk_src.clkr,
6946	[GCC_PCIE_6B_PIPE_CLK] = &gcc_pcie_6b_pipe_clk.clkr,
6947	[GCC_PCIE_6B_PIPE_CLK_SRC] = &gcc_pcie_6b_pipe_clk_src.clkr,
6948	[GCC_PCIE_6B_PIPE_DIV_CLK_SRC] = &gcc_pcie_6b_pipe_div_clk_src.clkr,
6949	[GCC_PCIE_6B_PIPEDIV2_CLK] = &gcc_pcie_6b_pipediv2_clk.clkr,
6950	[GCC_PCIE_6B_SLV_AXI_CLK] = &gcc_pcie_6b_slv_axi_clk.clkr,
6951	[GCC_PCIE_6B_SLV_Q2A_AXI_CLK] = &gcc_pcie_6b_slv_q2a_axi_clk.clkr,
6952	[GCC_PCIE_RSCC_AHB_CLK] = &gcc_pcie_rscc_ahb_clk.clkr,
6953	[GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr,
6954	[GCC_PCIE_RSCC_XO_CLK_SRC] = &gcc_pcie_rscc_xo_clk_src.clkr,
6955	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
6956	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
6957	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
6958	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
6959	[GCC_QMIP_AV1E_AHB_CLK] = &gcc_qmip_av1e_ahb_clk.clkr,
6960	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
6961	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
6962	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
6963	[GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
6964	[GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
6965	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
6966	[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
6967	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
6968	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
6969	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
6970	[GCC_QUPV3_WRAP0_QSPI_S2_CLK] = &gcc_qupv3_wrap0_qspi_s2_clk.clkr,
6971	[GCC_QUPV3_WRAP0_QSPI_S3_CLK] = &gcc_qupv3_wrap0_qspi_s3_clk.clkr,
6972	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
6973	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
6974	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
6975	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
6976	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
6977	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
6978	[GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s2_div_clk_src.clkr,
6979	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
6980	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
6981	[GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s3_div_clk_src.clkr,
6982	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
6983	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
6984	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
6985	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
6986	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
6987	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
6988	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
6989	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
6990	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
6991	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
6992	[GCC_QUPV3_WRAP1_QSPI_S2_CLK] = &gcc_qupv3_wrap1_qspi_s2_clk.clkr,
6993	[GCC_QUPV3_WRAP1_QSPI_S3_CLK] = &gcc_qupv3_wrap1_qspi_s3_clk.clkr,
6994	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
6995	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
6996	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
6997	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
6998	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
6999	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
7000	[GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s2_div_clk_src.clkr,
7001	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
7002	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
7003	[GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s3_div_clk_src.clkr,
7004	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
7005	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
7006	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
7007	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
7008	[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
7009	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
7010	[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
7011	[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
7012	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
7013	[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
7014	[GCC_QUPV3_WRAP2_QSPI_S2_CLK] = &gcc_qupv3_wrap2_qspi_s2_clk.clkr,
7015	[GCC_QUPV3_WRAP2_QSPI_S3_CLK] = &gcc_qupv3_wrap2_qspi_s3_clk.clkr,
7016	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
7017	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
7018	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
7019	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
7020	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
7021	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
7022	[GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s2_div_clk_src.clkr,
7023	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
7024	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
7025	[GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s3_div_clk_src.clkr,
7026	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
7027	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
7028	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
7029	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
7030	[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
7031	[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
7032	[GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
7033	[GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
7034	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
7035	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
7036	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
7037	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
7038	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
7039	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
7040	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
7041	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
7042	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
7043	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
7044	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
7045	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
7046	[GCC_SYS_NOC_USB_AXI_CLK] = &gcc_sys_noc_usb_axi_clk.clkr,
7047	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
7048	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
7049	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
7050	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
7051	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
7052	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
7053	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
7054	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
7055	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
7056	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
7057	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
7058	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
7059	[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
7060	[GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
7061	[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
7062	[GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr,
7063	[GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr,
7064	[GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
7065	[GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr,
7066	[GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr,
7067	[GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr,
7068	[GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr,
7069	[GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr,
7070	[GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr,
7071	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
7072	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
7073	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
7074	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
7075	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
7076	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
7077	[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
7078	[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
7079	[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
7080	[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
7081	[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
7082	[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
7083	[GCC_USB30_TERT_MASTER_CLK] = &gcc_usb30_tert_master_clk.clkr,
7084	[GCC_USB30_TERT_MASTER_CLK_SRC] = &gcc_usb30_tert_master_clk_src.clkr,
7085	[GCC_USB30_TERT_MOCK_UTMI_CLK] = &gcc_usb30_tert_mock_utmi_clk.clkr,
7086	[GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr,
7087	[GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr,
7088	[GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr,
7089	[GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr,
7090	[GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr,
7091	[GCC_USB34_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb34_tert_phy_pipe_clk_src.clkr,
7092	[GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
7093	[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
7094	[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
7095	[GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,
7096	[GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,
7097	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
7098	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
7099	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
7100	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
7101	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
7102	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
7103	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
7104	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
7105	[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
7106	[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
7107	[GCC_USB3_TERT_PHY_AUX_CLK] = &gcc_usb3_tert_phy_aux_clk.clkr,
7108	[GCC_USB3_TERT_PHY_AUX_CLK_SRC] = &gcc_usb3_tert_phy_aux_clk_src.clkr,
7109	[GCC_USB3_TERT_PHY_COM_AUX_CLK] = &gcc_usb3_tert_phy_com_aux_clk.clkr,
7110	[GCC_USB3_TERT_PHY_PIPE_CLK] = &gcc_usb3_tert_phy_pipe_clk.clkr,
7111	[GCC_USB3_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb3_tert_phy_pipe_clk_src.clkr,
7112	[GCC_USB4_0_CFG_AHB_CLK] = &gcc_usb4_0_cfg_ahb_clk.clkr,
7113	[GCC_USB4_0_DP0_CLK] = &gcc_usb4_0_dp0_clk.clkr,
7114	[GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr,
7115	[GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr,
7116	[GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr,
7117	[GCC_USB4_0_PHY_DP0_CLK_SRC] = &gcc_usb4_0_phy_dp0_clk_src.clkr,
7118	[GCC_USB4_0_PHY_DP1_CLK_SRC] = &gcc_usb4_0_phy_dp1_clk_src.clkr,
7119	[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr,
7120	[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr,
7121	[GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr,
7122	[GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr,
7123	[GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr,
7124	[GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr,
7125	[GCC_USB4_0_PHY_RX0_CLK_SRC] = &gcc_usb4_0_phy_rx0_clk_src.clkr,
7126	[GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr,
7127	[GCC_USB4_0_PHY_RX1_CLK_SRC] = &gcc_usb4_0_phy_rx1_clk_src.clkr,
7128	[GCC_USB4_0_PHY_SYS_CLK_SRC] = &gcc_usb4_0_phy_sys_clk_src.clkr,
7129	[GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr,
7130	[GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr,
7131	[GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr,
7132	[GCC_USB4_0_SYS_CLK] = &gcc_usb4_0_sys_clk.clkr,
7133	[GCC_USB4_0_TMU_CLK] = &gcc_usb4_0_tmu_clk.clkr,
7134	[GCC_USB4_0_TMU_CLK_SRC] = &gcc_usb4_0_tmu_clk_src.clkr,
7135	[GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr,
7136	[GCC_USB4_1_DP0_CLK] = &gcc_usb4_1_dp0_clk.clkr,
7137	[GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr,
7138	[GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr,
7139	[GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr,
7140	[GCC_USB4_1_PHY_DP0_CLK_SRC] = &gcc_usb4_1_phy_dp0_clk_src.clkr,
7141	[GCC_USB4_1_PHY_DP1_CLK_SRC] = &gcc_usb4_1_phy_dp1_clk_src.clkr,
7142	[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr,
7143	[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr,
7144	[GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr,
7145	[GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr,
7146	[GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr,
7147	[GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr,
7148	[GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr,
7149	[GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr,
7150	[GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr,
7151	[GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr,
7152	[GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr,
7153	[GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr,
7154	[GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr,
7155	[GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr,
7156	[GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr,
7157	[GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr,
7158	[GCC_USB4_2_CFG_AHB_CLK] = &gcc_usb4_2_cfg_ahb_clk.clkr,
7159	[GCC_USB4_2_DP0_CLK] = &gcc_usb4_2_dp0_clk.clkr,
7160	[GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr,
7161	[GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr,
7162	[GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr,
7163	[GCC_USB4_2_PHY_DP0_CLK_SRC] = &gcc_usb4_2_phy_dp0_clk_src.clkr,
7164	[GCC_USB4_2_PHY_DP1_CLK_SRC] = &gcc_usb4_2_phy_dp1_clk_src.clkr,
7165	[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr,
7166	[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr,
7167	[GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr,
7168	[GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr,
7169	[GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr,
7170	[GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr,
7171	[GCC_USB4_2_PHY_RX0_CLK_SRC] = &gcc_usb4_2_phy_rx0_clk_src.clkr,
7172	[GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr,
7173	[GCC_USB4_2_PHY_RX1_CLK_SRC] = &gcc_usb4_2_phy_rx1_clk_src.clkr,
7174	[GCC_USB4_2_PHY_SYS_CLK_SRC] = &gcc_usb4_2_phy_sys_clk_src.clkr,
7175	[GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr,
7176	[GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr,
7177	[GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr,
7178	[GCC_USB4_2_SYS_CLK] = &gcc_usb4_2_sys_clk.clkr,
7179	[GCC_USB4_2_TMU_CLK] = &gcc_usb4_2_tmu_clk.clkr,
7180	[GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr,
7181	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
7182	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
7183};
7184
7185static struct gdsc *gcc_x1e80100_gdscs[] = {
7186	[GCC_PCIE_0_TUNNEL_GDSC] = &gcc_pcie_0_tunnel_gdsc,
7187	[GCC_PCIE_1_TUNNEL_GDSC] = &gcc_pcie_1_tunnel_gdsc,
7188	[GCC_PCIE_2_TUNNEL_GDSC] = &gcc_pcie_2_tunnel_gdsc,
7189	[GCC_PCIE_3_GDSC] = &gcc_pcie_3_gdsc,
7190	[GCC_PCIE_3_PHY_GDSC] = &gcc_pcie_3_phy_gdsc,
7191	[GCC_PCIE_4_GDSC] = &gcc_pcie_4_gdsc,
7192	[GCC_PCIE_4_PHY_GDSC] = &gcc_pcie_4_phy_gdsc,
7193	[GCC_PCIE_5_GDSC] = &gcc_pcie_5_gdsc,
7194	[GCC_PCIE_5_PHY_GDSC] = &gcc_pcie_5_phy_gdsc,
7195	[GCC_PCIE_6_PHY_GDSC] = &gcc_pcie_6_phy_gdsc,
7196	[GCC_PCIE_6A_GDSC] = &gcc_pcie_6a_gdsc,
7197	[GCC_PCIE_6B_GDSC] = &gcc_pcie_6b_gdsc,
7198	[GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc,
7199	[GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
7200	[GCC_USB20_PRIM_GDSC] = &gcc_usb20_prim_gdsc,
7201	[GCC_USB30_MP_GDSC] = &gcc_usb30_mp_gdsc,
7202	[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
7203	[GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc,
7204	[GCC_USB30_TERT_GDSC] = &gcc_usb30_tert_gdsc,
7205	[GCC_USB3_MP_SS0_PHY_GDSC] = &gcc_usb3_mp_ss0_phy_gdsc,
7206	[GCC_USB3_MP_SS1_PHY_GDSC] = &gcc_usb3_mp_ss1_phy_gdsc,
7207	[GCC_USB4_0_GDSC] = &gcc_usb4_0_gdsc,
7208	[GCC_USB4_1_GDSC] = &gcc_usb4_1_gdsc,
7209	[GCC_USB4_2_GDSC] = &gcc_usb4_2_gdsc,
7210	[GCC_USB_0_PHY_GDSC] = &gcc_usb_0_phy_gdsc,
7211	[GCC_USB_1_PHY_GDSC] = &gcc_usb_1_phy_gdsc,
7212	[GCC_USB_2_PHY_GDSC] = &gcc_usb_2_phy_gdsc,
7213};
7214
7215static const struct qcom_reset_map gcc_x1e80100_resets[] = {
7216	[GCC_AV1E_BCR] = { 0x4a000 },
7217	[GCC_CAMERA_BCR] = { 0x26000 },
7218	[GCC_DISPLAY_BCR] = { 0x27000 },
7219	[GCC_GPU_BCR] = { 0x71000 },
7220	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
7221	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
7222	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
7223	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
7224	[GCC_PCIE_0_TUNNEL_BCR] = { 0xa0000 },
7225	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
7226	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
7227	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
7228	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
7229	[GCC_PCIE_1_TUNNEL_BCR] = { 0x2c000 },
7230	[GCC_PCIE_2_LINK_DOWN_BCR] = { 0xa5014 },
7231	[GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0xa5020 },
7232	[GCC_PCIE_2_PHY_BCR] = { 0xa501c },
7233	[GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0xa5028 },
7234	[GCC_PCIE_2_TUNNEL_BCR] = { 0x13000 },
7235	[GCC_PCIE_3_BCR] = { 0x58000 },
7236	[GCC_PCIE_3_LINK_DOWN_BCR] = { 0xab014 },
7237	[GCC_PCIE_3_NOCSR_COM_PHY_BCR] = { 0xab020 },
7238	[GCC_PCIE_3_PHY_BCR] = { 0xab01c },
7239	[GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] = { 0xab024 },
7240	[GCC_PCIE_4_BCR] = { 0x6b000 },
7241	[GCC_PCIE_4_LINK_DOWN_BCR] = { 0xb3014 },
7242	[GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0xb3020 },
7243	[GCC_PCIE_4_PHY_BCR] = { 0xb301c },
7244	[GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0xb3028 },
7245	[GCC_PCIE_5_BCR] = { 0x2f000 },
7246	[GCC_PCIE_5_LINK_DOWN_BCR] = { 0xaa014 },
7247	[GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0xaa020 },
7248	[GCC_PCIE_5_PHY_BCR] = { 0xaa01c },
7249	[GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0xaa028 },
7250	[GCC_PCIE_6A_BCR] = { 0x31000 },
7251	[GCC_PCIE_6A_LINK_DOWN_BCR] = { 0xac014 },
7252	[GCC_PCIE_6A_NOCSR_COM_PHY_BCR] = { 0xac020 },
7253	[GCC_PCIE_6A_PHY_BCR] = { 0xac01c },
7254	[GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] = { 0xac024 },
7255	[GCC_PCIE_6B_BCR] = { 0x8d000 },
7256	[GCC_PCIE_6B_LINK_DOWN_BCR] = { 0xb5014 },
7257	[GCC_PCIE_6B_NOCSR_COM_PHY_BCR] = { 0xb5020 },
7258	[GCC_PCIE_6B_PHY_BCR] = { 0xb501c },
7259	[GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] = { 0xb5024 },
7260	[GCC_PCIE_PHY_BCR] = { 0x6f000 },
7261	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
7262	[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
7263	[GCC_PCIE_RSCC_BCR] = { 0xa4000 },
7264	[GCC_PDM_BCR] = { 0x33000 },
7265	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x42000 },
7266	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
7267	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
7268	[GCC_QUSB2PHY_HS0_MP_BCR] = { 0x1200c },
7269	[GCC_QUSB2PHY_HS1_MP_BCR] = { 0x12010 },
7270	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
7271	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
7272	[GCC_QUSB2PHY_TERT_BCR] = { 0x12008 },
7273	[GCC_QUSB2PHY_USB20_HS_BCR] = { 0x12014 },
7274	[GCC_SDCC2_BCR] = { 0x14000 },
7275	[GCC_SDCC4_BCR] = { 0x16000 },
7276	[GCC_UFS_PHY_BCR] = { 0x77000 },
7277	[GCC_USB20_PRIM_BCR] = { 0x29000 },
7278	[GCC_USB30_MP_BCR] = { 0x17000 },
7279	[GCC_USB30_PRIM_BCR] = { 0x39000 },
7280	[GCC_USB30_SEC_BCR] = { 0xa1000 },
7281	[GCC_USB30_TERT_BCR] = { 0xa2000 },
7282	[GCC_USB3_MP_SS0_PHY_BCR] = { 0x19008 },
7283	[GCC_USB3_MP_SS1_PHY_BCR] = { 0x54008 },
7284	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
7285	[GCC_USB3_PHY_SEC_BCR] = { 0x2a000 },
7286	[GCC_USB3_PHY_TERT_BCR] = { 0xa3000 },
7287	[GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 },
7288	[GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 },
7289	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
7290	[GCC_USB4PHY_PHY_PRIM_BCR] = { 0x5000c },
7291	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 },
7292	[GCC_USB4PHY_PHY_SEC_BCR] = { 0x2a00c },
7293	[GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 },
7294	[GCC_USB4PHY_PHY_TERT_BCR] = { 0xa300c },
7295	[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 },
7296	[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 },
7297	[GCC_USB4_0_BCR] = { 0x9f000 },
7298	[GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 },
7299	[GCC_USB4_0_MISC_USB4_SYS_BCR] = { .reg = 0xad0f8, .bit = 0 },
7300	[GCC_USB4_0_MISC_RX_CLK_0_BCR] = { .reg = 0xad0f8, .bit = 1 },
7301	[GCC_USB4_0_MISC_RX_CLK_1_BCR] = { .reg = 0xad0f8, .bit = 2 },
7302	[GCC_USB4_0_MISC_USB_PIPE_BCR] = { .reg = 0xad0f8, .bit = 3 },
7303	[GCC_USB4_0_MISC_PCIE_PIPE_BCR] = { .reg = 0xad0f8, .bit = 4 },
7304	[GCC_USB4_0_MISC_TMU_BCR] = { .reg = 0xad0f8, .bit = 5 },
7305	[GCC_USB4_0_MISC_SB_IF_BCR] = { .reg = 0xad0f8, .bit = 6 },
7306	[GCC_USB4_0_MISC_HIA_MSTR_BCR] = { .reg = 0xad0f8, .bit = 7 },
7307	[GCC_USB4_0_MISC_AHB_BCR] = { .reg = 0xad0f8, .bit = 8 },
7308	[GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xad0f8, .bit = 9 },
7309	[GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xad0f8, .bit = 10 },
7310	[GCC_USB4_1_BCR] = { 0x2b000 },
7311	[GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
7312	[GCC_USB4_1_MISC_USB4_SYS_BCR] = { .reg = 0xae0f8, .bit = 0 },
7313	[GCC_USB4_1_MISC_RX_CLK_0_BCR] = { .reg = 0xae0f8, .bit = 1 },
7314	[GCC_USB4_1_MISC_RX_CLK_1_BCR] = { .reg = 0xae0f8, .bit = 2 },
7315	[GCC_USB4_1_MISC_USB_PIPE_BCR] = { .reg = 0xae0f8, .bit = 3 },
7316	[GCC_USB4_1_MISC_PCIE_PIPE_BCR] = { .reg = 0xae0f8, .bit = 4 },
7317	[GCC_USB4_1_MISC_TMU_BCR] = { .reg = 0xae0f8, .bit = 5 },
7318	[GCC_USB4_1_MISC_SB_IF_BCR] = { .reg = 0xae0f8, .bit = 6 },
7319	[GCC_USB4_1_MISC_HIA_MSTR_BCR] = { .reg = 0xae0f8, .bit = 7 },
7320	[GCC_USB4_1_MISC_AHB_BCR] = { .reg = 0xae0f8, .bit = 8 },
7321	[GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xae0f8, .bit = 9 },
7322	[GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xae0f8, .bit = 10 },
7323	[GCC_USB4_2_BCR] = { 0x11000 },
7324	[GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
7325	[GCC_USB4_2_MISC_USB4_SYS_BCR] = { .reg = 0xaf0f8, .bit = 0 },
7326	[GCC_USB4_2_MISC_RX_CLK_0_BCR] = { .reg = 0xaf0f8, .bit = 1 },
7327	[GCC_USB4_2_MISC_RX_CLK_1_BCR] = { .reg = 0xaf0f8, .bit = 2 },
7328	[GCC_USB4_2_MISC_USB_PIPE_BCR] = { .reg = 0xaf0f8, .bit = 3 },
7329	[GCC_USB4_2_MISC_PCIE_PIPE_BCR] = { .reg = 0xaf0f8, .bit = 4 },
7330	[GCC_USB4_2_MISC_TMU_BCR] = { .reg = 0xaf0f8, .bit = 5 },
7331	[GCC_USB4_2_MISC_SB_IF_BCR] = { .reg = 0xaf0f8, .bit = 6 },
7332	[GCC_USB4_2_MISC_HIA_MSTR_BCR] = { .reg = 0xaf0f8, .bit = 7 },
7333	[GCC_USB4_2_MISC_AHB_BCR] = { .reg = 0xaf0f8, .bit = 8 },
7334	[GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xaf0f8, .bit = 9 },
7335	[GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xaf0f8, .bit = 10 },
7336	[GCC_USB_0_PHY_BCR] = { 0x50020 },
7337	[GCC_USB_1_PHY_BCR] = { 0x2a020 },
7338	[GCC_USB_2_PHY_BCR] = { 0xa3020 },
7339	[GCC_VIDEO_BCR] = { 0x32000 },
7340	[GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 },
7341	[GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 },
7342};
7343
7344static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
7345	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
7346	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
7347	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
7348	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
7349	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
7350	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
7351	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
7352	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
7353	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
7354	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
7355	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
7356	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
7357	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
7358	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
7359	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
7360	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
7361	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
7362	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
7363	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
7364	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
7365	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
7366	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
7367	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
7368	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
7369};
7370
7371static const struct regmap_config gcc_x1e80100_regmap_config = {
7372	.reg_bits = 32,
7373	.reg_stride = 4,
7374	.val_bits = 32,
7375	.max_register = 0x1f41f0,
7376	.fast_io = true,
7377};
7378
7379static const struct qcom_cc_desc gcc_x1e80100_desc = {
7380	.config = &gcc_x1e80100_regmap_config,
7381	.clks = gcc_x1e80100_clocks,
7382	.num_clks = ARRAY_SIZE(gcc_x1e80100_clocks),
7383	.resets = gcc_x1e80100_resets,
7384	.num_resets = ARRAY_SIZE(gcc_x1e80100_resets),
7385	.gdscs = gcc_x1e80100_gdscs,
7386	.num_gdscs = ARRAY_SIZE(gcc_x1e80100_gdscs),
7387};
7388
7389static const struct of_device_id gcc_x1e80100_match_table[] = {
7390	{ .compatible = "qcom,x1e80100-gcc" },
7391	{ }
7392};
7393MODULE_DEVICE_TABLE(of, gcc_x1e80100_match_table);
7394
7395static int gcc_x1e80100_probe(struct platform_device *pdev)
7396{
7397	struct regmap *regmap;
7398	int ret;
7399
7400	regmap = qcom_cc_map(pdev, &gcc_x1e80100_desc);
7401	if (IS_ERR(regmap))
7402		return PTR_ERR(regmap);
7403
7404	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
7405				       ARRAY_SIZE(gcc_dfs_clocks));
7406	if (ret)
7407		return ret;
7408
7409	/* Keep some clocks always-on */
7410	qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */
7411	qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */
7412	qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */
7413	qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */
7414	qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */
7415	qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */
7416	qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
7417
7418	/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
7419	regmap_write(regmap, 0x52224, 0x0);
7420
7421	/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks  */
7422	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
7423	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
7424
7425	return qcom_cc_really_probe(&pdev->dev, &gcc_x1e80100_desc, regmap);
7426}
7427
7428static struct platform_driver gcc_x1e80100_driver = {
7429	.probe = gcc_x1e80100_probe,
7430	.driver = {
7431		.name = "gcc-x1e80100",
7432		.of_match_table = gcc_x1e80100_match_table,
7433	},
7434};
7435
7436static int __init gcc_x1e80100_init(void)
7437{
7438	return platform_driver_register(&gcc_x1e80100_driver);
7439}
7440subsys_initcall(gcc_x1e80100_init);
7441
7442static void __exit gcc_x1e80100_exit(void)
7443{
7444	platform_driver_unregister(&gcc_x1e80100_driver);
7445}
7446module_exit(gcc_x1e80100_exit);
7447
7448MODULE_DESCRIPTION("QTI GCC X1E80100 Driver");
7449MODULE_LICENSE("GPL");