gcc-sm8750.c

   1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2/*
   3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/mod_devicetable.h>
   8#include <linux/module.h>
   9#include <linux/platform_device.h>
  10#include <linux/regmap.h>
  11
  12#include <dt-bindings/clock/qcom,sm8750-gcc.h>
  13
  14#include "clk-alpha-pll.h"
  15#include "clk-branch.h"
  16#include "clk-pll.h"
  17#include "clk-rcg.h"
  18#include "clk-regmap.h"
  19#include "clk-regmap-divider.h"
  20#include "clk-regmap-mux.h"
  21#include "clk-regmap-phy-mux.h"
  22#include "common.h"
  23#include "gdsc.h"
  24#include "reset.h"
  25
  26enum {
  27	DT_BI_TCXO,
  28	DT_BI_TCXO_AO,
  29	DT_SLEEP_CLK,
  30	DT_PCIE_0_PIPE_CLK,
  31	DT_UFS_PHY_RX_SYMBOL_0_CLK,
  32	DT_UFS_PHY_RX_SYMBOL_1_CLK,
  33	DT_UFS_PHY_TX_SYMBOL_0_CLK,
  34	DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
  35};
  36
  37enum {
  38	P_BI_TCXO,
  39	P_GCC_GPLL0_OUT_EVEN,
  40	P_GCC_GPLL0_OUT_MAIN,
  41	P_GCC_GPLL1_OUT_MAIN,
  42	P_GCC_GPLL4_OUT_MAIN,
  43	P_GCC_GPLL7_OUT_MAIN,
  44	P_GCC_GPLL9_OUT_MAIN,
  45	P_PCIE_0_PIPE_CLK,
  46	P_SLEEP_CLK,
  47	P_UFS_PHY_RX_SYMBOL_0_CLK,
  48	P_UFS_PHY_RX_SYMBOL_1_CLK,
  49	P_UFS_PHY_TX_SYMBOL_0_CLK,
  50	P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
  51};
  52
  53static struct clk_alpha_pll gcc_gpll0 = {
  54	.offset = 0x0,
  55	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
  56	.clkr = {
  57		.enable_reg = 0x52020,
  58		.enable_mask = BIT(0),
  59		.hw.init = &(const struct clk_init_data) {
  60			.name = "gcc_gpll0",
  61			.parent_data = &(const struct clk_parent_data) {
  62				.index = DT_BI_TCXO,
  63			},
  64			.num_parents = 1,
  65			.ops = &clk_alpha_pll_fixed_taycan_elu_ops,
  66		},
  67	},
  68};
  69
  70static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
  71	{ 0x1, 2 },
  72	{ }
  73};
  74
  75static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
  76	.offset = 0x0,
  77	.post_div_shift = 10,
  78	.post_div_table = post_div_table_gcc_gpll0_out_even,
  79	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
  80	.width = 4,
  81	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
  82	.clkr.hw.init = &(const struct clk_init_data) {
  83		.name = "gcc_gpll0_out_even",
  84		.parent_hws = (const struct clk_hw*[]) {
  85			&gcc_gpll0.clkr.hw,
  86		},
  87		.num_parents = 1,
  88		.ops = &clk_alpha_pll_postdiv_taycan_elu_ops,
  89	},
  90};
  91
  92static struct clk_alpha_pll gcc_gpll1 = {
  93	.offset = 0x1000,
  94	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
  95	.clkr = {
  96		.enable_reg = 0x52020,
  97		.enable_mask = BIT(1),
  98		.hw.init = &(const struct clk_init_data) {
  99			.name = "gcc_gpll1",
 100			.parent_data = &(const struct clk_parent_data) {
 101				.index = DT_BI_TCXO,
 102			},
 103			.num_parents = 1,
 104			.ops = &clk_alpha_pll_fixed_taycan_elu_ops,
 105		},
 106	},
 107};
 108
 109static struct clk_alpha_pll gcc_gpll4 = {
 110	.offset = 0x4000,
 111	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
 112	.clkr = {
 113		.enable_reg = 0x52020,
 114		.enable_mask = BIT(4),
 115		.hw.init = &(const struct clk_init_data) {
 116			.name = "gcc_gpll4",
 117			.parent_data = &(const struct clk_parent_data) {
 118				.index = DT_BI_TCXO,
 119			},
 120			.num_parents = 1,
 121			.ops = &clk_alpha_pll_fixed_taycan_elu_ops,
 122		},
 123	},
 124};
 125
 126static struct clk_alpha_pll gcc_gpll7 = {
 127	.offset = 0x7000,
 128	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
 129	.clkr = {
 130		.enable_reg = 0x52020,
 131		.enable_mask = BIT(7),
 132		.hw.init = &(const struct clk_init_data) {
 133			.name = "gcc_gpll7",
 134			.parent_data = &(const struct clk_parent_data) {
 135				.index = DT_BI_TCXO,
 136			},
 137			.num_parents = 1,
 138			.ops = &clk_alpha_pll_fixed_taycan_elu_ops,
 139		},
 140	},
 141};
 142
 143static struct clk_alpha_pll gcc_gpll9 = {
 144	.offset = 0x9000,
 145	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
 146	.clkr = {
 147		.enable_reg = 0x52020,
 148		.enable_mask = BIT(9),
 149		.hw.init = &(const struct clk_init_data) {
 150			.name = "gcc_gpll9",
 151			.parent_data = &(const struct clk_parent_data) {
 152				.index = DT_BI_TCXO,
 153			},
 154			.num_parents = 1,
 155			.ops = &clk_alpha_pll_fixed_taycan_elu_ops,
 156		},
 157	},
 158};
 159
 160static const struct parent_map gcc_parent_map_0[] = {
 161	{ P_BI_TCXO, 0 },
 162	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 163	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 164};
 165
 166static const struct clk_parent_data gcc_parent_data_0[] = {
 167	{ .index = DT_BI_TCXO },
 168	{ .hw = &gcc_gpll0.clkr.hw },
 169	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 170};
 171
 172static const struct parent_map gcc_parent_map_1[] = {
 173	{ P_BI_TCXO, 0 },
 174	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 175	{ P_SLEEP_CLK, 5 },
 176	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 177};
 178
 179static const struct clk_parent_data gcc_parent_data_1[] = {
 180	{ .index = DT_BI_TCXO },
 181	{ .hw = &gcc_gpll0.clkr.hw },
 182	{ .index = DT_SLEEP_CLK },
 183	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 184};
 185
 186static const struct parent_map gcc_parent_map_2[] = {
 187	{ P_BI_TCXO, 0 },
 188	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 189	{ P_GCC_GPLL1_OUT_MAIN, 4 },
 190	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 191	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 192};
 193
 194static const struct clk_parent_data gcc_parent_data_2[] = {
 195	{ .index = DT_BI_TCXO },
 196	{ .hw = &gcc_gpll0.clkr.hw },
 197	{ .hw = &gcc_gpll1.clkr.hw },
 198	{ .hw = &gcc_gpll4.clkr.hw },
 199	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 200};
 201
 202static const struct parent_map gcc_parent_map_3[] = {
 203	{ P_BI_TCXO, 0 },
 204	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 205	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 206	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 207};
 208
 209static const struct clk_parent_data gcc_parent_data_3[] = {
 210	{ .index = DT_BI_TCXO },
 211	{ .hw = &gcc_gpll0.clkr.hw },
 212	{ .hw = &gcc_gpll4.clkr.hw },
 213	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 214};
 215
 216static const struct parent_map gcc_parent_map_4[] = {
 217	{ P_BI_TCXO, 0 },
 218	{ P_SLEEP_CLK, 5 },
 219};
 220
 221static const struct clk_parent_data gcc_parent_data_4[] = {
 222	{ .index = DT_BI_TCXO },
 223	{ .index = DT_SLEEP_CLK },
 224};
 225
 226static const struct parent_map gcc_parent_map_5[] = {
 227	{ P_BI_TCXO, 0 },
 228	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 229	{ P_GCC_GPLL7_OUT_MAIN, 2 },
 230	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 231};
 232
 233static const struct clk_parent_data gcc_parent_data_5[] = {
 234	{ .index = DT_BI_TCXO },
 235	{ .hw = &gcc_gpll0.clkr.hw },
 236	{ .hw = &gcc_gpll7.clkr.hw },
 237	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 238};
 239
 240static const struct parent_map gcc_parent_map_6[] = {
 241	{ P_BI_TCXO, 0 },
 242};
 243
 244static const struct clk_parent_data gcc_parent_data_6[] = {
 245	{ .index = DT_BI_TCXO },
 246};
 247
 248static const struct parent_map gcc_parent_map_8[] = {
 249	{ P_BI_TCXO, 0 },
 250	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 251	{ P_GCC_GPLL9_OUT_MAIN, 2 },
 252	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 253	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 254};
 255
 256static const struct clk_parent_data gcc_parent_data_8[] = {
 257	{ .index = DT_BI_TCXO },
 258	{ .hw = &gcc_gpll0.clkr.hw },
 259	{ .hw = &gcc_gpll9.clkr.hw },
 260	{ .hw = &gcc_gpll4.clkr.hw },
 261	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 262};
 263
 264static const struct parent_map gcc_parent_map_9[] = {
 265	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
 266	{ P_BI_TCXO, 2 },
 267};
 268
 269static const struct clk_parent_data gcc_parent_data_9[] = {
 270	{ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
 271	{ .index = DT_BI_TCXO },
 272};
 273
 274static const struct parent_map gcc_parent_map_10[] = {
 275	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
 276	{ P_BI_TCXO, 2 },
 277};
 278
 279static const struct clk_parent_data gcc_parent_data_10[] = {
 280	{ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
 281	{ .index = DT_BI_TCXO },
 282};
 283
 284static const struct parent_map gcc_parent_map_11[] = {
 285	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
 286	{ P_BI_TCXO, 2 },
 287};
 288
 289static const struct clk_parent_data gcc_parent_data_11[] = {
 290	{ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
 291	{ .index = DT_BI_TCXO },
 292};
 293
 294static const struct parent_map gcc_parent_map_12[] = {
 295	{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 296	{ P_BI_TCXO, 2 },
 297};
 298
 299static const struct clk_parent_data gcc_parent_data_12[] = {
 300	{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK },
 301	{ .index = DT_BI_TCXO },
 302};
 303
 304static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
 305	.reg = 0x6b080,
 306	.clkr = {
 307		.hw.init = &(const struct clk_init_data) {
 308			.name = "gcc_pcie_0_pipe_clk_src",
 309			.parent_data = &(const struct clk_parent_data){
 310				.index = DT_PCIE_0_PIPE_CLK,
 311			},
 312			.num_parents = 1,
 313			.ops = &clk_regmap_phy_mux_ops,
 314		},
 315	},
 316};
 317
 318static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
 319	.reg = 0x77068,
 320	.shift = 0,
 321	.width = 2,
 322	.parent_map = gcc_parent_map_9,
 323	.clkr = {
 324		.hw.init = &(const struct clk_init_data) {
 325			.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
 326			.parent_data = gcc_parent_data_9,
 327			.num_parents = ARRAY_SIZE(gcc_parent_data_9),
 328			.ops = &clk_regmap_mux_closest_ops,
 329		},
 330	},
 331};
 332
 333static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
 334	.reg = 0x770ec,
 335	.shift = 0,
 336	.width = 2,
 337	.parent_map = gcc_parent_map_10,
 338	.clkr = {
 339		.hw.init = &(const struct clk_init_data) {
 340			.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
 341			.parent_data = gcc_parent_data_10,
 342			.num_parents = ARRAY_SIZE(gcc_parent_data_10),
 343			.ops = &clk_regmap_mux_closest_ops,
 344		},
 345	},
 346};
 347
 348static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
 349	.reg = 0x77058,
 350	.shift = 0,
 351	.width = 2,
 352	.parent_map = gcc_parent_map_11,
 353	.clkr = {
 354		.hw.init = &(const struct clk_init_data) {
 355			.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
 356			.parent_data = gcc_parent_data_11,
 357			.num_parents = ARRAY_SIZE(gcc_parent_data_11),
 358			.ops = &clk_regmap_mux_closest_ops,
 359		},
 360	},
 361};
 362
 363static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
 364	.reg = 0x39070,
 365	.shift = 0,
 366	.width = 2,
 367	.parent_map = gcc_parent_map_12,
 368	.clkr = {
 369		.hw.init = &(const struct clk_init_data) {
 370			.name = "gcc_usb3_prim_phy_pipe_clk_src",
 371			.parent_data = gcc_parent_data_12,
 372			.num_parents = ARRAY_SIZE(gcc_parent_data_12),
 373			.ops = &clk_regmap_mux_closest_ops,
 374		},
 375	},
 376};
 377
 378static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 379	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 380	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 381	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
 382	{ }
 383};
 384
 385static struct clk_rcg2 gcc_gp1_clk_src = {
 386	.cmd_rcgr = 0x64004,
 387	.mnd_width = 16,
 388	.hid_width = 5,
 389	.parent_map = gcc_parent_map_1,
 390	.freq_tbl = ftbl_gcc_gp1_clk_src,
 391	.clkr.hw.init = &(const struct clk_init_data) {
 392		.name = "gcc_gp1_clk_src",
 393		.parent_data = gcc_parent_data_1,
 394		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 395		.flags = CLK_SET_RATE_PARENT,
 396		.ops = &clk_rcg2_shared_ops,
 397	},
 398};
 399
 400static struct clk_rcg2 gcc_gp2_clk_src = {
 401	.cmd_rcgr = 0x65004,
 402	.mnd_width = 16,
 403	.hid_width = 5,
 404	.parent_map = gcc_parent_map_1,
 405	.freq_tbl = ftbl_gcc_gp1_clk_src,
 406	.clkr.hw.init = &(const struct clk_init_data) {
 407		.name = "gcc_gp2_clk_src",
 408		.parent_data = gcc_parent_data_1,
 409		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 410		.flags = CLK_SET_RATE_PARENT,
 411		.ops = &clk_rcg2_shared_ops,
 412	},
 413};
 414
 415static struct clk_rcg2 gcc_gp3_clk_src = {
 416	.cmd_rcgr = 0x66004,
 417	.mnd_width = 16,
 418	.hid_width = 5,
 419	.parent_map = gcc_parent_map_1,
 420	.freq_tbl = ftbl_gcc_gp1_clk_src,
 421	.clkr.hw.init = &(const struct clk_init_data) {
 422		.name = "gcc_gp3_clk_src",
 423		.parent_data = gcc_parent_data_1,
 424		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 425		.flags = CLK_SET_RATE_PARENT,
 426		.ops = &clk_rcg2_shared_ops,
 427	},
 428};
 429
 430static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 431	F(19200000, P_BI_TCXO, 1, 0, 0),
 432	{ }
 433};
 434
 435static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 436	.cmd_rcgr = 0x6b084,
 437	.mnd_width = 16,
 438	.hid_width = 5,
 439	.parent_map = gcc_parent_map_4,
 440	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 441	.clkr.hw.init = &(const struct clk_init_data) {
 442		.name = "gcc_pcie_0_aux_clk_src",
 443		.parent_data = gcc_parent_data_4,
 444		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
 445		.flags = CLK_SET_RATE_PARENT,
 446		.ops = &clk_rcg2_shared_ops,
 447	},
 448};
 449
 450static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
 451	F(19200000, P_BI_TCXO, 1, 0, 0),
 452	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 453	{ }
 454};
 455
 456static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
 457	.cmd_rcgr = 0x6b068,
 458	.mnd_width = 0,
 459	.hid_width = 5,
 460	.parent_map = gcc_parent_map_0,
 461	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 462	.clkr.hw.init = &(const struct clk_init_data) {
 463		.name = "gcc_pcie_0_phy_rchng_clk_src",
 464		.parent_data = gcc_parent_data_0,
 465		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 466		.flags = CLK_SET_RATE_PARENT,
 467		.ops = &clk_rcg2_shared_ops,
 468	},
 469};
 470
 471static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 472	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
 473	{ }
 474};
 475
 476static struct clk_rcg2 gcc_pdm2_clk_src = {
 477	.cmd_rcgr = 0x33010,
 478	.mnd_width = 0,
 479	.hid_width = 5,
 480	.parent_map = gcc_parent_map_0,
 481	.freq_tbl = ftbl_gcc_pdm2_clk_src,
 482	.clkr.hw.init = &(const struct clk_init_data) {
 483		.name = "gcc_pdm2_clk_src",
 484		.parent_data = gcc_parent_data_0,
 485		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 486		.flags = CLK_SET_RATE_PARENT,
 487		.ops = &clk_rcg2_shared_ops,
 488	},
 489};
 490
 491static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = {
 492	.cmd_rcgr = 0x17008,
 493	.mnd_width = 0,
 494	.hid_width = 5,
 495	.parent_map = gcc_parent_map_0,
 496	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 497	.clkr.hw.init = &(const struct clk_init_data) {
 498		.name = "gcc_qupv3_i2c_s0_clk_src",
 499		.parent_data = gcc_parent_data_0,
 500		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 501		.flags = CLK_SET_RATE_PARENT,
 502		.ops = &clk_rcg2_shared_ops,
 503	},
 504};
 505
 506static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = {
 507	.cmd_rcgr = 0x17024,
 508	.mnd_width = 0,
 509	.hid_width = 5,
 510	.parent_map = gcc_parent_map_0,
 511	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 512	.clkr.hw.init = &(const struct clk_init_data) {
 513		.name = "gcc_qupv3_i2c_s1_clk_src",
 514		.parent_data = gcc_parent_data_0,
 515		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 516		.flags = CLK_SET_RATE_PARENT,
 517		.ops = &clk_rcg2_shared_ops,
 518	},
 519};
 520
 521static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = {
 522	.cmd_rcgr = 0x17040,
 523	.mnd_width = 0,
 524	.hid_width = 5,
 525	.parent_map = gcc_parent_map_0,
 526	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 527	.clkr.hw.init = &(const struct clk_init_data) {
 528		.name = "gcc_qupv3_i2c_s2_clk_src",
 529		.parent_data = gcc_parent_data_0,
 530		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 531		.flags = CLK_SET_RATE_PARENT,
 532		.ops = &clk_rcg2_shared_ops,
 533	},
 534};
 535
 536static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = {
 537	.cmd_rcgr = 0x1705c,
 538	.mnd_width = 0,
 539	.hid_width = 5,
 540	.parent_map = gcc_parent_map_0,
 541	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 542	.clkr.hw.init = &(const struct clk_init_data) {
 543		.name = "gcc_qupv3_i2c_s3_clk_src",
 544		.parent_data = gcc_parent_data_0,
 545		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 546		.flags = CLK_SET_RATE_PARENT,
 547		.ops = &clk_rcg2_shared_ops,
 548	},
 549};
 550
 551static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = {
 552	.cmd_rcgr = 0x17078,
 553	.mnd_width = 0,
 554	.hid_width = 5,
 555	.parent_map = gcc_parent_map_0,
 556	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 557	.clkr.hw.init = &(const struct clk_init_data) {
 558		.name = "gcc_qupv3_i2c_s4_clk_src",
 559		.parent_data = gcc_parent_data_0,
 560		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 561		.flags = CLK_SET_RATE_PARENT,
 562		.ops = &clk_rcg2_shared_ops,
 563	},
 564};
 565
 566static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = {
 567	.cmd_rcgr = 0x17094,
 568	.mnd_width = 0,
 569	.hid_width = 5,
 570	.parent_map = gcc_parent_map_0,
 571	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 572	.clkr.hw.init = &(const struct clk_init_data) {
 573		.name = "gcc_qupv3_i2c_s5_clk_src",
 574		.parent_data = gcc_parent_data_0,
 575		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 576		.flags = CLK_SET_RATE_PARENT,
 577		.ops = &clk_rcg2_shared_ops,
 578	},
 579};
 580
 581static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = {
 582	.cmd_rcgr = 0x170b0,
 583	.mnd_width = 0,
 584	.hid_width = 5,
 585	.parent_map = gcc_parent_map_0,
 586	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 587	.clkr.hw.init = &(const struct clk_init_data) {
 588		.name = "gcc_qupv3_i2c_s6_clk_src",
 589		.parent_data = gcc_parent_data_0,
 590		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 591		.flags = CLK_SET_RATE_PARENT,
 592		.ops = &clk_rcg2_shared_ops,
 593	},
 594};
 595
 596static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = {
 597	.cmd_rcgr = 0x170cc,
 598	.mnd_width = 0,
 599	.hid_width = 5,
 600	.parent_map = gcc_parent_map_0,
 601	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 602	.clkr.hw.init = &(const struct clk_init_data) {
 603		.name = "gcc_qupv3_i2c_s7_clk_src",
 604		.parent_data = gcc_parent_data_0,
 605		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 606		.flags = CLK_SET_RATE_PARENT,
 607		.ops = &clk_rcg2_shared_ops,
 608	},
 609};
 610
 611static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = {
 612	.cmd_rcgr = 0x170e8,
 613	.mnd_width = 0,
 614	.hid_width = 5,
 615	.parent_map = gcc_parent_map_0,
 616	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 617	.clkr.hw.init = &(const struct clk_init_data) {
 618		.name = "gcc_qupv3_i2c_s8_clk_src",
 619		.parent_data = gcc_parent_data_0,
 620		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 621		.flags = CLK_SET_RATE_PARENT,
 622		.ops = &clk_rcg2_shared_ops,
 623	},
 624};
 625
 626static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = {
 627	.cmd_rcgr = 0x17104,
 628	.mnd_width = 0,
 629	.hid_width = 5,
 630	.parent_map = gcc_parent_map_0,
 631	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 632	.clkr.hw.init = &(const struct clk_init_data) {
 633		.name = "gcc_qupv3_i2c_s9_clk_src",
 634		.parent_data = gcc_parent_data_0,
 635		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 636		.flags = CLK_SET_RATE_PARENT,
 637		.ops = &clk_rcg2_shared_ops,
 638	},
 639};
 640
 641/* Check this frequency table.*/
 642static const struct freq_tbl ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src[] = {
 643	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 644	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 645	F(19200000, P_BI_TCXO, 1, 0, 0),
 646	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 647	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 648	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 649	F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
 650	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 651	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 652	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 653	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 654	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 655	F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
 656	F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
 657	F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
 658	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
 659	F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
 660	F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
 661	{ }
 662};
 663
 664static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = {
 665	.name = "gcc_qupv3_wrap1_qspi_ref_clk_src",
 666	.parent_data = gcc_parent_data_5,
 667	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
 668	.flags = CLK_SET_RATE_PARENT,
 669	.ops = &clk_rcg2_shared_ops,
 670};
 671
 672static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = {
 673	.cmd_rcgr = 0x188c0,
 674	.mnd_width = 16,
 675	.hid_width = 5,
 676	.parent_map = gcc_parent_map_5,
 677	.freq_tbl = ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src,
 678	.clkr.hw.init = &gcc_qupv3_wrap1_qspi_ref_clk_src_init,
 679};
 680
 681static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
 682	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 683	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 684	F(19200000, P_BI_TCXO, 1, 0, 0),
 685	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 686	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 687	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 688	F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
 689	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 690	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 691	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 692	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 693	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 694	F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
 695	F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
 696	F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
 697	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
 698	{ }
 699};
 700
 701static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 702	.name = "gcc_qupv3_wrap1_s0_clk_src",
 703	.parent_data = gcc_parent_data_0,
 704	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 705	.flags = CLK_SET_RATE_PARENT,
 706	.ops = &clk_rcg2_shared_ops,
 707};
 708
 709static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 710	.cmd_rcgr = 0x18014,
 711	.mnd_width = 16,
 712	.hid_width = 5,
 713	.parent_map = gcc_parent_map_0,
 714	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 715	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 716};
 717
 718static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 719	.name = "gcc_qupv3_wrap1_s1_clk_src",
 720	.parent_data = gcc_parent_data_0,
 721	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 722	.flags = CLK_SET_RATE_PARENT,
 723	.ops = &clk_rcg2_shared_ops,
 724};
 725
 726static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 727	.cmd_rcgr = 0x18150,
 728	.mnd_width = 16,
 729	.hid_width = 5,
 730	.parent_map = gcc_parent_map_0,
 731	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 732	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 733};
 734
 735static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s3_clk_src[] = {
 736	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 737	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 738	F(19200000, P_BI_TCXO, 1, 0, 0),
 739	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 740	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 741	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 742	F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
 743	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 744	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 745	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 746	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 747	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 748	{ }
 749};
 750
 751static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 752	.name = "gcc_qupv3_wrap1_s3_clk_src",
 753	.parent_data = gcc_parent_data_0,
 754	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 755	.flags = CLK_SET_RATE_PARENT,
 756	.ops = &clk_rcg2_shared_ops,
 757};
 758
 759static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 760	.cmd_rcgr = 0x182a0,
 761	.mnd_width = 16,
 762	.hid_width = 5,
 763	.parent_map = gcc_parent_map_0,
 764	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
 765	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 766};
 767
 768static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 769	.name = "gcc_qupv3_wrap1_s4_clk_src",
 770	.parent_data = gcc_parent_data_0,
 771	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 772	.flags = CLK_SET_RATE_PARENT,
 773	.ops = &clk_rcg2_shared_ops,
 774};
 775
 776static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 777	.cmd_rcgr = 0x183dc,
 778	.mnd_width = 16,
 779	.hid_width = 5,
 780	.parent_map = gcc_parent_map_0,
 781	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 782	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 783};
 784
 785static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 786	.name = "gcc_qupv3_wrap1_s5_clk_src",
 787	.parent_data = gcc_parent_data_0,
 788	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 789	.flags = CLK_SET_RATE_PARENT,
 790	.ops = &clk_rcg2_shared_ops,
 791};
 792
 793static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 794	.cmd_rcgr = 0x18518,
 795	.mnd_width = 16,
 796	.hid_width = 5,
 797	.parent_map = gcc_parent_map_0,
 798	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
 799	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 800};
 801
 802static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
 803	.name = "gcc_qupv3_wrap1_s6_clk_src",
 804	.parent_data = gcc_parent_data_0,
 805	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 806	.flags = CLK_SET_RATE_PARENT,
 807	.ops = &clk_rcg2_shared_ops,
 808};
 809
 810static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
 811	.cmd_rcgr = 0x18654,
 812	.mnd_width = 16,
 813	.hid_width = 5,
 814	.parent_map = gcc_parent_map_0,
 815	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
 816	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
 817};
 818
 819static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
 820	.name = "gcc_qupv3_wrap1_s7_clk_src",
 821	.parent_data = gcc_parent_data_0,
 822	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 823	.flags = CLK_SET_RATE_PARENT,
 824	.ops = &clk_rcg2_shared_ops,
 825};
 826
 827static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
 828	.cmd_rcgr = 0x18790,
 829	.mnd_width = 16,
 830	.hid_width = 5,
 831	.parent_map = gcc_parent_map_0,
 832	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
 833	.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
 834};
 835
 836static const struct freq_tbl ftbl_gcc_qupv3_wrap2_ibi_ctrl_0_clk_src[] = {
 837	F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
 838	{ }
 839};
 840
 841static struct clk_rcg2 gcc_qupv3_wrap2_ibi_ctrl_0_clk_src = {
 842	.cmd_rcgr = 0x1e9f4,
 843	.mnd_width = 0,
 844	.hid_width = 5,
 845	.parent_map = gcc_parent_map_2,
 846	.freq_tbl = ftbl_gcc_qupv3_wrap2_ibi_ctrl_0_clk_src,
 847	.clkr.hw.init = &(const struct clk_init_data) {
 848		.name = "gcc_qupv3_wrap2_ibi_ctrl_0_clk_src",
 849		.parent_data = gcc_parent_data_2,
 850		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 851		.flags = CLK_SET_RATE_PARENT,
 852		.ops = &clk_rcg2_shared_ops,
 853	},
 854};
 855
 856static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
 857	.name = "gcc_qupv3_wrap2_s0_clk_src",
 858	.parent_data = gcc_parent_data_0,
 859	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 860	.flags = CLK_SET_RATE_PARENT,
 861	.ops = &clk_rcg2_shared_ops,
 862};
 863
 864static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
 865	.cmd_rcgr = 0x1e014,
 866	.mnd_width = 16,
 867	.hid_width = 5,
 868	.parent_map = gcc_parent_map_0,
 869	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 870	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
 871};
 872
 873static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
 874	.name = "gcc_qupv3_wrap2_s1_clk_src",
 875	.parent_data = gcc_parent_data_0,
 876	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 877	.flags = CLK_SET_RATE_PARENT,
 878	.ops = &clk_rcg2_shared_ops,
 879};
 880
 881static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
 882	.cmd_rcgr = 0x1e150,
 883	.mnd_width = 16,
 884	.hid_width = 5,
 885	.parent_map = gcc_parent_map_0,
 886	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 887	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
 888};
 889
 890static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
 891	.name = "gcc_qupv3_wrap2_s2_clk_src",
 892	.parent_data = gcc_parent_data_0,
 893	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 894	.flags = CLK_SET_RATE_PARENT,
 895	.ops = &clk_rcg2_shared_ops,
 896};
 897
 898static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
 899	.cmd_rcgr = 0x1e28c,
 900	.mnd_width = 16,
 901	.hid_width = 5,
 902	.parent_map = gcc_parent_map_0,
 903	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 904	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
 905};
 906
 907static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
 908	.name = "gcc_qupv3_wrap2_s3_clk_src",
 909	.parent_data = gcc_parent_data_0,
 910	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 911	.flags = CLK_SET_RATE_PARENT,
 912	.ops = &clk_rcg2_shared_ops,
 913};
 914
 915static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
 916	.cmd_rcgr = 0x1e3c8,
 917	.mnd_width = 16,
 918	.hid_width = 5,
 919	.parent_map = gcc_parent_map_0,
 920	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 921	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
 922};
 923
 924static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
 925	.name = "gcc_qupv3_wrap2_s4_clk_src",
 926	.parent_data = gcc_parent_data_0,
 927	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 928	.flags = CLK_SET_RATE_PARENT,
 929	.ops = &clk_rcg2_shared_ops,
 930};
 931
 932static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
 933	.cmd_rcgr = 0x1e504,
 934	.mnd_width = 16,
 935	.hid_width = 5,
 936	.parent_map = gcc_parent_map_0,
 937	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
 938	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
 939};
 940
 941static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
 942	.name = "gcc_qupv3_wrap2_s5_clk_src",
 943	.parent_data = gcc_parent_data_0,
 944	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 945	.flags = CLK_SET_RATE_PARENT,
 946	.ops = &clk_rcg2_shared_ops,
 947};
 948
 949static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
 950	.cmd_rcgr = 0x1e640,
 951	.mnd_width = 16,
 952	.hid_width = 5,
 953	.parent_map = gcc_parent_map_0,
 954	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
 955	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
 956};
 957
 958static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s6_clk_src[] = {
 959	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 960	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 961	F(19200000, P_BI_TCXO, 1, 0, 0),
 962	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 963	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 964	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 965	F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
 966	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 967	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 968	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 969	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 970	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 971	F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
 972	F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
 973	F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
 974	F(128000000, P_GCC_GPLL0_OUT_MAIN, 1, 16, 75),
 975	{ }
 976};
 977
 978static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
 979	.name = "gcc_qupv3_wrap2_s6_clk_src",
 980	.parent_data = gcc_parent_data_5,
 981	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
 982	.flags = CLK_SET_RATE_PARENT,
 983	.ops = &clk_rcg2_shared_ops,
 984};
 985
 986static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
 987	.cmd_rcgr = 0x1e77c,
 988	.mnd_width = 16,
 989	.hid_width = 5,
 990	.parent_map = gcc_parent_map_5,
 991	.freq_tbl = ftbl_gcc_qupv3_wrap2_s6_clk_src,
 992	.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
 993};
 994
 995static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
 996	.name = "gcc_qupv3_wrap2_s7_clk_src",
 997	.parent_data = gcc_parent_data_0,
 998	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 999	.flags = CLK_SET_RATE_PARENT,
1000	.ops = &clk_rcg2_shared_ops,
1001};
1002
1003static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
1004	.cmd_rcgr = 0x1e8b8,
1005	.mnd_width = 16,
1006	.hid_width = 5,
1007	.parent_map = gcc_parent_map_0,
1008	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
1009	.clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
1010};
1011
1012static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1013	F(400000, P_BI_TCXO, 12, 1, 4),
1014	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1015	F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
1016	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1017	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1018	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1019	{ }
1020};
1021
1022static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1023	.cmd_rcgr = 0x1401c,
1024	.mnd_width = 8,
1025	.hid_width = 5,
1026	.parent_map = gcc_parent_map_8,
1027	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1028	.clkr.hw.init = &(const struct clk_init_data) {
1029		.name = "gcc_sdcc2_apps_clk_src",
1030		.parent_data = gcc_parent_data_8,
1031		.num_parents = ARRAY_SIZE(gcc_parent_data_8),
1032		.flags = CLK_SET_RATE_PARENT,
1033		.ops = &clk_rcg2_shared_floor_ops,
1034	},
1035};
1036
1037static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
1038	F(400000, P_BI_TCXO, 12, 1, 4),
1039	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1040	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1041	{ }
1042};
1043
1044static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
1045	.cmd_rcgr = 0x1601c,
1046	.mnd_width = 8,
1047	.hid_width = 5,
1048	.parent_map = gcc_parent_map_0,
1049	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
1050	.clkr.hw.init = &(const struct clk_init_data) {
1051		.name = "gcc_sdcc4_apps_clk_src",
1052		.parent_data = gcc_parent_data_0,
1053		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1054		.flags = CLK_SET_RATE_PARENT,
1055		.ops = &clk_rcg2_shared_floor_ops,
1056	},
1057};
1058
1059static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1060	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1061	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1062	F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1063	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1064	{ }
1065};
1066
1067static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1068	.cmd_rcgr = 0x77034,
1069	.mnd_width = 8,
1070	.hid_width = 5,
1071	.parent_map = gcc_parent_map_3,
1072	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1073	.clkr.hw.init = &(const struct clk_init_data) {
1074		.name = "gcc_ufs_phy_axi_clk_src",
1075		.parent_data = gcc_parent_data_3,
1076		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1077		.flags = CLK_SET_RATE_PARENT,
1078		.ops = &clk_rcg2_shared_ops,
1079	},
1080};
1081
1082static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1083	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1084	F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1085	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1086	{ }
1087};
1088
1089static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1090	.cmd_rcgr = 0x7708c,
1091	.mnd_width = 0,
1092	.hid_width = 5,
1093	.parent_map = gcc_parent_map_3,
1094	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1095	.clkr.hw.init = &(const struct clk_init_data) {
1096		.name = "gcc_ufs_phy_ice_core_clk_src",
1097		.parent_data = gcc_parent_data_3,
1098		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1099		.flags = CLK_SET_RATE_PARENT,
1100		.ops = &clk_rcg2_shared_ops,
1101	},
1102};
1103
1104static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
1105	F(9600000, P_BI_TCXO, 2, 0, 0),
1106	F(19200000, P_BI_TCXO, 1, 0, 0),
1107	{ }
1108};
1109
1110static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1111	.cmd_rcgr = 0x770c0,
1112	.mnd_width = 0,
1113	.hid_width = 5,
1114	.parent_map = gcc_parent_map_6,
1115	.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
1116	.clkr.hw.init = &(const struct clk_init_data) {
1117		.name = "gcc_ufs_phy_phy_aux_clk_src",
1118		.parent_data = gcc_parent_data_6,
1119		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
1120		.flags = CLK_SET_RATE_PARENT,
1121		.ops = &clk_rcg2_shared_ops,
1122	},
1123};
1124
1125static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1126	.cmd_rcgr = 0x770a4,
1127	.mnd_width = 0,
1128	.hid_width = 5,
1129	.parent_map = gcc_parent_map_3,
1130	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1131	.clkr.hw.init = &(const struct clk_init_data) {
1132		.name = "gcc_ufs_phy_unipro_core_clk_src",
1133		.parent_data = gcc_parent_data_3,
1134		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1135		.flags = CLK_SET_RATE_PARENT,
1136		.ops = &clk_rcg2_shared_ops,
1137	},
1138};
1139
1140static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1141	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1142	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1143	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1144	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1145	{ }
1146};
1147
1148static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1149	.cmd_rcgr = 0x39030,
1150	.mnd_width = 8,
1151	.hid_width = 5,
1152	.parent_map = gcc_parent_map_0,
1153	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1154	.clkr.hw.init = &(const struct clk_init_data) {
1155		.name = "gcc_usb30_prim_master_clk_src",
1156		.parent_data = gcc_parent_data_0,
1157		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1158		.flags = CLK_SET_RATE_PARENT,
1159		.ops = &clk_rcg2_shared_ops,
1160	},
1161};
1162
1163static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1164	.cmd_rcgr = 0x39048,
1165	.mnd_width = 0,
1166	.hid_width = 5,
1167	.parent_map = gcc_parent_map_0,
1168	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1169	.clkr.hw.init = &(const struct clk_init_data) {
1170		.name = "gcc_usb30_prim_mock_utmi_clk_src",
1171		.parent_data = gcc_parent_data_0,
1172		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1173		.flags = CLK_SET_RATE_PARENT,
1174		.ops = &clk_rcg2_shared_ops,
1175	},
1176};
1177
1178static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1179	.cmd_rcgr = 0x39074,
1180	.mnd_width = 0,
1181	.hid_width = 5,
1182	.parent_map = gcc_parent_map_4,
1183	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1184	.clkr.hw.init = &(const struct clk_init_data) {
1185		.name = "gcc_usb3_prim_phy_aux_clk_src",
1186		.parent_data = gcc_parent_data_4,
1187		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
1188		.flags = CLK_SET_RATE_PARENT,
1189		.ops = &clk_rcg2_shared_ops,
1190	},
1191};
1192
1193static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = {
1194	.reg = 0x1828c,
1195	.shift = 0,
1196	.width = 4,
1197	.clkr.hw.init = &(const struct clk_init_data) {
1198		.name = "gcc_qupv3_wrap1_s2_clk_src",
1199		.parent_hws = (const struct clk_hw*[]) {
1200			&gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw,
1201		},
1202		.num_parents = 1,
1203		.flags = CLK_SET_RATE_PARENT,
1204		.ops = &clk_regmap_div_ro_ops,
1205	},
1206};
1207
1208static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1209	.reg = 0x39060,
1210	.shift = 0,
1211	.width = 4,
1212	.clkr.hw.init = &(const struct clk_init_data) {
1213		.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1214		.parent_hws = (const struct clk_hw*[]) {
1215			&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1216		},
1217		.num_parents = 1,
1218		.flags = CLK_SET_RATE_PARENT,
1219		.ops = &clk_regmap_div_ro_ops,
1220	},
1221};
1222
1223static struct clk_branch gcc_aggre_noc_pcie_axi_clk = {
1224	.halt_reg = 0x10068,
1225	.halt_check = BRANCH_HALT_SKIP,
1226	.hwcg_reg = 0x10068,
1227	.hwcg_bit = 1,
1228	.clkr = {
1229		.enable_reg = 0x52000,
1230		.enable_mask = BIT(12),
1231		.hw.init = &(const struct clk_init_data) {
1232			.name = "gcc_aggre_noc_pcie_axi_clk",
1233			.ops = &clk_branch2_ops,
1234		},
1235	},
1236};
1237
1238static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1239	.halt_reg = 0x770f0,
1240	.halt_check = BRANCH_HALT_VOTED,
1241	.hwcg_reg = 0x770f0,
1242	.hwcg_bit = 1,
1243	.clkr = {
1244		.enable_reg = 0x770f0,
1245		.enable_mask = BIT(0),
1246		.hw.init = &(const struct clk_init_data) {
1247			.name = "gcc_aggre_ufs_phy_axi_clk",
1248			.parent_hws = (const struct clk_hw*[]) {
1249				&gcc_ufs_phy_axi_clk_src.clkr.hw,
1250			},
1251			.num_parents = 1,
1252			.flags = CLK_SET_RATE_PARENT,
1253			.ops = &clk_branch2_ops,
1254		},
1255	},
1256};
1257
1258static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1259	.halt_reg = 0x39090,
1260	.halt_check = BRANCH_HALT_VOTED,
1261	.hwcg_reg = 0x39090,
1262	.hwcg_bit = 1,
1263	.clkr = {
1264		.enable_reg = 0x39090,
1265		.enable_mask = BIT(0),
1266		.hw.init = &(const struct clk_init_data) {
1267			.name = "gcc_aggre_usb3_prim_axi_clk",
1268			.parent_hws = (const struct clk_hw*[]) {
1269				&gcc_usb30_prim_master_clk_src.clkr.hw,
1270			},
1271			.num_parents = 1,
1272			.flags = CLK_SET_RATE_PARENT,
1273			.ops = &clk_branch2_ops,
1274		},
1275	},
1276};
1277
1278static struct clk_branch gcc_boot_rom_ahb_clk = {
1279	.halt_reg = 0x38004,
1280	.halt_check = BRANCH_HALT_VOTED,
1281	.hwcg_reg = 0x38004,
1282	.hwcg_bit = 1,
1283	.clkr = {
1284		.enable_reg = 0x52000,
1285		.enable_mask = BIT(10),
1286		.hw.init = &(const struct clk_init_data) {
1287			.name = "gcc_boot_rom_ahb_clk",
1288			.ops = &clk_branch2_ops,
1289		},
1290	},
1291};
1292
1293static struct clk_branch gcc_camera_hf_axi_clk = {
1294	.halt_reg = 0x26014,
1295	.halt_check = BRANCH_HALT_SKIP,
1296	.hwcg_reg = 0x26014,
1297	.hwcg_bit = 1,
1298	.clkr = {
1299		.enable_reg = 0x26014,
1300		.enable_mask = BIT(0),
1301		.hw.init = &(const struct clk_init_data) {
1302			.name = "gcc_camera_hf_axi_clk",
1303			.ops = &clk_branch2_ops,
1304		},
1305	},
1306};
1307
1308static struct clk_branch gcc_camera_sf_axi_clk = {
1309	.halt_reg = 0x26024,
1310	.halt_check = BRANCH_HALT_SKIP,
1311	.hwcg_reg = 0x26024,
1312	.hwcg_bit = 1,
1313	.clkr = {
1314		.enable_reg = 0x26024,
1315		.enable_mask = BIT(0),
1316		.hw.init = &(const struct clk_init_data) {
1317			.name = "gcc_camera_sf_axi_clk",
1318			.ops = &clk_branch2_ops,
1319		},
1320	},
1321};
1322
1323static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
1324	.halt_reg = 0x10050,
1325	.halt_check = BRANCH_HALT_VOTED,
1326	.hwcg_reg = 0x10050,
1327	.hwcg_bit = 1,
1328	.clkr = {
1329		.enable_reg = 0x52000,
1330		.enable_mask = BIT(20),
1331		.hw.init = &(const struct clk_init_data) {
1332			.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
1333			.ops = &clk_branch2_ops,
1334		},
1335	},
1336};
1337
1338static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1339	.halt_reg = 0x3908c,
1340	.halt_check = BRANCH_HALT_VOTED,
1341	.hwcg_reg = 0x3908c,
1342	.hwcg_bit = 1,
1343	.clkr = {
1344		.enable_reg = 0x3908c,
1345		.enable_mask = BIT(0),
1346		.hw.init = &(const struct clk_init_data) {
1347			.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1348			.parent_hws = (const struct clk_hw*[]) {
1349				&gcc_usb30_prim_master_clk_src.clkr.hw,
1350			},
1351			.num_parents = 1,
1352			.flags = CLK_SET_RATE_PARENT,
1353			.ops = &clk_branch2_ops,
1354		},
1355	},
1356};
1357
1358static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = {
1359	.halt_reg = 0x10058,
1360	.halt_check = BRANCH_HALT_VOTED,
1361	.hwcg_reg = 0x10058,
1362	.hwcg_bit = 1,
1363	.clkr = {
1364		.enable_reg = 0x52008,
1365		.enable_mask = BIT(6),
1366		.hw.init = &(const struct clk_init_data) {
1367			.name = "gcc_cnoc_pcie_sf_axi_clk",
1368			.ops = &clk_branch2_ops,
1369		},
1370	},
1371};
1372
1373static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1374	.halt_reg = 0x71150,
1375	.halt_check = BRANCH_HALT_SKIP,
1376	.hwcg_reg = 0x71150,
1377	.hwcg_bit = 1,
1378	.clkr = {
1379		.enable_reg = 0x71150,
1380		.enable_mask = BIT(0),
1381		.hw.init = &(const struct clk_init_data) {
1382			.name = "gcc_ddrss_gpu_axi_clk",
1383			.ops = &clk_branch2_aon_ops,
1384		},
1385	},
1386};
1387
1388static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = {
1389	.halt_reg = 0x1007c,
1390	.halt_check = BRANCH_HALT_SKIP,
1391	.hwcg_reg = 0x1007c,
1392	.hwcg_bit = 1,
1393	.clkr = {
1394		.enable_reg = 0x52000,
1395		.enable_mask = BIT(19),
1396		.hw.init = &(const struct clk_init_data) {
1397			.name = "gcc_ddrss_pcie_sf_qtb_clk",
1398			.ops = &clk_branch2_ops,
1399		},
1400	},
1401};
1402
1403static struct clk_branch gcc_disp_hf_axi_clk = {
1404	.halt_reg = 0x27008,
1405	.halt_check = BRANCH_HALT_SKIP,
1406	.clkr = {
1407		.enable_reg = 0x27008,
1408		.enable_mask = BIT(0),
1409		.hw.init = &(const struct clk_init_data) {
1410			.name = "gcc_disp_hf_axi_clk",
1411			.ops = &clk_branch2_ops,
1412		},
1413	},
1414};
1415
1416static struct clk_branch gcc_eva_axi0_clk = {
1417	.halt_reg = 0x9f008,
1418	.halt_check = BRANCH_HALT_SKIP,
1419	.hwcg_reg = 0x9f008,
1420	.hwcg_bit = 1,
1421	.clkr = {
1422		.enable_reg = 0x9f008,
1423		.enable_mask = BIT(0),
1424		.hw.init = &(const struct clk_init_data) {
1425			.name = "gcc_eva_axi0_clk",
1426			.ops = &clk_branch2_ops,
1427		},
1428	},
1429};
1430
1431static struct clk_branch gcc_eva_axi0c_clk = {
1432	.halt_reg = 0x9f018,
1433	.halt_check = BRANCH_HALT_SKIP,
1434	.hwcg_reg = 0x9f018,
1435	.hwcg_bit = 1,
1436	.clkr = {
1437		.enable_reg = 0x9f018,
1438		.enable_mask = BIT(0),
1439		.hw.init = &(const struct clk_init_data) {
1440			.name = "gcc_eva_axi0c_clk",
1441			.ops = &clk_branch2_ops,
1442		},
1443	},
1444};
1445
1446static struct clk_branch gcc_gp1_clk = {
1447	.halt_reg = 0x64000,
1448	.halt_check = BRANCH_HALT,
1449	.clkr = {
1450		.enable_reg = 0x64000,
1451		.enable_mask = BIT(0),
1452		.hw.init = &(const struct clk_init_data) {
1453			.name = "gcc_gp1_clk",
1454			.parent_hws = (const struct clk_hw*[]) {
1455				&gcc_gp1_clk_src.clkr.hw,
1456			},
1457			.num_parents = 1,
1458			.flags = CLK_SET_RATE_PARENT,
1459			.ops = &clk_branch2_ops,
1460		},
1461	},
1462};
1463
1464static struct clk_branch gcc_gp2_clk = {
1465	.halt_reg = 0x65000,
1466	.halt_check = BRANCH_HALT,
1467	.clkr = {
1468		.enable_reg = 0x65000,
1469		.enable_mask = BIT(0),
1470		.hw.init = &(const struct clk_init_data) {
1471			.name = "gcc_gp2_clk",
1472			.parent_hws = (const struct clk_hw*[]) {
1473				&gcc_gp2_clk_src.clkr.hw,
1474			},
1475			.num_parents = 1,
1476			.flags = CLK_SET_RATE_PARENT,
1477			.ops = &clk_branch2_ops,
1478		},
1479	},
1480};
1481
1482static struct clk_branch gcc_gp3_clk = {
1483	.halt_reg = 0x66000,
1484	.halt_check = BRANCH_HALT,
1485	.clkr = {
1486		.enable_reg = 0x66000,
1487		.enable_mask = BIT(0),
1488		.hw.init = &(const struct clk_init_data) {
1489			.name = "gcc_gp3_clk",
1490			.parent_hws = (const struct clk_hw*[]) {
1491				&gcc_gp3_clk_src.clkr.hw,
1492			},
1493			.num_parents = 1,
1494			.flags = CLK_SET_RATE_PARENT,
1495			.ops = &clk_branch2_ops,
1496		},
1497	},
1498};
1499
1500static struct clk_branch gcc_gpu_gemnoc_gfx_clk = {
1501	.halt_reg = 0x71010,
1502	.halt_check = BRANCH_HALT_VOTED,
1503	.hwcg_reg = 0x71010,
1504	.hwcg_bit = 1,
1505	.clkr = {
1506		.enable_reg = 0x71010,
1507		.enable_mask = BIT(0),
1508		.hw.init = &(const struct clk_init_data) {
1509			.name = "gcc_gpu_gemnoc_gfx_clk",
1510			.ops = &clk_branch2_ops,
1511		},
1512	},
1513};
1514
1515static struct clk_branch gcc_gpu_gpll0_clk_src = {
1516	.halt_check = BRANCH_HALT_DELAY,
1517	.clkr = {
1518		.enable_reg = 0x52000,
1519		.enable_mask = BIT(15),
1520		.hw.init = &(const struct clk_init_data) {
1521			.name = "gcc_gpu_gpll0_clk_src",
1522			.parent_hws = (const struct clk_hw*[]) {
1523				&gcc_gpll0.clkr.hw,
1524			},
1525			.num_parents = 1,
1526			.flags = CLK_SET_RATE_PARENT,
1527			.ops = &clk_branch2_ops,
1528		},
1529	},
1530};
1531
1532static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1533	.halt_check = BRANCH_HALT_DELAY,
1534	.clkr = {
1535		.enable_reg = 0x52000,
1536		.enable_mask = BIT(16),
1537		.hw.init = &(const struct clk_init_data) {
1538			.name = "gcc_gpu_gpll0_div_clk_src",
1539			.parent_hws = (const struct clk_hw*[]) {
1540				&gcc_gpll0_out_even.clkr.hw,
1541			},
1542			.num_parents = 1,
1543			.flags = CLK_SET_RATE_PARENT,
1544			.ops = &clk_branch2_ops,
1545		},
1546	},
1547};
1548
1549static struct clk_branch gcc_pcie_0_aux_clk = {
1550	.halt_reg = 0x6b044,
1551	.halt_check = BRANCH_HALT_VOTED,
1552	.clkr = {
1553		.enable_reg = 0x52008,
1554		.enable_mask = BIT(3),
1555		.hw.init = &(const struct clk_init_data) {
1556			.name = "gcc_pcie_0_aux_clk",
1557			.parent_hws = (const struct clk_hw*[]) {
1558				&gcc_pcie_0_aux_clk_src.clkr.hw,
1559			},
1560			.num_parents = 1,
1561			.flags = CLK_SET_RATE_PARENT,
1562			.ops = &clk_branch2_ops,
1563		},
1564	},
1565};
1566
1567static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1568	.halt_reg = 0x6b040,
1569	.halt_check = BRANCH_HALT_VOTED,
1570	.hwcg_reg = 0x6b040,
1571	.hwcg_bit = 1,
1572	.clkr = {
1573		.enable_reg = 0x52008,
1574		.enable_mask = BIT(2),
1575		.hw.init = &(const struct clk_init_data) {
1576			.name = "gcc_pcie_0_cfg_ahb_clk",
1577			.ops = &clk_branch2_ops,
1578		},
1579	},
1580};
1581
1582static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1583	.halt_reg = 0x6b030,
1584	.halt_check = BRANCH_HALT_SKIP,
1585	.hwcg_reg = 0x6b030,
1586	.hwcg_bit = 1,
1587	.clkr = {
1588		.enable_reg = 0x52008,
1589		.enable_mask = BIT(1),
1590		.hw.init = &(const struct clk_init_data) {
1591			.name = "gcc_pcie_0_mstr_axi_clk",
1592			.ops = &clk_branch2_ops,
1593		},
1594	},
1595};
1596
1597static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
1598	.halt_reg = 0x6b064,
1599	.halt_check = BRANCH_HALT_VOTED,
1600	.clkr = {
1601		.enable_reg = 0x52000,
1602		.enable_mask = BIT(22),
1603		.hw.init = &(const struct clk_init_data) {
1604			.name = "gcc_pcie_0_phy_rchng_clk",
1605			.parent_hws = (const struct clk_hw*[]) {
1606				&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1607			},
1608			.num_parents = 1,
1609			.flags = CLK_SET_RATE_PARENT,
1610			.ops = &clk_branch2_ops,
1611		},
1612	},
1613};
1614
1615static struct clk_branch gcc_pcie_0_pipe_clk = {
1616	.halt_reg = 0x6b054,
1617	.halt_check = BRANCH_HALT_SKIP,
1618	.clkr = {
1619		.enable_reg = 0x52008,
1620		.enable_mask = BIT(4),
1621		.hw.init = &(const struct clk_init_data) {
1622			.name = "gcc_pcie_0_pipe_clk",
1623			.parent_hws = (const struct clk_hw*[]) {
1624				&gcc_pcie_0_pipe_clk_src.clkr.hw,
1625			},
1626			.num_parents = 1,
1627			.flags = CLK_SET_RATE_PARENT,
1628			.ops = &clk_branch2_ops,
1629		},
1630	},
1631};
1632
1633static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1634	.halt_reg = 0x6b020,
1635	.halt_check = BRANCH_HALT_VOTED,
1636	.hwcg_reg = 0x6b020,
1637	.hwcg_bit = 1,
1638	.clkr = {
1639		.enable_reg = 0x52008,
1640		.enable_mask = BIT(0),
1641		.hw.init = &(const struct clk_init_data) {
1642			.name = "gcc_pcie_0_slv_axi_clk",
1643			.ops = &clk_branch2_ops,
1644		},
1645	},
1646};
1647
1648static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1649	.halt_reg = 0x6b01c,
1650	.halt_check = BRANCH_HALT_VOTED,
1651	.clkr = {
1652		.enable_reg = 0x52008,
1653		.enable_mask = BIT(5),
1654		.hw.init = &(const struct clk_init_data) {
1655			.name = "gcc_pcie_0_slv_q2a_axi_clk",
1656			.ops = &clk_branch2_ops,
1657		},
1658	},
1659};
1660
1661static struct clk_branch gcc_pdm2_clk = {
1662	.halt_reg = 0x3300c,
1663	.halt_check = BRANCH_HALT,
1664	.clkr = {
1665		.enable_reg = 0x3300c,
1666		.enable_mask = BIT(0),
1667		.hw.init = &(const struct clk_init_data) {
1668			.name = "gcc_pdm2_clk",
1669			.parent_hws = (const struct clk_hw*[]) {
1670				&gcc_pdm2_clk_src.clkr.hw,
1671			},
1672			.num_parents = 1,
1673			.flags = CLK_SET_RATE_PARENT,
1674			.ops = &clk_branch2_ops,
1675		},
1676	},
1677};
1678
1679static struct clk_branch gcc_pdm_ahb_clk = {
1680	.halt_reg = 0x33004,
1681	.halt_check = BRANCH_HALT_VOTED,
1682	.hwcg_reg = 0x33004,
1683	.hwcg_bit = 1,
1684	.clkr = {
1685		.enable_reg = 0x33004,
1686		.enable_mask = BIT(0),
1687		.hw.init = &(const struct clk_init_data) {
1688			.name = "gcc_pdm_ahb_clk",
1689			.ops = &clk_branch2_ops,
1690		},
1691	},
1692};
1693
1694static struct clk_branch gcc_pdm_xo4_clk = {
1695	.halt_reg = 0x33008,
1696	.halt_check = BRANCH_HALT,
1697	.clkr = {
1698		.enable_reg = 0x33008,
1699		.enable_mask = BIT(0),
1700		.hw.init = &(const struct clk_init_data) {
1701			.name = "gcc_pdm_xo4_clk",
1702			.ops = &clk_branch2_ops,
1703		},
1704	},
1705};
1706
1707static struct clk_branch gcc_qmip_camera_cmd_ahb_clk = {
1708	.halt_reg = 0x26010,
1709	.halt_check = BRANCH_HALT_VOTED,
1710	.hwcg_reg = 0x26010,
1711	.hwcg_bit = 1,
1712	.clkr = {
1713		.enable_reg = 0x26010,
1714		.enable_mask = BIT(0),
1715		.hw.init = &(const struct clk_init_data) {
1716			.name = "gcc_qmip_camera_cmd_ahb_clk",
1717			.ops = &clk_branch2_ops,
1718		},
1719	},
1720};
1721
1722static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1723	.halt_reg = 0x26008,
1724	.halt_check = BRANCH_HALT_VOTED,
1725	.hwcg_reg = 0x26008,
1726	.hwcg_bit = 1,
1727	.clkr = {
1728		.enable_reg = 0x26008,
1729		.enable_mask = BIT(0),
1730		.hw.init = &(const struct clk_init_data) {
1731			.name = "gcc_qmip_camera_nrt_ahb_clk",
1732			.ops = &clk_branch2_ops,
1733		},
1734	},
1735};
1736
1737static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
1738	.halt_reg = 0x2600c,
1739	.halt_check = BRANCH_HALT_VOTED,
1740	.hwcg_reg = 0x2600c,
1741	.hwcg_bit = 1,
1742	.clkr = {
1743		.enable_reg = 0x2600c,
1744		.enable_mask = BIT(0),
1745		.hw.init = &(const struct clk_init_data) {
1746			.name = "gcc_qmip_camera_rt_ahb_clk",
1747			.ops = &clk_branch2_ops,
1748		},
1749	},
1750};
1751
1752static struct clk_branch gcc_qmip_gpu_ahb_clk = {
1753	.halt_reg = 0x71008,
1754	.halt_check = BRANCH_HALT_VOTED,
1755	.hwcg_reg = 0x71008,
1756	.hwcg_bit = 1,
1757	.clkr = {
1758		.enable_reg = 0x71008,
1759		.enable_mask = BIT(0),
1760		.hw.init = &(const struct clk_init_data) {
1761			.name = "gcc_qmip_gpu_ahb_clk",
1762			.ops = &clk_branch2_ops,
1763		},
1764	},
1765};
1766
1767static struct clk_branch gcc_qmip_pcie_ahb_clk = {
1768	.halt_reg = 0x6b018,
1769	.halt_check = BRANCH_HALT_VOTED,
1770	.hwcg_reg = 0x6b018,
1771	.hwcg_bit = 1,
1772	.clkr = {
1773		.enable_reg = 0x52000,
1774		.enable_mask = BIT(11),
1775		.hw.init = &(const struct clk_init_data) {
1776			.name = "gcc_qmip_pcie_ahb_clk",
1777			.ops = &clk_branch2_ops,
1778		},
1779	},
1780};
1781
1782static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
1783	.halt_reg = 0x32014,
1784	.halt_check = BRANCH_HALT_VOTED,
1785	.hwcg_reg = 0x32014,
1786	.hwcg_bit = 1,
1787	.clkr = {
1788		.enable_reg = 0x32014,
1789		.enable_mask = BIT(0),
1790		.hw.init = &(const struct clk_init_data) {
1791			.name = "gcc_qmip_video_cv_cpu_ahb_clk",
1792			.ops = &clk_branch2_ops,
1793		},
1794	},
1795};
1796
1797static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
1798	.halt_reg = 0x32008,
1799	.halt_check = BRANCH_HALT_VOTED,
1800	.hwcg_reg = 0x32008,
1801	.hwcg_bit = 1,
1802	.clkr = {
1803		.enable_reg = 0x32008,
1804		.enable_mask = BIT(0),
1805		.hw.init = &(const struct clk_init_data) {
1806			.name = "gcc_qmip_video_cvp_ahb_clk",
1807			.ops = &clk_branch2_ops,
1808		},
1809	},
1810};
1811
1812static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
1813	.halt_reg = 0x32010,
1814	.halt_check = BRANCH_HALT_VOTED,
1815	.hwcg_reg = 0x32010,
1816	.hwcg_bit = 1,
1817	.clkr = {
1818		.enable_reg = 0x32010,
1819		.enable_mask = BIT(0),
1820		.hw.init = &(const struct clk_init_data) {
1821			.name = "gcc_qmip_video_v_cpu_ahb_clk",
1822			.ops = &clk_branch2_ops,
1823		},
1824	},
1825};
1826
1827static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
1828	.halt_reg = 0x3200c,
1829	.halt_check = BRANCH_HALT_VOTED,
1830	.hwcg_reg = 0x3200c,
1831	.hwcg_bit = 1,
1832	.clkr = {
1833		.enable_reg = 0x3200c,
1834		.enable_mask = BIT(0),
1835		.hw.init = &(const struct clk_init_data) {
1836			.name = "gcc_qmip_video_vcodec_ahb_clk",
1837			.ops = &clk_branch2_ops,
1838		},
1839	},
1840};
1841
1842static struct clk_branch gcc_qupv3_i2c_core_clk = {
1843	.halt_reg = 0x23004,
1844	.halt_check = BRANCH_HALT_VOTED,
1845	.clkr = {
1846		.enable_reg = 0x52008,
1847		.enable_mask = BIT(8),
1848		.hw.init = &(const struct clk_init_data) {
1849			.name = "gcc_qupv3_i2c_core_clk",
1850			.ops = &clk_branch2_ops,
1851		},
1852	},
1853};
1854
1855static struct clk_branch gcc_qupv3_i2c_s0_clk = {
1856	.halt_reg = 0x17004,
1857	.halt_check = BRANCH_HALT_VOTED,
1858	.clkr = {
1859		.enable_reg = 0x52008,
1860		.enable_mask = BIT(10),
1861		.hw.init = &(const struct clk_init_data) {
1862			.name = "gcc_qupv3_i2c_s0_clk",
1863			.parent_hws = (const struct clk_hw*[]) {
1864				&gcc_qupv3_i2c_s0_clk_src.clkr.hw,
1865			},
1866			.num_parents = 1,
1867			.flags = CLK_SET_RATE_PARENT,
1868			.ops = &clk_branch2_ops,
1869		},
1870	},
1871};
1872
1873static struct clk_branch gcc_qupv3_i2c_s1_clk = {
1874	.halt_reg = 0x17020,
1875	.halt_check = BRANCH_HALT_VOTED,
1876	.clkr = {
1877		.enable_reg = 0x52008,
1878		.enable_mask = BIT(11),
1879		.hw.init = &(const struct clk_init_data) {
1880			.name = "gcc_qupv3_i2c_s1_clk",
1881			.parent_hws = (const struct clk_hw*[]) {
1882				&gcc_qupv3_i2c_s1_clk_src.clkr.hw,
1883			},
1884			.num_parents = 1,
1885			.flags = CLK_SET_RATE_PARENT,
1886			.ops = &clk_branch2_ops,
1887		},
1888	},
1889};
1890
1891static struct clk_branch gcc_qupv3_i2c_s2_clk = {
1892	.halt_reg = 0x1703c,
1893	.halt_check = BRANCH_HALT_VOTED,
1894	.clkr = {
1895		.enable_reg = 0x52008,
1896		.enable_mask = BIT(12),
1897		.hw.init = &(const struct clk_init_data) {
1898			.name = "gcc_qupv3_i2c_s2_clk",
1899			.parent_hws = (const struct clk_hw*[]) {
1900				&gcc_qupv3_i2c_s2_clk_src.clkr.hw,
1901			},
1902			.num_parents = 1,
1903			.flags = CLK_SET_RATE_PARENT,
1904			.ops = &clk_branch2_ops,
1905		},
1906	},
1907};
1908
1909static struct clk_branch gcc_qupv3_i2c_s3_clk = {
1910	.halt_reg = 0x17058,
1911	.halt_check = BRANCH_HALT_VOTED,
1912	.clkr = {
1913		.enable_reg = 0x52008,
1914		.enable_mask = BIT(13),
1915		.hw.init = &(const struct clk_init_data) {
1916			.name = "gcc_qupv3_i2c_s3_clk",
1917			.parent_hws = (const struct clk_hw*[]) {
1918				&gcc_qupv3_i2c_s3_clk_src.clkr.hw,
1919			},
1920			.num_parents = 1,
1921			.flags = CLK_SET_RATE_PARENT,
1922			.ops = &clk_branch2_ops,
1923		},
1924	},
1925};
1926
1927static struct clk_branch gcc_qupv3_i2c_s4_clk = {
1928	.halt_reg = 0x17074,
1929	.halt_check = BRANCH_HALT_VOTED,
1930	.clkr = {
1931		.enable_reg = 0x52008,
1932		.enable_mask = BIT(14),
1933		.hw.init = &(const struct clk_init_data) {
1934			.name = "gcc_qupv3_i2c_s4_clk",
1935			.parent_hws = (const struct clk_hw*[]) {
1936				&gcc_qupv3_i2c_s4_clk_src.clkr.hw,
1937			},
1938			.num_parents = 1,
1939			.flags = CLK_SET_RATE_PARENT,
1940			.ops = &clk_branch2_ops,
1941		},
1942	},
1943};
1944
1945static struct clk_branch gcc_qupv3_i2c_s5_clk = {
1946	.halt_reg = 0x17090,
1947	.halt_check = BRANCH_HALT_VOTED,
1948	.clkr = {
1949		.enable_reg = 0x52008,
1950		.enable_mask = BIT(15),
1951		.hw.init = &(const struct clk_init_data) {
1952			.name = "gcc_qupv3_i2c_s5_clk",
1953			.parent_hws = (const struct clk_hw*[]) {
1954				&gcc_qupv3_i2c_s5_clk_src.clkr.hw,
1955			},
1956			.num_parents = 1,
1957			.flags = CLK_SET_RATE_PARENT,
1958			.ops = &clk_branch2_ops,
1959		},
1960	},
1961};
1962
1963static struct clk_branch gcc_qupv3_i2c_s6_clk = {
1964	.halt_reg = 0x170ac,
1965	.halt_check = BRANCH_HALT_VOTED,
1966	.clkr = {
1967		.enable_reg = 0x52008,
1968		.enable_mask = BIT(16),
1969		.hw.init = &(const struct clk_init_data) {
1970			.name = "gcc_qupv3_i2c_s6_clk",
1971			.parent_hws = (const struct clk_hw*[]) {
1972				&gcc_qupv3_i2c_s6_clk_src.clkr.hw,
1973			},
1974			.num_parents = 1,
1975			.flags = CLK_SET_RATE_PARENT,
1976			.ops = &clk_branch2_ops,
1977		},
1978	},
1979};
1980
1981static struct clk_branch gcc_qupv3_i2c_s7_clk = {
1982	.halt_reg = 0x170c8,
1983	.halt_check = BRANCH_HALT_VOTED,
1984	.clkr = {
1985		.enable_reg = 0x52008,
1986		.enable_mask = BIT(17),
1987		.hw.init = &(const struct clk_init_data) {
1988			.name = "gcc_qupv3_i2c_s7_clk",
1989			.parent_hws = (const struct clk_hw*[]) {
1990				&gcc_qupv3_i2c_s7_clk_src.clkr.hw,
1991			},
1992			.num_parents = 1,
1993			.flags = CLK_SET_RATE_PARENT,
1994			.ops = &clk_branch2_ops,
1995		},
1996	},
1997};
1998
1999static struct clk_branch gcc_qupv3_i2c_s8_clk = {
2000	.halt_reg = 0x170e4,
2001	.halt_check = BRANCH_HALT_VOTED,
2002	.clkr = {
2003		.enable_reg = 0x52010,
2004		.enable_mask = BIT(14),
2005		.hw.init = &(const struct clk_init_data) {
2006			.name = "gcc_qupv3_i2c_s8_clk",
2007			.parent_hws = (const struct clk_hw*[]) {
2008				&gcc_qupv3_i2c_s8_clk_src.clkr.hw,
2009			},
2010			.num_parents = 1,
2011			.flags = CLK_SET_RATE_PARENT,
2012			.ops = &clk_branch2_ops,
2013		},
2014	},
2015};
2016
2017static struct clk_branch gcc_qupv3_i2c_s9_clk = {
2018	.halt_reg = 0x17100,
2019	.halt_check = BRANCH_HALT_VOTED,
2020	.clkr = {
2021		.enable_reg = 0x52010,
2022		.enable_mask = BIT(15),
2023		.hw.init = &(const struct clk_init_data) {
2024			.name = "gcc_qupv3_i2c_s9_clk",
2025			.parent_hws = (const struct clk_hw*[]) {
2026				&gcc_qupv3_i2c_s9_clk_src.clkr.hw,
2027			},
2028			.num_parents = 1,
2029			.flags = CLK_SET_RATE_PARENT,
2030			.ops = &clk_branch2_ops,
2031		},
2032	},
2033};
2034
2035static struct clk_branch gcc_qupv3_i2c_s_ahb_clk = {
2036	.halt_reg = 0x23000,
2037	.halt_check = BRANCH_HALT_VOTED,
2038	.hwcg_reg = 0x23000,
2039	.hwcg_bit = 1,
2040	.clkr = {
2041		.enable_reg = 0x52008,
2042		.enable_mask = BIT(7),
2043		.hw.init = &(const struct clk_init_data) {
2044			.name = "gcc_qupv3_i2c_s_ahb_clk",
2045			.ops = &clk_branch2_ops,
2046		},
2047	},
2048};
2049
2050static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2051	.halt_reg = 0x2315c,
2052	.halt_check = BRANCH_HALT_VOTED,
2053	.clkr = {
2054		.enable_reg = 0x52008,
2055		.enable_mask = BIT(18),
2056		.hw.init = &(const struct clk_init_data) {
2057			.name = "gcc_qupv3_wrap1_core_2x_clk",
2058			.ops = &clk_branch2_ops,
2059		},
2060	},
2061};
2062
2063static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2064	.halt_reg = 0x23148,
2065	.halt_check = BRANCH_HALT_VOTED,
2066	.clkr = {
2067		.enable_reg = 0x52008,
2068		.enable_mask = BIT(19),
2069		.hw.init = &(const struct clk_init_data) {
2070			.name = "gcc_qupv3_wrap1_core_clk",
2071			.ops = &clk_branch2_ops,
2072		},
2073	},
2074};
2075
2076static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk = {
2077	.halt_reg = 0x188bc,
2078	.halt_check = BRANCH_HALT_VOTED,
2079	.clkr = {
2080		.enable_reg = 0x52010,
2081		.enable_mask = BIT(29),
2082		.hw.init = &(const struct clk_init_data) {
2083			.name = "gcc_qupv3_wrap1_qspi_ref_clk",
2084			.parent_hws = (const struct clk_hw*[]) {
2085				&gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw,
2086			},
2087			.num_parents = 1,
2088			.flags = CLK_SET_RATE_PARENT,
2089			.ops = &clk_branch2_ops,
2090		},
2091	},
2092};
2093
2094static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2095	.halt_reg = 0x18004,
2096	.halt_check = BRANCH_HALT_VOTED,
2097	.clkr = {
2098		.enable_reg = 0x52008,
2099		.enable_mask = BIT(22),
2100		.hw.init = &(const struct clk_init_data) {
2101			.name = "gcc_qupv3_wrap1_s0_clk",
2102			.parent_hws = (const struct clk_hw*[]) {
2103				&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2104			},
2105			.num_parents = 1,
2106			.flags = CLK_SET_RATE_PARENT,
2107			.ops = &clk_branch2_ops,
2108		},
2109	},
2110};
2111
2112static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2113	.halt_reg = 0x18140,
2114	.halt_check = BRANCH_HALT_VOTED,
2115	.clkr = {
2116		.enable_reg = 0x52008,
2117		.enable_mask = BIT(23),
2118		.hw.init = &(const struct clk_init_data) {
2119			.name = "gcc_qupv3_wrap1_s1_clk",
2120			.parent_hws = (const struct clk_hw*[]) {
2121				&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2122			},
2123			.num_parents = 1,
2124			.flags = CLK_SET_RATE_PARENT,
2125			.ops = &clk_branch2_ops,
2126		},
2127	},
2128};
2129
2130static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2131	.halt_reg = 0x1827c,
2132	.halt_check = BRANCH_HALT_VOTED,
2133	.clkr = {
2134		.enable_reg = 0x52008,
2135		.enable_mask = BIT(24),
2136		.hw.init = &(const struct clk_init_data) {
2137			.name = "gcc_qupv3_wrap1_s2_clk",
2138			.parent_hws = (const struct clk_hw*[]) {
2139				&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2140			},
2141			.num_parents = 1,
2142			.flags = CLK_SET_RATE_PARENT,
2143			.ops = &clk_branch2_ops,
2144		},
2145	},
2146};
2147
2148static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2149	.halt_reg = 0x18290,
2150	.halt_check = BRANCH_HALT_VOTED,
2151	.clkr = {
2152		.enable_reg = 0x52008,
2153		.enable_mask = BIT(25),
2154		.hw.init = &(const struct clk_init_data) {
2155			.name = "gcc_qupv3_wrap1_s3_clk",
2156			.parent_hws = (const struct clk_hw*[]) {
2157				&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2158			},
2159			.num_parents = 1,
2160			.flags = CLK_SET_RATE_PARENT,
2161			.ops = &clk_branch2_ops,
2162		},
2163	},
2164};
2165
2166static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2167	.halt_reg = 0x183cc,
2168	.halt_check = BRANCH_HALT_VOTED,
2169	.clkr = {
2170		.enable_reg = 0x52008,
2171		.enable_mask = BIT(26),
2172		.hw.init = &(const struct clk_init_data) {
2173			.name = "gcc_qupv3_wrap1_s4_clk",
2174			.parent_hws = (const struct clk_hw*[]) {
2175				&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2176			},
2177			.num_parents = 1,
2178			.flags = CLK_SET_RATE_PARENT,
2179			.ops = &clk_branch2_ops,
2180		},
2181	},
2182};
2183
2184static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2185	.halt_reg = 0x18508,
2186	.halt_check = BRANCH_HALT_VOTED,
2187	.clkr = {
2188		.enable_reg = 0x52008,
2189		.enable_mask = BIT(27),
2190		.hw.init = &(const struct clk_init_data) {
2191			.name = "gcc_qupv3_wrap1_s5_clk",
2192			.parent_hws = (const struct clk_hw*[]) {
2193				&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2194			},
2195			.num_parents = 1,
2196			.flags = CLK_SET_RATE_PARENT,
2197			.ops = &clk_branch2_ops,
2198		},
2199	},
2200};
2201
2202static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2203	.halt_reg = 0x18644,
2204	.halt_check = BRANCH_HALT_VOTED,
2205	.clkr = {
2206		.enable_reg = 0x52008,
2207		.enable_mask = BIT(28),
2208		.hw.init = &(const struct clk_init_data) {
2209			.name = "gcc_qupv3_wrap1_s6_clk",
2210			.parent_hws = (const struct clk_hw*[]) {
2211				&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2212			},
2213			.num_parents = 1,
2214			.flags = CLK_SET_RATE_PARENT,
2215			.ops = &clk_branch2_ops,
2216		},
2217	},
2218};
2219
2220static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2221	.halt_reg = 0x18780,
2222	.halt_check = BRANCH_HALT_VOTED,
2223	.clkr = {
2224		.enable_reg = 0x52010,
2225		.enable_mask = BIT(16),
2226		.hw.init = &(const struct clk_init_data) {
2227			.name = "gcc_qupv3_wrap1_s7_clk",
2228			.parent_hws = (const struct clk_hw*[]) {
2229				&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
2230			},
2231			.num_parents = 1,
2232			.flags = CLK_SET_RATE_PARENT,
2233			.ops = &clk_branch2_ops,
2234		},
2235	},
2236};
2237
2238static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
2239	.halt_reg = 0x232b4,
2240	.halt_check = BRANCH_HALT_VOTED,
2241	.clkr = {
2242		.enable_reg = 0x52010,
2243		.enable_mask = BIT(3),
2244		.hw.init = &(const struct clk_init_data) {
2245			.name = "gcc_qupv3_wrap2_core_2x_clk",
2246			.ops = &clk_branch2_ops,
2247		},
2248	},
2249};
2250
2251static struct clk_branch gcc_qupv3_wrap2_core_clk = {
2252	.halt_reg = 0x232a0,
2253	.halt_check = BRANCH_HALT_VOTED,
2254	.clkr = {
2255		.enable_reg = 0x52010,
2256		.enable_mask = BIT(0),
2257		.hw.init = &(const struct clk_init_data) {
2258			.name = "gcc_qupv3_wrap2_core_clk",
2259			.ops = &clk_branch2_ops,
2260		},
2261	},
2262};
2263
2264static struct clk_branch gcc_qupv3_wrap2_ibi_ctrl_2_clk = {
2265	.halt_reg = 0x1e9ec,
2266	.halt_check = BRANCH_HALT_VOTED,
2267	.hwcg_reg = 0x1e9ec,
2268	.hwcg_bit = 1,
2269	.clkr = {
2270		.enable_reg = 0x52010,
2271		.enable_mask = BIT(27),
2272		.hw.init = &(const struct clk_init_data) {
2273			.name = "gcc_qupv3_wrap2_ibi_ctrl_2_clk",
2274			.parent_hws = (const struct clk_hw*[]) {
2275				&gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr.hw,
2276			},
2277			.num_parents = 1,
2278			.flags = CLK_SET_RATE_PARENT,
2279			.ops = &clk_branch2_ops,
2280		},
2281	},
2282};
2283
2284static struct clk_branch gcc_qupv3_wrap2_ibi_ctrl_3_clk = {
2285	.halt_reg = 0x1e9f0,
2286	.halt_check = BRANCH_HALT_VOTED,
2287	.hwcg_reg = 0x1e9f0,
2288	.hwcg_bit = 1,
2289	.clkr = {
2290		.enable_reg = 0x52010,
2291		.enable_mask = BIT(28),
2292		.hw.init = &(const struct clk_init_data) {
2293			.name = "gcc_qupv3_wrap2_ibi_ctrl_3_clk",
2294			.parent_hws = (const struct clk_hw*[]) {
2295				&gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr.hw,
2296			},
2297			.num_parents = 1,
2298			.flags = CLK_SET_RATE_PARENT,
2299			.ops = &clk_branch2_ops,
2300		},
2301	},
2302};
2303
2304static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2305	.halt_reg = 0x1e004,
2306	.halt_check = BRANCH_HALT_VOTED,
2307	.clkr = {
2308		.enable_reg = 0x52010,
2309		.enable_mask = BIT(4),
2310		.hw.init = &(const struct clk_init_data) {
2311			.name = "gcc_qupv3_wrap2_s0_clk",
2312			.parent_hws = (const struct clk_hw*[]) {
2313				&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
2314			},
2315			.num_parents = 1,
2316			.flags = CLK_SET_RATE_PARENT,
2317			.ops = &clk_branch2_ops,
2318		},
2319	},
2320};
2321
2322static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2323	.halt_reg = 0x1e140,
2324	.halt_check = BRANCH_HALT_VOTED,
2325	.clkr = {
2326		.enable_reg = 0x52010,
2327		.enable_mask = BIT(5),
2328		.hw.init = &(const struct clk_init_data) {
2329			.name = "gcc_qupv3_wrap2_s1_clk",
2330			.parent_hws = (const struct clk_hw*[]) {
2331				&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
2332			},
2333			.num_parents = 1,
2334			.flags = CLK_SET_RATE_PARENT,
2335			.ops = &clk_branch2_ops,
2336		},
2337	},
2338};
2339
2340static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2341	.halt_reg = 0x1e27c,
2342	.halt_check = BRANCH_HALT_VOTED,
2343	.clkr = {
2344		.enable_reg = 0x52010,
2345		.enable_mask = BIT(6),
2346		.hw.init = &(const struct clk_init_data) {
2347			.name = "gcc_qupv3_wrap2_s2_clk",
2348			.parent_hws = (const struct clk_hw*[]) {
2349				&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2350			},
2351			.num_parents = 1,
2352			.flags = CLK_SET_RATE_PARENT,
2353			.ops = &clk_branch2_ops,
2354		},
2355	},
2356};
2357
2358static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2359	.halt_reg = 0x1e3b8,
2360	.halt_check = BRANCH_HALT_VOTED,
2361	.clkr = {
2362		.enable_reg = 0x52010,
2363		.enable_mask = BIT(7),
2364		.hw.init = &(const struct clk_init_data) {
2365			.name = "gcc_qupv3_wrap2_s3_clk",
2366			.parent_hws = (const struct clk_hw*[]) {
2367				&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2368			},
2369			.num_parents = 1,
2370			.flags = CLK_SET_RATE_PARENT,
2371			.ops = &clk_branch2_ops,
2372		},
2373	},
2374};
2375
2376static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2377	.halt_reg = 0x1e4f4,
2378	.halt_check = BRANCH_HALT_VOTED,
2379	.clkr = {
2380		.enable_reg = 0x52010,
2381		.enable_mask = BIT(8),
2382		.hw.init = &(const struct clk_init_data) {
2383			.name = "gcc_qupv3_wrap2_s4_clk",
2384			.parent_hws = (const struct clk_hw*[]) {
2385				&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
2386			},
2387			.num_parents = 1,
2388			.flags = CLK_SET_RATE_PARENT,
2389			.ops = &clk_branch2_ops,
2390		},
2391	},
2392};
2393
2394static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2395	.halt_reg = 0x1e630,
2396	.halt_check = BRANCH_HALT_VOTED,
2397	.clkr = {
2398		.enable_reg = 0x52010,
2399		.enable_mask = BIT(9),
2400		.hw.init = &(const struct clk_init_data) {
2401			.name = "gcc_qupv3_wrap2_s5_clk",
2402			.parent_hws = (const struct clk_hw*[]) {
2403				&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
2404			},
2405			.num_parents = 1,
2406			.flags = CLK_SET_RATE_PARENT,
2407			.ops = &clk_branch2_ops,
2408		},
2409	},
2410};
2411
2412static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
2413	.halt_reg = 0x1e76c,
2414	.halt_check = BRANCH_HALT_VOTED,
2415	.clkr = {
2416		.enable_reg = 0x52010,
2417		.enable_mask = BIT(10),
2418		.hw.init = &(const struct clk_init_data) {
2419			.name = "gcc_qupv3_wrap2_s6_clk",
2420			.parent_hws = (const struct clk_hw*[]) {
2421				&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
2422			},
2423			.num_parents = 1,
2424			.flags = CLK_SET_RATE_PARENT,
2425			.ops = &clk_branch2_ops,
2426		},
2427	},
2428};
2429
2430static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
2431	.halt_reg = 0x1e8a8,
2432	.halt_check = BRANCH_HALT_VOTED,
2433	.clkr = {
2434		.enable_reg = 0x52010,
2435		.enable_mask = BIT(17),
2436		.hw.init = &(const struct clk_init_data) {
2437			.name = "gcc_qupv3_wrap2_s7_clk",
2438			.parent_hws = (const struct clk_hw*[]) {
2439				&gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
2440			},
2441			.num_parents = 1,
2442			.flags = CLK_SET_RATE_PARENT,
2443			.ops = &clk_branch2_ops,
2444		},
2445	},
2446};
2447
2448static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2449	.halt_reg = 0x23140,
2450	.halt_check = BRANCH_HALT_VOTED,
2451	.hwcg_reg = 0x23140,
2452	.hwcg_bit = 1,
2453	.clkr = {
2454		.enable_reg = 0x52008,
2455		.enable_mask = BIT(20),
2456		.hw.init = &(const struct clk_init_data) {
2457			.name = "gcc_qupv3_wrap_1_m_ahb_clk",
2458			.ops = &clk_branch2_ops,
2459		},
2460	},
2461};
2462
2463static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2464	.halt_reg = 0x23144,
2465	.halt_check = BRANCH_HALT_VOTED,
2466	.hwcg_reg = 0x23144,
2467	.hwcg_bit = 1,
2468	.clkr = {
2469		.enable_reg = 0x52008,
2470		.enable_mask = BIT(21),
2471		.hw.init = &(const struct clk_init_data) {
2472			.name = "gcc_qupv3_wrap_1_s_ahb_clk",
2473			.ops = &clk_branch2_ops,
2474		},
2475	},
2476};
2477
2478static struct clk_branch gcc_qupv3_wrap_2_ibi_2_ahb_clk = {
2479	.halt_reg = 0x1e9e4,
2480	.halt_check = BRANCH_HALT_VOTED,
2481	.hwcg_reg = 0x1e9e4,
2482	.hwcg_bit = 1,
2483	.clkr = {
2484		.enable_reg = 0x52010,
2485		.enable_mask = BIT(25),
2486		.hw.init = &(const struct clk_init_data) {
2487			.name = "gcc_qupv3_wrap_2_ibi_2_ahb_clk",
2488			.ops = &clk_branch2_ops,
2489		},
2490	},
2491};
2492
2493static struct clk_branch gcc_qupv3_wrap_2_ibi_3_ahb_clk = {
2494	.halt_reg = 0x1e9e8,
2495	.halt_check = BRANCH_HALT_VOTED,
2496	.hwcg_reg = 0x1e9e8,
2497	.hwcg_bit = 1,
2498	.clkr = {
2499		.enable_reg = 0x52010,
2500		.enable_mask = BIT(26),
2501		.hw.init = &(const struct clk_init_data) {
2502			.name = "gcc_qupv3_wrap_2_ibi_3_ahb_clk",
2503			.ops = &clk_branch2_ops,
2504		},
2505	},
2506};
2507
2508static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2509	.halt_reg = 0x23298,
2510	.halt_check = BRANCH_HALT_VOTED,
2511	.hwcg_reg = 0x23298,
2512	.hwcg_bit = 1,
2513	.clkr = {
2514		.enable_reg = 0x52010,
2515		.enable_mask = BIT(2),
2516		.hw.init = &(const struct clk_init_data) {
2517			.name = "gcc_qupv3_wrap_2_m_ahb_clk",
2518			.ops = &clk_branch2_ops,
2519		},
2520	},
2521};
2522
2523static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2524	.halt_reg = 0x2329c,
2525	.halt_check = BRANCH_HALT_VOTED,
2526	.hwcg_reg = 0x2329c,
2527	.hwcg_bit = 1,
2528	.clkr = {
2529		.enable_reg = 0x52010,
2530		.enable_mask = BIT(1),
2531		.hw.init = &(const struct clk_init_data) {
2532			.name = "gcc_qupv3_wrap_2_s_ahb_clk",
2533			.ops = &clk_branch2_ops,
2534		},
2535	},
2536};
2537
2538static struct clk_branch gcc_sdcc2_ahb_clk = {
2539	.halt_reg = 0x14014,
2540	.halt_check = BRANCH_HALT,
2541	.clkr = {
2542		.enable_reg = 0x14014,
2543		.enable_mask = BIT(0),
2544		.hw.init = &(const struct clk_init_data) {
2545			.name = "gcc_sdcc2_ahb_clk",
2546			.ops = &clk_branch2_ops,
2547		},
2548	},
2549};
2550
2551static struct clk_branch gcc_sdcc2_apps_clk = {
2552	.halt_reg = 0x14004,
2553	.halt_check = BRANCH_HALT,
2554	.clkr = {
2555		.enable_reg = 0x14004,
2556		.enable_mask = BIT(0),
2557		.hw.init = &(const struct clk_init_data) {
2558			.name = "gcc_sdcc2_apps_clk",
2559			.parent_hws = (const struct clk_hw*[]) {
2560				&gcc_sdcc2_apps_clk_src.clkr.hw,
2561			},
2562			.num_parents = 1,
2563			.flags = CLK_SET_RATE_PARENT,
2564			.ops = &clk_branch2_ops,
2565		},
2566	},
2567};
2568
2569static struct clk_branch gcc_sdcc4_ahb_clk = {
2570	.halt_reg = 0x16014,
2571	.halt_check = BRANCH_HALT,
2572	.clkr = {
2573		.enable_reg = 0x16014,
2574		.enable_mask = BIT(0),
2575		.hw.init = &(const struct clk_init_data) {
2576			.name = "gcc_sdcc4_ahb_clk",
2577			.ops = &clk_branch2_ops,
2578		},
2579	},
2580};
2581
2582static struct clk_branch gcc_sdcc4_apps_clk = {
2583	.halt_reg = 0x16004,
2584	.halt_check = BRANCH_HALT,
2585	.clkr = {
2586		.enable_reg = 0x16004,
2587		.enable_mask = BIT(0),
2588		.hw.init = &(const struct clk_init_data) {
2589			.name = "gcc_sdcc4_apps_clk",
2590			.parent_hws = (const struct clk_hw*[]) {
2591				&gcc_sdcc4_apps_clk_src.clkr.hw,
2592			},
2593			.num_parents = 1,
2594			.flags = CLK_SET_RATE_PARENT,
2595			.ops = &clk_branch2_ops,
2596		},
2597	},
2598};
2599
2600static struct clk_branch gcc_ufs_phy_ahb_clk = {
2601	.halt_reg = 0x77028,
2602	.halt_check = BRANCH_HALT_VOTED,
2603	.hwcg_reg = 0x77028,
2604	.hwcg_bit = 1,
2605	.clkr = {
2606		.enable_reg = 0x77028,
2607		.enable_mask = BIT(0),
2608		.hw.init = &(const struct clk_init_data) {
2609			.name = "gcc_ufs_phy_ahb_clk",
2610			.ops = &clk_branch2_ops,
2611		},
2612	},
2613};
2614
2615static struct clk_branch gcc_ufs_phy_axi_clk = {
2616	.halt_reg = 0x77018,
2617	.halt_check = BRANCH_HALT_VOTED,
2618	.hwcg_reg = 0x77018,
2619	.hwcg_bit = 1,
2620	.clkr = {
2621		.enable_reg = 0x77018,
2622		.enable_mask = BIT(0),
2623		.hw.init = &(const struct clk_init_data) {
2624			.name = "gcc_ufs_phy_axi_clk",
2625			.parent_hws = (const struct clk_hw*[]) {
2626				&gcc_ufs_phy_axi_clk_src.clkr.hw,
2627			},
2628			.num_parents = 1,
2629			.flags = CLK_SET_RATE_PARENT,
2630			.ops = &clk_branch2_ops,
2631		},
2632	},
2633};
2634
2635static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2636	.halt_reg = 0x7707c,
2637	.halt_check = BRANCH_HALT_VOTED,
2638	.hwcg_reg = 0x7707c,
2639	.hwcg_bit = 1,
2640	.clkr = {
2641		.enable_reg = 0x7707c,
2642		.enable_mask = BIT(0),
2643		.hw.init = &(const struct clk_init_data) {
2644			.name = "gcc_ufs_phy_ice_core_clk",
2645			.parent_hws = (const struct clk_hw*[]) {
2646				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2647			},
2648			.num_parents = 1,
2649			.flags = CLK_SET_RATE_PARENT,
2650			.ops = &clk_branch2_ops,
2651		},
2652	},
2653};
2654
2655static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2656	.halt_reg = 0x770bc,
2657	.halt_check = BRANCH_HALT_VOTED,
2658	.hwcg_reg = 0x770bc,
2659	.hwcg_bit = 1,
2660	.clkr = {
2661		.enable_reg = 0x770bc,
2662		.enable_mask = BIT(0),
2663		.hw.init = &(const struct clk_init_data) {
2664			.name = "gcc_ufs_phy_phy_aux_clk",
2665			.parent_hws = (const struct clk_hw*[]) {
2666				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2667			},
2668			.num_parents = 1,
2669			.flags = CLK_SET_RATE_PARENT,
2670			.ops = &clk_branch2_ops,
2671		},
2672	},
2673};
2674
2675static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2676	.halt_reg = 0x77030,
2677	.halt_check = BRANCH_HALT_DELAY,
2678	.clkr = {
2679		.enable_reg = 0x77030,
2680		.enable_mask = BIT(0),
2681		.hw.init = &(const struct clk_init_data) {
2682			.name = "gcc_ufs_phy_rx_symbol_0_clk",
2683			.parent_hws = (const struct clk_hw*[]) {
2684				&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
2685			},
2686			.num_parents = 1,
2687			.flags = CLK_SET_RATE_PARENT,
2688			.ops = &clk_branch2_ops,
2689		},
2690	},
2691};
2692
2693static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2694	.halt_reg = 0x770d8,
2695	.halt_check = BRANCH_HALT_DELAY,
2696	.clkr = {
2697		.enable_reg = 0x770d8,
2698		.enable_mask = BIT(0),
2699		.hw.init = &(const struct clk_init_data) {
2700			.name = "gcc_ufs_phy_rx_symbol_1_clk",
2701			.parent_hws = (const struct clk_hw*[]) {
2702				&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
2703			},
2704			.num_parents = 1,
2705			.flags = CLK_SET_RATE_PARENT,
2706			.ops = &clk_branch2_ops,
2707		},
2708	},
2709};
2710
2711static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2712	.halt_reg = 0x7702c,
2713	.halt_check = BRANCH_HALT_DELAY,
2714	.clkr = {
2715		.enable_reg = 0x7702c,
2716		.enable_mask = BIT(0),
2717		.hw.init = &(const struct clk_init_data) {
2718			.name = "gcc_ufs_phy_tx_symbol_0_clk",
2719			.parent_hws = (const struct clk_hw*[]) {
2720				&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
2721			},
2722			.num_parents = 1,
2723			.flags = CLK_SET_RATE_PARENT,
2724			.ops = &clk_branch2_ops,
2725		},
2726	},
2727};
2728
2729static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2730	.halt_reg = 0x7706c,
2731	.halt_check = BRANCH_HALT_VOTED,
2732	.hwcg_reg = 0x7706c,
2733	.hwcg_bit = 1,
2734	.clkr = {
2735		.enable_reg = 0x7706c,
2736		.enable_mask = BIT(0),
2737		.hw.init = &(const struct clk_init_data) {
2738			.name = "gcc_ufs_phy_unipro_core_clk",
2739			.parent_hws = (const struct clk_hw*[]) {
2740				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2741			},
2742			.num_parents = 1,
2743			.flags = CLK_SET_RATE_PARENT,
2744			.ops = &clk_branch2_ops,
2745		},
2746	},
2747};
2748
2749static struct clk_branch gcc_usb30_prim_master_clk = {
2750	.halt_reg = 0x39018,
2751	.halt_check = BRANCH_HALT,
2752	.clkr = {
2753		.enable_reg = 0x39018,
2754		.enable_mask = BIT(0),
2755		.hw.init = &(const struct clk_init_data) {
2756			.name = "gcc_usb30_prim_master_clk",
2757			.parent_hws = (const struct clk_hw*[]) {
2758				&gcc_usb30_prim_master_clk_src.clkr.hw,
2759			},
2760			.num_parents = 1,
2761			.flags = CLK_SET_RATE_PARENT,
2762			.ops = &clk_branch2_ops,
2763		},
2764	},
2765};
2766
2767static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2768	.halt_reg = 0x3902c,
2769	.halt_check = BRANCH_HALT,
2770	.clkr = {
2771		.enable_reg = 0x3902c,
2772		.enable_mask = BIT(0),
2773		.hw.init = &(const struct clk_init_data) {
2774			.name = "gcc_usb30_prim_mock_utmi_clk",
2775			.parent_hws = (const struct clk_hw*[]) {
2776				&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2777			},
2778			.num_parents = 1,
2779			.flags = CLK_SET_RATE_PARENT,
2780			.ops = &clk_branch2_ops,
2781		},
2782	},
2783};
2784
2785static struct clk_branch gcc_usb30_prim_sleep_clk = {
2786	.halt_reg = 0x39028,
2787	.halt_check = BRANCH_HALT,
2788	.clkr = {
2789		.enable_reg = 0x39028,
2790		.enable_mask = BIT(0),
2791		.hw.init = &(const struct clk_init_data) {
2792			.name = "gcc_usb30_prim_sleep_clk",
2793			.ops = &clk_branch2_ops,
2794		},
2795	},
2796};
2797
2798static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2799	.halt_reg = 0x39064,
2800	.halt_check = BRANCH_HALT,
2801	.clkr = {
2802		.enable_reg = 0x39064,
2803		.enable_mask = BIT(0),
2804		.hw.init = &(const struct clk_init_data) {
2805			.name = "gcc_usb3_prim_phy_aux_clk",
2806			.parent_hws = (const struct clk_hw*[]) {
2807				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2808			},
2809			.num_parents = 1,
2810			.flags = CLK_SET_RATE_PARENT,
2811			.ops = &clk_branch2_ops,
2812		},
2813	},
2814};
2815
2816static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2817	.halt_reg = 0x39068,
2818	.halt_check = BRANCH_HALT,
2819	.clkr = {
2820		.enable_reg = 0x39068,
2821		.enable_mask = BIT(0),
2822		.hw.init = &(const struct clk_init_data) {
2823			.name = "gcc_usb3_prim_phy_com_aux_clk",
2824			.parent_hws = (const struct clk_hw*[]) {
2825				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2826			},
2827			.num_parents = 1,
2828			.flags = CLK_SET_RATE_PARENT,
2829			.ops = &clk_branch2_ops,
2830		},
2831	},
2832};
2833
2834static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2835	.halt_reg = 0x3906c,
2836	.halt_check = BRANCH_HALT_DELAY,
2837	.hwcg_reg = 0x3906c,
2838	.hwcg_bit = 1,
2839	.clkr = {
2840		.enable_reg = 0x3906c,
2841		.enable_mask = BIT(0),
2842		.hw.init = &(const struct clk_init_data) {
2843			.name = "gcc_usb3_prim_phy_pipe_clk",
2844			.parent_hws = (const struct clk_hw*[]) {
2845				&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
2846			},
2847			.num_parents = 1,
2848			.flags = CLK_SET_RATE_PARENT,
2849			.ops = &clk_branch2_ops,
2850		},
2851	},
2852};
2853
2854static struct clk_branch gcc_video_axi0_clk = {
2855	.halt_reg = 0x32018,
2856	.halt_check = BRANCH_HALT_SKIP,
2857	.hwcg_reg = 0x32018,
2858	.hwcg_bit = 1,
2859	.clkr = {
2860		.enable_reg = 0x32018,
2861		.enable_mask = BIT(0),
2862		.hw.init = &(const struct clk_init_data) {
2863			.name = "gcc_video_axi0_clk",
2864			.ops = &clk_branch2_ops,
2865		},
2866	},
2867};
2868
2869static struct clk_branch gcc_video_axi1_clk = {
2870	.halt_reg = 0x32028,
2871	.halt_check = BRANCH_HALT_SKIP,
2872	.hwcg_reg = 0x32028,
2873	.hwcg_bit = 1,
2874	.clkr = {
2875		.enable_reg = 0x32028,
2876		.enable_mask = BIT(0),
2877		.hw.init = &(const struct clk_init_data) {
2878			.name = "gcc_video_axi1_clk",
2879			.ops = &clk_branch2_ops,
2880		},
2881	},
2882};
2883
2884static struct gdsc gcc_pcie_0_gdsc = {
2885	.gdscr = 0x6b004,
2886	.en_rest_wait_val = 0x2,
2887	.en_few_wait_val = 0x2,
2888	.clk_dis_wait_val = 0xf,
2889	.collapse_ctrl = 0x5214c,
2890	.collapse_mask = BIT(0),
2891	.pd = {
2892		.name = "gcc_pcie_0_gdsc",
2893	},
2894	.pwrsts = PWRSTS_OFF_ON,
2895	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
2896};
2897
2898static struct gdsc gcc_pcie_0_phy_gdsc = {
2899	.gdscr = 0x6c000,
2900	.en_rest_wait_val = 0x2,
2901	.en_few_wait_val = 0x2,
2902	.clk_dis_wait_val = 0x2,
2903	.collapse_ctrl = 0x5214c,
2904	.collapse_mask = BIT(2),
2905	.pd = {
2906		.name = "gcc_pcie_0_phy_gdsc",
2907	},
2908	.pwrsts = PWRSTS_OFF_ON,
2909	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
2910};
2911
2912static struct gdsc gcc_ufs_mem_phy_gdsc = {
2913	.gdscr = 0x9e000,
2914	.en_rest_wait_val = 0x2,
2915	.en_few_wait_val = 0x2,
2916	.clk_dis_wait_val = 0x2,
2917	.pd = {
2918		.name = "gcc_ufs_mem_phy_gdsc",
2919	},
2920	.pwrsts = PWRSTS_OFF_ON,
2921	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2922};
2923
2924static struct gdsc gcc_ufs_phy_gdsc = {
2925	.gdscr = 0x77004,
2926	.en_rest_wait_val = 0x2,
2927	.en_few_wait_val = 0x2,
2928	.clk_dis_wait_val = 0xf,
2929	.pd = {
2930		.name = "gcc_ufs_phy_gdsc",
2931	},
2932	.pwrsts = PWRSTS_OFF_ON,
2933	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2934};
2935
2936static struct gdsc gcc_usb30_prim_gdsc = {
2937	.gdscr = 0x39004,
2938	.en_rest_wait_val = 0x2,
2939	.en_few_wait_val = 0x2,
2940	.clk_dis_wait_val = 0xf,
2941	.pd = {
2942		.name = "gcc_usb30_prim_gdsc",
2943	},
2944	.pwrsts = PWRSTS_OFF_ON,
2945	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2946};
2947
2948static struct gdsc gcc_usb3_phy_gdsc = {
2949	.gdscr = 0x50018,
2950	.en_rest_wait_val = 0x2,
2951	.en_few_wait_val = 0x2,
2952	.clk_dis_wait_val = 0x2,
2953	.pd = {
2954		.name = "gcc_usb3_phy_gdsc",
2955	},
2956	.pwrsts = PWRSTS_OFF_ON,
2957	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2958};
2959
2960static struct clk_regmap *gcc_sm8750_clocks[] = {
2961	[GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr,
2962	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2963	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2964	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2965	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
2966	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
2967	[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
2968	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2969	[GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr,
2970	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2971	[GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr,
2972	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
2973	[GCC_EVA_AXI0_CLK] = &gcc_eva_axi0_clk.clkr,
2974	[GCC_EVA_AXI0C_CLK] = &gcc_eva_axi0c_clk.clkr,
2975	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2976	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2977	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2978	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2979	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2980	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2981	[GCC_GPLL0] = &gcc_gpll0.clkr,
2982	[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
2983	[GCC_GPLL1] = &gcc_gpll1.clkr,
2984	[GCC_GPLL4] = &gcc_gpll4.clkr,
2985	[GCC_GPLL7] = &gcc_gpll7.clkr,
2986	[GCC_GPLL9] = &gcc_gpll9.clkr,
2987	[GCC_GPU_GEMNOC_GFX_CLK] = &gcc_gpu_gemnoc_gfx_clk.clkr,
2988	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
2989	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
2990	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2991	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
2992	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2993	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2994	[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
2995	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
2996	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2997	[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
2998	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2999	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3000	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3001	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3002	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3003	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3004	[GCC_QMIP_CAMERA_CMD_AHB_CLK] = &gcc_qmip_camera_cmd_ahb_clk.clkr,
3005	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3006	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3007	[GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
3008	[GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
3009	[GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
3010	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3011	[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
3012	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3013	[GCC_QUPV3_I2C_CORE_CLK] = &gcc_qupv3_i2c_core_clk.clkr,
3014	[GCC_QUPV3_I2C_S0_CLK] = &gcc_qupv3_i2c_s0_clk.clkr,
3015	[GCC_QUPV3_I2C_S0_CLK_SRC] = &gcc_qupv3_i2c_s0_clk_src.clkr,
3016	[GCC_QUPV3_I2C_S1_CLK] = &gcc_qupv3_i2c_s1_clk.clkr,
3017	[GCC_QUPV3_I2C_S1_CLK_SRC] = &gcc_qupv3_i2c_s1_clk_src.clkr,
3018	[GCC_QUPV3_I2C_S2_CLK] = &gcc_qupv3_i2c_s2_clk.clkr,
3019	[GCC_QUPV3_I2C_S2_CLK_SRC] = &gcc_qupv3_i2c_s2_clk_src.clkr,
3020	[GCC_QUPV3_I2C_S3_CLK] = &gcc_qupv3_i2c_s3_clk.clkr,
3021	[GCC_QUPV3_I2C_S3_CLK_SRC] = &gcc_qupv3_i2c_s3_clk_src.clkr,
3022	[GCC_QUPV3_I2C_S4_CLK] = &gcc_qupv3_i2c_s4_clk.clkr,
3023	[GCC_QUPV3_I2C_S4_CLK_SRC] = &gcc_qupv3_i2c_s4_clk_src.clkr,
3024	[GCC_QUPV3_I2C_S5_CLK] = &gcc_qupv3_i2c_s5_clk.clkr,
3025	[GCC_QUPV3_I2C_S5_CLK_SRC] = &gcc_qupv3_i2c_s5_clk_src.clkr,
3026	[GCC_QUPV3_I2C_S6_CLK] = &gcc_qupv3_i2c_s6_clk.clkr,
3027	[GCC_QUPV3_I2C_S6_CLK_SRC] = &gcc_qupv3_i2c_s6_clk_src.clkr,
3028	[GCC_QUPV3_I2C_S7_CLK] = &gcc_qupv3_i2c_s7_clk.clkr,
3029	[GCC_QUPV3_I2C_S7_CLK_SRC] = &gcc_qupv3_i2c_s7_clk_src.clkr,
3030	[GCC_QUPV3_I2C_S8_CLK] = &gcc_qupv3_i2c_s8_clk.clkr,
3031	[GCC_QUPV3_I2C_S8_CLK_SRC] = &gcc_qupv3_i2c_s8_clk_src.clkr,
3032	[GCC_QUPV3_I2C_S9_CLK] = &gcc_qupv3_i2c_s9_clk.clkr,
3033	[GCC_QUPV3_I2C_S9_CLK_SRC] = &gcc_qupv3_i2c_s9_clk_src.clkr,
3034	[GCC_QUPV3_I2C_S_AHB_CLK] = &gcc_qupv3_i2c_s_ahb_clk.clkr,
3035	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3036	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3037	[GCC_QUPV3_WRAP1_QSPI_REF_CLK] = &gcc_qupv3_wrap1_qspi_ref_clk.clkr,
3038	[GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr,
3039	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3040	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3041	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3042	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3043	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3044	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3045	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3046	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3047	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3048	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3049	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3050	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3051	[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3052	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3053	[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3054	[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3055	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
3056	[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
3057	[GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC] = &gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr,
3058	[GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK] = &gcc_qupv3_wrap2_ibi_ctrl_2_clk.clkr,
3059	[GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK] = &gcc_qupv3_wrap2_ibi_ctrl_3_clk.clkr,
3060	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3061	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3062	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3063	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3064	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3065	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3066	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3067	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3068	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3069	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3070	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3071	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3072	[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
3073	[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
3074	[GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
3075	[GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
3076	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3077	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3078	[GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK] = &gcc_qupv3_wrap_2_ibi_2_ahb_clk.clkr,
3079	[GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK] = &gcc_qupv3_wrap_2_ibi_3_ahb_clk.clkr,
3080	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3081	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3082	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3083	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3084	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3085	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3086	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3087	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3088	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3089	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3090	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3091	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3092	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3093	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3094	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3095	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3096	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3097	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3098	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3099	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3100	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3101	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3102	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3103	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3104	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3105	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3106	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3107	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3108	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3109	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3110	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3111	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3112	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3113	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3114	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3115	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3116};
3117
3118static struct gdsc *gcc_sm8750_gdscs[] = {
3119	[GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc,
3120	[GCC_PCIE_0_PHY_GDSC] = &gcc_pcie_0_phy_gdsc,
3121	[GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc,
3122	[GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
3123	[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
3124	[GCC_USB3_PHY_GDSC] = &gcc_usb3_phy_gdsc,
3125};
3126
3127static const struct qcom_reset_map gcc_sm8750_resets[] = {
3128	[GCC_CAMERA_BCR] = { 0x26000 },
3129	[GCC_DISPLAY_BCR] = { 0x27000 },
3130	[GCC_EVA_BCR] = { 0x9f000 },
3131	[GCC_EVA_AXI0_CLK_ARES] = { 0x9f008, 2 },
3132	[GCC_EVA_AXI0C_CLK_ARES] = { 0x9f018, 2 },
3133	[GCC_GPU_BCR] = { 0x71000 },
3134	[GCC_PCIE_0_BCR] = { 0x6b000 },
3135	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3136	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3137	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3138	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3139	[GCC_PCIE_PHY_BCR] = { 0x6f000 },
3140	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3141	[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3142	[GCC_PCIE_RSCC_BCR] = { 0x11000 },
3143	[GCC_PDM_BCR] = { 0x33000 },
3144	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3145	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3146	[GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 },
3147	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3148	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3149	[GCC_SDCC2_BCR] = { 0x14000 },
3150	[GCC_SDCC4_BCR] = { 0x16000 },
3151	[GCC_UFS_PHY_BCR] = { 0x77000 },
3152	[GCC_USB30_PRIM_BCR] = { 0x39000 },
3153	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3154	[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3155	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3156	[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3157	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3158	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3159	[GCC_VIDEO_BCR] = { 0x32000 },
3160	[GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },
3161	[GCC_VIDEO_AXI1_CLK_ARES] = { 0x32028, 2 },
3162};
3163
3164
3165static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3166	DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src),
3167	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3168	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3169	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3170	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3171	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3172	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3173	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
3174	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
3175	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
3176	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
3177	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
3178	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
3179	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
3180	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
3181	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
3182};
3183
3184static const struct regmap_config gcc_sm8750_regmap_config = {
3185	.reg_bits = 32,
3186	.reg_stride = 4,
3187	.val_bits = 32,
3188	.max_register = 0x1f41f0,
3189	.fast_io = true,
3190};
3191
3192static const struct qcom_cc_desc gcc_sm8750_desc = {
3193	.config = &gcc_sm8750_regmap_config,
3194	.clks = gcc_sm8750_clocks,
3195	.num_clks = ARRAY_SIZE(gcc_sm8750_clocks),
3196	.resets = gcc_sm8750_resets,
3197	.num_resets = ARRAY_SIZE(gcc_sm8750_resets),
3198	.gdscs = gcc_sm8750_gdscs,
3199	.num_gdscs = ARRAY_SIZE(gcc_sm8750_gdscs),
3200};
3201
3202static const struct of_device_id gcc_sm8750_match_table[] = {
3203	{ .compatible = "qcom,sm8750-gcc" },
3204	{ }
3205};
3206MODULE_DEVICE_TABLE(of, gcc_sm8750_match_table);
3207
3208static int gcc_sm8750_probe(struct platform_device *pdev)
3209{
3210	struct regmap *regmap;
3211	int ret;
3212
3213	regmap = qcom_cc_map(pdev, &gcc_sm8750_desc);
3214	if (IS_ERR(regmap))
3215		return PTR_ERR(regmap);
3216
3217	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3218				       ARRAY_SIZE(gcc_dfs_clocks));
3219	if (ret)
3220		return ret;
3221
3222	/*
3223	 * Keep clocks always enabled:
3224	 *	gcc_cam_bist_mclk_ahb_clk
3225	 *	gcc_camera_ahb_clk
3226	 *	gcc_camera_xo_clk
3227	 *	gcc_disp_ahb_clk
3228	 *	gcc_eva_ahb_clk
3229	 *	gcc_eva_xo_clk
3230	 *	gcc_gpu_cfg_ahb_clk
3231	 *	gcc_video_ahb_clk
3232	 *	gcc_video_xo_clk
3233	 *	gcc_pcie_rscc_cfg_ahb_clk
3234	 *	gcc_pcie_rscc_xo_clk
3235	 */
3236	qcom_branch_set_clk_en(regmap, 0xa0004);
3237	qcom_branch_set_clk_en(regmap, 0x26004);
3238	qcom_branch_set_clk_en(regmap, 0x26034);
3239	qcom_branch_set_clk_en(regmap, 0x27004);
3240	qcom_branch_set_clk_en(regmap, 0x9f004);
3241	qcom_branch_set_clk_en(regmap, 0x9f01c);
3242	qcom_branch_set_clk_en(regmap, 0x71004);
3243	qcom_branch_set_clk_en(regmap, 0x32004);
3244	qcom_branch_set_clk_en(regmap, 0x32038);
3245	regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20));
3246	regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21));
3247
3248	/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks  */
3249	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
3250	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
3251
3252	return qcom_cc_really_probe(&pdev->dev, &gcc_sm8750_desc, regmap);
3253}
3254
3255static struct platform_driver gcc_sm8750_driver = {
3256	.probe = gcc_sm8750_probe,
3257	.driver = {
3258		.name = "gcc-sm8750",
3259		.of_match_table = gcc_sm8750_match_table,
3260	},
3261};
3262
3263static int __init gcc_sm8750_init(void)
3264{
3265	return platform_driver_register(&gcc_sm8750_driver);
3266}
3267subsys_initcall(gcc_sm8750_init);
3268
3269static void __exit gcc_sm8750_exit(void)
3270{
3271	platform_driver_unregister(&gcc_sm8750_driver);
3272}
3273module_exit(gcc_sm8750_exit);
3274
3275MODULE_DESCRIPTION("QTI GCC SM8750 Driver");
3276MODULE_LICENSE("GPL");