gcc-sm8650.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
   5 * Copyright (c) 2023, Linaro Limited
   6 */
   7
   8#include <linux/clk-provider.h>
   9#include <linux/mod_devicetable.h>
  10#include <linux/module.h>
  11#include <linux/platform_device.h>
  12#include <linux/regmap.h>
  13
  14#include <dt-bindings/clock/qcom,sm8650-gcc.h>
  15
  16#include "clk-alpha-pll.h"
  17#include "clk-branch.h"
  18#include "clk-rcg.h"
  19#include "clk-regmap.h"
  20#include "clk-regmap-divider.h"
  21#include "clk-regmap-mux.h"
  22#include "clk-regmap-phy-mux.h"
  23#include "gdsc.h"
  24#include "reset.h"
  25
  26/* Need to match the order of clocks in DT binding */
  27enum {
  28	DT_BI_TCXO,
  29	DT_BI_TCXO_AO,
  30	DT_SLEEP_CLK,
  31
  32	DT_PCIE_0_PIPE,
  33	DT_PCIE_1_PIPE,
  34	DT_PCIE_1_PHY_AUX,
  35
  36	DT_UFS_PHY_RX_SYMBOL_0,
  37	DT_UFS_PHY_RX_SYMBOL_1,
  38	DT_UFS_PHY_TX_SYMBOL_0,
  39
  40	DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE,
  41};
  42
  43enum {
  44	P_BI_TCXO,
  45	P_GCC_GPLL0_OUT_EVEN,
  46	P_GCC_GPLL0_OUT_MAIN,
  47	P_GCC_GPLL1_OUT_MAIN,
  48	P_GCC_GPLL3_OUT_MAIN,
  49	P_GCC_GPLL4_OUT_MAIN,
  50	P_GCC_GPLL6_OUT_MAIN,
  51	P_GCC_GPLL7_OUT_MAIN,
  52	P_GCC_GPLL9_OUT_MAIN,
  53	P_PCIE_0_PIPE_CLK,
  54	P_PCIE_1_PHY_AUX_CLK,
  55	P_PCIE_1_PIPE_CLK,
  56	P_SLEEP_CLK,
  57	P_UFS_PHY_RX_SYMBOL_0_CLK,
  58	P_UFS_PHY_RX_SYMBOL_1_CLK,
  59	P_UFS_PHY_TX_SYMBOL_0_CLK,
  60	P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
  61};
  62
  63static struct clk_alpha_pll gcc_gpll0 = {
  64	.offset = 0x0,
  65	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
  66	.clkr = {
  67		.enable_reg = 0x52020,
  68		.enable_mask = BIT(0),
  69		.hw.init = &(const struct clk_init_data) {
  70			.name = "gcc_gpll0",
  71			.parent_data = &(const struct clk_parent_data) {
  72				.index = DT_BI_TCXO,
  73			},
  74			.num_parents = 1,
  75			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
  76		},
  77	},
  78};
  79
  80static struct clk_alpha_pll gcc_gpll0_ao = {
  81	.offset = 0x0,
  82	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
  83	.clkr = {
  84		.enable_reg = 0x57020,
  85		.enable_mask = BIT(0),
  86		.hw.init = &(const struct clk_init_data) {
  87			.name = "gcc_gpll0_ao",
  88			.parent_data = &(const struct clk_parent_data) {
  89				.index = DT_BI_TCXO_AO,
  90			},
  91			.num_parents = 1,
  92			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
  93		},
  94	},
  95};
  96
  97static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
  98	{ 0x1, 2 },
  99	{ }
 100};
 101
 102static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
 103	.offset = 0x0,
 104	.post_div_shift = 10,
 105	.post_div_table = post_div_table_gcc_gpll0_out_even,
 106	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
 107	.width = 4,
 108	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 109	.clkr.hw.init = &(const struct clk_init_data) {
 110		.name = "gcc_gpll0_out_even",
 111		.parent_hws = (const struct clk_hw*[]) {
 112			&gcc_gpll0.clkr.hw,
 113		},
 114		.num_parents = 1,
 115		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 116	},
 117};
 118
 119static struct clk_alpha_pll_postdiv gcc_gpll0_out_even_ao = {
 120	.offset = 0x0,
 121	.post_div_shift = 10,
 122	.post_div_table = post_div_table_gcc_gpll0_out_even,
 123	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
 124	.width = 4,
 125	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 126	.clkr.hw.init = &(const struct clk_init_data) {
 127		.name = "gcc_gpll0_out_even_ao",
 128		.parent_hws = (const struct clk_hw*[]) {
 129			&gcc_gpll0_ao.clkr.hw,
 130		},
 131		.num_parents = 1,
 132		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 133	},
 134};
 135
 136static struct clk_alpha_pll gcc_gpll1 = {
 137	.offset = 0x4000,
 138	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 139	.clkr = {
 140		.enable_reg = 0x52020,
 141		.enable_mask = BIT(1),
 142		.hw.init = &(const struct clk_init_data) {
 143			.name = "gcc_gpll1",
 144			.parent_data = &(const struct clk_parent_data) {
 145				.index = DT_BI_TCXO,
 146			},
 147			.num_parents = 1,
 148			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 149		},
 150	},
 151};
 152
 153static struct clk_alpha_pll gcc_gpll1_ao = {
 154	.offset = 0x1000,
 155	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 156	.clkr = {
 157		.enable_reg = 0x57020,
 158		.enable_mask = BIT(1),
 159		.hw.init = &(const struct clk_init_data) {
 160			.name = "gcc_gpll1_ao",
 161			.parent_data = &(const struct clk_parent_data) {
 162				.index = DT_BI_TCXO_AO,
 163			},
 164			.num_parents = 1,
 165			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 166		},
 167	},
 168};
 169
 170static struct clk_alpha_pll gcc_gpll3 = {
 171	.offset = 0x3000,
 172	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 173	.clkr = {
 174		.enable_reg = 0x52020,
 175		.enable_mask = BIT(3),
 176		.hw.init = &(const struct clk_init_data) {
 177			.name = "gcc_gpll3",
 178			.parent_data = &(const struct clk_parent_data) {
 179				.index = DT_BI_TCXO,
 180			},
 181			.num_parents = 1,
 182			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 183		},
 184	},
 185};
 186
 187static struct clk_alpha_pll gcc_gpll3_ao = {
 188	.offset = 0x3000,
 189	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 190	.clkr = {
 191		.enable_reg = 0x57020,
 192		.enable_mask = BIT(3),
 193		.hw.init = &(const struct clk_init_data) {
 194			.name = "gcc_gpll3_ao",
 195			.parent_data = &(const struct clk_parent_data) {
 196				.index = DT_BI_TCXO_AO,
 197			},
 198			.num_parents = 1,
 199			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 200		},
 201	},
 202};
 203
 204static struct clk_alpha_pll gcc_gpll4 = {
 205	.offset = 0x4000,
 206	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 207	.clkr = {
 208		.enable_reg = 0x52020,
 209		.enable_mask = BIT(4),
 210		.hw.init = &(const struct clk_init_data) {
 211			.name = "gcc_gpll4",
 212			.parent_data = &(const struct clk_parent_data) {
 213				.index = DT_BI_TCXO,
 214			},
 215			.num_parents = 1,
 216			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 217		},
 218	},
 219};
 220
 221static struct clk_alpha_pll gcc_gpll4_ao = {
 222	.offset = 0x4000,
 223	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 224	.clkr = {
 225		.enable_reg = 0x57020,
 226		.enable_mask = BIT(4),
 227		.hw.init = &(const struct clk_init_data) {
 228			.name = "gcc_gpll4_ao",
 229			.parent_data = &(const struct clk_parent_data) {
 230				.index = DT_BI_TCXO_AO,
 231			},
 232			.num_parents = 1,
 233			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 234		},
 235	},
 236};
 237
 238static struct clk_alpha_pll gcc_gpll6 = {
 239	.offset = 0x6000,
 240	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 241	.clkr = {
 242		.enable_reg = 0x52020,
 243		.enable_mask = BIT(6),
 244		.hw.init = &(const struct clk_init_data) {
 245			.name = "gcc_gpll6",
 246			.parent_data = &(const struct clk_parent_data) {
 247				.index = DT_BI_TCXO,
 248			},
 249			.num_parents = 1,
 250			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 251		},
 252	},
 253};
 254
 255static struct clk_alpha_pll gcc_gpll6_ao = {
 256	.offset = 0x6000,
 257	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 258	.clkr = {
 259		.enable_reg = 0x57020,
 260		.enable_mask = BIT(6),
 261		.hw.init = &(const struct clk_init_data) {
 262			.name = "gcc_gpll6_ao",
 263			.parent_data = &(const struct clk_parent_data) {
 264				.index = DT_BI_TCXO_AO,
 265			},
 266			.num_parents = 1,
 267			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 268		},
 269	},
 270};
 271
 272static struct clk_alpha_pll gcc_gpll7 = {
 273	.offset = 0x7000,
 274	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 275	.clkr = {
 276		.enable_reg = 0x52020,
 277		.enable_mask = BIT(7),
 278		.hw.init = &(const struct clk_init_data) {
 279			.name = "gcc_gpll7",
 280			.parent_data = &(const struct clk_parent_data) {
 281				.index = DT_BI_TCXO,
 282			},
 283			.num_parents = 1,
 284			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 285		},
 286	},
 287};
 288
 289static struct clk_alpha_pll gcc_gpll9 = {
 290	.offset = 0x9000,
 291	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 292	.clkr = {
 293		.enable_reg = 0x52020,
 294		.enable_mask = BIT(9),
 295		.hw.init = &(const struct clk_init_data) {
 296			.name = "gcc_gpll9",
 297			.parent_data = &(const struct clk_parent_data) {
 298				.index = DT_BI_TCXO,
 299			},
 300			.num_parents = 1,
 301			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 302		},
 303	},
 304};
 305
 306static const struct parent_map gcc_parent_map_0[] = {
 307	{ P_BI_TCXO, 0 },
 308	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 309	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 310};
 311
 312static const struct clk_parent_data gcc_parent_data_0[] = {
 313	{ .index = DT_BI_TCXO },
 314	{ .hw = &gcc_gpll0.clkr.hw },
 315	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 316};
 317
 318static const struct parent_map gcc_parent_map_1[] = {
 319	{ P_BI_TCXO, 0 },
 320	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 321	{ P_SLEEP_CLK, 5 },
 322	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 323};
 324
 325static const struct clk_parent_data gcc_parent_data_1[] = {
 326	{ .index = DT_BI_TCXO },
 327	{ .hw = &gcc_gpll0.clkr.hw },
 328	{ .index = DT_SLEEP_CLK },
 329	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 330};
 331
 332static const struct parent_map gcc_parent_map_2[] = {
 333	{ P_BI_TCXO, 0 },
 334	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 335	{ P_GCC_GPLL1_OUT_MAIN, 4 },
 336	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 337	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 338};
 339
 340static const struct clk_parent_data gcc_parent_data_2[] = {
 341	{ .index = DT_BI_TCXO },
 342	{ .hw = &gcc_gpll0.clkr.hw },
 343	{ .hw = &gcc_gpll1.clkr.hw },
 344	{ .hw = &gcc_gpll4.clkr.hw },
 345	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 346};
 347
 348static const struct parent_map gcc_parent_map_3[] = {
 349	{ P_BI_TCXO, 0 },
 350	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 351	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 352	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 353};
 354
 355static const struct clk_parent_data gcc_parent_data_3[] = {
 356	{ .index = DT_BI_TCXO },
 357	{ .hw = &gcc_gpll0.clkr.hw },
 358	{ .hw = &gcc_gpll4.clkr.hw },
 359	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 360};
 361
 362static const struct parent_map gcc_parent_map_4[] = {
 363	{ P_BI_TCXO, 0 },
 364	{ P_SLEEP_CLK, 5 },
 365};
 366
 367static const struct clk_parent_data gcc_parent_data_4[] = {
 368	{ .index = DT_BI_TCXO },
 369	{ .index = DT_SLEEP_CLK },
 370};
 371
 372static const struct parent_map gcc_parent_map_5[] = {
 373	{ P_BI_TCXO, 0 },
 374};
 375
 376static const struct clk_parent_data gcc_parent_data_5[] = {
 377	{ .index = DT_BI_TCXO },
 378};
 379
 380static const struct parent_map gcc_parent_map_8[] = {
 381	{ P_PCIE_1_PHY_AUX_CLK, 0 },
 382	{ P_BI_TCXO, 2 },
 383};
 384
 385static const struct clk_parent_data gcc_parent_data_8[] = {
 386	{ .index = DT_PCIE_1_PHY_AUX },
 387	{ .index = DT_BI_TCXO },
 388};
 389
 390static const struct parent_map gcc_parent_map_10[] = {
 391	{ P_BI_TCXO, 0 },
 392	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 393	{ P_GCC_GPLL7_OUT_MAIN, 2 },
 394	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 395};
 396
 397static const struct clk_parent_data gcc_parent_data_10[] = {
 398	{ .index = DT_BI_TCXO },
 399	{ .hw = &gcc_gpll0.clkr.hw },
 400	{ .hw = &gcc_gpll7.clkr.hw },
 401	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 402};
 403
 404static const struct parent_map gcc_parent_map_11[] = {
 405	{ P_BI_TCXO, 0 },
 406	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 407	{ P_GCC_GPLL9_OUT_MAIN, 2 },
 408	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 409	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 410};
 411
 412static const struct clk_parent_data gcc_parent_data_11[] = {
 413	{ .index = DT_BI_TCXO },
 414	{ .hw = &gcc_gpll0.clkr.hw },
 415	{ .hw = &gcc_gpll9.clkr.hw },
 416	{ .hw = &gcc_gpll4.clkr.hw },
 417	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 418};
 419
 420static const struct parent_map gcc_parent_map_12[] = {
 421	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
 422	{ P_BI_TCXO, 2 },
 423};
 424
 425static const struct clk_parent_data gcc_parent_data_12[] = {
 426	{ .index = DT_UFS_PHY_RX_SYMBOL_0 },
 427	{ .index = DT_BI_TCXO },
 428};
 429
 430static const struct parent_map gcc_parent_map_13[] = {
 431	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
 432	{ P_BI_TCXO, 2 },
 433};
 434
 435static const struct clk_parent_data gcc_parent_data_13[] = {
 436	{ .index = DT_UFS_PHY_RX_SYMBOL_1 },
 437	{ .index = DT_BI_TCXO },
 438};
 439
 440static const struct parent_map gcc_parent_map_14[] = {
 441	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
 442	{ P_BI_TCXO, 2 },
 443};
 444
 445static const struct clk_parent_data gcc_parent_data_14[] = {
 446	{ .index = DT_UFS_PHY_TX_SYMBOL_0 },
 447	{ .index = DT_BI_TCXO },
 448};
 449
 450static const struct parent_map gcc_parent_map_15[] = {
 451	{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 452	{ P_BI_TCXO, 2 },
 453};
 454
 455static const struct clk_parent_data gcc_parent_data_15[] = {
 456	{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE },
 457	{ .index = DT_BI_TCXO },
 458};
 459
 460static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
 461	.reg = 0x6b070,
 462	.clkr = {
 463		.hw.init = &(const struct clk_init_data) {
 464			.name = "gcc_pcie_0_pipe_clk_src",
 465			.parent_data = &(const struct clk_parent_data){
 466				.index = DT_PCIE_0_PIPE,
 467			},
 468			.num_parents = 1,
 469			.ops = &clk_regmap_phy_mux_ops,
 470		},
 471	},
 472};
 473
 474static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
 475	.reg = 0x8d094,
 476	.shift = 0,
 477	.width = 2,
 478	.parent_map = gcc_parent_map_8,
 479	.clkr = {
 480		.hw.init = &(const struct clk_init_data) {
 481			.name = "gcc_pcie_1_phy_aux_clk_src",
 482			.parent_data = gcc_parent_data_8,
 483			.num_parents = ARRAY_SIZE(gcc_parent_data_8),
 484			.ops = &clk_regmap_mux_closest_ops,
 485		},
 486	},
 487};
 488
 489static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
 490	.reg = 0x8d078,
 491	.clkr = {
 492		.hw.init = &(const struct clk_init_data) {
 493			.name = "gcc_pcie_1_pipe_clk_src",
 494			.parent_data = &(const struct clk_parent_data){
 495				.index = DT_PCIE_1_PIPE,
 496			},
 497			.num_parents = 1,
 498			.ops = &clk_regmap_phy_mux_ops,
 499		},
 500	},
 501};
 502
 503static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
 504	.reg = 0x77064,
 505	.shift = 0,
 506	.width = 2,
 507	.parent_map = gcc_parent_map_12,
 508	.clkr = {
 509		.hw.init = &(const struct clk_init_data) {
 510			.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
 511			.parent_data = gcc_parent_data_12,
 512			.num_parents = ARRAY_SIZE(gcc_parent_data_12),
 513			.ops = &clk_regmap_mux_closest_ops,
 514		},
 515	},
 516};
 517
 518static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
 519	.reg = 0x770e0,
 520	.shift = 0,
 521	.width = 2,
 522	.parent_map = gcc_parent_map_13,
 523	.clkr = {
 524		.hw.init = &(const struct clk_init_data) {
 525			.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
 526			.parent_data = gcc_parent_data_13,
 527			.num_parents = ARRAY_SIZE(gcc_parent_data_13),
 528			.ops = &clk_regmap_mux_closest_ops,
 529		},
 530	},
 531};
 532
 533static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
 534	.reg = 0x77054,
 535	.shift = 0,
 536	.width = 2,
 537	.parent_map = gcc_parent_map_14,
 538	.clkr = {
 539		.hw.init = &(const struct clk_init_data) {
 540			.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
 541			.parent_data = gcc_parent_data_14,
 542			.num_parents = ARRAY_SIZE(gcc_parent_data_14),
 543			.ops = &clk_regmap_mux_closest_ops,
 544		},
 545	},
 546};
 547
 548static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
 549	.reg = 0x3906c,
 550	.shift = 0,
 551	.width = 2,
 552	.parent_map = gcc_parent_map_15,
 553	.clkr = {
 554		.hw.init = &(const struct clk_init_data) {
 555			.name = "gcc_usb3_prim_phy_pipe_clk_src",
 556			.parent_data = gcc_parent_data_15,
 557			.num_parents = ARRAY_SIZE(gcc_parent_data_15),
 558			.ops = &clk_regmap_mux_closest_ops,
 559		},
 560	},
 561};
 562
 563static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 564	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 565	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 566	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
 567	{ }
 568};
 569
 570static struct clk_rcg2 gcc_gp1_clk_src = {
 571	.cmd_rcgr = 0x64004,
 572	.mnd_width = 16,
 573	.hid_width = 5,
 574	.parent_map = gcc_parent_map_1,
 575	.freq_tbl = ftbl_gcc_gp1_clk_src,
 576	.clkr.hw.init = &(const struct clk_init_data) {
 577		.name = "gcc_gp1_clk_src",
 578		.parent_data = gcc_parent_data_1,
 579		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 580		.flags = CLK_SET_RATE_PARENT,
 581		.ops = &clk_rcg2_shared_ops,
 582	},
 583};
 584
 585static struct clk_rcg2 gcc_gp2_clk_src = {
 586	.cmd_rcgr = 0x65004,
 587	.mnd_width = 16,
 588	.hid_width = 5,
 589	.parent_map = gcc_parent_map_1,
 590	.freq_tbl = ftbl_gcc_gp1_clk_src,
 591	.clkr.hw.init = &(const struct clk_init_data) {
 592		.name = "gcc_gp2_clk_src",
 593		.parent_data = gcc_parent_data_1,
 594		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 595		.flags = CLK_SET_RATE_PARENT,
 596		.ops = &clk_rcg2_shared_ops,
 597	},
 598};
 599
 600static struct clk_rcg2 gcc_gp3_clk_src = {
 601	.cmd_rcgr = 0x66004,
 602	.mnd_width = 16,
 603	.hid_width = 5,
 604	.parent_map = gcc_parent_map_1,
 605	.freq_tbl = ftbl_gcc_gp1_clk_src,
 606	.clkr.hw.init = &(const struct clk_init_data) {
 607		.name = "gcc_gp3_clk_src",
 608		.parent_data = gcc_parent_data_1,
 609		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 610		.flags = CLK_SET_RATE_PARENT,
 611		.ops = &clk_rcg2_shared_ops,
 612	},
 613};
 614
 615static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 616	F(19200000, P_BI_TCXO, 1, 0, 0),
 617	{ }
 618};
 619
 620static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 621	.cmd_rcgr = 0x6b074,
 622	.mnd_width = 16,
 623	.hid_width = 5,
 624	.parent_map = gcc_parent_map_4,
 625	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 626	.clkr.hw.init = &(const struct clk_init_data) {
 627		.name = "gcc_pcie_0_aux_clk_src",
 628		.parent_data = gcc_parent_data_4,
 629		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
 630		.flags = CLK_SET_RATE_PARENT,
 631		.ops = &clk_rcg2_shared_ops,
 632	},
 633};
 634
 635static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
 636	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 637	{ }
 638};
 639
 640static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
 641	.cmd_rcgr = 0x6b058,
 642	.mnd_width = 0,
 643	.hid_width = 5,
 644	.parent_map = gcc_parent_map_0,
 645	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 646	.clkr.hw.init = &(const struct clk_init_data) {
 647		.name = "gcc_pcie_0_phy_rchng_clk_src",
 648		.parent_data = gcc_parent_data_0,
 649		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 650		.flags = CLK_SET_RATE_PARENT,
 651		.ops = &clk_rcg2_shared_ops,
 652	},
 653};
 654
 655static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 656	.cmd_rcgr = 0x8d07c,
 657	.mnd_width = 16,
 658	.hid_width = 5,
 659	.parent_map = gcc_parent_map_4,
 660	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 661	.clkr.hw.init = &(const struct clk_init_data) {
 662		.name = "gcc_pcie_1_aux_clk_src",
 663		.parent_data = gcc_parent_data_4,
 664		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
 665		.flags = CLK_SET_RATE_PARENT,
 666		.ops = &clk_rcg2_shared_ops,
 667	},
 668};
 669
 670static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
 671	.cmd_rcgr = 0x8d060,
 672	.mnd_width = 0,
 673	.hid_width = 5,
 674	.parent_map = gcc_parent_map_0,
 675	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 676	.clkr.hw.init = &(const struct clk_init_data) {
 677		.name = "gcc_pcie_1_phy_rchng_clk_src",
 678		.parent_data = gcc_parent_data_0,
 679		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 680		.flags = CLK_SET_RATE_PARENT,
 681		.ops = &clk_rcg2_shared_ops,
 682	},
 683};
 684
 685static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 686	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
 687	{ }
 688};
 689
 690static struct clk_rcg2 gcc_pdm2_clk_src = {
 691	.cmd_rcgr = 0x33010,
 692	.mnd_width = 0,
 693	.hid_width = 5,
 694	.parent_map = gcc_parent_map_0,
 695	.freq_tbl = ftbl_gcc_pdm2_clk_src,
 696	.clkr.hw.init = &(const struct clk_init_data) {
 697		.name = "gcc_pdm2_clk_src",
 698		.parent_data = gcc_parent_data_0,
 699		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 700		.flags = CLK_SET_RATE_PARENT,
 701		.ops = &clk_rcg2_shared_ops,
 702	},
 703};
 704
 705static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = {
 706	.cmd_rcgr = 0x17008,
 707	.mnd_width = 0,
 708	.hid_width = 5,
 709	.parent_map = gcc_parent_map_0,
 710	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 711	.clkr.hw.init = &(const struct clk_init_data) {
 712		.name = "gcc_qupv3_i2c_s0_clk_src",
 713		.parent_data = gcc_parent_data_0,
 714		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 715		.flags = CLK_SET_RATE_PARENT,
 716		.ops = &clk_rcg2_ops,
 717	},
 718};
 719
 720static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = {
 721	.cmd_rcgr = 0x17024,
 722	.mnd_width = 0,
 723	.hid_width = 5,
 724	.parent_map = gcc_parent_map_0,
 725	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 726	.clkr.hw.init = &(const struct clk_init_data) {
 727		.name = "gcc_qupv3_i2c_s1_clk_src",
 728		.parent_data = gcc_parent_data_0,
 729		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 730		.flags = CLK_SET_RATE_PARENT,
 731		.ops = &clk_rcg2_ops,
 732	},
 733};
 734
 735static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = {
 736	.cmd_rcgr = 0x17040,
 737	.mnd_width = 0,
 738	.hid_width = 5,
 739	.parent_map = gcc_parent_map_0,
 740	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 741	.clkr.hw.init = &(const struct clk_init_data) {
 742		.name = "gcc_qupv3_i2c_s2_clk_src",
 743		.parent_data = gcc_parent_data_0,
 744		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 745		.flags = CLK_SET_RATE_PARENT,
 746		.ops = &clk_rcg2_ops,
 747	},
 748};
 749
 750static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = {
 751	.cmd_rcgr = 0x1705c,
 752	.mnd_width = 0,
 753	.hid_width = 5,
 754	.parent_map = gcc_parent_map_0,
 755	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 756	.clkr.hw.init = &(const struct clk_init_data) {
 757		.name = "gcc_qupv3_i2c_s3_clk_src",
 758		.parent_data = gcc_parent_data_0,
 759		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 760		.flags = CLK_SET_RATE_PARENT,
 761		.ops = &clk_rcg2_ops,
 762	},
 763};
 764
 765static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = {
 766	.cmd_rcgr = 0x17078,
 767	.mnd_width = 0,
 768	.hid_width = 5,
 769	.parent_map = gcc_parent_map_0,
 770	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 771	.clkr.hw.init = &(const struct clk_init_data) {
 772		.name = "gcc_qupv3_i2c_s4_clk_src",
 773		.parent_data = gcc_parent_data_0,
 774		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 775		.flags = CLK_SET_RATE_PARENT,
 776		.ops = &clk_rcg2_ops,
 777	},
 778};
 779
 780static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = {
 781	.cmd_rcgr = 0x17094,
 782	.mnd_width = 0,
 783	.hid_width = 5,
 784	.parent_map = gcc_parent_map_0,
 785	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 786	.clkr.hw.init = &(const struct clk_init_data) {
 787		.name = "gcc_qupv3_i2c_s5_clk_src",
 788		.parent_data = gcc_parent_data_0,
 789		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 790		.flags = CLK_SET_RATE_PARENT,
 791		.ops = &clk_rcg2_ops,
 792	},
 793};
 794
 795static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = {
 796	.cmd_rcgr = 0x170b0,
 797	.mnd_width = 0,
 798	.hid_width = 5,
 799	.parent_map = gcc_parent_map_0,
 800	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 801	.clkr.hw.init = &(const struct clk_init_data) {
 802		.name = "gcc_qupv3_i2c_s6_clk_src",
 803		.parent_data = gcc_parent_data_0,
 804		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 805		.flags = CLK_SET_RATE_PARENT,
 806		.ops = &clk_rcg2_ops,
 807	},
 808};
 809
 810static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = {
 811	.cmd_rcgr = 0x170cc,
 812	.mnd_width = 0,
 813	.hid_width = 5,
 814	.parent_map = gcc_parent_map_0,
 815	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 816	.clkr.hw.init = &(const struct clk_init_data) {
 817		.name = "gcc_qupv3_i2c_s7_clk_src",
 818		.parent_data = gcc_parent_data_0,
 819		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 820		.flags = CLK_SET_RATE_PARENT,
 821		.ops = &clk_rcg2_ops,
 822	},
 823};
 824
 825static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = {
 826	.cmd_rcgr = 0x170e8,
 827	.mnd_width = 0,
 828	.hid_width = 5,
 829	.parent_map = gcc_parent_map_0,
 830	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 831	.clkr.hw.init = &(const struct clk_init_data) {
 832		.name = "gcc_qupv3_i2c_s8_clk_src",
 833		.parent_data = gcc_parent_data_0,
 834		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 835		.flags = CLK_SET_RATE_PARENT,
 836		.ops = &clk_rcg2_ops,
 837	},
 838};
 839
 840static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = {
 841	.cmd_rcgr = 0x17104,
 842	.mnd_width = 0,
 843	.hid_width = 5,
 844	.parent_map = gcc_parent_map_0,
 845	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 846	.clkr.hw.init = &(const struct clk_init_data) {
 847		.name = "gcc_qupv3_i2c_s9_clk_src",
 848		.parent_data = gcc_parent_data_0,
 849		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 850		.flags = CLK_SET_RATE_PARENT,
 851		.ops = &clk_rcg2_ops,
 852	},
 853};
 854
 855static const struct freq_tbl ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src[] = {
 856	F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
 857	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
 858	{ }
 859};
 860
 861static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = {
 862	.name = "gcc_qupv3_wrap1_qspi_ref_clk_src",
 863	.parent_data = gcc_parent_data_0,
 864	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 865	.flags = CLK_SET_RATE_PARENT,
 866	.ops = &clk_rcg2_ops,
 867};
 868
 869static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = {
 870	.cmd_rcgr = 0x188a0,
 871	.mnd_width = 16,
 872	.hid_width = 5,
 873	.parent_map = gcc_parent_map_0,
 874	.freq_tbl = ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src,
 875	.clkr.hw.init = &gcc_qupv3_wrap1_qspi_ref_clk_src_init,
 876};
 877
 878static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
 879	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 880	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 881	F(19200000, P_BI_TCXO, 1, 0, 0),
 882	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 883	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 884	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 885	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 886	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 887	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 888	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 889	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 890	F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
 891	F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
 892	F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
 893	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
 894	{ }
 895};
 896
 897static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 898	.name = "gcc_qupv3_wrap1_s0_clk_src",
 899	.parent_data = gcc_parent_data_0,
 900	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 901	.flags = CLK_SET_RATE_PARENT,
 902	.ops = &clk_rcg2_ops,
 903};
 904
 905static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 906	.cmd_rcgr = 0x18010,
 907	.mnd_width = 16,
 908	.hid_width = 5,
 909	.parent_map = gcc_parent_map_0,
 910	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 911	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 912};
 913
 914static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 915	.name = "gcc_qupv3_wrap1_s1_clk_src",
 916	.parent_data = gcc_parent_data_0,
 917	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 918	.flags = CLK_SET_RATE_PARENT,
 919	.ops = &clk_rcg2_ops,
 920};
 921
 922static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 923	.cmd_rcgr = 0x18148,
 924	.mnd_width = 16,
 925	.hid_width = 5,
 926	.parent_map = gcc_parent_map_0,
 927	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 928	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 929};
 930
 931static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s3_clk_src[] = {
 932	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 933	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 934	F(19200000, P_BI_TCXO, 1, 0, 0),
 935	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 936	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 937	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 938	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 939	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 940	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 941	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 942	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 943	{ }
 944};
 945
 946static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 947	.name = "gcc_qupv3_wrap1_s3_clk_src",
 948	.parent_data = gcc_parent_data_0,
 949	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 950	.flags = CLK_SET_RATE_PARENT,
 951	.ops = &clk_rcg2_ops,
 952};
 953
 954static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 955	.cmd_rcgr = 0x18290,
 956	.mnd_width = 16,
 957	.hid_width = 5,
 958	.parent_map = gcc_parent_map_0,
 959	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
 960	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 961};
 962
 963static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s4_clk_src[] = {
 964	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 965	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 966	F(19200000, P_BI_TCXO, 1, 0, 0),
 967	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 968	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 969	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 970	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 971	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 972	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 973	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 974	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
 975	{ }
 976};
 977
 978static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 979	.name = "gcc_qupv3_wrap1_s4_clk_src",
 980	.parent_data = gcc_parent_data_0,
 981	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 982	.flags = CLK_SET_RATE_PARENT,
 983	.ops = &clk_rcg2_ops,
 984};
 985
 986static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 987	.cmd_rcgr = 0x183c8,
 988	.mnd_width = 16,
 989	.hid_width = 5,
 990	.parent_map = gcc_parent_map_0,
 991	.freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src,
 992	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 993};
 994
 995static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 996	.name = "gcc_qupv3_wrap1_s5_clk_src",
 997	.parent_data = gcc_parent_data_0,
 998	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 999	.flags = CLK_SET_RATE_PARENT,
1000	.ops = &clk_rcg2_ops,
1001};
1002
1003static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
1004	.cmd_rcgr = 0x18500,
1005	.mnd_width = 16,
1006	.hid_width = 5,
1007	.parent_map = gcc_parent_map_0,
1008	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
1009	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
1010};
1011
1012static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
1013	.name = "gcc_qupv3_wrap1_s6_clk_src",
1014	.parent_data = gcc_parent_data_0,
1015	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1016	.flags = CLK_SET_RATE_PARENT,
1017	.ops = &clk_rcg2_ops,
1018};
1019
1020static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
1021	.cmd_rcgr = 0x18638,
1022	.mnd_width = 16,
1023	.hid_width = 5,
1024	.parent_map = gcc_parent_map_0,
1025	.freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src,
1026	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
1027};
1028
1029static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
1030	.name = "gcc_qupv3_wrap1_s7_clk_src",
1031	.parent_data = gcc_parent_data_0,
1032	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1033	.flags = CLK_SET_RATE_PARENT,
1034	.ops = &clk_rcg2_ops,
1035};
1036
1037static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
1038	.cmd_rcgr = 0x18770,
1039	.mnd_width = 16,
1040	.hid_width = 5,
1041	.parent_map = gcc_parent_map_0,
1042	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
1043	.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
1044};
1045
1046static const struct freq_tbl ftbl_gcc_qupv3_wrap2_ibi_ctrl_0_clk_src[] = {
1047	F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
1048	{ }
1049};
1050
1051static struct clk_rcg2 gcc_qupv3_wrap2_ibi_ctrl_0_clk_src = {
1052	.cmd_rcgr = 0x1e9d4,
1053	.mnd_width = 0,
1054	.hid_width = 5,
1055	.parent_map = gcc_parent_map_2,
1056	.freq_tbl = ftbl_gcc_qupv3_wrap2_ibi_ctrl_0_clk_src,
1057	.clkr.hw.init = &(const struct clk_init_data) {
1058		.name = "gcc_qupv3_wrap2_ibi_ctrl_0_clk_src",
1059		.parent_data = gcc_parent_data_2,
1060		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1061		.flags = CLK_SET_RATE_PARENT,
1062		.ops = &clk_rcg2_ops,
1063	},
1064};
1065
1066static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
1067	.name = "gcc_qupv3_wrap2_s0_clk_src",
1068	.parent_data = gcc_parent_data_0,
1069	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1070	.flags = CLK_SET_RATE_PARENT,
1071	.ops = &clk_rcg2_ops,
1072};
1073
1074static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
1075	.cmd_rcgr = 0x1e010,
1076	.mnd_width = 16,
1077	.hid_width = 5,
1078	.parent_map = gcc_parent_map_0,
1079	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
1080	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
1081};
1082
1083static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
1084	.name = "gcc_qupv3_wrap2_s1_clk_src",
1085	.parent_data = gcc_parent_data_0,
1086	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1087	.flags = CLK_SET_RATE_PARENT,
1088	.ops = &clk_rcg2_ops,
1089};
1090
1091static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
1092	.cmd_rcgr = 0x1e148,
1093	.mnd_width = 16,
1094	.hid_width = 5,
1095	.parent_map = gcc_parent_map_0,
1096	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
1097	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
1098};
1099
1100static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
1101	.name = "gcc_qupv3_wrap2_s2_clk_src",
1102	.parent_data = gcc_parent_data_0,
1103	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1104	.flags = CLK_SET_RATE_PARENT,
1105	.ops = &clk_rcg2_ops,
1106};
1107
1108static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
1109	.cmd_rcgr = 0x1e280,
1110	.mnd_width = 16,
1111	.hid_width = 5,
1112	.parent_map = gcc_parent_map_0,
1113	.freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src,
1114	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
1115};
1116
1117static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
1118	.name = "gcc_qupv3_wrap2_s3_clk_src",
1119	.parent_data = gcc_parent_data_0,
1120	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1121	.flags = CLK_SET_RATE_PARENT,
1122	.ops = &clk_rcg2_ops,
1123};
1124
1125static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
1126	.cmd_rcgr = 0x1e3b8,
1127	.mnd_width = 16,
1128	.hid_width = 5,
1129	.parent_map = gcc_parent_map_0,
1130	.freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src,
1131	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
1132};
1133
1134static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
1135	.name = "gcc_qupv3_wrap2_s4_clk_src",
1136	.parent_data = gcc_parent_data_0,
1137	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1138	.flags = CLK_SET_RATE_PARENT,
1139	.ops = &clk_rcg2_ops,
1140};
1141
1142static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
1143	.cmd_rcgr = 0x1e4f0,
1144	.mnd_width = 16,
1145	.hid_width = 5,
1146	.parent_map = gcc_parent_map_0,
1147	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
1148	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
1149};
1150
1151static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
1152	.name = "gcc_qupv3_wrap2_s5_clk_src",
1153	.parent_data = gcc_parent_data_0,
1154	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1155	.flags = CLK_SET_RATE_PARENT,
1156	.ops = &clk_rcg2_ops,
1157};
1158
1159static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
1160	.cmd_rcgr = 0x1e628,
1161	.mnd_width = 16,
1162	.hid_width = 5,
1163	.parent_map = gcc_parent_map_0,
1164	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
1165	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
1166};
1167
1168static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s6_clk_src[] = {
1169	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1170	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1171	F(19200000, P_BI_TCXO, 1, 0, 0),
1172	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1173	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1174	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1175	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1176	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1177	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1178	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1179	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1180	F(128000000, P_GCC_GPLL0_OUT_MAIN, 1, 16, 75),
1181	{ }
1182};
1183
1184static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
1185	.name = "gcc_qupv3_wrap2_s6_clk_src",
1186	.parent_data = gcc_parent_data_10,
1187	.num_parents = ARRAY_SIZE(gcc_parent_data_10),
1188	.flags = CLK_SET_RATE_PARENT,
1189	.ops = &clk_rcg2_ops,
1190};
1191
1192static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
1193	.cmd_rcgr = 0x1e760,
1194	.mnd_width = 16,
1195	.hid_width = 5,
1196	.parent_map = gcc_parent_map_10,
1197	.freq_tbl = ftbl_gcc_qupv3_wrap2_s6_clk_src,
1198	.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
1199};
1200
1201static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
1202	.name = "gcc_qupv3_wrap2_s7_clk_src",
1203	.parent_data = gcc_parent_data_0,
1204	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1205	.flags = CLK_SET_RATE_PARENT,
1206	.ops = &clk_rcg2_ops,
1207};
1208
1209static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
1210	.cmd_rcgr = 0x1e898,
1211	.mnd_width = 16,
1212	.hid_width = 5,
1213	.parent_map = gcc_parent_map_0,
1214	.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
1215	.clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
1216};
1217
1218static const struct freq_tbl ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src[] = {
1219	F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1220	F(400000000, P_GCC_GPLL0_OUT_MAIN, 1.5, 0, 0),
1221	{ }
1222};
1223
1224static struct clk_init_data gcc_qupv3_wrap3_qspi_ref_clk_src_init = {
1225	.name = "gcc_qupv3_wrap3_qspi_ref_clk_src",
1226	.parent_data = gcc_parent_data_0,
1227	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1228	.flags = CLK_SET_RATE_PARENT,
1229	.ops = &clk_rcg2_ops,
1230};
1231
1232static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src = {
1233	.cmd_rcgr = 0x19018,
1234	.mnd_width = 16,
1235	.hid_width = 5,
1236	.parent_map = gcc_parent_map_0,
1237	.freq_tbl = ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src,
1238	.clkr.hw.init = &gcc_qupv3_wrap3_qspi_ref_clk_src_init,
1239};
1240
1241static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1242	F(400000, P_BI_TCXO, 12, 1, 4),
1243	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1244	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1245	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1246	{ }
1247};
1248
1249static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1250	.cmd_rcgr = 0x14018,
1251	.mnd_width = 8,
1252	.hid_width = 5,
1253	.parent_map = gcc_parent_map_11,
1254	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1255	.clkr.hw.init = &(const struct clk_init_data) {
1256		.name = "gcc_sdcc2_apps_clk_src",
1257		.parent_data = gcc_parent_data_11,
1258		.num_parents = ARRAY_SIZE(gcc_parent_data_11),
1259		.flags = CLK_SET_RATE_PARENT,
1260		.ops = &clk_rcg2_shared_floor_ops,
1261	},
1262};
1263
1264static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
1265	F(400000, P_BI_TCXO, 12, 1, 4),
1266	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1267	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1268	{ }
1269};
1270
1271static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
1272	.cmd_rcgr = 0x16018,
1273	.mnd_width = 8,
1274	.hid_width = 5,
1275	.parent_map = gcc_parent_map_0,
1276	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
1277	.clkr.hw.init = &(const struct clk_init_data) {
1278		.name = "gcc_sdcc4_apps_clk_src",
1279		.parent_data = gcc_parent_data_0,
1280		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1281		.flags = CLK_SET_RATE_PARENT,
1282		.ops = &clk_rcg2_shared_floor_ops,
1283	},
1284};
1285
1286static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1287	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1288	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1289	F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1290	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1291	{ }
1292};
1293
1294static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1295	.cmd_rcgr = 0x77030,
1296	.mnd_width = 8,
1297	.hid_width = 5,
1298	.parent_map = gcc_parent_map_3,
1299	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1300	.clkr.hw.init = &(const struct clk_init_data) {
1301		.name = "gcc_ufs_phy_axi_clk_src",
1302		.parent_data = gcc_parent_data_3,
1303		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1304		.flags = CLK_SET_RATE_PARENT,
1305		.ops = &clk_rcg2_shared_ops,
1306	},
1307};
1308
1309static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1310	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1311	F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1312	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1313	{ }
1314};
1315
1316static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1317	.cmd_rcgr = 0x77080,
1318	.mnd_width = 0,
1319	.hid_width = 5,
1320	.parent_map = gcc_parent_map_3,
1321	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1322	.clkr.hw.init = &(const struct clk_init_data) {
1323		.name = "gcc_ufs_phy_ice_core_clk_src",
1324		.parent_data = gcc_parent_data_3,
1325		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1326		.flags = CLK_SET_RATE_PARENT,
1327		.ops = &clk_rcg2_shared_ops,
1328	},
1329};
1330
1331static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
1332	F(9600000, P_BI_TCXO, 2, 0, 0),
1333	F(19200000, P_BI_TCXO, 1, 0, 0),
1334	{ }
1335};
1336
1337static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1338	.cmd_rcgr = 0x770b4,
1339	.mnd_width = 0,
1340	.hid_width = 5,
1341	.parent_map = gcc_parent_map_5,
1342	.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
1343	.clkr.hw.init = &(const struct clk_init_data) {
1344		.name = "gcc_ufs_phy_phy_aux_clk_src",
1345		.parent_data = gcc_parent_data_5,
1346		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
1347		.flags = CLK_SET_RATE_PARENT,
1348		.ops = &clk_rcg2_shared_ops,
1349	},
1350};
1351
1352static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1353	.cmd_rcgr = 0x77098,
1354	.mnd_width = 0,
1355	.hid_width = 5,
1356	.parent_map = gcc_parent_map_3,
1357	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1358	.clkr.hw.init = &(const struct clk_init_data) {
1359		.name = "gcc_ufs_phy_unipro_core_clk_src",
1360		.parent_data = gcc_parent_data_3,
1361		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1362		.flags = CLK_SET_RATE_PARENT,
1363		.ops = &clk_rcg2_shared_ops,
1364	},
1365};
1366
1367static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1368	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1369	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1370	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1371	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1372	{ }
1373};
1374
1375static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1376	.cmd_rcgr = 0x3902c,
1377	.mnd_width = 8,
1378	.hid_width = 5,
1379	.parent_map = gcc_parent_map_0,
1380	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1381	.clkr.hw.init = &(const struct clk_init_data) {
1382		.name = "gcc_usb30_prim_master_clk_src",
1383		.parent_data = gcc_parent_data_0,
1384		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1385		.flags = CLK_SET_RATE_PARENT,
1386		.ops = &clk_rcg2_shared_ops,
1387	},
1388};
1389
1390static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1391	.cmd_rcgr = 0x39044,
1392	.mnd_width = 0,
1393	.hid_width = 5,
1394	.parent_map = gcc_parent_map_0,
1395	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1396	.clkr.hw.init = &(const struct clk_init_data) {
1397		.name = "gcc_usb30_prim_mock_utmi_clk_src",
1398		.parent_data = gcc_parent_data_0,
1399		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1400		.flags = CLK_SET_RATE_PARENT,
1401		.ops = &clk_rcg2_shared_ops,
1402	},
1403};
1404
1405static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1406	.cmd_rcgr = 0x39070,
1407	.mnd_width = 0,
1408	.hid_width = 5,
1409	.parent_map = gcc_parent_map_4,
1410	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1411	.clkr.hw.init = &(const struct clk_init_data) {
1412		.name = "gcc_usb3_prim_phy_aux_clk_src",
1413		.parent_data = gcc_parent_data_4,
1414		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
1415		.flags = CLK_SET_RATE_PARENT,
1416		.ops = &clk_rcg2_shared_ops,
1417	},
1418};
1419
1420static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = {
1421	.reg = 0x18280,
1422	.shift = 0,
1423	.width = 4,
1424	.clkr.hw.init = &(const struct clk_init_data) {
1425		.name = "gcc_qupv3_wrap1_s2_clk_src",
1426		.parent_hws = (const struct clk_hw*[]) {
1427			&gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw,
1428		},
1429		.num_parents = 1,
1430		.flags = CLK_SET_RATE_PARENT,
1431		.ops = &clk_regmap_div_ro_ops,
1432	},
1433};
1434
1435static struct clk_regmap_div gcc_qupv3_wrap3_s0_clk_src = {
1436	.reg = 0x19010,
1437	.shift = 0,
1438	.width = 4,
1439	.clkr.hw.init = &(const struct clk_init_data) {
1440		.name = "gcc_qupv3_wrap3_s0_clk_src",
1441		.parent_hws = (const struct clk_hw*[]) {
1442			&gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw,
1443		},
1444		.num_parents = 1,
1445		.flags = CLK_SET_RATE_PARENT,
1446		.ops = &clk_regmap_div_ro_ops,
1447	},
1448};
1449
1450static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1451	.reg = 0x3905c,
1452	.shift = 0,
1453	.width = 4,
1454	.clkr.hw.init = &(const struct clk_init_data) {
1455		.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1456		.parent_hws = (const struct clk_hw*[]) {
1457			&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1458		},
1459		.num_parents = 1,
1460		.flags = CLK_SET_RATE_PARENT,
1461		.ops = &clk_regmap_div_ro_ops,
1462	},
1463};
1464
1465static struct clk_branch gcc_aggre_noc_pcie_axi_clk = {
1466	.halt_reg = 0x10064,
1467	.halt_check = BRANCH_HALT_SKIP,
1468	.hwcg_reg = 0x10064,
1469	.hwcg_bit = 1,
1470	.clkr = {
1471		.enable_reg = 0x52000,
1472		.enable_mask = BIT(12),
1473		.hw.init = &(const struct clk_init_data) {
1474			.name = "gcc_aggre_noc_pcie_axi_clk",
1475			.ops = &clk_branch2_ops,
1476		},
1477	},
1478};
1479
1480static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1481	.halt_reg = 0x770e4,
1482	.halt_check = BRANCH_HALT_VOTED,
1483	.hwcg_reg = 0x770e4,
1484	.hwcg_bit = 1,
1485	.clkr = {
1486		.enable_reg = 0x770e4,
1487		.enable_mask = BIT(0),
1488		.hw.init = &(const struct clk_init_data) {
1489			.name = "gcc_aggre_ufs_phy_axi_clk",
1490			.parent_hws = (const struct clk_hw*[]) {
1491				&gcc_ufs_phy_axi_clk_src.clkr.hw,
1492			},
1493			.num_parents = 1,
1494			.flags = CLK_SET_RATE_PARENT,
1495			.ops = &clk_branch2_ops,
1496		},
1497	},
1498};
1499
1500static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1501	.halt_reg = 0x770e4,
1502	.halt_check = BRANCH_HALT_VOTED,
1503	.hwcg_reg = 0x770e4,
1504	.hwcg_bit = 1,
1505	.clkr = {
1506		.enable_reg = 0x770e4,
1507		.enable_mask = BIT(1),
1508		.hw.init = &(const struct clk_init_data) {
1509			.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1510			.parent_hws = (const struct clk_hw*[]) {
1511				&gcc_ufs_phy_axi_clk_src.clkr.hw,
1512			},
1513			.num_parents = 1,
1514			.flags = CLK_SET_RATE_PARENT,
1515			.ops = &clk_branch2_ops,
1516		},
1517	},
1518};
1519
1520static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1521	.halt_reg = 0x3908c,
1522	.halt_check = BRANCH_HALT_VOTED,
1523	.hwcg_reg = 0x3908c,
1524	.hwcg_bit = 1,
1525	.clkr = {
1526		.enable_reg = 0x3908c,
1527		.enable_mask = BIT(0),
1528		.hw.init = &(const struct clk_init_data) {
1529			.name = "gcc_aggre_usb3_prim_axi_clk",
1530			.parent_hws = (const struct clk_hw*[]) {
1531				&gcc_usb30_prim_master_clk_src.clkr.hw,
1532			},
1533			.num_parents = 1,
1534			.flags = CLK_SET_RATE_PARENT,
1535			.ops = &clk_branch2_ops,
1536		},
1537	},
1538};
1539
1540static struct clk_branch gcc_boot_rom_ahb_clk = {
1541	.halt_reg = 0x38004,
1542	.halt_check = BRANCH_HALT_VOTED,
1543	.hwcg_reg = 0x38004,
1544	.hwcg_bit = 1,
1545	.clkr = {
1546		.enable_reg = 0x52000,
1547		.enable_mask = BIT(10),
1548		.hw.init = &(const struct clk_init_data) {
1549			.name = "gcc_boot_rom_ahb_clk",
1550			.ops = &clk_branch2_ops,
1551		},
1552	},
1553};
1554
1555static struct clk_branch gcc_camera_hf_axi_clk = {
1556	.halt_reg = 0x26010,
1557	.halt_check = BRANCH_HALT_SKIP,
1558	.hwcg_reg = 0x26010,
1559	.hwcg_bit = 1,
1560	.clkr = {
1561		.enable_reg = 0x26010,
1562		.enable_mask = BIT(0),
1563		.hw.init = &(const struct clk_init_data) {
1564			.name = "gcc_camera_hf_axi_clk",
1565			.ops = &clk_branch2_ops,
1566		},
1567	},
1568};
1569
1570static struct clk_branch gcc_camera_sf_axi_clk = {
1571	.halt_reg = 0x2601c,
1572	.halt_check = BRANCH_HALT_SKIP,
1573	.hwcg_reg = 0x2601c,
1574	.hwcg_bit = 1,
1575	.clkr = {
1576		.enable_reg = 0x2601c,
1577		.enable_mask = BIT(0),
1578		.hw.init = &(const struct clk_init_data) {
1579			.name = "gcc_camera_sf_axi_clk",
1580			.ops = &clk_branch2_ops,
1581		},
1582	},
1583};
1584
1585static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
1586	.halt_reg = 0x10050,
1587	.halt_check = BRANCH_HALT_SKIP,
1588	.hwcg_reg = 0x10050,
1589	.hwcg_bit = 1,
1590	.clkr = {
1591		.enable_reg = 0x52000,
1592		.enable_mask = BIT(20),
1593		.hw.init = &(const struct clk_init_data) {
1594			.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
1595			.ops = &clk_branch2_ops,
1596		},
1597	},
1598};
1599
1600static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1601	.halt_reg = 0x39088,
1602	.halt_check = BRANCH_HALT_VOTED,
1603	.hwcg_reg = 0x39088,
1604	.hwcg_bit = 1,
1605	.clkr = {
1606		.enable_reg = 0x39088,
1607		.enable_mask = BIT(0),
1608		.hw.init = &(const struct clk_init_data) {
1609			.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1610			.parent_hws = (const struct clk_hw*[]) {
1611				&gcc_usb30_prim_master_clk_src.clkr.hw,
1612			},
1613			.num_parents = 1,
1614			.flags = CLK_SET_RATE_PARENT,
1615			.ops = &clk_branch2_ops,
1616		},
1617	},
1618};
1619
1620static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = {
1621	.halt_reg = 0x10058,
1622	.halt_check = BRANCH_HALT_VOTED,
1623	.hwcg_reg = 0x10058,
1624	.hwcg_bit = 1,
1625	.clkr = {
1626		.enable_reg = 0x52008,
1627		.enable_mask = BIT(6),
1628		.hw.init = &(const struct clk_init_data) {
1629			.name = "gcc_cnoc_pcie_sf_axi_clk",
1630			.ops = &clk_branch2_ops,
1631		},
1632	},
1633};
1634
1635static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1636	.halt_reg = 0x71154,
1637	.halt_check = BRANCH_HALT_SKIP,
1638	.hwcg_reg = 0x71154,
1639	.hwcg_bit = 1,
1640	.clkr = {
1641		.enable_reg = 0x71154,
1642		.enable_mask = BIT(0),
1643		.hw.init = &(const struct clk_init_data) {
1644			.name = "gcc_ddrss_gpu_axi_clk",
1645			.ops = &clk_branch2_aon_ops,
1646		},
1647	},
1648};
1649
1650static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = {
1651	.halt_reg = 0x10074,
1652	.halt_check = BRANCH_HALT_SKIP,
1653	.hwcg_reg = 0x10074,
1654	.hwcg_bit = 1,
1655	.clkr = {
1656		.enable_reg = 0x52000,
1657		.enable_mask = BIT(19),
1658		.hw.init = &(const struct clk_init_data) {
1659			.name = "gcc_ddrss_pcie_sf_qtb_clk",
1660			.ops = &clk_branch2_ops,
1661		},
1662	},
1663};
1664
1665static struct clk_branch gcc_disp_hf_axi_clk = {
1666	.halt_reg = 0x2700c,
1667	.halt_check = BRANCH_HALT_SKIP,
1668	.hwcg_reg = 0x2700c,
1669	.hwcg_bit = 1,
1670	.clkr = {
1671		.enable_reg = 0x2700c,
1672		.enable_mask = BIT(0),
1673		.hw.init = &(const struct clk_init_data) {
1674			.name = "gcc_disp_hf_axi_clk",
1675			.ops = &clk_branch2_ops,
1676		},
1677	},
1678};
1679
1680static struct clk_branch gcc_gp1_clk = {
1681	.halt_reg = 0x64000,
1682	.halt_check = BRANCH_HALT,
1683	.clkr = {
1684		.enable_reg = 0x64000,
1685		.enable_mask = BIT(0),
1686		.hw.init = &(const struct clk_init_data) {
1687			.name = "gcc_gp1_clk",
1688			.parent_hws = (const struct clk_hw*[]) {
1689				&gcc_gp1_clk_src.clkr.hw,
1690			},
1691			.num_parents = 1,
1692			.flags = CLK_SET_RATE_PARENT,
1693			.ops = &clk_branch2_ops,
1694		},
1695	},
1696};
1697
1698static struct clk_branch gcc_gp2_clk = {
1699	.halt_reg = 0x65000,
1700	.halt_check = BRANCH_HALT,
1701	.clkr = {
1702		.enable_reg = 0x65000,
1703		.enable_mask = BIT(0),
1704		.hw.init = &(const struct clk_init_data) {
1705			.name = "gcc_gp2_clk",
1706			.parent_hws = (const struct clk_hw*[]) {
1707				&gcc_gp2_clk_src.clkr.hw,
1708			},
1709			.num_parents = 1,
1710			.flags = CLK_SET_RATE_PARENT,
1711			.ops = &clk_branch2_ops,
1712		},
1713	},
1714};
1715
1716static struct clk_branch gcc_gp3_clk = {
1717	.halt_reg = 0x66000,
1718	.halt_check = BRANCH_HALT,
1719	.clkr = {
1720		.enable_reg = 0x66000,
1721		.enable_mask = BIT(0),
1722		.hw.init = &(const struct clk_init_data) {
1723			.name = "gcc_gp3_clk",
1724			.parent_hws = (const struct clk_hw*[]) {
1725				&gcc_gp3_clk_src.clkr.hw,
1726			},
1727			.num_parents = 1,
1728			.flags = CLK_SET_RATE_PARENT,
1729			.ops = &clk_branch2_ops,
1730		},
1731	},
1732};
1733
1734static struct clk_branch gcc_gpu_gpll0_clk_src = {
1735	.halt_check = BRANCH_HALT_DELAY,
1736	.clkr = {
1737		.enable_reg = 0x52000,
1738		.enable_mask = BIT(15),
1739		.hw.init = &(const struct clk_init_data) {
1740			.name = "gcc_gpu_gpll0_clk_src",
1741			.parent_hws = (const struct clk_hw*[]) {
1742				&gcc_gpll0.clkr.hw,
1743			},
1744			.num_parents = 1,
1745			.flags = CLK_SET_RATE_PARENT,
1746			.ops = &clk_branch2_ops,
1747		},
1748	},
1749};
1750
1751static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1752	.halt_check = BRANCH_HALT_DELAY,
1753	.clkr = {
1754		.enable_reg = 0x52000,
1755		.enable_mask = BIT(16),
1756		.hw.init = &(const struct clk_init_data) {
1757			.name = "gcc_gpu_gpll0_div_clk_src",
1758			.parent_hws = (const struct clk_hw*[]) {
1759				&gcc_gpll0_out_even.clkr.hw,
1760			},
1761			.num_parents = 1,
1762			.flags = CLK_SET_RATE_PARENT,
1763			.ops = &clk_branch2_ops,
1764		},
1765	},
1766};
1767
1768static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1769	.halt_reg = 0x71010,
1770	.halt_check = BRANCH_HALT_VOTED,
1771	.hwcg_reg = 0x71010,
1772	.hwcg_bit = 1,
1773	.clkr = {
1774		.enable_reg = 0x71010,
1775		.enable_mask = BIT(0),
1776		.hw.init = &(const struct clk_init_data) {
1777			.name = "gcc_gpu_memnoc_gfx_clk",
1778			.ops = &clk_branch2_ops,
1779		},
1780	},
1781};
1782
1783static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1784	.halt_reg = 0x71018,
1785	.halt_check = BRANCH_HALT_DELAY,
1786	.clkr = {
1787		.enable_reg = 0x71018,
1788		.enable_mask = BIT(0),
1789		.hw.init = &(const struct clk_init_data) {
1790			.name = "gcc_gpu_snoc_dvm_gfx_clk",
1791			.ops = &clk_branch2_ops,
1792		},
1793	},
1794};
1795
1796static struct clk_branch gcc_pcie_0_aux_clk = {
1797	.halt_reg = 0x6b03c,
1798	.halt_check = BRANCH_HALT_VOTED,
1799	.clkr = {
1800		.enable_reg = 0x52008,
1801		.enable_mask = BIT(3),
1802		.hw.init = &(const struct clk_init_data) {
1803			.name = "gcc_pcie_0_aux_clk",
1804			.parent_hws = (const struct clk_hw*[]) {
1805				&gcc_pcie_0_aux_clk_src.clkr.hw,
1806			},
1807			.num_parents = 1,
1808			.flags = CLK_SET_RATE_PARENT,
1809			.ops = &clk_branch2_ops,
1810		},
1811	},
1812};
1813
1814static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1815	.halt_reg = 0x6b038,
1816	.halt_check = BRANCH_HALT_VOTED,
1817	.hwcg_reg = 0x6b038,
1818	.hwcg_bit = 1,
1819	.clkr = {
1820		.enable_reg = 0x52008,
1821		.enable_mask = BIT(2),
1822		.hw.init = &(const struct clk_init_data) {
1823			.name = "gcc_pcie_0_cfg_ahb_clk",
1824			.ops = &clk_branch2_ops,
1825		},
1826	},
1827};
1828
1829static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1830	.halt_reg = 0x6b02c,
1831	.halt_check = BRANCH_HALT_SKIP,
1832	.hwcg_reg = 0x6b02c,
1833	.hwcg_bit = 1,
1834	.clkr = {
1835		.enable_reg = 0x52008,
1836		.enable_mask = BIT(1),
1837		.hw.init = &(const struct clk_init_data) {
1838			.name = "gcc_pcie_0_mstr_axi_clk",
1839			.ops = &clk_branch2_ops,
1840		},
1841	},
1842};
1843
1844static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
1845	.halt_reg = 0x6b054,
1846	.halt_check = BRANCH_HALT_VOTED,
1847	.clkr = {
1848		.enable_reg = 0x52000,
1849		.enable_mask = BIT(22),
1850		.hw.init = &(const struct clk_init_data) {
1851			.name = "gcc_pcie_0_phy_rchng_clk",
1852			.parent_hws = (const struct clk_hw*[]) {
1853				&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1854			},
1855			.num_parents = 1,
1856			.flags = CLK_SET_RATE_PARENT,
1857			.ops = &clk_branch2_ops,
1858		},
1859	},
1860};
1861
1862static struct clk_branch gcc_pcie_0_pipe_clk = {
1863	.halt_reg = 0x6b048,
1864	.halt_check = BRANCH_HALT_SKIP,
1865	.clkr = {
1866		.enable_reg = 0x52008,
1867		.enable_mask = BIT(4),
1868		.hw.init = &(const struct clk_init_data) {
1869			.name = "gcc_pcie_0_pipe_clk",
1870			.parent_hws = (const struct clk_hw*[]) {
1871				&gcc_pcie_0_pipe_clk_src.clkr.hw,
1872			},
1873			.num_parents = 1,
1874			.flags = CLK_SET_RATE_PARENT,
1875			.ops = &clk_branch2_ops,
1876		},
1877	},
1878};
1879
1880static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1881	.halt_reg = 0x6b020,
1882	.halt_check = BRANCH_HALT_VOTED,
1883	.hwcg_reg = 0x6b020,
1884	.hwcg_bit = 1,
1885	.clkr = {
1886		.enable_reg = 0x52008,
1887		.enable_mask = BIT(0),
1888		.hw.init = &(const struct clk_init_data) {
1889			.name = "gcc_pcie_0_slv_axi_clk",
1890			.ops = &clk_branch2_ops,
1891		},
1892	},
1893};
1894
1895static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1896	.halt_reg = 0x6b01c,
1897	.halt_check = BRANCH_HALT_VOTED,
1898	.clkr = {
1899		.enable_reg = 0x52008,
1900		.enable_mask = BIT(5),
1901		.hw.init = &(const struct clk_init_data) {
1902			.name = "gcc_pcie_0_slv_q2a_axi_clk",
1903			.ops = &clk_branch2_ops,
1904		},
1905	},
1906};
1907
1908static struct clk_branch gcc_pcie_1_aux_clk = {
1909	.halt_reg = 0x8d038,
1910	.halt_check = BRANCH_HALT_VOTED,
1911	.clkr = {
1912		.enable_reg = 0x52000,
1913		.enable_mask = BIT(29),
1914		.hw.init = &(const struct clk_init_data) {
1915			.name = "gcc_pcie_1_aux_clk",
1916			.parent_hws = (const struct clk_hw*[]) {
1917				&gcc_pcie_1_aux_clk_src.clkr.hw,
1918			},
1919			.num_parents = 1,
1920			.flags = CLK_SET_RATE_PARENT,
1921			.ops = &clk_branch2_ops,
1922		},
1923	},
1924};
1925
1926static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1927	.halt_reg = 0x8d034,
1928	.halt_check = BRANCH_HALT_VOTED,
1929	.hwcg_reg = 0x8d034,
1930	.hwcg_bit = 1,
1931	.clkr = {
1932		.enable_reg = 0x52000,
1933		.enable_mask = BIT(28),
1934		.hw.init = &(const struct clk_init_data) {
1935			.name = "gcc_pcie_1_cfg_ahb_clk",
1936			.ops = &clk_branch2_ops,
1937		},
1938	},
1939};
1940
1941static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1942	.halt_reg = 0x8d028,
1943	.halt_check = BRANCH_HALT_SKIP,
1944	.hwcg_reg = 0x8d028,
1945	.hwcg_bit = 1,
1946	.clkr = {
1947		.enable_reg = 0x52000,
1948		.enable_mask = BIT(27),
1949		.hw.init = &(const struct clk_init_data) {
1950			.name = "gcc_pcie_1_mstr_axi_clk",
1951			.ops = &clk_branch2_ops,
1952		},
1953	},
1954};
1955
1956static struct clk_branch gcc_pcie_1_phy_aux_clk = {
1957	.halt_reg = 0x8d044,
1958	.halt_check = BRANCH_HALT_VOTED,
1959	.clkr = {
1960		.enable_reg = 0x52000,
1961		.enable_mask = BIT(24),
1962		.hw.init = &(const struct clk_init_data) {
1963			.name = "gcc_pcie_1_phy_aux_clk",
1964			.parent_hws = (const struct clk_hw*[]) {
1965				&gcc_pcie_1_phy_aux_clk_src.clkr.hw,
1966			},
1967			.num_parents = 1,
1968			.flags = CLK_SET_RATE_PARENT,
1969			.ops = &clk_branch2_ops,
1970		},
1971	},
1972};
1973
1974static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
1975	.halt_reg = 0x8d05c,
1976	.halt_check = BRANCH_HALT_VOTED,
1977	.clkr = {
1978		.enable_reg = 0x52000,
1979		.enable_mask = BIT(23),
1980		.hw.init = &(const struct clk_init_data) {
1981			.name = "gcc_pcie_1_phy_rchng_clk",
1982			.parent_hws = (const struct clk_hw*[]) {
1983				&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1984			},
1985			.num_parents = 1,
1986			.flags = CLK_SET_RATE_PARENT,
1987			.ops = &clk_branch2_ops,
1988		},
1989	},
1990};
1991
1992static struct clk_branch gcc_pcie_1_pipe_clk = {
1993	.halt_reg = 0x8d050,
1994	.halt_check = BRANCH_HALT_SKIP,
1995	.clkr = {
1996		.enable_reg = 0x52000,
1997		.enable_mask = BIT(30),
1998		.hw.init = &(const struct clk_init_data) {
1999			.name = "gcc_pcie_1_pipe_clk",
2000			.parent_hws = (const struct clk_hw*[]) {
2001				&gcc_pcie_1_pipe_clk_src.clkr.hw,
2002			},
2003			.num_parents = 1,
2004			.flags = CLK_SET_RATE_PARENT,
2005			.ops = &clk_branch2_ops,
2006		},
2007	},
2008};
2009
2010static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2011	.halt_reg = 0x8d01c,
2012	.halt_check = BRANCH_HALT_VOTED,
2013	.hwcg_reg = 0x8d01c,
2014	.hwcg_bit = 1,
2015	.clkr = {
2016		.enable_reg = 0x52000,
2017		.enable_mask = BIT(26),
2018		.hw.init = &(const struct clk_init_data) {
2019			.name = "gcc_pcie_1_slv_axi_clk",
2020			.ops = &clk_branch2_ops,
2021		},
2022	},
2023};
2024
2025static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
2026	.halt_reg = 0x8d018,
2027	.halt_check = BRANCH_HALT_VOTED,
2028	.clkr = {
2029		.enable_reg = 0x52000,
2030		.enable_mask = BIT(25),
2031		.hw.init = &(const struct clk_init_data) {
2032			.name = "gcc_pcie_1_slv_q2a_axi_clk",
2033			.ops = &clk_branch2_ops,
2034		},
2035	},
2036};
2037
2038static struct clk_branch gcc_pdm2_clk = {
2039	.halt_reg = 0x3300c,
2040	.halt_check = BRANCH_HALT,
2041	.clkr = {
2042		.enable_reg = 0x3300c,
2043		.enable_mask = BIT(0),
2044		.hw.init = &(const struct clk_init_data) {
2045			.name = "gcc_pdm2_clk",
2046			.parent_hws = (const struct clk_hw*[]) {
2047				&gcc_pdm2_clk_src.clkr.hw,
2048			},
2049			.num_parents = 1,
2050			.flags = CLK_SET_RATE_PARENT,
2051			.ops = &clk_branch2_ops,
2052		},
2053	},
2054};
2055
2056static struct clk_branch gcc_pdm_ahb_clk = {
2057	.halt_reg = 0x33004,
2058	.halt_check = BRANCH_HALT_VOTED,
2059	.hwcg_reg = 0x33004,
2060	.hwcg_bit = 1,
2061	.clkr = {
2062		.enable_reg = 0x33004,
2063		.enable_mask = BIT(0),
2064		.hw.init = &(const struct clk_init_data) {
2065			.name = "gcc_pdm_ahb_clk",
2066			.ops = &clk_branch2_ops,
2067		},
2068	},
2069};
2070
2071static struct clk_branch gcc_pdm_xo4_clk = {
2072	.halt_reg = 0x33008,
2073	.halt_check = BRANCH_HALT,
2074	.clkr = {
2075		.enable_reg = 0x33008,
2076		.enable_mask = BIT(0),
2077		.hw.init = &(const struct clk_init_data) {
2078			.name = "gcc_pdm_xo4_clk",
2079			.ops = &clk_branch2_ops,
2080		},
2081	},
2082};
2083
2084static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2085	.halt_reg = 0x26008,
2086	.halt_check = BRANCH_HALT_VOTED,
2087	.hwcg_reg = 0x26008,
2088	.hwcg_bit = 1,
2089	.clkr = {
2090		.enable_reg = 0x26008,
2091		.enable_mask = BIT(0),
2092		.hw.init = &(const struct clk_init_data) {
2093			.name = "gcc_qmip_camera_nrt_ahb_clk",
2094			.ops = &clk_branch2_ops,
2095		},
2096	},
2097};
2098
2099static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2100	.halt_reg = 0x2600c,
2101	.halt_check = BRANCH_HALT_VOTED,
2102	.hwcg_reg = 0x2600c,
2103	.hwcg_bit = 1,
2104	.clkr = {
2105		.enable_reg = 0x2600c,
2106		.enable_mask = BIT(0),
2107		.hw.init = &(const struct clk_init_data) {
2108			.name = "gcc_qmip_camera_rt_ahb_clk",
2109			.ops = &clk_branch2_ops,
2110		},
2111	},
2112};
2113
2114static struct clk_branch gcc_qmip_disp_ahb_clk = {
2115	.halt_reg = 0x27008,
2116	.halt_check = BRANCH_HALT_VOTED,
2117	.hwcg_reg = 0x27008,
2118	.hwcg_bit = 1,
2119	.clkr = {
2120		.enable_reg = 0x27008,
2121		.enable_mask = BIT(0),
2122		.hw.init = &(const struct clk_init_data) {
2123			.name = "gcc_qmip_disp_ahb_clk",
2124			.ops = &clk_branch2_ops,
2125		},
2126	},
2127};
2128
2129static struct clk_branch gcc_qmip_gpu_ahb_clk = {
2130	.halt_reg = 0x71008,
2131	.halt_check = BRANCH_HALT_VOTED,
2132	.hwcg_reg = 0x71008,
2133	.hwcg_bit = 1,
2134	.clkr = {
2135		.enable_reg = 0x71008,
2136		.enable_mask = BIT(0),
2137		.hw.init = &(const struct clk_init_data) {
2138			.name = "gcc_qmip_gpu_ahb_clk",
2139			.ops = &clk_branch2_ops,
2140		},
2141	},
2142};
2143
2144static struct clk_branch gcc_qmip_pcie_ahb_clk = {
2145	.halt_reg = 0x6b018,
2146	.halt_check = BRANCH_HALT_VOTED,
2147	.hwcg_reg = 0x6b018,
2148	.hwcg_bit = 1,
2149	.clkr = {
2150		.enable_reg = 0x52000,
2151		.enable_mask = BIT(11),
2152		.hw.init = &(const struct clk_init_data) {
2153			.name = "gcc_qmip_pcie_ahb_clk",
2154			.ops = &clk_branch2_ops,
2155		},
2156	},
2157};
2158
2159static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
2160	.halt_reg = 0x32014,
2161	.halt_check = BRANCH_HALT_VOTED,
2162	.hwcg_reg = 0x32014,
2163	.hwcg_bit = 1,
2164	.clkr = {
2165		.enable_reg = 0x32014,
2166		.enable_mask = BIT(0),
2167		.hw.init = &(const struct clk_init_data) {
2168			.name = "gcc_qmip_video_cv_cpu_ahb_clk",
2169			.ops = &clk_branch2_ops,
2170		},
2171	},
2172};
2173
2174static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2175	.halt_reg = 0x32008,
2176	.halt_check = BRANCH_HALT_VOTED,
2177	.hwcg_reg = 0x32008,
2178	.hwcg_bit = 1,
2179	.clkr = {
2180		.enable_reg = 0x32008,
2181		.enable_mask = BIT(0),
2182		.hw.init = &(const struct clk_init_data) {
2183			.name = "gcc_qmip_video_cvp_ahb_clk",
2184			.ops = &clk_branch2_ops,
2185		},
2186	},
2187};
2188
2189static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
2190	.halt_reg = 0x32010,
2191	.halt_check = BRANCH_HALT_VOTED,
2192	.hwcg_reg = 0x32010,
2193	.hwcg_bit = 1,
2194	.clkr = {
2195		.enable_reg = 0x32010,
2196		.enable_mask = BIT(0),
2197		.hw.init = &(const struct clk_init_data) {
2198			.name = "gcc_qmip_video_v_cpu_ahb_clk",
2199			.ops = &clk_branch2_ops,
2200		},
2201	},
2202};
2203
2204static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2205	.halt_reg = 0x3200c,
2206	.halt_check = BRANCH_HALT_VOTED,
2207	.hwcg_reg = 0x3200c,
2208	.hwcg_bit = 1,
2209	.clkr = {
2210		.enable_reg = 0x3200c,
2211		.enable_mask = BIT(0),
2212		.hw.init = &(const struct clk_init_data) {
2213			.name = "gcc_qmip_video_vcodec_ahb_clk",
2214			.ops = &clk_branch2_ops,
2215		},
2216	},
2217};
2218
2219static struct clk_branch gcc_qupv3_i2c_core_clk = {
2220	.halt_reg = 0x23004,
2221	.halt_check = BRANCH_HALT_VOTED,
2222	.clkr = {
2223		.enable_reg = 0x52008,
2224		.enable_mask = BIT(8),
2225		.hw.init = &(const struct clk_init_data) {
2226			.name = "gcc_qupv3_i2c_core_clk",
2227			.ops = &clk_branch2_ops,
2228		},
2229	},
2230};
2231
2232static struct clk_branch gcc_qupv3_i2c_s0_clk = {
2233	.halt_reg = 0x17004,
2234	.halt_check = BRANCH_HALT_VOTED,
2235	.clkr = {
2236		.enable_reg = 0x52008,
2237		.enable_mask = BIT(10),
2238		.hw.init = &(const struct clk_init_data) {
2239			.name = "gcc_qupv3_i2c_s0_clk",
2240			.parent_hws = (const struct clk_hw*[]) {
2241				&gcc_qupv3_i2c_s0_clk_src.clkr.hw,
2242			},
2243			.num_parents = 1,
2244			.flags = CLK_SET_RATE_PARENT,
2245			.ops = &clk_branch2_ops,
2246		},
2247	},
2248};
2249
2250static struct clk_branch gcc_qupv3_i2c_s1_clk = {
2251	.halt_reg = 0x17020,
2252	.halt_check = BRANCH_HALT_VOTED,
2253	.clkr = {
2254		.enable_reg = 0x52008,
2255		.enable_mask = BIT(11),
2256		.hw.init = &(const struct clk_init_data) {
2257			.name = "gcc_qupv3_i2c_s1_clk",
2258			.parent_hws = (const struct clk_hw*[]) {
2259				&gcc_qupv3_i2c_s1_clk_src.clkr.hw,
2260			},
2261			.num_parents = 1,
2262			.flags = CLK_SET_RATE_PARENT,
2263			.ops = &clk_branch2_ops,
2264		},
2265	},
2266};
2267
2268static struct clk_branch gcc_qupv3_i2c_s2_clk = {
2269	.halt_reg = 0x1703c,
2270	.halt_check = BRANCH_HALT_VOTED,
2271	.clkr = {
2272		.enable_reg = 0x52008,
2273		.enable_mask = BIT(12),
2274		.hw.init = &(const struct clk_init_data) {
2275			.name = "gcc_qupv3_i2c_s2_clk",
2276			.parent_hws = (const struct clk_hw*[]) {
2277				&gcc_qupv3_i2c_s2_clk_src.clkr.hw,
2278			},
2279			.num_parents = 1,
2280			.flags = CLK_SET_RATE_PARENT,
2281			.ops = &clk_branch2_ops,
2282		},
2283	},
2284};
2285
2286static struct clk_branch gcc_qupv3_i2c_s3_clk = {
2287	.halt_reg = 0x17058,
2288	.halt_check = BRANCH_HALT_VOTED,
2289	.clkr = {
2290		.enable_reg = 0x52008,
2291		.enable_mask = BIT(13),
2292		.hw.init = &(const struct clk_init_data) {
2293			.name = "gcc_qupv3_i2c_s3_clk",
2294			.parent_hws = (const struct clk_hw*[]) {
2295				&gcc_qupv3_i2c_s3_clk_src.clkr.hw,
2296			},
2297			.num_parents = 1,
2298			.flags = CLK_SET_RATE_PARENT,
2299			.ops = &clk_branch2_ops,
2300		},
2301	},
2302};
2303
2304static struct clk_branch gcc_qupv3_i2c_s4_clk = {
2305	.halt_reg = 0x17074,
2306	.halt_check = BRANCH_HALT_VOTED,
2307	.clkr = {
2308		.enable_reg = 0x52008,
2309		.enable_mask = BIT(14),
2310		.hw.init = &(const struct clk_init_data) {
2311			.name = "gcc_qupv3_i2c_s4_clk",
2312			.parent_hws = (const struct clk_hw*[]) {
2313				&gcc_qupv3_i2c_s4_clk_src.clkr.hw,
2314			},
2315			.num_parents = 1,
2316			.flags = CLK_SET_RATE_PARENT,
2317			.ops = &clk_branch2_ops,
2318		},
2319	},
2320};
2321
2322static struct clk_branch gcc_qupv3_i2c_s5_clk = {
2323	.halt_reg = 0x17090,
2324	.halt_check = BRANCH_HALT_VOTED,
2325	.clkr = {
2326		.enable_reg = 0x52008,
2327		.enable_mask = BIT(15),
2328		.hw.init = &(const struct clk_init_data) {
2329			.name = "gcc_qupv3_i2c_s5_clk",
2330			.parent_hws = (const struct clk_hw*[]) {
2331				&gcc_qupv3_i2c_s5_clk_src.clkr.hw,
2332			},
2333			.num_parents = 1,
2334			.flags = CLK_SET_RATE_PARENT,
2335			.ops = &clk_branch2_ops,
2336		},
2337	},
2338};
2339
2340static struct clk_branch gcc_qupv3_i2c_s6_clk = {
2341	.halt_reg = 0x170ac,
2342	.halt_check = BRANCH_HALT_VOTED,
2343	.clkr = {
2344		.enable_reg = 0x52008,
2345		.enable_mask = BIT(16),
2346		.hw.init = &(const struct clk_init_data) {
2347			.name = "gcc_qupv3_i2c_s6_clk",
2348			.parent_hws = (const struct clk_hw*[]) {
2349				&gcc_qupv3_i2c_s6_clk_src.clkr.hw,
2350			},
2351			.num_parents = 1,
2352			.flags = CLK_SET_RATE_PARENT,
2353			.ops = &clk_branch2_ops,
2354		},
2355	},
2356};
2357
2358static struct clk_branch gcc_qupv3_i2c_s7_clk = {
2359	.halt_reg = 0x170c8,
2360	.halt_check = BRANCH_HALT_VOTED,
2361	.clkr = {
2362		.enable_reg = 0x52008,
2363		.enable_mask = BIT(17),
2364		.hw.init = &(const struct clk_init_data) {
2365			.name = "gcc_qupv3_i2c_s7_clk",
2366			.parent_hws = (const struct clk_hw*[]) {
2367				&gcc_qupv3_i2c_s7_clk_src.clkr.hw,
2368			},
2369			.num_parents = 1,
2370			.flags = CLK_SET_RATE_PARENT,
2371			.ops = &clk_branch2_ops,
2372		},
2373	},
2374};
2375
2376static struct clk_branch gcc_qupv3_i2c_s8_clk = {
2377	.halt_reg = 0x170e4,
2378	.halt_check = BRANCH_HALT_VOTED,
2379	.clkr = {
2380		.enable_reg = 0x52010,
2381		.enable_mask = BIT(14),
2382		.hw.init = &(const struct clk_init_data) {
2383			.name = "gcc_qupv3_i2c_s8_clk",
2384			.parent_hws = (const struct clk_hw*[]) {
2385				&gcc_qupv3_i2c_s8_clk_src.clkr.hw,
2386			},
2387			.num_parents = 1,
2388			.flags = CLK_SET_RATE_PARENT,
2389			.ops = &clk_branch2_ops,
2390		},
2391	},
2392};
2393
2394static struct clk_branch gcc_qupv3_i2c_s9_clk = {
2395	.halt_reg = 0x17100,
2396	.halt_check = BRANCH_HALT_VOTED,
2397	.clkr = {
2398		.enable_reg = 0x52010,
2399		.enable_mask = BIT(15),
2400		.hw.init = &(const struct clk_init_data) {
2401			.name = "gcc_qupv3_i2c_s9_clk",
2402			.parent_hws = (const struct clk_hw*[]) {
2403				&gcc_qupv3_i2c_s9_clk_src.clkr.hw,
2404			},
2405			.num_parents = 1,
2406			.flags = CLK_SET_RATE_PARENT,
2407			.ops = &clk_branch2_ops,
2408		},
2409	},
2410};
2411
2412static struct clk_branch gcc_qupv3_i2c_s_ahb_clk = {
2413	.halt_reg = 0x23000,
2414	.halt_check = BRANCH_HALT_VOTED,
2415	.hwcg_reg = 0x23000,
2416	.hwcg_bit = 1,
2417	.clkr = {
2418		.enable_reg = 0x52008,
2419		.enable_mask = BIT(7),
2420		.hw.init = &(const struct clk_init_data) {
2421			.name = "gcc_qupv3_i2c_s_ahb_clk",
2422			.ops = &clk_branch2_ops,
2423		},
2424	},
2425};
2426
2427static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2428	.halt_reg = 0x23154,
2429	.halt_check = BRANCH_HALT_VOTED,
2430	.clkr = {
2431		.enable_reg = 0x52008,
2432		.enable_mask = BIT(18),
2433		.hw.init = &(const struct clk_init_data) {
2434			.name = "gcc_qupv3_wrap1_core_2x_clk",
2435			.ops = &clk_branch2_ops,
2436		},
2437	},
2438};
2439
2440static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2441	.halt_reg = 0x23144,
2442	.halt_check = BRANCH_HALT_VOTED,
2443	.clkr = {
2444		.enable_reg = 0x52008,
2445		.enable_mask = BIT(19),
2446		.hw.init = &(const struct clk_init_data) {
2447			.name = "gcc_qupv3_wrap1_core_clk",
2448			.ops = &clk_branch2_ops,
2449		},
2450	},
2451};
2452
2453static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk = {
2454	.halt_reg = 0x1889c,
2455	.halt_check = BRANCH_HALT_VOTED,
2456	.clkr = {
2457		.enable_reg = 0x52010,
2458		.enable_mask = BIT(29),
2459		.hw.init = &(const struct clk_init_data) {
2460			.name = "gcc_qupv3_wrap1_qspi_ref_clk",
2461			.parent_hws = (const struct clk_hw*[]) {
2462				&gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw,
2463			},
2464			.num_parents = 1,
2465			.flags = CLK_SET_RATE_PARENT,
2466			.ops = &clk_branch2_ops,
2467		},
2468	},
2469};
2470
2471static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2472	.halt_reg = 0x18004,
2473	.halt_check = BRANCH_HALT_VOTED,
2474	.clkr = {
2475		.enable_reg = 0x52008,
2476		.enable_mask = BIT(22),
2477		.hw.init = &(const struct clk_init_data) {
2478			.name = "gcc_qupv3_wrap1_s0_clk",
2479			.parent_hws = (const struct clk_hw*[]) {
2480				&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2481			},
2482			.num_parents = 1,
2483			.flags = CLK_SET_RATE_PARENT,
2484			.ops = &clk_branch2_ops,
2485		},
2486	},
2487};
2488
2489static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2490	.halt_reg = 0x1813c,
2491	.halt_check = BRANCH_HALT_VOTED,
2492	.clkr = {
2493		.enable_reg = 0x52008,
2494		.enable_mask = BIT(23),
2495		.hw.init = &(const struct clk_init_data) {
2496			.name = "gcc_qupv3_wrap1_s1_clk",
2497			.parent_hws = (const struct clk_hw*[]) {
2498				&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2499			},
2500			.num_parents = 1,
2501			.flags = CLK_SET_RATE_PARENT,
2502			.ops = &clk_branch2_ops,
2503		},
2504	},
2505};
2506
2507static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2508	.halt_reg = 0x18274,
2509	.halt_check = BRANCH_HALT_VOTED,
2510	.clkr = {
2511		.enable_reg = 0x52008,
2512		.enable_mask = BIT(24),
2513		.hw.init = &(const struct clk_init_data) {
2514			.name = "gcc_qupv3_wrap1_s2_clk",
2515			.parent_hws = (const struct clk_hw*[]) {
2516				&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2517			},
2518			.num_parents = 1,
2519			.flags = CLK_SET_RATE_PARENT,
2520			.ops = &clk_branch2_ops,
2521		},
2522	},
2523};
2524
2525static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2526	.halt_reg = 0x18284,
2527	.halt_check = BRANCH_HALT_VOTED,
2528	.clkr = {
2529		.enable_reg = 0x52008,
2530		.enable_mask = BIT(25),
2531		.hw.init = &(const struct clk_init_data) {
2532			.name = "gcc_qupv3_wrap1_s3_clk",
2533			.parent_hws = (const struct clk_hw*[]) {
2534				&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2535			},
2536			.num_parents = 1,
2537			.flags = CLK_SET_RATE_PARENT,
2538			.ops = &clk_branch2_ops,
2539		},
2540	},
2541};
2542
2543static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2544	.halt_reg = 0x183bc,
2545	.halt_check = BRANCH_HALT_VOTED,
2546	.clkr = {
2547		.enable_reg = 0x52008,
2548		.enable_mask = BIT(26),
2549		.hw.init = &(const struct clk_init_data) {
2550			.name = "gcc_qupv3_wrap1_s4_clk",
2551			.parent_hws = (const struct clk_hw*[]) {
2552				&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2553			},
2554			.num_parents = 1,
2555			.flags = CLK_SET_RATE_PARENT,
2556			.ops = &clk_branch2_ops,
2557		},
2558	},
2559};
2560
2561static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2562	.halt_reg = 0x184f4,
2563	.halt_check = BRANCH_HALT_VOTED,
2564	.clkr = {
2565		.enable_reg = 0x52008,
2566		.enable_mask = BIT(27),
2567		.hw.init = &(const struct clk_init_data) {
2568			.name = "gcc_qupv3_wrap1_s5_clk",
2569			.parent_hws = (const struct clk_hw*[]) {
2570				&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2571			},
2572			.num_parents = 1,
2573			.flags = CLK_SET_RATE_PARENT,
2574			.ops = &clk_branch2_ops,
2575		},
2576	},
2577};
2578
2579static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2580	.halt_reg = 0x1862c,
2581	.halt_check = BRANCH_HALT_VOTED,
2582	.clkr = {
2583		.enable_reg = 0x52008,
2584		.enable_mask = BIT(28),
2585		.hw.init = &(const struct clk_init_data) {
2586			.name = "gcc_qupv3_wrap1_s6_clk",
2587			.parent_hws = (const struct clk_hw*[]) {
2588				&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2589			},
2590			.num_parents = 1,
2591			.flags = CLK_SET_RATE_PARENT,
2592			.ops = &clk_branch2_ops,
2593		},
2594	},
2595};
2596
2597static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2598	.halt_reg = 0x18764,
2599	.halt_check = BRANCH_HALT_VOTED,
2600	.clkr = {
2601		.enable_reg = 0x52010,
2602		.enable_mask = BIT(16),
2603		.hw.init = &(const struct clk_init_data) {
2604			.name = "gcc_qupv3_wrap1_s7_clk",
2605			.parent_hws = (const struct clk_hw*[]) {
2606				&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
2607			},
2608			.num_parents = 1,
2609			.flags = CLK_SET_RATE_PARENT,
2610			.ops = &clk_branch2_ops,
2611		},
2612	},
2613};
2614
2615static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
2616	.halt_reg = 0x232a4,
2617	.halt_check = BRANCH_HALT_VOTED,
2618	.clkr = {
2619		.enable_reg = 0x52010,
2620		.enable_mask = BIT(3),
2621		.hw.init = &(const struct clk_init_data) {
2622			.name = "gcc_qupv3_wrap2_core_2x_clk",
2623			.ops = &clk_branch2_ops,
2624		},
2625	},
2626};
2627
2628static struct clk_branch gcc_qupv3_wrap2_core_clk = {
2629	.halt_reg = 0x23294,
2630	.halt_check = BRANCH_HALT_VOTED,
2631	.clkr = {
2632		.enable_reg = 0x52010,
2633		.enable_mask = BIT(0),
2634		.hw.init = &(const struct clk_init_data) {
2635			.name = "gcc_qupv3_wrap2_core_clk",
2636			.ops = &clk_branch2_ops,
2637		},
2638	},
2639};
2640
2641static struct clk_branch gcc_qupv3_wrap2_ibi_ctrl_2_clk = {
2642	.halt_reg = 0x1e9cc,
2643	.halt_check = BRANCH_HALT_VOTED,
2644	.hwcg_reg = 0x1e9cc,
2645	.hwcg_bit = 1,
2646	.clkr = {
2647		.enable_reg = 0x52010,
2648		.enable_mask = BIT(27),
2649		.hw.init = &(const struct clk_init_data) {
2650			.name = "gcc_qupv3_wrap2_ibi_ctrl_2_clk",
2651			.parent_hws = (const struct clk_hw*[]) {
2652				&gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr.hw,
2653			},
2654			.num_parents = 1,
2655			.flags = CLK_SET_RATE_PARENT,
2656			.ops = &clk_branch2_ops,
2657		},
2658	},
2659};
2660
2661static struct clk_branch gcc_qupv3_wrap2_ibi_ctrl_3_clk = {
2662	.halt_reg = 0x1e9d0,
2663	.halt_check = BRANCH_HALT_VOTED,
2664	.hwcg_reg = 0x1e9d0,
2665	.hwcg_bit = 1,
2666	.clkr = {
2667		.enable_reg = 0x52010,
2668		.enable_mask = BIT(28),
2669		.hw.init = &(const struct clk_init_data) {
2670			.name = "gcc_qupv3_wrap2_ibi_ctrl_3_clk",
2671			.parent_hws = (const struct clk_hw*[]) {
2672				&gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr.hw,
2673			},
2674			.num_parents = 1,
2675			.flags = CLK_SET_RATE_PARENT,
2676			.ops = &clk_branch2_ops,
2677		},
2678	},
2679};
2680
2681static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2682	.halt_reg = 0x1e004,
2683	.halt_check = BRANCH_HALT_VOTED,
2684	.clkr = {
2685		.enable_reg = 0x52010,
2686		.enable_mask = BIT(4),
2687		.hw.init = &(const struct clk_init_data) {
2688			.name = "gcc_qupv3_wrap2_s0_clk",
2689			.parent_hws = (const struct clk_hw*[]) {
2690				&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
2691			},
2692			.num_parents = 1,
2693			.flags = CLK_SET_RATE_PARENT,
2694			.ops = &clk_branch2_ops,
2695		},
2696	},
2697};
2698
2699static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2700	.halt_reg = 0x1e13c,
2701	.halt_check = BRANCH_HALT_VOTED,
2702	.clkr = {
2703		.enable_reg = 0x52010,
2704		.enable_mask = BIT(5),
2705		.hw.init = &(const struct clk_init_data) {
2706			.name = "gcc_qupv3_wrap2_s1_clk",
2707			.parent_hws = (const struct clk_hw*[]) {
2708				&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
2709			},
2710			.num_parents = 1,
2711			.flags = CLK_SET_RATE_PARENT,
2712			.ops = &clk_branch2_ops,
2713		},
2714	},
2715};
2716
2717static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2718	.halt_reg = 0x1e274,
2719	.halt_check = BRANCH_HALT_VOTED,
2720	.clkr = {
2721		.enable_reg = 0x52010,
2722		.enable_mask = BIT(6),
2723		.hw.init = &(const struct clk_init_data) {
2724			.name = "gcc_qupv3_wrap2_s2_clk",
2725			.parent_hws = (const struct clk_hw*[]) {
2726				&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2727			},
2728			.num_parents = 1,
2729			.flags = CLK_SET_RATE_PARENT,
2730			.ops = &clk_branch2_ops,
2731		},
2732	},
2733};
2734
2735static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2736	.halt_reg = 0x1e3ac,
2737	.halt_check = BRANCH_HALT_VOTED,
2738	.clkr = {
2739		.enable_reg = 0x52010,
2740		.enable_mask = BIT(7),
2741		.hw.init = &(const struct clk_init_data) {
2742			.name = "gcc_qupv3_wrap2_s3_clk",
2743			.parent_hws = (const struct clk_hw*[]) {
2744				&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2745			},
2746			.num_parents = 1,
2747			.flags = CLK_SET_RATE_PARENT,
2748			.ops = &clk_branch2_ops,
2749		},
2750	},
2751};
2752
2753static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2754	.halt_reg = 0x1e4e4,
2755	.halt_check = BRANCH_HALT_VOTED,
2756	.clkr = {
2757		.enable_reg = 0x52010,
2758		.enable_mask = BIT(8),
2759		.hw.init = &(const struct clk_init_data) {
2760			.name = "gcc_qupv3_wrap2_s4_clk",
2761			.parent_hws = (const struct clk_hw*[]) {
2762				&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
2763			},
2764			.num_parents = 1,
2765			.flags = CLK_SET_RATE_PARENT,
2766			.ops = &clk_branch2_ops,
2767		},
2768	},
2769};
2770
2771static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2772	.halt_reg = 0x1e61c,
2773	.halt_check = BRANCH_HALT_VOTED,
2774	.clkr = {
2775		.enable_reg = 0x52010,
2776		.enable_mask = BIT(9),
2777		.hw.init = &(const struct clk_init_data) {
2778			.name = "gcc_qupv3_wrap2_s5_clk",
2779			.parent_hws = (const struct clk_hw*[]) {
2780				&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
2781			},
2782			.num_parents = 1,
2783			.flags = CLK_SET_RATE_PARENT,
2784			.ops = &clk_branch2_ops,
2785		},
2786	},
2787};
2788
2789static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
2790	.halt_reg = 0x1e754,
2791	.halt_check = BRANCH_HALT_VOTED,
2792	.clkr = {
2793		.enable_reg = 0x52010,
2794		.enable_mask = BIT(10),
2795		.hw.init = &(const struct clk_init_data) {
2796			.name = "gcc_qupv3_wrap2_s6_clk",
2797			.parent_hws = (const struct clk_hw*[]) {
2798				&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
2799			},
2800			.num_parents = 1,
2801			.flags = CLK_SET_RATE_PARENT,
2802			.ops = &clk_branch2_ops,
2803		},
2804	},
2805};
2806
2807static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
2808	.halt_reg = 0x1e88c,
2809	.halt_check = BRANCH_HALT_VOTED,
2810	.clkr = {
2811		.enable_reg = 0x52010,
2812		.enable_mask = BIT(17),
2813		.hw.init = &(const struct clk_init_data) {
2814			.name = "gcc_qupv3_wrap2_s7_clk",
2815			.parent_hws = (const struct clk_hw*[]) {
2816				&gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
2817			},
2818			.num_parents = 1,
2819			.flags = CLK_SET_RATE_PARENT,
2820			.ops = &clk_branch2_ops,
2821		},
2822	},
2823};
2824
2825static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = {
2826	.halt_reg = 0x233f4,
2827	.halt_check = BRANCH_HALT_VOTED,
2828	.clkr = {
2829		.enable_reg = 0x52018,
2830		.enable_mask = BIT(1),
2831		.hw.init = &(const struct clk_init_data) {
2832			.name = "gcc_qupv3_wrap3_core_2x_clk",
2833			.ops = &clk_branch2_ops,
2834		},
2835	},
2836};
2837
2838static struct clk_branch gcc_qupv3_wrap3_core_clk = {
2839	.halt_reg = 0x233e4,
2840	.halt_check = BRANCH_HALT_VOTED,
2841	.clkr = {
2842		.enable_reg = 0x52018,
2843		.enable_mask = BIT(0),
2844		.hw.init = &(const struct clk_init_data) {
2845			.name = "gcc_qupv3_wrap3_core_clk",
2846			.ops = &clk_branch2_ops,
2847		},
2848	},
2849};
2850
2851static struct clk_branch gcc_qupv3_wrap3_qspi_ref_clk = {
2852	.halt_reg = 0x19014,
2853	.halt_check = BRANCH_HALT_VOTED,
2854	.clkr = {
2855		.enable_reg = 0x52018,
2856		.enable_mask = BIT(3),
2857		.hw.init = &(const struct clk_init_data) {
2858			.name = "gcc_qupv3_wrap3_qspi_ref_clk",
2859			.parent_hws = (const struct clk_hw*[]) {
2860				&gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw,
2861			},
2862			.num_parents = 1,
2863			.flags = CLK_SET_RATE_PARENT,
2864			.ops = &clk_branch2_ops,
2865		},
2866	},
2867};
2868
2869static struct clk_branch gcc_qupv3_wrap3_s0_clk = {
2870	.halt_reg = 0x19004,
2871	.halt_check = BRANCH_HALT_VOTED,
2872	.clkr = {
2873		.enable_reg = 0x52018,
2874		.enable_mask = BIT(2),
2875		.hw.init = &(const struct clk_init_data) {
2876			.name = "gcc_qupv3_wrap3_s0_clk",
2877			.parent_hws = (const struct clk_hw*[]) {
2878				&gcc_qupv3_wrap3_s0_clk_src.clkr.hw,
2879			},
2880			.num_parents = 1,
2881			.flags = CLK_SET_RATE_PARENT,
2882			.ops = &clk_branch2_ops,
2883		},
2884	},
2885};
2886
2887static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2888	.halt_reg = 0x2313c,
2889	.halt_check = BRANCH_HALT_VOTED,
2890	.hwcg_reg = 0x2313c,
2891	.hwcg_bit = 1,
2892	.clkr = {
2893		.enable_reg = 0x52008,
2894		.enable_mask = BIT(20),
2895		.hw.init = &(const struct clk_init_data) {
2896			.name = "gcc_qupv3_wrap_1_m_ahb_clk",
2897			.ops = &clk_branch2_ops,
2898		},
2899	},
2900};
2901
2902static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2903	.halt_reg = 0x23140,
2904	.halt_check = BRANCH_HALT_VOTED,
2905	.hwcg_reg = 0x23140,
2906	.hwcg_bit = 1,
2907	.clkr = {
2908		.enable_reg = 0x52008,
2909		.enable_mask = BIT(21),
2910		.hw.init = &(const struct clk_init_data) {
2911			.name = "gcc_qupv3_wrap_1_s_ahb_clk",
2912			.ops = &clk_branch2_ops,
2913		},
2914	},
2915};
2916
2917static struct clk_branch gcc_qupv3_wrap_2_ibi_2_ahb_clk = {
2918	.halt_reg = 0x1e9c4,
2919	.halt_check = BRANCH_HALT_VOTED,
2920	.hwcg_reg = 0x1e9c4,
2921	.hwcg_bit = 1,
2922	.clkr = {
2923		.enable_reg = 0x52010,
2924		.enable_mask = BIT(25),
2925		.hw.init = &(const struct clk_init_data) {
2926			.name = "gcc_qupv3_wrap_2_ibi_2_ahb_clk",
2927			.ops = &clk_branch2_ops,
2928		},
2929	},
2930};
2931
2932static struct clk_branch gcc_qupv3_wrap_2_ibi_3_ahb_clk = {
2933	.halt_reg = 0x1e9c8,
2934	.halt_check = BRANCH_HALT_VOTED,
2935	.hwcg_reg = 0x1e9c8,
2936	.hwcg_bit = 1,
2937	.clkr = {
2938		.enable_reg = 0x52010,
2939		.enable_mask = BIT(26),
2940		.hw.init = &(const struct clk_init_data) {
2941			.name = "gcc_qupv3_wrap_2_ibi_3_ahb_clk",
2942			.ops = &clk_branch2_ops,
2943		},
2944	},
2945};
2946
2947static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2948	.halt_reg = 0x2328c,
2949	.halt_check = BRANCH_HALT_VOTED,
2950	.hwcg_reg = 0x2328c,
2951	.hwcg_bit = 1,
2952	.clkr = {
2953		.enable_reg = 0x52010,
2954		.enable_mask = BIT(2),
2955		.hw.init = &(const struct clk_init_data) {
2956			.name = "gcc_qupv3_wrap_2_m_ahb_clk",
2957			.ops = &clk_branch2_ops,
2958		},
2959	},
2960};
2961
2962static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2963	.halt_reg = 0x23290,
2964	.halt_check = BRANCH_HALT_VOTED,
2965	.hwcg_reg = 0x23290,
2966	.hwcg_bit = 1,
2967	.clkr = {
2968		.enable_reg = 0x52010,
2969		.enable_mask = BIT(1),
2970		.hw.init = &(const struct clk_init_data) {
2971			.name = "gcc_qupv3_wrap_2_s_ahb_clk",
2972			.ops = &clk_branch2_ops,
2973		},
2974	},
2975};
2976
2977static struct clk_branch gcc_qupv3_wrap_3_m_ahb_clk = {
2978	.halt_reg = 0x233dc,
2979	.halt_check = BRANCH_HALT_VOTED,
2980	.hwcg_reg = 0x233dc,
2981	.hwcg_bit = 1,
2982	.clkr = {
2983		.enable_reg = 0x52010,
2984		.enable_mask = BIT(30),
2985		.hw.init = &(const struct clk_init_data) {
2986			.name = "gcc_qupv3_wrap_3_m_ahb_clk",
2987			.ops = &clk_branch2_ops,
2988		},
2989	},
2990};
2991
2992static struct clk_branch gcc_qupv3_wrap_3_s_ahb_clk = {
2993	.halt_reg = 0x233e0,
2994	.halt_check = BRANCH_HALT_VOTED,
2995	.hwcg_reg = 0x233e0,
2996	.hwcg_bit = 1,
2997	.clkr = {
2998		.enable_reg = 0x52010,
2999		.enable_mask = BIT(31),
3000		.hw.init = &(const struct clk_init_data) {
3001			.name = "gcc_qupv3_wrap_3_s_ahb_clk",
3002			.ops = &clk_branch2_ops,
3003		},
3004	},
3005};
3006
3007static struct clk_branch gcc_sdcc2_ahb_clk = {
3008	.halt_reg = 0x14010,
3009	.halt_check = BRANCH_HALT,
3010	.clkr = {
3011		.enable_reg = 0x14010,
3012		.enable_mask = BIT(0),
3013		.hw.init = &(const struct clk_init_data) {
3014			.name = "gcc_sdcc2_ahb_clk",
3015			.ops = &clk_branch2_ops,
3016		},
3017	},
3018};
3019
3020static struct clk_branch gcc_sdcc2_apps_clk = {
3021	.halt_reg = 0x14004,
3022	.halt_check = BRANCH_HALT,
3023	.clkr = {
3024		.enable_reg = 0x14004,
3025		.enable_mask = BIT(0),
3026		.hw.init = &(const struct clk_init_data) {
3027			.name = "gcc_sdcc2_apps_clk",
3028			.parent_hws = (const struct clk_hw*[]) {
3029				&gcc_sdcc2_apps_clk_src.clkr.hw,
3030			},
3031			.num_parents = 1,
3032			.flags = CLK_SET_RATE_PARENT,
3033			.ops = &clk_branch2_ops,
3034		},
3035	},
3036};
3037
3038static struct clk_branch gcc_sdcc4_ahb_clk = {
3039	.halt_reg = 0x16010,
3040	.halt_check = BRANCH_HALT,
3041	.clkr = {
3042		.enable_reg = 0x16010,
3043		.enable_mask = BIT(0),
3044		.hw.init = &(const struct clk_init_data) {
3045			.name = "gcc_sdcc4_ahb_clk",
3046			.ops = &clk_branch2_ops,
3047		},
3048	},
3049};
3050
3051static struct clk_branch gcc_sdcc4_apps_clk = {
3052	.halt_reg = 0x16004,
3053	.halt_check = BRANCH_HALT,
3054	.clkr = {
3055		.enable_reg = 0x16004,
3056		.enable_mask = BIT(0),
3057		.hw.init = &(const struct clk_init_data) {
3058			.name = "gcc_sdcc4_apps_clk",
3059			.parent_hws = (const struct clk_hw*[]) {
3060				&gcc_sdcc4_apps_clk_src.clkr.hw,
3061			},
3062			.num_parents = 1,
3063			.flags = CLK_SET_RATE_PARENT,
3064			.ops = &clk_branch2_ops,
3065		},
3066	},
3067};
3068
3069static struct clk_branch gcc_ufs_phy_ahb_clk = {
3070	.halt_reg = 0x77024,
3071	.halt_check = BRANCH_HALT_VOTED,
3072	.hwcg_reg = 0x77024,
3073	.hwcg_bit = 1,
3074	.clkr = {
3075		.enable_reg = 0x77024,
3076		.enable_mask = BIT(0),
3077		.hw.init = &(const struct clk_init_data) {
3078			.name = "gcc_ufs_phy_ahb_clk",
3079			.ops = &clk_branch2_ops,
3080		},
3081	},
3082};
3083
3084static struct clk_branch gcc_ufs_phy_axi_clk = {
3085	.halt_reg = 0x77018,
3086	.halt_check = BRANCH_HALT_VOTED,
3087	.hwcg_reg = 0x77018,
3088	.hwcg_bit = 1,
3089	.clkr = {
3090		.enable_reg = 0x77018,
3091		.enable_mask = BIT(0),
3092		.hw.init = &(const struct clk_init_data) {
3093			.name = "gcc_ufs_phy_axi_clk",
3094			.parent_hws = (const struct clk_hw*[]) {
3095				&gcc_ufs_phy_axi_clk_src.clkr.hw,
3096			},
3097			.num_parents = 1,
3098			.flags = CLK_SET_RATE_PARENT,
3099			.ops = &clk_branch2_ops,
3100		},
3101	},
3102};
3103
3104static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
3105	.halt_reg = 0x77018,
3106	.halt_check = BRANCH_HALT_VOTED,
3107	.hwcg_reg = 0x77018,
3108	.hwcg_bit = 1,
3109	.clkr = {
3110		.enable_reg = 0x77018,
3111		.enable_mask = BIT(1),
3112		.hw.init = &(const struct clk_init_data) {
3113			.name = "gcc_ufs_phy_axi_hw_ctl_clk",
3114			.parent_hws = (const struct clk_hw*[]) {
3115				&gcc_ufs_phy_axi_clk_src.clkr.hw,
3116			},
3117			.num_parents = 1,
3118			.flags = CLK_SET_RATE_PARENT,
3119			.ops = &clk_branch2_ops,
3120		},
3121	},
3122};
3123
3124static struct clk_branch gcc_ufs_phy_ice_core_clk = {
3125	.halt_reg = 0x77074,
3126	.halt_check = BRANCH_HALT_VOTED,
3127	.hwcg_reg = 0x77074,
3128	.hwcg_bit = 1,
3129	.clkr = {
3130		.enable_reg = 0x77074,
3131		.enable_mask = BIT(0),
3132		.hw.init = &(const struct clk_init_data) {
3133			.name = "gcc_ufs_phy_ice_core_clk",
3134			.parent_hws = (const struct clk_hw*[]) {
3135				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3136			},
3137			.num_parents = 1,
3138			.flags = CLK_SET_RATE_PARENT,
3139			.ops = &clk_branch2_ops,
3140		},
3141	},
3142};
3143
3144static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
3145	.halt_reg = 0x77074,
3146	.halt_check = BRANCH_HALT_VOTED,
3147	.hwcg_reg = 0x77074,
3148	.hwcg_bit = 1,
3149	.clkr = {
3150		.enable_reg = 0x77074,
3151		.enable_mask = BIT(1),
3152		.hw.init = &(const struct clk_init_data) {
3153			.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
3154			.parent_hws = (const struct clk_hw*[]) {
3155				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3156			},
3157			.num_parents = 1,
3158			.flags = CLK_SET_RATE_PARENT,
3159			.ops = &clk_branch2_ops,
3160		},
3161	},
3162};
3163
3164static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3165	.halt_reg = 0x770b0,
3166	.halt_check = BRANCH_HALT_VOTED,
3167	.hwcg_reg = 0x770b0,
3168	.hwcg_bit = 1,
3169	.clkr = {
3170		.enable_reg = 0x770b0,
3171		.enable_mask = BIT(0),
3172		.hw.init = &(const struct clk_init_data) {
3173			.name = "gcc_ufs_phy_phy_aux_clk",
3174			.parent_hws = (const struct clk_hw*[]) {
3175				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3176			},
3177			.num_parents = 1,
3178			.flags = CLK_SET_RATE_PARENT,
3179			.ops = &clk_branch2_ops,
3180		},
3181	},
3182};
3183
3184static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3185	.halt_reg = 0x770b0,
3186	.halt_check = BRANCH_HALT_VOTED,
3187	.hwcg_reg = 0x770b0,
3188	.hwcg_bit = 1,
3189	.clkr = {
3190		.enable_reg = 0x770b0,
3191		.enable_mask = BIT(1),
3192		.hw.init = &(const struct clk_init_data) {
3193			.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
3194			.parent_hws = (const struct clk_hw*[]) {
3195				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3196			},
3197			.num_parents = 1,
3198			.flags = CLK_SET_RATE_PARENT,
3199			.ops = &clk_branch2_ops,
3200		},
3201	},
3202};
3203
3204static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3205	.halt_reg = 0x7702c,
3206	.halt_check = BRANCH_HALT_DELAY,
3207	.clkr = {
3208		.enable_reg = 0x7702c,
3209		.enable_mask = BIT(0),
3210		.hw.init = &(const struct clk_init_data) {
3211			.name = "gcc_ufs_phy_rx_symbol_0_clk",
3212			.parent_hws = (const struct clk_hw*[]) {
3213				&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
3214			},
3215			.num_parents = 1,
3216			.flags = CLK_SET_RATE_PARENT,
3217			.ops = &clk_branch2_ops,
3218		},
3219	},
3220};
3221
3222static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
3223	.halt_reg = 0x770cc,
3224	.halt_check = BRANCH_HALT_DELAY,
3225	.clkr = {
3226		.enable_reg = 0x770cc,
3227		.enable_mask = BIT(0),
3228		.hw.init = &(const struct clk_init_data) {
3229			.name = "gcc_ufs_phy_rx_symbol_1_clk",
3230			.parent_hws = (const struct clk_hw*[]) {
3231				&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
3232			},
3233			.num_parents = 1,
3234			.flags = CLK_SET_RATE_PARENT,
3235			.ops = &clk_branch2_ops,
3236		},
3237	},
3238};
3239
3240static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3241	.halt_reg = 0x77028,
3242	.halt_check = BRANCH_HALT_DELAY,
3243	.clkr = {
3244		.enable_reg = 0x77028,
3245		.enable_mask = BIT(0),
3246		.hw.init = &(const struct clk_init_data) {
3247			.name = "gcc_ufs_phy_tx_symbol_0_clk",
3248			.parent_hws = (const struct clk_hw*[]) {
3249				&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
3250			},
3251			.num_parents = 1,
3252			.flags = CLK_SET_RATE_PARENT,
3253			.ops = &clk_branch2_ops,
3254		},
3255	},
3256};
3257
3258static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3259	.halt_reg = 0x77068,
3260	.halt_check = BRANCH_HALT_VOTED,
3261	.hwcg_reg = 0x77068,
3262	.hwcg_bit = 1,
3263	.clkr = {
3264		.enable_reg = 0x77068,
3265		.enable_mask = BIT(0),
3266		.hw.init = &(const struct clk_init_data) {
3267			.name = "gcc_ufs_phy_unipro_core_clk",
3268			.parent_hws = (const struct clk_hw*[]) {
3269				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3270			},
3271			.num_parents = 1,
3272			.flags = CLK_SET_RATE_PARENT,
3273			.ops = &clk_branch2_ops,
3274		},
3275	},
3276};
3277
3278static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3279	.halt_reg = 0x77068,
3280	.halt_check = BRANCH_HALT_VOTED,
3281	.hwcg_reg = 0x77068,
3282	.hwcg_bit = 1,
3283	.clkr = {
3284		.enable_reg = 0x77068,
3285		.enable_mask = BIT(1),
3286		.hw.init = &(const struct clk_init_data) {
3287			.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3288			.parent_hws = (const struct clk_hw*[]) {
3289				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3290			},
3291			.num_parents = 1,
3292			.flags = CLK_SET_RATE_PARENT,
3293			.ops = &clk_branch2_ops,
3294		},
3295	},
3296};
3297
3298static struct clk_branch gcc_usb30_prim_master_clk = {
3299	.halt_reg = 0x39018,
3300	.halt_check = BRANCH_HALT,
3301	.clkr = {
3302		.enable_reg = 0x39018,
3303		.enable_mask = BIT(0),
3304		.hw.init = &(const struct clk_init_data) {
3305			.name = "gcc_usb30_prim_master_clk",
3306			.parent_hws = (const struct clk_hw*[]) {
3307				&gcc_usb30_prim_master_clk_src.clkr.hw,
3308			},
3309			.num_parents = 1,
3310			.flags = CLK_SET_RATE_PARENT,
3311			.ops = &clk_branch2_ops,
3312		},
3313	},
3314};
3315
3316static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3317	.halt_reg = 0x39028,
3318	.halt_check = BRANCH_HALT,
3319	.clkr = {
3320		.enable_reg = 0x39028,
3321		.enable_mask = BIT(0),
3322		.hw.init = &(const struct clk_init_data) {
3323			.name = "gcc_usb30_prim_mock_utmi_clk",
3324			.parent_hws = (const struct clk_hw*[]) {
3325				&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
3326			},
3327			.num_parents = 1,
3328			.flags = CLK_SET_RATE_PARENT,
3329			.ops = &clk_branch2_ops,
3330		},
3331	},
3332};
3333
3334static struct clk_branch gcc_usb30_prim_sleep_clk = {
3335	.halt_reg = 0x39024,
3336	.halt_check = BRANCH_HALT,
3337	.clkr = {
3338		.enable_reg = 0x39024,
3339		.enable_mask = BIT(0),
3340		.hw.init = &(const struct clk_init_data) {
3341			.name = "gcc_usb30_prim_sleep_clk",
3342			.ops = &clk_branch2_ops,
3343		},
3344	},
3345};
3346
3347static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3348	.halt_reg = 0x39060,
3349	.halt_check = BRANCH_HALT,
3350	.clkr = {
3351		.enable_reg = 0x39060,
3352		.enable_mask = BIT(0),
3353		.hw.init = &(const struct clk_init_data) {
3354			.name = "gcc_usb3_prim_phy_aux_clk",
3355			.parent_hws = (const struct clk_hw*[]) {
3356				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3357			},
3358			.num_parents = 1,
3359			.flags = CLK_SET_RATE_PARENT,
3360			.ops = &clk_branch2_ops,
3361		},
3362	},
3363};
3364
3365static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3366	.halt_reg = 0x39064,
3367	.halt_check = BRANCH_HALT,
3368	.clkr = {
3369		.enable_reg = 0x39064,
3370		.enable_mask = BIT(0),
3371		.hw.init = &(const struct clk_init_data) {
3372			.name = "gcc_usb3_prim_phy_com_aux_clk",
3373			.parent_hws = (const struct clk_hw*[]) {
3374				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3375			},
3376			.num_parents = 1,
3377			.flags = CLK_SET_RATE_PARENT,
3378			.ops = &clk_branch2_ops,
3379		},
3380	},
3381};
3382
3383static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3384	.halt_reg = 0x39068,
3385	.halt_check = BRANCH_HALT_DELAY,
3386	.hwcg_reg = 0x39068,
3387	.hwcg_bit = 1,
3388	.clkr = {
3389		.enable_reg = 0x39068,
3390		.enable_mask = BIT(0),
3391		.hw.init = &(const struct clk_init_data) {
3392			.name = "gcc_usb3_prim_phy_pipe_clk",
3393			.parent_hws = (const struct clk_hw*[]) {
3394				&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
3395			},
3396			.num_parents = 1,
3397			.flags = CLK_SET_RATE_PARENT,
3398			.ops = &clk_branch2_ops,
3399		},
3400	},
3401};
3402
3403static struct clk_branch gcc_video_axi0_clk = {
3404	.halt_reg = 0x32018,
3405	.halt_check = BRANCH_HALT_SKIP,
3406	.hwcg_reg = 0x32018,
3407	.hwcg_bit = 1,
3408	.clkr = {
3409		.enable_reg = 0x32018,
3410		.enable_mask = BIT(0),
3411		.hw.init = &(const struct clk_init_data) {
3412			.name = "gcc_video_axi0_clk",
3413			.ops = &clk_branch2_ops,
3414		},
3415	},
3416};
3417
3418static struct clk_branch gcc_video_axi1_clk = {
3419	.halt_reg = 0x32024,
3420	.halt_check = BRANCH_HALT_SKIP,
3421	.hwcg_reg = 0x32024,
3422	.hwcg_bit = 1,
3423	.clkr = {
3424		.enable_reg = 0x32024,
3425		.enable_mask = BIT(0),
3426		.hw.init = &(const struct clk_init_data) {
3427			.name = "gcc_video_axi1_clk",
3428			.ops = &clk_branch2_ops,
3429		},
3430	},
3431};
3432
3433static struct gdsc pcie_0_gdsc = {
3434	.gdscr = 0x6b004,
3435	.collapse_ctrl = 0x5214c,
3436	.collapse_mask = BIT(0),
3437	.pd = {
3438		.name = "pcie_0_gdsc",
3439	},
3440	.pwrsts = PWRSTS_RET_ON,
3441	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
3442};
3443
3444static struct gdsc pcie_0_phy_gdsc = {
3445	.gdscr = 0x6c000,
3446	.collapse_ctrl = 0x5214c,
3447	.collapse_mask = BIT(3),
3448	.pd = {
3449		.name = "pcie_0_phy_gdsc",
3450	},
3451	.pwrsts = PWRSTS_RET_ON,
3452	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
3453};
3454
3455static struct gdsc pcie_1_gdsc = {
3456	.gdscr = 0x8d004,
3457	.collapse_ctrl = 0x5214c,
3458	.collapse_mask = BIT(1),
3459	.pd = {
3460		.name = "pcie_1_gdsc",
3461	},
3462	.pwrsts = PWRSTS_RET_ON,
3463	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
3464};
3465
3466static struct gdsc pcie_1_phy_gdsc = {
3467	.gdscr = 0x8e000,
3468	.collapse_ctrl = 0x5214c,
3469	.collapse_mask = BIT(4),
3470	.pd = {
3471		.name = "pcie_1_phy_gdsc",
3472	},
3473	.pwrsts = PWRSTS_RET_ON,
3474	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
3475};
3476
3477static struct gdsc ufs_phy_gdsc = {
3478	.gdscr = 0x77004,
3479	.pd = {
3480		.name = "ufs_phy_gdsc",
3481	},
3482	.pwrsts = PWRSTS_OFF_ON,
3483	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3484};
3485
3486static struct gdsc ufs_mem_phy_gdsc = {
3487	.gdscr = 0x9e000,
3488	.pd = {
3489		.name = "ufs_mem_phy_gdsc",
3490	},
3491	.pwrsts = PWRSTS_OFF_ON,
3492	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3493};
3494
3495static struct gdsc usb30_prim_gdsc = {
3496	.gdscr = 0x39004,
3497	.pd = {
3498		.name = "usb30_prim_gdsc",
3499	},
3500	.pwrsts = PWRSTS_RET_ON,
3501	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3502};
3503
3504static struct gdsc usb3_phy_gdsc = {
3505	.gdscr = 0x50018,
3506	.pd = {
3507		.name = "usb3_phy_gdsc",
3508	},
3509	.pwrsts = PWRSTS_RET_ON,
3510	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3511};
3512
3513static struct clk_regmap *gcc_sm8650_clocks[] = {
3514	[GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr,
3515	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3516	[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3517	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3518	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3519	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3520	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3521	[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
3522	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3523	[GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr,
3524	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3525	[GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr,
3526	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3527	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3528	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3529	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3530	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3531	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3532	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3533	[GCC_GPLL0] = &gcc_gpll0.clkr,
3534	[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3535	[GCC_GPLL1] = &gcc_gpll1.clkr,
3536	[GCC_GPLL3] = &gcc_gpll3.clkr,
3537	[GCC_GPLL4] = &gcc_gpll4.clkr,
3538	[GCC_GPLL6] = &gcc_gpll6.clkr,
3539	[GCC_GPLL7] = &gcc_gpll7.clkr,
3540	[GCC_GPLL9] = &gcc_gpll9.clkr,
3541	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3542	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3543	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3544	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3545	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3546	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3547	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3548	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3549	[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
3550	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3551	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3552	[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3553	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3554	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3555	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3556	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3557	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3558	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3559	[GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr,
3560	[GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr,
3561	[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
3562	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3563	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3564	[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3565	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3566	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3567	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3568	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3569	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3570	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3571	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3572	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3573	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3574	[GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
3575	[GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
3576	[GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
3577	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3578	[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
3579	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3580	[GCC_QUPV3_I2C_CORE_CLK] = &gcc_qupv3_i2c_core_clk.clkr,
3581	[GCC_QUPV3_I2C_S0_CLK] = &gcc_qupv3_i2c_s0_clk.clkr,
3582	[GCC_QUPV3_I2C_S0_CLK_SRC] = &gcc_qupv3_i2c_s0_clk_src.clkr,
3583	[GCC_QUPV3_I2C_S1_CLK] = &gcc_qupv3_i2c_s1_clk.clkr,
3584	[GCC_QUPV3_I2C_S1_CLK_SRC] = &gcc_qupv3_i2c_s1_clk_src.clkr,
3585	[GCC_QUPV3_I2C_S2_CLK] = &gcc_qupv3_i2c_s2_clk.clkr,
3586	[GCC_QUPV3_I2C_S2_CLK_SRC] = &gcc_qupv3_i2c_s2_clk_src.clkr,
3587	[GCC_QUPV3_I2C_S3_CLK] = &gcc_qupv3_i2c_s3_clk.clkr,
3588	[GCC_QUPV3_I2C_S3_CLK_SRC] = &gcc_qupv3_i2c_s3_clk_src.clkr,
3589	[GCC_QUPV3_I2C_S4_CLK] = &gcc_qupv3_i2c_s4_clk.clkr,
3590	[GCC_QUPV3_I2C_S4_CLK_SRC] = &gcc_qupv3_i2c_s4_clk_src.clkr,
3591	[GCC_QUPV3_I2C_S5_CLK] = &gcc_qupv3_i2c_s5_clk.clkr,
3592	[GCC_QUPV3_I2C_S5_CLK_SRC] = &gcc_qupv3_i2c_s5_clk_src.clkr,
3593	[GCC_QUPV3_I2C_S6_CLK] = &gcc_qupv3_i2c_s6_clk.clkr,
3594	[GCC_QUPV3_I2C_S6_CLK_SRC] = &gcc_qupv3_i2c_s6_clk_src.clkr,
3595	[GCC_QUPV3_I2C_S7_CLK] = &gcc_qupv3_i2c_s7_clk.clkr,
3596	[GCC_QUPV3_I2C_S7_CLK_SRC] = &gcc_qupv3_i2c_s7_clk_src.clkr,
3597	[GCC_QUPV3_I2C_S8_CLK] = &gcc_qupv3_i2c_s8_clk.clkr,
3598	[GCC_QUPV3_I2C_S8_CLK_SRC] = &gcc_qupv3_i2c_s8_clk_src.clkr,
3599	[GCC_QUPV3_I2C_S9_CLK] = &gcc_qupv3_i2c_s9_clk.clkr,
3600	[GCC_QUPV3_I2C_S9_CLK_SRC] = &gcc_qupv3_i2c_s9_clk_src.clkr,
3601	[GCC_QUPV3_I2C_S_AHB_CLK] = &gcc_qupv3_i2c_s_ahb_clk.clkr,
3602	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3603	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3604	[GCC_QUPV3_WRAP1_QSPI_REF_CLK] = &gcc_qupv3_wrap1_qspi_ref_clk.clkr,
3605	[GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr,
3606	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3607	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3608	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3609	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3610	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3611	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3612	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3613	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3614	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3615	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3616	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3617	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3618	[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3619	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3620	[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3621	[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3622	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
3623	[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
3624	[GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC] = &gcc_qupv3_wrap2_ibi_ctrl_0_clk_src.clkr,
3625	[GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK] = &gcc_qupv3_wrap2_ibi_ctrl_2_clk.clkr,
3626	[GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK] = &gcc_qupv3_wrap2_ibi_ctrl_3_clk.clkr,
3627	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3628	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3629	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3630	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3631	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3632	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3633	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3634	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3635	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3636	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3637	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3638	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3639	[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
3640	[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
3641	[GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
3642	[GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
3643	[GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr,
3644	[GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr,
3645	[GCC_QUPV3_WRAP3_QSPI_REF_CLK] = &gcc_qupv3_wrap3_qspi_ref_clk.clkr,
3646	[GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr,
3647	[GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr,
3648	[GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr,
3649	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3650	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3651	[GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK] = &gcc_qupv3_wrap_2_ibi_2_ahb_clk.clkr,
3652	[GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK] = &gcc_qupv3_wrap_2_ibi_3_ahb_clk.clkr,
3653	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3654	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3655	[GCC_QUPV3_WRAP_3_M_AHB_CLK] = &gcc_qupv3_wrap_3_m_ahb_clk.clkr,
3656	[GCC_QUPV3_WRAP_3_S_AHB_CLK] = &gcc_qupv3_wrap_3_s_ahb_clk.clkr,
3657	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3658	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3659	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3660	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3661	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3662	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3663	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3664	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3665	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3666	[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3667	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3668	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3669	[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3670	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3671	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3672	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3673	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3674	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3675	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3676	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3677	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3678	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3679	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3680	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3681	[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3682	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3683	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3684	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3685	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3686	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3687	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3688	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3689	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3690	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3691	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3692	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3693	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3694	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3695	[GCC_GPLL0_AO] = &gcc_gpll0_ao.clkr,
3696	[GCC_GPLL0_OUT_EVEN_AO] = &gcc_gpll0_out_even_ao.clkr,
3697	[GCC_GPLL1_AO] = &gcc_gpll1_ao.clkr,
3698	[GCC_GPLL3_AO] = &gcc_gpll3_ao.clkr,
3699	[GCC_GPLL4_AO] = &gcc_gpll4_ao.clkr,
3700	[GCC_GPLL6_AO] = &gcc_gpll6_ao.clkr,
3701};
3702
3703static const struct qcom_reset_map gcc_sm8650_resets[] = {
3704	[GCC_CAMERA_BCR] = { 0x26000 },
3705	[GCC_DISPLAY_BCR] = { 0x27000 },
3706	[GCC_GPU_BCR] = { 0x71000 },
3707	[GCC_PCIE_0_BCR] = { 0x6b000 },
3708	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3709	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3710	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3711	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3712	[GCC_PCIE_1_BCR] = { 0x8d000 },
3713	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3714	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3715	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3716	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
3717	[GCC_PCIE_PHY_BCR] = { 0x6f000 },
3718	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3719	[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3720	[GCC_PDM_BCR] = { 0x33000 },
3721	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3722	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3723	[GCC_QUPV3_WRAPPER_3_BCR] = { 0x19000 },
3724	[GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 },
3725	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3726	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3727	[GCC_SDCC2_BCR] = { 0x14000 },
3728	[GCC_SDCC4_BCR] = { 0x16000 },
3729	[GCC_UFS_PHY_BCR] = { 0x77000 },
3730	[GCC_USB30_PRIM_BCR] = { 0x39000 },
3731	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3732	[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3733	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3734	[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3735	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3736	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3737	[GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 },
3738	[GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 },
3739	[GCC_VIDEO_BCR] = { 0x32000 },
3740};
3741
3742static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3743	DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src),
3744	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3745	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3746	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3747	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3748	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3749	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3750	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
3751	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
3752	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
3753	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
3754	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
3755	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
3756	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
3757	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
3758	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
3759	DEFINE_RCG_DFS(gcc_qupv3_wrap3_qspi_ref_clk_src),
3760};
3761
3762static struct gdsc *gcc_sm8650_gdscs[] = {
3763	[PCIE_0_GDSC] = &pcie_0_gdsc,
3764	[PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc,
3765	[PCIE_1_GDSC] = &pcie_1_gdsc,
3766	[PCIE_1_PHY_GDSC] = &pcie_1_phy_gdsc,
3767	[UFS_PHY_GDSC] = &ufs_phy_gdsc,
3768	[UFS_MEM_PHY_GDSC] = &ufs_mem_phy_gdsc,
3769	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3770	[USB3_PHY_GDSC] = &usb3_phy_gdsc,
3771};
3772
3773static const struct regmap_config gcc_sm8650_regmap_config = {
3774	.reg_bits = 32,
3775	.reg_stride = 4,
3776	.val_bits = 32,
3777	.max_register = 0x1f41f0,
3778	.fast_io = true,
3779};
3780
3781static const struct qcom_cc_desc gcc_sm8650_desc = {
3782	.config = &gcc_sm8650_regmap_config,
3783	.clks = gcc_sm8650_clocks,
3784	.num_clks = ARRAY_SIZE(gcc_sm8650_clocks),
3785	.resets = gcc_sm8650_resets,
3786	.num_resets = ARRAY_SIZE(gcc_sm8650_resets),
3787	.gdscs = gcc_sm8650_gdscs,
3788	.num_gdscs = ARRAY_SIZE(gcc_sm8650_gdscs),
3789};
3790
3791static const struct of_device_id gcc_sm8650_match_table[] = {
3792	{ .compatible = "qcom,sm8650-gcc" },
3793	{ }
3794};
3795MODULE_DEVICE_TABLE(of, gcc_sm8650_match_table);
3796
3797static int gcc_sm8650_probe(struct platform_device *pdev)
3798{
3799	struct regmap *regmap;
3800	int ret;
3801
3802	regmap = qcom_cc_map(pdev, &gcc_sm8650_desc);
3803	if (IS_ERR(regmap))
3804		return PTR_ERR(regmap);
3805
3806	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3807				       ARRAY_SIZE(gcc_dfs_clocks));
3808	if (ret)
3809		return ret;
3810
3811	/* Keep some clocks always-on */
3812	qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */
3813	qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */
3814	qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */
3815	qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */
3816	qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
3817	qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */
3818	qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */
3819
3820	/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks  */
3821	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
3822	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
3823
3824	/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
3825	regmap_write(regmap, 0x52150, 0x0);
3826
3827	return qcom_cc_really_probe(&pdev->dev, &gcc_sm8650_desc, regmap);
3828}
3829
3830static struct platform_driver gcc_sm8650_driver = {
3831	.probe = gcc_sm8650_probe,
3832	.driver = {
3833		.name = "gcc-sm8650",
3834		.of_match_table = gcc_sm8650_match_table,
3835	},
3836};
3837
3838static int __init gcc_sm8650_init(void)
3839{
3840	return platform_driver_register(&gcc_sm8650_driver);
3841}
3842subsys_initcall(gcc_sm8650_init);
3843
3844static void __exit gcc_sm8650_exit(void)
3845{
3846	platform_driver_unregister(&gcc_sm8650_driver);
3847}
3848module_exit(gcc_sm8650_exit);
3849
3850MODULE_DESCRIPTION("QTI GCC SM8650 Driver");
3851MODULE_LICENSE("GPL");