gcc-sm8450.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2021, Linaro Limited
   5 */
   6
   7#include <linux/clk-provider.h>
   8#include <linux/module.h>
   9#include <linux/of.h>
  10#include <linux/platform_device.h>
  11#include <linux/regmap.h>
  12
  13#include <dt-bindings/clock/qcom,gcc-sm8450.h>
  14
  15#include "clk-alpha-pll.h"
  16#include "clk-branch.h"
  17#include "clk-rcg.h"
  18#include "clk-regmap.h"
  19#include "clk-regmap-divider.h"
  20#include "clk-regmap-mux.h"
  21#include "clk-regmap-phy-mux.h"
  22#include "gdsc.h"
  23#include "reset.h"
  24
  25enum {
  26	P_BI_TCXO,
  27	P_GCC_GPLL0_OUT_EVEN,
  28	P_GCC_GPLL0_OUT_MAIN,
  29	P_SM8475_GCC_GPLL2_OUT_EVEN,
  30	P_SM8475_GCC_GPLL3_OUT_EVEN,
  31	P_GCC_GPLL4_OUT_MAIN,
  32	P_GCC_GPLL9_OUT_MAIN,
  33	P_PCIE_1_PHY_AUX_CLK,
  34	P_SLEEP_CLK,
  35	P_UFS_PHY_RX_SYMBOL_0_CLK,
  36	P_UFS_PHY_RX_SYMBOL_1_CLK,
  37	P_UFS_PHY_TX_SYMBOL_0_CLK,
  38	P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
  39};
  40
  41static struct clk_init_data sm8475_gcc_gpll0_init = {
  42	.name = "gcc_gpll0",
  43	.parent_data = &(const struct clk_parent_data){
  44		.fw_name = "bi_tcxo",
  45	},
  46	.num_parents = 1,
  47	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
  48};
  49
  50static struct clk_alpha_pll gcc_gpll0 = {
  51	.offset = 0x0,
  52	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  53	.clkr = {
  54		.enable_reg = 0x62018,
  55		.enable_mask = BIT(0),
  56		.hw.init = &(struct clk_init_data){
  57			.name = "gcc_gpll0",
  58			.parent_data = &(const struct clk_parent_data){
  59				.fw_name = "bi_tcxo",
  60			},
  61			.num_parents = 1,
  62			.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
  63		},
  64	},
  65};
  66
  67static struct clk_init_data sm8475_gcc_gpll0_out_even_init = {
  68	.name = "gcc_gpll0_out_even",
  69	.parent_hws = (const struct clk_hw*[]) {
  70		&gcc_gpll0.clkr.hw,
  71	},
  72	.num_parents = 1,
  73	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
  74};
  75
  76static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
  77	{ 0x1, 2 },
  78	{ }
  79};
  80
  81static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
  82	.offset = 0x0,
  83	.post_div_shift = 10,
  84	.post_div_table = post_div_table_gcc_gpll0_out_even,
  85	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
  86	.width = 4,
  87	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  88	.clkr.hw.init = &(struct clk_init_data){
  89		.name = "gcc_gpll0_out_even",
  90		.parent_hws = (const struct clk_hw*[]) {
  91			&gcc_gpll0.clkr.hw,
  92		},
  93		.num_parents = 1,
  94		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
  95	},
  96};
  97
  98static struct clk_alpha_pll sm8475_gcc_gpll2 = {
  99	.offset = 0x2000,
 100	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 101	.clkr = {
 102		.enable_reg = 0x62018,
 103		.enable_mask = BIT(2),
 104		.hw.init = &(struct clk_init_data){
 105			.name = "gcc_gpll2",
 106			.parent_data = &(const struct clk_parent_data){
 107				.fw_name = "bi_tcxo",
 108			},
 109			.num_parents = 1,
 110			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 111		},
 112	},
 113};
 114
 115static struct clk_alpha_pll sm8475_gcc_gpll3 = {
 116	.offset = 0x3000,
 117	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 118	.clkr = {
 119		.enable_reg = 0x62018,
 120		.enable_mask = BIT(3),
 121		.hw.init = &(struct clk_init_data){
 122			.name = "gcc_gpll3",
 123			.parent_data = &(const struct clk_parent_data){
 124				.fw_name = "bi_tcxo",
 125			},
 126			.num_parents = 1,
 127			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 128		},
 129	},
 130};
 131
 132static struct clk_init_data sm8475_gcc_gpll4_init = {
 133	.name = "gcc_gpll4",
 134	.parent_data = &(const struct clk_parent_data){
 135		.fw_name = "bi_tcxo",
 136	},
 137	.num_parents = 1,
 138	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 139};
 140
 141static struct clk_alpha_pll gcc_gpll4 = {
 142	.offset = 0x4000,
 143	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 144	.clkr = {
 145		.enable_reg = 0x62018,
 146		.enable_mask = BIT(4),
 147		.hw.init = &(struct clk_init_data){
 148			.name = "gcc_gpll4",
 149			.parent_data = &(const struct clk_parent_data){
 150				.fw_name = "bi_tcxo",
 151			},
 152			.num_parents = 1,
 153			.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
 154		},
 155	},
 156};
 157
 158static struct clk_init_data sm8475_gcc_gpll9_init = {
 159	.name = "gcc_gpll9",
 160	.parent_data = &(const struct clk_parent_data){
 161		.fw_name = "bi_tcxo",
 162	},
 163	.num_parents = 1,
 164	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 165};
 166
 167static struct clk_alpha_pll gcc_gpll9 = {
 168	.offset = 0x9000,
 169	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 170	.clkr = {
 171		.enable_reg = 0x62018,
 172		.enable_mask = BIT(9),
 173		.hw.init = &(struct clk_init_data){
 174			.name = "gcc_gpll9",
 175			.parent_data = &(const struct clk_parent_data){
 176				.fw_name = "bi_tcxo",
 177			},
 178			.num_parents = 1,
 179			.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
 180		},
 181	},
 182};
 183
 184static const struct parent_map gcc_parent_map_0[] = {
 185	{ P_BI_TCXO, 0 },
 186	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 187	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 188};
 189
 190static const struct clk_parent_data gcc_parent_data_0[] = {
 191	{ .fw_name = "bi_tcxo" },
 192	{ .hw = &gcc_gpll0.clkr.hw },
 193	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 194};
 195
 196static const struct parent_map gcc_parent_map_1[] = {
 197	{ P_BI_TCXO, 0 },
 198	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 199	{ P_SLEEP_CLK, 5 },
 200	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 201};
 202
 203static const struct clk_parent_data gcc_parent_data_1[] = {
 204	{ .fw_name = "bi_tcxo" },
 205	{ .hw = &gcc_gpll0.clkr.hw },
 206	{ .fw_name = "sleep_clk" },
 207	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 208};
 209
 210static const struct parent_map gcc_parent_map_2[] = {
 211	{ P_BI_TCXO, 0 },
 212	{ P_SLEEP_CLK, 5 },
 213};
 214
 215static const struct clk_parent_data gcc_parent_data_2[] = {
 216	{ .fw_name = "bi_tcxo" },
 217	{ .fw_name = "sleep_clk" },
 218};
 219
 220static const struct parent_map gcc_parent_map_3[] = {
 221	{ P_BI_TCXO, 0 },
 222};
 223
 224static const struct clk_parent_data gcc_parent_data_3[] = {
 225	{ .fw_name = "bi_tcxo" },
 226};
 227
 228static const struct parent_map sm8475_gcc_parent_map_3[] = {
 229	{ P_BI_TCXO, 0 },
 230	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 231	{ P_SM8475_GCC_GPLL2_OUT_EVEN, 2 },
 232	{ P_SM8475_GCC_GPLL3_OUT_EVEN, 3 },
 233	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 234};
 235
 236static const struct clk_parent_data sm8475_gcc_parent_data_3[] = {
 237	{ .fw_name = "bi_tcxo" },
 238	{ .hw = &gcc_gpll0.clkr.hw },
 239	{ .hw = &sm8475_gcc_gpll2.clkr.hw },
 240	{ .hw = &sm8475_gcc_gpll3.clkr.hw },
 241	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 242};
 243
 244static const struct parent_map gcc_parent_map_5[] = {
 245	{ P_PCIE_1_PHY_AUX_CLK, 0 },
 246	{ P_BI_TCXO, 2 },
 247};
 248
 249static const struct clk_parent_data gcc_parent_data_5[] = {
 250	{ .fw_name = "pcie_1_phy_aux_clk" },
 251	{ .fw_name = "bi_tcxo" },
 252};
 253
 254static const struct parent_map gcc_parent_map_7[] = {
 255	{ P_BI_TCXO, 0 },
 256	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 257	{ P_GCC_GPLL9_OUT_MAIN, 2 },
 258	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 259	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 260};
 261
 262static const struct clk_parent_data gcc_parent_data_7[] = {
 263	{ .fw_name = "bi_tcxo" },
 264	{ .hw = &gcc_gpll0.clkr.hw },
 265	{ .hw = &gcc_gpll9.clkr.hw },
 266	{ .hw = &gcc_gpll4.clkr.hw },
 267	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 268};
 269
 270static const struct parent_map gcc_parent_map_8[] = {
 271	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
 272	{ P_BI_TCXO, 2 },
 273};
 274
 275static const struct clk_parent_data gcc_parent_data_8[] = {
 276	{ .fw_name = "ufs_phy_rx_symbol_0_clk" },
 277	{ .fw_name = "bi_tcxo" },
 278};
 279
 280static const struct parent_map gcc_parent_map_9[] = {
 281	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
 282	{ P_BI_TCXO, 2 },
 283};
 284
 285static const struct clk_parent_data gcc_parent_data_9[] = {
 286	{ .fw_name = "ufs_phy_rx_symbol_1_clk" },
 287	{ .fw_name = "bi_tcxo" },
 288};
 289
 290static const struct parent_map gcc_parent_map_10[] = {
 291	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
 292	{ P_BI_TCXO, 2 },
 293};
 294
 295static const struct clk_parent_data gcc_parent_data_10[] = {
 296	{ .fw_name = "ufs_phy_tx_symbol_0_clk" },
 297	{ .fw_name = "bi_tcxo" },
 298};
 299
 300static const struct parent_map gcc_parent_map_11[] = {
 301	{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 302	{ P_BI_TCXO, 2 },
 303};
 304
 305static const struct clk_parent_data gcc_parent_data_11[] = {
 306	{ .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
 307	{ .fw_name = "bi_tcxo" },
 308};
 309
 310static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
 311	.reg = 0x7b060,
 312	.clkr = {
 313		.hw.init = &(struct clk_init_data){
 314			.name = "gcc_pcie_0_pipe_clk_src",
 315			.parent_data = &(const struct clk_parent_data){
 316				.fw_name = "pcie_0_pipe_clk",
 317			},
 318			.num_parents = 1,
 319			.ops = &clk_regmap_phy_mux_ops,
 320		},
 321	},
 322};
 323
 324static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
 325	.reg = 0x9d080,
 326	.shift = 0,
 327	.width = 2,
 328	.parent_map = gcc_parent_map_5,
 329	.clkr = {
 330		.hw.init = &(struct clk_init_data){
 331			.name = "gcc_pcie_1_phy_aux_clk_src",
 332			.parent_data = gcc_parent_data_5,
 333			.num_parents = ARRAY_SIZE(gcc_parent_data_5),
 334			.ops = &clk_regmap_mux_closest_ops,
 335		},
 336	},
 337};
 338
 339static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
 340	.reg = 0x9d064,
 341	.clkr = {
 342		.hw.init = &(struct clk_init_data){
 343			.name = "gcc_pcie_1_pipe_clk_src",
 344			.parent_data = &(const struct clk_parent_data){
 345				.fw_name = "pcie_1_pipe_clk",
 346			},
 347			.num_parents = 1,
 348			.ops = &clk_regmap_phy_mux_ops,
 349		},
 350	},
 351};
 352
 353static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
 354	.reg = 0x87060,
 355	.shift = 0,
 356	.width = 2,
 357	.parent_map = gcc_parent_map_8,
 358	.clkr = {
 359		.hw.init = &(struct clk_init_data){
 360			.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
 361			.parent_data = gcc_parent_data_8,
 362			.num_parents = ARRAY_SIZE(gcc_parent_data_8),
 363			.ops = &clk_regmap_mux_closest_ops,
 364		},
 365	},
 366};
 367
 368static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
 369	.reg = 0x870d0,
 370	.shift = 0,
 371	.width = 2,
 372	.parent_map = gcc_parent_map_9,
 373	.clkr = {
 374		.hw.init = &(struct clk_init_data){
 375			.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
 376			.parent_data = gcc_parent_data_9,
 377			.num_parents = ARRAY_SIZE(gcc_parent_data_9),
 378			.ops = &clk_regmap_mux_closest_ops,
 379		},
 380	},
 381};
 382
 383static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
 384	.reg = 0x87050,
 385	.shift = 0,
 386	.width = 2,
 387	.parent_map = gcc_parent_map_10,
 388	.clkr = {
 389		.hw.init = &(struct clk_init_data){
 390			.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
 391			.parent_data = gcc_parent_data_10,
 392			.num_parents = ARRAY_SIZE(gcc_parent_data_10),
 393			.ops = &clk_regmap_mux_closest_ops,
 394		},
 395	},
 396};
 397
 398static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
 399	.reg = 0x49068,
 400	.shift = 0,
 401	.width = 2,
 402	.parent_map = gcc_parent_map_11,
 403	.clkr = {
 404		.hw.init = &(struct clk_init_data){
 405			.name = "gcc_usb3_prim_phy_pipe_clk_src",
 406			.parent_data = gcc_parent_data_11,
 407			.num_parents = ARRAY_SIZE(gcc_parent_data_11),
 408			.ops = &clk_regmap_mux_closest_ops,
 409		},
 410	},
 411};
 412
 413static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 414	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 415	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 416	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
 417	{ }
 418};
 419
 420static struct clk_rcg2 gcc_gp1_clk_src = {
 421	.cmd_rcgr = 0x74004,
 422	.mnd_width = 8,
 423	.hid_width = 5,
 424	.parent_map = gcc_parent_map_1,
 425	.freq_tbl = ftbl_gcc_gp1_clk_src,
 426	.hw_clk_ctrl = true,
 427	.clkr.hw.init = &(struct clk_init_data){
 428		.name = "gcc_gp1_clk_src",
 429		.parent_data = gcc_parent_data_1,
 430		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 431		.flags = CLK_SET_RATE_PARENT,
 432		.ops = &clk_rcg2_ops,
 433	},
 434};
 435
 436static struct clk_rcg2 gcc_gp2_clk_src = {
 437	.cmd_rcgr = 0x75004,
 438	.mnd_width = 8,
 439	.hid_width = 5,
 440	.parent_map = gcc_parent_map_1,
 441	.freq_tbl = ftbl_gcc_gp1_clk_src,
 442	.hw_clk_ctrl = true,
 443	.clkr.hw.init = &(struct clk_init_data){
 444		.name = "gcc_gp2_clk_src",
 445		.parent_data = gcc_parent_data_1,
 446		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 447		.flags = CLK_SET_RATE_PARENT,
 448		.ops = &clk_rcg2_ops,
 449	},
 450};
 451
 452static struct clk_rcg2 gcc_gp3_clk_src = {
 453	.cmd_rcgr = 0x76004,
 454	.mnd_width = 8,
 455	.hid_width = 5,
 456	.parent_map = gcc_parent_map_1,
 457	.freq_tbl = ftbl_gcc_gp1_clk_src,
 458	.hw_clk_ctrl = true,
 459	.clkr.hw.init = &(struct clk_init_data){
 460		.name = "gcc_gp3_clk_src",
 461		.parent_data = gcc_parent_data_1,
 462		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 463		.flags = CLK_SET_RATE_PARENT,
 464		.ops = &clk_rcg2_ops,
 465	},
 466};
 467
 468static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 469	F(19200000, P_BI_TCXO, 1, 0, 0),
 470	{ }
 471};
 472
 473static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 474	.cmd_rcgr = 0x7b064,
 475	.mnd_width = 16,
 476	.hid_width = 5,
 477	.parent_map = gcc_parent_map_2,
 478	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 479	.hw_clk_ctrl = true,
 480	.clkr.hw.init = &(struct clk_init_data){
 481		.name = "gcc_pcie_0_aux_clk_src",
 482		.parent_data = gcc_parent_data_2,
 483		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 484		.flags = CLK_SET_RATE_PARENT,
 485		.ops = &clk_rcg2_ops,
 486	},
 487};
 488
 489static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
 490	F(19200000, P_BI_TCXO, 1, 0, 0),
 491	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 492	{ }
 493};
 494
 495static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
 496	.cmd_rcgr = 0x7b048,
 497	.mnd_width = 0,
 498	.hid_width = 5,
 499	.parent_map = gcc_parent_map_0,
 500	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 501	.hw_clk_ctrl = true,
 502	.clkr.hw.init = &(struct clk_init_data){
 503		.name = "gcc_pcie_0_phy_rchng_clk_src",
 504		.parent_data = gcc_parent_data_0,
 505		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 506		.flags = CLK_SET_RATE_PARENT,
 507		.ops = &clk_rcg2_ops,
 508	},
 509};
 510
 511static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 512	.cmd_rcgr = 0x9d068,
 513	.mnd_width = 16,
 514	.hid_width = 5,
 515	.parent_map = gcc_parent_map_2,
 516	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 517	.hw_clk_ctrl = true,
 518	.clkr.hw.init = &(struct clk_init_data){
 519		.name = "gcc_pcie_1_aux_clk_src",
 520		.parent_data = gcc_parent_data_2,
 521		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 522		.flags = CLK_SET_RATE_PARENT,
 523		.ops = &clk_rcg2_ops,
 524	},
 525};
 526
 527static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
 528	.cmd_rcgr = 0x9d04c,
 529	.mnd_width = 0,
 530	.hid_width = 5,
 531	.parent_map = gcc_parent_map_0,
 532	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 533	.hw_clk_ctrl = true,
 534	.clkr.hw.init = &(struct clk_init_data){
 535		.name = "gcc_pcie_1_phy_rchng_clk_src",
 536		.parent_data = gcc_parent_data_0,
 537		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 538		.flags = CLK_SET_RATE_PARENT,
 539		.ops = &clk_rcg2_ops,
 540	},
 541};
 542
 543static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 544	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
 545	{ }
 546};
 547
 548static struct clk_rcg2 gcc_pdm2_clk_src = {
 549	.cmd_rcgr = 0x43010,
 550	.mnd_width = 0,
 551	.hid_width = 5,
 552	.parent_map = gcc_parent_map_0,
 553	.freq_tbl = ftbl_gcc_pdm2_clk_src,
 554	.hw_clk_ctrl = true,
 555	.clkr.hw.init = &(struct clk_init_data){
 556		.name = "gcc_pdm2_clk_src",
 557		.parent_data = gcc_parent_data_0,
 558		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 559		.flags = CLK_SET_RATE_PARENT,
 560		.ops = &clk_rcg2_ops,
 561	},
 562};
 563
 564static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 565	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 566	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 567	F(19200000, P_BI_TCXO, 1, 0, 0),
 568	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 569	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 570	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 571	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 572	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 573	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 574	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 575	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 576	{ }
 577};
 578
 579static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 580	.name = "gcc_qupv3_wrap0_s0_clk_src",
 581	.parent_data = gcc_parent_data_0,
 582	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 583	.flags = CLK_SET_RATE_PARENT,
 584	.ops = &clk_rcg2_ops,
 585};
 586
 587static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 588	.cmd_rcgr = 0x27014,
 589	.mnd_width = 16,
 590	.hid_width = 5,
 591	.parent_map = gcc_parent_map_0,
 592	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 593	.hw_clk_ctrl = true,
 594	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 595};
 596
 597static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 598	.name = "gcc_qupv3_wrap0_s1_clk_src",
 599	.parent_data = gcc_parent_data_0,
 600	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 601	.flags = CLK_SET_RATE_PARENT,
 602	.ops = &clk_rcg2_ops,
 603};
 604
 605static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 606	.cmd_rcgr = 0x27148,
 607	.mnd_width = 16,
 608	.hid_width = 5,
 609	.parent_map = gcc_parent_map_0,
 610	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 611	.hw_clk_ctrl = true,
 612	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 613};
 614
 615static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 616	.name = "gcc_qupv3_wrap0_s2_clk_src",
 617	.parent_data = gcc_parent_data_0,
 618	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 619	.flags = CLK_SET_RATE_PARENT,
 620	.ops = &clk_rcg2_ops,
 621};
 622
 623static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 624	.cmd_rcgr = 0x2727c,
 625	.mnd_width = 16,
 626	.hid_width = 5,
 627	.parent_map = gcc_parent_map_0,
 628	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 629	.hw_clk_ctrl = true,
 630	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 631};
 632
 633static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 634	.name = "gcc_qupv3_wrap0_s3_clk_src",
 635	.parent_data = gcc_parent_data_0,
 636	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 637	.flags = CLK_SET_RATE_PARENT,
 638	.ops = &clk_rcg2_ops,
 639};
 640
 641static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 642	.cmd_rcgr = 0x273b0,
 643	.mnd_width = 16,
 644	.hid_width = 5,
 645	.parent_map = gcc_parent_map_0,
 646	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 647	.hw_clk_ctrl = true,
 648	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 649};
 650
 651static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 652	.name = "gcc_qupv3_wrap0_s4_clk_src",
 653	.parent_data = gcc_parent_data_0,
 654	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 655	.flags = CLK_SET_RATE_PARENT,
 656	.ops = &clk_rcg2_ops,
 657};
 658
 659static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 660	.cmd_rcgr = 0x274e4,
 661	.mnd_width = 16,
 662	.hid_width = 5,
 663	.parent_map = gcc_parent_map_0,
 664	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 665	.hw_clk_ctrl = true,
 666	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 667};
 668
 669static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = {
 670	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 671	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 672	F(19200000, P_BI_TCXO, 1, 0, 0),
 673	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 674	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 675	F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
 676	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 677	F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
 678	{ }
 679};
 680
 681static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 682	.name = "gcc_qupv3_wrap0_s5_clk_src",
 683	.parent_data = gcc_parent_data_0,
 684	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 685	.flags = CLK_SET_RATE_PARENT,
 686	.ops = &clk_rcg2_ops,
 687};
 688
 689static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 690	.cmd_rcgr = 0x27618,
 691	.mnd_width = 16,
 692	.hid_width = 5,
 693	.parent_map = gcc_parent_map_0,
 694	.freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src,
 695	.hw_clk_ctrl = true,
 696	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 697};
 698
 699static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
 700	.name = "gcc_qupv3_wrap0_s6_clk_src",
 701	.parent_data = gcc_parent_data_0,
 702	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 703	.flags = CLK_SET_RATE_PARENT,
 704	.ops = &clk_rcg2_ops,
 705};
 706
 707static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
 708	.cmd_rcgr = 0x2774c,
 709	.mnd_width = 16,
 710	.hid_width = 5,
 711	.parent_map = gcc_parent_map_0,
 712	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 713	.hw_clk_ctrl = true,
 714	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
 715};
 716
 717static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
 718	.name = "gcc_qupv3_wrap0_s7_clk_src",
 719	.parent_data = gcc_parent_data_0,
 720	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 721	.flags = CLK_SET_RATE_PARENT,
 722	.ops = &clk_rcg2_ops,
 723};
 724
 725static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
 726	.cmd_rcgr = 0x27880,
 727	.mnd_width = 16,
 728	.hid_width = 5,
 729	.parent_map = gcc_parent_map_0,
 730	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 731	.hw_clk_ctrl = true,
 732	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
 733};
 734
 735static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
 736	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 737	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 738	F(19200000, P_BI_TCXO, 1, 0, 0),
 739	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 740	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 741	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 742	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 743	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 744	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 745	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 746	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 747	F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
 748	F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
 749	F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
 750	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
 751	{ }
 752};
 753
 754static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 755	.name = "gcc_qupv3_wrap1_s0_clk_src",
 756	.parent_data = gcc_parent_data_0,
 757	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 758	.flags = CLK_SET_RATE_PARENT,
 759	.ops = &clk_rcg2_ops,
 760};
 761
 762static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 763	.cmd_rcgr = 0x28014,
 764	.mnd_width = 16,
 765	.hid_width = 5,
 766	.parent_map = gcc_parent_map_0,
 767	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 768	.hw_clk_ctrl = true,
 769	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 770};
 771
 772static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 773	.name = "gcc_qupv3_wrap1_s1_clk_src",
 774	.parent_data = gcc_parent_data_0,
 775	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 776	.flags = CLK_SET_RATE_PARENT,
 777	.ops = &clk_rcg2_ops,
 778};
 779
 780static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 781	.cmd_rcgr = 0x28148,
 782	.mnd_width = 16,
 783	.hid_width = 5,
 784	.parent_map = gcc_parent_map_0,
 785	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 786	.hw_clk_ctrl = true,
 787	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 788};
 789
 790static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
 791	.name = "gcc_qupv3_wrap1_s2_clk_src",
 792	.parent_data = gcc_parent_data_0,
 793	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 794	.flags = CLK_SET_RATE_PARENT,
 795	.ops = &clk_rcg2_ops,
 796};
 797
 798static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 799	.cmd_rcgr = 0x2827c,
 800	.mnd_width = 16,
 801	.hid_width = 5,
 802	.parent_map = gcc_parent_map_0,
 803	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 804	.hw_clk_ctrl = true,
 805	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
 806};
 807
 808static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 809	.name = "gcc_qupv3_wrap1_s3_clk_src",
 810	.parent_data = gcc_parent_data_0,
 811	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 812	.flags = CLK_SET_RATE_PARENT,
 813	.ops = &clk_rcg2_ops,
 814};
 815
 816static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 817	.cmd_rcgr = 0x283b0,
 818	.mnd_width = 16,
 819	.hid_width = 5,
 820	.parent_map = gcc_parent_map_0,
 821	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 822	.hw_clk_ctrl = true,
 823	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 824};
 825
 826static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 827	.name = "gcc_qupv3_wrap1_s4_clk_src",
 828	.parent_data = gcc_parent_data_0,
 829	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 830	.flags = CLK_SET_RATE_PARENT,
 831	.ops = &clk_rcg2_ops,
 832};
 833
 834static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 835	.cmd_rcgr = 0x284e4,
 836	.mnd_width = 16,
 837	.hid_width = 5,
 838	.parent_map = gcc_parent_map_0,
 839	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 840	.hw_clk_ctrl = true,
 841	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 842};
 843
 844static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 845	.name = "gcc_qupv3_wrap1_s5_clk_src",
 846	.parent_data = gcc_parent_data_0,
 847	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 848	.flags = CLK_SET_RATE_PARENT,
 849	.ops = &clk_rcg2_ops,
 850};
 851
 852static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 853	.cmd_rcgr = 0x28618,
 854	.mnd_width = 16,
 855	.hid_width = 5,
 856	.parent_map = gcc_parent_map_0,
 857	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 858	.hw_clk_ctrl = true,
 859	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 860};
 861
 862static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
 863	.name = "gcc_qupv3_wrap1_s6_clk_src",
 864	.parent_data = gcc_parent_data_0,
 865	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 866	.flags = CLK_SET_RATE_PARENT,
 867	.ops = &clk_rcg2_ops,
 868};
 869
 870static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
 871	.cmd_rcgr = 0x2874c,
 872	.mnd_width = 16,
 873	.hid_width = 5,
 874	.parent_map = gcc_parent_map_0,
 875	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 876	.hw_clk_ctrl = true,
 877	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
 878};
 879
 880static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
 881	.name = "gcc_qupv3_wrap2_s0_clk_src",
 882	.parent_data = gcc_parent_data_0,
 883	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 884	.flags = CLK_SET_RATE_PARENT,
 885	.ops = &clk_rcg2_ops,
 886};
 887
 888static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
 889	.cmd_rcgr = 0x2e014,
 890	.mnd_width = 16,
 891	.hid_width = 5,
 892	.parent_map = gcc_parent_map_0,
 893	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 894	.hw_clk_ctrl = true,
 895	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
 896};
 897
 898static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
 899	.name = "gcc_qupv3_wrap2_s1_clk_src",
 900	.parent_data = gcc_parent_data_0,
 901	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 902	.flags = CLK_SET_RATE_PARENT,
 903	.ops = &clk_rcg2_ops,
 904};
 905
 906static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
 907	.cmd_rcgr = 0x2e148,
 908	.mnd_width = 16,
 909	.hid_width = 5,
 910	.parent_map = gcc_parent_map_0,
 911	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 912	.hw_clk_ctrl = true,
 913	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
 914};
 915
 916static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
 917	.name = "gcc_qupv3_wrap2_s2_clk_src",
 918	.parent_data = gcc_parent_data_0,
 919	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 920	.flags = CLK_SET_RATE_PARENT,
 921	.ops = &clk_rcg2_ops,
 922};
 923
 924static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
 925	.cmd_rcgr = 0x2e27c,
 926	.mnd_width = 16,
 927	.hid_width = 5,
 928	.parent_map = gcc_parent_map_0,
 929	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 930	.hw_clk_ctrl = true,
 931	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
 932};
 933
 934static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
 935	.name = "gcc_qupv3_wrap2_s3_clk_src",
 936	.parent_data = gcc_parent_data_0,
 937	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 938	.flags = CLK_SET_RATE_PARENT,
 939	.ops = &clk_rcg2_ops,
 940};
 941
 942static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
 943	.cmd_rcgr = 0x2e3b0,
 944	.mnd_width = 16,
 945	.hid_width = 5,
 946	.parent_map = gcc_parent_map_0,
 947	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 948	.hw_clk_ctrl = true,
 949	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
 950};
 951
 952static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
 953	.name = "gcc_qupv3_wrap2_s4_clk_src",
 954	.parent_data = gcc_parent_data_0,
 955	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 956	.flags = CLK_SET_RATE_PARENT,
 957	.ops = &clk_rcg2_ops,
 958};
 959
 960static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
 961	.cmd_rcgr = 0x2e4e4,
 962	.mnd_width = 16,
 963	.hid_width = 5,
 964	.parent_map = gcc_parent_map_0,
 965	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 966	.hw_clk_ctrl = true,
 967	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
 968};
 969
 970static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
 971	.name = "gcc_qupv3_wrap2_s5_clk_src",
 972	.parent_data = gcc_parent_data_0,
 973	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 974	.flags = CLK_SET_RATE_PARENT,
 975	.ops = &clk_rcg2_ops,
 976};
 977
 978static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
 979	.cmd_rcgr = 0x2e618,
 980	.mnd_width = 16,
 981	.hid_width = 5,
 982	.parent_map = gcc_parent_map_0,
 983	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 984	.hw_clk_ctrl = true,
 985	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
 986};
 987
 988static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
 989	.name = "gcc_qupv3_wrap2_s6_clk_src",
 990	.parent_data = gcc_parent_data_0,
 991	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 992	.flags = CLK_SET_RATE_PARENT,
 993	.ops = &clk_rcg2_ops,
 994};
 995
 996static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
 997	.cmd_rcgr = 0x2e74c,
 998	.mnd_width = 16,
 999	.hid_width = 5,
1000	.parent_map = gcc_parent_map_0,
1001	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1002	.hw_clk_ctrl = true,
1003	.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
1004};
1005
1006static const struct freq_tbl sm8475_ftbl_gcc_sdcc2_apps_clk_src[] = {
1007	F(400000, P_BI_TCXO, 12, 1, 4),
1008	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1009	F(37000000, P_GCC_GPLL9_OUT_MAIN, 16, 0, 0),
1010	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1011	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1012	F(148000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1013	{ }
1014};
1015
1016static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1017	F(400000, P_BI_TCXO, 12, 1, 4),
1018	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1019	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1020	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1021	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1022	{ }
1023};
1024
1025static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1026	.cmd_rcgr = 0x24014,
1027	.mnd_width = 8,
1028	.hid_width = 5,
1029	.parent_map = gcc_parent_map_7,
1030	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1031	.hw_clk_ctrl = true,
1032	.clkr.hw.init = &(struct clk_init_data){
1033		.name = "gcc_sdcc2_apps_clk_src",
1034		.parent_data = gcc_parent_data_7,
1035		.num_parents = ARRAY_SIZE(gcc_parent_data_7),
1036		.flags = CLK_SET_RATE_PARENT,
1037		.ops = &clk_rcg2_shared_floor_ops,
1038	},
1039};
1040
1041static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
1042	F(400000, P_BI_TCXO, 12, 1, 4),
1043	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1044	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1045	{ }
1046};
1047
1048static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
1049	.cmd_rcgr = 0x26014,
1050	.mnd_width = 8,
1051	.hid_width = 5,
1052	.parent_map = gcc_parent_map_0,
1053	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
1054	.hw_clk_ctrl = true,
1055	.clkr.hw.init = &(struct clk_init_data){
1056		.name = "gcc_sdcc4_apps_clk_src",
1057		.parent_data = gcc_parent_data_0,
1058		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1059		.flags = CLK_SET_RATE_PARENT,
1060		.ops = &clk_rcg2_shared_floor_ops,
1061	},
1062};
1063
1064static const struct freq_tbl sm8475_ftbl_gcc_ufs_phy_axi_clk_src[] = {
1065	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1066	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1067	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1068	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1069	F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
1070	F(806400000, P_SM8475_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
1071	F(850000000, P_SM8475_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
1072	{ }
1073};
1074
1075static struct clk_init_data sm8475_gcc_ufs_phy_axi_clk_src_init = {
1076	.name = "gcc_ufs_phy_axi_clk_src",
1077	.parent_data = sm8475_gcc_parent_data_3,
1078	.num_parents = ARRAY_SIZE(sm8475_gcc_parent_map_3),
1079	.flags = CLK_SET_RATE_PARENT,
1080	.ops = &clk_rcg2_ops,
1081};
1082
1083static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1084	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1085	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1086	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1087	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1088	{ }
1089};
1090
1091static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1092	.cmd_rcgr = 0x8702c,
1093	.mnd_width = 8,
1094	.hid_width = 5,
1095	.parent_map = gcc_parent_map_0,
1096	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1097	.hw_clk_ctrl = true,
1098	.clkr.hw.init = &(struct clk_init_data){
1099		.name = "gcc_ufs_phy_axi_clk_src",
1100		.parent_data = gcc_parent_data_0,
1101		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1102		.flags = CLK_SET_RATE_PARENT,
1103		.ops = &clk_rcg2_ops,
1104	},
1105};
1106
1107static const struct freq_tbl sm8475_ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1108	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1109	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1110	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1111	F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
1112	F(806400000, P_SM8475_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
1113	F(850000000, P_SM8475_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
1114	{ }
1115};
1116
1117static struct clk_init_data sm8475_gcc_ufs_phy_ice_core_clk_src_init = {
1118	.name = "gcc_ufs_phy_ice_core_clk_src",
1119	.parent_data = sm8475_gcc_parent_data_3,
1120	.num_parents = ARRAY_SIZE(sm8475_gcc_parent_map_3),
1121	.flags = CLK_SET_RATE_PARENT,
1122	.ops = &clk_rcg2_ops,
1123};
1124
1125static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1126	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1127	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1128	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1129	{ }
1130};
1131
1132static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1133	.cmd_rcgr = 0x87074,
1134	.mnd_width = 0,
1135	.hid_width = 5,
1136	.parent_map = gcc_parent_map_0,
1137	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1138	.hw_clk_ctrl = true,
1139	.clkr.hw.init = &(struct clk_init_data){
1140		.name = "gcc_ufs_phy_ice_core_clk_src",
1141		.parent_data = gcc_parent_data_0,
1142		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1143		.flags = CLK_SET_RATE_PARENT,
1144		.ops = &clk_rcg2_ops,
1145	},
1146};
1147
1148static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
1149	F(9600000, P_BI_TCXO, 2, 0, 0),
1150	F(19200000, P_BI_TCXO, 1, 0, 0),
1151	{ }
1152};
1153
1154static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1155	.cmd_rcgr = 0x870a8,
1156	.mnd_width = 0,
1157	.hid_width = 5,
1158	.parent_map = gcc_parent_map_3,
1159	.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
1160	.hw_clk_ctrl = true,
1161	.clkr.hw.init = &(struct clk_init_data){
1162		.name = "gcc_ufs_phy_phy_aux_clk_src",
1163		.parent_data = gcc_parent_data_3,
1164		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1165		.flags = CLK_SET_RATE_PARENT,
1166		.ops = &clk_rcg2_ops,
1167	},
1168};
1169
1170static struct clk_init_data sm8475_gcc_ufs_phy_unipro_core_clk_src_init = {
1171	.name = "gcc_ufs_phy_unipro_core_clk_src",
1172	.parent_data = sm8475_gcc_parent_data_3,
1173	.num_parents = ARRAY_SIZE(sm8475_gcc_parent_map_3),
1174	.flags = CLK_SET_RATE_PARENT,
1175	.ops = &clk_rcg2_ops,
1176};
1177
1178static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1179	.cmd_rcgr = 0x8708c,
1180	.mnd_width = 0,
1181	.hid_width = 5,
1182	.parent_map = gcc_parent_map_0,
1183	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1184	.hw_clk_ctrl = true,
1185	.clkr.hw.init = &(struct clk_init_data){
1186		.name = "gcc_ufs_phy_unipro_core_clk_src",
1187		.parent_data = gcc_parent_data_0,
1188		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1189		.flags = CLK_SET_RATE_PARENT,
1190		.ops = &clk_rcg2_ops,
1191	},
1192};
1193
1194static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1195	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1196	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1197	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1198	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1199	{ }
1200};
1201
1202static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1203	.cmd_rcgr = 0x49028,
1204	.mnd_width = 8,
1205	.hid_width = 5,
1206	.parent_map = gcc_parent_map_0,
1207	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1208	.hw_clk_ctrl = true,
1209	.clkr.hw.init = &(struct clk_init_data){
1210		.name = "gcc_usb30_prim_master_clk_src",
1211		.parent_data = gcc_parent_data_0,
1212		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1213		.flags = CLK_SET_RATE_PARENT,
1214		.ops = &clk_rcg2_ops,
1215	},
1216};
1217
1218static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1219	.cmd_rcgr = 0x49040,
1220	.mnd_width = 0,
1221	.hid_width = 5,
1222	.parent_map = gcc_parent_map_0,
1223	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1224	.hw_clk_ctrl = true,
1225	.clkr.hw.init = &(struct clk_init_data){
1226		.name = "gcc_usb30_prim_mock_utmi_clk_src",
1227		.parent_data = gcc_parent_data_0,
1228		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1229		.flags = CLK_SET_RATE_PARENT,
1230		.ops = &clk_rcg2_ops,
1231	},
1232};
1233
1234static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1235	.cmd_rcgr = 0x4906c,
1236	.mnd_width = 0,
1237	.hid_width = 5,
1238	.parent_map = gcc_parent_map_2,
1239	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1240	.hw_clk_ctrl = true,
1241	.clkr.hw.init = &(struct clk_init_data){
1242		.name = "gcc_usb3_prim_phy_aux_clk_src",
1243		.parent_data = gcc_parent_data_2,
1244		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1245		.flags = CLK_SET_RATE_PARENT,
1246		.ops = &clk_rcg2_ops,
1247	},
1248};
1249
1250static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1251	.reg = 0x49058,
1252	.shift = 0,
1253	.width = 4,
1254	.clkr.hw.init = &(struct clk_init_data) {
1255		.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1256		.parent_hws = (const struct clk_hw*[]) {
1257			&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1258		},
1259		.num_parents = 1,
1260		.flags = CLK_SET_RATE_PARENT,
1261		.ops = &clk_regmap_div_ro_ops,
1262	},
1263};
1264
1265static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1266	.halt_reg = 0x7b08c,
1267	.halt_check = BRANCH_HALT_SKIP,
1268	.hwcg_reg = 0x7b08c,
1269	.hwcg_bit = 1,
1270	.clkr = {
1271		.enable_reg = 0x62000,
1272		.enable_mask = BIT(12),
1273		.hw.init = &(struct clk_init_data){
1274			.name = "gcc_aggre_noc_pcie_0_axi_clk",
1275			.ops = &clk_branch2_ops,
1276		},
1277	},
1278};
1279
1280static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
1281	.halt_reg = 0x9d098,
1282	.halt_check = BRANCH_HALT_SKIP,
1283	.hwcg_reg = 0x9d098,
1284	.hwcg_bit = 1,
1285	.clkr = {
1286		.enable_reg = 0x62000,
1287		.enable_mask = BIT(11),
1288		.hw.init = &(struct clk_init_data){
1289			.name = "gcc_aggre_noc_pcie_1_axi_clk",
1290			.ops = &clk_branch2_ops,
1291		},
1292	},
1293};
1294
1295static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1296	.halt_reg = 0x870d4,
1297	.halt_check = BRANCH_HALT_VOTED,
1298	.hwcg_reg = 0x870d4,
1299	.hwcg_bit = 1,
1300	.clkr = {
1301		.enable_reg = 0x870d4,
1302		.enable_mask = BIT(0),
1303		.hw.init = &(struct clk_init_data){
1304			.name = "gcc_aggre_ufs_phy_axi_clk",
1305			.parent_hws = (const struct clk_hw*[]) {
1306				&gcc_ufs_phy_axi_clk_src.clkr.hw,
1307			},
1308			.num_parents = 1,
1309			.flags = CLK_SET_RATE_PARENT,
1310			.ops = &clk_branch2_ops,
1311		},
1312	},
1313};
1314
1315static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1316	.halt_reg = 0x870d4,
1317	.halt_check = BRANCH_HALT_VOTED,
1318	.hwcg_reg = 0x870d4,
1319	.hwcg_bit = 1,
1320	.clkr = {
1321		.enable_reg = 0x870d4,
1322		.enable_mask = BIT(1),
1323		.hw.init = &(struct clk_init_data){
1324			.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1325			.parent_hws = (const struct clk_hw*[]) {
1326				&gcc_ufs_phy_axi_clk_src.clkr.hw,
1327			},
1328			.num_parents = 1,
1329			.flags = CLK_SET_RATE_PARENT,
1330			.ops = &clk_branch2_ops,
1331		},
1332	},
1333};
1334
1335static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1336	.halt_reg = 0x49088,
1337	.halt_check = BRANCH_HALT_VOTED,
1338	.hwcg_reg = 0x49088,
1339	.hwcg_bit = 1,
1340	.clkr = {
1341		.enable_reg = 0x49088,
1342		.enable_mask = BIT(0),
1343		.hw.init = &(struct clk_init_data){
1344			.name = "gcc_aggre_usb3_prim_axi_clk",
1345			.parent_hws = (const struct clk_hw*[]) {
1346				&gcc_usb30_prim_master_clk_src.clkr.hw,
1347			},
1348			.num_parents = 1,
1349			.flags = CLK_SET_RATE_PARENT,
1350			.ops = &clk_branch2_ops,
1351		},
1352	},
1353};
1354
1355static struct clk_branch gcc_boot_rom_ahb_clk = {
1356	.halt_reg = 0x48004,
1357	.halt_check = BRANCH_HALT_VOTED,
1358	.hwcg_reg = 0x48004,
1359	.hwcg_bit = 1,
1360	.clkr = {
1361		.enable_reg = 0x62000,
1362		.enable_mask = BIT(10),
1363		.hw.init = &(struct clk_init_data){
1364			.name = "gcc_boot_rom_ahb_clk",
1365			.ops = &clk_branch2_ops,
1366		},
1367	},
1368};
1369
1370static struct clk_branch gcc_camera_hf_axi_clk = {
1371	.halt_reg = 0x36010,
1372	.halt_check = BRANCH_HALT_SKIP,
1373	.hwcg_reg = 0x36010,
1374	.hwcg_bit = 1,
1375	.clkr = {
1376		.enable_reg = 0x36010,
1377		.enable_mask = BIT(0),
1378		.hw.init = &(struct clk_init_data){
1379			.name = "gcc_camera_hf_axi_clk",
1380			.ops = &clk_branch2_ops,
1381		},
1382	},
1383};
1384
1385static struct clk_branch gcc_camera_sf_axi_clk = {
1386	.halt_reg = 0x36018,
1387	.halt_check = BRANCH_HALT_SKIP,
1388	.hwcg_reg = 0x36018,
1389	.hwcg_bit = 1,
1390	.clkr = {
1391		.enable_reg = 0x36018,
1392		.enable_mask = BIT(0),
1393		.hw.init = &(struct clk_init_data){
1394			.name = "gcc_camera_sf_axi_clk",
1395			.ops = &clk_branch2_ops,
1396		},
1397	},
1398};
1399
1400static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
1401	.halt_reg = 0x20030,
1402	.halt_check = BRANCH_HALT_VOTED,
1403	.hwcg_reg = 0x20030,
1404	.hwcg_bit = 1,
1405	.clkr = {
1406		.enable_reg = 0x62000,
1407		.enable_mask = BIT(20),
1408		.hw.init = &(struct clk_init_data){
1409			.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
1410			.ops = &clk_branch2_ops,
1411		},
1412	},
1413};
1414
1415static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1416	.halt_reg = 0x49084,
1417	.halt_check = BRANCH_HALT_VOTED,
1418	.hwcg_reg = 0x49084,
1419	.hwcg_bit = 1,
1420	.clkr = {
1421		.enable_reg = 0x49084,
1422		.enable_mask = BIT(0),
1423		.hw.init = &(struct clk_init_data){
1424			.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1425			.parent_hws = (const struct clk_hw*[]) {
1426				&gcc_usb30_prim_master_clk_src.clkr.hw,
1427			},
1428			.num_parents = 1,
1429			.flags = CLK_SET_RATE_PARENT,
1430			.ops = &clk_branch2_ops,
1431		},
1432	},
1433};
1434
1435static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1436	.halt_reg = 0x81154,
1437	.halt_check = BRANCH_HALT_SKIP,
1438	.hwcg_reg = 0x81154,
1439	.hwcg_bit = 1,
1440	.clkr = {
1441		.enable_reg = 0x81154,
1442		.enable_mask = BIT(0),
1443		.hw.init = &(struct clk_init_data){
1444			.name = "gcc_ddrss_gpu_axi_clk",
1445			.ops = &clk_branch2_aon_ops,
1446		},
1447	},
1448};
1449
1450static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
1451	.halt_reg = 0x9d094,
1452	.halt_check = BRANCH_HALT_SKIP,
1453	.hwcg_reg = 0x9d094,
1454	.hwcg_bit = 1,
1455	.clkr = {
1456		.enable_reg = 0x62000,
1457		.enable_mask = BIT(19),
1458		.hw.init = &(struct clk_init_data){
1459			.name = "gcc_ddrss_pcie_sf_tbu_clk",
1460			.ops = &clk_branch2_ops,
1461		},
1462	},
1463};
1464
1465static struct clk_branch gcc_disp_hf_axi_clk = {
1466	.halt_reg = 0x3700c,
1467	.halt_check = BRANCH_HALT_SKIP,
1468	.hwcg_reg = 0x3700c,
1469	.hwcg_bit = 1,
1470	.clkr = {
1471		.enable_reg = 0x3700c,
1472		.enable_mask = BIT(0),
1473		.hw.init = &(struct clk_init_data){
1474			.name = "gcc_disp_hf_axi_clk",
1475			.ops = &clk_branch2_ops,
1476		},
1477	},
1478};
1479
1480static struct clk_branch gcc_disp_sf_axi_clk = {
1481	.halt_reg = 0x37014,
1482	.halt_check = BRANCH_HALT_SKIP,
1483	.hwcg_reg = 0x37014,
1484	.hwcg_bit = 1,
1485	.clkr = {
1486		.enable_reg = 0x37014,
1487		.enable_mask = BIT(0),
1488		.hw.init = &(struct clk_init_data){
1489			.name = "gcc_disp_sf_axi_clk",
1490			.ops = &clk_branch2_ops,
1491		},
1492	},
1493};
1494
1495static struct clk_branch gcc_eusb3_0_clkref_en = {
1496	.halt_reg = 0x9c00c,
1497	.halt_check = BRANCH_HALT,
1498	.clkr = {
1499		.enable_reg = 0x9c00c,
1500		.enable_mask = BIT(0),
1501		.hw.init = &(struct clk_init_data){
1502			.name = "gcc_eusb3_0_clkref_en",
1503			.ops = &clk_branch2_ops,
1504		},
1505	},
1506};
1507
1508static struct clk_branch gcc_gp1_clk = {
1509	.halt_reg = 0x74000,
1510	.halt_check = BRANCH_HALT,
1511	.clkr = {
1512		.enable_reg = 0x74000,
1513		.enable_mask = BIT(0),
1514		.hw.init = &(struct clk_init_data){
1515			.name = "gcc_gp1_clk",
1516			.parent_hws = (const struct clk_hw*[]) {
1517				&gcc_gp1_clk_src.clkr.hw,
1518			},
1519			.num_parents = 1,
1520			.flags = CLK_SET_RATE_PARENT,
1521			.ops = &clk_branch2_ops,
1522		},
1523	},
1524};
1525
1526static struct clk_branch gcc_gp2_clk = {
1527	.halt_reg = 0x75000,
1528	.halt_check = BRANCH_HALT,
1529	.clkr = {
1530		.enable_reg = 0x75000,
1531		.enable_mask = BIT(0),
1532		.hw.init = &(struct clk_init_data){
1533			.name = "gcc_gp2_clk",
1534			.parent_hws = (const struct clk_hw*[]) {
1535				&gcc_gp2_clk_src.clkr.hw,
1536			},
1537			.num_parents = 1,
1538			.flags = CLK_SET_RATE_PARENT,
1539			.ops = &clk_branch2_ops,
1540		},
1541	},
1542};
1543
1544static struct clk_branch gcc_gp3_clk = {
1545	.halt_reg = 0x76000,
1546	.halt_check = BRANCH_HALT,
1547	.clkr = {
1548		.enable_reg = 0x76000,
1549		.enable_mask = BIT(0),
1550		.hw.init = &(struct clk_init_data){
1551			.name = "gcc_gp3_clk",
1552			.parent_hws = (const struct clk_hw*[]) {
1553				&gcc_gp3_clk_src.clkr.hw,
1554			},
1555			.num_parents = 1,
1556			.flags = CLK_SET_RATE_PARENT,
1557			.ops = &clk_branch2_ops,
1558		},
1559	},
1560};
1561
1562static struct clk_branch gcc_gpu_gpll0_clk_src = {
1563	.halt_check = BRANCH_HALT_DELAY,
1564	.clkr = {
1565		.enable_reg = 0x62000,
1566		.enable_mask = BIT(15),
1567		.hw.init = &(struct clk_init_data){
1568			.name = "gcc_gpu_gpll0_clk_src",
1569			.parent_hws = (const struct clk_hw*[]) {
1570				&gcc_gpll0.clkr.hw,
1571			},
1572			.num_parents = 1,
1573			.flags = CLK_SET_RATE_PARENT,
1574			.ops = &clk_branch2_ops,
1575		},
1576	},
1577};
1578
1579static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1580	.halt_check = BRANCH_HALT_DELAY,
1581	.clkr = {
1582		.enable_reg = 0x62000,
1583		.enable_mask = BIT(16),
1584		.hw.init = &(struct clk_init_data){
1585			.name = "gcc_gpu_gpll0_div_clk_src",
1586			.parent_hws = (const struct clk_hw*[]) {
1587				&gcc_gpll0_out_even.clkr.hw,
1588			},
1589			.num_parents = 1,
1590			.flags = CLK_SET_RATE_PARENT,
1591			.ops = &clk_branch2_ops,
1592		},
1593	},
1594};
1595
1596static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1597	.halt_reg = 0x81010,
1598	.halt_check = BRANCH_HALT_VOTED,
1599	.hwcg_reg = 0x81010,
1600	.hwcg_bit = 1,
1601	.clkr = {
1602		.enable_reg = 0x81010,
1603		.enable_mask = BIT(0),
1604		.hw.init = &(struct clk_init_data){
1605			.name = "gcc_gpu_memnoc_gfx_clk",
1606			.ops = &clk_branch2_ops,
1607		},
1608	},
1609};
1610
1611static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1612	.halt_reg = 0x81018,
1613	.halt_check = BRANCH_HALT_DELAY,
1614	.clkr = {
1615		.enable_reg = 0x81018,
1616		.enable_mask = BIT(0),
1617		.hw.init = &(struct clk_init_data){
1618			.name = "gcc_gpu_snoc_dvm_gfx_clk",
1619			.ops = &clk_branch2_ops,
1620		},
1621	},
1622};
1623
1624static struct clk_branch gcc_pcie_0_aux_clk = {
1625	.halt_reg = 0x7b034,
1626	.halt_check = BRANCH_HALT_VOTED,
1627	.clkr = {
1628		.enable_reg = 0x62008,
1629		.enable_mask = BIT(3),
1630		.hw.init = &(struct clk_init_data){
1631			.name = "gcc_pcie_0_aux_clk",
1632			.parent_hws = (const struct clk_hw*[]) {
1633				&gcc_pcie_0_aux_clk_src.clkr.hw,
1634			},
1635			.num_parents = 1,
1636			.flags = CLK_SET_RATE_PARENT,
1637			.ops = &clk_branch2_ops,
1638		},
1639	},
1640};
1641
1642static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1643	.halt_reg = 0x7b030,
1644	.halt_check = BRANCH_HALT_VOTED,
1645	.hwcg_reg = 0x7b030,
1646	.hwcg_bit = 1,
1647	.clkr = {
1648		.enable_reg = 0x62008,
1649		.enable_mask = BIT(2),
1650		.hw.init = &(struct clk_init_data){
1651			.name = "gcc_pcie_0_cfg_ahb_clk",
1652			.ops = &clk_branch2_ops,
1653		},
1654	},
1655};
1656
1657static struct clk_branch gcc_pcie_0_clkref_en = {
1658	.halt_reg = 0x9c004,
1659	.halt_check = BRANCH_HALT,
1660	.clkr = {
1661		.enable_reg = 0x9c004,
1662		.enable_mask = BIT(0),
1663		.hw.init = &(struct clk_init_data){
1664			.name = "gcc_pcie_0_clkref_en",
1665			.ops = &clk_branch2_ops,
1666		},
1667	},
1668};
1669
1670static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1671	.halt_reg = 0x7b028,
1672	.halt_check = BRANCH_HALT_SKIP,
1673	.clkr = {
1674		.enable_reg = 0x62008,
1675		.enable_mask = BIT(1),
1676		.hw.init = &(struct clk_init_data){
1677			.name = "gcc_pcie_0_mstr_axi_clk",
1678			.ops = &clk_branch2_ops,
1679		},
1680	},
1681};
1682
1683static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
1684	.halt_reg = 0x7b044,
1685	.halt_check = BRANCH_HALT_VOTED,
1686	.clkr = {
1687		.enable_reg = 0x62000,
1688		.enable_mask = BIT(22),
1689		.hw.init = &(struct clk_init_data){
1690			.name = "gcc_pcie_0_phy_rchng_clk",
1691			.parent_hws = (const struct clk_hw*[]) {
1692				&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1693			},
1694			.num_parents = 1,
1695			.flags = CLK_SET_RATE_PARENT,
1696			.ops = &clk_branch2_ops,
1697		},
1698	},
1699};
1700
1701static struct clk_branch gcc_pcie_0_pipe_clk = {
1702	.halt_reg = 0x7b03c,
1703	.halt_check = BRANCH_HALT_SKIP,
1704	.clkr = {
1705		.enable_reg = 0x62008,
1706		.enable_mask = BIT(4),
1707		.hw.init = &(struct clk_init_data){
1708			.name = "gcc_pcie_0_pipe_clk",
1709			.parent_hws = (const struct clk_hw*[]) {
1710				&gcc_pcie_0_pipe_clk_src.clkr.hw,
1711			},
1712			.num_parents = 1,
1713			.flags = CLK_SET_RATE_PARENT,
1714			.ops = &clk_branch2_ops,
1715		},
1716	},
1717};
1718
1719static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1720	.halt_reg = 0x7b020,
1721	.halt_check = BRANCH_HALT_VOTED,
1722	.hwcg_reg = 0x7b020,
1723	.hwcg_bit = 1,
1724	.clkr = {
1725		.enable_reg = 0x62008,
1726		.enable_mask = BIT(0),
1727		.hw.init = &(struct clk_init_data){
1728			.name = "gcc_pcie_0_slv_axi_clk",
1729			.ops = &clk_branch2_ops,
1730		},
1731	},
1732};
1733
1734static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1735	.halt_reg = 0x7b01c,
1736	.halt_check = BRANCH_HALT_VOTED,
1737	.clkr = {
1738		.enable_reg = 0x62008,
1739		.enable_mask = BIT(5),
1740		.hw.init = &(struct clk_init_data){
1741			.name = "gcc_pcie_0_slv_q2a_axi_clk",
1742			.ops = &clk_branch2_ops,
1743		},
1744	},
1745};
1746
1747static struct clk_branch gcc_pcie_1_aux_clk = {
1748	.halt_reg = 0x9d030,
1749	.halt_check = BRANCH_HALT_VOTED,
1750	.clkr = {
1751		.enable_reg = 0x62000,
1752		.enable_mask = BIT(29),
1753		.hw.init = &(struct clk_init_data){
1754			.name = "gcc_pcie_1_aux_clk",
1755			.parent_hws = (const struct clk_hw*[]) {
1756				&gcc_pcie_1_aux_clk_src.clkr.hw,
1757			},
1758			.num_parents = 1,
1759			.flags = CLK_SET_RATE_PARENT,
1760			.ops = &clk_branch2_ops,
1761		},
1762	},
1763};
1764
1765static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1766	.halt_reg = 0x9d02c,
1767	.halt_check = BRANCH_HALT_VOTED,
1768	.hwcg_reg = 0x9d02c,
1769	.hwcg_bit = 1,
1770	.clkr = {
1771		.enable_reg = 0x62000,
1772		.enable_mask = BIT(28),
1773		.hw.init = &(struct clk_init_data){
1774			.name = "gcc_pcie_1_cfg_ahb_clk",
1775			.ops = &clk_branch2_ops,
1776		},
1777	},
1778};
1779
1780static struct clk_branch gcc_pcie_1_clkref_en = {
1781	.halt_reg = 0x9c008,
1782	.halt_check = BRANCH_HALT,
1783	.clkr = {
1784		.enable_reg = 0x9c008,
1785		.enable_mask = BIT(0),
1786		.hw.init = &(struct clk_init_data){
1787			.name = "gcc_pcie_1_clkref_en",
1788			.ops = &clk_branch2_ops,
1789		},
1790	},
1791};
1792
1793static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1794	.halt_reg = 0x9d024,
1795	.halt_check = BRANCH_HALT_SKIP,
1796	.clkr = {
1797		.enable_reg = 0x62000,
1798		.enable_mask = BIT(27),
1799		.hw.init = &(struct clk_init_data){
1800			.name = "gcc_pcie_1_mstr_axi_clk",
1801			.ops = &clk_branch2_ops,
1802		},
1803	},
1804};
1805
1806static struct clk_branch gcc_pcie_1_phy_aux_clk = {
1807	.halt_reg = 0x9d038,
1808	.halt_check = BRANCH_HALT_VOTED,
1809	.clkr = {
1810		.enable_reg = 0x62000,
1811		.enable_mask = BIT(24),
1812		.hw.init = &(struct clk_init_data){
1813			.name = "gcc_pcie_1_phy_aux_clk",
1814			.parent_hws = (const struct clk_hw*[]) {
1815				&gcc_pcie_1_phy_aux_clk_src.clkr.hw,
1816			},
1817			.num_parents = 1,
1818			.flags = CLK_SET_RATE_PARENT,
1819			.ops = &clk_branch2_ops,
1820		},
1821	},
1822};
1823
1824static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
1825	.halt_reg = 0x9d048,
1826	.halt_check = BRANCH_HALT_VOTED,
1827	.clkr = {
1828		.enable_reg = 0x62000,
1829		.enable_mask = BIT(23),
1830		.hw.init = &(struct clk_init_data){
1831			.name = "gcc_pcie_1_phy_rchng_clk",
1832			.parent_hws = (const struct clk_hw*[]) {
1833				&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1834			},
1835			.num_parents = 1,
1836			.flags = CLK_SET_RATE_PARENT,
1837			.ops = &clk_branch2_ops,
1838		},
1839	},
1840};
1841
1842static struct clk_branch gcc_pcie_1_pipe_clk = {
1843	.halt_reg = 0x9d040,
1844	.halt_check = BRANCH_HALT_SKIP,
1845	.clkr = {
1846		.enable_reg = 0x62000,
1847		.enable_mask = BIT(30),
1848		.hw.init = &(struct clk_init_data){
1849			.name = "gcc_pcie_1_pipe_clk",
1850			.parent_hws = (const struct clk_hw*[]) {
1851				&gcc_pcie_1_pipe_clk_src.clkr.hw,
1852			},
1853			.num_parents = 1,
1854			.flags = CLK_SET_RATE_PARENT,
1855			.ops = &clk_branch2_ops,
1856		},
1857	},
1858};
1859
1860static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1861	.halt_reg = 0x9d01c,
1862	.halt_check = BRANCH_HALT_VOTED,
1863	.hwcg_reg = 0x9d01c,
1864	.hwcg_bit = 1,
1865	.clkr = {
1866		.enable_reg = 0x62000,
1867		.enable_mask = BIT(26),
1868		.hw.init = &(struct clk_init_data){
1869			.name = "gcc_pcie_1_slv_axi_clk",
1870			.ops = &clk_branch2_ops,
1871		},
1872	},
1873};
1874
1875static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1876	.halt_reg = 0x9d018,
1877	.halt_check = BRANCH_HALT_VOTED,
1878	.clkr = {
1879		.enable_reg = 0x62000,
1880		.enable_mask = BIT(25),
1881		.hw.init = &(struct clk_init_data){
1882			.name = "gcc_pcie_1_slv_q2a_axi_clk",
1883			.ops = &clk_branch2_ops,
1884		},
1885	},
1886};
1887
1888static struct clk_branch gcc_pdm2_clk = {
1889	.halt_reg = 0x4300c,
1890	.halt_check = BRANCH_HALT,
1891	.clkr = {
1892		.enable_reg = 0x4300c,
1893		.enable_mask = BIT(0),
1894		.hw.init = &(struct clk_init_data){
1895			.name = "gcc_pdm2_clk",
1896			.parent_hws = (const struct clk_hw*[]) {
1897				&gcc_pdm2_clk_src.clkr.hw,
1898			},
1899			.num_parents = 1,
1900			.flags = CLK_SET_RATE_PARENT,
1901			.ops = &clk_branch2_ops,
1902		},
1903	},
1904};
1905
1906static struct clk_branch gcc_pdm_ahb_clk = {
1907	.halt_reg = 0x43004,
1908	.halt_check = BRANCH_HALT_VOTED,
1909	.hwcg_reg = 0x43004,
1910	.hwcg_bit = 1,
1911	.clkr = {
1912		.enable_reg = 0x43004,
1913		.enable_mask = BIT(0),
1914		.hw.init = &(struct clk_init_data){
1915			.name = "gcc_pdm_ahb_clk",
1916			.ops = &clk_branch2_ops,
1917		},
1918	},
1919};
1920
1921static struct clk_branch gcc_pdm_xo4_clk = {
1922	.halt_reg = 0x43008,
1923	.halt_check = BRANCH_HALT,
1924	.clkr = {
1925		.enable_reg = 0x43008,
1926		.enable_mask = BIT(0),
1927		.hw.init = &(struct clk_init_data){
1928			.name = "gcc_pdm_xo4_clk",
1929			.ops = &clk_branch2_ops,
1930		},
1931	},
1932};
1933
1934static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1935	.halt_reg = 0x36008,
1936	.halt_check = BRANCH_HALT_VOTED,
1937	.hwcg_reg = 0x36008,
1938	.hwcg_bit = 1,
1939	.clkr = {
1940		.enable_reg = 0x36008,
1941		.enable_mask = BIT(0),
1942		.hw.init = &(struct clk_init_data){
1943			.name = "gcc_qmip_camera_nrt_ahb_clk",
1944			.ops = &clk_branch2_ops,
1945		},
1946	},
1947};
1948
1949static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
1950	.halt_reg = 0x3600c,
1951	.halt_check = BRANCH_HALT_VOTED,
1952	.hwcg_reg = 0x3600c,
1953	.hwcg_bit = 1,
1954	.clkr = {
1955		.enable_reg = 0x3600c,
1956		.enable_mask = BIT(0),
1957		.hw.init = &(struct clk_init_data){
1958			.name = "gcc_qmip_camera_rt_ahb_clk",
1959			.ops = &clk_branch2_ops,
1960		},
1961	},
1962};
1963
1964static struct clk_branch gcc_qmip_disp_ahb_clk = {
1965	.halt_reg = 0x37008,
1966	.halt_check = BRANCH_HALT_VOTED,
1967	.hwcg_reg = 0x37008,
1968	.hwcg_bit = 1,
1969	.clkr = {
1970		.enable_reg = 0x37008,
1971		.enable_mask = BIT(0),
1972		.hw.init = &(struct clk_init_data){
1973			.name = "gcc_qmip_disp_ahb_clk",
1974			.ops = &clk_branch2_ops,
1975		},
1976	},
1977};
1978
1979static struct clk_branch gcc_qmip_gpu_ahb_clk = {
1980	.halt_reg = 0x81008,
1981	.halt_check = BRANCH_HALT_VOTED,
1982	.hwcg_reg = 0x81008,
1983	.hwcg_bit = 1,
1984	.clkr = {
1985		.enable_reg = 0x81008,
1986		.enable_mask = BIT(0),
1987		.hw.init = &(struct clk_init_data){
1988			.name = "gcc_qmip_gpu_ahb_clk",
1989			.ops = &clk_branch2_ops,
1990		},
1991	},
1992};
1993
1994static struct clk_branch gcc_qmip_pcie_ahb_clk = {
1995	.halt_reg = 0x7b018,
1996	.halt_check = BRANCH_HALT_VOTED,
1997	.hwcg_reg = 0x7b018,
1998	.hwcg_bit = 1,
1999	.clkr = {
2000		.enable_reg = 0x7b018,
2001		.enable_mask = BIT(0),
2002		.hw.init = &(struct clk_init_data){
2003			.name = "gcc_qmip_pcie_ahb_clk",
2004			.ops = &clk_branch2_ops,
2005		},
2006	},
2007};
2008
2009static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
2010	.halt_reg = 0x42014,
2011	.halt_check = BRANCH_HALT_VOTED,
2012	.hwcg_reg = 0x42014,
2013	.hwcg_bit = 1,
2014	.clkr = {
2015		.enable_reg = 0x42014,
2016		.enable_mask = BIT(0),
2017		.hw.init = &(struct clk_init_data){
2018			.name = "gcc_qmip_video_cv_cpu_ahb_clk",
2019			.ops = &clk_branch2_ops,
2020		},
2021	},
2022};
2023
2024static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2025	.halt_reg = 0x42008,
2026	.halt_check = BRANCH_HALT_VOTED,
2027	.hwcg_reg = 0x42008,
2028	.hwcg_bit = 1,
2029	.clkr = {
2030		.enable_reg = 0x42008,
2031		.enable_mask = BIT(0),
2032		.hw.init = &(struct clk_init_data){
2033			.name = "gcc_qmip_video_cvp_ahb_clk",
2034			.ops = &clk_branch2_ops,
2035		},
2036	},
2037};
2038
2039static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
2040	.halt_reg = 0x42010,
2041	.halt_check = BRANCH_HALT_VOTED,
2042	.hwcg_reg = 0x42010,
2043	.hwcg_bit = 1,
2044	.clkr = {
2045		.enable_reg = 0x42010,
2046		.enable_mask = BIT(0),
2047		.hw.init = &(struct clk_init_data){
2048			.name = "gcc_qmip_video_v_cpu_ahb_clk",
2049			.ops = &clk_branch2_ops,
2050		},
2051	},
2052};
2053
2054static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2055	.halt_reg = 0x4200c,
2056	.halt_check = BRANCH_HALT_VOTED,
2057	.hwcg_reg = 0x4200c,
2058	.hwcg_bit = 1,
2059	.clkr = {
2060		.enable_reg = 0x4200c,
2061		.enable_mask = BIT(0),
2062		.hw.init = &(struct clk_init_data){
2063			.name = "gcc_qmip_video_vcodec_ahb_clk",
2064			.ops = &clk_branch2_ops,
2065		},
2066	},
2067};
2068
2069static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2070	.halt_reg = 0x3300c,
2071	.halt_check = BRANCH_HALT_VOTED,
2072	.clkr = {
2073		.enable_reg = 0x62008,
2074		.enable_mask = BIT(9),
2075		.hw.init = &(struct clk_init_data){
2076			.name = "gcc_qupv3_wrap0_core_2x_clk",
2077			.ops = &clk_branch2_ops,
2078		},
2079	},
2080};
2081
2082static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2083	.halt_reg = 0x33000,
2084	.halt_check = BRANCH_HALT_VOTED,
2085	.clkr = {
2086		.enable_reg = 0x62008,
2087		.enable_mask = BIT(8),
2088		.hw.init = &(struct clk_init_data){
2089			.name = "gcc_qupv3_wrap0_core_clk",
2090			.ops = &clk_branch2_ops,
2091		},
2092	},
2093};
2094
2095static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2096	.halt_reg = 0x2700c,
2097	.halt_check = BRANCH_HALT_VOTED,
2098	.clkr = {
2099		.enable_reg = 0x62008,
2100		.enable_mask = BIT(10),
2101		.hw.init = &(struct clk_init_data){
2102			.name = "gcc_qupv3_wrap0_s0_clk",
2103			.parent_hws = (const struct clk_hw*[]) {
2104				&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2105			},
2106			.num_parents = 1,
2107			.flags = CLK_SET_RATE_PARENT,
2108			.ops = &clk_branch2_ops,
2109		},
2110	},
2111};
2112
2113static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2114	.halt_reg = 0x27140,
2115	.halt_check = BRANCH_HALT_VOTED,
2116	.clkr = {
2117		.enable_reg = 0x62008,
2118		.enable_mask = BIT(11),
2119		.hw.init = &(struct clk_init_data){
2120			.name = "gcc_qupv3_wrap0_s1_clk",
2121			.parent_hws = (const struct clk_hw*[]) {
2122				&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2123			},
2124			.num_parents = 1,
2125			.flags = CLK_SET_RATE_PARENT,
2126			.ops = &clk_branch2_ops,
2127		},
2128	},
2129};
2130
2131static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2132	.halt_reg = 0x27274,
2133	.halt_check = BRANCH_HALT_VOTED,
2134	.clkr = {
2135		.enable_reg = 0x62008,
2136		.enable_mask = BIT(12),
2137		.hw.init = &(struct clk_init_data){
2138			.name = "gcc_qupv3_wrap0_s2_clk",
2139			.parent_hws = (const struct clk_hw*[]) {
2140				&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2141			},
2142			.num_parents = 1,
2143			.flags = CLK_SET_RATE_PARENT,
2144			.ops = &clk_branch2_ops,
2145		},
2146	},
2147};
2148
2149static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2150	.halt_reg = 0x273a8,
2151	.halt_check = BRANCH_HALT_VOTED,
2152	.clkr = {
2153		.enable_reg = 0x62008,
2154		.enable_mask = BIT(13),
2155		.hw.init = &(struct clk_init_data){
2156			.name = "gcc_qupv3_wrap0_s3_clk",
2157			.parent_hws = (const struct clk_hw*[]) {
2158				&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2159			},
2160			.num_parents = 1,
2161			.flags = CLK_SET_RATE_PARENT,
2162			.ops = &clk_branch2_ops,
2163		},
2164	},
2165};
2166
2167static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2168	.halt_reg = 0x274dc,
2169	.halt_check = BRANCH_HALT_VOTED,
2170	.clkr = {
2171		.enable_reg = 0x62008,
2172		.enable_mask = BIT(14),
2173		.hw.init = &(struct clk_init_data){
2174			.name = "gcc_qupv3_wrap0_s4_clk",
2175			.parent_hws = (const struct clk_hw*[]) {
2176				&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2177			},
2178			.num_parents = 1,
2179			.flags = CLK_SET_RATE_PARENT,
2180			.ops = &clk_branch2_ops,
2181		},
2182	},
2183};
2184
2185static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2186	.halt_reg = 0x27610,
2187	.halt_check = BRANCH_HALT_VOTED,
2188	.clkr = {
2189		.enable_reg = 0x62008,
2190		.enable_mask = BIT(15),
2191		.hw.init = &(struct clk_init_data){
2192			.name = "gcc_qupv3_wrap0_s5_clk",
2193			.parent_hws = (const struct clk_hw*[]) {
2194				&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2195			},
2196			.num_parents = 1,
2197			.flags = CLK_SET_RATE_PARENT,
2198			.ops = &clk_branch2_ops,
2199		},
2200	},
2201};
2202
2203static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2204	.halt_reg = 0x27744,
2205	.halt_check = BRANCH_HALT_VOTED,
2206	.clkr = {
2207		.enable_reg = 0x62008,
2208		.enable_mask = BIT(16),
2209		.hw.init = &(struct clk_init_data){
2210			.name = "gcc_qupv3_wrap0_s6_clk",
2211			.parent_hws = (const struct clk_hw*[]) {
2212				&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2213			},
2214			.num_parents = 1,
2215			.flags = CLK_SET_RATE_PARENT,
2216			.ops = &clk_branch2_ops,
2217		},
2218	},
2219};
2220
2221static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2222	.halt_reg = 0x27878,
2223	.halt_check = BRANCH_HALT_VOTED,
2224	.clkr = {
2225		.enable_reg = 0x62008,
2226		.enable_mask = BIT(17),
2227		.hw.init = &(struct clk_init_data){
2228			.name = "gcc_qupv3_wrap0_s7_clk",
2229			.parent_hws = (const struct clk_hw*[]) {
2230				&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2231			},
2232			.num_parents = 1,
2233			.flags = CLK_SET_RATE_PARENT,
2234			.ops = &clk_branch2_ops,
2235		},
2236	},
2237};
2238
2239static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2240	.halt_reg = 0x3314c,
2241	.halt_check = BRANCH_HALT_VOTED,
2242	.clkr = {
2243		.enable_reg = 0x62008,
2244		.enable_mask = BIT(18),
2245		.hw.init = &(struct clk_init_data){
2246			.name = "gcc_qupv3_wrap1_core_2x_clk",
2247			.ops = &clk_branch2_ops,
2248		},
2249	},
2250};
2251
2252static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2253	.halt_reg = 0x33140,
2254	.halt_check = BRANCH_HALT_VOTED,
2255	.clkr = {
2256		.enable_reg = 0x62008,
2257		.enable_mask = BIT(19),
2258		.hw.init = &(struct clk_init_data){
2259			.name = "gcc_qupv3_wrap1_core_clk",
2260			.ops = &clk_branch2_ops,
2261		},
2262	},
2263};
2264
2265static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2266	.halt_reg = 0x2800c,
2267	.halt_check = BRANCH_HALT_VOTED,
2268	.clkr = {
2269		.enable_reg = 0x62008,
2270		.enable_mask = BIT(22),
2271		.hw.init = &(struct clk_init_data){
2272			.name = "gcc_qupv3_wrap1_s0_clk",
2273			.parent_hws = (const struct clk_hw*[]) {
2274				&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2275			},
2276			.num_parents = 1,
2277			.flags = CLK_SET_RATE_PARENT,
2278			.ops = &clk_branch2_ops,
2279		},
2280	},
2281};
2282
2283static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2284	.halt_reg = 0x28140,
2285	.halt_check = BRANCH_HALT_VOTED,
2286	.clkr = {
2287		.enable_reg = 0x62008,
2288		.enable_mask = BIT(23),
2289		.hw.init = &(struct clk_init_data){
2290			.name = "gcc_qupv3_wrap1_s1_clk",
2291			.parent_hws = (const struct clk_hw*[]) {
2292				&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2293			},
2294			.num_parents = 1,
2295			.flags = CLK_SET_RATE_PARENT,
2296			.ops = &clk_branch2_ops,
2297		},
2298	},
2299};
2300
2301static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2302	.halt_reg = 0x28274,
2303	.halt_check = BRANCH_HALT_VOTED,
2304	.clkr = {
2305		.enable_reg = 0x62008,
2306		.enable_mask = BIT(24),
2307		.hw.init = &(struct clk_init_data){
2308			.name = "gcc_qupv3_wrap1_s2_clk",
2309			.parent_hws = (const struct clk_hw*[]) {
2310				&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2311			},
2312			.num_parents = 1,
2313			.flags = CLK_SET_RATE_PARENT,
2314			.ops = &clk_branch2_ops,
2315		},
2316	},
2317};
2318
2319static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2320	.halt_reg = 0x283a8,
2321	.halt_check = BRANCH_HALT_VOTED,
2322	.clkr = {
2323		.enable_reg = 0x62008,
2324		.enable_mask = BIT(25),
2325		.hw.init = &(struct clk_init_data){
2326			.name = "gcc_qupv3_wrap1_s3_clk",
2327			.parent_hws = (const struct clk_hw*[]) {
2328				&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2329			},
2330			.num_parents = 1,
2331			.flags = CLK_SET_RATE_PARENT,
2332			.ops = &clk_branch2_ops,
2333		},
2334	},
2335};
2336
2337static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2338	.halt_reg = 0x284dc,
2339	.halt_check = BRANCH_HALT_VOTED,
2340	.clkr = {
2341		.enable_reg = 0x62008,
2342		.enable_mask = BIT(26),
2343		.hw.init = &(struct clk_init_data){
2344			.name = "gcc_qupv3_wrap1_s4_clk",
2345			.parent_hws = (const struct clk_hw*[]) {
2346				&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2347			},
2348			.num_parents = 1,
2349			.flags = CLK_SET_RATE_PARENT,
2350			.ops = &clk_branch2_ops,
2351		},
2352	},
2353};
2354
2355static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2356	.halt_reg = 0x28610,
2357	.halt_check = BRANCH_HALT_VOTED,
2358	.clkr = {
2359		.enable_reg = 0x62008,
2360		.enable_mask = BIT(27),
2361		.hw.init = &(struct clk_init_data){
2362			.name = "gcc_qupv3_wrap1_s5_clk",
2363			.parent_hws = (const struct clk_hw*[]) {
2364				&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2365			},
2366			.num_parents = 1,
2367			.flags = CLK_SET_RATE_PARENT,
2368			.ops = &clk_branch2_ops,
2369		},
2370	},
2371};
2372
2373static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2374	.halt_reg = 0x28744,
2375	.halt_check = BRANCH_HALT_VOTED,
2376	.clkr = {
2377		.enable_reg = 0x62008,
2378		.enable_mask = BIT(28),
2379		.hw.init = &(struct clk_init_data){
2380			.name = "gcc_qupv3_wrap1_s6_clk",
2381			.parent_hws = (const struct clk_hw*[]) {
2382				&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2383			},
2384			.num_parents = 1,
2385			.flags = CLK_SET_RATE_PARENT,
2386			.ops = &clk_branch2_ops,
2387		},
2388	},
2389};
2390
2391static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
2392	.halt_reg = 0x3328c,
2393	.halt_check = BRANCH_HALT_VOTED,
2394	.clkr = {
2395		.enable_reg = 0x62010,
2396		.enable_mask = BIT(3),
2397		.hw.init = &(struct clk_init_data){
2398			.name = "gcc_qupv3_wrap2_core_2x_clk",
2399			.ops = &clk_branch2_ops,
2400		},
2401	},
2402};
2403
2404static struct clk_branch gcc_qupv3_wrap2_core_clk = {
2405	.halt_reg = 0x33280,
2406	.halt_check = BRANCH_HALT_VOTED,
2407	.clkr = {
2408		.enable_reg = 0x62010,
2409		.enable_mask = BIT(0),
2410		.hw.init = &(struct clk_init_data){
2411			.name = "gcc_qupv3_wrap2_core_clk",
2412			.ops = &clk_branch2_ops,
2413		},
2414	},
2415};
2416
2417static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2418	.halt_reg = 0x2e00c,
2419	.halt_check = BRANCH_HALT_VOTED,
2420	.clkr = {
2421		.enable_reg = 0x62010,
2422		.enable_mask = BIT(4),
2423		.hw.init = &(struct clk_init_data){
2424			.name = "gcc_qupv3_wrap2_s0_clk",
2425			.parent_hws = (const struct clk_hw*[]) {
2426				&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
2427			},
2428			.num_parents = 1,
2429			.flags = CLK_SET_RATE_PARENT,
2430			.ops = &clk_branch2_ops,
2431		},
2432	},
2433};
2434
2435static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2436	.halt_reg = 0x2e140,
2437	.halt_check = BRANCH_HALT_VOTED,
2438	.clkr = {
2439		.enable_reg = 0x62010,
2440		.enable_mask = BIT(5),
2441		.hw.init = &(struct clk_init_data){
2442			.name = "gcc_qupv3_wrap2_s1_clk",
2443			.parent_hws = (const struct clk_hw*[]) {
2444				&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
2445			},
2446			.num_parents = 1,
2447			.flags = CLK_SET_RATE_PARENT,
2448			.ops = &clk_branch2_ops,
2449		},
2450	},
2451};
2452
2453static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2454	.halt_reg = 0x2e274,
2455	.halt_check = BRANCH_HALT_VOTED,
2456	.clkr = {
2457		.enable_reg = 0x62010,
2458		.enable_mask = BIT(6),
2459		.hw.init = &(struct clk_init_data){
2460			.name = "gcc_qupv3_wrap2_s2_clk",
2461			.parent_hws = (const struct clk_hw*[]) {
2462				&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2463			},
2464			.num_parents = 1,
2465			.flags = CLK_SET_RATE_PARENT,
2466			.ops = &clk_branch2_ops,
2467		},
2468	},
2469};
2470
2471static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2472	.halt_reg = 0x2e3a8,
2473	.halt_check = BRANCH_HALT_VOTED,
2474	.clkr = {
2475		.enable_reg = 0x62010,
2476		.enable_mask = BIT(7),
2477		.hw.init = &(struct clk_init_data){
2478			.name = "gcc_qupv3_wrap2_s3_clk",
2479			.parent_hws = (const struct clk_hw*[]) {
2480				&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2481			},
2482			.num_parents = 1,
2483			.flags = CLK_SET_RATE_PARENT,
2484			.ops = &clk_branch2_ops,
2485		},
2486	},
2487};
2488
2489static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2490	.halt_reg = 0x2e4dc,
2491	.halt_check = BRANCH_HALT_VOTED,
2492	.clkr = {
2493		.enable_reg = 0x62010,
2494		.enable_mask = BIT(8),
2495		.hw.init = &(struct clk_init_data){
2496			.name = "gcc_qupv3_wrap2_s4_clk",
2497			.parent_hws = (const struct clk_hw*[]) {
2498				&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
2499			},
2500			.num_parents = 1,
2501			.flags = CLK_SET_RATE_PARENT,
2502			.ops = &clk_branch2_ops,
2503		},
2504	},
2505};
2506
2507static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2508	.halt_reg = 0x2e610,
2509	.halt_check = BRANCH_HALT_VOTED,
2510	.clkr = {
2511		.enable_reg = 0x62010,
2512		.enable_mask = BIT(9),
2513		.hw.init = &(struct clk_init_data){
2514			.name = "gcc_qupv3_wrap2_s5_clk",
2515			.parent_hws = (const struct clk_hw*[]) {
2516				&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
2517			},
2518			.num_parents = 1,
2519			.flags = CLK_SET_RATE_PARENT,
2520			.ops = &clk_branch2_ops,
2521		},
2522	},
2523};
2524
2525static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
2526	.halt_reg = 0x2e744,
2527	.halt_check = BRANCH_HALT_VOTED,
2528	.clkr = {
2529		.enable_reg = 0x62010,
2530		.enable_mask = BIT(10),
2531		.hw.init = &(struct clk_init_data){
2532			.name = "gcc_qupv3_wrap2_s6_clk",
2533			.parent_hws = (const struct clk_hw*[]) {
2534				&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
2535			},
2536			.num_parents = 1,
2537			.flags = CLK_SET_RATE_PARENT,
2538			.ops = &clk_branch2_ops,
2539		},
2540	},
2541};
2542
2543static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2544	.halt_reg = 0x27004,
2545	.halt_check = BRANCH_HALT_VOTED,
2546	.hwcg_reg = 0x27004,
2547	.hwcg_bit = 1,
2548	.clkr = {
2549		.enable_reg = 0x62008,
2550		.enable_mask = BIT(6),
2551		.hw.init = &(struct clk_init_data){
2552			.name = "gcc_qupv3_wrap_0_m_ahb_clk",
2553			.ops = &clk_branch2_ops,
2554		},
2555	},
2556};
2557
2558static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2559	.halt_reg = 0x27008,
2560	.halt_check = BRANCH_HALT_VOTED,
2561	.hwcg_reg = 0x27008,
2562	.hwcg_bit = 1,
2563	.clkr = {
2564		.enable_reg = 0x62008,
2565		.enable_mask = BIT(7),
2566		.hw.init = &(struct clk_init_data){
2567			.name = "gcc_qupv3_wrap_0_s_ahb_clk",
2568			.ops = &clk_branch2_ops,
2569		},
2570	},
2571};
2572
2573static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2574	.halt_reg = 0x28004,
2575	.halt_check = BRANCH_HALT_VOTED,
2576	.hwcg_reg = 0x28004,
2577	.hwcg_bit = 1,
2578	.clkr = {
2579		.enable_reg = 0x62008,
2580		.enable_mask = BIT(20),
2581		.hw.init = &(struct clk_init_data){
2582			.name = "gcc_qupv3_wrap_1_m_ahb_clk",
2583			.ops = &clk_branch2_ops,
2584		},
2585	},
2586};
2587
2588static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2589	.halt_reg = 0x28008,
2590	.halt_check = BRANCH_HALT_VOTED,
2591	.hwcg_reg = 0x28008,
2592	.hwcg_bit = 1,
2593	.clkr = {
2594		.enable_reg = 0x62008,
2595		.enable_mask = BIT(21),
2596		.hw.init = &(struct clk_init_data){
2597			.name = "gcc_qupv3_wrap_1_s_ahb_clk",
2598			.ops = &clk_branch2_ops,
2599		},
2600	},
2601};
2602
2603static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2604	.halt_reg = 0x2e004,
2605	.halt_check = BRANCH_HALT_VOTED,
2606	.hwcg_reg = 0x2e004,
2607	.hwcg_bit = 1,
2608	.clkr = {
2609		.enable_reg = 0x62010,
2610		.enable_mask = BIT(2),
2611		.hw.init = &(struct clk_init_data){
2612			.name = "gcc_qupv3_wrap_2_m_ahb_clk",
2613			.ops = &clk_branch2_ops,
2614		},
2615	},
2616};
2617
2618static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2619	.halt_reg = 0x2e008,
2620	.halt_check = BRANCH_HALT_VOTED,
2621	.hwcg_reg = 0x2e008,
2622	.hwcg_bit = 1,
2623	.clkr = {
2624		.enable_reg = 0x62010,
2625		.enable_mask = BIT(1),
2626		.hw.init = &(struct clk_init_data){
2627			.name = "gcc_qupv3_wrap_2_s_ahb_clk",
2628			.ops = &clk_branch2_ops,
2629		},
2630	},
2631};
2632
2633static struct clk_branch gcc_sdcc2_ahb_clk = {
2634	.halt_reg = 0x2400c,
2635	.halt_check = BRANCH_HALT,
2636	.clkr = {
2637		.enable_reg = 0x2400c,
2638		.enable_mask = BIT(0),
2639		.hw.init = &(struct clk_init_data){
2640			.name = "gcc_sdcc2_ahb_clk",
2641			.ops = &clk_branch2_ops,
2642		},
2643	},
2644};
2645
2646static struct clk_branch gcc_sdcc2_apps_clk = {
2647	.halt_reg = 0x24004,
2648	.halt_check = BRANCH_HALT,
2649	.clkr = {
2650		.enable_reg = 0x24004,
2651		.enable_mask = BIT(0),
2652		.hw.init = &(struct clk_init_data){
2653			.name = "gcc_sdcc2_apps_clk",
2654			.parent_hws = (const struct clk_hw*[]) {
2655				&gcc_sdcc2_apps_clk_src.clkr.hw,
2656			},
2657			.num_parents = 1,
2658			.flags = CLK_SET_RATE_PARENT,
2659			.ops = &clk_branch2_ops,
2660		},
2661	},
2662};
2663
2664static struct clk_branch gcc_sdcc2_at_clk = {
2665	.halt_reg = 0x24010,
2666	.halt_check = BRANCH_HALT_VOTED,
2667	.hwcg_reg = 0x24010,
2668	.hwcg_bit = 1,
2669	.clkr = {
2670		.enable_reg = 0x24010,
2671		.enable_mask = BIT(0),
2672		.hw.init = &(struct clk_init_data){
2673			.name = "gcc_sdcc2_at_clk",
2674			.ops = &clk_branch2_ops,
2675		},
2676	},
2677};
2678
2679static struct clk_branch gcc_sdcc4_ahb_clk = {
2680	.halt_reg = 0x2600c,
2681	.halt_check = BRANCH_HALT,
2682	.clkr = {
2683		.enable_reg = 0x2600c,
2684		.enable_mask = BIT(0),
2685		.hw.init = &(struct clk_init_data){
2686			.name = "gcc_sdcc4_ahb_clk",
2687			.ops = &clk_branch2_ops,
2688		},
2689	},
2690};
2691
2692static struct clk_branch gcc_sdcc4_apps_clk = {
2693	.halt_reg = 0x26004,
2694	.halt_check = BRANCH_HALT,
2695	.clkr = {
2696		.enable_reg = 0x26004,
2697		.enable_mask = BIT(0),
2698		.hw.init = &(struct clk_init_data){
2699			.name = "gcc_sdcc4_apps_clk",
2700			.parent_hws = (const struct clk_hw*[]) {
2701				&gcc_sdcc4_apps_clk_src.clkr.hw,
2702			},
2703			.num_parents = 1,
2704			.flags = CLK_SET_RATE_PARENT,
2705			.ops = &clk_branch2_ops,
2706		},
2707	},
2708};
2709
2710static struct clk_branch gcc_sdcc4_at_clk = {
2711	.halt_reg = 0x26010,
2712	.halt_check = BRANCH_HALT_VOTED,
2713	.hwcg_reg = 0x26010,
2714	.hwcg_bit = 1,
2715	.clkr = {
2716		.enable_reg = 0x26010,
2717		.enable_mask = BIT(0),
2718		.hw.init = &(struct clk_init_data){
2719			.name = "gcc_sdcc4_at_clk",
2720			.ops = &clk_branch2_ops,
2721		},
2722	},
2723};
2724
2725static struct clk_branch gcc_ufs_0_clkref_en = {
2726	.halt_reg = 0x9c000,
2727	.halt_check = BRANCH_HALT,
2728	.clkr = {
2729		.enable_reg = 0x9c000,
2730		.enable_mask = BIT(0),
2731		.hw.init = &(struct clk_init_data){
2732			.name = "gcc_ufs_0_clkref_en",
2733			.ops = &clk_branch2_ops,
2734		},
2735	},
2736};
2737
2738static struct clk_branch gcc_ufs_phy_ahb_clk = {
2739	.halt_reg = 0x87020,
2740	.halt_check = BRANCH_HALT_VOTED,
2741	.hwcg_reg = 0x87020,
2742	.hwcg_bit = 1,
2743	.clkr = {
2744		.enable_reg = 0x87020,
2745		.enable_mask = BIT(0),
2746		.hw.init = &(struct clk_init_data){
2747			.name = "gcc_ufs_phy_ahb_clk",
2748			.ops = &clk_branch2_ops,
2749		},
2750	},
2751};
2752
2753static struct clk_branch gcc_ufs_phy_axi_clk = {
2754	.halt_reg = 0x87018,
2755	.halt_check = BRANCH_HALT_VOTED,
2756	.hwcg_reg = 0x87018,
2757	.hwcg_bit = 1,
2758	.clkr = {
2759		.enable_reg = 0x87018,
2760		.enable_mask = BIT(0),
2761		.hw.init = &(struct clk_init_data){
2762			.name = "gcc_ufs_phy_axi_clk",
2763			.parent_hws = (const struct clk_hw*[]) {
2764				&gcc_ufs_phy_axi_clk_src.clkr.hw,
2765			},
2766			.num_parents = 1,
2767			.flags = CLK_SET_RATE_PARENT,
2768			.ops = &clk_branch2_ops,
2769		},
2770	},
2771};
2772
2773static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2774	.halt_reg = 0x87018,
2775	.halt_check = BRANCH_HALT_VOTED,
2776	.hwcg_reg = 0x87018,
2777	.hwcg_bit = 1,
2778	.clkr = {
2779		.enable_reg = 0x87018,
2780		.enable_mask = BIT(1),
2781		.hw.init = &(struct clk_init_data){
2782			.name = "gcc_ufs_phy_axi_hw_ctl_clk",
2783			.parent_hws = (const struct clk_hw*[]) {
2784				&gcc_ufs_phy_axi_clk_src.clkr.hw,
2785			},
2786			.num_parents = 1,
2787			.flags = CLK_SET_RATE_PARENT,
2788			.ops = &clk_branch2_ops,
2789		},
2790	},
2791};
2792
2793static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2794	.halt_reg = 0x8706c,
2795	.halt_check = BRANCH_HALT_VOTED,
2796	.hwcg_reg = 0x8706c,
2797	.hwcg_bit = 1,
2798	.clkr = {
2799		.enable_reg = 0x8706c,
2800		.enable_mask = BIT(0),
2801		.hw.init = &(struct clk_init_data){
2802			.name = "gcc_ufs_phy_ice_core_clk",
2803			.parent_hws = (const struct clk_hw*[]) {
2804				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2805			},
2806			.num_parents = 1,
2807			.flags = CLK_SET_RATE_PARENT,
2808			.ops = &clk_branch2_ops,
2809		},
2810	},
2811};
2812
2813static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2814	.halt_reg = 0x8706c,
2815	.halt_check = BRANCH_HALT_VOTED,
2816	.hwcg_reg = 0x8706c,
2817	.hwcg_bit = 1,
2818	.clkr = {
2819		.enable_reg = 0x8706c,
2820		.enable_mask = BIT(1),
2821		.hw.init = &(struct clk_init_data){
2822			.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2823			.parent_hws = (const struct clk_hw*[]) {
2824				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2825			},
2826			.num_parents = 1,
2827			.flags = CLK_SET_RATE_PARENT,
2828			.ops = &clk_branch2_ops,
2829		},
2830	},
2831};
2832
2833static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2834	.halt_reg = 0x870a4,
2835	.halt_check = BRANCH_HALT_VOTED,
2836	.hwcg_reg = 0x870a4,
2837	.hwcg_bit = 1,
2838	.clkr = {
2839		.enable_reg = 0x870a4,
2840		.enable_mask = BIT(0),
2841		.hw.init = &(struct clk_init_data){
2842			.name = "gcc_ufs_phy_phy_aux_clk",
2843			.parent_hws = (const struct clk_hw*[]) {
2844				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2845			},
2846			.num_parents = 1,
2847			.flags = CLK_SET_RATE_PARENT,
2848			.ops = &clk_branch2_ops,
2849		},
2850	},
2851};
2852
2853static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2854	.halt_reg = 0x870a4,
2855	.halt_check = BRANCH_HALT_VOTED,
2856	.hwcg_reg = 0x870a4,
2857	.hwcg_bit = 1,
2858	.clkr = {
2859		.enable_reg = 0x870a4,
2860		.enable_mask = BIT(1),
2861		.hw.init = &(struct clk_init_data){
2862			.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2863			.parent_hws = (const struct clk_hw*[]) {
2864				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2865			},
2866			.num_parents = 1,
2867			.flags = CLK_SET_RATE_PARENT,
2868			.ops = &clk_branch2_ops,
2869		},
2870	},
2871};
2872
2873static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2874	.halt_reg = 0x87028,
2875	.halt_check = BRANCH_HALT_DELAY,
2876	.clkr = {
2877		.enable_reg = 0x87028,
2878		.enable_mask = BIT(0),
2879		.hw.init = &(struct clk_init_data){
2880			.name = "gcc_ufs_phy_rx_symbol_0_clk",
2881			.parent_hws = (const struct clk_hw*[]) {
2882				&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
2883			},
2884			.num_parents = 1,
2885			.flags = CLK_SET_RATE_PARENT,
2886			.ops = &clk_branch2_ops,
2887		},
2888	},
2889};
2890
2891static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2892	.halt_reg = 0x870c0,
2893	.halt_check = BRANCH_HALT_DELAY,
2894	.clkr = {
2895		.enable_reg = 0x870c0,
2896		.enable_mask = BIT(0),
2897		.hw.init = &(struct clk_init_data){
2898			.name = "gcc_ufs_phy_rx_symbol_1_clk",
2899			.parent_hws = (const struct clk_hw*[]) {
2900				&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
2901			},
2902			.num_parents = 1,
2903			.flags = CLK_SET_RATE_PARENT,
2904			.ops = &clk_branch2_ops,
2905		},
2906	},
2907};
2908
2909static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2910	.halt_reg = 0x87024,
2911	.halt_check = BRANCH_HALT_DELAY,
2912	.clkr = {
2913		.enable_reg = 0x87024,
2914		.enable_mask = BIT(0),
2915		.hw.init = &(struct clk_init_data){
2916			.name = "gcc_ufs_phy_tx_symbol_0_clk",
2917			.parent_hws = (const struct clk_hw*[]) {
2918				&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
2919			},
2920			.num_parents = 1,
2921			.flags = CLK_SET_RATE_PARENT,
2922			.ops = &clk_branch2_ops,
2923		},
2924	},
2925};
2926
2927static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2928	.halt_reg = 0x87064,
2929	.halt_check = BRANCH_HALT_VOTED,
2930	.hwcg_reg = 0x87064,
2931	.hwcg_bit = 1,
2932	.clkr = {
2933		.enable_reg = 0x87064,
2934		.enable_mask = BIT(0),
2935		.hw.init = &(struct clk_init_data){
2936			.name = "gcc_ufs_phy_unipro_core_clk",
2937			.parent_hws = (const struct clk_hw*[]) {
2938				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2939			},
2940			.num_parents = 1,
2941			.flags = CLK_SET_RATE_PARENT,
2942			.ops = &clk_branch2_ops,
2943		},
2944	},
2945};
2946
2947static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
2948	.halt_reg = 0x87064,
2949	.halt_check = BRANCH_HALT_VOTED,
2950	.hwcg_reg = 0x87064,
2951	.hwcg_bit = 1,
2952	.clkr = {
2953		.enable_reg = 0x87064,
2954		.enable_mask = BIT(1),
2955		.hw.init = &(struct clk_init_data){
2956			.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
2957			.parent_hws = (const struct clk_hw*[]) {
2958				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2959			},
2960			.num_parents = 1,
2961			.flags = CLK_SET_RATE_PARENT,
2962			.ops = &clk_branch2_ops,
2963		},
2964	},
2965};
2966
2967static struct clk_branch gcc_usb30_prim_master_clk = {
2968	.halt_reg = 0x49018,
2969	.halt_check = BRANCH_HALT,
2970	.clkr = {
2971		.enable_reg = 0x49018,
2972		.enable_mask = BIT(0),
2973		.hw.init = &(struct clk_init_data){
2974			.name = "gcc_usb30_prim_master_clk",
2975			.parent_hws = (const struct clk_hw*[]) {
2976				&gcc_usb30_prim_master_clk_src.clkr.hw,
2977			},
2978			.num_parents = 1,
2979			.flags = CLK_SET_RATE_PARENT,
2980			.ops = &clk_branch2_ops,
2981		},
2982	},
2983};
2984
2985static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2986	.halt_reg = 0x49024,
2987	.halt_check = BRANCH_HALT,
2988	.clkr = {
2989		.enable_reg = 0x49024,
2990		.enable_mask = BIT(0),
2991		.hw.init = &(struct clk_init_data){
2992			.name = "gcc_usb30_prim_mock_utmi_clk",
2993			.parent_hws = (const struct clk_hw*[]) {
2994				&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2995			},
2996			.num_parents = 1,
2997			.flags = CLK_SET_RATE_PARENT,
2998			.ops = &clk_branch2_ops,
2999		},
3000	},
3001};
3002
3003static struct clk_branch gcc_usb30_prim_sleep_clk = {
3004	.halt_reg = 0x49020,
3005	.halt_check = BRANCH_HALT,
3006	.clkr = {
3007		.enable_reg = 0x49020,
3008		.enable_mask = BIT(0),
3009		.hw.init = &(struct clk_init_data){
3010			.name = "gcc_usb30_prim_sleep_clk",
3011			.ops = &clk_branch2_ops,
3012		},
3013	},
3014};
3015
3016static struct clk_branch gcc_usb3_0_clkref_en = {
3017	.halt_reg = 0x9c010,
3018	.halt_check = BRANCH_HALT,
3019	.clkr = {
3020		.enable_reg = 0x9c010,
3021		.enable_mask = BIT(0),
3022		.hw.init = &(struct clk_init_data){
3023			.name = "gcc_usb3_0_clkref_en",
3024			.ops = &clk_branch2_ops,
3025		},
3026	},
3027};
3028
3029static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3030	.halt_reg = 0x4905c,
3031	.halt_check = BRANCH_HALT,
3032	.clkr = {
3033		.enable_reg = 0x4905c,
3034		.enable_mask = BIT(0),
3035		.hw.init = &(struct clk_init_data){
3036			.name = "gcc_usb3_prim_phy_aux_clk",
3037			.parent_hws = (const struct clk_hw*[]) {
3038				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3039			},
3040			.num_parents = 1,
3041			.flags = CLK_SET_RATE_PARENT,
3042			.ops = &clk_branch2_ops,
3043		},
3044	},
3045};
3046
3047static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3048	.halt_reg = 0x49060,
3049	.halt_check = BRANCH_HALT,
3050	.clkr = {
3051		.enable_reg = 0x49060,
3052		.enable_mask = BIT(0),
3053		.hw.init = &(struct clk_init_data){
3054			.name = "gcc_usb3_prim_phy_com_aux_clk",
3055			.parent_hws = (const struct clk_hw*[]) {
3056				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3057			},
3058			.num_parents = 1,
3059			.flags = CLK_SET_RATE_PARENT,
3060			.ops = &clk_branch2_ops,
3061		},
3062	},
3063};
3064
3065static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3066	.halt_reg = 0x49064,
3067	.halt_check = BRANCH_HALT_DELAY,
3068	.hwcg_reg = 0x49064,
3069	.hwcg_bit = 1,
3070	.clkr = {
3071		.enable_reg = 0x49064,
3072		.enable_mask = BIT(0),
3073		.hw.init = &(struct clk_init_data){
3074			.name = "gcc_usb3_prim_phy_pipe_clk",
3075			.parent_hws = (const struct clk_hw*[]) {
3076				&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
3077			},
3078			.num_parents = 1,
3079			.flags = CLK_SET_RATE_PARENT,
3080			.ops = &clk_branch2_ops,
3081		},
3082	},
3083};
3084
3085static struct clk_branch gcc_video_axi0_clk = {
3086	.halt_reg = 0x42018,
3087	.halt_check = BRANCH_HALT_SKIP,
3088	.hwcg_reg = 0x42018,
3089	.hwcg_bit = 1,
3090	.clkr = {
3091		.enable_reg = 0x42018,
3092		.enable_mask = BIT(0),
3093		.hw.init = &(struct clk_init_data){
3094			.name = "gcc_video_axi0_clk",
3095			.ops = &clk_branch2_ops,
3096		},
3097	},
3098};
3099
3100static struct clk_branch gcc_video_axi1_clk = {
3101	.halt_reg = 0x42020,
3102	.halt_check = BRANCH_HALT_SKIP,
3103	.hwcg_reg = 0x42020,
3104	.hwcg_bit = 1,
3105	.clkr = {
3106		.enable_reg = 0x42020,
3107		.enable_mask = BIT(0),
3108		.hw.init = &(struct clk_init_data){
3109			.name = "gcc_video_axi1_clk",
3110			.ops = &clk_branch2_ops,
3111		},
3112	},
3113};
3114
3115static struct gdsc pcie_0_gdsc = {
3116	.gdscr = 0x7b004,
3117	.pd = {
3118		.name = "pcie_0_gdsc",
3119	},
3120	.pwrsts = PWRSTS_RET_ON,
3121};
3122
3123static struct gdsc pcie_1_gdsc = {
3124	.gdscr = 0x9d004,
3125	.pd = {
3126		.name = "pcie_1_gdsc",
3127	},
3128	.pwrsts = PWRSTS_RET_ON,
3129};
3130
3131static struct gdsc ufs_phy_gdsc = {
3132	.gdscr = 0x87004,
3133	.pd = {
3134		.name = "ufs_phy_gdsc",
3135	},
3136	.pwrsts = PWRSTS_OFF_ON,
3137};
3138
3139static struct gdsc usb30_prim_gdsc = {
3140	.gdscr = 0x49004,
3141	.pd = {
3142		.name = "usb30_prim_gdsc",
3143	},
3144	.pwrsts = PWRSTS_OFF_ON,
3145};
3146
3147static struct clk_regmap *gcc_sm8450_clocks[] = {
3148	[GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
3149	[GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
3150	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3151	[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3152	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3153	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3154	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3155	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3156	[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
3157	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3158	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3159	[GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
3160	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3161	[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3162	[GCC_EUSB3_0_CLKREF_EN] = &gcc_eusb3_0_clkref_en.clkr,
3163	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3164	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3165	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3166	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3167	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3168	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3169	[GCC_GPLL0] = &gcc_gpll0.clkr,
3170	[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3171	[GCC_GPLL4] = &gcc_gpll4.clkr,
3172	[GCC_GPLL9] = &gcc_gpll9.clkr,
3173	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3174	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3175	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3176	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3177	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3178	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3179	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3180	[GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
3181	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3182	[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
3183	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3184	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3185	[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3186	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3187	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3188	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3189	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3190	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3191	[GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,
3192	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3193	[GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr,
3194	[GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr,
3195	[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
3196	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3197	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3198	[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3199	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3200	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3201	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3202	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3203	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3204	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3205	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3206	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3207	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3208	[GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
3209	[GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
3210	[GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
3211	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3212	[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
3213	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3214	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3215	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3216	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3217	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3218	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3219	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3220	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3221	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3222	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3223	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3224	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3225	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3226	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3227	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3228	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3229	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3230	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3231	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3232	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3233	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3234	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3235	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3236	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3237	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3238	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3239	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3240	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3241	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3242	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3243	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3244	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3245	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3246	[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3247	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3248	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
3249	[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
3250	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3251	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3252	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3253	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3254	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3255	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3256	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3257	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3258	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3259	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3260	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3261	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3262	[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
3263	[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
3264	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3265	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3266	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3267	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3268	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3269	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3270	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3271	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3272	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3273	[GCC_SDCC2_AT_CLK] = &gcc_sdcc2_at_clk.clkr,
3274	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3275	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3276	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3277	[GCC_SDCC4_AT_CLK] = &gcc_sdcc4_at_clk.clkr,
3278	[GCC_UFS_0_CLKREF_EN] = &gcc_ufs_0_clkref_en.clkr,
3279	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3280	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3281	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3282	[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3283	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3284	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3285	[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3286	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3287	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3288	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3289	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3290	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3291	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3292	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3293	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3294	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3295	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3296	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3297	[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3298	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3299	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3300	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3301	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3302	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3303	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3304	[GCC_USB3_0_CLKREF_EN] = &gcc_usb3_0_clkref_en.clkr,
3305	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3306	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3307	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3308	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3309	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3310	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3311	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3312	[SM8475_GCC_GPLL2] = NULL,
3313	[SM8475_GCC_GPLL3] = NULL,
3314};
3315
3316static const struct qcom_reset_map gcc_sm8450_resets[] = {
3317	[GCC_CAMERA_BCR] = { 0x36000 },
3318	[GCC_DISPLAY_BCR] = { 0x37000 },
3319	[GCC_GPU_BCR] = { 0x81000 },
3320	[GCC_PCIE_0_BCR] = { 0x7b000 },
3321	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 },
3322	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 },
3323	[GCC_PCIE_0_PHY_BCR] = { 0x7c01c },
3324	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 },
3325	[GCC_PCIE_1_BCR] = { 0x9d000 },
3326	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e014 },
3327	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x9e020 },
3328	[GCC_PCIE_1_PHY_BCR] = { 0x9e01c },
3329	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 },
3330	[GCC_PCIE_PHY_BCR] = { 0x7f000 },
3331	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
3332	[GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
3333	[GCC_PDM_BCR] = { 0x43000 },
3334	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },
3335	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },
3336	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x2e000 },
3337	[GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
3338	[GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
3339	[GCC_SDCC2_BCR] = { 0x24000 },
3340	[GCC_SDCC4_BCR] = { 0x26000 },
3341	[GCC_UFS_PHY_BCR] = { 0x87000 },
3342	[GCC_USB30_PRIM_BCR] = { 0x49000 },
3343	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
3344	[GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
3345	[GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
3346	[GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
3347	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
3348	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
3349	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
3350	[GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x42018, .bit = 2, .udelay = 1000 },
3351	[GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x42020, .bit = 2, .udelay = 1000 },
3352	[GCC_VIDEO_BCR] = { 0x42000 },
3353};
3354
3355static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3356	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3357	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3358	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3359	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3360	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3361	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3362	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3363	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3364	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3365	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3366	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3367	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3368	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3369	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3370	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3371	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
3372	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
3373	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
3374	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
3375	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
3376	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
3377	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
3378};
3379
3380static struct gdsc *gcc_sm8450_gdscs[] = {
3381	[PCIE_0_GDSC] = &pcie_0_gdsc,
3382	[PCIE_1_GDSC] = &pcie_1_gdsc,
3383	[UFS_PHY_GDSC] = &ufs_phy_gdsc,
3384	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3385};
3386
3387static const struct regmap_config gcc_sm8450_regmap_config = {
3388	.reg_bits = 32,
3389	.reg_stride = 4,
3390	.val_bits = 32,
3391	.max_register = 0x1f1030,
3392	.fast_io = true,
3393};
3394
3395static const struct qcom_cc_desc gcc_sm8450_desc = {
3396	.config = &gcc_sm8450_regmap_config,
3397	.clks = gcc_sm8450_clocks,
3398	.num_clks = ARRAY_SIZE(gcc_sm8450_clocks),
3399	.resets = gcc_sm8450_resets,
3400	.num_resets = ARRAY_SIZE(gcc_sm8450_resets),
3401	.gdscs = gcc_sm8450_gdscs,
3402	.num_gdscs = ARRAY_SIZE(gcc_sm8450_gdscs),
3403};
3404
3405static const struct of_device_id gcc_sm8450_match_table[] = {
3406	{ .compatible = "qcom,gcc-sm8450" },
3407	{ .compatible = "qcom,sm8475-gcc" },
3408	{ }
3409};
3410MODULE_DEVICE_TABLE(of, gcc_sm8450_match_table);
3411
3412static int gcc_sm8450_probe(struct platform_device *pdev)
3413{
3414	struct regmap *regmap;
3415	int ret;
3416
3417	regmap = qcom_cc_map(pdev, &gcc_sm8450_desc);
3418	if (IS_ERR(regmap))
3419		return PTR_ERR(regmap);
3420
3421	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3422				       ARRAY_SIZE(gcc_dfs_clocks));
3423	if (ret)
3424		return ret;
3425
3426	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-gcc")) {
3427		/* Update GCC PLL0 */
3428		gcc_gpll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3429		gcc_gpll0.clkr.hw.init = &sm8475_gcc_gpll0_init;
3430		gcc_gpll0_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3431		gcc_gpll0_out_even.clkr.hw.init = &sm8475_gcc_gpll0_out_even_init;
3432
3433		/* Update GCC PLL4 */
3434		gcc_gpll4.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3435		gcc_gpll4.clkr.hw.init = &sm8475_gcc_gpll4_init;
3436
3437		/* Update GCC PLL9 */
3438		gcc_gpll9.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3439		gcc_gpll9.clkr.hw.init = &sm8475_gcc_gpll9_init;
3440
3441		gcc_sdcc2_apps_clk_src.freq_tbl = sm8475_ftbl_gcc_sdcc2_apps_clk_src;
3442
3443		gcc_ufs_phy_axi_clk_src.parent_map = sm8475_gcc_parent_map_3;
3444		gcc_ufs_phy_axi_clk_src.freq_tbl = sm8475_ftbl_gcc_ufs_phy_axi_clk_src;
3445		gcc_ufs_phy_axi_clk_src.clkr.hw.init = &sm8475_gcc_ufs_phy_axi_clk_src_init;
3446
3447		gcc_ufs_phy_ice_core_clk_src.parent_map = sm8475_gcc_parent_map_3;
3448		gcc_ufs_phy_ice_core_clk_src.freq_tbl = sm8475_ftbl_gcc_ufs_phy_ice_core_clk_src;
3449		gcc_ufs_phy_ice_core_clk_src.clkr.hw.init = &sm8475_gcc_ufs_phy_ice_core_clk_src_init;
3450
3451		gcc_ufs_phy_unipro_core_clk_src.parent_map = sm8475_gcc_parent_map_3;
3452		gcc_ufs_phy_unipro_core_clk_src.freq_tbl = sm8475_ftbl_gcc_ufs_phy_ice_core_clk_src;
3453		gcc_ufs_phy_unipro_core_clk_src.clkr.hw.init = &sm8475_gcc_ufs_phy_unipro_core_clk_src_init;
3454
3455		gcc_sm8450_desc.clks[SM8475_GCC_GPLL2] = &sm8475_gcc_gpll2.clkr;
3456		gcc_sm8450_desc.clks[SM8475_GCC_GPLL3] = &sm8475_gcc_gpll3.clkr;
3457	}
3458
3459	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
3460	regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
3461
3462	/* Keep some clocks always-on */
3463	qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */
3464	qcom_branch_set_clk_en(regmap, 0x36020); /* GCC_CAMERA_XO_CLK */
3465	qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */
3466	qcom_branch_set_clk_en(regmap, 0x3701c); /* GCC_DISP_XO_CLK */
3467	qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */
3468	qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */
3469	qcom_branch_set_clk_en(regmap, 0x42028); /* GCC_VIDEO_XO_CLK */
3470
3471	return qcom_cc_really_probe(&pdev->dev, &gcc_sm8450_desc, regmap);
3472}
3473
3474static struct platform_driver gcc_sm8450_driver = {
3475	.probe = gcc_sm8450_probe,
3476	.driver = {
3477		.name = "gcc-sm8450",
3478		.of_match_table = gcc_sm8450_match_table,
3479	},
3480};
3481
3482static int __init gcc_sm8450_init(void)
3483{
3484	return platform_driver_register(&gcc_sm8450_driver);
3485}
3486subsys_initcall(gcc_sm8450_init);
3487
3488static void __exit gcc_sm8450_exit(void)
3489{
3490	platform_driver_unregister(&gcc_sm8450_driver);
3491}
3492module_exit(gcc_sm8450_exit);
3493
3494MODULE_DESCRIPTION("QTI GCC SM8450 / SM8475 Driver");
3495MODULE_LICENSE("GPL v2");