gcc-qcm2290.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/err.h>
   8#include <linux/kernel.h>
   9#include <linux/module.h>
  10#include <linux/platform_device.h>
  11#include <linux/regmap.h>
  12
  13#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
  14
  15#include "clk-alpha-pll.h"
  16#include "clk-branch.h"
  17#include "clk-rcg.h"
  18#include "clk-regmap-divider.h"
  19#include "common.h"
  20#include "gdsc.h"
  21#include "reset.h"
  22
  23enum {
  24	P_BI_TCXO,
  25	P_GPLL0_OUT_AUX2,
  26	P_GPLL0_OUT_EARLY,
  27	P_GPLL10_OUT_MAIN,
  28	P_GPLL11_OUT_AUX,
  29	P_GPLL11_OUT_AUX2,
  30	P_GPLL11_OUT_MAIN,
  31	P_GPLL3_OUT_EARLY,
  32	P_GPLL3_OUT_MAIN,
  33	P_GPLL4_OUT_MAIN,
  34	P_GPLL5_OUT_MAIN,
  35	P_GPLL6_OUT_EARLY,
  36	P_GPLL6_OUT_MAIN,
  37	P_GPLL7_OUT_MAIN,
  38	P_GPLL8_OUT_EARLY,
  39	P_GPLL8_OUT_MAIN,
  40	P_GPLL9_OUT_EARLY,
  41	P_GPLL9_OUT_MAIN,
  42	P_SLEEP_CLK,
  43};
  44
  45static const struct pll_vco brammo_vco[] = {
  46	{ 500000000, 1250000000, 0 },
  47};
  48
  49static const struct pll_vco default_vco[] = {
  50	{ 500000000, 1000000000, 2 },
  51};
  52
  53static const struct pll_vco spark_vco[] = {
  54	{ 750000000, 1500000000, 1 },
  55};
  56
  57static struct clk_alpha_pll gpll0 = {
  58	.offset = 0x0,
  59	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
  60	.clkr = {
  61		.enable_reg = 0x79000,
  62		.enable_mask = BIT(0),
  63		.hw.init = &(struct clk_init_data){
  64			.name = "gpll0",
  65			.parent_data = &(const struct clk_parent_data){
  66				.fw_name = "bi_tcxo",
  67			},
  68			.num_parents = 1,
  69			.ops = &clk_alpha_pll_ops,
  70		},
  71	},
  72};
  73
  74static const struct clk_div_table post_div_table_gpll0_out_aux2[] = {
  75	{ 0x1, 2 },
  76	{ }
  77};
  78
  79static struct clk_alpha_pll_postdiv gpll0_out_aux2 = {
  80	.offset = 0x0,
  81	.post_div_shift = 8,
  82	.post_div_table = post_div_table_gpll0_out_aux2,
  83	.num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_aux2),
  84	.width = 4,
  85	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
  86	.clkr.hw.init = &(struct clk_init_data){
  87		.name = "gpll0_out_aux2",
  88		.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
  89		.num_parents = 1,
  90		.ops = &clk_alpha_pll_postdiv_ro_ops,
  91	},
  92};
  93
  94static struct clk_alpha_pll gpll1 = {
  95	.offset = 0x1000,
  96	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
  97	.clkr = {
  98		.enable_reg = 0x79000,
  99		.enable_mask = BIT(1),
 100		.hw.init = &(struct clk_init_data){
 101			.name = "gpll1",
 102			.parent_data = &(const struct clk_parent_data){
 103				.fw_name = "bi_tcxo",
 104			},
 105			.num_parents = 1,
 106			.ops = &clk_alpha_pll_ops,
 107		},
 108	},
 109};
 110
 111/* 1152MHz configuration */
 112static const struct alpha_pll_config gpll10_config = {
 113	.l = 0x3c,
 114	.alpha = 0x0,
 115	.vco_val = 0x1 << 20,
 116	.vco_mask = GENMASK(21, 20),
 117	.main_output_mask = BIT(0),
 118	.config_ctl_val = 0x4001055B,
 119	.test_ctl_hi1_val = 0x1,
 120};
 121
 122static struct clk_alpha_pll gpll10 = {
 123	.offset = 0xa000,
 124	.vco_table = spark_vco,
 125	.num_vco = ARRAY_SIZE(spark_vco),
 126	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 127	.clkr = {
 128		.enable_reg = 0x79000,
 129		.enable_mask = BIT(10),
 130		.hw.init = &(struct clk_init_data){
 131			.name = "gpll10",
 132			.parent_data = &(const struct clk_parent_data){
 133				.fw_name = "bi_tcxo",
 134			},
 135			.num_parents = 1,
 136			.ops = &clk_alpha_pll_ops,
 137		},
 138	},
 139};
 140
 141/* 532MHz configuration */
 142static const struct alpha_pll_config gpll11_config = {
 143	.l = 0x1B,
 144	.alpha = 0x55555555,
 145	.alpha_hi = 0xB5,
 146	.alpha_en_mask = BIT(24),
 147	.vco_val = 0x2 << 20,
 148	.vco_mask = GENMASK(21, 20),
 149	.main_output_mask = BIT(0),
 150	.config_ctl_val = 0x4001055B,
 151	.test_ctl_hi1_val = 0x1,
 152};
 153
 154static struct clk_alpha_pll gpll11 = {
 155	.offset = 0xb000,
 156	.vco_table = default_vco,
 157	.num_vco = ARRAY_SIZE(default_vco),
 158	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 159	.flags = SUPPORTS_DYNAMIC_UPDATE,
 160	.clkr = {
 161		.enable_reg = 0x79000,
 162		.enable_mask = BIT(11),
 163		.hw.init = &(struct clk_init_data){
 164			.name = "gpll11",
 165			.parent_data = &(const struct clk_parent_data){
 166				.fw_name = "bi_tcxo",
 167			},
 168			.num_parents = 1,
 169			.ops = &clk_alpha_pll_ops,
 170		},
 171	},
 172};
 173
 174static struct clk_alpha_pll gpll3 = {
 175	.offset = 0x3000,
 176	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 177	.clkr = {
 178		.enable_reg = 0x79000,
 179		.enable_mask = BIT(3),
 180		.hw.init = &(struct clk_init_data){
 181			.name = "gpll3",
 182			.parent_data = &(const struct clk_parent_data){
 183				.fw_name = "bi_tcxo",
 184			},
 185			.num_parents = 1,
 186			.ops = &clk_alpha_pll_ops,
 187		},
 188	},
 189};
 190
 191static const struct clk_div_table post_div_table_gpll3_out_main[] = {
 192	{ 0x1, 2 },
 193	{ }
 194};
 195
 196static struct clk_alpha_pll_postdiv gpll3_out_main = {
 197	.offset = 0x3000,
 198	.post_div_shift = 8,
 199	.post_div_table = post_div_table_gpll3_out_main,
 200	.num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_main),
 201	.width = 4,
 202	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 203	.clkr.hw.init = &(struct clk_init_data){
 204		.name = "gpll3_out_main",
 205		.parent_hws = (const struct clk_hw *[]){ &gpll3.clkr.hw },
 206		.num_parents = 1,
 207		.ops = &clk_alpha_pll_postdiv_ro_ops,
 208	},
 209};
 210
 211static struct clk_alpha_pll gpll4 = {
 212	.offset = 0x4000,
 213	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 214	.clkr = {
 215		.enable_reg = 0x79000,
 216		.enable_mask = BIT(4),
 217		.hw.init = &(struct clk_init_data){
 218			.name = "gpll4",
 219			.parent_data = &(const struct clk_parent_data){
 220				.fw_name = "bi_tcxo",
 221			},
 222			.num_parents = 1,
 223			.ops = &clk_alpha_pll_ops,
 224		},
 225	},
 226};
 227
 228static struct clk_alpha_pll gpll5 = {
 229	.offset = 0x5000,
 230	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 231	.clkr = {
 232		.enable_reg = 0x79000,
 233		.enable_mask = BIT(5),
 234		.hw.init = &(struct clk_init_data){
 235			.name = "gpll5",
 236			.parent_data = &(const struct clk_parent_data){
 237				.fw_name = "bi_tcxo",
 238			},
 239			.num_parents = 1,
 240			.ops = &clk_alpha_pll_ops,
 241		},
 242	},
 243};
 244
 245static struct clk_alpha_pll gpll6 = {
 246	.offset = 0x6000,
 247	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 248	.clkr = {
 249		.enable_reg = 0x79000,
 250		.enable_mask = BIT(6),
 251		.hw.init = &(struct clk_init_data){
 252			.name = "gpll6",
 253			.parent_data = &(const struct clk_parent_data){
 254				.fw_name = "bi_tcxo",
 255			},
 256			.num_parents = 1,
 257			.ops = &clk_alpha_pll_ops,
 258		},
 259	},
 260};
 261
 262static const struct clk_div_table post_div_table_gpll6_out_main[] = {
 263	{ 0x1, 2 },
 264	{ }
 265};
 266
 267static struct clk_alpha_pll_postdiv gpll6_out_main = {
 268	.offset = 0x6000,
 269	.post_div_shift = 8,
 270	.post_div_table = post_div_table_gpll6_out_main,
 271	.num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_main),
 272	.width = 4,
 273	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 274	.clkr.hw.init = &(struct clk_init_data){
 275		.name = "gpll6_out_main",
 276		.parent_hws = (const struct clk_hw *[]){ &gpll6.clkr.hw },
 277		.num_parents = 1,
 278		.ops = &clk_alpha_pll_postdiv_ro_ops,
 279	},
 280};
 281
 282static struct clk_alpha_pll gpll7 = {
 283	.offset = 0x7000,
 284	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 285	.clkr = {
 286		.enable_reg = 0x79000,
 287		.enable_mask = BIT(7),
 288		.hw.init = &(struct clk_init_data){
 289			.name = "gpll7",
 290			.parent_data = &(const struct clk_parent_data){
 291				.fw_name = "bi_tcxo",
 292			},
 293			.num_parents = 1,
 294			.ops = &clk_alpha_pll_ops,
 295		},
 296	},
 297};
 298
 299/* 533.2MHz configuration */
 300static const struct alpha_pll_config gpll8_config = {
 301	.l = 0x1B,
 302	.alpha = 0x55555555,
 303	.alpha_hi = 0xC5,
 304	.alpha_en_mask = BIT(24),
 305	.vco_val = 0x2 << 20,
 306	.vco_mask = GENMASK(21, 20),
 307	.main_output_mask = BIT(0),
 308	.early_output_mask = BIT(3),
 309	.post_div_val = 0x1 << 8,
 310	.post_div_mask = GENMASK(11, 8),
 311	.config_ctl_val = 0x4001055B,
 312	.test_ctl_hi1_val = 0x1,
 313};
 314
 315static struct clk_alpha_pll gpll8 = {
 316	.offset = 0x8000,
 317	.vco_table = default_vco,
 318	.num_vco = ARRAY_SIZE(default_vco),
 319	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 320	.flags = SUPPORTS_DYNAMIC_UPDATE,
 321	.clkr = {
 322		.enable_reg = 0x79000,
 323		.enable_mask = BIT(8),
 324		.hw.init = &(struct clk_init_data){
 325			.name = "gpll8",
 326			.parent_data = &(const struct clk_parent_data){
 327				.fw_name = "bi_tcxo",
 328			},
 329			.num_parents = 1,
 330			.ops = &clk_alpha_pll_ops,
 331		},
 332	},
 333};
 334
 335static const struct clk_div_table post_div_table_gpll8_out_main[] = {
 336	{ 0x1, 2 },
 337	{ }
 338};
 339
 340static struct clk_alpha_pll_postdiv gpll8_out_main = {
 341	.offset = 0x8000,
 342	.post_div_shift = 8,
 343	.post_div_table = post_div_table_gpll8_out_main,
 344	.num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_main),
 345	.width = 4,
 346	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 347	.clkr.hw.init = &(struct clk_init_data){
 348		.name = "gpll8_out_main",
 349		.parent_hws = (const struct clk_hw *[]){ &gpll8.clkr.hw },
 350		.num_parents = 1,
 351		.flags = CLK_SET_RATE_PARENT,
 352		.ops = &clk_alpha_pll_postdiv_ro_ops,
 353	},
 354};
 355
 356/* 1152MHz configuration */
 357static const struct alpha_pll_config gpll9_config = {
 358	.l = 0x3C,
 359	.alpha = 0x0,
 360	.post_div_val = 0x1 << 8,
 361	.post_div_mask = GENMASK(9, 8),
 362	.main_output_mask = BIT(0),
 363	.early_output_mask = BIT(3),
 364	.config_ctl_val = 0x00004289,
 365	.test_ctl_val = 0x08000000,
 366};
 367
 368static struct clk_alpha_pll gpll9 = {
 369	.offset = 0x9000,
 370	.vco_table = brammo_vco,
 371	.num_vco = ARRAY_SIZE(brammo_vco),
 372	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
 373	.clkr = {
 374		.enable_reg = 0x79000,
 375		.enable_mask = BIT(9),
 376		.hw.init = &(struct clk_init_data){
 377			.name = "gpll9",
 378			.parent_data = &(const struct clk_parent_data){
 379				.fw_name = "bi_tcxo",
 380			},
 381			.num_parents = 1,
 382			.ops = &clk_alpha_pll_ops,
 383		},
 384	},
 385};
 386
 387static const struct clk_div_table post_div_table_gpll9_out_main[] = {
 388	{ 0x1, 2 },
 389	{ }
 390};
 391
 392static struct clk_alpha_pll_postdiv gpll9_out_main = {
 393	.offset = 0x9000,
 394	.post_div_shift = 8,
 395	.post_div_table = post_div_table_gpll9_out_main,
 396	.num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main),
 397	.width = 2,
 398	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO_EVO],
 399	.clkr.hw.init = &(struct clk_init_data){
 400		.name = "gpll9_out_main",
 401		.parent_hws = (const struct clk_hw *[]){ &gpll9.clkr.hw },
 402		.num_parents = 1,
 403		.flags = CLK_SET_RATE_PARENT,
 404		.ops = &clk_alpha_pll_postdiv_ro_ops,
 405	},
 406};
 407
 408static const struct parent_map gcc_parent_map_0[] = {
 409	{ P_BI_TCXO, 0 },
 410	{ P_GPLL0_OUT_EARLY, 1 },
 411	{ P_GPLL0_OUT_AUX2, 2 },
 412};
 413
 414static const struct clk_parent_data gcc_parents_0[] = {
 415	{ .fw_name = "bi_tcxo" },
 416	{ .hw = &gpll0.clkr.hw },
 417	{ .hw = &gpll0_out_aux2.clkr.hw },
 418};
 419
 420static const struct parent_map gcc_parent_map_1[] = {
 421	{ P_BI_TCXO, 0 },
 422	{ P_GPLL0_OUT_EARLY, 1 },
 423	{ P_GPLL0_OUT_AUX2, 2 },
 424	{ P_GPLL6_OUT_MAIN, 4 },
 425};
 426
 427static const struct clk_parent_data gcc_parents_1[] = {
 428	{ .fw_name = "bi_tcxo" },
 429	{ .hw = &gpll0.clkr.hw },
 430	{ .hw = &gpll0_out_aux2.clkr.hw },
 431	{ .hw = &gpll6_out_main.clkr.hw },
 432};
 433
 434static const struct parent_map gcc_parent_map_2[] = {
 435	{ P_BI_TCXO, 0 },
 436	{ P_GPLL0_OUT_EARLY, 1 },
 437	{ P_GPLL0_OUT_AUX2, 2 },
 438	{ P_SLEEP_CLK, 5 },
 439};
 440
 441static const struct clk_parent_data gcc_parents_2[] = {
 442	{ .fw_name = "bi_tcxo" },
 443	{ .hw = &gpll0.clkr.hw },
 444	{ .hw = &gpll0_out_aux2.clkr.hw },
 445	{ .fw_name = "sleep_clk" },
 446};
 447
 448static const struct parent_map gcc_parent_map_3[] = {
 449	{ P_BI_TCXO, 0 },
 450	{ P_GPLL0_OUT_EARLY, 1 },
 451	{ P_GPLL9_OUT_EARLY, 2 },
 452	{ P_GPLL10_OUT_MAIN, 3 },
 453	{ P_GPLL9_OUT_MAIN, 5 },
 454	{ P_GPLL3_OUT_MAIN, 6 },
 455};
 456
 457static const struct clk_parent_data gcc_parents_3[] = {
 458	{ .fw_name = "bi_tcxo" },
 459	{ .hw = &gpll0.clkr.hw },
 460	{ .hw = &gpll9.clkr.hw },
 461	{ .hw = &gpll10.clkr.hw },
 462	{ .hw = &gpll9_out_main.clkr.hw },
 463	{ .hw = &gpll3_out_main.clkr.hw },
 464};
 465
 466static const struct parent_map gcc_parent_map_4[] = {
 467	{ P_BI_TCXO, 0 },
 468	{ P_GPLL0_OUT_EARLY, 1 },
 469	{ P_GPLL0_OUT_AUX2, 2 },
 470	{ P_GPLL10_OUT_MAIN, 3 },
 471	{ P_GPLL4_OUT_MAIN, 5 },
 472	{ P_GPLL3_OUT_EARLY, 6 },
 473};
 474
 475static const struct clk_parent_data gcc_parents_4[] = {
 476	{ .fw_name = "bi_tcxo" },
 477	{ .hw = &gpll0.clkr.hw },
 478	{ .hw = &gpll0_out_aux2.clkr.hw },
 479	{ .hw = &gpll10.clkr.hw },
 480	{ .hw = &gpll4.clkr.hw },
 481	{ .hw = &gpll3.clkr.hw },
 482};
 483
 484static const struct parent_map gcc_parent_map_5[] = {
 485	{ P_BI_TCXO, 0 },
 486	{ P_GPLL0_OUT_EARLY, 1 },
 487	{ P_GPLL0_OUT_AUX2, 2 },
 488	{ P_GPLL4_OUT_MAIN, 5 },
 489	{ P_GPLL3_OUT_MAIN, 6 },
 490};
 491
 492static const struct clk_parent_data gcc_parents_5[] = {
 493	{ .fw_name = "bi_tcxo" },
 494	{ .hw = &gpll0.clkr.hw },
 495	{ .hw = &gpll0_out_aux2.clkr.hw },
 496	{ .hw = &gpll4.clkr.hw },
 497	{ .hw = &gpll3_out_main.clkr.hw },
 498};
 499
 500static const struct parent_map gcc_parent_map_6[] = {
 501	{ P_BI_TCXO, 0 },
 502	{ P_GPLL0_OUT_EARLY, 1 },
 503	{ P_GPLL8_OUT_EARLY, 2 },
 504	{ P_GPLL10_OUT_MAIN, 3 },
 505	{ P_GPLL8_OUT_MAIN, 4 },
 506	{ P_GPLL9_OUT_MAIN, 5 },
 507	{ P_GPLL3_OUT_EARLY, 6 },
 508};
 509
 510static const struct clk_parent_data gcc_parents_6[] = {
 511	{ .fw_name = "bi_tcxo" },
 512	{ .hw = &gpll0.clkr.hw },
 513	{ .hw = &gpll8.clkr.hw },
 514	{ .hw = &gpll10.clkr.hw },
 515	{ .hw = &gpll8_out_main.clkr.hw },
 516	{ .hw = &gpll9_out_main.clkr.hw },
 517	{ .hw = &gpll3.clkr.hw },
 518};
 519
 520static const struct parent_map gcc_parent_map_7[] = {
 521	{ P_BI_TCXO, 0 },
 522	{ P_GPLL0_OUT_EARLY, 1 },
 523	{ P_GPLL8_OUT_EARLY, 2 },
 524	{ P_GPLL10_OUT_MAIN, 3 },
 525	{ P_GPLL8_OUT_MAIN, 4 },
 526	{ P_GPLL9_OUT_MAIN, 5 },
 527	{ P_GPLL3_OUT_MAIN, 6 },
 528};
 529
 530static const struct clk_parent_data gcc_parents_7[] = {
 531	{ .fw_name = "bi_tcxo" },
 532	{ .hw = &gpll0.clkr.hw },
 533	{ .hw = &gpll8.clkr.hw },
 534	{ .hw = &gpll10.clkr.hw },
 535	{ .hw = &gpll8_out_main.clkr.hw },
 536	{ .hw = &gpll9_out_main.clkr.hw },
 537	{ .hw = &gpll3_out_main.clkr.hw },
 538};
 539
 540static const struct parent_map gcc_parent_map_8[] = {
 541	{ P_BI_TCXO, 0 },
 542	{ P_GPLL0_OUT_EARLY, 1 },
 543	{ P_GPLL8_OUT_EARLY, 2 },
 544	{ P_GPLL10_OUT_MAIN, 3 },
 545	{ P_GPLL6_OUT_MAIN, 4 },
 546	{ P_GPLL9_OUT_MAIN, 5 },
 547	{ P_GPLL3_OUT_EARLY, 6 },
 548};
 549
 550static const struct clk_parent_data gcc_parents_8[] = {
 551	{ .fw_name = "bi_tcxo" },
 552	{ .hw = &gpll0.clkr.hw },
 553	{ .hw = &gpll8.clkr.hw },
 554	{ .hw = &gpll10.clkr.hw },
 555	{ .hw = &gpll6_out_main.clkr.hw },
 556	{ .hw = &gpll9_out_main.clkr.hw },
 557	{ .hw = &gpll3.clkr.hw },
 558};
 559
 560static const struct parent_map gcc_parent_map_9[] = {
 561	{ P_BI_TCXO, 0 },
 562	{ P_GPLL0_OUT_EARLY, 1 },
 563	{ P_GPLL0_OUT_AUX2, 2 },
 564	{ P_GPLL10_OUT_MAIN, 3 },
 565	{ P_GPLL8_OUT_MAIN, 4 },
 566	{ P_GPLL9_OUT_MAIN, 5 },
 567	{ P_GPLL3_OUT_EARLY, 6 },
 568};
 569
 570static const struct clk_parent_data gcc_parents_9[] = {
 571	{ .fw_name = "bi_tcxo" },
 572	{ .hw = &gpll0.clkr.hw },
 573	{ .hw = &gpll0_out_aux2.clkr.hw },
 574	{ .hw = &gpll10.clkr.hw },
 575	{ .hw = &gpll8_out_main.clkr.hw },
 576	{ .hw = &gpll9_out_main.clkr.hw },
 577	{ .hw = &gpll3.clkr.hw },
 578};
 579
 580static const struct parent_map gcc_parent_map_10[] = {
 581	{ P_BI_TCXO, 0 },
 582	{ P_GPLL0_OUT_EARLY, 1 },
 583	{ P_GPLL8_OUT_EARLY, 2 },
 584	{ P_GPLL10_OUT_MAIN, 3 },
 585	{ P_GPLL6_OUT_EARLY, 5 },
 586	{ P_GPLL3_OUT_MAIN, 6 },
 587};
 588
 589static const struct clk_parent_data gcc_parents_10[] = {
 590	{ .fw_name = "bi_tcxo" },
 591	{ .hw = &gpll0.clkr.hw },
 592	{ .hw = &gpll8.clkr.hw },
 593	{ .hw = &gpll10.clkr.hw },
 594	{ .hw = &gpll6.clkr.hw },
 595	{ .hw = &gpll3_out_main.clkr.hw },
 596};
 597
 598static const struct parent_map gcc_parent_map_12[] = {
 599	{ P_BI_TCXO, 0 },
 600	{ P_GPLL0_OUT_EARLY, 1 },
 601	{ P_GPLL0_OUT_AUX2, 2 },
 602	{ P_GPLL7_OUT_MAIN, 3 },
 603	{ P_GPLL4_OUT_MAIN, 5 },
 604};
 605
 606static const struct clk_parent_data gcc_parents_12[] = {
 607	{ .fw_name = "bi_tcxo" },
 608	{ .hw = &gpll0.clkr.hw },
 609	{ .hw = &gpll0_out_aux2.clkr.hw },
 610	{ .hw = &gpll7.clkr.hw },
 611	{ .hw = &gpll4.clkr.hw },
 612};
 613
 614static const struct parent_map gcc_parent_map_13[] = {
 615	{ P_BI_TCXO, 0 },
 616	{ P_SLEEP_CLK, 5 },
 617};
 618
 619static const struct clk_parent_data gcc_parents_13[] = {
 620	{ .fw_name = "bi_tcxo" },
 621	{ .fw_name = "sleep_clk" },
 622};
 623
 624static const struct parent_map gcc_parent_map_14[] = {
 625	{ P_BI_TCXO, 0 },
 626	{ P_GPLL11_OUT_MAIN, 1 },
 627	{ P_GPLL11_OUT_AUX, 2 },
 628	{ P_GPLL11_OUT_AUX2, 3 },
 629};
 630
 631static const struct clk_parent_data gcc_parents_14[] = {
 632	{ .fw_name = "bi_tcxo" },
 633	{ .hw = &gpll11.clkr.hw },
 634	{ .hw = &gpll11.clkr.hw },
 635	{ .hw = &gpll11.clkr.hw },
 636};
 637
 638static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
 639	F(19200000, P_BI_TCXO, 1, 0, 0),
 640	{ }
 641};
 642
 643static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
 644	.cmd_rcgr = 0x1a034,
 645	.mnd_width = 0,
 646	.hid_width = 5,
 647	.parent_map = gcc_parent_map_0,
 648	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
 649	.clkr.hw.init = &(struct clk_init_data){
 650		.name = "gcc_usb30_prim_mock_utmi_clk_src",
 651		.parent_data = gcc_parents_0,
 652		.num_parents = ARRAY_SIZE(gcc_parents_0),
 653		.ops = &clk_rcg2_shared_ops,
 654	},
 655};
 656
 657static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv = {
 658	.reg = 0x1a04c,
 659	.shift = 0,
 660	.width = 2,
 661	.clkr.hw.init = &(struct clk_init_data) {
 662		.name = "gcc_usb30_prim_mock_utmi_postdiv",
 663		.parent_hws = (const struct clk_hw *[])
 664				{ &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
 665		.num_parents = 1,
 666		.flags = CLK_SET_RATE_PARENT,
 667		.ops = &clk_regmap_div_ro_ops,
 668	},
 669};
 670
 671static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = {
 672	F(19200000, P_BI_TCXO, 1, 0, 0),
 673	F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
 674	F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
 675	F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
 676	{ }
 677};
 678
 679static struct clk_rcg2 gcc_camss_axi_clk_src = {
 680	.cmd_rcgr = 0x5802c,
 681	.mnd_width = 0,
 682	.hid_width = 5,
 683	.parent_map = gcc_parent_map_4,
 684	.freq_tbl = ftbl_gcc_camss_axi_clk_src,
 685	.clkr.hw.init = &(struct clk_init_data){
 686		.name = "gcc_camss_axi_clk_src",
 687		.parent_data = gcc_parents_4,
 688		.num_parents = ARRAY_SIZE(gcc_parents_4),
 689		.ops = &clk_rcg2_shared_ops,
 690	},
 691};
 692
 693static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = {
 694	F(19200000, P_BI_TCXO, 1, 0, 0),
 695	F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
 696	{ }
 697};
 698
 699static struct clk_rcg2 gcc_camss_cci_clk_src = {
 700	.cmd_rcgr = 0x56000,
 701	.mnd_width = 0,
 702	.hid_width = 5,
 703	.parent_map = gcc_parent_map_9,
 704	.freq_tbl = ftbl_gcc_camss_cci_clk_src,
 705	.clkr.hw.init = &(struct clk_init_data){
 706		.name = "gcc_camss_cci_clk_src",
 707		.parent_data = gcc_parents_9,
 708		.num_parents = ARRAY_SIZE(gcc_parents_9),
 709		.ops = &clk_rcg2_shared_ops,
 710	},
 711};
 712
 713static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = {
 714	F(19200000, P_BI_TCXO, 1, 0, 0),
 715	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
 716	F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
 717	F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
 718	{ }
 719};
 720
 721static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
 722	.cmd_rcgr = 0x45000,
 723	.mnd_width = 0,
 724	.hid_width = 5,
 725	.parent_map = gcc_parent_map_5,
 726	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
 727	.clkr.hw.init = &(struct clk_init_data){
 728		.name = "gcc_camss_csi0phytimer_clk_src",
 729		.parent_data = gcc_parents_5,
 730		.num_parents = ARRAY_SIZE(gcc_parents_5),
 731		.ops = &clk_rcg2_shared_ops,
 732	},
 733};
 734
 735static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
 736	.cmd_rcgr = 0x4501c,
 737	.mnd_width = 0,
 738	.hid_width = 5,
 739	.parent_map = gcc_parent_map_5,
 740	.freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
 741	.clkr.hw.init = &(struct clk_init_data){
 742		.name = "gcc_camss_csi1phytimer_clk_src",
 743		.parent_data = gcc_parents_5,
 744		.num_parents = ARRAY_SIZE(gcc_parents_5),
 745		.ops = &clk_rcg2_shared_ops,
 746	},
 747};
 748
 749static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {
 750	F(19200000, P_BI_TCXO, 1, 0, 0),
 751	F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24),
 752	F(64000000, P_GPLL9_OUT_EARLY, 9, 1, 2),
 753	{ }
 754};
 755
 756static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
 757	.cmd_rcgr = 0x51000,
 758	.mnd_width = 8,
 759	.hid_width = 5,
 760	.parent_map = gcc_parent_map_3,
 761	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
 762	.clkr.hw.init = &(struct clk_init_data){
 763		.name = "gcc_camss_mclk0_clk_src",
 764		.parent_data = gcc_parents_3,
 765		.num_parents = ARRAY_SIZE(gcc_parents_3),
 766		.flags = CLK_OPS_PARENT_ENABLE,
 767		.ops = &clk_rcg2_shared_ops,
 768	},
 769};
 770
 771static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
 772	.cmd_rcgr = 0x5101c,
 773	.mnd_width = 8,
 774	.hid_width = 5,
 775	.parent_map = gcc_parent_map_3,
 776	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
 777	.clkr.hw.init = &(struct clk_init_data){
 778		.name = "gcc_camss_mclk1_clk_src",
 779		.parent_data = gcc_parents_3,
 780		.num_parents = ARRAY_SIZE(gcc_parents_3),
 781		.flags = CLK_OPS_PARENT_ENABLE,
 782		.ops = &clk_rcg2_shared_ops,
 783	},
 784};
 785
 786static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
 787	.cmd_rcgr = 0x51038,
 788	.mnd_width = 8,
 789	.hid_width = 5,
 790	.parent_map = gcc_parent_map_3,
 791	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
 792	.clkr.hw.init = &(struct clk_init_data){
 793		.name = "gcc_camss_mclk2_clk_src",
 794		.parent_data = gcc_parents_3,
 795		.num_parents = ARRAY_SIZE(gcc_parents_3),
 796		.flags = CLK_OPS_PARENT_ENABLE,
 797		.ops = &clk_rcg2_shared_ops,
 798	},
 799};
 800
 801static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
 802	.cmd_rcgr = 0x51054,
 803	.mnd_width = 8,
 804	.hid_width = 5,
 805	.parent_map = gcc_parent_map_3,
 806	.freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
 807	.clkr.hw.init = &(struct clk_init_data){
 808		.name = "gcc_camss_mclk3_clk_src",
 809		.parent_data = gcc_parents_3,
 810		.num_parents = ARRAY_SIZE(gcc_parents_3),
 811		.flags = CLK_OPS_PARENT_ENABLE,
 812		.ops = &clk_rcg2_shared_ops,
 813	},
 814};
 815
 816static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = {
 817	F(19200000, P_BI_TCXO, 1, 0, 0),
 818	F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0),
 819	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
 820	{ }
 821};
 822
 823static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
 824	.cmd_rcgr = 0x55024,
 825	.mnd_width = 0,
 826	.hid_width = 5,
 827	.parent_map = gcc_parent_map_6,
 828	.freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src,
 829	.clkr.hw.init = &(struct clk_init_data){
 830		.name = "gcc_camss_ope_ahb_clk_src",
 831		.parent_data = gcc_parents_6,
 832		.num_parents = ARRAY_SIZE(gcc_parents_6),
 833		.ops = &clk_rcg2_shared_ops,
 834	},
 835};
 836
 837static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = {
 838	F(19200000, P_BI_TCXO, 1, 0, 0),
 839	F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
 840	F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0),
 841	F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
 842	F(580000000, P_GPLL8_OUT_EARLY, 1, 0, 0),
 843	{ }
 844};
 845
 846static struct clk_rcg2 gcc_camss_ope_clk_src = {
 847	.cmd_rcgr = 0x55004,
 848	.mnd_width = 0,
 849	.hid_width = 5,
 850	.parent_map = gcc_parent_map_6,
 851	.freq_tbl = ftbl_gcc_camss_ope_clk_src,
 852	.clkr.hw.init = &(struct clk_init_data){
 853		.name = "gcc_camss_ope_clk_src",
 854		.parent_data = gcc_parents_6,
 855		.num_parents = ARRAY_SIZE(gcc_parents_6),
 856		.flags = CLK_SET_RATE_PARENT,
 857		.ops = &clk_rcg2_shared_ops,
 858	},
 859};
 860
 861static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = {
 862	F(19200000, P_BI_TCXO, 1, 0, 0),
 863	F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0),
 864	F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0),
 865	F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0),
 866	F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0),
 867	F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0),
 868	F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0),
 869	F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0),
 870	F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0),
 871	F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0),
 872	F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0),
 873	F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0),
 874	F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0),
 875	F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0),
 876	F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0),
 877	F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0),
 878	{ }
 879};
 880
 881static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
 882	.cmd_rcgr = 0x52004,
 883	.mnd_width = 8,
 884	.hid_width = 5,
 885	.parent_map = gcc_parent_map_7,
 886	.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
 887	.clkr.hw.init = &(struct clk_init_data){
 888		.name = "gcc_camss_tfe_0_clk_src",
 889		.parent_data = gcc_parents_7,
 890		.num_parents = ARRAY_SIZE(gcc_parents_7),
 891		.ops = &clk_rcg2_shared_ops,
 892	},
 893};
 894
 895static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = {
 896	F(19200000, P_BI_TCXO, 1, 0, 0),
 897	F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0),
 898	F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
 899	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
 900	F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
 901	F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0),
 902	{ }
 903};
 904
 905static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
 906	.cmd_rcgr = 0x52094,
 907	.mnd_width = 0,
 908	.hid_width = 5,
 909	.parent_map = gcc_parent_map_8,
 910	.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
 911	.clkr.hw.init = &(struct clk_init_data){
 912		.name = "gcc_camss_tfe_0_csid_clk_src",
 913		.parent_data = gcc_parents_8,
 914		.num_parents = ARRAY_SIZE(gcc_parents_8),
 915		.ops = &clk_rcg2_shared_ops,
 916	},
 917};
 918
 919static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
 920	.cmd_rcgr = 0x52024,
 921	.mnd_width = 8,
 922	.hid_width = 5,
 923	.parent_map = gcc_parent_map_7,
 924	.freq_tbl = ftbl_gcc_camss_tfe_0_clk_src,
 925	.clkr.hw.init = &(struct clk_init_data){
 926		.name = "gcc_camss_tfe_1_clk_src",
 927		.parent_data = gcc_parents_7,
 928		.num_parents = ARRAY_SIZE(gcc_parents_7),
 929		.ops = &clk_rcg2_shared_ops,
 930	},
 931};
 932
 933static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
 934	.cmd_rcgr = 0x520b4,
 935	.mnd_width = 0,
 936	.hid_width = 5,
 937	.parent_map = gcc_parent_map_8,
 938	.freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src,
 939	.clkr.hw.init = &(struct clk_init_data){
 940		.name = "gcc_camss_tfe_1_csid_clk_src",
 941		.parent_data = gcc_parents_8,
 942		.num_parents = ARRAY_SIZE(gcc_parents_8),
 943		.ops = &clk_rcg2_shared_ops,
 944	},
 945};
 946
 947static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = {
 948	F(19200000, P_BI_TCXO, 1, 0, 0),
 949	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
 950	F(341333333, P_GPLL6_OUT_EARLY, 1, 4, 9),
 951	F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0),
 952	{ }
 953};
 954
 955static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
 956	.cmd_rcgr = 0x52064,
 957	.mnd_width = 16,
 958	.hid_width = 5,
 959	.parent_map = gcc_parent_map_10,
 960	.freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src,
 961	.clkr.hw.init = &(struct clk_init_data){
 962		.name = "gcc_camss_tfe_cphy_rx_clk_src",
 963		.parent_data = gcc_parents_10,
 964		.num_parents = ARRAY_SIZE(gcc_parents_10),
 965		.flags = CLK_OPS_PARENT_ENABLE,
 966		.ops = &clk_rcg2_shared_ops,
 967	},
 968};
 969
 970static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = {
 971	F(19200000, P_BI_TCXO, 1, 0, 0),
 972	F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
 973	F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0),
 974	{ }
 975};
 976
 977static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
 978	.cmd_rcgr = 0x58010,
 979	.mnd_width = 0,
 980	.hid_width = 5,
 981	.parent_map = gcc_parent_map_4,
 982	.freq_tbl = ftbl_gcc_camss_top_ahb_clk_src,
 983	.clkr.hw.init = &(struct clk_init_data){
 984		.name = "gcc_camss_top_ahb_clk_src",
 985		.parent_data = gcc_parents_4,
 986		.num_parents = ARRAY_SIZE(gcc_parents_4),
 987		.ops = &clk_rcg2_shared_ops,
 988	},
 989};
 990
 991static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 992	F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
 993	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
 994	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
 995	F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
 996	{ }
 997};
 998
 999static struct clk_rcg2 gcc_gp1_clk_src = {
1000	.cmd_rcgr = 0x4d004,
1001	.mnd_width = 8,
1002	.hid_width = 5,
1003	.parent_map = gcc_parent_map_2,
1004	.freq_tbl = ftbl_gcc_gp1_clk_src,
1005	.clkr.hw.init = &(struct clk_init_data){
1006		.name = "gcc_gp1_clk_src",
1007		.parent_data = gcc_parents_2,
1008		.num_parents = ARRAY_SIZE(gcc_parents_2),
1009		.ops = &clk_rcg2_shared_ops,
1010	},
1011};
1012
1013static struct clk_rcg2 gcc_gp2_clk_src = {
1014	.cmd_rcgr = 0x4e004,
1015	.mnd_width = 8,
1016	.hid_width = 5,
1017	.parent_map = gcc_parent_map_2,
1018	.freq_tbl = ftbl_gcc_gp1_clk_src,
1019	.clkr.hw.init = &(struct clk_init_data){
1020		.name = "gcc_gp2_clk_src",
1021		.parent_data = gcc_parents_2,
1022		.num_parents = ARRAY_SIZE(gcc_parents_2),
1023		.ops = &clk_rcg2_shared_ops,
1024	},
1025};
1026
1027static struct clk_rcg2 gcc_gp3_clk_src = {
1028	.cmd_rcgr = 0x4f004,
1029	.mnd_width = 8,
1030	.hid_width = 5,
1031	.parent_map = gcc_parent_map_2,
1032	.freq_tbl = ftbl_gcc_gp1_clk_src,
1033	.clkr.hw.init = &(struct clk_init_data){
1034		.name = "gcc_gp3_clk_src",
1035		.parent_data = gcc_parents_2,
1036		.num_parents = ARRAY_SIZE(gcc_parents_2),
1037		.ops = &clk_rcg2_shared_ops,
1038	},
1039};
1040
1041static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
1042	F(19200000, P_BI_TCXO, 1, 0, 0),
1043	F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0),
1044	{ }
1045};
1046
1047static struct clk_rcg2 gcc_pdm2_clk_src = {
1048	.cmd_rcgr = 0x20010,
1049	.mnd_width = 0,
1050	.hid_width = 5,
1051	.parent_map = gcc_parent_map_0,
1052	.freq_tbl = ftbl_gcc_pdm2_clk_src,
1053	.clkr.hw.init = &(struct clk_init_data){
1054		.name = "gcc_pdm2_clk_src",
1055		.parent_data = gcc_parents_0,
1056		.num_parents = ARRAY_SIZE(gcc_parents_0),
1057		.ops = &clk_rcg2_shared_ops,
1058	},
1059};
1060
1061static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
1062	F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625),
1063	F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625),
1064	F(19200000, P_BI_TCXO, 1, 0, 0),
1065	F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625),
1066	F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75),
1067	F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25),
1068	F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75),
1069	F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1070	F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15),
1071	F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25),
1072	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1073	F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375),
1074	F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75),
1075	F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625),
1076	F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
1077	F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
1078	{ }
1079};
1080
1081static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
1082	.name = "gcc_qupv3_wrap0_s0_clk_src",
1083	.parent_data = gcc_parents_1,
1084	.num_parents = ARRAY_SIZE(gcc_parents_1),
1085	.ops = &clk_rcg2_shared_ops,
1086};
1087
1088static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
1089	.cmd_rcgr = 0x1f148,
1090	.mnd_width = 16,
1091	.hid_width = 5,
1092	.parent_map = gcc_parent_map_1,
1093	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1094	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
1095};
1096
1097static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
1098	.name = "gcc_qupv3_wrap0_s1_clk_src",
1099	.parent_data = gcc_parents_1,
1100	.num_parents = ARRAY_SIZE(gcc_parents_1),
1101	.ops = &clk_rcg2_shared_ops,
1102};
1103
1104static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
1105	.cmd_rcgr = 0x1f278,
1106	.mnd_width = 16,
1107	.hid_width = 5,
1108	.parent_map = gcc_parent_map_1,
1109	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1110	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
1111};
1112
1113static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
1114	.name = "gcc_qupv3_wrap0_s2_clk_src",
1115	.parent_data = gcc_parents_1,
1116	.num_parents = ARRAY_SIZE(gcc_parents_1),
1117	.ops = &clk_rcg2_shared_ops,
1118};
1119
1120static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
1121	.cmd_rcgr = 0x1f3a8,
1122	.mnd_width = 16,
1123	.hid_width = 5,
1124	.parent_map = gcc_parent_map_1,
1125	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1126	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
1127};
1128
1129static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
1130	.name = "gcc_qupv3_wrap0_s3_clk_src",
1131	.parent_data = gcc_parents_1,
1132	.num_parents = ARRAY_SIZE(gcc_parents_1),
1133	.ops = &clk_rcg2_shared_ops,
1134};
1135
1136static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
1137	.cmd_rcgr = 0x1f4d8,
1138	.mnd_width = 16,
1139	.hid_width = 5,
1140	.parent_map = gcc_parent_map_1,
1141	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1142	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
1143};
1144
1145static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
1146	.name = "gcc_qupv3_wrap0_s4_clk_src",
1147	.parent_data = gcc_parents_1,
1148	.num_parents = ARRAY_SIZE(gcc_parents_1),
1149	.ops = &clk_rcg2_shared_ops,
1150};
1151
1152static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
1153	.cmd_rcgr = 0x1f608,
1154	.mnd_width = 16,
1155	.hid_width = 5,
1156	.parent_map = gcc_parent_map_1,
1157	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1158	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
1159};
1160
1161static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
1162	.name = "gcc_qupv3_wrap0_s5_clk_src",
1163	.parent_data = gcc_parents_1,
1164	.num_parents = ARRAY_SIZE(gcc_parents_1),
1165	.ops = &clk_rcg2_shared_ops,
1166};
1167
1168static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
1169	.cmd_rcgr = 0x1f738,
1170	.mnd_width = 16,
1171	.hid_width = 5,
1172	.parent_map = gcc_parent_map_1,
1173	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1174	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
1175};
1176
1177static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
1178	F(144000, P_BI_TCXO, 16, 3, 25),
1179	F(400000, P_BI_TCXO, 12, 1, 4),
1180	F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3),
1181	F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2),
1182	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1183	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1184	F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1185	F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
1186	{ }
1187};
1188
1189static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
1190	.cmd_rcgr = 0x38028,
1191	.mnd_width = 8,
1192	.hid_width = 5,
1193	.parent_map = gcc_parent_map_1,
1194	.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
1195	.clkr.hw.init = &(struct clk_init_data){
1196		.name = "gcc_sdcc1_apps_clk_src",
1197		.parent_data = gcc_parents_1,
1198		.num_parents = ARRAY_SIZE(gcc_parents_1),
1199		.ops = &clk_rcg2_floor_ops,
1200	},
1201};
1202
1203static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
1204	F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1205	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1206	F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1207	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1208	F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
1209	{ }
1210};
1211
1212static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
1213	.cmd_rcgr = 0x38010,
1214	.mnd_width = 0,
1215	.hid_width = 5,
1216	.parent_map = gcc_parent_map_0,
1217	.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
1218	.clkr.hw.init = &(struct clk_init_data){
1219		.name = "gcc_sdcc1_ice_core_clk_src",
1220		.parent_data = gcc_parents_0,
1221		.num_parents = ARRAY_SIZE(gcc_parents_0),
1222		.ops = &clk_rcg2_shared_ops,
1223	},
1224};
1225
1226static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1227	F(400000, P_BI_TCXO, 12, 1, 4),
1228	F(19200000, P_BI_TCXO, 1, 0, 0),
1229	F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1230	F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1231	F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1232	F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
1233	{ }
1234};
1235
1236static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1237	.cmd_rcgr = 0x1e00c,
1238	.mnd_width = 8,
1239	.hid_width = 5,
1240	.parent_map = gcc_parent_map_12,
1241	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1242	.clkr.hw.init = &(struct clk_init_data){
1243		.name = "gcc_sdcc2_apps_clk_src",
1244		.parent_data = gcc_parents_12,
1245		.num_parents = ARRAY_SIZE(gcc_parents_12),
1246		.ops = &clk_rcg2_floor_ops,
1247		.flags = CLK_OPS_PARENT_ENABLE,
1248	},
1249};
1250
1251static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1252	F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
1253	F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
1254	F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1255	F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1256	{ }
1257};
1258
1259static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1260	.cmd_rcgr = 0x1a01c,
1261	.mnd_width = 8,
1262	.hid_width = 5,
1263	.parent_map = gcc_parent_map_0,
1264	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1265	.clkr.hw.init = &(struct clk_init_data){
1266		.name = "gcc_usb30_prim_master_clk_src",
1267		.parent_data = gcc_parents_0,
1268		.num_parents = ARRAY_SIZE(gcc_parents_0),
1269		.ops = &clk_rcg2_shared_ops,
1270	},
1271};
1272
1273static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1274	.cmd_rcgr = 0x1a060,
1275	.mnd_width = 0,
1276	.hid_width = 5,
1277	.parent_map = gcc_parent_map_13,
1278	.freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1279	.clkr.hw.init = &(struct clk_init_data){
1280		.name = "gcc_usb3_prim_phy_aux_clk_src",
1281		.parent_data = gcc_parents_13,
1282		.num_parents = ARRAY_SIZE(gcc_parents_13),
1283		.ops = &clk_rcg2_shared_ops,
1284	},
1285};
1286
1287static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = {
1288	F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0),
1289	F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0),
1290	F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1291	F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1292	{ }
1293};
1294
1295static struct clk_rcg2 gcc_video_venus_clk_src = {
1296	.cmd_rcgr = 0x58060,
1297	.mnd_width = 0,
1298	.hid_width = 5,
1299	.parent_map = gcc_parent_map_14,
1300	.freq_tbl = ftbl_gcc_video_venus_clk_src,
1301	.clkr.hw.init = &(struct clk_init_data){
1302		.name = "gcc_video_venus_clk_src",
1303		.parent_data = gcc_parents_14,
1304		.num_parents = ARRAY_SIZE(gcc_parents_14),
1305		.flags = CLK_SET_RATE_PARENT,
1306		.ops = &clk_rcg2_shared_ops,
1307	},
1308};
1309
1310static struct clk_branch gcc_ahb2phy_csi_clk = {
1311	.halt_reg = 0x1d004,
1312	.halt_check = BRANCH_HALT_DELAY,
1313	.hwcg_reg = 0x1d004,
1314	.hwcg_bit = 1,
1315	.clkr = {
1316		.enable_reg = 0x1d004,
1317		.enable_mask = BIT(0),
1318		.hw.init = &(struct clk_init_data){
1319			.name = "gcc_ahb2phy_csi_clk",
1320			.ops = &clk_branch2_ops,
1321		},
1322	},
1323};
1324
1325static struct clk_branch gcc_ahb2phy_usb_clk = {
1326	.halt_reg = 0x1d008,
1327	.halt_check = BRANCH_HALT,
1328	.hwcg_reg = 0x1d008,
1329	.hwcg_bit = 1,
1330	.clkr = {
1331		.enable_reg = 0x1d008,
1332		.enable_mask = BIT(0),
1333		.hw.init = &(struct clk_init_data){
1334			.name = "gcc_ahb2phy_usb_clk",
1335			.ops = &clk_branch2_ops,
1336		},
1337	},
1338};
1339
1340static struct clk_branch gcc_bimc_gpu_axi_clk = {
1341	.halt_reg = 0x71154,
1342	.halt_check = BRANCH_HALT_DELAY,
1343	.hwcg_reg = 0x71154,
1344	.hwcg_bit = 1,
1345	.clkr = {
1346		.enable_reg = 0x71154,
1347		.enable_mask = BIT(0),
1348		.hw.init = &(struct clk_init_data){
1349			.name = "gcc_bimc_gpu_axi_clk",
1350			.ops = &clk_branch2_ops,
1351		},
1352	},
1353};
1354
1355static struct clk_branch gcc_boot_rom_ahb_clk = {
1356	.halt_reg = 0x23004,
1357	.halt_check = BRANCH_HALT_VOTED,
1358	.hwcg_reg = 0x23004,
1359	.hwcg_bit = 1,
1360	.clkr = {
1361		.enable_reg = 0x79004,
1362		.enable_mask = BIT(10),
1363		.hw.init = &(struct clk_init_data){
1364			.name = "gcc_boot_rom_ahb_clk",
1365			.ops = &clk_branch2_ops,
1366		},
1367	},
1368};
1369
1370static struct clk_branch gcc_cam_throttle_nrt_clk = {
1371	.halt_reg = 0x17070,
1372	.halt_check = BRANCH_HALT_VOTED,
1373	.hwcg_reg = 0x17070,
1374	.hwcg_bit = 1,
1375	.clkr = {
1376		.enable_reg = 0x79004,
1377		.enable_mask = BIT(27),
1378		.hw.init = &(struct clk_init_data){
1379			.name = "gcc_cam_throttle_nrt_clk",
1380			.ops = &clk_branch2_ops,
1381		},
1382	},
1383};
1384
1385static struct clk_branch gcc_cam_throttle_rt_clk = {
1386	.halt_reg = 0x1706c,
1387	.halt_check = BRANCH_HALT_VOTED,
1388	.hwcg_reg = 0x1706c,
1389	.hwcg_bit = 1,
1390	.clkr = {
1391		.enable_reg = 0x79004,
1392		.enable_mask = BIT(26),
1393		.hw.init = &(struct clk_init_data){
1394			.name = "gcc_cam_throttle_rt_clk",
1395			.ops = &clk_branch2_ops,
1396		},
1397	},
1398};
1399
1400static struct clk_branch gcc_camera_ahb_clk = {
1401	.halt_reg = 0x17008,
1402	.halt_check = BRANCH_HALT_DELAY,
1403	.hwcg_reg = 0x17008,
1404	.hwcg_bit = 1,
1405	.clkr = {
1406		.enable_reg = 0x17008,
1407		.enable_mask = BIT(0),
1408		.hw.init = &(struct clk_init_data){
1409			.name = "gcc_camera_ahb_clk",
1410			.flags = CLK_IS_CRITICAL,
1411			.ops = &clk_branch2_ops,
1412		},
1413	},
1414};
1415
1416static struct clk_branch gcc_camera_xo_clk = {
1417	.halt_reg = 0x17028,
1418	.halt_check = BRANCH_HALT,
1419	.clkr = {
1420		.enable_reg = 0x17028,
1421		.enable_mask = BIT(0),
1422		.hw.init = &(struct clk_init_data){
1423			.name = "gcc_camera_xo_clk",
1424			.flags = CLK_IS_CRITICAL,
1425			.ops = &clk_branch2_ops,
1426		},
1427	},
1428};
1429
1430static struct clk_branch gcc_camss_axi_clk = {
1431	.halt_reg = 0x58044,
1432	.halt_check = BRANCH_HALT,
1433	.clkr = {
1434		.enable_reg = 0x58044,
1435		.enable_mask = BIT(0),
1436		.hw.init = &(struct clk_init_data){
1437			.name = "gcc_camss_axi_clk",
1438			.parent_hws = (const struct clk_hw *[])
1439					{ &gcc_camss_axi_clk_src.clkr.hw },
1440			.num_parents = 1,
1441			.flags = CLK_SET_RATE_PARENT,
1442			.ops = &clk_branch2_ops,
1443		},
1444	},
1445};
1446
1447static struct clk_branch gcc_camss_camnoc_atb_clk = {
1448	.halt_reg = 0x5804c,
1449	.halt_check = BRANCH_HALT_DELAY,
1450	.hwcg_reg = 0x5804c,
1451	.hwcg_bit = 1,
1452	.clkr = {
1453		.enable_reg = 0x5804c,
1454		.enable_mask = BIT(0),
1455		.hw.init = &(struct clk_init_data){
1456			.name = "gcc_camss_camnoc_atb_clk",
1457			.ops = &clk_branch2_ops,
1458		},
1459	},
1460};
1461
1462static struct clk_branch gcc_camss_camnoc_nts_xo_clk = {
1463	.halt_reg = 0x58050,
1464	.halt_check = BRANCH_HALT_DELAY,
1465	.hwcg_reg = 0x58050,
1466	.hwcg_bit = 1,
1467	.clkr = {
1468		.enable_reg = 0x58050,
1469		.enable_mask = BIT(0),
1470		.hw.init = &(struct clk_init_data){
1471			.name = "gcc_camss_camnoc_nts_xo_clk",
1472			.ops = &clk_branch2_ops,
1473		},
1474	},
1475};
1476
1477static struct clk_branch gcc_camss_cci_0_clk = {
1478	.halt_reg = 0x56018,
1479	.halt_check = BRANCH_HALT,
1480	.clkr = {
1481		.enable_reg = 0x56018,
1482		.enable_mask = BIT(0),
1483		.hw.init = &(struct clk_init_data){
1484			.name = "gcc_camss_cci_0_clk",
1485			.parent_hws = (const struct clk_hw *[])
1486					{ &gcc_camss_cci_clk_src.clkr.hw },
1487			.num_parents = 1,
1488			.flags = CLK_SET_RATE_PARENT,
1489			.ops = &clk_branch2_ops,
1490		},
1491	},
1492};
1493
1494static struct clk_branch gcc_camss_cphy_0_clk = {
1495	.halt_reg = 0x52088,
1496	.halt_check = BRANCH_HALT,
1497	.clkr = {
1498		.enable_reg = 0x52088,
1499		.enable_mask = BIT(0),
1500		.hw.init = &(struct clk_init_data){
1501			.name = "gcc_camss_cphy_0_clk",
1502			.parent_hws = (const struct clk_hw *[])
1503				{ &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw },
1504			.num_parents = 1,
1505			.flags = CLK_SET_RATE_PARENT,
1506			.ops = &clk_branch2_ops,
1507		},
1508	},
1509};
1510
1511static struct clk_branch gcc_camss_cphy_1_clk = {
1512	.halt_reg = 0x5208c,
1513	.halt_check = BRANCH_HALT,
1514	.clkr = {
1515		.enable_reg = 0x5208c,
1516		.enable_mask = BIT(0),
1517		.hw.init = &(struct clk_init_data){
1518			.name = "gcc_camss_cphy_1_clk",
1519			.parent_hws = (const struct clk_hw *[])
1520				{ &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw },
1521			.num_parents = 1,
1522			.flags = CLK_SET_RATE_PARENT,
1523			.ops = &clk_branch2_ops,
1524		},
1525	},
1526};
1527
1528static struct clk_branch gcc_camss_csi0phytimer_clk = {
1529	.halt_reg = 0x45018,
1530	.halt_check = BRANCH_HALT,
1531	.clkr = {
1532		.enable_reg = 0x45018,
1533		.enable_mask = BIT(0),
1534		.hw.init = &(struct clk_init_data){
1535			.name = "gcc_camss_csi0phytimer_clk",
1536			.parent_hws = (const struct clk_hw *[])
1537				{ &gcc_camss_csi0phytimer_clk_src.clkr.hw },
1538			.num_parents = 1,
1539			.flags = CLK_SET_RATE_PARENT,
1540			.ops = &clk_branch2_ops,
1541		},
1542	},
1543};
1544
1545static struct clk_branch gcc_camss_csi1phytimer_clk = {
1546	.halt_reg = 0x45034,
1547	.halt_check = BRANCH_HALT,
1548	.clkr = {
1549		.enable_reg = 0x45034,
1550		.enable_mask = BIT(0),
1551		.hw.init = &(struct clk_init_data){
1552			.name = "gcc_camss_csi1phytimer_clk",
1553			.parent_hws = (const struct clk_hw *[])
1554				{ &gcc_camss_csi1phytimer_clk_src.clkr.hw },
1555			.num_parents = 1,
1556			.flags = CLK_SET_RATE_PARENT,
1557			.ops = &clk_branch2_ops,
1558		},
1559	},
1560};
1561
1562static struct clk_branch gcc_camss_mclk0_clk = {
1563	.halt_reg = 0x51018,
1564	.halt_check = BRANCH_HALT,
1565	.clkr = {
1566		.enable_reg = 0x51018,
1567		.enable_mask = BIT(0),
1568		.hw.init = &(struct clk_init_data){
1569			.name = "gcc_camss_mclk0_clk",
1570			.parent_hws = (const struct clk_hw *[])
1571					{ &gcc_camss_mclk0_clk_src.clkr.hw },
1572			.num_parents = 1,
1573			.flags = CLK_SET_RATE_PARENT,
1574			.ops = &clk_branch2_ops,
1575		},
1576	},
1577};
1578
1579static struct clk_branch gcc_camss_mclk1_clk = {
1580	.halt_reg = 0x51034,
1581	.halt_check = BRANCH_HALT,
1582	.clkr = {
1583		.enable_reg = 0x51034,
1584		.enable_mask = BIT(0),
1585		.hw.init = &(struct clk_init_data){
1586			.name = "gcc_camss_mclk1_clk",
1587			.parent_hws = (const struct clk_hw *[])
1588					{ &gcc_camss_mclk1_clk_src.clkr.hw },
1589			.num_parents = 1,
1590			.flags = CLK_SET_RATE_PARENT,
1591			.ops = &clk_branch2_ops,
1592		},
1593	},
1594};
1595
1596static struct clk_branch gcc_camss_mclk2_clk = {
1597	.halt_reg = 0x51050,
1598	.halt_check = BRANCH_HALT,
1599	.clkr = {
1600		.enable_reg = 0x51050,
1601		.enable_mask = BIT(0),
1602		.hw.init = &(struct clk_init_data){
1603			.name = "gcc_camss_mclk2_clk",
1604			.parent_hws = (const struct clk_hw *[])
1605					{ &gcc_camss_mclk2_clk_src.clkr.hw },
1606			.num_parents = 1,
1607			.flags = CLK_SET_RATE_PARENT,
1608			.ops = &clk_branch2_ops,
1609		},
1610	},
1611};
1612
1613static struct clk_branch gcc_camss_mclk3_clk = {
1614	.halt_reg = 0x5106c,
1615	.halt_check = BRANCH_HALT,
1616	.clkr = {
1617		.enable_reg = 0x5106c,
1618		.enable_mask = BIT(0),
1619		.hw.init = &(struct clk_init_data){
1620			.name = "gcc_camss_mclk3_clk",
1621			.parent_hws = (const struct clk_hw *[])
1622					{ &gcc_camss_mclk3_clk_src.clkr.hw },
1623			.num_parents = 1,
1624			.flags = CLK_SET_RATE_PARENT,
1625			.ops = &clk_branch2_ops,
1626		},
1627	},
1628};
1629
1630static struct clk_branch gcc_camss_nrt_axi_clk = {
1631	.halt_reg = 0x58054,
1632	.halt_check = BRANCH_HALT,
1633	.clkr = {
1634		.enable_reg = 0x58054,
1635		.enable_mask = BIT(0),
1636		.hw.init = &(struct clk_init_data){
1637			.name = "gcc_camss_nrt_axi_clk",
1638			.ops = &clk_branch2_ops,
1639		},
1640	},
1641};
1642
1643static struct clk_branch gcc_camss_ope_ahb_clk = {
1644	.halt_reg = 0x5503c,
1645	.halt_check = BRANCH_HALT,
1646	.clkr = {
1647		.enable_reg = 0x5503c,
1648		.enable_mask = BIT(0),
1649		.hw.init = &(struct clk_init_data){
1650			.name = "gcc_camss_ope_ahb_clk",
1651			.parent_hws = (const struct clk_hw *[])
1652					{ &gcc_camss_ope_ahb_clk_src.clkr.hw },
1653			.num_parents = 1,
1654			.flags = CLK_SET_RATE_PARENT,
1655			.ops = &clk_branch2_ops,
1656		},
1657	},
1658};
1659
1660static struct clk_branch gcc_camss_ope_clk = {
1661	.halt_reg = 0x5501c,
1662	.halt_check = BRANCH_HALT,
1663	.clkr = {
1664		.enable_reg = 0x5501c,
1665		.enable_mask = BIT(0),
1666		.hw.init = &(struct clk_init_data){
1667			.name = "gcc_camss_ope_clk",
1668			.parent_hws = (const struct clk_hw *[])
1669					{ &gcc_camss_ope_clk_src.clkr.hw },
1670			.num_parents = 1,
1671			.flags = CLK_SET_RATE_PARENT,
1672			.ops = &clk_branch2_ops,
1673		},
1674	},
1675};
1676
1677static struct clk_branch gcc_camss_rt_axi_clk = {
1678	.halt_reg = 0x5805c,
1679	.halt_check = BRANCH_HALT,
1680	.clkr = {
1681		.enable_reg = 0x5805c,
1682		.enable_mask = BIT(0),
1683		.hw.init = &(struct clk_init_data){
1684			.name = "gcc_camss_rt_axi_clk",
1685			.ops = &clk_branch2_ops,
1686		},
1687	},
1688};
1689
1690static struct clk_branch gcc_camss_tfe_0_clk = {
1691	.halt_reg = 0x5201c,
1692	.halt_check = BRANCH_HALT,
1693	.clkr = {
1694		.enable_reg = 0x5201c,
1695		.enable_mask = BIT(0),
1696		.hw.init = &(struct clk_init_data){
1697			.name = "gcc_camss_tfe_0_clk",
1698			.parent_hws = (const struct clk_hw *[])
1699					{ &gcc_camss_tfe_0_clk_src.clkr.hw },
1700			.num_parents = 1,
1701			.flags = CLK_SET_RATE_PARENT,
1702			.ops = &clk_branch2_ops,
1703		},
1704	},
1705};
1706
1707static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = {
1708	.halt_reg = 0x5207c,
1709	.halt_check = BRANCH_HALT,
1710	.clkr = {
1711		.enable_reg = 0x5207c,
1712		.enable_mask = BIT(0),
1713		.hw.init = &(struct clk_init_data){
1714			.name = "gcc_camss_tfe_0_cphy_rx_clk",
1715			.parent_hws = (const struct clk_hw *[])
1716				{ &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw },
1717			.num_parents = 1,
1718			.flags = CLK_SET_RATE_PARENT,
1719			.ops = &clk_branch2_ops,
1720		},
1721	},
1722};
1723
1724static struct clk_branch gcc_camss_tfe_0_csid_clk = {
1725	.halt_reg = 0x520ac,
1726	.halt_check = BRANCH_HALT,
1727	.clkr = {
1728		.enable_reg = 0x520ac,
1729		.enable_mask = BIT(0),
1730		.hw.init = &(struct clk_init_data){
1731			.name = "gcc_camss_tfe_0_csid_clk",
1732			.parent_hws = (const struct clk_hw *[])
1733				{ &gcc_camss_tfe_0_csid_clk_src.clkr.hw },
1734			.num_parents = 1,
1735			.flags = CLK_SET_RATE_PARENT,
1736			.ops = &clk_branch2_ops,
1737		},
1738	},
1739};
1740
1741static struct clk_branch gcc_camss_tfe_1_clk = {
1742	.halt_reg = 0x5203c,
1743	.halt_check = BRANCH_HALT,
1744	.clkr = {
1745		.enable_reg = 0x5203c,
1746		.enable_mask = BIT(0),
1747		.hw.init = &(struct clk_init_data){
1748			.name = "gcc_camss_tfe_1_clk",
1749			.parent_hws = (const struct clk_hw *[])
1750					{ &gcc_camss_tfe_1_clk_src.clkr.hw },
1751			.num_parents = 1,
1752			.flags = CLK_SET_RATE_PARENT,
1753			.ops = &clk_branch2_ops,
1754		},
1755	},
1756};
1757
1758static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = {
1759	.halt_reg = 0x52080,
1760	.halt_check = BRANCH_HALT,
1761	.clkr = {
1762		.enable_reg = 0x52080,
1763		.enable_mask = BIT(0),
1764		.hw.init = &(struct clk_init_data){
1765			.name = "gcc_camss_tfe_1_cphy_rx_clk",
1766			.parent_hws = (const struct clk_hw *[])
1767				{ &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw },
1768			.num_parents = 1,
1769			.flags = CLK_SET_RATE_PARENT,
1770			.ops = &clk_branch2_ops,
1771		},
1772	},
1773};
1774
1775static struct clk_branch gcc_camss_tfe_1_csid_clk = {
1776	.halt_reg = 0x520cc,
1777	.halt_check = BRANCH_HALT,
1778	.clkr = {
1779		.enable_reg = 0x520cc,
1780		.enable_mask = BIT(0),
1781		.hw.init = &(struct clk_init_data){
1782			.name = "gcc_camss_tfe_1_csid_clk",
1783			.parent_hws = (const struct clk_hw *[])
1784				{ &gcc_camss_tfe_1_csid_clk_src.clkr.hw },
1785			.num_parents = 1,
1786			.flags = CLK_SET_RATE_PARENT,
1787			.ops = &clk_branch2_ops,
1788		},
1789	},
1790};
1791
1792static struct clk_branch gcc_camss_top_ahb_clk = {
1793	.halt_reg = 0x58028,
1794	.halt_check = BRANCH_HALT,
1795	.clkr = {
1796		.enable_reg = 0x58028,
1797		.enable_mask = BIT(0),
1798		.hw.init = &(struct clk_init_data){
1799			.name = "gcc_camss_top_ahb_clk",
1800			.parent_hws = (const struct clk_hw *[])
1801					{ &gcc_camss_top_ahb_clk_src.clkr.hw },
1802			.num_parents = 1,
1803			.flags = CLK_SET_RATE_PARENT,
1804			.ops = &clk_branch2_ops,
1805		},
1806	},
1807};
1808
1809static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1810	.halt_reg = 0x1a084,
1811	.halt_check = BRANCH_HALT,
1812	.hwcg_reg = 0x1a084,
1813	.hwcg_bit = 1,
1814	.clkr = {
1815		.enable_reg = 0x1a084,
1816		.enable_mask = BIT(0),
1817		.hw.init = &(struct clk_init_data){
1818			.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1819			.parent_hws = (const struct clk_hw *[])
1820				{ &gcc_usb30_prim_master_clk_src.clkr.hw },
1821			.num_parents = 1,
1822			.flags = CLK_SET_RATE_PARENT,
1823			.ops = &clk_branch2_ops,
1824		},
1825	},
1826};
1827
1828static struct clk_branch gcc_disp_ahb_clk = {
1829	.halt_reg = 0x1700c,
1830	.halt_check = BRANCH_HALT,
1831	.hwcg_reg = 0x1700c,
1832	.hwcg_bit = 1,
1833	.clkr = {
1834		.enable_reg = 0x1700c,
1835		.enable_mask = BIT(0),
1836		.hw.init = &(struct clk_init_data){
1837			.name = "gcc_disp_ahb_clk",
1838			.flags = CLK_IS_CRITICAL,
1839			.ops = &clk_branch2_ops,
1840		},
1841	},
1842};
1843
1844static struct clk_regmap_div gcc_disp_gpll0_clk_src = {
1845	.reg = 0x17058,
1846	.shift = 0,
1847	.width = 2,
1848	.clkr.hw.init = &(struct clk_init_data) {
1849		.name = "gcc_disp_gpll0_clk_src",
1850		.parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
1851		.num_parents = 1,
1852		.ops = &clk_regmap_div_ops,
1853	},
1854};
1855
1856static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1857	.halt_check = BRANCH_HALT_DELAY,
1858	.clkr = {
1859		.enable_reg = 0x79004,
1860		.enable_mask = BIT(20),
1861		.hw.init = &(struct clk_init_data){
1862			.name = "gcc_disp_gpll0_div_clk_src",
1863			.parent_hws = (const struct clk_hw *[])
1864					{ &gcc_disp_gpll0_clk_src.clkr.hw },
1865			.num_parents = 1,
1866			.flags = CLK_SET_RATE_PARENT,
1867			.ops = &clk_branch2_ops,
1868		},
1869	},
1870};
1871
1872static struct clk_branch gcc_disp_hf_axi_clk = {
1873	.halt_reg = 0x17020,
1874	.halt_check = BRANCH_HALT,
1875	.hwcg_reg = 0x17020,
1876	.hwcg_bit = 1,
1877	.clkr = {
1878		.enable_reg = 0x17020,
1879		.enable_mask = BIT(0),
1880		.hw.init = &(struct clk_init_data){
1881			.name = "gcc_disp_hf_axi_clk",
1882			.ops = &clk_branch2_ops,
1883		},
1884	},
1885};
1886
1887static struct clk_branch gcc_disp_throttle_core_clk = {
1888	.halt_reg = 0x17064,
1889	.halt_check = BRANCH_HALT_VOTED,
1890	.hwcg_reg = 0x17064,
1891	.hwcg_bit = 1,
1892	.clkr = {
1893		.enable_reg = 0x7900c,
1894		.enable_mask = BIT(5),
1895		.hw.init = &(struct clk_init_data){
1896			.name = "gcc_disp_throttle_core_clk",
1897			.ops = &clk_branch2_ops,
1898		},
1899	},
1900};
1901
1902static struct clk_branch gcc_disp_xo_clk = {
1903	.halt_reg = 0x1702c,
1904	.halt_check = BRANCH_HALT,
1905	.clkr = {
1906		.enable_reg = 0x1702c,
1907		.enable_mask = BIT(0),
1908		.hw.init = &(struct clk_init_data){
1909			.name = "gcc_disp_xo_clk",
1910			.flags = CLK_IS_CRITICAL,
1911			.ops = &clk_branch2_ops,
1912		},
1913	},
1914};
1915
1916static struct clk_branch gcc_gp1_clk = {
1917	.halt_reg = 0x4d000,
1918	.halt_check = BRANCH_HALT,
1919	.clkr = {
1920		.enable_reg = 0x4d000,
1921		.enable_mask = BIT(0),
1922		.hw.init = &(struct clk_init_data){
1923			.name = "gcc_gp1_clk",
1924			.parent_hws = (const struct clk_hw *[])
1925					{ &gcc_gp1_clk_src.clkr.hw },
1926			.num_parents = 1,
1927			.flags = CLK_SET_RATE_PARENT,
1928			.ops = &clk_branch2_ops,
1929		},
1930	},
1931};
1932
1933static struct clk_branch gcc_gp2_clk = {
1934	.halt_reg = 0x4e000,
1935	.halt_check = BRANCH_HALT,
1936	.clkr = {
1937		.enable_reg = 0x4e000,
1938		.enable_mask = BIT(0),
1939		.hw.init = &(struct clk_init_data){
1940			.name = "gcc_gp2_clk",
1941			.parent_hws = (const struct clk_hw *[])
1942					{ &gcc_gp2_clk_src.clkr.hw },
1943			.num_parents = 1,
1944			.flags = CLK_SET_RATE_PARENT,
1945			.ops = &clk_branch2_ops,
1946		},
1947	},
1948};
1949
1950static struct clk_branch gcc_gp3_clk = {
1951	.halt_reg = 0x4f000,
1952	.halt_check = BRANCH_HALT,
1953	.clkr = {
1954		.enable_reg = 0x4f000,
1955		.enable_mask = BIT(0),
1956		.hw.init = &(struct clk_init_data){
1957			.name = "gcc_gp3_clk",
1958			.parent_hws = (const struct clk_hw *[])
1959					{ &gcc_gp3_clk_src.clkr.hw },
1960			.num_parents = 1,
1961			.flags = CLK_SET_RATE_PARENT,
1962			.ops = &clk_branch2_ops,
1963		},
1964	},
1965};
1966
1967static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1968	.halt_reg = 0x36004,
1969	.halt_check = BRANCH_HALT,
1970	.hwcg_reg = 0x36004,
1971	.hwcg_bit = 1,
1972	.clkr = {
1973		.enable_reg = 0x36004,
1974		.enable_mask = BIT(0),
1975		.hw.init = &(struct clk_init_data){
1976			.name = "gcc_gpu_cfg_ahb_clk",
1977			.flags = CLK_IS_CRITICAL,
1978			.ops = &clk_branch2_ops,
1979		},
1980	},
1981};
1982
1983static struct clk_branch gcc_gpu_gpll0_clk_src = {
1984	.halt_check = BRANCH_HALT_DELAY,
1985	.clkr = {
1986		.enable_reg = 0x79004,
1987		.enable_mask = BIT(15),
1988		.hw.init = &(struct clk_init_data){
1989			.name = "gcc_gpu_gpll0_clk_src",
1990			.parent_hws = (const struct clk_hw *[])
1991					{ &gpll0.clkr.hw },
1992			.num_parents = 1,
1993			.flags = CLK_SET_RATE_PARENT,
1994			.ops = &clk_branch2_ops,
1995		},
1996	},
1997};
1998
1999static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
2000	.halt_check = BRANCH_HALT_DELAY,
2001	.clkr = {
2002		.enable_reg = 0x79004,
2003		.enable_mask = BIT(16),
2004		.hw.init = &(struct clk_init_data){
2005			.name = "gcc_gpu_gpll0_div_clk_src",
2006			.parent_hws = (const struct clk_hw *[])
2007					{ &gpll0_out_aux2.clkr.hw },
2008			.num_parents = 1,
2009			.flags = CLK_SET_RATE_PARENT,
2010			.ops = &clk_branch2_ops,
2011		},
2012	},
2013};
2014
2015static struct clk_branch gcc_gpu_iref_clk = {
2016	.halt_reg = 0x36100,
2017	.halt_check = BRANCH_HALT_DELAY,
2018	.clkr = {
2019		.enable_reg = 0x36100,
2020		.enable_mask = BIT(0),
2021		.hw.init = &(struct clk_init_data){
2022			.name = "gcc_gpu_iref_clk",
2023			.ops = &clk_branch2_ops,
2024		},
2025	},
2026};
2027
2028static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
2029	.halt_reg = 0x3600c,
2030	.halt_check = BRANCH_VOTED,
2031	.hwcg_reg = 0x3600c,
2032	.hwcg_bit = 1,
2033	.clkr = {
2034		.enable_reg = 0x3600c,
2035		.enable_mask = BIT(0),
2036		.hw.init = &(struct clk_init_data){
2037			.name = "gcc_gpu_memnoc_gfx_clk",
2038			.ops = &clk_branch2_ops,
2039		},
2040	},
2041};
2042
2043static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
2044	.halt_reg = 0x36018,
2045	.halt_check = BRANCH_HALT,
2046	.clkr = {
2047		.enable_reg = 0x36018,
2048		.enable_mask = BIT(0),
2049		.hw.init = &(struct clk_init_data){
2050			.name = "gcc_gpu_snoc_dvm_gfx_clk",
2051			.ops = &clk_branch2_ops,
2052		},
2053	},
2054};
2055
2056static struct clk_branch gcc_gpu_throttle_core_clk = {
2057	.halt_reg = 0x36048,
2058	.halt_check = BRANCH_HALT_VOTED,
2059	.hwcg_reg = 0x36048,
2060	.hwcg_bit = 1,
2061	.clkr = {
2062		.enable_reg = 0x79004,
2063		.enable_mask = BIT(31),
2064		.hw.init = &(struct clk_init_data){
2065			.name = "gcc_gpu_throttle_core_clk",
2066			.flags = CLK_SET_RATE_PARENT,
2067			.ops = &clk_branch2_ops,
2068		},
2069	},
2070};
2071
2072static struct clk_branch gcc_pdm2_clk = {
2073	.halt_reg = 0x2000c,
2074	.halt_check = BRANCH_HALT,
2075	.clkr = {
2076		.enable_reg = 0x2000c,
2077		.enable_mask = BIT(0),
2078		.hw.init = &(struct clk_init_data){
2079			.name = "gcc_pdm2_clk",
2080			.parent_hws = (const struct clk_hw *[])
2081					{ &gcc_pdm2_clk_src.clkr.hw },
2082			.num_parents = 1,
2083			.flags = CLK_SET_RATE_PARENT,
2084			.ops = &clk_branch2_ops,
2085		},
2086	},
2087};
2088
2089static struct clk_branch gcc_pdm_ahb_clk = {
2090	.halt_reg = 0x20004,
2091	.halt_check = BRANCH_HALT,
2092	.hwcg_reg = 0x20004,
2093	.hwcg_bit = 1,
2094	.clkr = {
2095		.enable_reg = 0x20004,
2096		.enable_mask = BIT(0),
2097		.hw.init = &(struct clk_init_data){
2098			.name = "gcc_pdm_ahb_clk",
2099			.ops = &clk_branch2_ops,
2100		},
2101	},
2102};
2103
2104static struct clk_branch gcc_pdm_xo4_clk = {
2105	.halt_reg = 0x20008,
2106	.halt_check = BRANCH_HALT,
2107	.clkr = {
2108		.enable_reg = 0x20008,
2109		.enable_mask = BIT(0),
2110		.hw.init = &(struct clk_init_data){
2111			.name = "gcc_pdm_xo4_clk",
2112			.ops = &clk_branch2_ops,
2113		},
2114	},
2115};
2116
2117static struct clk_branch gcc_pwm0_xo512_clk = {
2118	.halt_reg = 0x2002c,
2119	.halt_check = BRANCH_HALT,
2120	.clkr = {
2121		.enable_reg = 0x2002c,
2122		.enable_mask = BIT(0),
2123		.hw.init = &(struct clk_init_data){
2124			.name = "gcc_pwm0_xo512_clk",
2125			.ops = &clk_branch2_ops,
2126		},
2127	},
2128};
2129
2130static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2131	.halt_reg = 0x17014,
2132	.halt_check = BRANCH_HALT_VOTED,
2133	.hwcg_reg = 0x17014,
2134	.hwcg_bit = 1,
2135	.clkr = {
2136		.enable_reg = 0x7900c,
2137		.enable_mask = BIT(0),
2138		.hw.init = &(struct clk_init_data){
2139			.name = "gcc_qmip_camera_nrt_ahb_clk",
2140			.ops = &clk_branch2_ops,
2141		},
2142	},
2143};
2144
2145static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2146	.halt_reg = 0x17060,
2147	.halt_check = BRANCH_HALT_VOTED,
2148	.hwcg_reg = 0x17060,
2149	.hwcg_bit = 1,
2150	.clkr = {
2151		.enable_reg = 0x7900c,
2152		.enable_mask = BIT(2),
2153		.hw.init = &(struct clk_init_data){
2154			.name = "gcc_qmip_camera_rt_ahb_clk",
2155			.ops = &clk_branch2_ops,
2156		},
2157	},
2158};
2159
2160static struct clk_branch gcc_qmip_disp_ahb_clk = {
2161	.halt_reg = 0x17018,
2162	.halt_check = BRANCH_HALT_VOTED,
2163	.hwcg_reg = 0x17018,
2164	.hwcg_bit = 1,
2165	.clkr = {
2166		.enable_reg = 0x7900c,
2167		.enable_mask = BIT(1),
2168		.hw.init = &(struct clk_init_data){
2169			.name = "gcc_qmip_disp_ahb_clk",
2170			.ops = &clk_branch2_ops,
2171		},
2172	},
2173};
2174
2175static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = {
2176	.halt_reg = 0x36040,
2177	.halt_check = BRANCH_HALT_VOTED,
2178	.hwcg_reg = 0x36040,
2179	.hwcg_bit = 1,
2180	.clkr = {
2181		.enable_reg = 0x7900c,
2182		.enable_mask = BIT(4),
2183		.hw.init = &(struct clk_init_data){
2184			.name = "gcc_qmip_gpu_cfg_ahb_clk",
2185			.ops = &clk_branch2_ops,
2186		},
2187	},
2188};
2189
2190static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2191	.halt_reg = 0x17010,
2192	.halt_check = BRANCH_HALT_VOTED,
2193	.hwcg_reg = 0x17010,
2194	.hwcg_bit = 1,
2195	.clkr = {
2196		.enable_reg = 0x79004,
2197		.enable_mask = BIT(25),
2198		.hw.init = &(struct clk_init_data){
2199			.name = "gcc_qmip_video_vcodec_ahb_clk",
2200			.ops = &clk_branch2_ops,
2201		},
2202	},
2203};
2204
2205static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2206	.halt_reg = 0x1f014,
2207	.halt_check = BRANCH_HALT_VOTED,
2208	.clkr = {
2209		.enable_reg = 0x7900c,
2210		.enable_mask = BIT(9),
2211		.hw.init = &(struct clk_init_data){
2212			.name = "gcc_qupv3_wrap0_core_2x_clk",
2213			.ops = &clk_branch2_ops,
2214		},
2215	},
2216};
2217
2218static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2219	.halt_reg = 0x1f00c,
2220	.halt_check = BRANCH_HALT_VOTED,
2221	.clkr = {
2222		.enable_reg = 0x7900c,
2223		.enable_mask = BIT(8),
2224		.hw.init = &(struct clk_init_data){
2225			.name = "gcc_qupv3_wrap0_core_clk",
2226			.ops = &clk_branch2_ops,
2227		},
2228	},
2229};
2230
2231static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2232	.halt_reg = 0x1f144,
2233	.halt_check = BRANCH_HALT_VOTED,
2234	.clkr = {
2235		.enable_reg = 0x7900c,
2236		.enable_mask = BIT(10),
2237		.hw.init = &(struct clk_init_data){
2238			.name = "gcc_qupv3_wrap0_s0_clk",
2239			.parent_hws = (const struct clk_hw *[])
2240					{ &gcc_qupv3_wrap0_s0_clk_src.clkr.hw },
2241			.num_parents = 1,
2242			.flags = CLK_SET_RATE_PARENT,
2243			.ops = &clk_branch2_ops,
2244		},
2245	},
2246};
2247
2248static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2249	.halt_reg = 0x1f274,
2250	.halt_check = BRANCH_HALT_VOTED,
2251	.clkr = {
2252		.enable_reg = 0x7900c,
2253		.enable_mask = BIT(11),
2254		.hw.init = &(struct clk_init_data){
2255			.name = "gcc_qupv3_wrap0_s1_clk",
2256			.parent_hws = (const struct clk_hw *[])
2257					{ &gcc_qupv3_wrap0_s1_clk_src.clkr.hw },
2258			.num_parents = 1,
2259			.flags = CLK_SET_RATE_PARENT,
2260			.ops = &clk_branch2_ops,
2261		},
2262	},
2263};
2264
2265static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2266	.halt_reg = 0x1f3a4,
2267	.halt_check = BRANCH_HALT_VOTED,
2268	.clkr = {
2269		.enable_reg = 0x7900c,
2270		.enable_mask = BIT(12),
2271		.hw.init = &(struct clk_init_data){
2272			.name = "gcc_qupv3_wrap0_s2_clk",
2273			.parent_hws = (const struct clk_hw *[])
2274					{ &gcc_qupv3_wrap0_s2_clk_src.clkr.hw },
2275			.num_parents = 1,
2276			.flags = CLK_SET_RATE_PARENT,
2277			.ops = &clk_branch2_ops,
2278		},
2279	},
2280};
2281
2282static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2283	.halt_reg = 0x1f4d4,
2284	.halt_check = BRANCH_HALT_VOTED,
2285	.clkr = {
2286		.enable_reg = 0x7900c,
2287		.enable_mask = BIT(13),
2288		.hw.init = &(struct clk_init_data){
2289			.name = "gcc_qupv3_wrap0_s3_clk",
2290			.parent_hws = (const struct clk_hw *[])
2291					{ &gcc_qupv3_wrap0_s3_clk_src.clkr.hw },
2292			.num_parents = 1,
2293			.flags = CLK_SET_RATE_PARENT,
2294			.ops = &clk_branch2_ops,
2295		},
2296	},
2297};
2298
2299static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2300	.halt_reg = 0x1f604,
2301	.halt_check = BRANCH_HALT_VOTED,
2302	.clkr = {
2303		.enable_reg = 0x7900c,
2304		.enable_mask = BIT(14),
2305		.hw.init = &(struct clk_init_data){
2306			.name = "gcc_qupv3_wrap0_s4_clk",
2307			.parent_hws = (const struct clk_hw *[])
2308					{ &gcc_qupv3_wrap0_s4_clk_src.clkr.hw },
2309			.num_parents = 1,
2310			.flags = CLK_SET_RATE_PARENT,
2311			.ops = &clk_branch2_ops,
2312		},
2313	},
2314};
2315
2316static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2317	.halt_reg = 0x1f734,
2318	.halt_check = BRANCH_HALT_VOTED,
2319	.clkr = {
2320		.enable_reg = 0x7900c,
2321		.enable_mask = BIT(15),
2322		.hw.init = &(struct clk_init_data){
2323			.name = "gcc_qupv3_wrap0_s5_clk",
2324			.parent_hws = (const struct clk_hw *[])
2325					{ &gcc_qupv3_wrap0_s5_clk_src.clkr.hw },
2326			.num_parents = 1,
2327			.flags = CLK_SET_RATE_PARENT,
2328			.ops = &clk_branch2_ops,
2329		},
2330	},
2331};
2332
2333static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2334	.halt_reg = 0x1f004,
2335	.halt_check = BRANCH_HALT_VOTED,
2336	.hwcg_reg = 0x1f004,
2337	.hwcg_bit = 1,
2338	.clkr = {
2339		.enable_reg = 0x7900c,
2340		.enable_mask = BIT(6),
2341		.hw.init = &(struct clk_init_data){
2342			.name = "gcc_qupv3_wrap_0_m_ahb_clk",
2343			.ops = &clk_branch2_ops,
2344		},
2345	},
2346};
2347
2348static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2349	.halt_reg = 0x1f008,
2350	.halt_check = BRANCH_HALT_VOTED,
2351	.hwcg_reg = 0x1f008,
2352	.hwcg_bit = 1,
2353	.clkr = {
2354		.enable_reg = 0x7900c,
2355		.enable_mask = BIT(7),
2356		.hw.init = &(struct clk_init_data){
2357			.name = "gcc_qupv3_wrap_0_s_ahb_clk",
2358			.ops = &clk_branch2_ops,
2359		},
2360	},
2361};
2362
2363static struct clk_branch gcc_sdcc1_ahb_clk = {
2364	.halt_reg = 0x38008,
2365	.halt_check = BRANCH_HALT,
2366	.clkr = {
2367		.enable_reg = 0x38008,
2368		.enable_mask = BIT(0),
2369		.hw.init = &(struct clk_init_data){
2370			.name = "gcc_sdcc1_ahb_clk",
2371			.ops = &clk_branch2_ops,
2372		},
2373	},
2374};
2375
2376static struct clk_branch gcc_sdcc1_apps_clk = {
2377	.halt_reg = 0x38004,
2378	.halt_check = BRANCH_HALT,
2379	.clkr = {
2380		.enable_reg = 0x38004,
2381		.enable_mask = BIT(0),
2382		.hw.init = &(struct clk_init_data){
2383			.name = "gcc_sdcc1_apps_clk",
2384			.parent_hws = (const struct clk_hw *[])
2385					{ &gcc_sdcc1_apps_clk_src.clkr.hw },
2386			.num_parents = 1,
2387			.flags = CLK_SET_RATE_PARENT,
2388			.ops = &clk_branch2_ops,
2389		},
2390	},
2391};
2392
2393static struct clk_branch gcc_sdcc1_ice_core_clk = {
2394	.halt_reg = 0x3800c,
2395	.halt_check = BRANCH_HALT,
2396	.hwcg_reg = 0x3800c,
2397	.hwcg_bit = 1,
2398	.clkr = {
2399		.enable_reg = 0x3800c,
2400		.enable_mask = BIT(0),
2401		.hw.init = &(struct clk_init_data){
2402			.name = "gcc_sdcc1_ice_core_clk",
2403			.parent_hws = (const struct clk_hw *[])
2404					{ &gcc_sdcc1_ice_core_clk_src.clkr.hw },
2405			.num_parents = 1,
2406			.flags = CLK_SET_RATE_PARENT,
2407			.ops = &clk_branch2_ops,
2408		},
2409	},
2410};
2411
2412static struct clk_branch gcc_sdcc2_ahb_clk = {
2413	.halt_reg = 0x1e008,
2414	.halt_check = BRANCH_HALT,
2415	.clkr = {
2416		.enable_reg = 0x1e008,
2417		.enable_mask = BIT(0),
2418		.hw.init = &(struct clk_init_data){
2419			.name = "gcc_sdcc2_ahb_clk",
2420			.ops = &clk_branch2_ops,
2421		},
2422	},
2423};
2424
2425static struct clk_branch gcc_sdcc2_apps_clk = {
2426	.halt_reg = 0x1e004,
2427	.halt_check = BRANCH_HALT,
2428	.clkr = {
2429		.enable_reg = 0x1e004,
2430		.enable_mask = BIT(0),
2431		.hw.init = &(struct clk_init_data){
2432			.name = "gcc_sdcc2_apps_clk",
2433			.parent_hws = (const struct clk_hw *[])
2434					{ &gcc_sdcc2_apps_clk_src.clkr.hw },
2435			.num_parents = 1,
2436			.flags = CLK_SET_RATE_PARENT,
2437			.ops = &clk_branch2_ops,
2438		},
2439	},
2440};
2441
2442static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2443	.halt_reg = 0x2b06c,
2444	.halt_check = BRANCH_HALT_VOTED,
2445	.hwcg_reg = 0x2b06c,
2446	.hwcg_bit = 1,
2447	.clkr = {
2448		.enable_reg = 0x79004,
2449		.enable_mask = BIT(0),
2450		.hw.init = &(struct clk_init_data){
2451			.name = "gcc_sys_noc_cpuss_ahb_clk",
2452			.flags = CLK_IS_CRITICAL,
2453			.ops = &clk_branch2_ops,
2454		},
2455	},
2456};
2457
2458static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
2459	.halt_reg = 0x1a080,
2460	.halt_check = BRANCH_HALT,
2461	.hwcg_reg = 0x1a080,
2462	.hwcg_bit = 1,
2463	.clkr = {
2464		.enable_reg = 0x1a080,
2465		.enable_mask = BIT(0),
2466		.hw.init = &(struct clk_init_data){
2467			.name = "gcc_sys_noc_usb3_prim_axi_clk",
2468			.parent_hws = (const struct clk_hw *[])
2469				{ &gcc_usb30_prim_master_clk_src.clkr.hw },
2470			.num_parents = 1,
2471			.flags = CLK_SET_RATE_PARENT,
2472			.ops = &clk_branch2_ops,
2473		},
2474	},
2475};
2476
2477static struct clk_branch gcc_usb30_prim_master_clk = {
2478	.halt_reg = 0x1a010,
2479	.halt_check = BRANCH_HALT,
2480	.clkr = {
2481		.enable_reg = 0x1a010,
2482		.enable_mask = BIT(0),
2483		.hw.init = &(struct clk_init_data){
2484			.name = "gcc_usb30_prim_master_clk",
2485			.parent_hws = (const struct clk_hw *[])
2486				{ &gcc_usb30_prim_master_clk_src.clkr.hw },
2487			.num_parents = 1,
2488			.flags = CLK_SET_RATE_PARENT,
2489			.ops = &clk_branch2_ops,
2490		},
2491	},
2492};
2493
2494static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2495	.halt_reg = 0x1a018,
2496	.halt_check = BRANCH_HALT,
2497	.clkr = {
2498		.enable_reg = 0x1a018,
2499		.enable_mask = BIT(0),
2500		.hw.init = &(struct clk_init_data){
2501			.name = "gcc_usb30_prim_mock_utmi_clk",
2502			.parent_hws = (const struct clk_hw *[])
2503				{ &gcc_usb30_prim_mock_utmi_postdiv.clkr.hw },
2504			.num_parents = 1,
2505			.flags = CLK_SET_RATE_PARENT,
2506			.ops = &clk_branch2_ops,
2507		},
2508	},
2509};
2510
2511static struct clk_branch gcc_usb30_prim_sleep_clk = {
2512	.halt_reg = 0x1a014,
2513	.halt_check = BRANCH_HALT,
2514	.clkr = {
2515		.enable_reg = 0x1a014,
2516		.enable_mask = BIT(0),
2517		.hw.init = &(struct clk_init_data){
2518			.name = "gcc_usb30_prim_sleep_clk",
2519			.ops = &clk_branch2_ops,
2520		},
2521	},
2522};
2523
2524static struct clk_branch gcc_usb3_prim_clkref_clk = {
2525	.halt_reg = 0x9f000,
2526	.halt_check = BRANCH_HALT,
2527	.clkr = {
2528		.enable_reg = 0x9f000,
2529		.enable_mask = BIT(0),
2530		.hw.init = &(struct clk_init_data){
2531			.name = "gcc_usb3_prim_clkref_clk",
2532			.ops = &clk_branch2_ops,
2533		},
2534	},
2535};
2536
2537static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2538	.halt_reg = 0x1a054,
2539	.halt_check = BRANCH_HALT,
2540	.clkr = {
2541		.enable_reg = 0x1a054,
2542		.enable_mask = BIT(0),
2543		.hw.init = &(struct clk_init_data){
2544			.name = "gcc_usb3_prim_phy_com_aux_clk",
2545			.parent_hws = (const struct clk_hw *[])
2546				{ &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
2547			.num_parents = 1,
2548			.flags = CLK_SET_RATE_PARENT,
2549			.ops = &clk_branch2_ops,
2550		},
2551	},
2552};
2553
2554static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2555	.halt_reg = 0x1a058,
2556	.halt_check = BRANCH_HALT_SKIP,
2557	.hwcg_reg = 0x1a058,
2558	.hwcg_bit = 1,
2559	.clkr = {
2560		.enable_reg = 0x1a058,
2561		.enable_mask = BIT(0),
2562		.hw.init = &(struct clk_init_data){
2563			.name = "gcc_usb3_prim_phy_pipe_clk",
2564			.ops = &clk_branch2_ops,
2565		},
2566	},
2567};
2568
2569static struct clk_branch gcc_vcodec0_axi_clk = {
2570	.halt_reg = 0x6e008,
2571	.halt_check = BRANCH_HALT,
2572	.clkr = {
2573		.enable_reg = 0x6e008,
2574		.enable_mask = BIT(0),
2575		.hw.init = &(struct clk_init_data){
2576			.name = "gcc_vcodec0_axi_clk",
2577			.ops = &clk_branch2_ops,
2578		},
2579	},
2580};
2581
2582static struct clk_branch gcc_venus_ahb_clk = {
2583	.halt_reg = 0x6e010,
2584	.halt_check = BRANCH_HALT,
2585	.clkr = {
2586		.enable_reg = 0x6e010,
2587		.enable_mask = BIT(0),
2588		.hw.init = &(struct clk_init_data){
2589			.name = "gcc_venus_ahb_clk",
2590			.ops = &clk_branch2_ops,
2591		},
2592	},
2593};
2594
2595static struct clk_branch gcc_venus_ctl_axi_clk = {
2596	.halt_reg = 0x6e004,
2597	.halt_check = BRANCH_HALT,
2598	.clkr = {
2599		.enable_reg = 0x6e004,
2600		.enable_mask = BIT(0),
2601		.hw.init = &(struct clk_init_data){
2602			.name = "gcc_venus_ctl_axi_clk",
2603			.ops = &clk_branch2_ops,
2604		},
2605	},
2606};
2607
2608static struct clk_branch gcc_video_ahb_clk = {
2609	.halt_reg = 0x17004,
2610	.halt_check = BRANCH_HALT,
2611	.hwcg_reg = 0x17004,
2612	.hwcg_bit = 1,
2613	.clkr = {
2614		.enable_reg = 0x17004,
2615		.enable_mask = BIT(0),
2616		.hw.init = &(struct clk_init_data){
2617			.name = "gcc_video_ahb_clk",
2618			.ops = &clk_branch2_ops,
2619		},
2620	},
2621};
2622
2623static struct clk_branch gcc_video_axi0_clk = {
2624	.halt_reg = 0x1701c,
2625	.halt_check = BRANCH_HALT,
2626	.hwcg_reg = 0x1701c,
2627	.hwcg_bit = 1,
2628	.clkr = {
2629		.enable_reg = 0x1701c,
2630		.enable_mask = BIT(0),
2631		.hw.init = &(struct clk_init_data){
2632			.name = "gcc_video_axi0_clk",
2633			.ops = &clk_branch2_ops,
2634		},
2635	},
2636};
2637
2638static struct clk_branch gcc_video_throttle_core_clk = {
2639	.halt_reg = 0x17068,
2640	.halt_check = BRANCH_HALT_VOTED,
2641	.hwcg_reg = 0x17068,
2642	.hwcg_bit = 1,
2643	.clkr = {
2644		.enable_reg = 0x79004,
2645		.enable_mask = BIT(28),
2646		.hw.init = &(struct clk_init_data){
2647			.name = "gcc_video_throttle_core_clk",
2648			.ops = &clk_branch2_ops,
2649		},
2650	},
2651};
2652
2653static struct clk_branch gcc_video_vcodec0_sys_clk = {
2654	.halt_reg = 0x580a4,
2655	.halt_check = BRANCH_HALT_DELAY,
2656	.hwcg_reg = 0x580a4,
2657	.hwcg_bit = 1,
2658	.clkr = {
2659		.enable_reg = 0x580a4,
2660		.enable_mask = BIT(0),
2661		.hw.init = &(struct clk_init_data){
2662			.name = "gcc_video_vcodec0_sys_clk",
2663			.parent_hws = (const struct clk_hw *[])
2664					{ &gcc_video_venus_clk_src.clkr.hw },
2665			.num_parents = 1,
2666			.flags = CLK_SET_RATE_PARENT,
2667			.ops = &clk_branch2_ops,
2668		},
2669	},
2670};
2671
2672static struct clk_branch gcc_video_venus_ctl_clk = {
2673	.halt_reg = 0x5808c,
2674	.halt_check = BRANCH_HALT,
2675	.clkr = {
2676		.enable_reg = 0x5808c,
2677		.enable_mask = BIT(0),
2678		.hw.init = &(struct clk_init_data){
2679			.name = "gcc_video_venus_ctl_clk",
2680			.parent_hws = (const struct clk_hw *[])
2681					{ &gcc_video_venus_clk_src.clkr.hw },
2682			.num_parents = 1,
2683			.flags = CLK_SET_RATE_PARENT,
2684			.ops = &clk_branch2_ops,
2685		},
2686	},
2687};
2688
2689static struct clk_branch gcc_video_xo_clk = {
2690	.halt_reg = 0x17024,
2691	.halt_check = BRANCH_HALT,
2692	.clkr = {
2693		.enable_reg = 0x17024,
2694		.enable_mask = BIT(0),
2695		.hw.init = &(struct clk_init_data){
2696			.name = "gcc_video_xo_clk",
2697			.ops = &clk_branch2_ops,
2698		},
2699	},
2700};
2701
2702static struct gdsc gcc_camss_top_gdsc = {
2703	.gdscr = 0x58004,
2704	.pd = {
2705		.name = "gcc_camss_top",
2706	},
2707	.pwrsts = PWRSTS_OFF_ON,
2708};
2709
2710static struct gdsc gcc_usb30_prim_gdsc = {
2711	.gdscr = 0x1a004,
2712	.pd = {
2713		.name = "gcc_usb30_prim",
2714	},
2715	.pwrsts = PWRSTS_OFF_ON,
2716};
2717
2718static struct gdsc gcc_vcodec0_gdsc = {
2719	.gdscr = 0x58098,
2720	.pd = {
2721		.name = "gcc_vcodec0",
2722	},
2723	.flags = HW_CTRL_TRIGGER,
2724	.pwrsts = PWRSTS_OFF_ON,
2725};
2726
2727static struct gdsc gcc_venus_gdsc = {
2728	.gdscr = 0x5807c,
2729	.pd = {
2730		.name = "gcc_venus",
2731	},
2732	.pwrsts = PWRSTS_OFF_ON,
2733};
2734
2735static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
2736	.gdscr = 0x7d060,
2737	.pd = {
2738		.name = "hlos1_vote_turing_mmu_tbu1",
2739	},
2740	.pwrsts = PWRSTS_OFF_ON,
2741	.flags = VOTABLE,
2742};
2743
2744static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
2745	.gdscr = 0x7d07c,
2746	.pd = {
2747		.name = "hlos1_vote_turing_mmu_tbu0",
2748	},
2749	.pwrsts = PWRSTS_OFF_ON,
2750	.flags = VOTABLE,
2751};
2752
2753static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = {
2754	.gdscr = 0x7d074,
2755	.pd = {
2756		.name = "hlos1_vote_mm_snoc_mmu_tbu_rt",
2757	},
2758	.pwrsts = PWRSTS_OFF_ON,
2759	.flags = VOTABLE,
2760};
2761
2762static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = {
2763	.gdscr = 0x7d078,
2764	.pd = {
2765		.name = "hlos1_vote_mm_snoc_mmu_tbu_nrt",
2766	},
2767	.pwrsts = PWRSTS_OFF_ON,
2768	.flags = VOTABLE,
2769};
2770
2771static struct clk_regmap *gcc_qcm2290_clocks[] = {
2772	[GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr,
2773	[GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr,
2774	[GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr,
2775	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2776	[GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr,
2777	[GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr,
2778	[GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
2779	[GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
2780	[GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr,
2781	[GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr,
2782	[GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr,
2783	[GCC_CAMSS_CAMNOC_NTS_XO_CLK] = &gcc_camss_camnoc_nts_xo_clk.clkr,
2784	[GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr,
2785	[GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr,
2786	[GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr,
2787	[GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr,
2788	[GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
2789	[GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr,
2790	[GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
2791	[GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,
2792	[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
2793	[GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,
2794	[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
2795	[GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr,
2796	[GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
2797	[GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,
2798	[GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
2799	[GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,
2800	[GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr,
2801	[GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr,
2802	[GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr,
2803	[GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr,
2804	[GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr,
2805	[GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr,
2806	[GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr,
2807	[GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr,
2808	[GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr,
2809	[GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr,
2810	[GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr,
2811	[GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr,
2812	[GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr,
2813	[GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr,
2814	[GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr,
2815	[GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr,
2816	[GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr,
2817	[GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
2818	[GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr,
2819	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2820	[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
2821	[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
2822	[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
2823	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
2824	[GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
2825	[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
2826	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2827	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2828	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2829	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2830	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2831	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2832	[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2833	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
2834	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
2835	[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
2836	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2837	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2838	[GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr,
2839	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2840	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2841	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2842	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2843	[GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr,
2844	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
2845	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
2846	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
2847	[GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,
2848	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
2849	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2850	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2851	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2852	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2853	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2854	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2855	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2856	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2857	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2858	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2859	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2860	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2861	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2862	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2863	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2864	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2865	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2866	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2867	[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2868	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2869	[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2870	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2871	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2872	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2873	[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
2874	[GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
2875	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2876	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2877	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2878	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
2879		&gcc_usb30_prim_mock_utmi_clk_src.clkr,
2880	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV] =
2881		&gcc_usb30_prim_mock_utmi_postdiv.clkr,
2882	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2883	[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
2884	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2885	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2886	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2887	[GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr,
2888	[GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr,
2889	[GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr,
2890	[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
2891	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
2892	[GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
2893	[GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr,
2894	[GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr,
2895	[GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr,
2896	[GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
2897	[GPLL0] = &gpll0.clkr,
2898	[GPLL0_OUT_AUX2] = &gpll0_out_aux2.clkr,
2899	[GPLL1] = &gpll1.clkr,
2900	[GPLL10] = &gpll10.clkr,
2901	[GPLL11] = &gpll11.clkr,
2902	[GPLL3] = &gpll3.clkr,
2903	[GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2904	[GPLL4] = &gpll4.clkr,
2905	[GPLL5] = &gpll5.clkr,
2906	[GPLL6] = &gpll6.clkr,
2907	[GPLL6_OUT_MAIN] = &gpll6_out_main.clkr,
2908	[GPLL7] = &gpll7.clkr,
2909	[GPLL8] = &gpll8.clkr,
2910	[GPLL8_OUT_MAIN] = &gpll8_out_main.clkr,
2911	[GPLL9] = &gpll9.clkr,
2912	[GPLL9_OUT_MAIN] = &gpll9_out_main.clkr,
2913};
2914
2915static const struct qcom_reset_map gcc_qcm2290_resets[] = {
2916	[GCC_CAMSS_OPE_BCR] = { 0x55000 },
2917	[GCC_CAMSS_TFE_BCR] = { 0x52000 },
2918	[GCC_CAMSS_TOP_BCR] = { 0x58000 },
2919	[GCC_GPU_BCR] = { 0x36000 },
2920	[GCC_MMSS_BCR] = { 0x17000 },
2921	[GCC_PDM_BCR] = { 0x20000 },
2922	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 },
2923	[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
2924	[GCC_SDCC1_BCR] = { 0x38000 },
2925	[GCC_SDCC2_BCR] = { 0x1e000 },
2926	[GCC_USB30_PRIM_BCR] = { 0x1a000 },
2927	[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
2928	[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
2929	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
2930	[GCC_VCODEC0_BCR] = { 0x58094 },
2931	[GCC_VENUS_BCR] = { 0x58078 },
2932	[GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
2933};
2934
2935static struct gdsc *gcc_qcm2290_gdscs[] = {
2936	[GCC_CAMSS_TOP_GDSC] = &gcc_camss_top_gdsc,
2937	[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
2938	[GCC_VCODEC0_GDSC] = &gcc_vcodec0_gdsc,
2939	[GCC_VENUS_GDSC] = &gcc_venus_gdsc,
2940	[HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
2941	[HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
2942	[HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc,
2943	[HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,
2944};
2945
2946static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2947	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2948	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2949	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2950	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2951	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2952	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2953};
2954
2955static const struct regmap_config gcc_qcm2290_regmap_config = {
2956	.reg_bits = 32,
2957	.reg_stride = 4,
2958	.val_bits = 32,
2959	.max_register = 0xc7000,
2960	.fast_io = true,
2961};
2962
2963static const struct qcom_cc_desc gcc_qcm2290_desc = {
2964	.config = &gcc_qcm2290_regmap_config,
2965	.clks = gcc_qcm2290_clocks,
2966	.num_clks = ARRAY_SIZE(gcc_qcm2290_clocks),
2967	.resets = gcc_qcm2290_resets,
2968	.num_resets = ARRAY_SIZE(gcc_qcm2290_resets),
2969	.gdscs = gcc_qcm2290_gdscs,
2970	.num_gdscs = ARRAY_SIZE(gcc_qcm2290_gdscs),
2971};
2972
2973static const struct of_device_id gcc_qcm2290_match_table[] = {
2974	{ .compatible = "qcom,gcc-qcm2290" },
2975	{ }
2976};
2977MODULE_DEVICE_TABLE(of, gcc_qcm2290_match_table);
2978
2979static int gcc_qcm2290_probe(struct platform_device *pdev)
2980{
2981	struct regmap *regmap;
2982	int ret;
2983
2984	regmap = qcom_cc_map(pdev, &gcc_qcm2290_desc);
2985	if (IS_ERR(regmap))
2986		return PTR_ERR(regmap);
2987
2988	ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2989				       ARRAY_SIZE(gcc_dfs_clocks));
2990	if (ret)
2991		return ret;
2992
2993	clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config);
2994	clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config);
2995	clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config);
2996	clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config);
2997
2998	return qcom_cc_really_probe(&pdev->dev, &gcc_qcm2290_desc, regmap);
2999}
3000
3001static struct platform_driver gcc_qcm2290_driver = {
3002	.probe = gcc_qcm2290_probe,
3003	.driver = {
3004		.name = "gcc-qcm2290",
3005		.of_match_table = gcc_qcm2290_match_table,
3006	},
3007};
3008
3009static int __init gcc_qcm2290_init(void)
3010{
3011	return platform_driver_register(&gcc_qcm2290_driver);
3012}
3013subsys_initcall(gcc_qcm2290_init);
3014
3015static void __exit gcc_qcm2290_exit(void)
3016{
3017	platform_driver_unregister(&gcc_qcm2290_driver);
3018}
3019module_exit(gcc_qcm2290_exit);
3020
3021MODULE_DESCRIPTION("QTI GCC QCM2290 Driver");
3022MODULE_LICENSE("GPL v2");