gcc-milos.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
   4 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
   5 */
   6
   7#include <linux/clk-provider.h>
   8#include <linux/mod_devicetable.h>
   9#include <linux/module.h>
  10#include <linux/platform_device.h>
  11#include <linux/regmap.h>
  12
  13#include <dt-bindings/clock/qcom,milos-gcc.h>
  14
  15#include "clk-alpha-pll.h"
  16#include "clk-branch.h"
  17#include "clk-rcg.h"
  18#include "clk-regmap-divider.h"
  19#include "clk-regmap-mux.h"
  20#include "gdsc.h"
  21#include "reset.h"
  22
  23/* Need to match the order of clocks in DT binding */
  24enum {
  25	DT_BI_TCXO,
  26	DT_SLEEP_CLK,
  27	DT_PCIE_0_PIPE,
  28	DT_PCIE_1_PIPE,
  29	DT_UFS_PHY_RX_SYMBOL_0,
  30	DT_UFS_PHY_RX_SYMBOL_1,
  31	DT_UFS_PHY_TX_SYMBOL_0,
  32	DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE,
  33};
  34
  35enum {
  36	P_BI_TCXO,
  37	P_GCC_GPLL0_OUT_EVEN,
  38	P_GCC_GPLL0_OUT_MAIN,
  39	P_GCC_GPLL0_OUT_ODD,
  40	P_GCC_GPLL2_OUT_MAIN,
  41	P_GCC_GPLL4_OUT_MAIN,
  42	P_GCC_GPLL6_OUT_MAIN,
  43	P_GCC_GPLL7_OUT_MAIN,
  44	P_GCC_GPLL9_OUT_MAIN,
  45	P_PCIE_0_PIPE_CLK,
  46	P_PCIE_1_PIPE_CLK,
  47	P_SLEEP_CLK,
  48	P_UFS_PHY_RX_SYMBOL_0_CLK,
  49	P_UFS_PHY_RX_SYMBOL_1_CLK,
  50	P_UFS_PHY_TX_SYMBOL_0_CLK,
  51	P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
  52};
  53
  54static struct clk_alpha_pll gcc_gpll0 = {
  55	.offset = 0x0,
  56	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
  57	.clkr = {
  58		.enable_reg = 0x52020,
  59		.enable_mask = BIT(0),
  60		.hw.init = &(const struct clk_init_data) {
  61			.name = "gcc_gpll0",
  62			.parent_data = &(const struct clk_parent_data) {
  63				.index = DT_BI_TCXO,
  64			},
  65			.num_parents = 1,
  66			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
  67		},
  68	},
  69};
  70
  71static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
  72	{ 0x1, 2 },
  73	{ }
  74};
  75
  76static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
  77	.offset = 0x0,
  78	.post_div_shift = 10,
  79	.post_div_table = post_div_table_gcc_gpll0_out_even,
  80	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
  81	.width = 4,
  82	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
  83	.clkr.hw.init = &(const struct clk_init_data) {
  84		.name = "gcc_gpll0_out_even",
  85		.parent_hws = (const struct clk_hw*[]) {
  86			&gcc_gpll0.clkr.hw,
  87		},
  88		.num_parents = 1,
  89		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
  90	},
  91};
  92
  93static struct clk_alpha_pll gcc_gpll2 = {
  94	.offset = 0x2000,
  95	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
  96	.clkr = {
  97		.enable_reg = 0x52020,
  98		.enable_mask = BIT(2),
  99		.hw.init = &(const struct clk_init_data) {
 100			.name = "gcc_gpll2",
 101			.parent_data = &(const struct clk_parent_data) {
 102				.index = DT_BI_TCXO,
 103			},
 104			.num_parents = 1,
 105			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 106		},
 107	},
 108};
 109
 110static struct clk_alpha_pll gcc_gpll4 = {
 111	.offset = 0x4000,
 112	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 113	.clkr = {
 114		.enable_reg = 0x52020,
 115		.enable_mask = BIT(4),
 116		.hw.init = &(const struct clk_init_data) {
 117			.name = "gcc_gpll4",
 118			.parent_data = &(const struct clk_parent_data) {
 119				.index = DT_BI_TCXO,
 120			},
 121			.num_parents = 1,
 122			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 123		},
 124	},
 125};
 126
 127static struct clk_alpha_pll gcc_gpll6 = {
 128	.offset = 0x6000,
 129	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 130	.clkr = {
 131		.enable_reg = 0x52020,
 132		.enable_mask = BIT(6),
 133		.hw.init = &(const struct clk_init_data) {
 134			.name = "gcc_gpll6",
 135			.parent_data = &(const struct clk_parent_data) {
 136				.index = DT_BI_TCXO,
 137			},
 138			.num_parents = 1,
 139			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 140		},
 141	},
 142};
 143
 144static struct clk_alpha_pll gcc_gpll7 = {
 145	.offset = 0x7000,
 146	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 147	.clkr = {
 148		.enable_reg = 0x52020,
 149		.enable_mask = BIT(7),
 150		.hw.init = &(const struct clk_init_data) {
 151			.name = "gcc_gpll7",
 152			.parent_data = &(const struct clk_parent_data) {
 153				.index = DT_BI_TCXO,
 154			},
 155			.num_parents = 1,
 156			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 157		},
 158	},
 159};
 160
 161static struct clk_alpha_pll gcc_gpll9 = {
 162	.offset = 0x9000,
 163	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 164	.clkr = {
 165		.enable_reg = 0x52020,
 166		.enable_mask = BIT(9),
 167		.hw.init = &(const struct clk_init_data) {
 168			.name = "gcc_gpll9",
 169			.parent_data = &(const struct clk_parent_data) {
 170				.index = DT_BI_TCXO,
 171			},
 172			.num_parents = 1,
 173			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
 174		},
 175	},
 176};
 177
 178static const struct parent_map gcc_parent_map_0[] = {
 179	{ P_BI_TCXO, 0 },
 180	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 181	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 182};
 183
 184static const struct clk_parent_data gcc_parent_data_0[] = {
 185	{ .index = DT_BI_TCXO },
 186	{ .hw = &gcc_gpll0.clkr.hw },
 187	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 188};
 189
 190static const struct parent_map gcc_parent_map_1[] = {
 191	{ P_BI_TCXO, 0 },
 192	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 193	{ P_SLEEP_CLK, 5 },
 194	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 195};
 196
 197static const struct clk_parent_data gcc_parent_data_1[] = {
 198	{ .index = DT_BI_TCXO },
 199	{ .hw = &gcc_gpll0.clkr.hw },
 200	{ .index = DT_SLEEP_CLK },
 201	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 202};
 203
 204static const struct parent_map gcc_parent_map_2[] = {
 205	{ P_BI_TCXO, 0 },
 206	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 207	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 208	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 209};
 210
 211static const struct clk_parent_data gcc_parent_data_2[] = {
 212	{ .index = DT_BI_TCXO },
 213	{ .hw = &gcc_gpll0.clkr.hw },
 214	{ .hw = &gcc_gpll4.clkr.hw },
 215	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 216};
 217
 218static const struct parent_map gcc_parent_map_3[] = {
 219	{ P_BI_TCXO, 0 },
 220	{ P_SLEEP_CLK, 5 },
 221};
 222
 223static const struct clk_parent_data gcc_parent_data_3[] = {
 224	{ .index = DT_BI_TCXO },
 225	{ .index = DT_SLEEP_CLK },
 226};
 227
 228static const struct parent_map gcc_parent_map_4[] = {
 229	{ P_BI_TCXO, 0 },
 230	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 231	{ P_GCC_GPLL6_OUT_MAIN, 2 },
 232	{ P_GCC_GPLL7_OUT_MAIN, 3 },
 233	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 234};
 235
 236static const struct clk_parent_data gcc_parent_data_4[] = {
 237	{ .index = DT_BI_TCXO },
 238	{ .hw = &gcc_gpll0.clkr.hw },
 239	{ .hw = &gcc_gpll6.clkr.hw },
 240	{ .hw = &gcc_gpll7.clkr.hw },
 241	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 242};
 243
 244static const struct parent_map gcc_parent_map_5[] = {
 245	{ P_BI_TCXO, 0 },
 246};
 247
 248static const struct clk_parent_data gcc_parent_data_5[] = {
 249	{ .index = DT_BI_TCXO },
 250};
 251
 252static const struct parent_map gcc_parent_map_6[] = {
 253	{ P_PCIE_0_PIPE_CLK, 0 },
 254	{ P_BI_TCXO, 2 },
 255};
 256
 257static const struct clk_parent_data gcc_parent_data_6[] = {
 258	{ .index = DT_PCIE_0_PIPE },
 259	{ .index = DT_BI_TCXO },
 260};
 261
 262static const struct parent_map gcc_parent_map_7[] = {
 263	{ P_PCIE_1_PIPE_CLK, 0 },
 264	{ P_BI_TCXO, 2 },
 265};
 266
 267static const struct clk_parent_data gcc_parent_data_7[] = {
 268	{ .index = DT_PCIE_1_PIPE },
 269	{ .index = DT_BI_TCXO },
 270};
 271
 272static const struct parent_map gcc_parent_map_8[] = {
 273	{ P_BI_TCXO, 0 },
 274	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 275	{ P_GCC_GPLL7_OUT_MAIN, 2 },
 276	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 277};
 278
 279static const struct clk_parent_data gcc_parent_data_8[] = {
 280	{ .index = DT_BI_TCXO },
 281	{ .hw = &gcc_gpll0.clkr.hw },
 282	{ .hw = &gcc_gpll7.clkr.hw },
 283	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 284};
 285
 286static const struct parent_map gcc_parent_map_9[] = {
 287	{ P_BI_TCXO, 0 },
 288	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 289	{ P_GCC_GPLL6_OUT_MAIN, 2 },
 290	{ P_GCC_GPLL0_OUT_ODD, 3 },
 291	{ P_GCC_GPLL2_OUT_MAIN, 4 },
 292	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 293};
 294
 295static const struct clk_parent_data gcc_parent_data_9[] = {
 296	{ .index = DT_BI_TCXO },
 297	{ .hw = &gcc_gpll0.clkr.hw },
 298	{ .hw = &gcc_gpll6.clkr.hw },
 299	{ .hw = &gcc_gpll0.clkr.hw },
 300	{ .hw = &gcc_gpll2.clkr.hw },
 301	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 302};
 303
 304static const struct parent_map gcc_parent_map_10[] = {
 305	{ P_BI_TCXO, 0 },
 306	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 307	{ P_GCC_GPLL6_OUT_MAIN, 2 },
 308	{ P_GCC_GPLL0_OUT_ODD, 3 },
 309	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 310};
 311
 312static const struct clk_parent_data gcc_parent_data_10[] = {
 313	{ .index = DT_BI_TCXO },
 314	{ .hw = &gcc_gpll0.clkr.hw },
 315	{ .hw = &gcc_gpll6.clkr.hw },
 316	{ .hw = &gcc_gpll0.clkr.hw },
 317	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 318};
 319
 320static const struct parent_map gcc_parent_map_11[] = {
 321	{ P_BI_TCXO, 0 },
 322	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 323	{ P_GCC_GPLL9_OUT_MAIN, 2 },
 324	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 325	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 326};
 327
 328static const struct clk_parent_data gcc_parent_data_11[] = {
 329	{ .index = DT_BI_TCXO },
 330	{ .hw = &gcc_gpll0.clkr.hw },
 331	{ .hw = &gcc_gpll9.clkr.hw },
 332	{ .hw = &gcc_gpll4.clkr.hw },
 333	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 334};
 335
 336static const struct parent_map gcc_parent_map_12[] = {
 337	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
 338	{ P_BI_TCXO, 2 },
 339};
 340
 341static const struct clk_parent_data gcc_parent_data_12[] = {
 342	{ .index = DT_UFS_PHY_RX_SYMBOL_0 },
 343	{ .index = DT_BI_TCXO },
 344};
 345
 346static const struct parent_map gcc_parent_map_13[] = {
 347	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
 348	{ P_BI_TCXO, 2 },
 349};
 350
 351static const struct clk_parent_data gcc_parent_data_13[] = {
 352	{ .index = DT_UFS_PHY_RX_SYMBOL_1 },
 353	{ .index = DT_BI_TCXO },
 354};
 355
 356static const struct parent_map gcc_parent_map_14[] = {
 357	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
 358	{ P_BI_TCXO, 2 },
 359};
 360
 361static const struct clk_parent_data gcc_parent_data_14[] = {
 362	{ .index = DT_UFS_PHY_TX_SYMBOL_0 },
 363	{ .index = DT_BI_TCXO },
 364};
 365
 366static const struct parent_map gcc_parent_map_15[] = {
 367	{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 368	{ P_BI_TCXO, 2 },
 369};
 370
 371static const struct clk_parent_data gcc_parent_data_15[] = {
 372	{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE },
 373	{ .index = DT_BI_TCXO },
 374};
 375
 376static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
 377	.reg = 0x6b070,
 378	.shift = 0,
 379	.width = 2,
 380	.parent_map = gcc_parent_map_6,
 381	.clkr = {
 382		.hw.init = &(const struct clk_init_data) {
 383			.name = "gcc_pcie_0_pipe_clk_src",
 384			.parent_data = gcc_parent_data_6,
 385			.num_parents = ARRAY_SIZE(gcc_parent_data_6),
 386			.ops = &clk_regmap_mux_closest_ops,
 387		},
 388	},
 389};
 390
 391static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
 392	.reg = 0x9006c,
 393	.shift = 0,
 394	.width = 2,
 395	.parent_map = gcc_parent_map_7,
 396	.clkr = {
 397		.hw.init = &(const struct clk_init_data) {
 398			.name = "gcc_pcie_1_pipe_clk_src",
 399			.parent_data = gcc_parent_data_7,
 400			.num_parents = ARRAY_SIZE(gcc_parent_data_7),
 401			.ops = &clk_regmap_mux_closest_ops,
 402		},
 403	},
 404};
 405
 406static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
 407	.reg = 0x77064,
 408	.shift = 0,
 409	.width = 2,
 410	.parent_map = gcc_parent_map_12,
 411	.clkr = {
 412		.hw.init = &(const struct clk_init_data) {
 413			.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
 414			.parent_data = gcc_parent_data_12,
 415			.num_parents = ARRAY_SIZE(gcc_parent_data_12),
 416			.ops = &clk_regmap_mux_closest_ops,
 417		},
 418	},
 419};
 420
 421static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
 422	.reg = 0x770e0,
 423	.shift = 0,
 424	.width = 2,
 425	.parent_map = gcc_parent_map_13,
 426	.clkr = {
 427		.hw.init = &(const struct clk_init_data) {
 428			.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
 429			.parent_data = gcc_parent_data_13,
 430			.num_parents = ARRAY_SIZE(gcc_parent_data_13),
 431			.ops = &clk_regmap_mux_closest_ops,
 432		},
 433	},
 434};
 435
 436static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
 437	.reg = 0x77054,
 438	.shift = 0,
 439	.width = 2,
 440	.parent_map = gcc_parent_map_14,
 441	.clkr = {
 442		.hw.init = &(const struct clk_init_data) {
 443			.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
 444			.parent_data = gcc_parent_data_14,
 445			.num_parents = ARRAY_SIZE(gcc_parent_data_14),
 446			.ops = &clk_regmap_mux_closest_ops,
 447		},
 448	},
 449};
 450
 451static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
 452	.reg = 0x3906c,
 453	.shift = 0,
 454	.width = 2,
 455	.parent_map = gcc_parent_map_15,
 456	.clkr = {
 457		.hw.init = &(const struct clk_init_data) {
 458			.name = "gcc_usb3_prim_phy_pipe_clk_src",
 459			.parent_data = gcc_parent_data_15,
 460			.num_parents = ARRAY_SIZE(gcc_parent_data_15),
 461			.ops = &clk_regmap_mux_closest_ops,
 462		},
 463	},
 464};
 465
 466static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 467	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 468	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 469	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
 470	{ }
 471};
 472
 473static struct clk_rcg2 gcc_gp1_clk_src = {
 474	.cmd_rcgr = 0x64004,
 475	.mnd_width = 16,
 476	.hid_width = 5,
 477	.parent_map = gcc_parent_map_1,
 478	.freq_tbl = ftbl_gcc_gp1_clk_src,
 479	.clkr.hw.init = &(const struct clk_init_data) {
 480		.name = "gcc_gp1_clk_src",
 481		.parent_data = gcc_parent_data_1,
 482		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 483		.ops = &clk_rcg2_shared_ops,
 484	},
 485};
 486
 487static struct clk_rcg2 gcc_gp2_clk_src = {
 488	.cmd_rcgr = 0x65004,
 489	.mnd_width = 16,
 490	.hid_width = 5,
 491	.parent_map = gcc_parent_map_1,
 492	.freq_tbl = ftbl_gcc_gp1_clk_src,
 493	.clkr.hw.init = &(const struct clk_init_data) {
 494		.name = "gcc_gp2_clk_src",
 495		.parent_data = gcc_parent_data_1,
 496		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 497		.ops = &clk_rcg2_shared_ops,
 498	},
 499};
 500
 501static struct clk_rcg2 gcc_gp3_clk_src = {
 502	.cmd_rcgr = 0x66004,
 503	.mnd_width = 16,
 504	.hid_width = 5,
 505	.parent_map = gcc_parent_map_1,
 506	.freq_tbl = ftbl_gcc_gp1_clk_src,
 507	.clkr.hw.init = &(const struct clk_init_data) {
 508		.name = "gcc_gp3_clk_src",
 509		.parent_data = gcc_parent_data_1,
 510		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 511		.ops = &clk_rcg2_shared_ops,
 512	},
 513};
 514
 515static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 516	F(19200000, P_BI_TCXO, 1, 0, 0),
 517	{ }
 518};
 519
 520static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 521	.cmd_rcgr = 0x6b074,
 522	.mnd_width = 16,
 523	.hid_width = 5,
 524	.parent_map = gcc_parent_map_3,
 525	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 526	.clkr.hw.init = &(const struct clk_init_data) {
 527		.name = "gcc_pcie_0_aux_clk_src",
 528		.parent_data = gcc_parent_data_3,
 529		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
 530		.ops = &clk_rcg2_shared_ops,
 531	},
 532};
 533
 534static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
 535	F(19200000, P_BI_TCXO, 1, 0, 0),
 536	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 537	{ }
 538};
 539
 540static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
 541	.cmd_rcgr = 0x6b058,
 542	.mnd_width = 0,
 543	.hid_width = 5,
 544	.parent_map = gcc_parent_map_0,
 545	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 546	.clkr.hw.init = &(const struct clk_init_data) {
 547		.name = "gcc_pcie_0_phy_rchng_clk_src",
 548		.parent_data = gcc_parent_data_0,
 549		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 550		.ops = &clk_rcg2_shared_ops,
 551	},
 552};
 553
 554static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 555	.cmd_rcgr = 0x90070,
 556	.mnd_width = 16,
 557	.hid_width = 5,
 558	.parent_map = gcc_parent_map_3,
 559	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 560	.clkr.hw.init = &(const struct clk_init_data) {
 561		.name = "gcc_pcie_1_aux_clk_src",
 562		.parent_data = gcc_parent_data_3,
 563		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
 564		.ops = &clk_rcg2_shared_ops,
 565	},
 566};
 567
 568static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
 569	.cmd_rcgr = 0x90054,
 570	.mnd_width = 0,
 571	.hid_width = 5,
 572	.parent_map = gcc_parent_map_0,
 573	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 574	.clkr.hw.init = &(const struct clk_init_data) {
 575		.name = "gcc_pcie_1_phy_rchng_clk_src",
 576		.parent_data = gcc_parent_data_0,
 577		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 578		.ops = &clk_rcg2_shared_ops,
 579	},
 580};
 581
 582static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 583	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
 584	{ }
 585};
 586
 587static struct clk_rcg2 gcc_pdm2_clk_src = {
 588	.cmd_rcgr = 0x33010,
 589	.mnd_width = 0,
 590	.hid_width = 5,
 591	.parent_map = gcc_parent_map_0,
 592	.freq_tbl = ftbl_gcc_pdm2_clk_src,
 593	.clkr.hw.init = &(const struct clk_init_data) {
 594		.name = "gcc_pdm2_clk_src",
 595		.parent_data = gcc_parent_data_0,
 596		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 597		.ops = &clk_rcg2_shared_ops,
 598	},
 599};
 600
 601static const struct freq_tbl ftbl_gcc_qupv3_wrap0_qspi_ref_clk_src[] = {
 602	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 603	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 604	F(19200000, P_BI_TCXO, 1, 0, 0),
 605	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 606	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 607	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 608	F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
 609	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 610	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 611	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 612	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 613	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 614	F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
 615	F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
 616	F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
 617	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
 618	F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
 619	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
 620	{ }
 621};
 622
 623static struct clk_init_data gcc_qupv3_wrap0_qspi_ref_clk_src_init = {
 624	.name = "gcc_qupv3_wrap0_qspi_ref_clk_src",
 625	.parent_data = gcc_parent_data_0,
 626	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 627	.ops = &clk_rcg2_ops,
 628};
 629
 630static struct clk_rcg2 gcc_qupv3_wrap0_qspi_ref_clk_src = {
 631	.cmd_rcgr = 0x18768,
 632	.mnd_width = 16,
 633	.hid_width = 5,
 634	.parent_map = gcc_parent_map_0,
 635	.freq_tbl = ftbl_gcc_qupv3_wrap0_qspi_ref_clk_src,
 636	.clkr.hw.init = &gcc_qupv3_wrap0_qspi_ref_clk_src_init,
 637};
 638
 639static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 640	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 641	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 642	F(19200000, P_BI_TCXO, 1, 0, 0),
 643	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 644	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 645	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 646	F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
 647	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 648	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 649	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 650	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 651	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 652	F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
 653	F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
 654	F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
 655	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
 656	{ }
 657};
 658
 659static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 660	.name = "gcc_qupv3_wrap0_s0_clk_src",
 661	.parent_data = gcc_parent_data_0,
 662	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 663	.ops = &clk_rcg2_ops,
 664};
 665
 666static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 667	.cmd_rcgr = 0x18010,
 668	.mnd_width = 16,
 669	.hid_width = 5,
 670	.parent_map = gcc_parent_map_0,
 671	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 672	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 673};
 674
 675static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 676	.name = "gcc_qupv3_wrap0_s1_clk_src",
 677	.parent_data = gcc_parent_data_0,
 678	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 679	.ops = &clk_rcg2_ops,
 680};
 681
 682static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 683	.cmd_rcgr = 0x18148,
 684	.mnd_width = 16,
 685	.hid_width = 5,
 686	.parent_map = gcc_parent_map_0,
 687	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 688	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 689};
 690
 691static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s3_clk_src[] = {
 692	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 693	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 694	F(19200000, P_BI_TCXO, 1, 0, 0),
 695	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 696	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 697	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 698	F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
 699	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 700	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 701	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 702	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 703	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 704	{ }
 705};
 706
 707static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 708	.name = "gcc_qupv3_wrap0_s3_clk_src",
 709	.parent_data = gcc_parent_data_0,
 710	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 711	.ops = &clk_rcg2_ops,
 712};
 713
 714static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 715	.cmd_rcgr = 0x18290,
 716	.mnd_width = 16,
 717	.hid_width = 5,
 718	.parent_map = gcc_parent_map_0,
 719	.freq_tbl = ftbl_gcc_qupv3_wrap0_s3_clk_src,
 720	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 721};
 722
 723static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = {
 724	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 725	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 726	F(19200000, P_BI_TCXO, 1, 0, 0),
 727	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 728	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 729	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 730	F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
 731	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 732	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 733	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 734	F(128000000, P_GCC_GPLL6_OUT_MAIN, 3, 0, 0),
 735	{ }
 736};
 737
 738static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 739	.name = "gcc_qupv3_wrap0_s4_clk_src",
 740	.parent_data = gcc_parent_data_4,
 741	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
 742	.ops = &clk_rcg2_ops,
 743};
 744
 745static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 746	.cmd_rcgr = 0x183c8,
 747	.mnd_width = 16,
 748	.hid_width = 5,
 749	.parent_map = gcc_parent_map_4,
 750	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
 751	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 752};
 753
 754static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 755	.name = "gcc_qupv3_wrap0_s5_clk_src",
 756	.parent_data = gcc_parent_data_0,
 757	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 758	.ops = &clk_rcg2_ops,
 759};
 760
 761static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 762	.cmd_rcgr = 0x18500,
 763	.mnd_width = 16,
 764	.hid_width = 5,
 765	.parent_map = gcc_parent_map_0,
 766	.freq_tbl = ftbl_gcc_qupv3_wrap0_s3_clk_src,
 767	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 768};
 769
 770static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
 771	.name = "gcc_qupv3_wrap0_s6_clk_src",
 772	.parent_data = gcc_parent_data_0,
 773	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 774	.ops = &clk_rcg2_ops,
 775};
 776
 777static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
 778	.cmd_rcgr = 0x18638,
 779	.mnd_width = 16,
 780	.hid_width = 5,
 781	.parent_map = gcc_parent_map_0,
 782	.freq_tbl = ftbl_gcc_qupv3_wrap0_s3_clk_src,
 783	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
 784};
 785
 786static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = {
 787	.name = "gcc_qupv3_wrap1_qspi_ref_clk_src",
 788	.parent_data = gcc_parent_data_0,
 789	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 790	.ops = &clk_rcg2_ops,
 791};
 792
 793static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = {
 794	.cmd_rcgr = 0x1e768,
 795	.mnd_width = 16,
 796	.hid_width = 5,
 797	.parent_map = gcc_parent_map_0,
 798	.freq_tbl = ftbl_gcc_qupv3_wrap0_qspi_ref_clk_src,
 799	.clkr.hw.init = &gcc_qupv3_wrap1_qspi_ref_clk_src_init,
 800};
 801
 802static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 803	.name = "gcc_qupv3_wrap1_s0_clk_src",
 804	.parent_data = gcc_parent_data_0,
 805	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 806	.ops = &clk_rcg2_ops,
 807};
 808
 809static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 810	.cmd_rcgr = 0x1e010,
 811	.mnd_width = 16,
 812	.hid_width = 5,
 813	.parent_map = gcc_parent_map_0,
 814	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 815	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 816};
 817
 818static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 819	.name = "gcc_qupv3_wrap1_s1_clk_src",
 820	.parent_data = gcc_parent_data_0,
 821	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 822	.ops = &clk_rcg2_ops,
 823};
 824
 825static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 826	.cmd_rcgr = 0x1e148,
 827	.mnd_width = 16,
 828	.hid_width = 5,
 829	.parent_map = gcc_parent_map_0,
 830	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 831	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 832};
 833
 834static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 835	.name = "gcc_qupv3_wrap1_s3_clk_src",
 836	.parent_data = gcc_parent_data_0,
 837	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 838	.ops = &clk_rcg2_ops,
 839};
 840
 841static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 842	.cmd_rcgr = 0x1e290,
 843	.mnd_width = 16,
 844	.hid_width = 5,
 845	.parent_map = gcc_parent_map_0,
 846	.freq_tbl = ftbl_gcc_qupv3_wrap0_s3_clk_src,
 847	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 848};
 849
 850static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 851	.name = "gcc_qupv3_wrap1_s4_clk_src",
 852	.parent_data = gcc_parent_data_4,
 853	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
 854	.ops = &clk_rcg2_ops,
 855};
 856
 857static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 858	.cmd_rcgr = 0x1e3c8,
 859	.mnd_width = 16,
 860	.hid_width = 5,
 861	.parent_map = gcc_parent_map_4,
 862	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
 863	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 864};
 865
 866static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 867	.name = "gcc_qupv3_wrap1_s5_clk_src",
 868	.parent_data = gcc_parent_data_0,
 869	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 870	.ops = &clk_rcg2_ops,
 871};
 872
 873static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 874	.cmd_rcgr = 0x1e500,
 875	.mnd_width = 16,
 876	.hid_width = 5,
 877	.parent_map = gcc_parent_map_0,
 878	.freq_tbl = ftbl_gcc_qupv3_wrap0_s3_clk_src,
 879	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 880};
 881
 882static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
 883	.name = "gcc_qupv3_wrap1_s6_clk_src",
 884	.parent_data = gcc_parent_data_8,
 885	.num_parents = ARRAY_SIZE(gcc_parent_data_8),
 886	.ops = &clk_rcg2_ops,
 887};
 888
 889static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
 890	.cmd_rcgr = 0x1e638,
 891	.mnd_width = 16,
 892	.hid_width = 5,
 893	.parent_map = gcc_parent_map_8,
 894	.freq_tbl = ftbl_gcc_qupv3_wrap0_s3_clk_src,
 895	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
 896};
 897
 898static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
 899	F(144000, P_BI_TCXO, 16, 3, 25),
 900	F(400000, P_BI_TCXO, 12, 1, 4),
 901	F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
 902	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
 903	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 904	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 905	F(192000000, P_GCC_GPLL6_OUT_MAIN, 2, 0, 0),
 906	F(384000000, P_GCC_GPLL6_OUT_MAIN, 1, 0, 0),
 907	{ }
 908};
 909
 910static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
 911	.cmd_rcgr = 0xa3014,
 912	.mnd_width = 8,
 913	.hid_width = 5,
 914	.parent_map = gcc_parent_map_9,
 915	.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
 916	.clkr.hw.init = &(const struct clk_init_data) {
 917		.name = "gcc_sdcc1_apps_clk_src",
 918		.parent_data = gcc_parent_data_9,
 919		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
 920		.ops = &clk_rcg2_shared_floor_ops,
 921	},
 922};
 923
 924static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
 925	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 926	F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
 927	F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
 928	{ }
 929};
 930
 931static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
 932	.cmd_rcgr = 0xa3038,
 933	.mnd_width = 0,
 934	.hid_width = 5,
 935	.parent_map = gcc_parent_map_10,
 936	.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
 937	.clkr.hw.init = &(const struct clk_init_data) {
 938		.name = "gcc_sdcc1_ice_core_clk_src",
 939		.parent_data = gcc_parent_data_10,
 940		.num_parents = ARRAY_SIZE(gcc_parent_data_10),
 941		.ops = &clk_rcg2_shared_floor_ops,
 942	},
 943};
 944
 945static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 946	F(400000, P_BI_TCXO, 12, 1, 4),
 947	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
 948	F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
 949	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 950	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 951	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
 952	{ }
 953};
 954
 955static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
 956	.cmd_rcgr = 0x14018,
 957	.mnd_width = 8,
 958	.hid_width = 5,
 959	.parent_map = gcc_parent_map_11,
 960	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
 961	.clkr.hw.init = &(const struct clk_init_data) {
 962		.name = "gcc_sdcc2_apps_clk_src",
 963		.parent_data = gcc_parent_data_11,
 964		.num_parents = ARRAY_SIZE(gcc_parent_data_11),
 965		.ops = &clk_rcg2_shared_floor_ops,
 966	},
 967};
 968
 969static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
 970	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
 971	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 972	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 973	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
 974	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
 975	{ }
 976};
 977
 978static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
 979	.cmd_rcgr = 0x77030,
 980	.mnd_width = 8,
 981	.hid_width = 5,
 982	.parent_map = gcc_parent_map_2,
 983	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
 984	.clkr.hw.init = &(const struct clk_init_data) {
 985		.name = "gcc_ufs_phy_axi_clk_src",
 986		.parent_data = gcc_parent_data_2,
 987		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 988		.ops = &clk_rcg2_shared_ops,
 989	},
 990};
 991
 992static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
 993	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 994	F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
 995	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
 996	{ }
 997};
 998
 999static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1000	.cmd_rcgr = 0x77080,
1001	.mnd_width = 0,
1002	.hid_width = 5,
1003	.parent_map = gcc_parent_map_2,
1004	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1005	.clkr.hw.init = &(const struct clk_init_data) {
1006		.name = "gcc_ufs_phy_ice_core_clk_src",
1007		.parent_data = gcc_parent_data_2,
1008		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1009		.ops = &clk_rcg2_shared_ops,
1010	},
1011};
1012
1013static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
1014	F(9600000, P_BI_TCXO, 2, 0, 0),
1015	F(19200000, P_BI_TCXO, 1, 0, 0),
1016	{ }
1017};
1018
1019static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1020	.cmd_rcgr = 0x770b4,
1021	.mnd_width = 0,
1022	.hid_width = 5,
1023	.parent_map = gcc_parent_map_5,
1024	.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
1025	.clkr.hw.init = &(const struct clk_init_data) {
1026		.name = "gcc_ufs_phy_phy_aux_clk_src",
1027		.parent_data = gcc_parent_data_5,
1028		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
1029		.ops = &clk_rcg2_shared_ops,
1030	},
1031};
1032
1033static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
1034	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1035	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1036	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1037	{ }
1038};
1039
1040static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1041	.cmd_rcgr = 0x77098,
1042	.mnd_width = 0,
1043	.hid_width = 5,
1044	.parent_map = gcc_parent_map_2,
1045	.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
1046	.clkr.hw.init = &(const struct clk_init_data) {
1047		.name = "gcc_ufs_phy_unipro_core_clk_src",
1048		.parent_data = gcc_parent_data_2,
1049		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1050		.ops = &clk_rcg2_shared_ops,
1051	},
1052};
1053
1054static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1055	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1056	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1057	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1058	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1059	{ }
1060};
1061
1062static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1063	.cmd_rcgr = 0x3902c,
1064	.mnd_width = 8,
1065	.hid_width = 5,
1066	.parent_map = gcc_parent_map_0,
1067	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1068	.clkr.hw.init = &(const struct clk_init_data) {
1069		.name = "gcc_usb30_prim_master_clk_src",
1070		.parent_data = gcc_parent_data_0,
1071		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1072		.ops = &clk_rcg2_shared_ops,
1073	},
1074};
1075
1076static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1077	.cmd_rcgr = 0x39044,
1078	.mnd_width = 0,
1079	.hid_width = 5,
1080	.parent_map = gcc_parent_map_0,
1081	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1082	.clkr.hw.init = &(const struct clk_init_data) {
1083		.name = "gcc_usb30_prim_mock_utmi_clk_src",
1084		.parent_data = gcc_parent_data_0,
1085		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1086		.ops = &clk_rcg2_shared_ops,
1087	},
1088};
1089
1090static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1091	.cmd_rcgr = 0x39070,
1092	.mnd_width = 0,
1093	.hid_width = 5,
1094	.parent_map = gcc_parent_map_3,
1095	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1096	.clkr.hw.init = &(const struct clk_init_data) {
1097		.name = "gcc_usb3_prim_phy_aux_clk_src",
1098		.parent_data = gcc_parent_data_3,
1099		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1100		.ops = &clk_rcg2_shared_ops,
1101	},
1102};
1103
1104static struct clk_regmap_div gcc_pcie_0_pipe_div2_clk_src = {
1105	.reg = 0x6b094,
1106	.shift = 0,
1107	.width = 4,
1108	.clkr.hw.init = &(const struct clk_init_data) {
1109		.name = "gcc_pcie_0_pipe_div2_clk_src",
1110		.parent_hws = (const struct clk_hw*[]) {
1111			&gcc_pcie_0_pipe_clk_src.clkr.hw,
1112		},
1113		.num_parents = 1,
1114		.flags = CLK_SET_RATE_PARENT,
1115		.ops = &clk_regmap_div_ro_ops,
1116	},
1117};
1118
1119static struct clk_regmap_div gcc_pcie_1_pipe_div2_clk_src = {
1120	.reg = 0x90090,
1121	.shift = 0,
1122	.width = 4,
1123	.clkr.hw.init = &(const struct clk_init_data) {
1124		.name = "gcc_pcie_1_pipe_div2_clk_src",
1125		.parent_hws = (const struct clk_hw*[]) {
1126			&gcc_pcie_1_pipe_clk_src.clkr.hw,
1127		},
1128		.num_parents = 1,
1129		.flags = CLK_SET_RATE_PARENT,
1130		.ops = &clk_regmap_div_ro_ops,
1131	},
1132};
1133
1134static struct clk_regmap_div gcc_qupv3_wrap0_s2_clk_src = {
1135	.reg = 0x18280,
1136	.shift = 0,
1137	.width = 4,
1138	.clkr.hw.init = &(const struct clk_init_data) {
1139		.name = "gcc_qupv3_wrap0_s2_clk_src",
1140		.parent_hws = (const struct clk_hw*[]) {
1141			&gcc_qupv3_wrap0_qspi_ref_clk_src.clkr.hw,
1142		},
1143		.num_parents = 1,
1144		.flags = CLK_SET_RATE_PARENT,
1145		.ops = &clk_regmap_div_ro_ops,
1146	},
1147};
1148
1149static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = {
1150	.reg = 0x1e280,
1151	.shift = 0,
1152	.width = 4,
1153	.clkr.hw.init = &(const struct clk_init_data) {
1154		.name = "gcc_qupv3_wrap1_s2_clk_src",
1155		.parent_hws = (const struct clk_hw*[]) {
1156			&gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw,
1157		},
1158		.num_parents = 1,
1159		.flags = CLK_SET_RATE_PARENT,
1160		.ops = &clk_regmap_div_ro_ops,
1161	},
1162};
1163
1164static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1165	.reg = 0x3905c,
1166	.shift = 0,
1167	.width = 4,
1168	.clkr.hw.init = &(const struct clk_init_data) {
1169		.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1170		.parent_hws = (const struct clk_hw*[]) {
1171			&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1172		},
1173		.num_parents = 1,
1174		.flags = CLK_SET_RATE_PARENT,
1175		.ops = &clk_regmap_div_ro_ops,
1176	},
1177};
1178
1179static struct clk_branch gcc_aggre_noc_pcie_axi_clk = {
1180	.halt_reg = 0x1005c,
1181	.halt_check = BRANCH_HALT_SKIP,
1182	.hwcg_reg = 0x1005c,
1183	.hwcg_bit = 1,
1184	.clkr = {
1185		.enable_reg = 0x52000,
1186		.enable_mask = BIT(12),
1187		.hw.init = &(const struct clk_init_data) {
1188			.name = "gcc_aggre_noc_pcie_axi_clk",
1189			.ops = &clk_branch2_ops,
1190		},
1191	},
1192};
1193
1194static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1195	.halt_reg = 0x770e4,
1196	.halt_check = BRANCH_HALT_VOTED,
1197	.hwcg_reg = 0x770e4,
1198	.hwcg_bit = 1,
1199	.clkr = {
1200		.enable_reg = 0x770e4,
1201		.enable_mask = BIT(0),
1202		.hw.init = &(const struct clk_init_data) {
1203			.name = "gcc_aggre_ufs_phy_axi_clk",
1204			.parent_hws = (const struct clk_hw*[]) {
1205				&gcc_ufs_phy_axi_clk_src.clkr.hw,
1206			},
1207			.num_parents = 1,
1208			.flags = CLK_SET_RATE_PARENT,
1209			.ops = &clk_branch2_ops,
1210		},
1211	},
1212};
1213
1214static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1215	.halt_reg = 0x770e4,
1216	.halt_check = BRANCH_HALT_VOTED,
1217	.hwcg_reg = 0x770e4,
1218	.hwcg_bit = 1,
1219	.clkr = {
1220		.enable_reg = 0x770e4,
1221		.enable_mask = BIT(1),
1222		.hw.init = &(const struct clk_init_data) {
1223			.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1224			.parent_hws = (const struct clk_hw*[]) {
1225				&gcc_ufs_phy_axi_clk_src.clkr.hw,
1226			},
1227			.num_parents = 1,
1228			.flags = CLK_SET_RATE_PARENT,
1229			.ops = &clk_branch2_ops,
1230		},
1231	},
1232};
1233
1234static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1235	.halt_reg = 0x39090,
1236	.halt_check = BRANCH_HALT_VOTED,
1237	.hwcg_reg = 0x39090,
1238	.hwcg_bit = 1,
1239	.clkr = {
1240		.enable_reg = 0x39090,
1241		.enable_mask = BIT(0),
1242		.hw.init = &(const struct clk_init_data) {
1243			.name = "gcc_aggre_usb3_prim_axi_clk",
1244			.parent_hws = (const struct clk_hw*[]) {
1245				&gcc_usb30_prim_master_clk_src.clkr.hw,
1246			},
1247			.num_parents = 1,
1248			.flags = CLK_SET_RATE_PARENT,
1249			.ops = &clk_branch2_ops,
1250		},
1251	},
1252};
1253
1254static struct clk_branch gcc_boot_rom_ahb_clk = {
1255	.halt_reg = 0x38004,
1256	.halt_check = BRANCH_HALT_VOTED,
1257	.hwcg_reg = 0x38004,
1258	.hwcg_bit = 1,
1259	.clkr = {
1260		.enable_reg = 0x52000,
1261		.enable_mask = BIT(10),
1262		.hw.init = &(const struct clk_init_data) {
1263			.name = "gcc_boot_rom_ahb_clk",
1264			.ops = &clk_branch2_ops,
1265		},
1266	},
1267};
1268
1269static struct clk_branch gcc_camera_hf_axi_clk = {
1270	.halt_reg = 0x26010,
1271	.halt_check = BRANCH_HALT_SKIP,
1272	.hwcg_reg = 0x26010,
1273	.hwcg_bit = 1,
1274	.clkr = {
1275		.enable_reg = 0x26010,
1276		.enable_mask = BIT(0),
1277		.hw.init = &(const struct clk_init_data) {
1278			.name = "gcc_camera_hf_axi_clk",
1279			.ops = &clk_branch2_ops,
1280		},
1281	},
1282};
1283
1284static struct clk_branch gcc_camera_sf_axi_clk = {
1285	.halt_reg = 0x26014,
1286	.halt_check = BRANCH_HALT_SKIP,
1287	.hwcg_reg = 0x26014,
1288	.hwcg_bit = 1,
1289	.clkr = {
1290		.enable_reg = 0x26014,
1291		.enable_mask = BIT(0),
1292		.hw.init = &(const struct clk_init_data) {
1293			.name = "gcc_camera_sf_axi_clk",
1294			.ops = &clk_branch2_ops,
1295		},
1296	},
1297};
1298
1299static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
1300	.halt_reg = 0x10050,
1301	.halt_check = BRANCH_HALT_SKIP,
1302	.hwcg_reg = 0x10050,
1303	.hwcg_bit = 1,
1304	.clkr = {
1305		.enable_reg = 0x52000,
1306		.enable_mask = BIT(20),
1307		.hw.init = &(const struct clk_init_data) {
1308			.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
1309			.ops = &clk_branch2_ops,
1310		},
1311	},
1312};
1313
1314static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1315	.halt_reg = 0x3908c,
1316	.halt_check = BRANCH_HALT_VOTED,
1317	.clkr = {
1318		.enable_reg = 0x3908c,
1319		.enable_mask = BIT(0),
1320		.hw.init = &(const struct clk_init_data) {
1321			.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1322			.parent_hws = (const struct clk_hw*[]) {
1323				&gcc_usb30_prim_master_clk_src.clkr.hw,
1324			},
1325			.num_parents = 1,
1326			.flags = CLK_SET_RATE_PARENT,
1327			.ops = &clk_branch2_ops,
1328		},
1329	},
1330};
1331
1332static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = {
1333	.halt_reg = 0x10058,
1334	.halt_check = BRANCH_HALT_VOTED,
1335	.hwcg_reg = 0x10058,
1336	.hwcg_bit = 1,
1337	.clkr = {
1338		.enable_reg = 0x52008,
1339		.enable_mask = BIT(6),
1340		.hw.init = &(const struct clk_init_data) {
1341			.name = "gcc_cnoc_pcie_sf_axi_clk",
1342			.ops = &clk_branch2_ops,
1343		},
1344	},
1345};
1346
1347static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1348	.halt_reg = 0x7115c,
1349	.halt_check = BRANCH_HALT_SKIP,
1350	.hwcg_reg = 0x7115c,
1351	.hwcg_bit = 1,
1352	.clkr = {
1353		.enable_reg = 0x7115c,
1354		.enable_mask = BIT(0),
1355		.hw.init = &(const struct clk_init_data) {
1356			.name = "gcc_ddrss_gpu_axi_clk",
1357			.ops = &clk_branch2_aon_ops,
1358		},
1359	},
1360};
1361
1362static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = {
1363	.halt_reg = 0x1006c,
1364	.halt_check = BRANCH_HALT_SKIP,
1365	.hwcg_reg = 0x1006c,
1366	.hwcg_bit = 1,
1367	.clkr = {
1368		.enable_reg = 0x52000,
1369		.enable_mask = BIT(19),
1370		.hw.init = &(const struct clk_init_data) {
1371			.name = "gcc_ddrss_pcie_sf_qtb_clk",
1372			.ops = &clk_branch2_ops,
1373		},
1374	},
1375};
1376
1377static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1378	.halt_check = BRANCH_HALT_DELAY,
1379	.clkr = {
1380		.enable_reg = 0x52000,
1381		.enable_mask = BIT(23),
1382		.hw.init = &(const struct clk_init_data) {
1383			.name = "gcc_disp_gpll0_div_clk_src",
1384			.parent_hws = (const struct clk_hw*[]) {
1385				&gcc_gpll0_out_even.clkr.hw,
1386			},
1387			.num_parents = 1,
1388			.flags = CLK_SET_RATE_PARENT,
1389			.ops = &clk_branch2_ops,
1390		},
1391	},
1392};
1393
1394static struct clk_branch gcc_disp_hf_axi_clk = {
1395	.halt_reg = 0x2700c,
1396	.halt_check = BRANCH_HALT_SKIP,
1397	.hwcg_reg = 0x2700c,
1398	.hwcg_bit = 1,
1399	.clkr = {
1400		.enable_reg = 0x2700c,
1401		.enable_mask = BIT(0),
1402		.hw.init = &(const struct clk_init_data) {
1403			.name = "gcc_disp_hf_axi_clk",
1404			.ops = &clk_branch2_ops,
1405		},
1406	},
1407};
1408
1409static struct clk_branch gcc_gp1_clk = {
1410	.halt_reg = 0x64000,
1411	.halt_check = BRANCH_HALT,
1412	.clkr = {
1413		.enable_reg = 0x64000,
1414		.enable_mask = BIT(0),
1415		.hw.init = &(const struct clk_init_data) {
1416			.name = "gcc_gp1_clk",
1417			.parent_hws = (const struct clk_hw*[]) {
1418				&gcc_gp1_clk_src.clkr.hw,
1419			},
1420			.num_parents = 1,
1421			.flags = CLK_SET_RATE_PARENT,
1422			.ops = &clk_branch2_ops,
1423		},
1424	},
1425};
1426
1427static struct clk_branch gcc_gp2_clk = {
1428	.halt_reg = 0x65000,
1429	.halt_check = BRANCH_HALT,
1430	.clkr = {
1431		.enable_reg = 0x65000,
1432		.enable_mask = BIT(0),
1433		.hw.init = &(const struct clk_init_data) {
1434			.name = "gcc_gp2_clk",
1435			.parent_hws = (const struct clk_hw*[]) {
1436				&gcc_gp2_clk_src.clkr.hw,
1437			},
1438			.num_parents = 1,
1439			.flags = CLK_SET_RATE_PARENT,
1440			.ops = &clk_branch2_ops,
1441		},
1442	},
1443};
1444
1445static struct clk_branch gcc_gp3_clk = {
1446	.halt_reg = 0x66000,
1447	.halt_check = BRANCH_HALT,
1448	.clkr = {
1449		.enable_reg = 0x66000,
1450		.enable_mask = BIT(0),
1451		.hw.init = &(const struct clk_init_data) {
1452			.name = "gcc_gp3_clk",
1453			.parent_hws = (const struct clk_hw*[]) {
1454				&gcc_gp3_clk_src.clkr.hw,
1455			},
1456			.num_parents = 1,
1457			.flags = CLK_SET_RATE_PARENT,
1458			.ops = &clk_branch2_ops,
1459		},
1460	},
1461};
1462
1463static struct clk_branch gcc_gpu_gpll0_clk_src = {
1464	.halt_check = BRANCH_HALT_DELAY,
1465	.clkr = {
1466		.enable_reg = 0x52000,
1467		.enable_mask = BIT(15),
1468		.hw.init = &(const struct clk_init_data) {
1469			.name = "gcc_gpu_gpll0_clk_src",
1470			.parent_hws = (const struct clk_hw*[]) {
1471				&gcc_gpll0.clkr.hw,
1472			},
1473			.num_parents = 1,
1474			.flags = CLK_SET_RATE_PARENT,
1475			.ops = &clk_branch2_ops,
1476		},
1477	},
1478};
1479
1480static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1481	.halt_check = BRANCH_HALT_DELAY,
1482	.clkr = {
1483		.enable_reg = 0x52000,
1484		.enable_mask = BIT(16),
1485		.hw.init = &(const struct clk_init_data) {
1486			.name = "gcc_gpu_gpll0_div_clk_src",
1487			.parent_hws = (const struct clk_hw*[]) {
1488				&gcc_gpll0_out_even.clkr.hw,
1489			},
1490			.num_parents = 1,
1491			.flags = CLK_SET_RATE_PARENT,
1492			.ops = &clk_branch2_ops,
1493		},
1494	},
1495};
1496
1497static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1498	.halt_reg = 0x71010,
1499	.halt_check = BRANCH_HALT_VOTED,
1500	.hwcg_reg = 0x71010,
1501	.hwcg_bit = 1,
1502	.clkr = {
1503		.enable_reg = 0x71010,
1504		.enable_mask = BIT(0),
1505		.hw.init = &(const struct clk_init_data) {
1506			.name = "gcc_gpu_memnoc_gfx_clk",
1507			.ops = &clk_branch2_ops,
1508		},
1509	},
1510};
1511
1512static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1513	.halt_reg = 0x71018,
1514	.halt_check = BRANCH_HALT_DELAY,
1515	.clkr = {
1516		.enable_reg = 0x71018,
1517		.enable_mask = BIT(0),
1518		.hw.init = &(const struct clk_init_data) {
1519			.name = "gcc_gpu_snoc_dvm_gfx_clk",
1520			.ops = &clk_branch2_ops,
1521		},
1522	},
1523};
1524
1525static struct clk_branch gcc_pcie_0_aux_clk = {
1526	.halt_reg = 0x6b03c,
1527	.halt_check = BRANCH_HALT_VOTED,
1528	.clkr = {
1529		.enable_reg = 0x52008,
1530		.enable_mask = BIT(3),
1531		.hw.init = &(const struct clk_init_data) {
1532			.name = "gcc_pcie_0_aux_clk",
1533			.parent_hws = (const struct clk_hw*[]) {
1534				&gcc_pcie_0_aux_clk_src.clkr.hw,
1535			},
1536			.num_parents = 1,
1537			.flags = CLK_SET_RATE_PARENT,
1538			.ops = &clk_branch2_ops,
1539		},
1540	},
1541};
1542
1543static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1544	.halt_reg = 0x6b038,
1545	.halt_check = BRANCH_HALT_VOTED,
1546	.hwcg_reg = 0x6b038,
1547	.hwcg_bit = 1,
1548	.clkr = {
1549		.enable_reg = 0x52008,
1550		.enable_mask = BIT(2),
1551		.hw.init = &(const struct clk_init_data) {
1552			.name = "gcc_pcie_0_cfg_ahb_clk",
1553			.ops = &clk_branch2_ops,
1554		},
1555	},
1556};
1557
1558static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1559	.halt_reg = 0x6b02c,
1560	.halt_check = BRANCH_HALT_SKIP,
1561	.hwcg_reg = 0x6b02c,
1562	.hwcg_bit = 1,
1563	.clkr = {
1564		.enable_reg = 0x52008,
1565		.enable_mask = BIT(1),
1566		.hw.init = &(const struct clk_init_data) {
1567			.name = "gcc_pcie_0_mstr_axi_clk",
1568			.ops = &clk_branch2_ops,
1569		},
1570	},
1571};
1572
1573static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
1574	.halt_reg = 0x6b054,
1575	.halt_check = BRANCH_HALT_VOTED,
1576	.clkr = {
1577		.enable_reg = 0x52000,
1578		.enable_mask = BIT(22),
1579		.hw.init = &(const struct clk_init_data) {
1580			.name = "gcc_pcie_0_phy_rchng_clk",
1581			.parent_hws = (const struct clk_hw*[]) {
1582				&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1583			},
1584			.num_parents = 1,
1585			.flags = CLK_SET_RATE_PARENT,
1586			.ops = &clk_branch2_ops,
1587		},
1588	},
1589};
1590
1591static struct clk_branch gcc_pcie_0_pipe_clk = {
1592	.halt_reg = 0x6b048,
1593	.halt_check = BRANCH_HALT_SKIP,
1594	.clkr = {
1595		.enable_reg = 0x52008,
1596		.enable_mask = BIT(4),
1597		.hw.init = &(const struct clk_init_data) {
1598			.name = "gcc_pcie_0_pipe_clk",
1599			.parent_hws = (const struct clk_hw*[]) {
1600				&gcc_pcie_0_pipe_clk_src.clkr.hw,
1601			},
1602			.num_parents = 1,
1603			.flags = CLK_SET_RATE_PARENT,
1604			.ops = &clk_branch2_ops,
1605		},
1606	},
1607};
1608
1609static struct clk_branch gcc_pcie_0_pipe_div2_clk = {
1610	.halt_reg = 0x6b098,
1611	.halt_check = BRANCH_HALT_SKIP,
1612	.clkr = {
1613		.enable_reg = 0x52018,
1614		.enable_mask = BIT(13),
1615		.hw.init = &(const struct clk_init_data) {
1616			.name = "gcc_pcie_0_pipe_div2_clk",
1617			.parent_hws = (const struct clk_hw*[]) {
1618				&gcc_pcie_0_pipe_div2_clk_src.clkr.hw,
1619			},
1620			.num_parents = 1,
1621			.flags = CLK_SET_RATE_PARENT,
1622			.ops = &clk_branch2_ops,
1623		},
1624	},
1625};
1626
1627static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1628	.halt_reg = 0x6b020,
1629	.halt_check = BRANCH_HALT_VOTED,
1630	.hwcg_reg = 0x6b020,
1631	.hwcg_bit = 1,
1632	.clkr = {
1633		.enable_reg = 0x52008,
1634		.enable_mask = BIT(0),
1635		.hw.init = &(const struct clk_init_data) {
1636			.name = "gcc_pcie_0_slv_axi_clk",
1637			.ops = &clk_branch2_ops,
1638		},
1639	},
1640};
1641
1642static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1643	.halt_reg = 0x6b01c,
1644	.halt_check = BRANCH_HALT_VOTED,
1645	.clkr = {
1646		.enable_reg = 0x52008,
1647		.enable_mask = BIT(5),
1648		.hw.init = &(const struct clk_init_data) {
1649			.name = "gcc_pcie_0_slv_q2a_axi_clk",
1650			.ops = &clk_branch2_ops,
1651		},
1652	},
1653};
1654
1655static struct clk_branch gcc_pcie_1_aux_clk = {
1656	.halt_reg = 0x90038,
1657	.halt_check = BRANCH_HALT_VOTED,
1658	.clkr = {
1659		.enable_reg = 0x52000,
1660		.enable_mask = BIT(29),
1661		.hw.init = &(const struct clk_init_data) {
1662			.name = "gcc_pcie_1_aux_clk",
1663			.parent_hws = (const struct clk_hw*[]) {
1664				&gcc_pcie_1_aux_clk_src.clkr.hw,
1665			},
1666			.num_parents = 1,
1667			.flags = CLK_SET_RATE_PARENT,
1668			.ops = &clk_branch2_ops,
1669		},
1670	},
1671};
1672
1673static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1674	.halt_reg = 0x90034,
1675	.halt_check = BRANCH_HALT_VOTED,
1676	.hwcg_reg = 0x90034,
1677	.hwcg_bit = 1,
1678	.clkr = {
1679		.enable_reg = 0x52000,
1680		.enable_mask = BIT(28),
1681		.hw.init = &(const struct clk_init_data) {
1682			.name = "gcc_pcie_1_cfg_ahb_clk",
1683			.ops = &clk_branch2_ops,
1684		},
1685	},
1686};
1687
1688static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1689	.halt_reg = 0x90028,
1690	.halt_check = BRANCH_HALT_SKIP,
1691	.hwcg_reg = 0x90028,
1692	.hwcg_bit = 1,
1693	.clkr = {
1694		.enable_reg = 0x52000,
1695		.enable_mask = BIT(27),
1696		.hw.init = &(const struct clk_init_data) {
1697			.name = "gcc_pcie_1_mstr_axi_clk",
1698			.ops = &clk_branch2_ops,
1699		},
1700	},
1701};
1702
1703static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
1704	.halt_reg = 0x90050,
1705	.halt_check = BRANCH_HALT_VOTED,
1706	.clkr = {
1707		.enable_reg = 0x52008,
1708		.enable_mask = BIT(8),
1709		.hw.init = &(const struct clk_init_data) {
1710			.name = "gcc_pcie_1_phy_rchng_clk",
1711			.parent_hws = (const struct clk_hw*[]) {
1712				&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1713			},
1714			.num_parents = 1,
1715			.flags = CLK_SET_RATE_PARENT,
1716			.ops = &clk_branch2_ops,
1717		},
1718	},
1719};
1720
1721static struct clk_branch gcc_pcie_1_pipe_clk = {
1722	.halt_reg = 0x90044,
1723	.halt_check = BRANCH_HALT_SKIP,
1724	.clkr = {
1725		.enable_reg = 0x52008,
1726		.enable_mask = BIT(7),
1727		.hw.init = &(const struct clk_init_data) {
1728			.name = "gcc_pcie_1_pipe_clk",
1729			.parent_hws = (const struct clk_hw*[]) {
1730				&gcc_pcie_1_pipe_clk_src.clkr.hw,
1731			},
1732			.num_parents = 1,
1733			.flags = CLK_SET_RATE_PARENT,
1734			.ops = &clk_branch2_ops,
1735		},
1736	},
1737};
1738
1739static struct clk_branch gcc_pcie_1_pipe_div2_clk = {
1740	.halt_reg = 0x90094,
1741	.halt_check = BRANCH_HALT_SKIP,
1742	.clkr = {
1743		.enable_reg = 0x52018,
1744		.enable_mask = BIT(15),
1745		.hw.init = &(const struct clk_init_data) {
1746			.name = "gcc_pcie_1_pipe_div2_clk",
1747			.parent_hws = (const struct clk_hw*[]) {
1748				&gcc_pcie_1_pipe_div2_clk_src.clkr.hw,
1749			},
1750			.num_parents = 1,
1751			.flags = CLK_SET_RATE_PARENT,
1752			.ops = &clk_branch2_ops,
1753		},
1754	},
1755};
1756
1757static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1758	.halt_reg = 0x9001c,
1759	.halt_check = BRANCH_HALT_VOTED,
1760	.hwcg_reg = 0x9001c,
1761	.hwcg_bit = 1,
1762	.clkr = {
1763		.enable_reg = 0x52000,
1764		.enable_mask = BIT(26),
1765		.hw.init = &(const struct clk_init_data) {
1766			.name = "gcc_pcie_1_slv_axi_clk",
1767			.ops = &clk_branch2_ops,
1768		},
1769	},
1770};
1771
1772static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1773	.halt_reg = 0x90018,
1774	.halt_check = BRANCH_HALT_VOTED,
1775	.clkr = {
1776		.enable_reg = 0x52000,
1777		.enable_mask = BIT(25),
1778		.hw.init = &(const struct clk_init_data) {
1779			.name = "gcc_pcie_1_slv_q2a_axi_clk",
1780			.ops = &clk_branch2_ops,
1781		},
1782	},
1783};
1784
1785static struct clk_branch gcc_pcie_rscc_cfg_ahb_clk = {
1786	.halt_reg = 0x11004,
1787	.halt_check = BRANCH_HALT_VOTED,
1788	.hwcg_reg = 0x11004,
1789	.hwcg_bit = 1,
1790	.clkr = {
1791		.enable_reg = 0x52010,
1792		.enable_mask = BIT(20),
1793		.hw.init = &(const struct clk_init_data) {
1794			.name = "gcc_pcie_rscc_cfg_ahb_clk",
1795			.ops = &clk_branch2_ops,
1796		},
1797	},
1798};
1799
1800static struct clk_branch gcc_pcie_rscc_xo_clk = {
1801	.halt_reg = 0x11008,
1802	.halt_check = BRANCH_HALT_VOTED,
1803	.clkr = {
1804		.enable_reg = 0x52010,
1805		.enable_mask = BIT(21),
1806		.hw.init = &(const struct clk_init_data) {
1807			.name = "gcc_pcie_rscc_xo_clk",
1808			.ops = &clk_branch2_ops,
1809		},
1810	},
1811};
1812
1813static struct clk_branch gcc_pdm2_clk = {
1814	.halt_reg = 0x3300c,
1815	.halt_check = BRANCH_HALT,
1816	.clkr = {
1817		.enable_reg = 0x3300c,
1818		.enable_mask = BIT(0),
1819		.hw.init = &(const struct clk_init_data) {
1820			.name = "gcc_pdm2_clk",
1821			.parent_hws = (const struct clk_hw*[]) {
1822				&gcc_pdm2_clk_src.clkr.hw,
1823			},
1824			.num_parents = 1,
1825			.flags = CLK_SET_RATE_PARENT,
1826			.ops = &clk_branch2_ops,
1827		},
1828	},
1829};
1830
1831static struct clk_branch gcc_pdm_ahb_clk = {
1832	.halt_reg = 0x33004,
1833	.halt_check = BRANCH_HALT_VOTED,
1834	.hwcg_reg = 0x33004,
1835	.hwcg_bit = 1,
1836	.clkr = {
1837		.enable_reg = 0x33004,
1838		.enable_mask = BIT(0),
1839		.hw.init = &(const struct clk_init_data) {
1840			.name = "gcc_pdm_ahb_clk",
1841			.ops = &clk_branch2_ops,
1842		},
1843	},
1844};
1845
1846static struct clk_branch gcc_pdm_xo4_clk = {
1847	.halt_reg = 0x33008,
1848	.halt_check = BRANCH_HALT,
1849	.clkr = {
1850		.enable_reg = 0x33008,
1851		.enable_mask = BIT(0),
1852		.hw.init = &(const struct clk_init_data) {
1853			.name = "gcc_pdm_xo4_clk",
1854			.ops = &clk_branch2_ops,
1855		},
1856	},
1857};
1858
1859static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1860	.halt_reg = 0x26008,
1861	.halt_check = BRANCH_HALT_VOTED,
1862	.hwcg_reg = 0x26008,
1863	.hwcg_bit = 1,
1864	.clkr = {
1865		.enable_reg = 0x26008,
1866		.enable_mask = BIT(0),
1867		.hw.init = &(const struct clk_init_data) {
1868			.name = "gcc_qmip_camera_nrt_ahb_clk",
1869			.ops = &clk_branch2_ops,
1870		},
1871	},
1872};
1873
1874static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
1875	.halt_reg = 0x2600c,
1876	.halt_check = BRANCH_HALT_VOTED,
1877	.hwcg_reg = 0x2600c,
1878	.hwcg_bit = 1,
1879	.clkr = {
1880		.enable_reg = 0x2600c,
1881		.enable_mask = BIT(0),
1882		.hw.init = &(const struct clk_init_data) {
1883			.name = "gcc_qmip_camera_rt_ahb_clk",
1884			.ops = &clk_branch2_ops,
1885		},
1886	},
1887};
1888
1889static struct clk_branch gcc_qmip_disp_ahb_clk = {
1890	.halt_reg = 0x27008,
1891	.halt_check = BRANCH_HALT_VOTED,
1892	.hwcg_reg = 0x27008,
1893	.hwcg_bit = 1,
1894	.clkr = {
1895		.enable_reg = 0x27008,
1896		.enable_mask = BIT(0),
1897		.hw.init = &(const struct clk_init_data) {
1898			.name = "gcc_qmip_disp_ahb_clk",
1899			.ops = &clk_branch2_ops,
1900		},
1901	},
1902};
1903
1904static struct clk_branch gcc_qmip_gpu_ahb_clk = {
1905	.halt_reg = 0x71008,
1906	.halt_check = BRANCH_HALT_VOTED,
1907	.hwcg_reg = 0x71008,
1908	.hwcg_bit = 1,
1909	.clkr = {
1910		.enable_reg = 0x71008,
1911		.enable_mask = BIT(0),
1912		.hw.init = &(const struct clk_init_data) {
1913			.name = "gcc_qmip_gpu_ahb_clk",
1914			.ops = &clk_branch2_ops,
1915		},
1916	},
1917};
1918
1919static struct clk_branch gcc_qmip_pcie_ahb_clk = {
1920	.halt_reg = 0x6b018,
1921	.halt_check = BRANCH_HALT_VOTED,
1922	.hwcg_reg = 0x6b018,
1923	.hwcg_bit = 1,
1924	.clkr = {
1925		.enable_reg = 0x52000,
1926		.enable_mask = BIT(11),
1927		.hw.init = &(const struct clk_init_data) {
1928			.name = "gcc_qmip_pcie_ahb_clk",
1929			.ops = &clk_branch2_ops,
1930		},
1931	},
1932};
1933
1934static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
1935	.halt_reg = 0x32014,
1936	.halt_check = BRANCH_HALT_VOTED,
1937	.hwcg_reg = 0x32014,
1938	.hwcg_bit = 1,
1939	.clkr = {
1940		.enable_reg = 0x32014,
1941		.enable_mask = BIT(0),
1942		.hw.init = &(const struct clk_init_data) {
1943			.name = "gcc_qmip_video_cv_cpu_ahb_clk",
1944			.ops = &clk_branch2_ops,
1945		},
1946	},
1947};
1948
1949static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
1950	.halt_reg = 0x32008,
1951	.halt_check = BRANCH_HALT_VOTED,
1952	.hwcg_reg = 0x32008,
1953	.hwcg_bit = 1,
1954	.clkr = {
1955		.enable_reg = 0x32008,
1956		.enable_mask = BIT(0),
1957		.hw.init = &(const struct clk_init_data) {
1958			.name = "gcc_qmip_video_cvp_ahb_clk",
1959			.ops = &clk_branch2_ops,
1960		},
1961	},
1962};
1963
1964static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
1965	.halt_reg = 0x32010,
1966	.halt_check = BRANCH_HALT_VOTED,
1967	.hwcg_reg = 0x32010,
1968	.hwcg_bit = 1,
1969	.clkr = {
1970		.enable_reg = 0x32010,
1971		.enable_mask = BIT(0),
1972		.hw.init = &(const struct clk_init_data) {
1973			.name = "gcc_qmip_video_v_cpu_ahb_clk",
1974			.ops = &clk_branch2_ops,
1975		},
1976	},
1977};
1978
1979static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
1980	.halt_reg = 0x3200c,
1981	.halt_check = BRANCH_HALT_VOTED,
1982	.hwcg_reg = 0x3200c,
1983	.hwcg_bit = 1,
1984	.clkr = {
1985		.enable_reg = 0x3200c,
1986		.enable_mask = BIT(0),
1987		.hw.init = &(const struct clk_init_data) {
1988			.name = "gcc_qmip_video_vcodec_ahb_clk",
1989			.ops = &clk_branch2_ops,
1990		},
1991	},
1992};
1993
1994static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1995	.halt_reg = 0x23018,
1996	.halt_check = BRANCH_HALT_VOTED,
1997	.clkr = {
1998		.enable_reg = 0x52008,
1999		.enable_mask = BIT(18),
2000		.hw.init = &(const struct clk_init_data) {
2001			.name = "gcc_qupv3_wrap0_core_2x_clk",
2002			.ops = &clk_branch2_ops,
2003		},
2004	},
2005};
2006
2007static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2008	.halt_reg = 0x23008,
2009	.halt_check = BRANCH_HALT_VOTED,
2010	.clkr = {
2011		.enable_reg = 0x52008,
2012		.enable_mask = BIT(19),
2013		.hw.init = &(const struct clk_init_data) {
2014			.name = "gcc_qupv3_wrap0_core_clk",
2015			.ops = &clk_branch2_ops,
2016		},
2017	},
2018};
2019
2020static struct clk_branch gcc_qupv3_wrap0_qspi_ref_clk = {
2021	.halt_reg = 0x18764,
2022	.halt_check = BRANCH_HALT_VOTED,
2023	.clkr = {
2024		.enable_reg = 0x52010,
2025		.enable_mask = BIT(29),
2026		.hw.init = &(const struct clk_init_data) {
2027			.name = "gcc_qupv3_wrap0_qspi_ref_clk",
2028			.parent_hws = (const struct clk_hw*[]) {
2029				&gcc_qupv3_wrap0_qspi_ref_clk_src.clkr.hw,
2030			},
2031			.num_parents = 1,
2032			.flags = CLK_SET_RATE_PARENT,
2033			.ops = &clk_branch2_ops,
2034		},
2035	},
2036};
2037
2038static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2039	.halt_reg = 0x18004,
2040	.halt_check = BRANCH_HALT_VOTED,
2041	.clkr = {
2042		.enable_reg = 0x52008,
2043		.enable_mask = BIT(22),
2044		.hw.init = &(const struct clk_init_data) {
2045			.name = "gcc_qupv3_wrap0_s0_clk",
2046			.parent_hws = (const struct clk_hw*[]) {
2047				&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2048			},
2049			.num_parents = 1,
2050			.flags = CLK_SET_RATE_PARENT,
2051			.ops = &clk_branch2_ops,
2052		},
2053	},
2054};
2055
2056static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2057	.halt_reg = 0x1813c,
2058	.halt_check = BRANCH_HALT_VOTED,
2059	.clkr = {
2060		.enable_reg = 0x52008,
2061		.enable_mask = BIT(23),
2062		.hw.init = &(const struct clk_init_data) {
2063			.name = "gcc_qupv3_wrap0_s1_clk",
2064			.parent_hws = (const struct clk_hw*[]) {
2065				&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2066			},
2067			.num_parents = 1,
2068			.flags = CLK_SET_RATE_PARENT,
2069			.ops = &clk_branch2_ops,
2070		},
2071	},
2072};
2073
2074static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2075	.halt_reg = 0x18274,
2076	.halt_check = BRANCH_HALT_VOTED,
2077	.clkr = {
2078		.enable_reg = 0x52008,
2079		.enable_mask = BIT(24),
2080		.hw.init = &(const struct clk_init_data) {
2081			.name = "gcc_qupv3_wrap0_s2_clk",
2082			.parent_hws = (const struct clk_hw*[]) {
2083				&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2084			},
2085			.num_parents = 1,
2086			.flags = CLK_SET_RATE_PARENT,
2087			.ops = &clk_branch2_ops,
2088		},
2089	},
2090};
2091
2092static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2093	.halt_reg = 0x18284,
2094	.halt_check = BRANCH_HALT_VOTED,
2095	.clkr = {
2096		.enable_reg = 0x52008,
2097		.enable_mask = BIT(25),
2098		.hw.init = &(const struct clk_init_data) {
2099			.name = "gcc_qupv3_wrap0_s3_clk",
2100			.parent_hws = (const struct clk_hw*[]) {
2101				&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2102			},
2103			.num_parents = 1,
2104			.flags = CLK_SET_RATE_PARENT,
2105			.ops = &clk_branch2_ops,
2106		},
2107	},
2108};
2109
2110static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2111	.halt_reg = 0x183bc,
2112	.halt_check = BRANCH_HALT_VOTED,
2113	.clkr = {
2114		.enable_reg = 0x52008,
2115		.enable_mask = BIT(26),
2116		.hw.init = &(const struct clk_init_data) {
2117			.name = "gcc_qupv3_wrap0_s4_clk",
2118			.parent_hws = (const struct clk_hw*[]) {
2119				&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2120			},
2121			.num_parents = 1,
2122			.flags = CLK_SET_RATE_PARENT,
2123			.ops = &clk_branch2_ops,
2124		},
2125	},
2126};
2127
2128static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2129	.halt_reg = 0x184f4,
2130	.halt_check = BRANCH_HALT_VOTED,
2131	.clkr = {
2132		.enable_reg = 0x52008,
2133		.enable_mask = BIT(27),
2134		.hw.init = &(const struct clk_init_data) {
2135			.name = "gcc_qupv3_wrap0_s5_clk",
2136			.parent_hws = (const struct clk_hw*[]) {
2137				&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2138			},
2139			.num_parents = 1,
2140			.flags = CLK_SET_RATE_PARENT,
2141			.ops = &clk_branch2_ops,
2142		},
2143	},
2144};
2145
2146static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2147	.halt_reg = 0x1862c,
2148	.halt_check = BRANCH_HALT_VOTED,
2149	.clkr = {
2150		.enable_reg = 0x52008,
2151		.enable_mask = BIT(28),
2152		.hw.init = &(const struct clk_init_data) {
2153			.name = "gcc_qupv3_wrap0_s6_clk",
2154			.parent_hws = (const struct clk_hw*[]) {
2155				&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2156			},
2157			.num_parents = 1,
2158			.flags = CLK_SET_RATE_PARENT,
2159			.ops = &clk_branch2_ops,
2160		},
2161	},
2162};
2163
2164static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2165	.halt_reg = 0x23168,
2166	.halt_check = BRANCH_HALT_VOTED,
2167	.clkr = {
2168		.enable_reg = 0x52010,
2169		.enable_mask = BIT(3),
2170		.hw.init = &(const struct clk_init_data) {
2171			.name = "gcc_qupv3_wrap1_core_2x_clk",
2172			.ops = &clk_branch2_ops,
2173		},
2174	},
2175};
2176
2177static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2178	.halt_reg = 0x23158,
2179	.halt_check = BRANCH_HALT_VOTED,
2180	.clkr = {
2181		.enable_reg = 0x52010,
2182		.enable_mask = BIT(0),
2183		.hw.init = &(const struct clk_init_data) {
2184			.name = "gcc_qupv3_wrap1_core_clk",
2185			.ops = &clk_branch2_ops,
2186		},
2187	},
2188};
2189
2190static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk = {
2191	.halt_reg = 0x1e764,
2192	.halt_check = BRANCH_HALT_VOTED,
2193	.clkr = {
2194		.enable_reg = 0x52010,
2195		.enable_mask = BIT(30),
2196		.hw.init = &(const struct clk_init_data) {
2197			.name = "gcc_qupv3_wrap1_qspi_ref_clk",
2198			.parent_hws = (const struct clk_hw*[]) {
2199				&gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw,
2200			},
2201			.num_parents = 1,
2202			.flags = CLK_SET_RATE_PARENT,
2203			.ops = &clk_branch2_ops,
2204		},
2205	},
2206};
2207
2208static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2209	.halt_reg = 0x1e004,
2210	.halt_check = BRANCH_HALT_VOTED,
2211	.clkr = {
2212		.enable_reg = 0x52010,
2213		.enable_mask = BIT(4),
2214		.hw.init = &(const struct clk_init_data) {
2215			.name = "gcc_qupv3_wrap1_s0_clk",
2216			.parent_hws = (const struct clk_hw*[]) {
2217				&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2218			},
2219			.num_parents = 1,
2220			.flags = CLK_SET_RATE_PARENT,
2221			.ops = &clk_branch2_ops,
2222		},
2223	},
2224};
2225
2226static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2227	.halt_reg = 0x1e13c,
2228	.halt_check = BRANCH_HALT_VOTED,
2229	.clkr = {
2230		.enable_reg = 0x52010,
2231		.enable_mask = BIT(5),
2232		.hw.init = &(const struct clk_init_data) {
2233			.name = "gcc_qupv3_wrap1_s1_clk",
2234			.parent_hws = (const struct clk_hw*[]) {
2235				&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2236			},
2237			.num_parents = 1,
2238			.flags = CLK_SET_RATE_PARENT,
2239			.ops = &clk_branch2_ops,
2240		},
2241	},
2242};
2243
2244static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2245	.halt_reg = 0x1e274,
2246	.halt_check = BRANCH_HALT_VOTED,
2247	.clkr = {
2248		.enable_reg = 0x52010,
2249		.enable_mask = BIT(6),
2250		.hw.init = &(const struct clk_init_data) {
2251			.name = "gcc_qupv3_wrap1_s2_clk",
2252			.parent_hws = (const struct clk_hw*[]) {
2253				&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2254			},
2255			.num_parents = 1,
2256			.flags = CLK_SET_RATE_PARENT,
2257			.ops = &clk_branch2_ops,
2258		},
2259	},
2260};
2261
2262static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2263	.halt_reg = 0x1e284,
2264	.halt_check = BRANCH_HALT_VOTED,
2265	.clkr = {
2266		.enable_reg = 0x52010,
2267		.enable_mask = BIT(7),
2268		.hw.init = &(const struct clk_init_data) {
2269			.name = "gcc_qupv3_wrap1_s3_clk",
2270			.parent_hws = (const struct clk_hw*[]) {
2271				&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2272			},
2273			.num_parents = 1,
2274			.flags = CLK_SET_RATE_PARENT,
2275			.ops = &clk_branch2_ops,
2276		},
2277	},
2278};
2279
2280static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2281	.halt_reg = 0x1e3bc,
2282	.halt_check = BRANCH_HALT_VOTED,
2283	.clkr = {
2284		.enable_reg = 0x52010,
2285		.enable_mask = BIT(8),
2286		.hw.init = &(const struct clk_init_data) {
2287			.name = "gcc_qupv3_wrap1_s4_clk",
2288			.parent_hws = (const struct clk_hw*[]) {
2289				&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2290			},
2291			.num_parents = 1,
2292			.flags = CLK_SET_RATE_PARENT,
2293			.ops = &clk_branch2_ops,
2294		},
2295	},
2296};
2297
2298static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2299	.halt_reg = 0x1e4f4,
2300	.halt_check = BRANCH_HALT_VOTED,
2301	.clkr = {
2302		.enable_reg = 0x52010,
2303		.enable_mask = BIT(9),
2304		.hw.init = &(const struct clk_init_data) {
2305			.name = "gcc_qupv3_wrap1_s5_clk",
2306			.parent_hws = (const struct clk_hw*[]) {
2307				&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2308			},
2309			.num_parents = 1,
2310			.flags = CLK_SET_RATE_PARENT,
2311			.ops = &clk_branch2_ops,
2312		},
2313	},
2314};
2315
2316static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2317	.halt_reg = 0x1e62c,
2318	.halt_check = BRANCH_HALT_VOTED,
2319	.clkr = {
2320		.enable_reg = 0x52010,
2321		.enable_mask = BIT(10),
2322		.hw.init = &(const struct clk_init_data) {
2323			.name = "gcc_qupv3_wrap1_s6_clk",
2324			.parent_hws = (const struct clk_hw*[]) {
2325				&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2326			},
2327			.num_parents = 1,
2328			.flags = CLK_SET_RATE_PARENT,
2329			.ops = &clk_branch2_ops,
2330		},
2331	},
2332};
2333
2334static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2335	.halt_reg = 0x23000,
2336	.halt_check = BRANCH_HALT_VOTED,
2337	.clkr = {
2338		.enable_reg = 0x52008,
2339		.enable_mask = BIT(20),
2340		.hw.init = &(const struct clk_init_data) {
2341			.name = "gcc_qupv3_wrap_0_m_ahb_clk",
2342			.ops = &clk_branch2_ops,
2343		},
2344	},
2345};
2346
2347static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2348	.halt_reg = 0x23004,
2349	.halt_check = BRANCH_HALT_VOTED,
2350	.hwcg_reg = 0x23004,
2351	.hwcg_bit = 1,
2352	.clkr = {
2353		.enable_reg = 0x52008,
2354		.enable_mask = BIT(21),
2355		.hw.init = &(const struct clk_init_data) {
2356			.name = "gcc_qupv3_wrap_0_s_ahb_clk",
2357			.ops = &clk_branch2_ops,
2358		},
2359	},
2360};
2361
2362static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2363	.halt_reg = 0x23150,
2364	.halt_check = BRANCH_HALT_VOTED,
2365	.clkr = {
2366		.enable_reg = 0x52010,
2367		.enable_mask = BIT(2),
2368		.hw.init = &(const struct clk_init_data) {
2369			.name = "gcc_qupv3_wrap_1_m_ahb_clk",
2370			.ops = &clk_branch2_ops,
2371		},
2372	},
2373};
2374
2375static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2376	.halt_reg = 0x23154,
2377	.halt_check = BRANCH_HALT_VOTED,
2378	.hwcg_reg = 0x23154,
2379	.hwcg_bit = 1,
2380	.clkr = {
2381		.enable_reg = 0x52010,
2382		.enable_mask = BIT(1),
2383		.hw.init = &(const struct clk_init_data) {
2384			.name = "gcc_qupv3_wrap_1_s_ahb_clk",
2385			.ops = &clk_branch2_ops,
2386		},
2387	},
2388};
2389
2390static struct clk_branch gcc_sdcc1_ahb_clk = {
2391	.halt_reg = 0xa3004,
2392	.halt_check = BRANCH_HALT,
2393	.clkr = {
2394		.enable_reg = 0xa3004,
2395		.enable_mask = BIT(0),
2396		.hw.init = &(const struct clk_init_data) {
2397			.name = "gcc_sdcc1_ahb_clk",
2398			.ops = &clk_branch2_ops,
2399		},
2400	},
2401};
2402
2403static struct clk_branch gcc_sdcc1_apps_clk = {
2404	.halt_reg = 0xa3008,
2405	.halt_check = BRANCH_HALT,
2406	.clkr = {
2407		.enable_reg = 0xa3008,
2408		.enable_mask = BIT(0),
2409		.hw.init = &(const struct clk_init_data) {
2410			.name = "gcc_sdcc1_apps_clk",
2411			.parent_hws = (const struct clk_hw*[]) {
2412				&gcc_sdcc1_apps_clk_src.clkr.hw,
2413			},
2414			.num_parents = 1,
2415			.flags = CLK_SET_RATE_PARENT,
2416			.ops = &clk_branch2_ops,
2417		},
2418	},
2419};
2420
2421static struct clk_branch gcc_sdcc1_ice_core_clk = {
2422	.halt_reg = 0xa302c,
2423	.halt_check = BRANCH_HALT_VOTED,
2424	.hwcg_reg = 0xa302c,
2425	.hwcg_bit = 1,
2426	.clkr = {
2427		.enable_reg = 0xa302c,
2428		.enable_mask = BIT(0),
2429		.hw.init = &(const struct clk_init_data) {
2430			.name = "gcc_sdcc1_ice_core_clk",
2431			.parent_hws = (const struct clk_hw*[]) {
2432				&gcc_sdcc1_ice_core_clk_src.clkr.hw,
2433			},
2434			.num_parents = 1,
2435			.flags = CLK_SET_RATE_PARENT,
2436			.ops = &clk_branch2_ops,
2437		},
2438	},
2439};
2440
2441static struct clk_branch gcc_sdcc2_ahb_clk = {
2442	.halt_reg = 0x14010,
2443	.halt_check = BRANCH_HALT,
2444	.clkr = {
2445		.enable_reg = 0x14010,
2446		.enable_mask = BIT(0),
2447		.hw.init = &(const struct clk_init_data) {
2448			.name = "gcc_sdcc2_ahb_clk",
2449			.ops = &clk_branch2_ops,
2450		},
2451	},
2452};
2453
2454static struct clk_branch gcc_sdcc2_apps_clk = {
2455	.halt_reg = 0x14004,
2456	.halt_check = BRANCH_HALT,
2457	.clkr = {
2458		.enable_reg = 0x14004,
2459		.enable_mask = BIT(0),
2460		.hw.init = &(const struct clk_init_data) {
2461			.name = "gcc_sdcc2_apps_clk",
2462			.parent_hws = (const struct clk_hw*[]) {
2463				&gcc_sdcc2_apps_clk_src.clkr.hw,
2464			},
2465			.num_parents = 1,
2466			.flags = CLK_SET_RATE_PARENT,
2467			.ops = &clk_branch2_ops,
2468		},
2469	},
2470};
2471
2472static struct clk_branch gcc_ufs_phy_ahb_clk = {
2473	.halt_reg = 0x77024,
2474	.halt_check = BRANCH_HALT_VOTED,
2475	.hwcg_reg = 0x77024,
2476	.hwcg_bit = 1,
2477	.clkr = {
2478		.enable_reg = 0x77024,
2479		.enable_mask = BIT(0),
2480		.hw.init = &(const struct clk_init_data) {
2481			.name = "gcc_ufs_phy_ahb_clk",
2482			.ops = &clk_branch2_ops,
2483		},
2484	},
2485};
2486
2487static struct clk_branch gcc_ufs_phy_axi_clk = {
2488	.halt_reg = 0x77018,
2489	.halt_check = BRANCH_HALT_VOTED,
2490	.hwcg_reg = 0x77018,
2491	.hwcg_bit = 1,
2492	.clkr = {
2493		.enable_reg = 0x77018,
2494		.enable_mask = BIT(0),
2495		.hw.init = &(const struct clk_init_data) {
2496			.name = "gcc_ufs_phy_axi_clk",
2497			.parent_hws = (const struct clk_hw*[]) {
2498				&gcc_ufs_phy_axi_clk_src.clkr.hw,
2499			},
2500			.num_parents = 1,
2501			.flags = CLK_SET_RATE_PARENT,
2502			.ops = &clk_branch2_ops,
2503		},
2504	},
2505};
2506
2507static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2508	.halt_reg = 0x77018,
2509	.halt_check = BRANCH_HALT_VOTED,
2510	.hwcg_reg = 0x77018,
2511	.hwcg_bit = 1,
2512	.clkr = {
2513		.enable_reg = 0x77018,
2514		.enable_mask = BIT(1),
2515		.hw.init = &(const struct clk_init_data) {
2516			.name = "gcc_ufs_phy_axi_hw_ctl_clk",
2517			.parent_hws = (const struct clk_hw*[]) {
2518				&gcc_ufs_phy_axi_clk_src.clkr.hw,
2519			},
2520			.num_parents = 1,
2521			.flags = CLK_SET_RATE_PARENT,
2522			.ops = &clk_branch2_ops,
2523		},
2524	},
2525};
2526
2527static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2528	.halt_reg = 0x77074,
2529	.halt_check = BRANCH_HALT_VOTED,
2530	.hwcg_reg = 0x77074,
2531	.hwcg_bit = 1,
2532	.clkr = {
2533		.enable_reg = 0x77074,
2534		.enable_mask = BIT(0),
2535		.hw.init = &(const struct clk_init_data) {
2536			.name = "gcc_ufs_phy_ice_core_clk",
2537			.parent_hws = (const struct clk_hw*[]) {
2538				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2539			},
2540			.num_parents = 1,
2541			.flags = CLK_SET_RATE_PARENT,
2542			.ops = &clk_branch2_ops,
2543		},
2544	},
2545};
2546
2547static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2548	.halt_reg = 0x77074,
2549	.halt_check = BRANCH_HALT_VOTED,
2550	.hwcg_reg = 0x77074,
2551	.hwcg_bit = 1,
2552	.clkr = {
2553		.enable_reg = 0x77074,
2554		.enable_mask = BIT(1),
2555		.hw.init = &(const struct clk_init_data) {
2556			.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2557			.parent_hws = (const struct clk_hw*[]) {
2558				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2559			},
2560			.num_parents = 1,
2561			.flags = CLK_SET_RATE_PARENT,
2562			.ops = &clk_branch2_ops,
2563		},
2564	},
2565};
2566
2567static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2568	.halt_reg = 0x770b0,
2569	.halt_check = BRANCH_HALT_VOTED,
2570	.hwcg_reg = 0x770b0,
2571	.hwcg_bit = 1,
2572	.clkr = {
2573		.enable_reg = 0x770b0,
2574		.enable_mask = BIT(0),
2575		.hw.init = &(const struct clk_init_data) {
2576			.name = "gcc_ufs_phy_phy_aux_clk",
2577			.parent_hws = (const struct clk_hw*[]) {
2578				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2579			},
2580			.num_parents = 1,
2581			.flags = CLK_SET_RATE_PARENT,
2582			.ops = &clk_branch2_ops,
2583		},
2584	},
2585};
2586
2587static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2588	.halt_reg = 0x770b0,
2589	.halt_check = BRANCH_HALT_VOTED,
2590	.hwcg_reg = 0x770b0,
2591	.hwcg_bit = 1,
2592	.clkr = {
2593		.enable_reg = 0x770b0,
2594		.enable_mask = BIT(1),
2595		.hw.init = &(const struct clk_init_data) {
2596			.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2597			.parent_hws = (const struct clk_hw*[]) {
2598				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2599			},
2600			.num_parents = 1,
2601			.flags = CLK_SET_RATE_PARENT,
2602			.ops = &clk_branch2_ops,
2603		},
2604	},
2605};
2606
2607static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2608	.halt_reg = 0x7702c,
2609	.halt_check = BRANCH_HALT_DELAY,
2610	.clkr = {
2611		.enable_reg = 0x7702c,
2612		.enable_mask = BIT(0),
2613		.hw.init = &(const struct clk_init_data) {
2614			.name = "gcc_ufs_phy_rx_symbol_0_clk",
2615			.parent_hws = (const struct clk_hw*[]) {
2616				&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
2617			},
2618			.num_parents = 1,
2619			.flags = CLK_SET_RATE_PARENT,
2620			.ops = &clk_branch2_ops,
2621		},
2622	},
2623};
2624
2625static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2626	.halt_reg = 0x770cc,
2627	.halt_check = BRANCH_HALT_DELAY,
2628	.clkr = {
2629		.enable_reg = 0x770cc,
2630		.enable_mask = BIT(0),
2631		.hw.init = &(const struct clk_init_data) {
2632			.name = "gcc_ufs_phy_rx_symbol_1_clk",
2633			.parent_hws = (const struct clk_hw*[]) {
2634				&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
2635			},
2636			.num_parents = 1,
2637			.flags = CLK_SET_RATE_PARENT,
2638			.ops = &clk_branch2_ops,
2639		},
2640	},
2641};
2642
2643static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2644	.halt_reg = 0x77028,
2645	.halt_check = BRANCH_HALT_DELAY,
2646	.clkr = {
2647		.enable_reg = 0x77028,
2648		.enable_mask = BIT(0),
2649		.hw.init = &(const struct clk_init_data) {
2650			.name = "gcc_ufs_phy_tx_symbol_0_clk",
2651			.parent_hws = (const struct clk_hw*[]) {
2652				&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
2653			},
2654			.num_parents = 1,
2655			.flags = CLK_SET_RATE_PARENT,
2656			.ops = &clk_branch2_ops,
2657		},
2658	},
2659};
2660
2661static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2662	.halt_reg = 0x77068,
2663	.halt_check = BRANCH_HALT_VOTED,
2664	.hwcg_reg = 0x77068,
2665	.hwcg_bit = 1,
2666	.clkr = {
2667		.enable_reg = 0x77068,
2668		.enable_mask = BIT(0),
2669		.hw.init = &(const struct clk_init_data) {
2670			.name = "gcc_ufs_phy_unipro_core_clk",
2671			.parent_hws = (const struct clk_hw*[]) {
2672				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2673			},
2674			.num_parents = 1,
2675			.flags = CLK_SET_RATE_PARENT,
2676			.ops = &clk_branch2_ops,
2677		},
2678	},
2679};
2680
2681static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
2682	.halt_reg = 0x77068,
2683	.halt_check = BRANCH_HALT_VOTED,
2684	.hwcg_reg = 0x77068,
2685	.hwcg_bit = 1,
2686	.clkr = {
2687		.enable_reg = 0x77068,
2688		.enable_mask = BIT(1),
2689		.hw.init = &(const struct clk_init_data) {
2690			.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
2691			.parent_hws = (const struct clk_hw*[]) {
2692				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2693			},
2694			.num_parents = 1,
2695			.flags = CLK_SET_RATE_PARENT,
2696			.ops = &clk_branch2_ops,
2697		},
2698	},
2699};
2700
2701static struct clk_branch gcc_usb30_prim_atb_clk = {
2702	.halt_reg = 0x39088,
2703	.halt_check = BRANCH_HALT_VOTED,
2704	.clkr = {
2705		.enable_reg = 0x39088,
2706		.enable_mask = BIT(0),
2707		.hw.init = &(const struct clk_init_data) {
2708			.name = "gcc_usb30_prim_atb_clk",
2709			.parent_hws = (const struct clk_hw*[]) {
2710				&gcc_usb30_prim_master_clk_src.clkr.hw,
2711			},
2712			.num_parents = 1,
2713			.flags = CLK_SET_RATE_PARENT,
2714			.ops = &clk_branch2_ops,
2715		},
2716	},
2717};
2718
2719static struct clk_branch gcc_usb30_prim_master_clk = {
2720	.halt_reg = 0x39018,
2721	.halt_check = BRANCH_HALT,
2722	.clkr = {
2723		.enable_reg = 0x39018,
2724		.enable_mask = BIT(0),
2725		.hw.init = &(const struct clk_init_data) {
2726			.name = "gcc_usb30_prim_master_clk",
2727			.parent_hws = (const struct clk_hw*[]) {
2728				&gcc_usb30_prim_master_clk_src.clkr.hw,
2729			},
2730			.num_parents = 1,
2731			.flags = CLK_SET_RATE_PARENT,
2732			.ops = &clk_branch2_ops,
2733		},
2734	},
2735};
2736
2737static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2738	.halt_reg = 0x39028,
2739	.halt_check = BRANCH_HALT,
2740	.clkr = {
2741		.enable_reg = 0x39028,
2742		.enable_mask = BIT(0),
2743		.hw.init = &(const struct clk_init_data) {
2744			.name = "gcc_usb30_prim_mock_utmi_clk",
2745			.parent_hws = (const struct clk_hw*[]) {
2746				&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2747			},
2748			.num_parents = 1,
2749			.flags = CLK_SET_RATE_PARENT,
2750			.ops = &clk_branch2_ops,
2751		},
2752	},
2753};
2754
2755static struct clk_branch gcc_usb30_prim_sleep_clk = {
2756	.halt_reg = 0x39024,
2757	.halt_check = BRANCH_HALT,
2758	.clkr = {
2759		.enable_reg = 0x39024,
2760		.enable_mask = BIT(0),
2761		.hw.init = &(const struct clk_init_data) {
2762			.name = "gcc_usb30_prim_sleep_clk",
2763			.ops = &clk_branch2_ops,
2764		},
2765	},
2766};
2767
2768static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2769	.halt_reg = 0x39060,
2770	.halt_check = BRANCH_HALT,
2771	.clkr = {
2772		.enable_reg = 0x39060,
2773		.enable_mask = BIT(0),
2774		.hw.init = &(const struct clk_init_data) {
2775			.name = "gcc_usb3_prim_phy_aux_clk",
2776			.parent_hws = (const struct clk_hw*[]) {
2777				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2778			},
2779			.num_parents = 1,
2780			.flags = CLK_SET_RATE_PARENT,
2781			.ops = &clk_branch2_ops,
2782		},
2783	},
2784};
2785
2786static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2787	.halt_reg = 0x39064,
2788	.halt_check = BRANCH_HALT,
2789	.clkr = {
2790		.enable_reg = 0x39064,
2791		.enable_mask = BIT(0),
2792		.hw.init = &(const struct clk_init_data) {
2793			.name = "gcc_usb3_prim_phy_com_aux_clk",
2794			.parent_hws = (const struct clk_hw*[]) {
2795				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2796			},
2797			.num_parents = 1,
2798			.flags = CLK_SET_RATE_PARENT,
2799			.ops = &clk_branch2_ops,
2800		},
2801	},
2802};
2803
2804static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2805	.halt_reg = 0x39068,
2806	.halt_check = BRANCH_HALT_DELAY,
2807	.hwcg_reg = 0x39068,
2808	.hwcg_bit = 1,
2809	.clkr = {
2810		.enable_reg = 0x39068,
2811		.enable_mask = BIT(0),
2812		.hw.init = &(const struct clk_init_data) {
2813			.name = "gcc_usb3_prim_phy_pipe_clk",
2814			.parent_hws = (const struct clk_hw*[]) {
2815				&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
2816			},
2817			.num_parents = 1,
2818			.flags = CLK_SET_RATE_PARENT,
2819			.ops = &clk_branch2_ops,
2820		},
2821	},
2822};
2823
2824static struct clk_branch gcc_video_axi0_clk = {
2825	.halt_reg = 0x32018,
2826	.halt_check = BRANCH_HALT_SKIP,
2827	.hwcg_reg = 0x32018,
2828	.hwcg_bit = 1,
2829	.clkr = {
2830		.enable_reg = 0x32018,
2831		.enable_mask = BIT(0),
2832		.hw.init = &(const struct clk_init_data) {
2833			.name = "gcc_video_axi0_clk",
2834			.ops = &clk_branch2_ops,
2835		},
2836	},
2837};
2838
2839static struct gdsc pcie_0_gdsc = {
2840	.gdscr = 0x6b004,
2841	.collapse_ctrl = 0x5214c,
2842	.collapse_mask = BIT(0),
2843	.en_rest_wait_val = 0x2,
2844	.en_few_wait_val = 0x2,
2845	.clk_dis_wait_val = 0xf,
2846	.pd = {
2847		.name = "pcie_0_gdsc",
2848	},
2849	.pwrsts = PWRSTS_OFF_ON,
2850	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2851};
2852
2853static struct gdsc pcie_0_phy_gdsc = {
2854	.gdscr = 0x6c000,
2855	.collapse_ctrl = 0x5214c,
2856	.collapse_mask = BIT(1),
2857	.en_rest_wait_val = 0x2,
2858	.en_few_wait_val = 0x2,
2859	.clk_dis_wait_val = 0x2,
2860	.pd = {
2861		.name = "pcie_0_phy_gdsc",
2862	},
2863	.pwrsts = PWRSTS_OFF_ON,
2864	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2865};
2866
2867static struct gdsc pcie_1_gdsc = {
2868	.gdscr = 0x90004,
2869	.collapse_ctrl = 0x5214c,
2870	.collapse_mask = BIT(3),
2871	.en_rest_wait_val = 0x2,
2872	.en_few_wait_val = 0x2,
2873	.clk_dis_wait_val = 0xf,
2874	.pd = {
2875		.name = "pcie_1_gdsc",
2876	},
2877	.pwrsts = PWRSTS_OFF_ON,
2878	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2879};
2880
2881static struct gdsc pcie_1_phy_gdsc = {
2882	.gdscr = 0xa2000,
2883	.collapse_ctrl = 0x5214c,
2884	.collapse_mask = BIT(4),
2885	.en_rest_wait_val = 0x2,
2886	.en_few_wait_val = 0x2,
2887	.clk_dis_wait_val = 0x2,
2888	.pd = {
2889		.name = "pcie_1_phy_gdsc",
2890	},
2891	.pwrsts = PWRSTS_OFF_ON,
2892	.flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2893};
2894
2895static struct gdsc ufs_phy_gdsc = {
2896	.gdscr = 0x77004,
2897	.en_rest_wait_val = 0x2,
2898	.en_few_wait_val = 0x2,
2899	.clk_dis_wait_val = 0xf,
2900	.pd = {
2901		.name = "ufs_phy_gdsc",
2902	},
2903	.pwrsts = PWRSTS_OFF_ON,
2904	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2905};
2906
2907static struct gdsc ufs_mem_phy_gdsc = {
2908	.gdscr = 0x9e000,
2909	.en_rest_wait_val = 0x2,
2910	.en_few_wait_val = 0x2,
2911	.clk_dis_wait_val = 0x2,
2912	.pd = {
2913		.name = "ufs_mem_phy_gdsc",
2914	},
2915	.pwrsts = PWRSTS_OFF_ON,
2916	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2917};
2918
2919static struct gdsc usb30_prim_gdsc = {
2920	.gdscr = 0x39004,
2921	.en_rest_wait_val = 0x2,
2922	.en_few_wait_val = 0x2,
2923	.clk_dis_wait_val = 0xf,
2924	.pd = {
2925		.name = "usb30_prim_gdsc",
2926	},
2927	.pwrsts = PWRSTS_RET_ON,
2928	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2929};
2930
2931static struct gdsc usb3_phy_gdsc = {
2932	.gdscr = 0x5000c,
2933	.en_rest_wait_val = 0x2,
2934	.en_few_wait_val = 0x2,
2935	.clk_dis_wait_val = 0x2,
2936	.pd = {
2937		.name = "usb3_phy_gdsc",
2938	},
2939	.pwrsts = PWRSTS_RET_ON,
2940	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
2941};
2942
2943static struct clk_regmap *gcc_milos_clocks[] = {
2944	[GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr,
2945	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2946	[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
2947	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2948	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2949	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
2950	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
2951	[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
2952	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2953	[GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr,
2954	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2955	[GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr,
2956	[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
2957	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
2958	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2959	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2960	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2961	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2962	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2963	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2964	[GCC_GPLL0] = &gcc_gpll0.clkr,
2965	[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
2966	[GCC_GPLL2] = &gcc_gpll2.clkr,
2967	[GCC_GPLL4] = &gcc_gpll4.clkr,
2968	[GCC_GPLL6] = &gcc_gpll6.clkr,
2969	[GCC_GPLL7] = &gcc_gpll7.clkr,
2970	[GCC_GPLL9] = &gcc_gpll9.clkr,
2971	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
2972	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
2973	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2974	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2975	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2976	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
2977	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2978	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2979	[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
2980	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
2981	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2982	[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
2983	[GCC_PCIE_0_PIPE_DIV2_CLK] = &gcc_pcie_0_pipe_div2_clk.clkr,
2984	[GCC_PCIE_0_PIPE_DIV2_CLK_SRC] = &gcc_pcie_0_pipe_div2_clk_src.clkr,
2985	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2986	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
2987	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2988	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
2989	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
2990	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
2991	[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
2992	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
2993	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2994	[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
2995	[GCC_PCIE_1_PIPE_DIV2_CLK] = &gcc_pcie_1_pipe_div2_clk.clkr,
2996	[GCC_PCIE_1_PIPE_DIV2_CLK_SRC] = &gcc_pcie_1_pipe_div2_clk_src.clkr,
2997	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
2998	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
2999	[GCC_PCIE_RSCC_CFG_AHB_CLK] = &gcc_pcie_rscc_cfg_ahb_clk.clkr,
3000	[GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr,
3001	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3002	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3003	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3004	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3005	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3006	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3007	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3008	[GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
3009	[GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
3010	[GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
3011	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3012	[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
3013	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3014	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3015	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3016	[GCC_QUPV3_WRAP0_QSPI_REF_CLK] = &gcc_qupv3_wrap0_qspi_ref_clk.clkr,
3017	[GCC_QUPV3_WRAP0_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap0_qspi_ref_clk_src.clkr,
3018	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3019	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3020	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3021	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3022	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3023	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3024	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3025	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3026	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3027	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3028	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3029	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3030	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3031	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3032	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3033	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3034	[GCC_QUPV3_WRAP1_QSPI_REF_CLK] = &gcc_qupv3_wrap1_qspi_ref_clk.clkr,
3035	[GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr,
3036	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3037	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3038	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3039	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3040	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3041	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3042	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3043	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3044	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3045	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3046	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3047	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3048	[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3049	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3050	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3051	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3052	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3053	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3054	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3055	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3056	[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3057	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3058	[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
3059	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3060	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3061	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3062	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3063	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3064	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3065	[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3066	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3067	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3068	[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3069	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3070	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3071	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3072	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3073	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3074	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3075	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3076	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3077	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3078	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3079	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3080	[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3081	[GCC_USB30_PRIM_ATB_CLK] = &gcc_usb30_prim_atb_clk.clkr,
3082	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3083	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3084	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3085	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3086	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3087	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3088	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3089	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3090	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3091	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3092	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3093	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3094};
3095
3096static const struct qcom_reset_map gcc_milos_resets[] = {
3097	[GCC_CAMERA_BCR] = { 0x26000 },
3098	[GCC_DISPLAY_BCR] = { 0x27000 },
3099	[GCC_GPU_BCR] = { 0x71000 },
3100	[GCC_PCIE_0_BCR] = { 0x6b000 },
3101	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3102	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3103	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3104	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3105	[GCC_PCIE_1_BCR] = { 0x90000 },
3106	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3107	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3108	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3109	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
3110	[GCC_PCIE_RSCC_BCR] = { 0x11000 },
3111	[GCC_PDM_BCR] = { 0x33000 },
3112	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x18000 },
3113	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x1e000 },
3114	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3115	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3116	[GCC_SDCC1_BCR] = { 0xa3000 },
3117	[GCC_SDCC2_BCR] = { 0x14000 },
3118	[GCC_UFS_PHY_BCR] = { 0x77000 },
3119	[GCC_USB30_PRIM_BCR] = { 0x39000 },
3120	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3121	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3122	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3123	[GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },
3124	[GCC_VIDEO_BCR] = { 0x32000 },
3125};
3126
3127static const struct clk_rcg_dfs_data gcc_milos_dfs_clocks[] = {
3128	DEFINE_RCG_DFS(gcc_qupv3_wrap0_qspi_ref_clk_src),
3129	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3130	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3131	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3132	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3133	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3134	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3135	DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src),
3136	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3137	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3138	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3139	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3140	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3141	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3142};
3143
3144static struct gdsc *gcc_milos_gdscs[] = {
3145	[PCIE_0_GDSC] = &pcie_0_gdsc,
3146	[PCIE_0_PHY_GDSC] = &pcie_0_phy_gdsc,
3147	[PCIE_1_GDSC] = &pcie_1_gdsc,
3148	[PCIE_1_PHY_GDSC] = &pcie_1_phy_gdsc,
3149	[UFS_PHY_GDSC] = &ufs_phy_gdsc,
3150	[UFS_MEM_PHY_GDSC] = &ufs_mem_phy_gdsc,
3151	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3152	[USB3_PHY_GDSC] = &usb3_phy_gdsc,
3153};
3154
3155static u32 gcc_milos_critical_cbcrs[] = {
3156	0x26004, /* GCC_CAMERA_AHB_CLK */
3157	0x26018, /* GCC_CAMERA_HF_XO_CLK */
3158	0x2601c, /* GCC_CAMERA_SF_XO_CLK */
3159	0x27004, /* GCC_DISP_AHB_CLK */
3160	0x27018, /* GCC_DISP_XO_CLK */
3161	0x71004, /* GCC_GPU_CFG_AHB_CLK */
3162	0x32004, /* GCC_VIDEO_AHB_CLK */
3163	0x32024, /* GCC_VIDEO_XO_CLK */
3164};
3165
3166static const struct regmap_config gcc_milos_regmap_config = {
3167	.reg_bits = 32,
3168	.reg_stride = 4,
3169	.val_bits = 32,
3170	.max_register = 0x1f41f0,
3171	.fast_io = true,
3172};
3173
3174static struct qcom_cc_driver_data gcc_milos_driver_data = {
3175	.clk_cbcrs = gcc_milos_critical_cbcrs,
3176	.num_clk_cbcrs = ARRAY_SIZE(gcc_milos_critical_cbcrs),
3177	.dfs_rcgs = gcc_milos_dfs_clocks,
3178	.num_dfs_rcgs = ARRAY_SIZE(gcc_milos_dfs_clocks),
3179};
3180
3181static const struct qcom_cc_desc gcc_milos_desc = {
3182	.config = &gcc_milos_regmap_config,
3183	.clks = gcc_milos_clocks,
3184	.num_clks = ARRAY_SIZE(gcc_milos_clocks),
3185	.resets = gcc_milos_resets,
3186	.num_resets = ARRAY_SIZE(gcc_milos_resets),
3187	.gdscs = gcc_milos_gdscs,
3188	.num_gdscs = ARRAY_SIZE(gcc_milos_gdscs),
3189	.use_rpm = true,
3190	.driver_data = &gcc_milos_driver_data,
3191};
3192
3193static const struct of_device_id gcc_milos_match_table[] = {
3194	{ .compatible = "qcom,milos-gcc" },
3195	{ }
3196};
3197MODULE_DEVICE_TABLE(of, gcc_milos_match_table);
3198
3199static int gcc_milos_probe(struct platform_device *pdev)
3200{
3201	return qcom_cc_probe(pdev, &gcc_milos_desc);
3202}
3203
3204static struct platform_driver gcc_milos_driver = {
3205	.probe = gcc_milos_probe,
3206	.driver = {
3207		.name = "gcc-milos",
3208		.of_match_table = gcc_milos_match_table,
3209	},
3210};
3211
3212static int __init gcc_milos_init(void)
3213{
3214	return platform_driver_register(&gcc_milos_driver);
3215}
3216subsys_initcall(gcc_milos_init);
3217
3218static void __exit gcc_milos_exit(void)
3219{
3220	platform_driver_unregister(&gcc_milos_driver);
3221}
3222module_exit(gcc_milos_exit);
3223
3224MODULE_DESCRIPTION("QTI GCC Milos Driver");
3225MODULE_LICENSE("GPL");