gcc-ipq6018.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/kernel.h>
   7#include <linux/err.h>
   8#include <linux/platform_device.h>
   9#include <linux/module.h>
  10#include <linux/of.h>
  11#include <linux/clk-provider.h>
  12#include <linux/regmap.h>
  13
  14#include <linux/reset-controller.h>
  15#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
  16#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
  17
  18#include "common.h"
  19#include "clk-regmap.h"
  20#include "clk-pll.h"
  21#include "clk-rcg.h"
  22#include "clk-branch.h"
  23#include "clk-alpha-pll.h"
  24#include "clk-regmap-divider.h"
  25#include "clk-regmap-mux.h"
  26#include "reset.h"
  27
  28enum {
  29	P_XO,
  30	P_BIAS_PLL,
  31	P_UNIPHY0_RX,
  32	P_UNIPHY0_TX,
  33	P_UNIPHY1_RX,
  34	P_BIAS_PLL_NSS_NOC,
  35	P_UNIPHY1_TX,
  36	P_PCIE20_PHY0_PIPE,
  37	P_USB3PHY_0_PIPE,
  38	P_GPLL0,
  39	P_GPLL0_DIV2,
  40	P_GPLL2,
  41	P_GPLL4,
  42	P_GPLL6,
  43	P_SLEEP_CLK,
  44	P_UBI32_PLL,
  45	P_NSS_CRYPTO_PLL,
  46	P_PI_SLEEP,
  47};
  48
  49static struct clk_alpha_pll gpll0_main = {
  50	.offset = 0x21000,
  51	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  52	.clkr = {
  53		.enable_reg = 0x0b000,
  54		.enable_mask = BIT(0),
  55		.hw.init = &(struct clk_init_data){
  56			.name = "gpll0_main",
  57			.parent_data = &(const struct clk_parent_data){
  58				.fw_name = "xo",
  59			},
  60			.num_parents = 1,
  61			.ops = &clk_alpha_pll_ops,
  62		},
  63	},
  64};
  65
  66static struct clk_fixed_factor gpll0_out_main_div2 = {
  67	.mult = 1,
  68	.div = 2,
  69	.hw.init = &(struct clk_init_data){
  70		.name = "gpll0_out_main_div2",
  71		.parent_hws = (const struct clk_hw *[]){
  72				&gpll0_main.clkr.hw },
  73		.num_parents = 1,
  74		.ops = &clk_fixed_factor_ops,
  75	},
  76};
  77
  78static struct clk_alpha_pll_postdiv gpll0 = {
  79	.offset = 0x21000,
  80	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  81	.width = 4,
  82	.clkr.hw.init = &(struct clk_init_data){
  83		.name = "gpll0",
  84		.parent_hws = (const struct clk_hw *[]){
  85				&gpll0_main.clkr.hw },
  86		.num_parents = 1,
  87		.ops = &clk_alpha_pll_postdiv_ro_ops,
  88	},
  89};
  90
  91static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
  92	{ .fw_name = "xo" },
  93	{ .hw = &gpll0.clkr.hw},
  94	{ .hw = &gpll0_out_main_div2.hw},
  95};
  96
  97static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
  98	{ P_XO, 0 },
  99	{ P_GPLL0, 1 },
 100	{ P_GPLL0_DIV2, 4 },
 101};
 102
 103static struct clk_alpha_pll ubi32_pll_main = {
 104	.offset = 0x25000,
 105	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 106	.flags = SUPPORTS_DYNAMIC_UPDATE,
 107	.clkr = {
 108		.enable_reg = 0x0b000,
 109		.enable_mask = BIT(6),
 110		.hw.init = &(struct clk_init_data){
 111			.name = "ubi32_pll_main",
 112			.parent_data = &(const struct clk_parent_data){
 113				.fw_name = "xo",
 114			},
 115			.num_parents = 1,
 116			.ops = &clk_alpha_pll_huayra_ops,
 117		},
 118	},
 119};
 120
 121static struct clk_alpha_pll_postdiv ubi32_pll = {
 122	.offset = 0x25000,
 123	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 124	.width = 2,
 125	.clkr.hw.init = &(struct clk_init_data){
 126		.name = "ubi32_pll",
 127		.parent_hws = (const struct clk_hw *[]){
 128				&ubi32_pll_main.clkr.hw },
 129		.num_parents = 1,
 130		.ops = &clk_alpha_pll_postdiv_ro_ops,
 131		.flags = CLK_SET_RATE_PARENT,
 132	},
 133};
 134
 135static struct clk_alpha_pll gpll6_main = {
 136	.offset = 0x37000,
 137	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 138	.clkr = {
 139		.enable_reg = 0x0b000,
 140		.enable_mask = BIT(7),
 141		.hw.init = &(struct clk_init_data){
 142			.name = "gpll6_main",
 143			.parent_data = &(const struct clk_parent_data){
 144				.fw_name = "xo",
 145			},
 146			.num_parents = 1,
 147			.ops = &clk_alpha_pll_ops,
 148		},
 149	},
 150};
 151
 152static struct clk_alpha_pll_postdiv gpll6 = {
 153	.offset = 0x37000,
 154	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 155	.width = 2,
 156	.clkr.hw.init = &(struct clk_init_data){
 157		.name = "gpll6",
 158		.parent_hws = (const struct clk_hw *[]){
 159				&gpll6_main.clkr.hw },
 160		.num_parents = 1,
 161		.ops = &clk_alpha_pll_postdiv_ro_ops,
 162	},
 163};
 164
 165static struct clk_alpha_pll gpll4_main = {
 166	.offset = 0x24000,
 167	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 168	.clkr = {
 169		.enable_reg = 0x0b000,
 170		.enable_mask = BIT(5),
 171		.hw.init = &(struct clk_init_data){
 172			.name = "gpll4_main",
 173			.parent_data = &(const struct clk_parent_data){
 174				.fw_name = "xo",
 175			},
 176			.num_parents = 1,
 177			.ops = &clk_alpha_pll_ops,
 178		},
 179	},
 180};
 181
 182static struct clk_alpha_pll_postdiv gpll4 = {
 183	.offset = 0x24000,
 184	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 185	.width = 4,
 186	.clkr.hw.init = &(struct clk_init_data){
 187		.name = "gpll4",
 188		.parent_hws = (const struct clk_hw *[]){
 189				&gpll4_main.clkr.hw },
 190		.num_parents = 1,
 191		.ops = &clk_alpha_pll_postdiv_ro_ops,
 192	},
 193};
 194
 195static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 196	F(24000000, P_XO, 1, 0, 0),
 197	F(50000000, P_GPLL0, 16, 0, 0),
 198	F(100000000, P_GPLL0, 8, 0, 0),
 199	{ }
 200};
 201
 202static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 203	.cmd_rcgr = 0x27000,
 204	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 205	.hid_width = 5,
 206	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 207	.clkr.hw.init = &(struct clk_init_data){
 208		.name = "pcnoc_bfdcd_clk_src",
 209		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 210		.num_parents = 3,
 211		.ops = &clk_rcg2_ops,
 212	},
 213};
 214
 215static struct clk_alpha_pll gpll2_main = {
 216	.offset = 0x4a000,
 217	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 218	.clkr = {
 219		.enable_reg = 0x0b000,
 220		.enable_mask = BIT(2),
 221		.hw.init = &(struct clk_init_data){
 222			.name = "gpll2_main",
 223			.parent_data = &(const struct clk_parent_data){
 224				.fw_name = "xo",
 225			},
 226			.num_parents = 1,
 227			.ops = &clk_alpha_pll_ops,
 228		},
 229	},
 230};
 231
 232static struct clk_alpha_pll_postdiv gpll2 = {
 233	.offset = 0x4a000,
 234	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 235	.width = 4,
 236	.clkr.hw.init = &(struct clk_init_data){
 237		.name = "gpll2",
 238		.parent_hws = (const struct clk_hw *[]){
 239				&gpll2_main.clkr.hw },
 240		.num_parents = 1,
 241		.ops = &clk_alpha_pll_postdiv_ro_ops,
 242	},
 243};
 244
 245static struct clk_alpha_pll nss_crypto_pll_main = {
 246	.offset = 0x22000,
 247	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 248	.clkr = {
 249		.enable_reg = 0x0b000,
 250		.enable_mask = BIT(4),
 251		.hw.init = &(struct clk_init_data){
 252			.name = "nss_crypto_pll_main",
 253			.parent_data = &(const struct clk_parent_data){
 254				.fw_name = "xo",
 255			},
 256			.num_parents = 1,
 257			.ops = &clk_alpha_pll_ops,
 258		},
 259	},
 260};
 261
 262static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 263	.offset = 0x22000,
 264	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 265	.width = 4,
 266	.clkr.hw.init = &(struct clk_init_data){
 267		.name = "nss_crypto_pll",
 268		.parent_hws = (const struct clk_hw *[]){
 269				&nss_crypto_pll_main.clkr.hw },
 270		.num_parents = 1,
 271		.ops = &clk_alpha_pll_postdiv_ro_ops,
 272	},
 273};
 274
 275static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
 276	F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
 277	F(320000000, P_GPLL0, 2.5, 0, 0),
 278	F(600000000, P_GPLL4, 2, 0, 0),
 279	{ }
 280};
 281
 282static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll6_gpll0_div2[] = {
 283	{ .fw_name = "xo" },
 284	{ .hw = &gpll4.clkr.hw },
 285	{ .hw = &gpll0.clkr.hw },
 286	{ .hw = &gpll6.clkr.hw },
 287	{ .hw = &gpll0_out_main_div2.hw },
 288};
 289
 290static const struct parent_map gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map[] = {
 291	{ P_XO, 0 },
 292	{ P_GPLL4, 1 },
 293	{ P_GPLL0, 2 },
 294	{ P_GPLL6, 3 },
 295	{ P_GPLL0_DIV2, 4 },
 296};
 297
 298static struct clk_rcg2 qdss_tsctr_clk_src = {
 299	.cmd_rcgr = 0x29064,
 300	.freq_tbl = ftbl_qdss_tsctr_clk_src,
 301	.hid_width = 5,
 302	.parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
 303	.clkr.hw.init = &(struct clk_init_data){
 304		.name = "qdss_tsctr_clk_src",
 305		.parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
 306		.num_parents = 5,
 307		.ops = &clk_rcg2_ops,
 308	},
 309};
 310
 311static struct clk_fixed_factor qdss_dap_sync_clk_src = {
 312	.mult = 1,
 313	.div = 4,
 314	.hw.init = &(struct clk_init_data){
 315		.name = "qdss_dap_sync_clk_src",
 316		.parent_hws = (const struct clk_hw *[]){
 317				&qdss_tsctr_clk_src.clkr.hw },
 318		.num_parents = 1,
 319		.ops = &clk_fixed_factor_ops,
 320	},
 321};
 322
 323static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
 324	F(66670000, P_GPLL0_DIV2, 6, 0, 0),
 325	F(240000000, P_GPLL4, 5, 0, 0),
 326	{ }
 327};
 328
 329static struct clk_rcg2 qdss_at_clk_src = {
 330	.cmd_rcgr = 0x2900c,
 331	.freq_tbl = ftbl_qdss_at_clk_src,
 332	.hid_width = 5,
 333	.parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
 334	.clkr.hw.init = &(struct clk_init_data){
 335		.name = "qdss_at_clk_src",
 336		.parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
 337		.num_parents = 5,
 338		.ops = &clk_rcg2_ops,
 339	},
 340};
 341
 342static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
 343	.mult = 1,
 344	.div = 2,
 345	.hw.init = &(struct clk_init_data){
 346		.name = "qdss_tsctr_div2_clk_src",
 347		.parent_hws = (const struct clk_hw *[]){
 348				&qdss_tsctr_clk_src.clkr.hw },
 349		.num_parents = 1,
 350		.flags = CLK_SET_RATE_PARENT,
 351		.ops = &clk_fixed_factor_ops,
 352	},
 353};
 354
 355static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
 356	F(24000000, P_XO, 1, 0, 0),
 357	F(300000000, P_BIAS_PLL, 1, 0, 0),
 358	{ }
 359};
 360
 361static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
 362	{ .fw_name = "xo" },
 363	{ .fw_name = "bias_pll_cc_clk" },
 364	{ .hw = &gpll0.clkr.hw },
 365	{ .hw = &gpll4.clkr.hw },
 366	{ .hw = &nss_crypto_pll.clkr.hw },
 367	{ .hw = &ubi32_pll.clkr.hw },
 368};
 369
 370static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
 371	{ P_XO, 0 },
 372	{ P_BIAS_PLL, 1 },
 373	{ P_GPLL0, 2 },
 374	{ P_GPLL4, 3 },
 375	{ P_NSS_CRYPTO_PLL, 4 },
 376	{ P_UBI32_PLL, 5 },
 377};
 378
 379static struct clk_rcg2 nss_ppe_clk_src = {
 380	.cmd_rcgr = 0x68080,
 381	.freq_tbl = ftbl_nss_ppe_clk_src,
 382	.hid_width = 5,
 383	.parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
 384	.clkr.hw.init = &(struct clk_init_data){
 385		.name = "nss_ppe_clk_src",
 386		.parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
 387		.num_parents = 6,
 388		.ops = &clk_rcg2_ops,
 389	},
 390};
 391
 392static struct clk_branch gcc_xo_clk_src = {
 393	.halt_reg = 0x30018,
 394	.clkr = {
 395		.enable_reg = 0x30018,
 396		.enable_mask = BIT(1),
 397		.hw.init = &(struct clk_init_data){
 398			.name = "gcc_xo_clk_src",
 399			.parent_data = &(const struct clk_parent_data){
 400				.fw_name = "xo",
 401			},
 402			.num_parents = 1,
 403			.flags = CLK_SET_RATE_PARENT,
 404			.ops = &clk_branch2_ops,
 405		},
 406	},
 407};
 408
 409static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
 410	F(24000000, P_XO, 1, 0, 0),
 411	F(200000000, P_GPLL0, 4, 0, 0),
 412	{ }
 413};
 414
 415static const struct clk_parent_data gcc_xo_gpll0[] = {
 416	{ .fw_name = "xo" },
 417	{ .hw = &gpll0.clkr.hw },
 418};
 419
 420static const struct parent_map gcc_xo_gpll0_map[] = {
 421	{ P_XO, 0 },
 422	{ P_GPLL0, 1 },
 423};
 424
 425static struct clk_rcg2 nss_ce_clk_src = {
 426	.cmd_rcgr = 0x68098,
 427	.freq_tbl = ftbl_nss_ce_clk_src,
 428	.hid_width = 5,
 429	.parent_map = gcc_xo_gpll0_map,
 430	.clkr.hw.init = &(struct clk_init_data){
 431		.name = "nss_ce_clk_src",
 432		.parent_data = gcc_xo_gpll0,
 433		.num_parents = 2,
 434		.ops = &clk_rcg2_ops,
 435	},
 436};
 437
 438static struct clk_branch gcc_sleep_clk_src = {
 439	.halt_reg = 0x30000,
 440	.clkr = {
 441		.enable_reg = 0x30000,
 442		.enable_mask = BIT(1),
 443		.hw.init = &(struct clk_init_data){
 444			.name = "gcc_sleep_clk_src",
 445			.parent_data = &(const struct clk_parent_data){
 446				.fw_name = "sleep_clk",
 447			},
 448			.num_parents = 1,
 449			.ops = &clk_branch2_ops,
 450		},
 451	},
 452};
 453
 454static const struct freq_tbl ftbl_snoc_nssnoc_bfdcd_clk_src[] = {
 455	F(24000000, P_XO, 1, 0, 0),
 456	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
 457	F(100000000, P_GPLL0, 8, 0, 0),
 458	F(133333333, P_GPLL0, 6, 0, 0),
 459	F(160000000, P_GPLL0, 5, 0, 0),
 460	F(200000000, P_GPLL0, 4, 0, 0),
 461	F(266666667, P_GPLL0, 3, 0, 0),
 462	{ }
 463};
 464
 465static const struct clk_parent_data
 466			gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
 467	{ .fw_name = "xo" },
 468	{ .hw = &gpll0.clkr.hw },
 469	{ .hw = &gpll6.clkr.hw },
 470	{ .hw = &gpll0_out_main_div2.hw },
 471};
 472
 473static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
 474	{ P_XO, 0 },
 475	{ P_GPLL0, 1 },
 476	{ P_GPLL6, 2 },
 477	{ P_GPLL0_DIV2, 3 },
 478};
 479
 480static struct clk_rcg2 snoc_nssnoc_bfdcd_clk_src = {
 481	.cmd_rcgr = 0x76054,
 482	.freq_tbl = ftbl_snoc_nssnoc_bfdcd_clk_src,
 483	.hid_width = 5,
 484	.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
 485	.clkr.hw.init = &(struct clk_init_data){
 486		.name = "snoc_nssnoc_bfdcd_clk_src",
 487		.parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
 488		.num_parents = 4,
 489		.ops = &clk_rcg2_ops,
 490	},
 491};
 492
 493static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
 494	F(24000000, P_XO, 1, 0, 0),
 495	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 496	F(50000000, P_GPLL0, 16, 0, 0),
 497	F(100000000, P_GPLL0, 8, 0, 0),
 498	{ }
 499};
 500
 501static struct clk_rcg2 apss_ahb_clk_src = {
 502	.cmd_rcgr = 0x46000,
 503	.freq_tbl = ftbl_apss_ahb_clk_src,
 504	.hid_width = 5,
 505	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 506	.clkr.hw.init = &(struct clk_init_data){
 507		.name = "apss_ahb_clk_src",
 508		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 509		.num_parents = 3,
 510		.ops = &clk_rcg2_ops,
 511	},
 512};
 513
 514static const struct freq_conf ftbl_nss_port5_rx_clk_src_25[] = {
 515	C(P_UNIPHY1_RX, 12.5, 0, 0),
 516	C(P_UNIPHY0_RX, 5, 0, 0),
 517};
 518
 519static const struct freq_conf ftbl_nss_port5_rx_clk_src_125[] = {
 520	C(P_UNIPHY1_RX, 2.5, 0, 0),
 521	C(P_UNIPHY0_RX, 1, 0, 0),
 522};
 523
 524static const struct freq_multi_tbl ftbl_nss_port5_rx_clk_src[] = {
 525	FMS(24000000, P_XO, 1, 0, 0),
 526	FM(25000000, ftbl_nss_port5_rx_clk_src_25),
 527	FMS(78125000, P_UNIPHY1_RX, 4, 0, 0),
 528	FM(125000000, ftbl_nss_port5_rx_clk_src_125),
 529	FMS(156250000, P_UNIPHY1_RX, 2, 0, 0),
 530	FMS(312500000, P_UNIPHY1_RX, 1, 0, 0),
 531	{ }
 532};
 533
 534static const struct clk_parent_data
 535gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
 536	{ .fw_name = "xo" },
 537	{ .fw_name = "uniphy0_gcc_rx_clk" },
 538	{ .fw_name = "uniphy0_gcc_tx_clk" },
 539	{ .fw_name = "uniphy1_gcc_rx_clk" },
 540	{ .fw_name = "uniphy1_gcc_tx_clk" },
 541	{ .hw = &ubi32_pll.clkr.hw },
 542	{ .fw_name = "bias_pll_cc_clk" },
 543};
 544
 545static const struct parent_map
 546gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
 547	{ P_XO, 0 },
 548	{ P_UNIPHY0_RX, 1 },
 549	{ P_UNIPHY0_TX, 2 },
 550	{ P_UNIPHY1_RX, 3 },
 551	{ P_UNIPHY1_TX, 4 },
 552	{ P_UBI32_PLL, 5 },
 553	{ P_BIAS_PLL, 6 },
 554};
 555
 556static struct clk_rcg2 nss_port5_rx_clk_src = {
 557	.cmd_rcgr = 0x68060,
 558	.freq_multi_tbl = ftbl_nss_port5_rx_clk_src,
 559	.hid_width = 5,
 560	.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
 561	.clkr.hw.init = &(struct clk_init_data){
 562		.name = "nss_port5_rx_clk_src",
 563		.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
 564		.num_parents = 7,
 565		.ops = &clk_rcg2_fm_ops,
 566	},
 567};
 568
 569static const struct freq_conf ftbl_nss_port5_tx_clk_src_25[] = {
 570	C(P_UNIPHY1_TX, 12.5, 0, 0),
 571	C(P_UNIPHY0_TX, 5, 0, 0),
 572};
 573
 574static const struct freq_conf ftbl_nss_port5_tx_clk_src_125[] = {
 575	C(P_UNIPHY1_TX, 2.5, 0, 0),
 576	C(P_UNIPHY0_TX, 1, 0, 0),
 577};
 578
 579static const struct freq_multi_tbl ftbl_nss_port5_tx_clk_src[] = {
 580	FMS(24000000, P_XO, 1, 0, 0),
 581	FM(25000000, ftbl_nss_port5_tx_clk_src_25),
 582	FMS(78125000, P_UNIPHY1_TX, 4, 0, 0),
 583	FM(125000000, ftbl_nss_port5_tx_clk_src_125),
 584	FMS(156250000, P_UNIPHY1_TX, 2, 0, 0),
 585	FMS(312500000, P_UNIPHY1_TX, 1, 0, 0),
 586	{ }
 587};
 588
 589static const struct clk_parent_data
 590gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
 591	{ .fw_name = "xo" },
 592	{ .fw_name = "uniphy0_gcc_tx_clk" },
 593	{ .fw_name = "uniphy0_gcc_rx_clk" },
 594	{ .fw_name = "uniphy1_gcc_tx_clk" },
 595	{ .fw_name = "uniphy1_gcc_rx_clk" },
 596	{ .hw = &ubi32_pll.clkr.hw },
 597	{ .fw_name = "bias_pll_cc_clk" },
 598};
 599
 600static const struct parent_map
 601gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
 602	{ P_XO, 0 },
 603	{ P_UNIPHY0_TX, 1 },
 604	{ P_UNIPHY0_RX, 2 },
 605	{ P_UNIPHY1_TX, 3 },
 606	{ P_UNIPHY1_RX, 4 },
 607	{ P_UBI32_PLL, 5 },
 608	{ P_BIAS_PLL, 6 },
 609};
 610
 611static struct clk_rcg2 nss_port5_tx_clk_src = {
 612	.cmd_rcgr = 0x68068,
 613	.freq_multi_tbl = ftbl_nss_port5_tx_clk_src,
 614	.hid_width = 5,
 615	.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
 616	.clkr.hw.init = &(struct clk_init_data){
 617		.name = "nss_port5_tx_clk_src",
 618		.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
 619		.num_parents = 7,
 620		.ops = &clk_rcg2_fm_ops,
 621	},
 622};
 623
 624static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
 625	F(24000000, P_XO, 1, 0, 0),
 626	F(200000000, P_GPLL0, 4, 0, 0),
 627	F(240000000, P_GPLL4, 5, 0, 0),
 628	{ }
 629};
 630
 631static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
 632	F(24000000, P_XO, 1, 0, 0),
 633	F(100000000, P_GPLL0, 8, 0, 0),
 634	{ }
 635};
 636
 637static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
 638	{ .fw_name = "xo" },
 639	{ .hw = &gpll0.clkr.hw },
 640	{ .hw = &gpll4.clkr.hw },
 641};
 642
 643static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 644	{ P_XO, 0 },
 645	{ P_GPLL0, 1 },
 646	{ P_GPLL4, 2 },
 647};
 648
 649static struct clk_rcg2 pcie0_axi_clk_src = {
 650	.cmd_rcgr = 0x75054,
 651	.freq_tbl = ftbl_pcie_axi_clk_src,
 652	.hid_width = 5,
 653	.parent_map = gcc_xo_gpll0_gpll4_map,
 654	.clkr.hw.init = &(struct clk_init_data){
 655		.name = "pcie0_axi_clk_src",
 656		.parent_data = gcc_xo_gpll0_gpll4,
 657		.num_parents = 3,
 658		.ops = &clk_rcg2_ops,
 659	},
 660};
 661
 662static const struct freq_tbl ftbl_usb0_master_clk_src[] = {
 663	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
 664	F(100000000, P_GPLL0, 8, 0, 0),
 665	F(133330000, P_GPLL0, 6, 0, 0),
 666	F(200000000, P_GPLL0, 4, 0, 0),
 667	{ }
 668};
 669
 670static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
 671	{ .fw_name = "xo" },
 672	{ .hw = &gpll0_out_main_div2.hw },
 673	{ .hw = &gpll0.clkr.hw },
 674};
 675
 676static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 677	{ P_XO, 0 },
 678	{ P_GPLL0_DIV2, 2 },
 679	{ P_GPLL0, 1 },
 680};
 681
 682static struct clk_rcg2 usb0_master_clk_src = {
 683	.cmd_rcgr = 0x3e00c,
 684	.freq_tbl = ftbl_usb0_master_clk_src,
 685	.mnd_width = 8,
 686	.hid_width = 5,
 687	.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
 688	.clkr.hw.init = &(struct clk_init_data){
 689		.name = "usb0_master_clk_src",
 690		.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
 691		.num_parents = 3,
 692		.ops = &clk_rcg2_ops,
 693	},
 694};
 695
 696static struct clk_regmap_div apss_ahb_postdiv_clk_src = {
 697	.reg = 0x46018,
 698	.shift = 4,
 699	.width = 4,
 700	.clkr = {
 701		.hw.init = &(struct clk_init_data){
 702			.name = "apss_ahb_postdiv_clk_src",
 703			.parent_hws = (const struct clk_hw *[]){
 704					&apss_ahb_clk_src.clkr.hw },
 705			.num_parents = 1,
 706			.ops = &clk_regmap_div_ops,
 707		},
 708	},
 709};
 710
 711static struct clk_fixed_factor gcc_xo_div4_clk_src = {
 712	.mult = 1,
 713	.div = 4,
 714	.hw.init = &(struct clk_init_data){
 715		.name = "gcc_xo_div4_clk_src",
 716		.parent_hws = (const struct clk_hw *[]){
 717				&gcc_xo_clk_src.clkr.hw },
 718		.num_parents = 1,
 719		.ops = &clk_fixed_factor_ops,
 720		.flags = CLK_SET_RATE_PARENT,
 721	},
 722};
 723
 724static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
 725	F(24000000, P_XO, 1, 0, 0),
 726	F(25000000, P_UNIPHY0_RX, 5, 0, 0),
 727	F(125000000, P_UNIPHY0_RX, 1, 0, 0),
 728	{ }
 729};
 730
 731static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
 732	{ .fw_name = "xo" },
 733	{ .fw_name = "uniphy0_gcc_rx_clk" },
 734	{ .fw_name = "uniphy0_gcc_tx_clk" },
 735	{ .hw = &ubi32_pll.clkr.hw },
 736	{ .fw_name = "bias_pll_cc_clk" },
 737};
 738
 739static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
 740	{ P_XO, 0 },
 741	{ P_UNIPHY0_RX, 1 },
 742	{ P_UNIPHY0_TX, 2 },
 743	{ P_UBI32_PLL, 5 },
 744	{ P_BIAS_PLL, 6 },
 745};
 746
 747static struct clk_rcg2 nss_port1_rx_clk_src = {
 748	.cmd_rcgr = 0x68020,
 749	.freq_tbl = ftbl_nss_port1_rx_clk_src,
 750	.hid_width = 5,
 751	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 752	.clkr.hw.init = &(struct clk_init_data){
 753		.name = "nss_port1_rx_clk_src",
 754		.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 755		.num_parents = 5,
 756		.ops = &clk_rcg2_ops,
 757	},
 758};
 759
 760static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
 761	F(24000000, P_XO, 1, 0, 0),
 762	F(25000000, P_UNIPHY0_TX, 5, 0, 0),
 763	F(125000000, P_UNIPHY0_TX, 1, 0, 0),
 764	{ }
 765};
 766
 767static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
 768	{ .fw_name = "xo" },
 769	{ .fw_name = "uniphy0_gcc_tx_clk" },
 770	{ .fw_name = "uniphy0_gcc_rx_clk" },
 771	{ .hw = &ubi32_pll.clkr.hw },
 772	{ .fw_name = "bias_pll_cc_clk" },
 773};
 774
 775static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
 776	{ P_XO, 0 },
 777	{ P_UNIPHY0_TX, 1 },
 778	{ P_UNIPHY0_RX, 2 },
 779	{ P_UBI32_PLL, 5 },
 780	{ P_BIAS_PLL, 6 },
 781};
 782
 783static struct clk_rcg2 nss_port1_tx_clk_src = {
 784	.cmd_rcgr = 0x68028,
 785	.freq_tbl = ftbl_nss_port1_tx_clk_src,
 786	.hid_width = 5,
 787	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 788	.clkr.hw.init = &(struct clk_init_data){
 789		.name = "nss_port1_tx_clk_src",
 790		.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 791		.num_parents = 5,
 792		.ops = &clk_rcg2_ops,
 793	},
 794};
 795
 796static struct clk_rcg2 nss_port2_rx_clk_src = {
 797	.cmd_rcgr = 0x68030,
 798	.freq_tbl = ftbl_nss_port1_rx_clk_src,
 799	.hid_width = 5,
 800	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 801	.clkr.hw.init = &(struct clk_init_data){
 802		.name = "nss_port2_rx_clk_src",
 803		.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 804		.num_parents = 5,
 805		.ops = &clk_rcg2_ops,
 806	},
 807};
 808
 809static struct clk_rcg2 nss_port2_tx_clk_src = {
 810	.cmd_rcgr = 0x68038,
 811	.freq_tbl = ftbl_nss_port1_tx_clk_src,
 812	.hid_width = 5,
 813	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 814	.clkr.hw.init = &(struct clk_init_data){
 815		.name = "nss_port2_tx_clk_src",
 816		.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 817		.num_parents = 5,
 818		.ops = &clk_rcg2_ops,
 819	},
 820};
 821
 822static struct clk_rcg2 nss_port3_rx_clk_src = {
 823	.cmd_rcgr = 0x68040,
 824	.freq_tbl = ftbl_nss_port1_rx_clk_src,
 825	.hid_width = 5,
 826	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 827	.clkr.hw.init = &(struct clk_init_data){
 828		.name = "nss_port3_rx_clk_src",
 829		.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 830		.num_parents = 5,
 831		.ops = &clk_rcg2_ops,
 832	},
 833};
 834
 835static struct clk_rcg2 nss_port3_tx_clk_src = {
 836	.cmd_rcgr = 0x68048,
 837	.freq_tbl = ftbl_nss_port1_tx_clk_src,
 838	.hid_width = 5,
 839	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 840	.clkr.hw.init = &(struct clk_init_data){
 841		.name = "nss_port3_tx_clk_src",
 842		.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 843		.num_parents = 5,
 844		.ops = &clk_rcg2_ops,
 845	},
 846};
 847
 848static struct clk_rcg2 nss_port4_rx_clk_src = {
 849	.cmd_rcgr = 0x68050,
 850	.freq_tbl = ftbl_nss_port1_rx_clk_src,
 851	.hid_width = 5,
 852	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
 853	.clkr.hw.init = &(struct clk_init_data){
 854		.name = "nss_port4_rx_clk_src",
 855		.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
 856		.num_parents = 5,
 857		.ops = &clk_rcg2_ops,
 858	},
 859};
 860
 861static struct clk_rcg2 nss_port4_tx_clk_src = {
 862	.cmd_rcgr = 0x68058,
 863	.freq_tbl = ftbl_nss_port1_tx_clk_src,
 864	.hid_width = 5,
 865	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
 866	.clkr.hw.init = &(struct clk_init_data){
 867		.name = "nss_port4_tx_clk_src",
 868		.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
 869		.num_parents = 5,
 870		.ops = &clk_rcg2_ops,
 871	},
 872};
 873
 874static struct clk_regmap_div nss_port5_rx_div_clk_src = {
 875	.reg = 0x68440,
 876	.shift = 0,
 877	.width = 4,
 878	.clkr = {
 879		.hw.init = &(struct clk_init_data){
 880			.name = "nss_port5_rx_div_clk_src",
 881			.parent_hws = (const struct clk_hw *[]){
 882					&nss_port5_rx_clk_src.clkr.hw },
 883			.num_parents = 1,
 884			.ops = &clk_regmap_div_ops,
 885			.flags = CLK_SET_RATE_PARENT,
 886		},
 887	},
 888};
 889
 890static struct clk_regmap_div nss_port5_tx_div_clk_src = {
 891	.reg = 0x68444,
 892	.shift = 0,
 893	.width = 4,
 894	.clkr = {
 895		.hw.init = &(struct clk_init_data){
 896			.name = "nss_port5_tx_div_clk_src",
 897			.parent_hws = (const struct clk_hw *[]){
 898					&nss_port5_tx_clk_src.clkr.hw },
 899			.num_parents = 1,
 900			.ops = &clk_regmap_div_ops,
 901			.flags = CLK_SET_RATE_PARENT,
 902		},
 903	},
 904};
 905
 906static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
 907	F(24000000, P_XO, 1, 0, 0),
 908	F(100000000, P_GPLL0_DIV2, 4, 0, 0),
 909	F(200000000, P_GPLL0, 4, 0, 0),
 910	F(308570000, P_GPLL6, 3.5, 0, 0),
 911	F(400000000, P_GPLL0, 2, 0, 0),
 912	F(533000000, P_GPLL0, 1.5, 0, 0),
 913	{ }
 914};
 915
 916static const struct clk_parent_data gcc_xo_gpll0_gpll6_ubi32_gpll0_div2[] = {
 917	{ .fw_name = "xo" },
 918	{ .hw = &gpll0.clkr.hw },
 919	{ .hw = &gpll6.clkr.hw },
 920	{ .hw = &ubi32_pll.clkr.hw },
 921	{ .hw = &gpll0_out_main_div2.hw },
 922};
 923
 924static const struct parent_map
 925gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map[] = {
 926	{ P_XO, 0 },
 927	{ P_GPLL0, 1 },
 928	{ P_GPLL6, 2 },
 929	{ P_UBI32_PLL, 3 },
 930	{ P_GPLL0_DIV2, 6 },
 931};
 932
 933static struct clk_rcg2 apss_axi_clk_src = {
 934	.cmd_rcgr = 0x38048,
 935	.freq_tbl = ftbl_apss_axi_clk_src,
 936	.hid_width = 5,
 937	.parent_map = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map,
 938	.clkr.hw.init = &(struct clk_init_data){
 939		.name = "apss_axi_clk_src",
 940		.parent_data = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2,
 941		.num_parents = 5,
 942		.ops = &clk_rcg2_ops,
 943	},
 944};
 945
 946static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
 947	F(24000000, P_XO, 1, 0, 0),
 948	F(300000000, P_NSS_CRYPTO_PLL, 2, 0, 0),
 949	{ }
 950};
 951
 952static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
 953	{ .fw_name = "xo" },
 954	{ .hw = &nss_crypto_pll.clkr.hw },
 955	{ .hw = &gpll0.clkr.hw },
 956};
 957
 958static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
 959	{ P_XO, 0 },
 960	{ P_NSS_CRYPTO_PLL, 1 },
 961	{ P_GPLL0, 2 },
 962};
 963
 964static struct clk_rcg2 nss_crypto_clk_src = {
 965	.cmd_rcgr = 0x68144,
 966	.freq_tbl = ftbl_nss_crypto_clk_src,
 967	.mnd_width = 16,
 968	.hid_width = 5,
 969	.parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
 970	.clkr.hw.init = &(struct clk_init_data){
 971		.name = "nss_crypto_clk_src",
 972		.parent_data = gcc_xo_nss_crypto_pll_gpll0,
 973		.num_parents = 3,
 974		.ops = &clk_rcg2_ops,
 975	},
 976};
 977
 978static struct clk_regmap_div nss_port1_rx_div_clk_src = {
 979	.reg = 0x68400,
 980	.shift = 0,
 981	.width = 4,
 982	.clkr = {
 983		.hw.init = &(struct clk_init_data){
 984			.name = "nss_port1_rx_div_clk_src",
 985			.parent_hws = (const struct clk_hw *[]){
 986				&nss_port1_rx_clk_src.clkr.hw },
 987			.num_parents = 1,
 988			.ops = &clk_regmap_div_ops,
 989			.flags = CLK_SET_RATE_PARENT,
 990		},
 991	},
 992};
 993
 994static struct clk_regmap_div nss_port1_tx_div_clk_src = {
 995	.reg = 0x68404,
 996	.shift = 0,
 997	.width = 4,
 998	.clkr = {
 999		.hw.init = &(struct clk_init_data){
1000			.name = "nss_port1_tx_div_clk_src",
1001			.parent_hws = (const struct clk_hw *[]){
1002					&nss_port1_tx_clk_src.clkr.hw },
1003			.num_parents = 1,
1004			.ops = &clk_regmap_div_ops,
1005			.flags = CLK_SET_RATE_PARENT,
1006		},
1007	},
1008};
1009
1010static struct clk_regmap_div nss_port2_rx_div_clk_src = {
1011	.reg = 0x68410,
1012	.shift = 0,
1013	.width = 4,
1014	.clkr = {
1015		.hw.init = &(struct clk_init_data){
1016			.name = "nss_port2_rx_div_clk_src",
1017			.parent_hws = (const struct clk_hw *[]){
1018					&nss_port2_rx_clk_src.clkr.hw },
1019			.num_parents = 1,
1020			.ops = &clk_regmap_div_ops,
1021			.flags = CLK_SET_RATE_PARENT,
1022		},
1023	},
1024};
1025
1026static struct clk_regmap_div nss_port2_tx_div_clk_src = {
1027	.reg = 0x68414,
1028	.shift = 0,
1029	.width = 4,
1030	.clkr = {
1031		.hw.init = &(struct clk_init_data){
1032			.name = "nss_port2_tx_div_clk_src",
1033			.parent_hws = (const struct clk_hw *[]){
1034					&nss_port2_tx_clk_src.clkr.hw },
1035			.num_parents = 1,
1036			.ops = &clk_regmap_div_ops,
1037			.flags = CLK_SET_RATE_PARENT,
1038		},
1039	},
1040};
1041
1042static struct clk_regmap_div nss_port3_rx_div_clk_src = {
1043	.reg = 0x68420,
1044	.shift = 0,
1045	.width = 4,
1046	.clkr = {
1047		.hw.init = &(struct clk_init_data){
1048			.name = "nss_port3_rx_div_clk_src",
1049			.parent_hws = (const struct clk_hw *[]){
1050					&nss_port3_rx_clk_src.clkr.hw },
1051			.num_parents = 1,
1052			.ops = &clk_regmap_div_ops,
1053			.flags = CLK_SET_RATE_PARENT,
1054		},
1055	},
1056};
1057
1058static struct clk_regmap_div nss_port3_tx_div_clk_src = {
1059	.reg = 0x68424,
1060	.shift = 0,
1061	.width = 4,
1062	.clkr = {
1063		.hw.init = &(struct clk_init_data){
1064			.name = "nss_port3_tx_div_clk_src",
1065			.parent_hws = (const struct clk_hw *[]){
1066					&nss_port3_tx_clk_src.clkr.hw },
1067			.num_parents = 1,
1068			.ops = &clk_regmap_div_ops,
1069			.flags = CLK_SET_RATE_PARENT,
1070		},
1071	},
1072};
1073
1074static struct clk_regmap_div nss_port4_rx_div_clk_src = {
1075	.reg = 0x68430,
1076	.shift = 0,
1077	.width = 4,
1078	.clkr = {
1079		.hw.init = &(struct clk_init_data){
1080			.name = "nss_port4_rx_div_clk_src",
1081			.parent_hws = (const struct clk_hw *[]){
1082					&nss_port4_rx_clk_src.clkr.hw },
1083			.num_parents = 1,
1084			.ops = &clk_regmap_div_ops,
1085			.flags = CLK_SET_RATE_PARENT,
1086		},
1087	},
1088};
1089
1090static struct clk_regmap_div nss_port4_tx_div_clk_src = {
1091	.reg = 0x68434,
1092	.shift = 0,
1093	.width = 4,
1094	.clkr = {
1095		.hw.init = &(struct clk_init_data){
1096			.name = "nss_port4_tx_div_clk_src",
1097			.parent_hws = (const struct clk_hw *[]){
1098					&nss_port4_tx_clk_src.clkr.hw },
1099			.num_parents = 1,
1100			.ops = &clk_regmap_div_ops,
1101			.flags = CLK_SET_RATE_PARENT,
1102		},
1103	},
1104};
1105
1106static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1107	F(24000000, P_XO, 1, 0, 0),
1108	F(149760000, P_UBI32_PLL, 10, 0, 0),
1109	F(187200000, P_UBI32_PLL, 8, 0, 0),
1110	F(249600000, P_UBI32_PLL, 6, 0, 0),
1111	F(374400000, P_UBI32_PLL, 4, 0, 0),
1112	F(748800000, P_UBI32_PLL, 2, 0, 0),
1113	F(1497600000, P_UBI32_PLL, 1, 0, 0),
1114	{ }
1115};
1116
1117static const struct clk_parent_data
1118			gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
1119	{ .fw_name = "xo" },
1120	{ .hw = &ubi32_pll.clkr.hw },
1121	{ .hw = &gpll0.clkr.hw },
1122	{ .hw = &gpll2.clkr.hw },
1123	{ .hw = &gpll4.clkr.hw },
1124	{ .hw = &gpll6.clkr.hw },
1125};
1126
1127static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
1128	{ P_XO, 0 },
1129	{ P_UBI32_PLL, 1 },
1130	{ P_GPLL0, 2 },
1131	{ P_GPLL2, 3 },
1132	{ P_GPLL4, 4 },
1133	{ P_GPLL6, 5 },
1134};
1135
1136static struct clk_rcg2 nss_ubi0_clk_src = {
1137	.cmd_rcgr = 0x68104,
1138	.freq_tbl = ftbl_nss_ubi_clk_src,
1139	.hid_width = 5,
1140	.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1141	.clkr.hw.init = &(struct clk_init_data){
1142		.name = "nss_ubi0_clk_src",
1143		.parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1144		.num_parents = 6,
1145		.ops = &clk_rcg2_ops,
1146		.flags = CLK_SET_RATE_PARENT,
1147	},
1148};
1149
1150static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
1151	F(24000000, P_XO, 1, 0, 0),
1152	F(100000000, P_GPLL0, 8, 0, 0),
1153	{ }
1154};
1155
1156static struct clk_rcg2 adss_pwm_clk_src = {
1157	.cmd_rcgr = 0x1c008,
1158	.freq_tbl = ftbl_adss_pwm_clk_src,
1159	.hid_width = 5,
1160	.parent_map = gcc_xo_gpll0_map,
1161	.clkr.hw.init = &(struct clk_init_data){
1162		.name = "adss_pwm_clk_src",
1163		.parent_data = gcc_xo_gpll0,
1164		.num_parents = 2,
1165		.ops = &clk_rcg2_ops,
1166	},
1167};
1168
1169static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
1170	F(24000000, P_XO, 1, 0, 0),
1171	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1172	F(50000000, P_GPLL0, 16, 0, 0),
1173	{ }
1174};
1175
1176static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
1177	.cmd_rcgr = 0x0200c,
1178	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1179	.hid_width = 5,
1180	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1181	.clkr.hw.init = &(struct clk_init_data){
1182		.name = "blsp1_qup1_i2c_apps_clk_src",
1183		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1184		.num_parents = 3,
1185		.ops = &clk_rcg2_ops,
1186	},
1187};
1188
1189static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
1190	F(960000, P_XO, 10, 2, 5),
1191	F(4800000, P_XO, 5, 0, 0),
1192	F(9600000, P_XO, 2, 4, 5),
1193	F(12500000, P_GPLL0_DIV2, 16, 1, 2),
1194	F(16000000, P_GPLL0, 10, 1, 5),
1195	F(24000000, P_XO, 1, 0, 0),
1196	F(25000000, P_GPLL0, 16, 1, 2),
1197	F(50000000, P_GPLL0, 16, 0, 0),
1198	{ }
1199};
1200
1201static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
1202	.cmd_rcgr = 0x02024,
1203	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1204	.mnd_width = 8,
1205	.hid_width = 5,
1206	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1207	.clkr.hw.init = &(struct clk_init_data){
1208		.name = "blsp1_qup1_spi_apps_clk_src",
1209		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1210		.num_parents = 3,
1211		.ops = &clk_rcg2_ops,
1212	},
1213};
1214
1215static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
1216	.cmd_rcgr = 0x03000,
1217	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1218	.hid_width = 5,
1219	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1220	.clkr.hw.init = &(struct clk_init_data){
1221		.name = "blsp1_qup2_i2c_apps_clk_src",
1222		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1223		.num_parents = 3,
1224		.ops = &clk_rcg2_ops,
1225	},
1226};
1227
1228static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
1229	.cmd_rcgr = 0x03014,
1230	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1231	.mnd_width = 8,
1232	.hid_width = 5,
1233	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1234	.clkr.hw.init = &(struct clk_init_data){
1235		.name = "blsp1_qup2_spi_apps_clk_src",
1236		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1237		.num_parents = 3,
1238		.ops = &clk_rcg2_ops,
1239	},
1240};
1241
1242static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
1243	.cmd_rcgr = 0x04000,
1244	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1245	.hid_width = 5,
1246	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1247	.clkr.hw.init = &(struct clk_init_data){
1248		.name = "blsp1_qup3_i2c_apps_clk_src",
1249		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1250		.num_parents = 3,
1251		.ops = &clk_rcg2_ops,
1252	},
1253};
1254
1255static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
1256	.cmd_rcgr = 0x04014,
1257	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1258	.mnd_width = 8,
1259	.hid_width = 5,
1260	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1261	.clkr.hw.init = &(struct clk_init_data){
1262		.name = "blsp1_qup3_spi_apps_clk_src",
1263		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1264		.num_parents = 3,
1265		.ops = &clk_rcg2_ops,
1266	},
1267};
1268
1269static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
1270	.cmd_rcgr = 0x05000,
1271	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1272	.hid_width = 5,
1273	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1274	.clkr.hw.init = &(struct clk_init_data){
1275		.name = "blsp1_qup4_i2c_apps_clk_src",
1276		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1277		.num_parents = 3,
1278		.ops = &clk_rcg2_ops,
1279	},
1280};
1281
1282static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
1283	.cmd_rcgr = 0x05014,
1284	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1285	.mnd_width = 8,
1286	.hid_width = 5,
1287	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1288	.clkr.hw.init = &(struct clk_init_data){
1289		.name = "blsp1_qup4_spi_apps_clk_src",
1290		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1291		.num_parents = 3,
1292		.ops = &clk_rcg2_ops,
1293	},
1294};
1295
1296static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
1297	.cmd_rcgr = 0x06000,
1298	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1299	.hid_width = 5,
1300	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1301	.clkr.hw.init = &(struct clk_init_data){
1302		.name = "blsp1_qup5_i2c_apps_clk_src",
1303		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1304		.num_parents = 3,
1305		.ops = &clk_rcg2_ops,
1306	},
1307};
1308
1309static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
1310	.cmd_rcgr = 0x06014,
1311	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1312	.mnd_width = 8,
1313	.hid_width = 5,
1314	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1315	.clkr.hw.init = &(struct clk_init_data){
1316		.name = "blsp1_qup5_spi_apps_clk_src",
1317		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1318		.num_parents = 3,
1319		.ops = &clk_rcg2_ops,
1320	},
1321};
1322
1323static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
1324	.cmd_rcgr = 0x07000,
1325	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1326	.hid_width = 5,
1327	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1328	.clkr.hw.init = &(struct clk_init_data){
1329		.name = "blsp1_qup6_i2c_apps_clk_src",
1330		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1331		.num_parents = 3,
1332		.ops = &clk_rcg2_ops,
1333	},
1334};
1335
1336static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
1337	.cmd_rcgr = 0x07014,
1338	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1339	.mnd_width = 8,
1340	.hid_width = 5,
1341	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1342	.clkr.hw.init = &(struct clk_init_data){
1343		.name = "blsp1_qup6_spi_apps_clk_src",
1344		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1345		.num_parents = 3,
1346		.ops = &clk_rcg2_ops,
1347	},
1348};
1349
1350static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
1351	F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
1352	F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
1353	F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
1354	F(16000000, P_GPLL0_DIV2, 5, 1, 5),
1355	F(24000000, P_XO, 1, 0, 0),
1356	F(24000000, P_GPLL0, 1, 3, 100),
1357	F(25000000, P_GPLL0, 16, 1, 2),
1358	F(32000000, P_GPLL0, 1, 1, 25),
1359	F(40000000, P_GPLL0, 1, 1, 20),
1360	F(46400000, P_GPLL0, 1, 29, 500),
1361	F(48000000, P_GPLL0, 1, 3, 50),
1362	F(51200000, P_GPLL0, 1, 8, 125),
1363	F(56000000, P_GPLL0, 1, 7, 100),
1364	F(58982400, P_GPLL0, 1, 1152, 15625),
1365	F(60000000, P_GPLL0, 1, 3, 40),
1366	F(64000000, P_GPLL0, 12.5, 1, 1),
1367	{ }
1368};
1369
1370static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
1371	.cmd_rcgr = 0x02044,
1372	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1373	.mnd_width = 16,
1374	.hid_width = 5,
1375	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1376	.clkr.hw.init = &(struct clk_init_data){
1377		.name = "blsp1_uart1_apps_clk_src",
1378		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1379		.num_parents = 3,
1380		.ops = &clk_rcg2_ops,
1381	},
1382};
1383
1384static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
1385	.cmd_rcgr = 0x03034,
1386	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1387	.mnd_width = 16,
1388	.hid_width = 5,
1389	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1390	.clkr.hw.init = &(struct clk_init_data){
1391		.name = "blsp1_uart2_apps_clk_src",
1392		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1393		.num_parents = 3,
1394		.ops = &clk_rcg2_ops,
1395	},
1396};
1397
1398static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
1399	.cmd_rcgr = 0x04034,
1400	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1401	.mnd_width = 16,
1402	.hid_width = 5,
1403	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1404	.clkr.hw.init = &(struct clk_init_data){
1405		.name = "blsp1_uart3_apps_clk_src",
1406		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1407		.num_parents = 3,
1408		.ops = &clk_rcg2_ops,
1409	},
1410};
1411
1412static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
1413	.cmd_rcgr = 0x05034,
1414	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1415	.mnd_width = 16,
1416	.hid_width = 5,
1417	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1418	.clkr.hw.init = &(struct clk_init_data){
1419		.name = "blsp1_uart4_apps_clk_src",
1420		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1421		.num_parents = 3,
1422		.ops = &clk_rcg2_ops,
1423	},
1424};
1425
1426static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
1427	.cmd_rcgr = 0x06034,
1428	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1429	.mnd_width = 16,
1430	.hid_width = 5,
1431	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1432	.clkr.hw.init = &(struct clk_init_data){
1433		.name = "blsp1_uart5_apps_clk_src",
1434		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1435		.num_parents = 3,
1436		.ops = &clk_rcg2_ops,
1437	},
1438};
1439
1440static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
1441	.cmd_rcgr = 0x07034,
1442	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1443	.mnd_width = 16,
1444	.hid_width = 5,
1445	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1446	.clkr.hw.init = &(struct clk_init_data){
1447		.name = "blsp1_uart6_apps_clk_src",
1448		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1449		.num_parents = 3,
1450		.ops = &clk_rcg2_ops,
1451	},
1452};
1453
1454static const struct freq_tbl ftbl_crypto_clk_src[] = {
1455	F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1456	F(80000000, P_GPLL0, 10, 0, 0),
1457	F(100000000, P_GPLL0, 8, 0, 0),
1458	F(160000000, P_GPLL0, 5, 0, 0),
1459	{ }
1460};
1461
1462static struct clk_rcg2 crypto_clk_src = {
1463	.cmd_rcgr = 0x16004,
1464	.freq_tbl = ftbl_crypto_clk_src,
1465	.hid_width = 5,
1466	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1467	.clkr.hw.init = &(struct clk_init_data){
1468		.name = "crypto_clk_src",
1469		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1470		.num_parents = 3,
1471		.ops = &clk_rcg2_ops,
1472	},
1473};
1474
1475static const struct freq_tbl ftbl_gp_clk_src[] = {
1476	F(24000000, P_XO, 1, 0, 0),
1477	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1478	F(100000000, P_GPLL0, 8, 0, 0),
1479	F(200000000, P_GPLL0, 4, 0, 0),
1480	F(266666666, P_GPLL0, 3, 0, 0),
1481	{ }
1482};
1483
1484static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
1485	{ .fw_name = "xo" },
1486	{ .hw = &gpll0.clkr.hw },
1487	{ .hw = &gpll6.clkr.hw },
1488	{ .hw = &gpll0_out_main_div2.hw },
1489	{ .fw_name = "sleep_clk" },
1490};
1491
1492static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
1493	{ P_XO, 0 },
1494	{ P_GPLL0, 1 },
1495	{ P_GPLL6, 2 },
1496	{ P_GPLL0_DIV2, 4 },
1497	{ P_SLEEP_CLK, 6 },
1498};
1499
1500static struct clk_rcg2 gp1_clk_src = {
1501	.cmd_rcgr = 0x08004,
1502	.freq_tbl = ftbl_gp_clk_src,
1503	.mnd_width = 8,
1504	.hid_width = 5,
1505	.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1506	.clkr.hw.init = &(struct clk_init_data){
1507		.name = "gp1_clk_src",
1508		.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1509		.num_parents = 5,
1510		.ops = &clk_rcg2_ops,
1511	},
1512};
1513
1514static struct clk_rcg2 gp2_clk_src = {
1515	.cmd_rcgr = 0x09004,
1516	.freq_tbl = ftbl_gp_clk_src,
1517	.mnd_width = 8,
1518	.hid_width = 5,
1519	.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1520	.clkr.hw.init = &(struct clk_init_data){
1521		.name = "gp2_clk_src",
1522		.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1523		.num_parents = 5,
1524		.ops = &clk_rcg2_ops,
1525	},
1526};
1527
1528static struct clk_rcg2 gp3_clk_src = {
1529	.cmd_rcgr = 0x0a004,
1530	.freq_tbl = ftbl_gp_clk_src,
1531	.mnd_width = 8,
1532	.hid_width = 5,
1533	.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1534	.clkr.hw.init = &(struct clk_init_data){
1535		.name = "gp3_clk_src",
1536		.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1537		.num_parents = 5,
1538		.ops = &clk_rcg2_ops,
1539	},
1540};
1541
1542static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1543	.mult = 1,
1544	.div = 4,
1545	.hw.init = &(struct clk_init_data){
1546		.name = "nss_ppe_cdiv_clk_src",
1547		.parent_hws = (const struct clk_hw *[]){
1548				&nss_ppe_clk_src.clkr.hw },
1549		.num_parents = 1,
1550		.ops = &clk_fixed_factor_ops,
1551		.flags = CLK_SET_RATE_PARENT,
1552	},
1553};
1554
1555static struct clk_regmap_div nss_ubi0_div_clk_src = {
1556	.reg = 0x68118,
1557	.shift = 0,
1558	.width = 4,
1559	.clkr = {
1560		.hw.init = &(struct clk_init_data){
1561			.name = "nss_ubi0_div_clk_src",
1562			.parent_hws = (const struct clk_hw *[]){
1563				&nss_ubi0_clk_src.clkr.hw },
1564			.num_parents = 1,
1565			.ops = &clk_regmap_div_ro_ops,
1566			.flags = CLK_SET_RATE_PARENT,
1567		},
1568	},
1569};
1570
1571static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1572	F(24000000, P_XO, 1, 0, 0),
1573	{ }
1574};
1575
1576static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
1577	{ .fw_name = "xo" },
1578	{ .hw = &gpll0.clkr.hw },
1579	{ .fw_name = "sleep_clk" },
1580};
1581
1582static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
1583	{ P_XO, 0 },
1584	{ P_GPLL0, 2 },
1585	{ P_PI_SLEEP, 6 },
1586};
1587
1588static struct clk_rcg2 pcie0_aux_clk_src = {
1589	.cmd_rcgr = 0x75024,
1590	.freq_tbl = ftbl_pcie_aux_clk_src,
1591	.mnd_width = 16,
1592	.hid_width = 5,
1593	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1594	.clkr.hw.init = &(struct clk_init_data){
1595		.name = "pcie0_aux_clk_src",
1596		.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1597		.num_parents = 3,
1598		.ops = &clk_rcg2_ops,
1599	},
1600};
1601
1602static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
1603	{ .fw_name = "pcie20_phy0_pipe_clk" },
1604	{ .fw_name = "xo" },
1605};
1606
1607static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
1608	{ P_PCIE20_PHY0_PIPE, 0 },
1609	{ P_XO, 2 },
1610};
1611
1612static struct clk_regmap_mux pcie0_pipe_clk_src = {
1613	.reg = 0x7501c,
1614	.shift = 8,
1615	.width = 2,
1616	.parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
1617	.clkr = {
1618		.hw.init = &(struct clk_init_data){
1619			.name = "pcie0_pipe_clk_src",
1620			.parent_data = gcc_pcie20_phy0_pipe_clk_xo,
1621			.num_parents = 2,
1622			.ops = &clk_regmap_mux_closest_ops,
1623			.flags = CLK_SET_RATE_PARENT,
1624		},
1625	},
1626};
1627
1628static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
1629	F(144000, P_XO, 16, 12, 125),
1630	F(400000, P_XO, 12, 1, 5),
1631	F(24000000, P_GPLL2, 12, 1, 4),
1632	F(48000000, P_GPLL2, 12, 1, 2),
1633	F(96000000, P_GPLL2, 12, 0, 0),
1634	F(177777778, P_GPLL0, 4.5, 0, 0),
1635	F(192000000, P_GPLL2, 6, 0, 0),
1636	F(200000000, P_GPLL0, 4, 0, 0),
1637	{ }
1638};
1639
1640static const struct clk_parent_data
1641			gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
1642	{ .fw_name = "xo" },
1643	{ .hw = &gpll0.clkr.hw },
1644	{ .hw = &gpll2.clkr.hw },
1645	{ .hw = &gpll0_out_main_div2.hw },
1646};
1647
1648static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
1649	{ P_XO, 0 },
1650	{ P_GPLL0, 1 },
1651	{ P_GPLL2, 2 },
1652	{ P_GPLL0_DIV2, 4 },
1653};
1654
1655static struct clk_rcg2 sdcc1_apps_clk_src = {
1656	.cmd_rcgr = 0x42004,
1657	.freq_tbl = ftbl_sdcc_apps_clk_src,
1658	.mnd_width = 8,
1659	.hid_width = 5,
1660	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1661	.clkr.hw.init = &(struct clk_init_data){
1662		.name = "sdcc1_apps_clk_src",
1663		.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1664		.num_parents = 4,
1665		.ops = &clk_rcg2_floor_ops,
1666	},
1667};
1668
1669static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1670	F(24000000, P_XO, 1, 0, 0),
1671	{ }
1672};
1673
1674static struct clk_rcg2 usb0_aux_clk_src = {
1675	.cmd_rcgr = 0x3e05c,
1676	.freq_tbl = ftbl_usb_aux_clk_src,
1677	.mnd_width = 16,
1678	.hid_width = 5,
1679	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1680	.clkr.hw.init = &(struct clk_init_data){
1681		.name = "usb0_aux_clk_src",
1682		.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1683		.num_parents = 3,
1684		.ops = &clk_rcg2_ops,
1685	},
1686};
1687
1688static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
1689	F(24000000, P_XO, 1, 0, 0),
1690	F(60000000, P_GPLL6, 6, 1, 3),
1691	{ }
1692};
1693
1694static const struct clk_parent_data
1695			gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
1696	{ .fw_name = "xo" },
1697	{ .hw = &gpll6.clkr.hw },
1698	{ .hw = &gpll0.clkr.hw },
1699	{ .hw = &gpll0_out_main_div2.hw },
1700};
1701
1702static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
1703	{ P_XO, 0 },
1704	{ P_GPLL6, 1 },
1705	{ P_GPLL0, 3 },
1706	{ P_GPLL0_DIV2, 4 },
1707};
1708
1709static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1710	.cmd_rcgr = 0x3e020,
1711	.freq_tbl = ftbl_usb_mock_utmi_clk_src,
1712	.mnd_width = 8,
1713	.hid_width = 5,
1714	.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1715	.clkr.hw.init = &(struct clk_init_data){
1716		.name = "usb0_mock_utmi_clk_src",
1717		.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1718		.num_parents = 4,
1719		.ops = &clk_rcg2_ops,
1720	},
1721};
1722
1723static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
1724	{ .fw_name = "usb3phy_0_cc_pipe_clk" },
1725	{ .fw_name = "xo" },
1726};
1727
1728static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
1729	{ P_USB3PHY_0_PIPE, 0 },
1730	{ P_XO, 2 },
1731};
1732
1733static struct clk_regmap_mux usb0_pipe_clk_src = {
1734	.reg = 0x3e048,
1735	.shift = 8,
1736	.width = 2,
1737	.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1738	.clkr = {
1739		.hw.init = &(struct clk_init_data){
1740			.name = "usb0_pipe_clk_src",
1741			.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
1742			.num_parents = 2,
1743			.ops = &clk_regmap_mux_closest_ops,
1744			.flags = CLK_SET_RATE_PARENT,
1745		},
1746	},
1747};
1748
1749static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
1750	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1751	F(160000000, P_GPLL0, 5, 0, 0),
1752	F(216000000, P_GPLL6, 5, 0, 0),
1753	F(308570000, P_GPLL6, 3.5, 0, 0),
1754	{ }
1755};
1756
1757static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
1758	{ .fw_name = "xo"},
1759	{ .hw = &gpll0.clkr.hw },
1760	{ .hw = &gpll6.clkr.hw },
1761	{ .hw = &gpll0_out_main_div2.hw },
1762};
1763
1764static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
1765	{ P_XO, 0 },
1766	{ P_GPLL0, 1 },
1767	{ P_GPLL6, 2 },
1768	{ P_GPLL0_DIV2, 4 },
1769};
1770
1771static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1772	.cmd_rcgr = 0x5d000,
1773	.freq_tbl = ftbl_sdcc_ice_core_clk_src,
1774	.mnd_width = 8,
1775	.hid_width = 5,
1776	.parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
1777	.clkr.hw.init = &(struct clk_init_data){
1778		.name = "sdcc1_ice_core_clk_src",
1779		.parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
1780		.num_parents = 4,
1781		.ops = &clk_rcg2_ops,
1782	},
1783};
1784
1785static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
1786	F(24000000, P_XO, 1, 0, 0),
1787	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1788	F(100000000, P_GPLL0, 8, 0, 0),
1789	F(200000000, P_GPLL0, 4, 0, 0),
1790	{ }
1791};
1792
1793static struct clk_rcg2 qdss_stm_clk_src = {
1794	.cmd_rcgr = 0x2902C,
1795	.freq_tbl = ftbl_qdss_stm_clk_src,
1796	.hid_width = 5,
1797	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1798	.clkr.hw.init = &(struct clk_init_data){
1799		.name = "qdss_stm_clk_src",
1800		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1801		.num_parents = 3,
1802		.ops = &clk_rcg2_ops,
1803	},
1804};
1805
1806static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
1807	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1808	F(160000000, P_GPLL0, 5, 0, 0),
1809	F(300000000, P_GPLL4, 4, 0, 0),
1810	{ }
1811};
1812
1813static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {
1814	{ .fw_name = "xo" },
1815	{ .hw = &gpll4.clkr.hw },
1816	{ .hw = &gpll0.clkr.hw },
1817	{ .hw = &gpll0_out_main_div2.hw },
1818};
1819
1820static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {
1821	{ P_XO, 0 },
1822	{ P_GPLL4, 1 },
1823	{ P_GPLL0, 2 },
1824	{ P_GPLL0_DIV2, 4 },
1825};
1826
1827static struct clk_rcg2 qdss_traceclkin_clk_src = {
1828	.cmd_rcgr = 0x29048,
1829	.freq_tbl = ftbl_qdss_traceclkin_clk_src,
1830	.hid_width = 5,
1831	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
1832	.clkr.hw.init = &(struct clk_init_data){
1833		.name = "qdss_traceclkin_clk_src",
1834		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
1835		.num_parents = 4,
1836		.ops = &clk_rcg2_ops,
1837	},
1838};
1839
1840static struct clk_rcg2 usb1_mock_utmi_clk_src = {
1841	.cmd_rcgr = 0x3f020,
1842	.freq_tbl = ftbl_usb_mock_utmi_clk_src,
1843	.mnd_width = 8,
1844	.hid_width = 5,
1845	.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1846	.clkr.hw.init = &(struct clk_init_data){
1847		.name = "usb1_mock_utmi_clk_src",
1848		.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1849		.num_parents = 4,
1850		.ops = &clk_rcg2_ops,
1851	},
1852};
1853
1854static struct clk_branch gcc_adss_pwm_clk = {
1855	.halt_reg = 0x1c020,
1856	.clkr = {
1857		.enable_reg = 0x1c020,
1858		.enable_mask = BIT(0),
1859		.hw.init = &(struct clk_init_data){
1860			.name = "gcc_adss_pwm_clk",
1861			.parent_hws = (const struct clk_hw *[]){
1862					&adss_pwm_clk_src.clkr.hw },
1863			.num_parents = 1,
1864			.flags = CLK_SET_RATE_PARENT,
1865			.ops = &clk_branch2_ops,
1866		},
1867	},
1868};
1869
1870static struct clk_branch gcc_apss_ahb_clk = {
1871	.halt_reg = 0x4601c,
1872	.halt_check = BRANCH_HALT_VOTED,
1873	.clkr = {
1874		.enable_reg = 0x0b004,
1875		.enable_mask = BIT(14),
1876		.hw.init = &(struct clk_init_data){
1877			.name = "gcc_apss_ahb_clk",
1878			.parent_hws = (const struct clk_hw *[]){
1879					&apss_ahb_postdiv_clk_src.clkr.hw },
1880			.num_parents = 1,
1881			.flags = CLK_SET_RATE_PARENT,
1882			.ops = &clk_branch2_ops,
1883		},
1884	},
1885};
1886
1887static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1888	F(24000000, P_XO, 1, 0, 0),
1889	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1890	F(100000000, P_GPLL0, 8, 0, 0),
1891	F(133333333, P_GPLL0, 6, 0, 0),
1892	F(160000000, P_GPLL0, 5, 0, 0),
1893	F(200000000, P_GPLL0, 4, 0, 0),
1894	F(266666667, P_GPLL0, 3, 0, 0),
1895	{ }
1896};
1897
1898static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1899	.cmd_rcgr = 0x26004,
1900	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1901	.hid_width = 5,
1902	.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1903	.clkr.hw.init = &(struct clk_init_data){
1904		.name = "system_noc_bfdcd_clk_src",
1905		.parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1906		.num_parents = 4,
1907		.ops = &clk_rcg2_ops,
1908	},
1909};
1910
1911static const struct freq_tbl ftbl_ubi32_mem_noc_bfdcd_clk_src[] = {
1912	F(24000000, P_XO, 1, 0, 0),
1913	F(307670000, P_BIAS_PLL_NSS_NOC, 1.5, 0, 0),
1914	F(533333333, P_GPLL0, 1.5, 0, 0),
1915	{ }
1916};
1917
1918static const struct clk_parent_data
1919			gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
1920	{ .fw_name = "xo" },
1921	{ .hw = &gpll0.clkr.hw },
1922	{ .hw = &gpll2.clkr.hw },
1923	{ .fw_name = "bias_pll_nss_noc_clk" },
1924};
1925
1926static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {
1927	{ P_XO, 0 },
1928	{ P_GPLL0, 1 },
1929	{ P_GPLL2, 3 },
1930	{ P_BIAS_PLL_NSS_NOC, 4 },
1931};
1932
1933static struct clk_rcg2 ubi32_mem_noc_bfdcd_clk_src = {
1934	.cmd_rcgr = 0x68088,
1935	.freq_tbl = ftbl_ubi32_mem_noc_bfdcd_clk_src,
1936	.hid_width = 5,
1937	.parent_map = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map,
1938	.clkr.hw.init = &(struct clk_init_data){
1939		.name = "ubi32_mem_noc_bfdcd_clk_src",
1940		.parent_data = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk,
1941		.num_parents = 4,
1942		.ops = &clk_rcg2_ops,
1943	},
1944};
1945
1946static struct clk_branch gcc_apss_axi_clk = {
1947	.halt_reg = 0x46020,
1948	.halt_check = BRANCH_HALT_VOTED,
1949	.clkr = {
1950		.enable_reg = 0x0b004,
1951		.enable_mask = BIT(13),
1952		.hw.init = &(struct clk_init_data){
1953			.name = "gcc_apss_axi_clk",
1954			.parent_hws = (const struct clk_hw *[]){
1955					&apss_axi_clk_src.clkr.hw },
1956			.num_parents = 1,
1957			.flags = CLK_SET_RATE_PARENT,
1958			.ops = &clk_branch2_ops,
1959		},
1960	},
1961};
1962
1963static struct clk_branch gcc_blsp1_ahb_clk = {
1964	.halt_reg = 0x01008,
1965	.halt_check = BRANCH_HALT_VOTED,
1966	.clkr = {
1967		.enable_reg = 0x0b004,
1968		.enable_mask = BIT(10),
1969		.hw.init = &(struct clk_init_data){
1970			.name = "gcc_blsp1_ahb_clk",
1971			.parent_hws = (const struct clk_hw *[]){
1972					&pcnoc_bfdcd_clk_src.clkr.hw },
1973			.num_parents = 1,
1974			.flags = CLK_SET_RATE_PARENT,
1975			.ops = &clk_branch2_ops,
1976		},
1977	},
1978};
1979
1980static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1981	.halt_reg = 0x02008,
1982	.clkr = {
1983		.enable_reg = 0x02008,
1984		.enable_mask = BIT(0),
1985		.hw.init = &(struct clk_init_data){
1986			.name = "gcc_blsp1_qup1_i2c_apps_clk",
1987			.parent_hws = (const struct clk_hw *[]){
1988					&blsp1_qup1_i2c_apps_clk_src.clkr.hw },
1989			.num_parents = 1,
1990			.flags = CLK_SET_RATE_PARENT,
1991			.ops = &clk_branch2_ops,
1992		},
1993	},
1994};
1995
1996static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1997	.halt_reg = 0x02004,
1998	.clkr = {
1999		.enable_reg = 0x02004,
2000		.enable_mask = BIT(0),
2001		.hw.init = &(struct clk_init_data){
2002			.name = "gcc_blsp1_qup1_spi_apps_clk",
2003			.parent_hws = (const struct clk_hw *[]){
2004					&blsp1_qup1_spi_apps_clk_src.clkr.hw },
2005			.num_parents = 1,
2006			.flags = CLK_SET_RATE_PARENT,
2007			.ops = &clk_branch2_ops,
2008		},
2009	},
2010};
2011
2012static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
2013	.halt_reg = 0x03010,
2014	.clkr = {
2015		.enable_reg = 0x03010,
2016		.enable_mask = BIT(0),
2017		.hw.init = &(struct clk_init_data){
2018			.name = "gcc_blsp1_qup2_i2c_apps_clk",
2019			.parent_hws = (const struct clk_hw *[]){
2020					&blsp1_qup2_i2c_apps_clk_src.clkr.hw },
2021			.num_parents = 1,
2022			.flags = CLK_SET_RATE_PARENT,
2023			.ops = &clk_branch2_ops,
2024		},
2025	},
2026};
2027
2028static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2029	.halt_reg = 0x0300c,
2030	.clkr = {
2031		.enable_reg = 0x0300c,
2032		.enable_mask = BIT(0),
2033		.hw.init = &(struct clk_init_data){
2034			.name = "gcc_blsp1_qup2_spi_apps_clk",
2035			.parent_hws = (const struct clk_hw *[]){
2036					&blsp1_qup2_spi_apps_clk_src.clkr.hw },
2037			.num_parents = 1,
2038			.flags = CLK_SET_RATE_PARENT,
2039			.ops = &clk_branch2_ops,
2040		},
2041	},
2042};
2043
2044static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
2045	.halt_reg = 0x04010,
2046	.clkr = {
2047		.enable_reg = 0x04010,
2048		.enable_mask = BIT(0),
2049		.hw.init = &(struct clk_init_data){
2050			.name = "gcc_blsp1_qup3_i2c_apps_clk",
2051			.parent_hws = (const struct clk_hw *[]){
2052					&blsp1_qup3_i2c_apps_clk_src.clkr.hw },
2053			.num_parents = 1,
2054			.flags = CLK_SET_RATE_PARENT,
2055			.ops = &clk_branch2_ops,
2056		},
2057	},
2058};
2059
2060static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2061	.halt_reg = 0x0400c,
2062	.clkr = {
2063		.enable_reg = 0x0400c,
2064		.enable_mask = BIT(0),
2065		.hw.init = &(struct clk_init_data){
2066			.name = "gcc_blsp1_qup3_spi_apps_clk",
2067			.parent_hws = (const struct clk_hw *[]){
2068					&blsp1_qup3_spi_apps_clk_src.clkr.hw },
2069			.num_parents = 1,
2070			.flags = CLK_SET_RATE_PARENT,
2071			.ops = &clk_branch2_ops,
2072		},
2073	},
2074};
2075
2076static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2077	.halt_reg = 0x05010,
2078	.clkr = {
2079		.enable_reg = 0x05010,
2080		.enable_mask = BIT(0),
2081		.hw.init = &(struct clk_init_data){
2082			.name = "gcc_blsp1_qup4_i2c_apps_clk",
2083			.parent_hws = (const struct clk_hw *[]){
2084					&blsp1_qup4_i2c_apps_clk_src.clkr.hw },
2085			.num_parents = 1,
2086			.flags = CLK_SET_RATE_PARENT,
2087			.ops = &clk_branch2_ops,
2088		},
2089	},
2090};
2091
2092static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2093	.halt_reg = 0x0500c,
2094	.clkr = {
2095		.enable_reg = 0x0500c,
2096		.enable_mask = BIT(0),
2097		.hw.init = &(struct clk_init_data){
2098			.name = "gcc_blsp1_qup4_spi_apps_clk",
2099			.parent_hws = (const struct clk_hw *[]){
2100					&blsp1_qup4_spi_apps_clk_src.clkr.hw },
2101			.num_parents = 1,
2102			.flags = CLK_SET_RATE_PARENT,
2103			.ops = &clk_branch2_ops,
2104		},
2105	},
2106};
2107
2108static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2109	.halt_reg = 0x06010,
2110	.clkr = {
2111		.enable_reg = 0x06010,
2112		.enable_mask = BIT(0),
2113		.hw.init = &(struct clk_init_data){
2114			.name = "gcc_blsp1_qup5_i2c_apps_clk",
2115			.parent_hws = (const struct clk_hw *[]){
2116					&blsp1_qup5_i2c_apps_clk_src.clkr.hw },
2117			.num_parents = 1,
2118			.flags = CLK_SET_RATE_PARENT,
2119			.ops = &clk_branch2_ops,
2120		},
2121	},
2122};
2123
2124static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2125	.halt_reg = 0x0600c,
2126	.clkr = {
2127		.enable_reg = 0x0600c,
2128		.enable_mask = BIT(0),
2129		.hw.init = &(struct clk_init_data){
2130			.name = "gcc_blsp1_qup5_spi_apps_clk",
2131			.parent_hws = (const struct clk_hw *[]){
2132					&blsp1_qup5_spi_apps_clk_src.clkr.hw },
2133			.num_parents = 1,
2134			.flags = CLK_SET_RATE_PARENT,
2135			.ops = &clk_branch2_ops,
2136		},
2137	},
2138};
2139
2140static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2141	.halt_reg = 0x07010,
2142	.clkr = {
2143		.enable_reg = 0x07010,
2144		.enable_mask = BIT(0),
2145		.hw.init = &(struct clk_init_data){
2146			.name = "gcc_blsp1_qup6_i2c_apps_clk",
2147			.parent_hws = (const struct clk_hw *[]){
2148					&blsp1_qup6_i2c_apps_clk_src.clkr.hw },
2149			.num_parents = 1,
2150			/*
2151			 * RPM uses QUP6 I2C to communicate with the external
2152			 * PMIC so it must not be disabled.
2153			 */
2154			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2155			.ops = &clk_branch2_ops,
2156		},
2157	},
2158};
2159
2160static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2161	.halt_reg = 0x0700c,
2162	.clkr = {
2163		.enable_reg = 0x0700c,
2164		.enable_mask = BIT(0),
2165		.hw.init = &(struct clk_init_data){
2166			.name = "gcc_blsp1_qup6_spi_apps_clk",
2167			.parent_hws = (const struct clk_hw *[]){
2168					&blsp1_qup6_spi_apps_clk_src.clkr.hw },
2169			.num_parents = 1,
2170			.flags = CLK_SET_RATE_PARENT,
2171			.ops = &clk_branch2_ops,
2172		},
2173	},
2174};
2175
2176static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2177	.halt_reg = 0x0203c,
2178	.clkr = {
2179		.enable_reg = 0x0203c,
2180		.enable_mask = BIT(0),
2181		.hw.init = &(struct clk_init_data){
2182			.name = "gcc_blsp1_uart1_apps_clk",
2183			.parent_hws = (const struct clk_hw *[]){
2184					&blsp1_uart1_apps_clk_src.clkr.hw },
2185			.num_parents = 1,
2186			.flags = CLK_SET_RATE_PARENT,
2187			.ops = &clk_branch2_ops,
2188		},
2189	},
2190};
2191
2192static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2193	.halt_reg = 0x0302c,
2194	.clkr = {
2195		.enable_reg = 0x0302c,
2196		.enable_mask = BIT(0),
2197		.hw.init = &(struct clk_init_data){
2198			.name = "gcc_blsp1_uart2_apps_clk",
2199			.parent_hws = (const struct clk_hw *[]){
2200					&blsp1_uart2_apps_clk_src.clkr.hw },
2201			.num_parents = 1,
2202			.flags = CLK_SET_RATE_PARENT,
2203			.ops = &clk_branch2_ops,
2204		},
2205	},
2206};
2207
2208static struct clk_branch gcc_blsp1_uart3_apps_clk = {
2209	.halt_reg = 0x0402c,
2210	.clkr = {
2211		.enable_reg = 0x0402c,
2212		.enable_mask = BIT(0),
2213		.hw.init = &(struct clk_init_data){
2214			.name = "gcc_blsp1_uart3_apps_clk",
2215			.parent_hws = (const struct clk_hw *[]){
2216					&blsp1_uart3_apps_clk_src.clkr.hw },
2217			.num_parents = 1,
2218			.flags = CLK_SET_RATE_PARENT,
2219			.ops = &clk_branch2_ops,
2220		},
2221	},
2222};
2223
2224static struct clk_branch gcc_blsp1_uart4_apps_clk = {
2225	.halt_reg = 0x0502c,
2226	.clkr = {
2227		.enable_reg = 0x0502c,
2228		.enable_mask = BIT(0),
2229		.hw.init = &(struct clk_init_data){
2230			.name = "gcc_blsp1_uart4_apps_clk",
2231			.parent_hws = (const struct clk_hw *[]){
2232					&blsp1_uart4_apps_clk_src.clkr.hw },
2233			.num_parents = 1,
2234			.flags = CLK_SET_RATE_PARENT,
2235			.ops = &clk_branch2_ops,
2236		},
2237	},
2238};
2239
2240static struct clk_branch gcc_blsp1_uart5_apps_clk = {
2241	.halt_reg = 0x0602c,
2242	.clkr = {
2243		.enable_reg = 0x0602c,
2244		.enable_mask = BIT(0),
2245		.hw.init = &(struct clk_init_data){
2246			.name = "gcc_blsp1_uart5_apps_clk",
2247			.parent_hws = (const struct clk_hw *[]){
2248					&blsp1_uart5_apps_clk_src.clkr.hw },
2249			.num_parents = 1,
2250			.flags = CLK_SET_RATE_PARENT,
2251			.ops = &clk_branch2_ops,
2252		},
2253	},
2254};
2255
2256static struct clk_branch gcc_blsp1_uart6_apps_clk = {
2257	.halt_reg = 0x0702c,
2258	.clkr = {
2259		.enable_reg = 0x0702c,
2260		.enable_mask = BIT(0),
2261		.hw.init = &(struct clk_init_data){
2262			.name = "gcc_blsp1_uart6_apps_clk",
2263			.parent_hws = (const struct clk_hw *[]){
2264					&blsp1_uart6_apps_clk_src.clkr.hw },
2265			.num_parents = 1,
2266			.flags = CLK_SET_RATE_PARENT,
2267			.ops = &clk_branch2_ops,
2268		},
2269	},
2270};
2271
2272static struct clk_branch gcc_crypto_ahb_clk = {
2273	.halt_reg = 0x16024,
2274	.halt_check = BRANCH_HALT_VOTED,
2275	.clkr = {
2276		.enable_reg = 0x0b004,
2277		.enable_mask = BIT(0),
2278		.hw.init = &(struct clk_init_data){
2279			.name = "gcc_crypto_ahb_clk",
2280			.parent_hws = (const struct clk_hw *[]){
2281					&pcnoc_bfdcd_clk_src.clkr.hw },
2282			.num_parents = 1,
2283			.flags = CLK_SET_RATE_PARENT,
2284			.ops = &clk_branch2_ops,
2285		},
2286	},
2287};
2288
2289static struct clk_branch gcc_crypto_axi_clk = {
2290	.halt_reg = 0x16020,
2291	.halt_check = BRANCH_HALT_VOTED,
2292	.clkr = {
2293		.enable_reg = 0x0b004,
2294		.enable_mask = BIT(1),
2295		.hw.init = &(struct clk_init_data){
2296			.name = "gcc_crypto_axi_clk",
2297			.parent_hws = (const struct clk_hw *[]){
2298					&pcnoc_bfdcd_clk_src.clkr.hw },
2299			.num_parents = 1,
2300			.flags = CLK_SET_RATE_PARENT,
2301			.ops = &clk_branch2_ops,
2302		},
2303	},
2304};
2305
2306static struct clk_branch gcc_crypto_clk = {
2307	.halt_reg = 0x1601c,
2308	.halt_check = BRANCH_HALT_VOTED,
2309	.clkr = {
2310		.enable_reg = 0x0b004,
2311		.enable_mask = BIT(2),
2312		.hw.init = &(struct clk_init_data){
2313			.name = "gcc_crypto_clk",
2314			.parent_hws = (const struct clk_hw *[]){
2315					&crypto_clk_src.clkr.hw },
2316			.num_parents = 1,
2317			.flags = CLK_SET_RATE_PARENT,
2318			.ops = &clk_branch2_ops,
2319		},
2320	},
2321};
2322
2323static struct clk_fixed_factor gpll6_out_main_div2 = {
2324	.mult = 1,
2325	.div = 2,
2326	.hw.init = &(struct clk_init_data){
2327		.name = "gpll6_out_main_div2",
2328		.parent_hws = (const struct clk_hw *[]){
2329				&gpll6_main.clkr.hw },
2330		.num_parents = 1,
2331		.ops = &clk_fixed_factor_ops,
2332		.flags = CLK_SET_RATE_PARENT,
2333	},
2334};
2335
2336static struct clk_branch gcc_xo_clk = {
2337	.halt_reg = 0x30030,
2338	.clkr = {
2339		.enable_reg = 0x30030,
2340		.enable_mask = BIT(0),
2341		.hw.init = &(struct clk_init_data){
2342			.name = "gcc_xo_clk",
2343			.parent_hws = (const struct clk_hw *[]){
2344					&gcc_xo_clk_src.clkr.hw },
2345			.num_parents = 1,
2346			.flags = CLK_SET_RATE_PARENT,
2347			.ops = &clk_branch2_ops,
2348		},
2349	},
2350};
2351
2352static struct clk_branch gcc_gp1_clk = {
2353	.halt_reg = 0x08000,
2354	.clkr = {
2355		.enable_reg = 0x08000,
2356		.enable_mask = BIT(0),
2357		.hw.init = &(struct clk_init_data){
2358			.name = "gcc_gp1_clk",
2359			.parent_hws = (const struct clk_hw *[]){
2360					&gp1_clk_src.clkr.hw },
2361			.num_parents = 1,
2362			.flags = CLK_SET_RATE_PARENT,
2363			.ops = &clk_branch2_ops,
2364		},
2365	},
2366};
2367
2368static struct clk_branch gcc_gp2_clk = {
2369	.halt_reg = 0x09000,
2370	.clkr = {
2371		.enable_reg = 0x09000,
2372		.enable_mask = BIT(0),
2373		.hw.init = &(struct clk_init_data){
2374			.name = "gcc_gp2_clk",
2375			.parent_hws = (const struct clk_hw *[]){
2376					&gp2_clk_src.clkr.hw },
2377			.num_parents = 1,
2378			.flags = CLK_SET_RATE_PARENT,
2379			.ops = &clk_branch2_ops,
2380		},
2381	},
2382};
2383
2384static struct clk_branch gcc_gp3_clk = {
2385	.halt_reg = 0x0a000,
2386	.clkr = {
2387		.enable_reg = 0x0a000,
2388		.enable_mask = BIT(0),
2389		.hw.init = &(struct clk_init_data){
2390			.name = "gcc_gp3_clk",
2391			.parent_hws = (const struct clk_hw *[]){
2392					&gp3_clk_src.clkr.hw },
2393			.num_parents = 1,
2394			.flags = CLK_SET_RATE_PARENT,
2395			.ops = &clk_branch2_ops,
2396		},
2397	},
2398};
2399
2400static struct clk_branch gcc_mdio_ahb_clk = {
2401	.halt_reg = 0x58004,
2402	.clkr = {
2403		.enable_reg = 0x58004,
2404		.enable_mask = BIT(0),
2405		.hw.init = &(struct clk_init_data){
2406			.name = "gcc_mdio_ahb_clk",
2407			.parent_hws = (const struct clk_hw *[]){
2408					&pcnoc_bfdcd_clk_src.clkr.hw },
2409			.num_parents = 1,
2410			.flags = CLK_SET_RATE_PARENT,
2411			.ops = &clk_branch2_ops,
2412		},
2413	},
2414};
2415
2416static struct clk_branch gcc_crypto_ppe_clk = {
2417	.halt_reg = 0x68310,
2418	.clkr = {
2419		.enable_reg = 0x68310,
2420		.enable_mask = BIT(0),
2421		.hw.init = &(struct clk_init_data){
2422			.name = "gcc_crypto_ppe_clk",
2423			.parent_hws = (const struct clk_hw *[]){
2424					&nss_ppe_clk_src.clkr.hw },
2425			.num_parents = 1,
2426			.flags = CLK_SET_RATE_PARENT,
2427			.ops = &clk_branch2_ops,
2428		},
2429	},
2430};
2431
2432static struct clk_branch gcc_nss_ce_apb_clk = {
2433	.halt_reg = 0x68174,
2434	.clkr = {
2435		.enable_reg = 0x68174,
2436		.enable_mask = BIT(0),
2437		.hw.init = &(struct clk_init_data){
2438			.name = "gcc_nss_ce_apb_clk",
2439			.parent_hws = (const struct clk_hw *[]){
2440					&nss_ce_clk_src.clkr.hw },
2441			.num_parents = 1,
2442			.flags = CLK_SET_RATE_PARENT,
2443			.ops = &clk_branch2_ops,
2444		},
2445	},
2446};
2447
2448static struct clk_branch gcc_nss_ce_axi_clk = {
2449	.halt_reg = 0x68170,
2450	.clkr = {
2451		.enable_reg = 0x68170,
2452		.enable_mask = BIT(0),
2453		.hw.init = &(struct clk_init_data){
2454			.name = "gcc_nss_ce_axi_clk",
2455			.parent_hws = (const struct clk_hw *[]){
2456					&nss_ce_clk_src.clkr.hw },
2457			.num_parents = 1,
2458			.flags = CLK_SET_RATE_PARENT,
2459			.ops = &clk_branch2_ops,
2460		},
2461	},
2462};
2463
2464static struct clk_branch gcc_nss_cfg_clk = {
2465	.halt_reg = 0x68160,
2466	.clkr = {
2467		.enable_reg = 0x68160,
2468		.enable_mask = BIT(0),
2469		.hw.init = &(struct clk_init_data){
2470			.name = "gcc_nss_cfg_clk",
2471			.parent_hws = (const struct clk_hw *[]){
2472					&pcnoc_bfdcd_clk_src.clkr.hw },
2473			.num_parents = 1,
2474			.flags = CLK_SET_RATE_PARENT,
2475			.ops = &clk_branch2_ops,
2476		},
2477	},
2478};
2479
2480static struct clk_branch gcc_nss_crypto_clk = {
2481	.halt_reg = 0x68164,
2482	.clkr = {
2483		.enable_reg = 0x68164,
2484		.enable_mask = BIT(0),
2485		.hw.init = &(struct clk_init_data){
2486			.name = "gcc_nss_crypto_clk",
2487			.parent_hws = (const struct clk_hw *[]){
2488					&nss_crypto_clk_src.clkr.hw },
2489			.num_parents = 1,
2490			.flags = CLK_SET_RATE_PARENT,
2491			.ops = &clk_branch2_ops,
2492		},
2493	},
2494};
2495
2496static struct clk_branch gcc_nss_csr_clk = {
2497	.halt_reg = 0x68318,
2498	.clkr = {
2499		.enable_reg = 0x68318,
2500		.enable_mask = BIT(0),
2501		.hw.init = &(struct clk_init_data){
2502			.name = "gcc_nss_csr_clk",
2503			.parent_hws = (const struct clk_hw *[]){
2504					&nss_ce_clk_src.clkr.hw },
2505			.num_parents = 1,
2506			.flags = CLK_SET_RATE_PARENT,
2507			.ops = &clk_branch2_ops,
2508		},
2509	},
2510};
2511
2512static struct clk_branch gcc_nss_edma_cfg_clk = {
2513	.halt_reg = 0x6819C,
2514	.clkr = {
2515		.enable_reg = 0x6819C,
2516		.enable_mask = BIT(0),
2517		.hw.init = &(struct clk_init_data){
2518			.name = "gcc_nss_edma_cfg_clk",
2519			.parent_hws = (const struct clk_hw *[]){
2520					&nss_ppe_clk_src.clkr.hw },
2521			.num_parents = 1,
2522			.flags = CLK_SET_RATE_PARENT,
2523			.ops = &clk_branch2_ops,
2524		},
2525	},
2526};
2527
2528static struct clk_branch gcc_nss_edma_clk = {
2529	.halt_reg = 0x68198,
2530	.clkr = {
2531		.enable_reg = 0x68198,
2532		.enable_mask = BIT(0),
2533		.hw.init = &(struct clk_init_data){
2534			.name = "gcc_nss_edma_clk",
2535			.parent_hws = (const struct clk_hw *[]){
2536					&nss_ppe_clk_src.clkr.hw },
2537			.num_parents = 1,
2538			.flags = CLK_SET_RATE_PARENT,
2539			.ops = &clk_branch2_ops,
2540		},
2541	},
2542};
2543
2544static struct clk_branch gcc_nss_noc_clk = {
2545	.halt_reg = 0x68168,
2546	.clkr = {
2547		.enable_reg = 0x68168,
2548		.enable_mask = BIT(0),
2549		.hw.init = &(struct clk_init_data){
2550			.name = "gcc_nss_noc_clk",
2551			.parent_hws = (const struct clk_hw *[]){
2552					&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2553			.num_parents = 1,
2554			.flags = CLK_SET_RATE_PARENT,
2555			.ops = &clk_branch2_ops,
2556		},
2557	},
2558};
2559
2560static struct clk_branch gcc_ubi0_utcm_clk = {
2561	.halt_reg = 0x2606c,
2562	.clkr = {
2563		.enable_reg = 0x2606c,
2564		.enable_mask = BIT(0),
2565		.hw.init = &(struct clk_init_data){
2566			.name = "gcc_ubi0_utcm_clk",
2567			.parent_hws = (const struct clk_hw *[]){
2568					&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2569			.num_parents = 1,
2570			.flags = CLK_SET_RATE_PARENT,
2571			.ops = &clk_branch2_ops,
2572		},
2573	},
2574};
2575
2576static struct clk_branch gcc_snoc_nssnoc_clk = {
2577	.halt_reg = 0x26070,
2578	.clkr = {
2579		.enable_reg = 0x26070,
2580		.enable_mask = BIT(0),
2581		.hw.init = &(struct clk_init_data){
2582			.name = "gcc_snoc_nssnoc_clk",
2583			.parent_hws = (const struct clk_hw *[]){
2584					&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2585			.num_parents = 1,
2586			.flags = CLK_SET_RATE_PARENT,
2587			.ops = &clk_branch2_ops,
2588		},
2589	},
2590};
2591
2592static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
2593	F(24000000, P_XO, 1, 0, 0),
2594	F(133333333, P_GPLL0, 6, 0, 0),
2595	{ }
2596};
2597
2598static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
2599	F(24000000, P_XO, 1, 0, 0),
2600	F(400000000, P_GPLL0, 2, 0, 0),
2601	{ }
2602};
2603
2604static struct clk_rcg2 wcss_ahb_clk_src = {
2605	.cmd_rcgr = 0x59020,
2606	.freq_tbl = ftbl_wcss_ahb_clk_src,
2607	.hid_width = 5,
2608	.parent_map = gcc_xo_gpll0_map,
2609	.clkr.hw.init = &(struct clk_init_data){
2610		.name = "wcss_ahb_clk_src",
2611		.parent_data = gcc_xo_gpll0,
2612		.num_parents = 2,
2613		.ops = &clk_rcg2_ops,
2614	},
2615};
2616
2617static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_gpll6[] = {
2618	{ .fw_name = "xo" },
2619	{ .hw = &gpll0.clkr.hw },
2620	{ .hw = &gpll2.clkr.hw },
2621	{ .hw = &gpll4.clkr.hw },
2622	{ .hw = &gpll6.clkr.hw },
2623};
2624
2625static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_gpll6_map[] = {
2626	{ P_XO, 0 },
2627	{ P_GPLL0, 1 },
2628	{ P_GPLL2, 2 },
2629	{ P_GPLL4, 3 },
2630	{ P_GPLL6, 4 },
2631};
2632
2633static struct clk_rcg2 q6_axi_clk_src = {
2634	.cmd_rcgr = 0x59120,
2635	.freq_tbl = ftbl_q6_axi_clk_src,
2636	.hid_width = 5,
2637	.parent_map = gcc_xo_gpll0_gpll2_gpll4_gpll6_map,
2638	.clkr.hw.init = &(struct clk_init_data){
2639		.name = "q6_axi_clk_src",
2640		.parent_data = gcc_xo_gpll0_gpll2_gpll4_gpll6,
2641		.num_parents = 5,
2642		.ops = &clk_rcg2_ops,
2643	},
2644};
2645
2646static const struct freq_tbl ftbl_lpass_core_axim_clk_src[] = {
2647	F(24000000, P_XO, 1, 0, 0),
2648	F(100000000, P_GPLL0, 8, 0, 0),
2649	{ }
2650};
2651
2652static struct clk_rcg2 lpass_core_axim_clk_src = {
2653	.cmd_rcgr = 0x1F020,
2654	.freq_tbl = ftbl_lpass_core_axim_clk_src,
2655	.hid_width = 5,
2656	.parent_map = gcc_xo_gpll0_map,
2657	.clkr.hw.init = &(struct clk_init_data){
2658		.name = "lpass_core_axim_clk_src",
2659		.parent_data = gcc_xo_gpll0,
2660		.num_parents = 2,
2661		.ops = &clk_rcg2_ops,
2662	},
2663};
2664
2665static const struct freq_tbl ftbl_lpass_snoc_cfg_clk_src[] = {
2666	F(24000000, P_XO, 1, 0, 0),
2667	F(266666667, P_GPLL0, 3, 0, 0),
2668	{ }
2669};
2670
2671static struct clk_rcg2 lpass_snoc_cfg_clk_src = {
2672	.cmd_rcgr = 0x1F040,
2673	.freq_tbl = ftbl_lpass_snoc_cfg_clk_src,
2674	.hid_width = 5,
2675	.parent_map = gcc_xo_gpll0_map,
2676	.clkr.hw.init = &(struct clk_init_data){
2677		.name = "lpass_snoc_cfg_clk_src",
2678		.parent_data = gcc_xo_gpll0,
2679		.num_parents = 2,
2680		.ops = &clk_rcg2_ops,
2681	},
2682};
2683
2684static const struct freq_tbl ftbl_lpass_q6_axim_clk_src[] = {
2685	F(24000000, P_XO, 1, 0, 0),
2686	F(400000000, P_GPLL0, 2, 0, 0),
2687	{ }
2688};
2689
2690static struct clk_rcg2 lpass_q6_axim_clk_src = {
2691	.cmd_rcgr = 0x1F008,
2692	.freq_tbl = ftbl_lpass_q6_axim_clk_src,
2693	.hid_width = 5,
2694	.parent_map = gcc_xo_gpll0_map,
2695	.clkr.hw.init = &(struct clk_init_data){
2696		.name = "lpass_q6_axim_clk_src",
2697		.parent_data = gcc_xo_gpll0,
2698		.num_parents = 2,
2699		.ops = &clk_rcg2_ops,
2700	},
2701};
2702
2703static const struct freq_tbl ftbl_rbcpr_wcss_clk_src[] = {
2704	F(24000000, P_XO, 1, 0, 0),
2705	F(50000000, P_GPLL0, 16, 0, 0),
2706	{ }
2707};
2708
2709static struct clk_rcg2 rbcpr_wcss_clk_src = {
2710	.cmd_rcgr = 0x3a00c,
2711	.freq_tbl = ftbl_rbcpr_wcss_clk_src,
2712	.hid_width = 5,
2713	.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
2714	.clkr.hw.init = &(struct clk_init_data){
2715		.name = "rbcpr_wcss_clk_src",
2716		.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
2717		.num_parents = 3,
2718		.ops = &clk_rcg2_ops,
2719	},
2720};
2721
2722static struct clk_branch gcc_lpass_core_axim_clk = {
2723	.halt_reg = 0x1F028,
2724	.clkr = {
2725		.enable_reg = 0x1F028,
2726		.enable_mask = BIT(0),
2727		.hw.init = &(struct clk_init_data){
2728			.name = "gcc_lpass_core_axim_clk",
2729			.parent_hws = (const struct clk_hw *[]){
2730					&lpass_core_axim_clk_src.clkr.hw },
2731			.num_parents = 1,
2732			.flags = CLK_SET_RATE_PARENT,
2733			.ops = &clk_branch2_ops,
2734		},
2735	},
2736};
2737
2738static struct clk_branch gcc_lpass_snoc_cfg_clk = {
2739	.halt_reg = 0x1F048,
2740	.clkr = {
2741		.enable_reg = 0x1F048,
2742		.enable_mask = BIT(0),
2743		.hw.init = &(struct clk_init_data){
2744			.name = "gcc_lpass_snoc_cfg_clk",
2745			.parent_hws = (const struct clk_hw *[]){
2746					&lpass_snoc_cfg_clk_src.clkr.hw },
2747			.num_parents = 1,
2748			.flags = CLK_SET_RATE_PARENT,
2749			.ops = &clk_branch2_ops,
2750		},
2751	},
2752};
2753
2754static struct clk_branch gcc_lpass_q6_axim_clk = {
2755	.halt_reg = 0x1F010,
2756	.clkr = {
2757		.enable_reg = 0x1F010,
2758		.enable_mask = BIT(0),
2759		.hw.init = &(struct clk_init_data){
2760			.name = "gcc_lpass_q6_axim_clk",
2761			.parent_hws = (const struct clk_hw *[]){
2762					&lpass_q6_axim_clk_src.clkr.hw },
2763			.num_parents = 1,
2764			.flags = CLK_SET_RATE_PARENT,
2765			.ops = &clk_branch2_ops,
2766		},
2767	},
2768};
2769
2770static struct clk_branch gcc_lpass_q6_atbm_at_clk = {
2771	.halt_reg = 0x1F018,
2772	.clkr = {
2773		.enable_reg = 0x1F018,
2774		.enable_mask = BIT(0),
2775		.hw.init = &(struct clk_init_data){
2776			.name = "gcc_lpass_q6_atbm_at_clk",
2777			.parent_hws = (const struct clk_hw *[]){
2778					&qdss_at_clk_src.clkr.hw },
2779			.num_parents = 1,
2780			.flags = CLK_SET_RATE_PARENT,
2781			.ops = &clk_branch2_ops,
2782		},
2783	},
2784};
2785
2786static struct clk_branch gcc_lpass_q6_pclkdbg_clk = {
2787	.halt_reg = 0x1F01C,
2788	.clkr = {
2789		.enable_reg = 0x1F01C,
2790		.enable_mask = BIT(0),
2791		.hw.init = &(struct clk_init_data){
2792			.name = "gcc_lpass_q6_pclkdbg_clk",
2793			.parent_hws = (const struct clk_hw *[]){
2794					&qdss_dap_sync_clk_src.hw },
2795			.num_parents = 1,
2796			.flags = CLK_SET_RATE_PARENT,
2797			.ops = &clk_branch2_ops,
2798		},
2799	},
2800};
2801
2802static struct clk_branch gcc_lpass_q6ss_tsctr_1to2_clk = {
2803	.halt_reg = 0x1F014,
2804	.clkr = {
2805		.enable_reg = 0x1F014,
2806		.enable_mask = BIT(0),
2807		.hw.init = &(struct clk_init_data){
2808			.name = "gcc_lpass_q6ss_tsctr_1to2_clk",
2809			.parent_hws = (const struct clk_hw *[]){
2810					&qdss_tsctr_div2_clk_src.hw },
2811			.num_parents = 1,
2812			.flags = CLK_SET_RATE_PARENT,
2813			.ops = &clk_branch2_ops,
2814		},
2815	},
2816};
2817
2818static struct clk_branch gcc_lpass_q6ss_trig_clk = {
2819	.halt_reg = 0x1F038,
2820	.clkr = {
2821		.enable_reg = 0x1F038,
2822		.enable_mask = BIT(0),
2823		.hw.init = &(struct clk_init_data){
2824			.name = "gcc_lpass_q6ss_trig_clk",
2825			.parent_hws = (const struct clk_hw *[]){
2826					&qdss_dap_sync_clk_src.hw },
2827			.num_parents = 1,
2828			.flags = CLK_SET_RATE_PARENT,
2829			.ops = &clk_branch2_ops,
2830		},
2831	},
2832};
2833
2834static struct clk_branch gcc_lpass_tbu_clk = {
2835	.halt_reg = 0x12094,
2836	.clkr = {
2837		.enable_reg = 0xb00c,
2838		.enable_mask = BIT(10),
2839		.hw.init = &(struct clk_init_data){
2840			.name = "gcc_lpass_tbu_clk",
2841			.parent_hws = (const struct clk_hw *[]){
2842					&lpass_q6_axim_clk_src.clkr.hw },
2843			.num_parents = 1,
2844			.flags = CLK_SET_RATE_PARENT,
2845			.ops = &clk_branch2_ops,
2846		},
2847	},
2848};
2849
2850static struct clk_branch gcc_pcnoc_lpass_clk = {
2851	.halt_reg = 0x27020,
2852	.clkr = {
2853		.enable_reg = 0x27020,
2854		.enable_mask = BIT(0),
2855		.hw.init = &(struct clk_init_data){
2856			.name = "gcc_pcnoc_lpass_clk",
2857			.parent_hws = (const struct clk_hw *[]){
2858					&lpass_core_axim_clk_src.clkr.hw },
2859			.num_parents = 1,
2860			.flags = CLK_SET_RATE_PARENT,
2861			.ops = &clk_branch2_ops,
2862		},
2863	},
2864};
2865
2866static struct clk_branch gcc_mem_noc_lpass_clk = {
2867	.halt_reg = 0x1D044,
2868	.clkr = {
2869		.enable_reg = 0x1D044,
2870		.enable_mask = BIT(0),
2871		.hw.init = &(struct clk_init_data){
2872			.name = "gcc_mem_noc_lpass_clk",
2873			.parent_hws = (const struct clk_hw *[]){
2874					&lpass_q6_axim_clk_src.clkr.hw },
2875			.num_parents = 1,
2876			.flags = CLK_SET_RATE_PARENT,
2877			.ops = &clk_branch2_ops,
2878		},
2879	},
2880};
2881
2882static struct clk_branch gcc_snoc_lpass_cfg_clk = {
2883	.halt_reg = 0x26074,
2884	.clkr = {
2885		.enable_reg = 0x26074,
2886		.enable_mask = BIT(0),
2887		.hw.init = &(struct clk_init_data){
2888			.name = "gcc_snoc_lpass_cfg_clk",
2889			.parent_hws = (const struct clk_hw *[]){
2890					&lpass_snoc_cfg_clk_src.clkr.hw },
2891			.num_parents = 1,
2892			.flags = CLK_SET_RATE_PARENT,
2893			.ops = &clk_branch2_ops,
2894		},
2895	},
2896};
2897
2898static struct clk_branch gcc_mem_noc_ubi32_clk = {
2899	.halt_reg = 0x1D03C,
2900	.clkr = {
2901		.enable_reg = 0x1D03C,
2902		.enable_mask = BIT(0),
2903		.hw.init = &(struct clk_init_data){
2904			.name = "gcc_mem_noc_ubi32_clk",
2905			.parent_hws = (const struct clk_hw *[]){
2906					&ubi32_mem_noc_bfdcd_clk_src.clkr.hw },
2907			.num_parents = 1,
2908			.flags = CLK_SET_RATE_PARENT,
2909			.ops = &clk_branch2_ops,
2910		},
2911	},
2912};
2913
2914static struct clk_branch gcc_nss_port1_rx_clk = {
2915	.halt_reg = 0x68240,
2916	.clkr = {
2917		.enable_reg = 0x68240,
2918		.enable_mask = BIT(0),
2919		.hw.init = &(struct clk_init_data){
2920			.name = "gcc_nss_port1_rx_clk",
2921			.parent_hws = (const struct clk_hw *[]){
2922					&nss_port1_rx_div_clk_src.clkr.hw },
2923			.num_parents = 1,
2924			.flags = CLK_SET_RATE_PARENT,
2925			.ops = &clk_branch2_ops,
2926		},
2927	},
2928};
2929
2930static struct clk_branch gcc_nss_port1_tx_clk = {
2931	.halt_reg = 0x68244,
2932	.clkr = {
2933		.enable_reg = 0x68244,
2934		.enable_mask = BIT(0),
2935		.hw.init = &(struct clk_init_data){
2936			.name = "gcc_nss_port1_tx_clk",
2937			.parent_hws = (const struct clk_hw *[]){
2938					&nss_port1_tx_div_clk_src.clkr.hw },
2939			.num_parents = 1,
2940			.flags = CLK_SET_RATE_PARENT,
2941			.ops = &clk_branch2_ops,
2942		},
2943	},
2944};
2945
2946static struct clk_branch gcc_nss_port2_rx_clk = {
2947	.halt_reg = 0x68248,
2948	.clkr = {
2949		.enable_reg = 0x68248,
2950		.enable_mask = BIT(0),
2951		.hw.init = &(struct clk_init_data){
2952			.name = "gcc_nss_port2_rx_clk",
2953			.parent_hws = (const struct clk_hw *[]){
2954					&nss_port2_rx_div_clk_src.clkr.hw },
2955			.num_parents = 1,
2956			.flags = CLK_SET_RATE_PARENT,
2957			.ops = &clk_branch2_ops,
2958		},
2959	},
2960};
2961
2962static struct clk_branch gcc_nss_port2_tx_clk = {
2963	.halt_reg = 0x6824c,
2964	.clkr = {
2965		.enable_reg = 0x6824c,
2966		.enable_mask = BIT(0),
2967		.hw.init = &(struct clk_init_data){
2968			.name = "gcc_nss_port2_tx_clk",
2969			.parent_hws = (const struct clk_hw *[]){
2970					&nss_port2_tx_div_clk_src.clkr.hw },
2971			.num_parents = 1,
2972			.flags = CLK_SET_RATE_PARENT,
2973			.ops = &clk_branch2_ops,
2974		},
2975	},
2976};
2977
2978static struct clk_branch gcc_nss_port3_rx_clk = {
2979	.halt_reg = 0x68250,
2980	.clkr = {
2981		.enable_reg = 0x68250,
2982		.enable_mask = BIT(0),
2983		.hw.init = &(struct clk_init_data){
2984			.name = "gcc_nss_port3_rx_clk",
2985			.parent_hws = (const struct clk_hw *[]){
2986					&nss_port3_rx_div_clk_src.clkr.hw },
2987			.num_parents = 1,
2988			.flags = CLK_SET_RATE_PARENT,
2989			.ops = &clk_branch2_ops,
2990		},
2991	},
2992};
2993
2994static struct clk_branch gcc_nss_port3_tx_clk = {
2995	.halt_reg = 0x68254,
2996	.clkr = {
2997		.enable_reg = 0x68254,
2998		.enable_mask = BIT(0),
2999		.hw.init = &(struct clk_init_data){
3000			.name = "gcc_nss_port3_tx_clk",
3001			.parent_hws = (const struct clk_hw *[]){
3002					&nss_port3_tx_div_clk_src.clkr.hw },
3003			.num_parents = 1,
3004			.flags = CLK_SET_RATE_PARENT,
3005			.ops = &clk_branch2_ops,
3006		},
3007	},
3008};
3009
3010static struct clk_branch gcc_nss_port4_rx_clk = {
3011	.halt_reg = 0x68258,
3012	.clkr = {
3013		.enable_reg = 0x68258,
3014		.enable_mask = BIT(0),
3015		.hw.init = &(struct clk_init_data){
3016			.name = "gcc_nss_port4_rx_clk",
3017			.parent_hws = (const struct clk_hw *[]){
3018					&nss_port4_rx_div_clk_src.clkr.hw },
3019			.num_parents = 1,
3020			.flags = CLK_SET_RATE_PARENT,
3021			.ops = &clk_branch2_ops,
3022		},
3023	},
3024};
3025
3026static struct clk_branch gcc_nss_port4_tx_clk = {
3027	.halt_reg = 0x6825c,
3028	.clkr = {
3029		.enable_reg = 0x6825c,
3030		.enable_mask = BIT(0),
3031		.hw.init = &(struct clk_init_data){
3032			.name = "gcc_nss_port4_tx_clk",
3033			.parent_hws = (const struct clk_hw *[]){
3034					&nss_port4_tx_div_clk_src.clkr.hw },
3035			.num_parents = 1,
3036			.flags = CLK_SET_RATE_PARENT,
3037			.ops = &clk_branch2_ops,
3038		},
3039	},
3040};
3041
3042static struct clk_branch gcc_nss_port5_rx_clk = {
3043	.halt_reg = 0x68260,
3044	.clkr = {
3045		.enable_reg = 0x68260,
3046		.enable_mask = BIT(0),
3047		.hw.init = &(struct clk_init_data){
3048			.name = "gcc_nss_port5_rx_clk",
3049			.parent_hws = (const struct clk_hw *[]){
3050					&nss_port5_rx_div_clk_src.clkr.hw },
3051			.num_parents = 1,
3052			.flags = CLK_SET_RATE_PARENT,
3053			.ops = &clk_branch2_ops,
3054		},
3055	},
3056};
3057
3058static struct clk_branch gcc_nss_port5_tx_clk = {
3059	.halt_reg = 0x68264,
3060	.clkr = {
3061		.enable_reg = 0x68264,
3062		.enable_mask = BIT(0),
3063		.hw.init = &(struct clk_init_data){
3064			.name = "gcc_nss_port5_tx_clk",
3065			.parent_hws = (const struct clk_hw *[]){
3066					&nss_port5_tx_div_clk_src.clkr.hw },
3067			.num_parents = 1,
3068			.flags = CLK_SET_RATE_PARENT,
3069			.ops = &clk_branch2_ops,
3070		},
3071	},
3072};
3073
3074static struct clk_branch gcc_nss_ppe_cfg_clk = {
3075	.halt_reg = 0x68194,
3076	.clkr = {
3077		.enable_reg = 0x68194,
3078		.enable_mask = BIT(0),
3079		.hw.init = &(struct clk_init_data){
3080			.name = "gcc_nss_ppe_cfg_clk",
3081			.parent_hws = (const struct clk_hw *[]){
3082					&nss_ppe_clk_src.clkr.hw },
3083			.num_parents = 1,
3084			.flags = CLK_SET_RATE_PARENT,
3085			.ops = &clk_branch2_ops,
3086		},
3087	},
3088};
3089
3090static struct clk_branch gcc_nss_ppe_clk = {
3091	.halt_reg = 0x68190,
3092	.clkr = {
3093		.enable_reg = 0x68190,
3094		.enable_mask = BIT(0),
3095		.hw.init = &(struct clk_init_data){
3096			.name = "gcc_nss_ppe_clk",
3097			.parent_hws = (const struct clk_hw *[]){
3098					&nss_ppe_clk_src.clkr.hw },
3099			.num_parents = 1,
3100			.flags = CLK_SET_RATE_PARENT,
3101			.ops = &clk_branch2_ops,
3102		},
3103	},
3104};
3105
3106static struct clk_branch gcc_nss_ppe_ipe_clk = {
3107	.halt_reg = 0x68338,
3108	.clkr = {
3109		.enable_reg = 0x68338,
3110		.enable_mask = BIT(0),
3111		.hw.init = &(struct clk_init_data){
3112			.name = "gcc_nss_ppe_ipe_clk",
3113			.parent_hws = (const struct clk_hw *[]){
3114					&nss_ppe_clk_src.clkr.hw },
3115			.num_parents = 1,
3116			.flags = CLK_SET_RATE_PARENT,
3117			.ops = &clk_branch2_ops,
3118		},
3119	},
3120};
3121
3122static struct clk_branch gcc_nss_ptp_ref_clk = {
3123	.halt_reg = 0x6816C,
3124	.clkr = {
3125		.enable_reg = 0x6816C,
3126		.enable_mask = BIT(0),
3127		.hw.init = &(struct clk_init_data){
3128			.name = "gcc_nss_ptp_ref_clk",
3129			.parent_hws = (const struct clk_hw *[]){
3130					&nss_ppe_cdiv_clk_src.hw },
3131			.num_parents = 1,
3132			.flags = CLK_SET_RATE_PARENT,
3133			.ops = &clk_branch2_ops,
3134		},
3135	},
3136};
3137
3138static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3139	.halt_reg = 0x6830C,
3140	.clkr = {
3141		.enable_reg = 0x6830C,
3142		.enable_mask = BIT(0),
3143		.hw.init = &(struct clk_init_data){
3144			.name = "gcc_nssnoc_ce_apb_clk",
3145			.parent_hws = (const struct clk_hw *[]){
3146					&nss_ce_clk_src.clkr.hw },
3147			.num_parents = 1,
3148			.flags = CLK_SET_RATE_PARENT,
3149			.ops = &clk_branch2_ops,
3150		},
3151	},
3152};
3153
3154static struct clk_branch gcc_nssnoc_ce_axi_clk = {
3155	.halt_reg = 0x68308,
3156	.clkr = {
3157		.enable_reg = 0x68308,
3158		.enable_mask = BIT(0),
3159		.hw.init = &(struct clk_init_data){
3160			.name = "gcc_nssnoc_ce_axi_clk",
3161			.parent_hws = (const struct clk_hw *[]){
3162					&nss_ce_clk_src.clkr.hw },
3163			.num_parents = 1,
3164			.flags = CLK_SET_RATE_PARENT,
3165			.ops = &clk_branch2_ops,
3166		},
3167	},
3168};
3169
3170static struct clk_branch gcc_nssnoc_crypto_clk = {
3171	.halt_reg = 0x68314,
3172	.clkr = {
3173		.enable_reg = 0x68314,
3174		.enable_mask = BIT(0),
3175		.hw.init = &(struct clk_init_data){
3176			.name = "gcc_nssnoc_crypto_clk",
3177			.parent_hws = (const struct clk_hw *[]){
3178					&nss_crypto_clk_src.clkr.hw },
3179			.num_parents = 1,
3180			.flags = CLK_SET_RATE_PARENT,
3181			.ops = &clk_branch2_ops,
3182		},
3183	},
3184};
3185
3186static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
3187	.halt_reg = 0x68304,
3188	.clkr = {
3189		.enable_reg = 0x68304,
3190		.enable_mask = BIT(0),
3191		.hw.init = &(struct clk_init_data){
3192			.name = "gcc_nssnoc_ppe_cfg_clk",
3193			.parent_hws = (const struct clk_hw *[]){
3194					&nss_ppe_clk_src.clkr.hw },
3195			.flags = CLK_SET_RATE_PARENT,
3196			.ops = &clk_branch2_ops,
3197		},
3198	},
3199};
3200
3201static struct clk_branch gcc_nssnoc_ppe_clk = {
3202	.halt_reg = 0x68300,
3203	.clkr = {
3204		.enable_reg = 0x68300,
3205		.enable_mask = BIT(0),
3206		.hw.init = &(struct clk_init_data){
3207			.name = "gcc_nssnoc_ppe_clk",
3208			.parent_hws = (const struct clk_hw *[]){
3209					&nss_ppe_clk_src.clkr.hw },
3210			.num_parents = 1,
3211			.flags = CLK_SET_RATE_PARENT,
3212			.ops = &clk_branch2_ops,
3213		},
3214	},
3215};
3216
3217static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3218	.halt_reg = 0x68180,
3219	.clkr = {
3220		.enable_reg = 0x68180,
3221		.enable_mask = BIT(0),
3222		.hw.init = &(struct clk_init_data){
3223			.name = "gcc_nssnoc_qosgen_ref_clk",
3224			.parent_hws = (const struct clk_hw *[]){
3225					&gcc_xo_clk_src.clkr.hw },
3226			.num_parents = 1,
3227			.flags = CLK_SET_RATE_PARENT,
3228			.ops = &clk_branch2_ops,
3229		},
3230	},
3231};
3232
3233static struct clk_branch gcc_nssnoc_snoc_clk = {
3234	.halt_reg = 0x68188,
3235	.clkr = {
3236		.enable_reg = 0x68188,
3237		.enable_mask = BIT(0),
3238		.hw.init = &(struct clk_init_data){
3239			.name = "gcc_nssnoc_snoc_clk",
3240			.parent_hws = (const struct clk_hw *[]){
3241					&system_noc_bfdcd_clk_src.clkr.hw },
3242			.num_parents = 1,
3243			.flags = CLK_SET_RATE_PARENT,
3244			.ops = &clk_branch2_ops,
3245		},
3246	},
3247};
3248
3249static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3250	.halt_reg = 0x68184,
3251	.clkr = {
3252		.enable_reg = 0x68184,
3253		.enable_mask = BIT(0),
3254		.hw.init = &(struct clk_init_data){
3255			.name = "gcc_nssnoc_timeout_ref_clk",
3256			.parent_hws = (const struct clk_hw *[]){
3257					&gcc_xo_div4_clk_src.hw },
3258			.num_parents = 1,
3259			.flags = CLK_SET_RATE_PARENT,
3260			.ops = &clk_branch2_ops,
3261		},
3262	},
3263};
3264
3265static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
3266	.halt_reg = 0x68270,
3267	.clkr = {
3268		.enable_reg = 0x68270,
3269		.enable_mask = BIT(0),
3270		.hw.init = &(struct clk_init_data){
3271			.name = "gcc_nssnoc_ubi0_ahb_clk",
3272			.parent_hws = (const struct clk_hw *[]){
3273					&nss_ce_clk_src.clkr.hw },
3274			.num_parents = 1,
3275			.flags = CLK_SET_RATE_PARENT,
3276			.ops = &clk_branch2_ops,
3277		},
3278	},
3279};
3280
3281static struct clk_branch gcc_port1_mac_clk = {
3282	.halt_reg = 0x68320,
3283	.clkr = {
3284		.enable_reg = 0x68320,
3285		.enable_mask = BIT(0),
3286		.hw.init = &(struct clk_init_data){
3287			.name = "gcc_port1_mac_clk",
3288			.parent_hws = (const struct clk_hw *[]){
3289					&nss_ppe_clk_src.clkr.hw },
3290			.num_parents = 1,
3291			.flags = CLK_SET_RATE_PARENT,
3292			.ops = &clk_branch2_ops,
3293		},
3294	},
3295};
3296
3297static struct clk_branch gcc_port2_mac_clk = {
3298	.halt_reg = 0x68324,
3299	.clkr = {
3300		.enable_reg = 0x68324,
3301		.enable_mask = BIT(0),
3302		.hw.init = &(struct clk_init_data){
3303			.name = "gcc_port2_mac_clk",
3304			.parent_hws = (const struct clk_hw *[]){
3305					&nss_ppe_clk_src.clkr.hw },
3306			.num_parents = 1,
3307			.flags = CLK_SET_RATE_PARENT,
3308			.ops = &clk_branch2_ops,
3309		},
3310	},
3311};
3312
3313static struct clk_branch gcc_port3_mac_clk = {
3314	.halt_reg = 0x68328,
3315	.clkr = {
3316		.enable_reg = 0x68328,
3317		.enable_mask = BIT(0),
3318		.hw.init = &(struct clk_init_data){
3319			.name = "gcc_port3_mac_clk",
3320			.parent_hws = (const struct clk_hw *[]){
3321					&nss_ppe_clk_src.clkr.hw },
3322			.num_parents = 1,
3323			.flags = CLK_SET_RATE_PARENT,
3324			.ops = &clk_branch2_ops,
3325		},
3326	},
3327};
3328
3329static struct clk_branch gcc_port4_mac_clk = {
3330	.halt_reg = 0x6832c,
3331	.clkr = {
3332		.enable_reg = 0x6832c,
3333		.enable_mask = BIT(0),
3334		.hw.init = &(struct clk_init_data){
3335			.name = "gcc_port4_mac_clk",
3336			.parent_hws = (const struct clk_hw *[]){
3337					&nss_ppe_clk_src.clkr.hw },
3338			.num_parents = 1,
3339			.flags = CLK_SET_RATE_PARENT,
3340			.ops = &clk_branch2_ops,
3341		},
3342	},
3343};
3344
3345static struct clk_branch gcc_port5_mac_clk = {
3346	.halt_reg = 0x68330,
3347	.clkr = {
3348		.enable_reg = 0x68330,
3349		.enable_mask = BIT(0),
3350		.hw.init = &(struct clk_init_data){
3351			.name = "gcc_port5_mac_clk",
3352			.parent_hws = (const struct clk_hw *[]){
3353					&nss_ppe_clk_src.clkr.hw },
3354			.num_parents = 1,
3355			.flags = CLK_SET_RATE_PARENT,
3356			.ops = &clk_branch2_ops,
3357		},
3358	},
3359};
3360
3361static struct clk_branch gcc_ubi0_ahb_clk = {
3362	.halt_reg = 0x6820C,
3363	.halt_check = BRANCH_HALT_DELAY,
3364	.clkr = {
3365		.enable_reg = 0x6820C,
3366		.enable_mask = BIT(0),
3367		.hw.init = &(struct clk_init_data){
3368			.name = "gcc_ubi0_ahb_clk",
3369			.parent_hws = (const struct clk_hw *[]){
3370					&nss_ce_clk_src.clkr.hw },
3371			.num_parents = 1,
3372			.flags = CLK_SET_RATE_PARENT,
3373			.ops = &clk_branch2_ops,
3374		},
3375	},
3376};
3377
3378static struct clk_branch gcc_ubi0_axi_clk = {
3379	.halt_reg = 0x68200,
3380	.halt_check = BRANCH_HALT_DELAY,
3381	.clkr = {
3382		.enable_reg = 0x68200,
3383		.enable_mask = BIT(0),
3384		.hw.init = &(struct clk_init_data){
3385			.name = "gcc_ubi0_axi_clk",
3386			.parent_hws = (const struct clk_hw *[]){
3387					&ubi32_mem_noc_bfdcd_clk_src.clkr.hw },
3388			.num_parents = 1,
3389			.flags = CLK_SET_RATE_PARENT,
3390			.ops = &clk_branch2_ops,
3391		},
3392	},
3393};
3394
3395static struct clk_branch gcc_ubi0_nc_axi_clk = {
3396	.halt_reg = 0x68204,
3397	.halt_check = BRANCH_HALT_DELAY,
3398	.clkr = {
3399		.enable_reg = 0x68204,
3400		.enable_mask = BIT(0),
3401		.hw.init = &(struct clk_init_data){
3402			.name = "gcc_ubi0_nc_axi_clk",
3403			.parent_hws = (const struct clk_hw *[]){
3404					&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
3405			.num_parents = 1,
3406			.flags = CLK_SET_RATE_PARENT,
3407			.ops = &clk_branch2_ops,
3408		},
3409	},
3410};
3411
3412static struct clk_branch gcc_ubi0_core_clk = {
3413	.halt_reg = 0x68210,
3414	.halt_check = BRANCH_HALT_DELAY,
3415	.clkr = {
3416		.enable_reg = 0x68210,
3417		.enable_mask = BIT(0),
3418		.hw.init = &(struct clk_init_data){
3419			.name = "gcc_ubi0_core_clk",
3420			.parent_hws = (const struct clk_hw *[]){
3421					&nss_ubi0_div_clk_src.clkr.hw },
3422			.num_parents = 1,
3423			.flags = CLK_SET_RATE_PARENT,
3424			.ops = &clk_branch2_ops,
3425		},
3426	},
3427};
3428
3429static struct clk_branch gcc_pcie0_ahb_clk = {
3430	.halt_reg = 0x75010,
3431	.clkr = {
3432		.enable_reg = 0x75010,
3433		.enable_mask = BIT(0),
3434		.hw.init = &(struct clk_init_data){
3435			.name = "gcc_pcie0_ahb_clk",
3436			.parent_hws = (const struct clk_hw *[]){
3437					&pcnoc_bfdcd_clk_src.clkr.hw },
3438			.num_parents = 1,
3439			.flags = CLK_SET_RATE_PARENT,
3440			.ops = &clk_branch2_ops,
3441		},
3442	},
3443};
3444
3445static struct clk_branch gcc_pcie0_aux_clk = {
3446	.halt_reg = 0x75014,
3447	.clkr = {
3448		.enable_reg = 0x75014,
3449		.enable_mask = BIT(0),
3450		.hw.init = &(struct clk_init_data){
3451			.name = "gcc_pcie0_aux_clk",
3452			.parent_hws = (const struct clk_hw *[]){
3453					&pcie0_aux_clk_src.clkr.hw },
3454			.num_parents = 1,
3455			.flags = CLK_SET_RATE_PARENT,
3456			.ops = &clk_branch2_ops,
3457		},
3458	},
3459};
3460
3461static struct clk_branch gcc_pcie0_axi_m_clk = {
3462	.halt_reg = 0x75008,
3463	.clkr = {
3464		.enable_reg = 0x75008,
3465		.enable_mask = BIT(0),
3466		.hw.init = &(struct clk_init_data){
3467			.name = "gcc_pcie0_axi_m_clk",
3468			.parent_hws = (const struct clk_hw *[]){
3469					&pcie0_axi_clk_src.clkr.hw },
3470			.num_parents = 1,
3471			.flags = CLK_SET_RATE_PARENT,
3472			.ops = &clk_branch2_ops,
3473		},
3474	},
3475};
3476
3477static struct clk_branch gcc_pcie0_axi_s_clk = {
3478	.halt_reg = 0x7500c,
3479	.clkr = {
3480		.enable_reg = 0x7500c,
3481		.enable_mask = BIT(0),
3482		.hw.init = &(struct clk_init_data){
3483			.name = "gcc_pcie0_axi_s_clk",
3484			.parent_hws = (const struct clk_hw *[]){
3485					&pcie0_axi_clk_src.clkr.hw },
3486			.num_parents = 1,
3487			.flags = CLK_SET_RATE_PARENT,
3488			.ops = &clk_branch2_ops,
3489		},
3490	},
3491};
3492
3493static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
3494	.halt_reg = 0x26048,
3495	.clkr = {
3496		.enable_reg = 0x26048,
3497		.enable_mask = BIT(0),
3498		.hw.init = &(struct clk_init_data){
3499			.name = "gcc_sys_noc_pcie0_axi_clk",
3500			.parent_hws = (const struct clk_hw *[]){
3501					&pcie0_axi_clk_src.clkr.hw },
3502			.num_parents = 1,
3503			.flags = CLK_SET_RATE_PARENT,
3504			.ops = &clk_branch2_ops,
3505		},
3506	},
3507};
3508
3509static struct clk_branch gcc_pcie0_pipe_clk = {
3510	.halt_reg = 0x75018,
3511	.halt_check = BRANCH_HALT_DELAY,
3512	.clkr = {
3513		.enable_reg = 0x75018,
3514		.enable_mask = BIT(0),
3515		.hw.init = &(struct clk_init_data){
3516			.name = "gcc_pcie0_pipe_clk",
3517			.parent_hws = (const struct clk_hw *[]){
3518					&pcie0_pipe_clk_src.clkr.hw },
3519			.num_parents = 1,
3520			.flags = CLK_SET_RATE_PARENT,
3521			.ops = &clk_branch2_ops,
3522		},
3523	},
3524};
3525
3526static struct clk_branch gcc_prng_ahb_clk = {
3527	.halt_reg = 0x13004,
3528	.halt_check = BRANCH_HALT_VOTED,
3529	.clkr = {
3530		.enable_reg = 0x0b004,
3531		.enable_mask = BIT(8),
3532		.hw.init = &(struct clk_init_data){
3533			.name = "gcc_prng_ahb_clk",
3534			.parent_hws = (const struct clk_hw *[]){
3535					&pcnoc_bfdcd_clk_src.clkr.hw },
3536			.num_parents = 1,
3537			.flags = CLK_SET_RATE_PARENT,
3538			.ops = &clk_branch2_ops,
3539		},
3540	},
3541};
3542
3543static struct clk_branch gcc_qdss_at_clk = {
3544	.halt_reg = 0x29024,
3545	.clkr = {
3546		.enable_reg = 0x29024,
3547		.enable_mask = BIT(0),
3548		.hw.init = &(struct clk_init_data){
3549			.name = "gcc_qdss_at_clk",
3550			.parent_hws = (const struct clk_hw *[]){
3551				&qdss_at_clk_src.clkr.hw },
3552			.num_parents = 1,
3553			.flags = CLK_SET_RATE_PARENT,
3554			.ops = &clk_branch2_ops,
3555		},
3556	},
3557};
3558
3559static struct clk_branch gcc_qdss_dap_clk = {
3560	.halt_reg = 0x29084,
3561	.clkr = {
3562		.enable_reg = 0x29084,
3563		.enable_mask = BIT(0),
3564		.hw.init = &(struct clk_init_data){
3565			.name = "gcc_qdss_dap_clk",
3566			.parent_hws = (const struct clk_hw *[]){
3567					&qdss_dap_sync_clk_src.hw },
3568			.num_parents = 1,
3569			.flags = CLK_SET_RATE_PARENT,
3570			.ops = &clk_branch2_ops,
3571		},
3572	},
3573};
3574
3575static struct clk_branch gcc_qpic_ahb_clk = {
3576	.halt_reg = 0x57024,
3577	.clkr = {
3578		.enable_reg = 0x57024,
3579		.enable_mask = BIT(0),
3580		.hw.init = &(struct clk_init_data){
3581			.name = "gcc_qpic_ahb_clk",
3582			.parent_hws = (const struct clk_hw *[]){
3583					&pcnoc_bfdcd_clk_src.clkr.hw },
3584			.num_parents = 1,
3585			.flags = CLK_SET_RATE_PARENT,
3586			.ops = &clk_branch2_ops,
3587		},
3588	},
3589};
3590
3591static struct clk_branch gcc_qpic_clk = {
3592	.halt_reg = 0x57020,
3593	.clkr = {
3594		.enable_reg = 0x57020,
3595		.enable_mask = BIT(0),
3596		.hw.init = &(struct clk_init_data){
3597			.name = "gcc_qpic_clk",
3598			.parent_hws = (const struct clk_hw *[]){
3599					&pcnoc_bfdcd_clk_src.clkr.hw },
3600			.num_parents = 1,
3601			.flags = CLK_SET_RATE_PARENT,
3602			.ops = &clk_branch2_ops,
3603		},
3604	},
3605};
3606
3607static struct clk_branch gcc_sdcc1_ahb_clk = {
3608	.halt_reg = 0x4201c,
3609	.clkr = {
3610		.enable_reg = 0x4201c,
3611		.enable_mask = BIT(0),
3612		.hw.init = &(struct clk_init_data){
3613			.name = "gcc_sdcc1_ahb_clk",
3614			.parent_hws = (const struct clk_hw *[]){
3615					&pcnoc_bfdcd_clk_src.clkr.hw },
3616			.num_parents = 1,
3617			.flags = CLK_SET_RATE_PARENT,
3618			.ops = &clk_branch2_ops,
3619		},
3620	},
3621};
3622
3623static struct clk_branch gcc_sdcc1_apps_clk = {
3624	.halt_reg = 0x42018,
3625	.clkr = {
3626		.enable_reg = 0x42018,
3627		.enable_mask = BIT(0),
3628		.hw.init = &(struct clk_init_data){
3629			.name = "gcc_sdcc1_apps_clk",
3630			.parent_hws = (const struct clk_hw *[]){
3631					&sdcc1_apps_clk_src.clkr.hw },
3632			.num_parents = 1,
3633			.flags = CLK_SET_RATE_PARENT,
3634			.ops = &clk_branch2_ops,
3635		},
3636	},
3637};
3638
3639static struct clk_branch gcc_uniphy0_ahb_clk = {
3640	.halt_reg = 0x56008,
3641	.clkr = {
3642		.enable_reg = 0x56008,
3643		.enable_mask = BIT(0),
3644		.hw.init = &(struct clk_init_data){
3645			.name = "gcc_uniphy0_ahb_clk",
3646			.parent_hws = (const struct clk_hw *[]){
3647					&pcnoc_bfdcd_clk_src.clkr.hw },
3648			.num_parents = 1,
3649			.flags = CLK_SET_RATE_PARENT,
3650			.ops = &clk_branch2_ops,
3651		},
3652	},
3653};
3654
3655static struct clk_branch gcc_uniphy0_port1_rx_clk = {
3656	.halt_reg = 0x56010,
3657	.clkr = {
3658		.enable_reg = 0x56010,
3659		.enable_mask = BIT(0),
3660		.hw.init = &(struct clk_init_data){
3661			.name = "gcc_uniphy0_port1_rx_clk",
3662			.parent_hws = (const struct clk_hw *[]){
3663					&nss_port1_rx_div_clk_src.clkr.hw },
3664			.num_parents = 1,
3665			.flags = CLK_SET_RATE_PARENT,
3666			.ops = &clk_branch2_ops,
3667		},
3668	},
3669};
3670
3671static struct clk_branch gcc_uniphy0_port1_tx_clk = {
3672	.halt_reg = 0x56014,
3673	.clkr = {
3674		.enable_reg = 0x56014,
3675		.enable_mask = BIT(0),
3676		.hw.init = &(struct clk_init_data){
3677			.name = "gcc_uniphy0_port1_tx_clk",
3678			.parent_hws = (const struct clk_hw *[]){
3679					&nss_port1_tx_div_clk_src.clkr.hw },
3680			.num_parents = 1,
3681			.flags = CLK_SET_RATE_PARENT,
3682			.ops = &clk_branch2_ops,
3683		},
3684	},
3685};
3686
3687static struct clk_branch gcc_uniphy0_port2_rx_clk = {
3688	.halt_reg = 0x56018,
3689	.clkr = {
3690		.enable_reg = 0x56018,
3691		.enable_mask = BIT(0),
3692		.hw.init = &(struct clk_init_data){
3693			.name = "gcc_uniphy0_port2_rx_clk",
3694			.parent_hws = (const struct clk_hw *[]){
3695					&nss_port2_rx_div_clk_src.clkr.hw },
3696			.num_parents = 1,
3697			.flags = CLK_SET_RATE_PARENT,
3698			.ops = &clk_branch2_ops,
3699		},
3700	},
3701};
3702
3703static struct clk_branch gcc_uniphy0_port2_tx_clk = {
3704	.halt_reg = 0x5601c,
3705	.clkr = {
3706		.enable_reg = 0x5601c,
3707		.enable_mask = BIT(0),
3708		.hw.init = &(struct clk_init_data){
3709			.name = "gcc_uniphy0_port2_tx_clk",
3710			.parent_hws = (const struct clk_hw *[]){
3711					&nss_port2_tx_div_clk_src.clkr.hw },
3712			.num_parents = 1,
3713			.flags = CLK_SET_RATE_PARENT,
3714			.ops = &clk_branch2_ops,
3715		},
3716	},
3717};
3718
3719static struct clk_branch gcc_uniphy0_port3_rx_clk = {
3720	.halt_reg = 0x56020,
3721	.clkr = {
3722		.enable_reg = 0x56020,
3723		.enable_mask = BIT(0),
3724		.hw.init = &(struct clk_init_data){
3725			.name = "gcc_uniphy0_port3_rx_clk",
3726			.parent_hws = (const struct clk_hw *[]){
3727					&nss_port3_rx_div_clk_src.clkr.hw },
3728			.num_parents = 1,
3729			.flags = CLK_SET_RATE_PARENT,
3730			.ops = &clk_branch2_ops,
3731		},
3732	},
3733};
3734
3735static struct clk_branch gcc_uniphy0_port3_tx_clk = {
3736	.halt_reg = 0x56024,
3737	.clkr = {
3738		.enable_reg = 0x56024,
3739		.enable_mask = BIT(0),
3740		.hw.init = &(struct clk_init_data){
3741			.name = "gcc_uniphy0_port3_tx_clk",
3742			.parent_hws = (const struct clk_hw *[]){
3743					&nss_port3_tx_div_clk_src.clkr.hw },
3744			.num_parents = 1,
3745			.flags = CLK_SET_RATE_PARENT,
3746			.ops = &clk_branch2_ops,
3747		},
3748	},
3749};
3750
3751static struct clk_branch gcc_uniphy0_port4_rx_clk = {
3752	.halt_reg = 0x56028,
3753	.clkr = {
3754		.enable_reg = 0x56028,
3755		.enable_mask = BIT(0),
3756		.hw.init = &(struct clk_init_data){
3757			.name = "gcc_uniphy0_port4_rx_clk",
3758			.parent_hws = (const struct clk_hw *[]){
3759					&nss_port4_rx_div_clk_src.clkr.hw },
3760			.num_parents = 1,
3761			.flags = CLK_SET_RATE_PARENT,
3762			.ops = &clk_branch2_ops,
3763		},
3764	},
3765};
3766
3767static struct clk_branch gcc_uniphy0_port4_tx_clk = {
3768	.halt_reg = 0x5602c,
3769	.clkr = {
3770		.enable_reg = 0x5602c,
3771		.enable_mask = BIT(0),
3772		.hw.init = &(struct clk_init_data){
3773			.name = "gcc_uniphy0_port4_tx_clk",
3774			.parent_hws = (const struct clk_hw *[]){
3775					&nss_port4_tx_div_clk_src.clkr.hw },
3776			.num_parents = 1,
3777			.flags = CLK_SET_RATE_PARENT,
3778			.ops = &clk_branch2_ops,
3779		},
3780	},
3781};
3782
3783static struct clk_branch gcc_uniphy0_port5_rx_clk = {
3784	.halt_reg = 0x56030,
3785	.clkr = {
3786		.enable_reg = 0x56030,
3787		.enable_mask = BIT(0),
3788		.hw.init = &(struct clk_init_data){
3789			.name = "gcc_uniphy0_port5_rx_clk",
3790			.parent_hws = (const struct clk_hw *[]){
3791					&nss_port5_rx_div_clk_src.clkr.hw },
3792			.num_parents = 1,
3793			.flags = CLK_SET_RATE_PARENT,
3794			.ops = &clk_branch2_ops,
3795		},
3796	},
3797};
3798
3799static struct clk_branch gcc_uniphy0_port5_tx_clk = {
3800	.halt_reg = 0x56034,
3801	.clkr = {
3802		.enable_reg = 0x56034,
3803		.enable_mask = BIT(0),
3804		.hw.init = &(struct clk_init_data){
3805			.name = "gcc_uniphy0_port5_tx_clk",
3806			.parent_hws = (const struct clk_hw *[]){
3807					&nss_port5_tx_div_clk_src.clkr.hw },
3808			.num_parents = 1,
3809			.flags = CLK_SET_RATE_PARENT,
3810			.ops = &clk_branch2_ops,
3811		},
3812	},
3813};
3814
3815static struct clk_branch gcc_uniphy0_sys_clk = {
3816	.halt_reg = 0x5600C,
3817	.clkr = {
3818		.enable_reg = 0x5600C,
3819		.enable_mask = BIT(0),
3820		.hw.init = &(struct clk_init_data){
3821			.name = "gcc_uniphy0_sys_clk",
3822			.parent_hws = (const struct clk_hw *[]){
3823					&gcc_xo_clk_src.clkr.hw },
3824			.num_parents = 1,
3825			.flags = CLK_SET_RATE_PARENT,
3826			.ops = &clk_branch2_ops,
3827		},
3828	},
3829};
3830
3831static struct clk_branch gcc_uniphy1_ahb_clk = {
3832	.halt_reg = 0x56108,
3833	.clkr = {
3834		.enable_reg = 0x56108,
3835		.enable_mask = BIT(0),
3836		.hw.init = &(struct clk_init_data){
3837			.name = "gcc_uniphy1_ahb_clk",
3838			.parent_hws = (const struct clk_hw *[]){
3839					&pcnoc_bfdcd_clk_src.clkr.hw },
3840			.num_parents = 1,
3841			.flags = CLK_SET_RATE_PARENT,
3842			.ops = &clk_branch2_ops,
3843		},
3844	},
3845};
3846
3847static struct clk_branch gcc_uniphy1_port5_rx_clk = {
3848	.halt_reg = 0x56110,
3849	.clkr = {
3850		.enable_reg = 0x56110,
3851		.enable_mask = BIT(0),
3852		.hw.init = &(struct clk_init_data){
3853			.name = "gcc_uniphy1_port5_rx_clk",
3854			.parent_hws = (const struct clk_hw *[]){
3855					&nss_port5_rx_div_clk_src.clkr.hw },
3856			.num_parents = 1,
3857			.flags = CLK_SET_RATE_PARENT,
3858			.ops = &clk_branch2_ops,
3859		},
3860	},
3861};
3862
3863static struct clk_branch gcc_uniphy1_port5_tx_clk = {
3864	.halt_reg = 0x56114,
3865	.clkr = {
3866		.enable_reg = 0x56114,
3867		.enable_mask = BIT(0),
3868		.hw.init = &(struct clk_init_data){
3869			.name = "gcc_uniphy1_port5_tx_clk",
3870			.parent_hws = (const struct clk_hw *[]){
3871					&nss_port5_tx_div_clk_src.clkr.hw },
3872			.num_parents = 1,
3873			.flags = CLK_SET_RATE_PARENT,
3874			.ops = &clk_branch2_ops,
3875		},
3876	},
3877};
3878
3879static struct clk_branch gcc_uniphy1_sys_clk = {
3880	.halt_reg = 0x5610C,
3881	.clkr = {
3882		.enable_reg = 0x5610C,
3883		.enable_mask = BIT(0),
3884		.hw.init = &(struct clk_init_data){
3885			.name = "gcc_uniphy1_sys_clk",
3886			.parent_hws = (const struct clk_hw *[]){
3887					&gcc_xo_clk_src.clkr.hw },
3888			.num_parents = 1,
3889			.flags = CLK_SET_RATE_PARENT,
3890			.ops = &clk_branch2_ops,
3891		},
3892	},
3893};
3894
3895static struct clk_branch gcc_usb0_aux_clk = {
3896	.halt_reg = 0x3e044,
3897	.clkr = {
3898		.enable_reg = 0x3e044,
3899		.enable_mask = BIT(0),
3900		.hw.init = &(struct clk_init_data){
3901			.name = "gcc_usb0_aux_clk",
3902			.parent_hws = (const struct clk_hw *[]){
3903					&usb0_aux_clk_src.clkr.hw },
3904			.num_parents = 1,
3905			.flags = CLK_SET_RATE_PARENT,
3906			.ops = &clk_branch2_ops,
3907		},
3908	},
3909};
3910
3911static struct clk_branch gcc_usb0_master_clk = {
3912	.halt_reg = 0x3e000,
3913	.clkr = {
3914		.enable_reg = 0x3e000,
3915		.enable_mask = BIT(0),
3916		.hw.init = &(struct clk_init_data){
3917			.name = "gcc_usb0_master_clk",
3918			.parent_hws = (const struct clk_hw *[]){
3919					&usb0_master_clk_src.clkr.hw },
3920			.num_parents = 1,
3921			.flags = CLK_SET_RATE_PARENT,
3922			.ops = &clk_branch2_ops,
3923		},
3924	},
3925};
3926
3927static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = {
3928	.halt_reg = 0x47014,
3929	.clkr = {
3930		.enable_reg = 0x47014,
3931		.enable_mask = BIT(0),
3932		.hw.init = &(struct clk_init_data){
3933			.name = "gcc_snoc_bus_timeout2_ahb_clk",
3934			.parent_hws = (const struct clk_hw *[]){
3935					&usb0_master_clk_src.clkr.hw },
3936			.num_parents = 1,
3937			.flags = CLK_SET_RATE_PARENT,
3938			.ops = &clk_branch2_ops,
3939		},
3940	},
3941};
3942
3943static struct clk_rcg2 pcie0_rchng_clk_src = {
3944	.cmd_rcgr = 0x75070,
3945	.freq_tbl = ftbl_pcie_rchng_clk_src,
3946	.hid_width = 5,
3947	.parent_map = gcc_xo_gpll0_map,
3948	.clkr.hw.init = &(struct clk_init_data){
3949		.name = "pcie0_rchng_clk_src",
3950		.parent_data = gcc_xo_gpll0,
3951		.num_parents = 2,
3952		.ops = &clk_rcg2_ops,
3953	},
3954};
3955
3956static struct clk_branch gcc_pcie0_rchng_clk = {
3957	.halt_reg = 0x75070,
3958	.clkr = {
3959		.enable_reg = 0x75070,
3960		.enable_mask = BIT(1),
3961		.hw.init = &(struct clk_init_data){
3962			.name = "gcc_pcie0_rchng_clk",
3963			.parent_hws = (const struct clk_hw *[]){
3964					&pcie0_rchng_clk_src.clkr.hw },
3965			.num_parents = 1,
3966			.flags = CLK_SET_RATE_PARENT,
3967			.ops = &clk_branch2_ops,
3968		},
3969	},
3970};
3971
3972static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
3973	.halt_reg = 0x75048,
3974	.clkr = {
3975		.enable_reg = 0x75048,
3976		.enable_mask = BIT(0),
3977		.hw.init = &(struct clk_init_data){
3978			.name = "gcc_pcie0_axi_s_bridge_clk",
3979			.parent_hws = (const struct clk_hw *[]){
3980					&pcie0_axi_clk_src.clkr.hw },
3981			.num_parents = 1,
3982			.flags = CLK_SET_RATE_PARENT,
3983			.ops = &clk_branch2_ops,
3984		},
3985	},
3986};
3987
3988static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
3989	.halt_reg = 0x26040,
3990	.clkr = {
3991		.enable_reg = 0x26040,
3992		.enable_mask = BIT(0),
3993		.hw.init = &(struct clk_init_data){
3994			.name = "gcc_sys_noc_usb0_axi_clk",
3995			.parent_hws = (const struct clk_hw *[]){
3996					&usb0_master_clk_src.clkr.hw },
3997			.num_parents = 1,
3998			.flags = CLK_SET_RATE_PARENT,
3999			.ops = &clk_branch2_ops,
4000		},
4001	},
4002};
4003
4004static struct clk_branch gcc_usb0_mock_utmi_clk = {
4005	.halt_reg = 0x3e008,
4006	.clkr = {
4007		.enable_reg = 0x3e008,
4008		.enable_mask = BIT(0),
4009		.hw.init = &(struct clk_init_data){
4010			.name = "gcc_usb0_mock_utmi_clk",
4011			.parent_hws = (const struct clk_hw *[]){
4012					&usb0_mock_utmi_clk_src.clkr.hw },
4013			.num_parents = 1,
4014			.flags = CLK_SET_RATE_PARENT,
4015			.ops = &clk_branch2_ops,
4016		},
4017	},
4018};
4019
4020static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
4021	.halt_reg = 0x3e080,
4022	.clkr = {
4023		.enable_reg = 0x3e080,
4024		.enable_mask = BIT(0),
4025		.hw.init = &(struct clk_init_data){
4026			.name = "gcc_usb0_phy_cfg_ahb_clk",
4027			.parent_hws = (const struct clk_hw *[]){
4028					&pcnoc_bfdcd_clk_src.clkr.hw },
4029			.num_parents = 1,
4030			.flags = CLK_SET_RATE_PARENT,
4031			.ops = &clk_branch2_ops,
4032		},
4033	},
4034};
4035
4036static struct clk_branch gcc_usb0_pipe_clk = {
4037	.halt_reg = 0x3e040,
4038	.halt_check = BRANCH_HALT_DELAY,
4039	.clkr = {
4040		.enable_reg = 0x3e040,
4041		.enable_mask = BIT(0),
4042		.hw.init = &(struct clk_init_data){
4043			.name = "gcc_usb0_pipe_clk",
4044			.parent_hws = (const struct clk_hw *[]){
4045					&usb0_pipe_clk_src.clkr.hw },
4046			.num_parents = 1,
4047			.flags = CLK_SET_RATE_PARENT,
4048			.ops = &clk_branch2_ops,
4049		},
4050	},
4051};
4052
4053static struct clk_branch gcc_usb0_sleep_clk = {
4054	.halt_reg = 0x3e004,
4055	.clkr = {
4056		.enable_reg = 0x3e004,
4057		.enable_mask = BIT(0),
4058		.hw.init = &(struct clk_init_data){
4059			.name = "gcc_usb0_sleep_clk",
4060			.parent_hws = (const struct clk_hw *[]){
4061					&gcc_sleep_clk_src.clkr.hw },
4062			.num_parents = 1,
4063			.flags = CLK_SET_RATE_PARENT,
4064			.ops = &clk_branch2_ops,
4065		},
4066	},
4067};
4068
4069static struct clk_branch gcc_usb1_master_clk = {
4070	.halt_reg = 0x3f000,
4071	.clkr = {
4072		.enable_reg = 0x3f000,
4073		.enable_mask = BIT(0),
4074		.hw.init = &(struct clk_init_data){
4075			.name = "gcc_usb1_master_clk",
4076			.parent_hws = (const struct clk_hw *[]){
4077					&pcnoc_bfdcd_clk_src.clkr.hw },
4078			.num_parents = 1,
4079			.flags = CLK_SET_RATE_PARENT,
4080			.ops = &clk_branch2_ops,
4081		},
4082	},
4083};
4084
4085static struct clk_branch gcc_usb1_mock_utmi_clk = {
4086	.halt_reg = 0x3f008,
4087	.clkr = {
4088		.enable_reg = 0x3f008,
4089		.enable_mask = BIT(0),
4090		.hw.init = &(struct clk_init_data){
4091			.name = "gcc_usb1_mock_utmi_clk",
4092			.parent_hws = (const struct clk_hw *[]){
4093					&usb1_mock_utmi_clk_src.clkr.hw },
4094			.num_parents = 1,
4095			.flags = CLK_SET_RATE_PARENT,
4096			.ops = &clk_branch2_ops,
4097		},
4098	},
4099};
4100
4101static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
4102	.halt_reg = 0x3f080,
4103	.clkr = {
4104		.enable_reg = 0x3f080,
4105		.enable_mask = BIT(0),
4106		.hw.init = &(struct clk_init_data){
4107			.name = "gcc_usb1_phy_cfg_ahb_clk",
4108			.parent_hws = (const struct clk_hw *[]){
4109					&pcnoc_bfdcd_clk_src.clkr.hw },
4110			.num_parents = 1,
4111			.flags = CLK_SET_RATE_PARENT,
4112			.ops = &clk_branch2_ops,
4113		},
4114	},
4115};
4116
4117static struct clk_branch gcc_usb1_sleep_clk = {
4118	.halt_reg = 0x3f004,
4119	.clkr = {
4120		.enable_reg = 0x3f004,
4121		.enable_mask = BIT(0),
4122		.hw.init = &(struct clk_init_data){
4123			.name = "gcc_usb1_sleep_clk",
4124			.parent_hws = (const struct clk_hw *[]){
4125					&gcc_sleep_clk_src.clkr.hw },
4126			.num_parents = 1,
4127			.flags = CLK_SET_RATE_PARENT,
4128			.ops = &clk_branch2_ops,
4129		},
4130	},
4131};
4132
4133static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
4134	.halt_reg = 0x56308,
4135	.clkr = {
4136		.enable_reg = 0x56308,
4137		.enable_mask = BIT(0),
4138		.hw.init = &(struct clk_init_data){
4139			.name = "gcc_cmn_12gpll_ahb_clk",
4140			.parent_hws = (const struct clk_hw *[]){
4141					&pcnoc_bfdcd_clk_src.clkr.hw },
4142			.num_parents = 1,
4143			.flags = CLK_SET_RATE_PARENT,
4144			.ops = &clk_branch2_ops,
4145		},
4146	},
4147};
4148
4149static struct clk_branch gcc_cmn_12gpll_sys_clk = {
4150	.halt_reg = 0x5630c,
4151	.clkr = {
4152		.enable_reg = 0x5630c,
4153		.enable_mask = BIT(0),
4154		.hw.init = &(struct clk_init_data){
4155			.name = "gcc_cmn_12gpll_sys_clk",
4156			.parent_hws = (const struct clk_hw *[]){
4157					&gcc_xo_clk_src.clkr.hw },
4158			.num_parents = 1,
4159			.flags = CLK_SET_RATE_PARENT,
4160			.ops = &clk_branch2_ops,
4161		},
4162	},
4163};
4164
4165static struct clk_branch gcc_sdcc1_ice_core_clk = {
4166	.halt_reg = 0x5d014,
4167	.clkr = {
4168		.enable_reg = 0x5d014,
4169		.enable_mask = BIT(0),
4170		.hw.init = &(struct clk_init_data){
4171			.name = "gcc_sdcc1_ice_core_clk",
4172			.parent_hws = (const struct clk_hw *[]){
4173					&sdcc1_ice_core_clk_src.clkr.hw },
4174			.num_parents = 1,
4175			.flags = CLK_SET_RATE_PARENT,
4176			.ops = &clk_branch2_ops,
4177		},
4178	},
4179};
4180
4181static struct clk_branch gcc_dcc_clk = {
4182	.halt_reg = 0x77004,
4183	.clkr = {
4184		.enable_reg = 0x77004,
4185		.enable_mask = BIT(0),
4186		.hw.init = &(struct clk_init_data){
4187			.name = "gcc_dcc_clk",
4188			.parent_hws = (const struct clk_hw *[]){
4189					&pcnoc_bfdcd_clk_src.clkr.hw },
4190			.num_parents = 1,
4191			.flags = CLK_SET_RATE_PARENT,
4192			.ops = &clk_branch2_ops,
4193		},
4194	},
4195};
4196
4197static const struct alpha_pll_config ubi32_pll_config = {
4198	.l = 0x3e,
4199	.alpha = 0x6667,
4200	.config_ctl_val = 0x240d4828,
4201	.config_ctl_hi_val = 0x6,
4202	.main_output_mask = BIT(0),
4203	.aux_output_mask = BIT(1),
4204	.pre_div_val = 0x0,
4205	.pre_div_mask = BIT(12),
4206	.post_div_val = 0x0,
4207	.post_div_mask = GENMASK(9, 8),
4208	.alpha_en_mask = BIT(24),
4209	.test_ctl_val = 0x1C0000C0,
4210	.test_ctl_hi_val = 0x4000,
4211};
4212
4213/* 1200 MHz configuration */
4214static const struct alpha_pll_config nss_crypto_pll_config = {
4215	.l = 0x32,
4216	.config_ctl_val = 0x4001055b,
4217	.main_output_mask = BIT(0),
4218	.pre_div_val = 0x0,
4219	.pre_div_mask = GENMASK(14, 12),
4220	.post_div_val = 0x1 << 8,
4221	.post_div_mask = GENMASK(11, 8),
4222	.vco_mask = GENMASK(21, 20),
4223	.vco_val = 0x0,
4224};
4225
4226static struct clk_hw *gcc_ipq6018_hws[] = {
4227	&gpll0_out_main_div2.hw,
4228	&gcc_xo_div4_clk_src.hw,
4229	&nss_ppe_cdiv_clk_src.hw,
4230	&gpll6_out_main_div2.hw,
4231	&qdss_dap_sync_clk_src.hw,
4232	&qdss_tsctr_div2_clk_src.hw,
4233};
4234
4235static struct clk_regmap *gcc_ipq6018_clks[] = {
4236	[GPLL0_MAIN] = &gpll0_main.clkr,
4237	[GPLL0] = &gpll0.clkr,
4238	[UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4239	[UBI32_PLL] = &ubi32_pll.clkr,
4240	[GPLL6_MAIN] = &gpll6_main.clkr,
4241	[GPLL6] = &gpll6.clkr,
4242	[GPLL4_MAIN] = &gpll4_main.clkr,
4243	[GPLL4] = &gpll4.clkr,
4244	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4245	[GPLL2_MAIN] = &gpll2_main.clkr,
4246	[GPLL2] = &gpll2.clkr,
4247	[NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4248	[NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4249	[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
4250	[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
4251	[NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4252	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4253	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4254	[SNOC_NSSNOC_BFDCD_CLK_SRC] = &snoc_nssnoc_bfdcd_clk_src.clkr,
4255	[NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4256	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4257	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
4258	[NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4259	[NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4260	[UBI32_MEM_NOC_BFDCD_CLK_SRC] = &ubi32_mem_noc_bfdcd_clk_src.clkr,
4261	[PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4262	[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4263	[APSS_AHB_POSTDIV_CLK_SRC] = &apss_ahb_postdiv_clk_src.clkr,
4264	[NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4265	[NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4266	[NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4267	[NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4268	[NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4269	[NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4270	[NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4271	[NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4272	[NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4273	[NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4274	[APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
4275	[NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4276	[NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4277	[NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4278	[NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4279	[NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4280	[NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4281	[NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4282	[NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4283	[NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4284	[NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4285	[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
4286	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4287	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4288	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4289	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4290	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4291	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4292	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4293	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4294	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4295	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4296	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4297	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4298	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4299	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4300	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4301	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4302	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4303	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4304	[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4305	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
4306	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
4307	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
4308	[NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4309	[PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4310	[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4311	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4312	[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4313	[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4314	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4315	[USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4316	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
4317	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
4318	[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
4319	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4320	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4321	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4322	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4323	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4324	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4325	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4326	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4327	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4328	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4329	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4330	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
4331	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4332	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4333	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4334	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4335	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4336	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4337	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4338	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4339	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4340	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4341	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
4342	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4343	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4344	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4345	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4346	[GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
4347	[GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4348	[GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4349	[GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4350	[GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4351	[GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4352	[GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4353	[GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4354	[GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4355	[GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
4356	[GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
4357	[GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4358	[GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4359	[GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4360	[GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4361	[GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4362	[GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4363	[GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4364	[GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4365	[GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4366	[GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4367	[GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4368	[GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4369	[GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4370	[GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4371	[GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4372	[GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4373	[GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4374	[GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4375	[GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4376	[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4377	[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4378	[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4379	[GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4380	[GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4381	[GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4382	[GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4383	[GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4384	[GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4385	[GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4386	[GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4387	[GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4388	[GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4389	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4390	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4391	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4392	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4393	[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4394	[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4395	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4396	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
4397	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
4398	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4399	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4400	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4401	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4402	[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4403	[GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4404	[GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4405	[GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4406	[GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4407	[GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4408	[GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4409	[GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4410	[GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4411	[GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4412	[GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4413	[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4414	[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4415	[GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4416	[GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4417	[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4418	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4419	[GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4420	[GCC_SNOC_BUS_TIMEOUT2_AHB_CLK] = &gcc_snoc_bus_timeout2_ahb_clk.clkr,
4421	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4422	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4423	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4424	[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4425	[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4426	[GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4427	[GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4428	[GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4429	[GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4430	[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4431	[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4432	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4433	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4434	[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
4435	[PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4436	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
4437	[PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4438	[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
4439	[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
4440	[RBCPR_WCSS_CLK_SRC] = &rbcpr_wcss_clk_src.clkr,
4441	[GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
4442	[LPASS_CORE_AXIM_CLK_SRC] = &lpass_core_axim_clk_src.clkr,
4443	[GCC_LPASS_SNOC_CFG_CLK] = &gcc_lpass_snoc_cfg_clk.clkr,
4444	[LPASS_SNOC_CFG_CLK_SRC] = &lpass_snoc_cfg_clk_src.clkr,
4445	[GCC_LPASS_Q6_AXIM_CLK] = &gcc_lpass_q6_axim_clk.clkr,
4446	[LPASS_Q6_AXIM_CLK_SRC] = &lpass_q6_axim_clk_src.clkr,
4447	[GCC_LPASS_Q6_ATBM_AT_CLK] = &gcc_lpass_q6_atbm_at_clk.clkr,
4448	[GCC_LPASS_Q6_PCLKDBG_CLK] = &gcc_lpass_q6_pclkdbg_clk.clkr,
4449	[GCC_LPASS_Q6SS_TSCTR_1TO2_CLK] = &gcc_lpass_q6ss_tsctr_1to2_clk.clkr,
4450	[GCC_LPASS_Q6SS_TRIG_CLK] = &gcc_lpass_q6ss_trig_clk.clkr,
4451	[GCC_LPASS_TBU_CLK] = &gcc_lpass_tbu_clk.clkr,
4452	[GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,
4453	[GCC_MEM_NOC_UBI32_CLK] = &gcc_mem_noc_ubi32_clk.clkr,
4454	[GCC_MEM_NOC_LPASS_CLK] = &gcc_mem_noc_lpass_clk.clkr,
4455	[GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
4456	[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
4457	[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
4458};
4459
4460static const struct qcom_reset_map gcc_ipq6018_resets[] = {
4461	[GCC_BLSP1_BCR] = { 0x01000, 0 },
4462	[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4463	[GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4464	[GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4465	[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4466	[GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4467	[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4468	[GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4469	[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4470	[GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4471	[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4472	[GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4473	[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4474	[GCC_IMEM_BCR] = { 0x0e000, 0 },
4475	[GCC_SMMU_BCR] = { 0x12000, 0 },
4476	[GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4477	[GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4478	[GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4479	[GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4480	[GCC_PRNG_BCR] = { 0x13000, 0 },
4481	[GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4482	[GCC_CRYPTO_BCR] = { 0x16000, 0 },
4483	[GCC_WCSS_BCR] = { 0x18000, 0 },
4484	[GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4485	[GCC_NSS_BCR] = { 0x19000, 0 },
4486	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4487	[GCC_ADSS_BCR] = { 0x1c000, 0 },
4488	[GCC_DDRSS_BCR] = { 0x1e000, 0 },
4489	[GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4490	[GCC_PCNOC_BCR] = { 0x27018, 0 },
4491	[GCC_TCSR_BCR] = { 0x28000, 0 },
4492	[GCC_QDSS_BCR] = { 0x29000, 0 },
4493	[GCC_DCD_BCR] = { 0x2a000, 0 },
4494	[GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4495	[GCC_MPM_BCR] = { 0x2c000, 0 },
4496	[GCC_SPDM_BCR] = { 0x2f000, 0 },
4497	[GCC_RBCPR_BCR] = { 0x33000, 0 },
4498	[GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4499	[GCC_TLMM_BCR] = { 0x34000, 0 },
4500	[GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4501	[GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4502	[GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4503	[GCC_USB0_BCR] = { 0x3e070, 0 },
4504	[GCC_USB1_BCR] = { 0x3f070, 0 },
4505	[GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4506	[GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4507	[GCC_SDCC1_BCR] = { 0x42000, 0 },
4508	[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4509	[GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x47008, 0 },
4510	[GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47010, 0 },
4511	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4512	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4513	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4514	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4515	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4516	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4517	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4518	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4519	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4520	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4521	[GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4522	[GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4523	[GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4524	[GCC_QPIC_BCR] = { 0x57018, 0 },
4525	[GCC_MDIO_BCR] = { 0x58000, 0 },
4526	[GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4527	[GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4528	[GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4529	[GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4530	[GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4531	[GCC_PCIE0_BCR] = { 0x75004, 0 },
4532	[GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4533	[GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4534	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4535	[GCC_DCC_BCR] = { 0x77000, 0 },
4536	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4537	[GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4538	[GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4539	[GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4540	[GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4541	[GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4542	[GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4543	[GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4544	[GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
4545	[GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
4546	[GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4547	[GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4548	[GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4549	[GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4550	[GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4551	[GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4552	[GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4553	[GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4554	[GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4555	[GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4556	[GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4557	[GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4558	[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4559	[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4560	[GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4561	[GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4562	[GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4563	[GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4564	[GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4565	[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4566	[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4567	[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4568	[GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 },
4569	[GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 },
4570	[GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4571	[GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 },
4572	[GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4573	[GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 },
4574	[GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 },
4575	[GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c },
4576	[GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 },
4577	[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 },
4578	[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 },
4579	[GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 },
4580	[GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 },
4581	[GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 },
4582	[GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 },
4583	[GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 },
4584	[GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 },
4585	[GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 },
4586	[GCC_LPASS_BCR] = {0x1F000, 0},
4587	[GCC_UBI32_TBU_BCR] = {0x65000, 0},
4588	[GCC_LPASS_TBU_BCR] = {0x6C000, 0},
4589	[GCC_WCSSAON_RESET] = {0x59010, 0},
4590	[GCC_LPASS_Q6_AXIM_ARES] = {0x1F004, 0},
4591	[GCC_LPASS_Q6SS_TSCTR_1TO2_ARES] = {0x1F004, 1},
4592	[GCC_LPASS_Q6SS_TRIG_ARES] = {0x1F004, 2},
4593	[GCC_LPASS_Q6_ATBM_AT_ARES] = {0x1F004, 3},
4594	[GCC_LPASS_Q6_PCLKDBG_ARES] = {0x1F004, 4},
4595	[GCC_LPASS_CORE_AXIM_ARES] = {0x1F004, 5},
4596	[GCC_LPASS_SNOC_CFG_ARES] = {0x1F004, 6},
4597	[GCC_WCSS_DBG_ARES] = {0x59008, 0},
4598	[GCC_WCSS_ECAHB_ARES] = {0x59008, 1},
4599	[GCC_WCSS_ACMT_ARES] = {0x59008, 2},
4600	[GCC_WCSS_DBG_BDG_ARES] = {0x59008, 3},
4601	[GCC_WCSS_AHB_S_ARES] = {0x59008, 4},
4602	[GCC_WCSS_AXI_M_ARES] = {0x59008, 5},
4603	[GCC_Q6SS_DBG_ARES] = {0x59110, 0},
4604	[GCC_Q6_AHB_S_ARES] = {0x59110, 1},
4605	[GCC_Q6_AHB_ARES] = {0x59110, 2},
4606	[GCC_Q6_AXIM2_ARES] = {0x59110, 3},
4607	[GCC_Q6_AXIM_ARES] = {0x59110, 4},
4608};
4609
4610static const struct of_device_id gcc_ipq6018_match_table[] = {
4611	{ .compatible = "qcom,gcc-ipq6018" },
4612	{ }
4613};
4614MODULE_DEVICE_TABLE(of, gcc_ipq6018_match_table);
4615
4616static const struct regmap_config gcc_ipq6018_regmap_config = {
4617	.reg_bits       = 32,
4618	.reg_stride     = 4,
4619	.val_bits       = 32,
4620	.max_register   = 0x7fffc,
4621	.fast_io	= true,
4622};
4623
4624static const struct qcom_cc_desc gcc_ipq6018_desc = {
4625	.config = &gcc_ipq6018_regmap_config,
4626	.clks = gcc_ipq6018_clks,
4627	.num_clks = ARRAY_SIZE(gcc_ipq6018_clks),
4628	.resets = gcc_ipq6018_resets,
4629	.num_resets = ARRAY_SIZE(gcc_ipq6018_resets),
4630	.clk_hws = gcc_ipq6018_hws,
4631	.num_clk_hws = ARRAY_SIZE(gcc_ipq6018_hws),
4632};
4633
4634static int gcc_ipq6018_probe(struct platform_device *pdev)
4635{
4636	struct regmap *regmap;
4637
4638	regmap = qcom_cc_map(pdev, &gcc_ipq6018_desc);
4639	if (IS_ERR(regmap))
4640		return PTR_ERR(regmap);
4641
4642	/* Disable SW_COLLAPSE for USB0 GDSCR */
4643	regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
4644	/* Enable SW_OVERRIDE for USB0 GDSCR */
4645	regmap_update_bits(regmap, 0x3e078, BIT(2), BIT(2));
4646	/* Disable SW_COLLAPSE for USB1 GDSCR */
4647	regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
4648	/* Enable SW_OVERRIDE for USB1 GDSCR */
4649	regmap_update_bits(regmap, 0x3f078, BIT(2), BIT(2));
4650
4651	/* SW Workaround for UBI Huyara PLL */
4652	regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
4653
4654	clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
4655
4656	clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
4657				&nss_crypto_pll_config);
4658
4659	return qcom_cc_really_probe(&pdev->dev, &gcc_ipq6018_desc, regmap);
4660}
4661
4662static struct platform_driver gcc_ipq6018_driver = {
4663	.probe = gcc_ipq6018_probe,
4664	.driver = {
4665		.name   = "qcom,gcc-ipq6018",
4666		.of_match_table = gcc_ipq6018_match_table,
4667	},
4668};
4669
4670static int __init gcc_ipq6018_init(void)
4671{
4672	return platform_driver_register(&gcc_ipq6018_driver);
4673}
4674core_initcall(gcc_ipq6018_init);
4675
4676static void __exit gcc_ipq6018_exit(void)
4677{
4678	platform_driver_unregister(&gcc_ipq6018_driver);
4679}
4680module_exit(gcc_ipq6018_exit);
4681
4682MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ6018 Driver");
4683MODULE_LICENSE("GPL v2");