gcc-ipq5424.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved.
   4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
   5 */
   6
   7#include <linux/clk-provider.h>
   8#include <linux/interconnect-provider.h>
   9#include <linux/kernel.h>
  10#include <linux/module.h>
  11#include <linux/of.h>
  12#include <linux/platform_device.h>
  13#include <linux/regmap.h>
  14
  15#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
  16#include <dt-bindings/interconnect/qcom,ipq5424.h>
  17#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
  18
  19#include "clk-alpha-pll.h"
  20#include "clk-branch.h"
  21#include "clk-rcg.h"
  22#include "clk-regmap.h"
  23#include "clk-regmap-divider.h"
  24#include "clk-regmap-mux.h"
  25#include "clk-regmap-phy-mux.h"
  26#include "common.h"
  27#include "reset.h"
  28
  29enum {
  30	DT_XO,
  31	DT_SLEEP_CLK,
  32	DT_PCIE30_PHY0_PIPE_CLK,
  33	DT_PCIE30_PHY1_PIPE_CLK,
  34	DT_PCIE30_PHY2_PIPE_CLK,
  35	DT_PCIE30_PHY3_PIPE_CLK,
  36	DT_USB_PCIE_WRAPPER_PIPE_CLK,
  37};
  38
  39enum {
  40	P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
  41	P_GPLL0_OUT_AUX,
  42	P_GPLL0_OUT_MAIN,
  43	P_GPLL2_OUT_AUX,
  44	P_GPLL2_OUT_MAIN,
  45	P_GPLL4_OUT_AUX,
  46	P_GPLL4_OUT_MAIN,
  47	P_SLEEP_CLK,
  48	P_XO,
  49	P_USB3PHY_0_PIPE,
  50};
  51
  52static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
  53
  54static struct clk_alpha_pll gpll0 = {
  55	.offset = 0x20000,
  56	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
  57	.clkr = {
  58		.enable_reg = 0xb000,
  59		.enable_mask = BIT(0),
  60		.hw.init = &(const struct clk_init_data) {
  61			.name = "gpll0",
  62			.parent_data = &gcc_parent_data_xo,
  63			.num_parents = 1,
  64			.ops = &clk_alpha_pll_ops,
  65		},
  66	},
  67};
  68
  69static struct clk_fixed_factor gpll0_div2 = {
  70	.mult = 1,
  71	.div = 2,
  72	.hw.init = &(const struct clk_init_data) {
  73		.name = "gpll0_div2",
  74		.parent_hws = (const struct clk_hw *[]) {
  75			&gpll0.clkr.hw
  76		},
  77		.num_parents = 1,
  78		.ops = &clk_fixed_factor_ops,
  79	},
  80};
  81
  82static struct clk_alpha_pll_postdiv gpll0_out_aux = {
  83	.offset = 0x20000,
  84	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  85	.width = 4,
  86	.clkr.hw.init = &(const struct clk_init_data) {
  87		.name = "gpll0_out_aux",
  88		.parent_hws = (const struct clk_hw *[]) {
  89			&gpll0.clkr.hw
  90		},
  91		.num_parents = 1,
  92		.ops = &clk_alpha_pll_postdiv_ro_ops,
  93	},
  94};
  95
  96static struct clk_alpha_pll gpll2 = {
  97	.offset = 0x21000,
  98	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
  99	.clkr = {
 100		.enable_reg = 0xb000,
 101		.enable_mask = BIT(1),
 102		.hw.init = &(const struct clk_init_data) {
 103			.name = "gpll2",
 104			.parent_data = &gcc_parent_data_xo,
 105			.num_parents = 1,
 106			.ops = &clk_alpha_pll_ops,
 107		},
 108	},
 109};
 110
 111static const struct clk_div_table post_div_table_gpll2_out_main[] = {
 112	{ 0x1, 2 },
 113	{ }
 114};
 115
 116static struct clk_alpha_pll_postdiv gpll2_out_main = {
 117	.offset = 0x21000,
 118	.post_div_table = post_div_table_gpll2_out_main,
 119	.num_post_div = ARRAY_SIZE(post_div_table_gpll2_out_main),
 120	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
 121	.clkr.hw.init = &(const struct clk_init_data) {
 122		.name = "gpll2_out_main",
 123		.parent_hws = (const struct clk_hw*[]) {
 124			&gpll2.clkr.hw,
 125		},
 126		.num_parents = 1,
 127		.ops = &clk_alpha_pll_postdiv_ro_ops,
 128	},
 129};
 130
 131static struct clk_alpha_pll gpll4 = {
 132	.offset = 0x22000,
 133	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
 134	.clkr = {
 135		.enable_reg = 0xb000,
 136		.enable_mask = BIT(2),
 137		.hw.init = &(const struct clk_init_data) {
 138			.name = "gpll4",
 139			.parent_data = &gcc_parent_data_xo,
 140			.num_parents = 1,
 141			.ops = &clk_alpha_pll_ops,
 142			/*
 143			 * There are no consumers for this GPLL in kernel yet,
 144			 * (will be added soon), so the clock framework
 145			 * disables this source. But some of the clocks
 146			 * initialized by boot loaders uses this source. So we
 147			 * need to keep this clock ON. Add the
 148			 * CLK_IGNORE_UNUSED flag so the clock will not be
 149			 * disabled. Once the consumer in kernel is added, we
 150			 * can get rid of this flag.
 151			 */
 152			.flags = CLK_IGNORE_UNUSED,
 153		},
 154	},
 155};
 156
 157static const struct parent_map gcc_parent_map_xo[] = {
 158	{ P_XO, 0 },
 159};
 160
 161static const struct parent_map gcc_parent_map_0[] = {
 162	{ P_XO, 0 },
 163	{ P_GPLL0_OUT_MAIN, 1 },
 164	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
 165};
 166
 167static const struct clk_parent_data gcc_parent_data_0[] = {
 168	{ .index = DT_XO },
 169	{ .hw = &gpll0.clkr.hw },
 170	{ .hw = &gpll0_div2.hw },
 171};
 172
 173static const struct parent_map gcc_parent_map_1[] = {
 174	{ P_XO, 0 },
 175	{ P_GPLL0_OUT_MAIN, 1 },
 176};
 177
 178static const struct clk_parent_data gcc_parent_data_1[] = {
 179	{ .index = DT_XO },
 180	{ .hw = &gpll0.clkr.hw },
 181};
 182
 183static const struct parent_map gcc_parent_map_2[] = {
 184	{ P_XO, 0 },
 185	{ P_GPLL0_OUT_MAIN, 1 },
 186	{ P_GPLL4_OUT_MAIN, 2 },
 187};
 188
 189static const struct clk_parent_data gcc_parent_data_2[] = {
 190	{ .index = DT_XO },
 191	{ .hw = &gpll0.clkr.hw },
 192	{ .hw = &gpll4.clkr.hw },
 193};
 194
 195static const struct parent_map gcc_parent_map_3[] = {
 196	{ P_XO, 0 },
 197	{ P_GPLL4_OUT_MAIN, 1 },
 198	{ P_GPLL0_OUT_AUX, 2 },
 199	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
 200};
 201
 202static const struct clk_parent_data gcc_parent_data_3[] = {
 203	{ .index = DT_XO },
 204	{ .hw = &gpll4.clkr.hw },
 205	{ .hw = &gpll0.clkr.hw },
 206	{ .hw = &gpll0_div2.hw },
 207};
 208
 209static const struct parent_map gcc_parent_map_4[] = {
 210	{ P_XO, 0 },
 211};
 212
 213static const struct clk_parent_data gcc_parent_data_4[] = {
 214	{ .index = DT_XO },
 215};
 216
 217static const struct parent_map gcc_parent_map_5[] = {
 218	{ P_XO, 0 },
 219	{ P_GPLL4_OUT_AUX, 1 },
 220	{ P_GPLL0_OUT_MAIN, 3 },
 221	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
 222};
 223
 224static const struct clk_parent_data gcc_parent_data_5[] = {
 225	{ .index = DT_XO },
 226	{ .hw = &gpll4.clkr.hw },
 227	{ .hw = &gpll0.clkr.hw },
 228	{ .hw = &gpll0_div2.hw },
 229};
 230
 231static const struct parent_map gcc_parent_map_6[] = {
 232	{ P_SLEEP_CLK, 6 },
 233};
 234
 235static const struct clk_parent_data gcc_parent_data_6[] = {
 236	{ .index = DT_SLEEP_CLK },
 237};
 238
 239static const struct parent_map gcc_parent_map_7[] = {
 240	{ P_XO, 0 },
 241	{ P_GPLL0_OUT_MAIN, 1 },
 242	{ P_GPLL0_OUT_AUX, 2 },
 243	{ P_SLEEP_CLK, 6 },
 244};
 245
 246static const struct clk_parent_data gcc_parent_data_7[] = {
 247	{ .index = DT_XO },
 248	{ .hw = &gpll0.clkr.hw },
 249	{ .hw = &gpll0.clkr.hw },
 250	{ .index = DT_SLEEP_CLK },
 251};
 252
 253static const struct parent_map gcc_parent_map_8[] = {
 254	{ P_XO, 0 },
 255	{ P_GPLL0_OUT_MAIN, 1 },
 256	{ P_GPLL2_OUT_MAIN, 2 },
 257	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
 258};
 259
 260static const struct clk_parent_data gcc_parent_data_8[] = {
 261	{ .index = DT_XO },
 262	{ .hw = &gpll0.clkr.hw },
 263	{ .hw = &gpll2_out_main.clkr.hw },
 264	{ .hw = &gpll0_div2.hw },
 265};
 266
 267static const struct parent_map gcc_parent_map_9[] = {
 268	{ P_XO, 0 },
 269	{ P_GPLL0_OUT_MAIN, 1 },
 270	{ P_GPLL4_OUT_MAIN, 2 },
 271	{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
 272};
 273
 274static const struct clk_parent_data gcc_parent_data_9[] = {
 275	{ .index = DT_XO },
 276	{ .hw = &gpll0.clkr.hw },
 277	{ .hw = &gpll4.clkr.hw },
 278	{ .hw = &gpll0_div2.hw },
 279};
 280
 281static const struct parent_map gcc_parent_map_10[] = {
 282	{ P_XO, 0 },
 283	{ P_GPLL0_OUT_AUX, 2 },
 284	{ P_SLEEP_CLK, 6 },
 285};
 286
 287static const struct clk_parent_data gcc_parent_data_10[] = {
 288	{ .index = DT_XO },
 289	{ .hw = &gpll0.clkr.hw },
 290	{ .index = DT_SLEEP_CLK },
 291};
 292
 293static const struct parent_map gcc_parent_map_11[] = {
 294	{ P_XO, 0 },
 295	{ P_GPLL0_OUT_MAIN, 1 },
 296	{ P_GPLL2_OUT_AUX, 2 },
 297};
 298
 299static const struct clk_parent_data gcc_parent_data_11[] = {
 300	{ .index = DT_XO },
 301	{ .hw = &gpll0.clkr.hw },
 302	{ .hw = &gpll2.clkr.hw },
 303};
 304
 305static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = {
 306	F(24000000, P_XO, 1, 0, 0),
 307	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 308	{ }
 309};
 310
 311static struct clk_rcg2 gcc_adss_pwm_clk_src = {
 312	.cmd_rcgr = 0x1c004,
 313	.mnd_width = 0,
 314	.hid_width = 5,
 315	.parent_map = gcc_parent_map_1,
 316	.freq_tbl = ftbl_gcc_adss_pwm_clk_src,
 317	.clkr.hw.init = &(const struct clk_init_data) {
 318		.name = "gcc_adss_pwm_clk_src",
 319		.parent_data = gcc_parent_data_1,
 320		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 321		.ops = &clk_rcg2_ops,
 322	},
 323};
 324
 325static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = {
 326	F(24000000, P_XO, 1, 0, 0),
 327	{ }
 328};
 329
 330static struct clk_rcg2 gcc_xo_clk_src = {
 331	.cmd_rcgr = 0x34004,
 332	.mnd_width = 0,
 333	.hid_width = 5,
 334	.parent_map = gcc_parent_map_xo,
 335	.freq_tbl = ftbl_gcc_nss_ts_clk_src,
 336	.clkr.hw.init = &(const struct clk_init_data) {
 337		.name = "gcc_xo_clk_src",
 338		.parent_data = &gcc_parent_data_xo,
 339		.num_parents = 1,
 340		.ops = &clk_rcg2_ops,
 341	},
 342};
 343
 344static struct clk_branch gcc_xo_clk = {
 345	.halt_reg = 0x34018,
 346	.halt_check = BRANCH_HALT,
 347	.clkr = {
 348		.enable_reg = 0x34018,
 349		.enable_mask = BIT(0),
 350		.hw.init = &(const struct clk_init_data) {
 351			.name = "gcc_xo_clk",
 352			.parent_hws = (const struct clk_hw*[]) {
 353				&gcc_xo_clk_src.clkr.hw,
 354			},
 355			.num_parents = 1,
 356			.flags = CLK_SET_RATE_PARENT,
 357			.ops = &clk_branch2_ops,
 358		},
 359	},
 360};
 361
 362static struct clk_fixed_factor gcc_xo_div4_clk_src = {
 363	.mult = 1,
 364	.div = 4,
 365	.hw.init = &(const struct clk_init_data) {
 366		.name = "gcc_xo_div4_clk_src",
 367		.parent_hws = (const struct clk_hw *[]) {
 368			&gcc_xo_clk_src.clkr.hw
 369		},
 370		.num_parents = 1,
 371		.flags = CLK_SET_RATE_PARENT,
 372		.ops = &clk_fixed_factor_ops,
 373	},
 374};
 375
 376static struct clk_rcg2 gcc_nss_ts_clk_src = {
 377	.cmd_rcgr = 0x17088,
 378	.mnd_width = 0,
 379	.hid_width = 5,
 380	.parent_map = gcc_parent_map_4,
 381	.freq_tbl = ftbl_gcc_nss_ts_clk_src,
 382	.clkr.hw.init = &(const struct clk_init_data) {
 383		.name = "gcc_nss_ts_clk_src",
 384		.parent_data = gcc_parent_data_4,
 385		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
 386		.ops = &clk_rcg2_ops,
 387	},
 388};
 389
 390static const struct freq_tbl ftbl_gcc_pcie0_axi_m_clk_src[] = {
 391	F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
 392	{ }
 393};
 394
 395static struct clk_rcg2 gcc_pcie0_axi_m_clk_src = {
 396	.cmd_rcgr = 0x28018,
 397	.mnd_width = 0,
 398	.hid_width = 5,
 399	.parent_map = gcc_parent_map_2,
 400	.freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
 401	.clkr.hw.init = &(const struct clk_init_data) {
 402		.name = "gcc_pcie0_axi_m_clk_src",
 403		.parent_data = gcc_parent_data_2,
 404		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 405		.ops = &clk_rcg2_ops,
 406	},
 407};
 408
 409static struct clk_rcg2 gcc_pcie0_axi_s_clk_src = {
 410	.cmd_rcgr = 0x28020,
 411	.mnd_width = 0,
 412	.hid_width = 5,
 413	.parent_map = gcc_parent_map_2,
 414	.freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
 415	.clkr.hw.init = &(const struct clk_init_data) {
 416		.name = "gcc_pcie0_axi_s_clk_src",
 417		.parent_data = gcc_parent_data_2,
 418		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 419		.ops = &clk_rcg2_ops,
 420	},
 421};
 422
 423static struct clk_rcg2 gcc_pcie1_axi_m_clk_src = {
 424	.cmd_rcgr = 0x29018,
 425	.mnd_width = 0,
 426	.hid_width = 5,
 427	.parent_map = gcc_parent_map_2,
 428	.freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
 429	.clkr.hw.init = &(const struct clk_init_data) {
 430		.name = "gcc_pcie1_axi_m_clk_src",
 431		.parent_data = gcc_parent_data_2,
 432		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 433		.ops = &clk_rcg2_ops,
 434	},
 435};
 436
 437static struct clk_rcg2 gcc_pcie1_axi_s_clk_src = {
 438	.cmd_rcgr = 0x29020,
 439	.mnd_width = 0,
 440	.hid_width = 5,
 441	.parent_map = gcc_parent_map_2,
 442	.freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
 443	.clkr.hw.init = &(const struct clk_init_data) {
 444		.name = "gcc_pcie1_axi_s_clk_src",
 445		.parent_data = gcc_parent_data_2,
 446		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 447		.ops = &clk_rcg2_ops,
 448	},
 449};
 450
 451static const struct freq_tbl ftbl_gcc_pcie2_axi_m_clk_src[] = {
 452	F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
 453	{ }
 454};
 455
 456static struct clk_rcg2 gcc_pcie2_axi_m_clk_src = {
 457	.cmd_rcgr = 0x2a018,
 458	.mnd_width = 0,
 459	.hid_width = 5,
 460	.parent_map = gcc_parent_map_2,
 461	.freq_tbl = ftbl_gcc_pcie2_axi_m_clk_src,
 462	.clkr.hw.init = &(const struct clk_init_data) {
 463		.name = "gcc_pcie2_axi_m_clk_src",
 464		.parent_data = gcc_parent_data_2,
 465		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 466		.ops = &clk_rcg2_ops,
 467	},
 468};
 469
 470static struct clk_rcg2 gcc_pcie2_axi_s_clk_src = {
 471	.cmd_rcgr = 0x2a020,
 472	.mnd_width = 0,
 473	.hid_width = 5,
 474	.parent_map = gcc_parent_map_2,
 475	.freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
 476	.clkr.hw.init = &(const struct clk_init_data) {
 477		.name = "gcc_pcie2_axi_s_clk_src",
 478		.parent_data = gcc_parent_data_2,
 479		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 480		.ops = &clk_rcg2_ops,
 481	},
 482};
 483
 484static struct clk_rcg2 gcc_pcie3_axi_m_clk_src = {
 485	.cmd_rcgr = 0x2b018,
 486	.mnd_width = 0,
 487	.hid_width = 5,
 488	.parent_map = gcc_parent_map_2,
 489	.freq_tbl = ftbl_gcc_pcie2_axi_m_clk_src,
 490	.clkr.hw.init = &(const struct clk_init_data) {
 491		.name = "gcc_pcie3_axi_m_clk_src",
 492		.parent_data = gcc_parent_data_2,
 493		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 494		.ops = &clk_rcg2_ops,
 495	},
 496};
 497
 498static struct clk_rcg2 gcc_pcie3_axi_s_clk_src = {
 499	.cmd_rcgr = 0x2b020,
 500	.mnd_width = 0,
 501	.hid_width = 5,
 502	.parent_map = gcc_parent_map_2,
 503	.freq_tbl = ftbl_gcc_pcie0_axi_m_clk_src,
 504	.clkr.hw.init = &(const struct clk_init_data) {
 505		.name = "gcc_pcie3_axi_s_clk_src",
 506		.parent_data = gcc_parent_data_2,
 507		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
 508		.ops = &clk_rcg2_ops,
 509	},
 510};
 511
 512static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {
 513	F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
 514	{ }
 515};
 516
 517static struct clk_rcg2 gcc_pcie_aux_clk_src = {
 518	.cmd_rcgr = 0x28004,
 519	.mnd_width = 16,
 520	.hid_width = 5,
 521	.parent_map = gcc_parent_map_7,
 522	.freq_tbl = ftbl_gcc_pcie_aux_clk_src,
 523	.clkr.hw.init = &(const struct clk_init_data) {
 524		.name = "gcc_pcie_aux_clk_src",
 525		.parent_data = gcc_parent_data_7,
 526		.num_parents = ARRAY_SIZE(gcc_parent_data_7),
 527		.ops = &clk_rcg2_ops,
 528	},
 529};
 530
 531static const struct freq_tbl ftbl_gcc_qupv3_i2c0_clk_src[] = {
 532	F(4800000, P_XO, 5, 0, 0),
 533	F(9600000, P_XO, 2.5, 0, 0),
 534	F(24000000, P_XO, 1, 0, 0),
 535	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 536	F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
 537	{ }
 538};
 539
 540static struct clk_rcg2 gcc_qupv3_i2c0_clk_src = {
 541	.cmd_rcgr = 0x2018,
 542	.mnd_width = 0,
 543	.hid_width = 5,
 544	.parent_map = gcc_parent_map_0,
 545	.freq_tbl = ftbl_gcc_qupv3_i2c0_clk_src,
 546	.clkr.hw.init = &(const struct clk_init_data) {
 547		.name = "gcc_qupv3_i2c0_clk_src",
 548		.parent_data = gcc_parent_data_0,
 549		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 550		.ops = &clk_rcg2_ops,
 551	},
 552};
 553
 554static struct clk_rcg2 gcc_qupv3_i2c1_clk_src = {
 555	.cmd_rcgr = 0x3018,
 556	.mnd_width = 0,
 557	.hid_width = 5,
 558	.parent_map = gcc_parent_map_0,
 559	.freq_tbl = ftbl_gcc_qupv3_i2c0_clk_src,
 560	.clkr.hw.init = &(const struct clk_init_data) {
 561		.name = "gcc_qupv3_i2c1_clk_src",
 562		.parent_data = gcc_parent_data_0,
 563		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 564		.ops = &clk_rcg2_ops,
 565	},
 566};
 567
 568static const struct freq_tbl ftbl_gcc_qupv3_spi0_clk_src[] = {
 569	F(960000, P_XO, 10, 2, 5),
 570	F(4800000, P_XO, 5, 0, 0),
 571	F(9600000, P_XO, 2, 4, 5),
 572	F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
 573	F(24000000, P_XO, 1, 0, 0),
 574	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
 575	F(32000000, P_GPLL0_OUT_MAIN, 10, 2, 5),
 576	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 577	{ }
 578};
 579
 580static struct clk_rcg2 gcc_qupv3_spi0_clk_src = {
 581	.cmd_rcgr = 0x4004,
 582	.mnd_width = 8,
 583	.hid_width = 5,
 584	.parent_map = gcc_parent_map_0,
 585	.freq_tbl = ftbl_gcc_qupv3_spi0_clk_src,
 586	.clkr.hw.init = &(const struct clk_init_data) {
 587		.name = "gcc_qupv3_spi0_clk_src",
 588		.parent_data = gcc_parent_data_0,
 589		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 590		.ops = &clk_rcg2_ops,
 591	},
 592};
 593
 594static struct clk_rcg2 gcc_qupv3_spi1_clk_src = {
 595	.cmd_rcgr = 0x5004,
 596	.mnd_width = 8,
 597	.hid_width = 5,
 598	.parent_map = gcc_parent_map_0,
 599	.freq_tbl = ftbl_gcc_qupv3_spi0_clk_src,
 600	.clkr.hw.init = &(const struct clk_init_data) {
 601		.name = "gcc_qupv3_spi1_clk_src",
 602		.parent_data = gcc_parent_data_0,
 603		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 604		.ops = &clk_rcg2_ops,
 605	},
 606};
 607
 608static const struct freq_tbl ftbl_gcc_qupv3_uart0_clk_src[] = {
 609	F(3686400,  P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 144, 15625),
 610	F(7372800,  P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 288, 15625),
 611	F(14745600, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 576, 15625),
 612	F(24000000, P_XO, 1, 0, 0),
 613	F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
 614	F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
 615	F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
 616	F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
 617	F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
 618	F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
 619	F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
 620	F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
 621	F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
 622	F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
 623	{ }
 624};
 625
 626static struct clk_rcg2 gcc_qupv3_uart0_clk_src = {
 627	.cmd_rcgr = 0x202c,
 628	.mnd_width = 16,
 629	.hid_width = 5,
 630	.parent_map = gcc_parent_map_0,
 631	.freq_tbl = ftbl_gcc_qupv3_uart0_clk_src,
 632	.clkr.hw.init = &(const struct clk_init_data) {
 633		.name = "gcc_qupv3_uart0_clk_src",
 634		.parent_data = gcc_parent_data_0,
 635		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 636		.ops = &clk_rcg2_ops,
 637	},
 638};
 639
 640static struct clk_rcg2 gcc_qupv3_uart1_clk_src = {
 641	.cmd_rcgr = 0x302c,
 642	.mnd_width = 16,
 643	.hid_width = 5,
 644	.parent_map = gcc_parent_map_0,
 645	.freq_tbl = ftbl_gcc_qupv3_uart0_clk_src,
 646	.clkr.hw.init = &(const struct clk_init_data) {
 647		.name = "gcc_qupv3_uart1_clk_src",
 648		.parent_data = gcc_parent_data_0,
 649		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 650		.ops = &clk_rcg2_ops,
 651	},
 652};
 653
 654static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
 655	F(144000, P_XO, 16, 12, 125),
 656	F(400000, P_XO, 12, 1, 5),
 657	F(24000000, P_GPLL2_OUT_MAIN, 12, 1, 2),
 658	F(48000000, P_GPLL2_OUT_MAIN, 12, 0, 0),
 659	F(96000000, P_GPLL2_OUT_MAIN, 6, 0, 0),
 660	F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
 661	F(192000000, P_GPLL2_OUT_MAIN, 3, 0, 0),
 662	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 663	{ }
 664};
 665
 666static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
 667	.cmd_rcgr = 0x33004,
 668	.mnd_width = 8,
 669	.hid_width = 5,
 670	.parent_map = gcc_parent_map_8,
 671	.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
 672	.clkr.hw.init = &(const struct clk_init_data) {
 673		.name = "gcc_sdcc1_apps_clk_src",
 674		.parent_data = gcc_parent_data_8,
 675		.num_parents = ARRAY_SIZE(gcc_parent_data_8),
 676		.ops = &clk_rcg2_floor_ops,
 677	},
 678};
 679
 680static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
 681	F(300000000, P_GPLL4_OUT_MAIN, 4, 0, 0),
 682	{ }
 683};
 684
 685static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
 686	.cmd_rcgr = 0x33018,
 687	.mnd_width = 8,
 688	.hid_width = 5,
 689	.parent_map = gcc_parent_map_9,
 690	.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
 691	.clkr.hw.init = &(const struct clk_init_data) {
 692		.name = "gcc_sdcc1_ice_core_clk_src",
 693		.parent_data = gcc_parent_data_9,
 694		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
 695		.ops = &clk_rcg2_ops,
 696	},
 697};
 698
 699static struct clk_rcg2 gcc_uniphy_sys_clk_src = {
 700	.cmd_rcgr = 0x17090,
 701	.mnd_width = 0,
 702	.hid_width = 5,
 703	.parent_map = gcc_parent_map_4,
 704	.freq_tbl = ftbl_gcc_nss_ts_clk_src,
 705	.clkr.hw.init = &(const struct clk_init_data) {
 706		.name = "gcc_uniphy_sys_clk_src",
 707		.parent_data = &gcc_parent_data_xo,
 708		.num_parents = 1,
 709		.ops = &clk_rcg2_ops,
 710	},
 711};
 712
 713static struct clk_rcg2 gcc_usb0_aux_clk_src = {
 714	.cmd_rcgr = 0x2c018,
 715	.mnd_width = 16,
 716	.hid_width = 5,
 717	.parent_map = gcc_parent_map_10,
 718	.freq_tbl = ftbl_gcc_nss_ts_clk_src,
 719	.clkr.hw.init = &(const struct clk_init_data) {
 720		.name = "gcc_usb0_aux_clk_src",
 721		.parent_data = gcc_parent_data_10,
 722		.num_parents = ARRAY_SIZE(gcc_parent_data_10),
 723		.ops = &clk_rcg2_ops,
 724	},
 725};
 726
 727static const struct freq_tbl ftbl_gcc_usb0_master_clk_src[] = {
 728	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 729	{ }
 730};
 731
 732static struct clk_rcg2 gcc_usb0_master_clk_src = {
 733	.cmd_rcgr = 0x2c004,
 734	.mnd_width = 8,
 735	.hid_width = 5,
 736	.parent_map = gcc_parent_map_0,
 737	.freq_tbl = ftbl_gcc_usb0_master_clk_src,
 738	.clkr.hw.init = &(const struct clk_init_data) {
 739		.name = "gcc_usb0_master_clk_src",
 740		.parent_data = gcc_parent_data_0,
 741		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 742		.ops = &clk_rcg2_ops,
 743	},
 744};
 745
 746static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = {
 747	F(24000000, P_XO, 1, 0, 0),
 748	F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2),
 749	{ }
 750};
 751
 752static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
 753	.cmd_rcgr = 0x2c02c,
 754	.mnd_width = 8,
 755	.hid_width = 5,
 756	.parent_map = gcc_parent_map_5,
 757	.freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
 758	.clkr.hw.init = &(const struct clk_init_data) {
 759		.name = "gcc_usb0_mock_utmi_clk_src",
 760		.parent_data = gcc_parent_data_5,
 761		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
 762		.ops = &clk_rcg2_ops,
 763	},
 764};
 765
 766static struct clk_rcg2 gcc_usb1_mock_utmi_clk_src = {
 767	.cmd_rcgr = 0x3c004,
 768	.mnd_width = 8,
 769	.hid_width = 5,
 770	.parent_map = gcc_parent_map_5,
 771	.freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
 772	.clkr.hw.init = &(const struct clk_init_data) {
 773		.name = "gcc_usb1_mock_utmi_clk_src",
 774		.parent_data = gcc_parent_data_5,
 775		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
 776		.ops = &clk_rcg2_ops,
 777	},
 778};
 779
 780static const struct freq_tbl ftbl_gcc_wcss_ahb_clk_src[] = {
 781	F(24000000, P_XO, 1, 0, 0),
 782	F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
 783	{ }
 784};
 785
 786static struct clk_rcg2 gcc_wcss_ahb_clk_src = {
 787	.cmd_rcgr = 0x25030,
 788	.freq_tbl = ftbl_gcc_wcss_ahb_clk_src,
 789	.hid_width = 5,
 790	.parent_map = gcc_parent_map_1,
 791	.clkr.hw.init = &(const struct clk_init_data) {
 792		.name = "gcc_wcss_ahb_clk_src",
 793		.parent_data = gcc_parent_data_1,
 794		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 795		.ops = &clk_rcg2_ops,
 796	},
 797};
 798
 799static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = {
 800	F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
 801	{ }
 802};
 803
 804static struct clk_rcg2 gcc_qdss_at_clk_src = {
 805	.cmd_rcgr = 0x2d004,
 806	.freq_tbl = ftbl_gcc_qdss_at_clk_src,
 807	.hid_width = 5,
 808	.parent_map = gcc_parent_map_3,
 809	.clkr.hw.init = &(const struct clk_init_data) {
 810		.name = "gcc_qdss_at_clk_src",
 811		.parent_data = gcc_parent_data_3,
 812		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
 813		.ops = &clk_rcg2_ops,
 814	},
 815};
 816
 817static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = {
 818	F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
 819	{ }
 820};
 821
 822static struct clk_rcg2 gcc_qdss_tsctr_clk_src = {
 823	.cmd_rcgr = 0x2d01c,
 824	.freq_tbl = ftbl_gcc_qdss_tsctr_clk_src,
 825	.hid_width = 5,
 826	.parent_map = gcc_parent_map_3,
 827	.clkr.hw.init = &(const struct clk_init_data) {
 828		.name = "gcc_qdss_tsctr_clk_src",
 829		.parent_data = gcc_parent_data_3,
 830		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
 831		.ops = &clk_rcg2_ops,
 832	},
 833};
 834
 835static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {
 836	.mult = 1,
 837	.div = 2,
 838	.hw.init = &(const struct clk_init_data) {
 839		.name = "gcc_qdss_tsctr_div2_clk_src",
 840		.parent_hws = (const struct clk_hw *[]) {
 841			&gcc_qdss_tsctr_clk_src.clkr.hw
 842		},
 843		.num_parents = 1,
 844		.flags = CLK_SET_RATE_PARENT,
 845		.ops = &clk_fixed_factor_ops,
 846	},
 847};
 848
 849static struct clk_fixed_factor gcc_qdss_dap_sync_clk_src = {
 850	.mult = 1,
 851	.div = 4,
 852	.hw.init = &(const struct clk_init_data) {
 853		.name = "gcc_qdss_dap_sync_clk_src",
 854		.parent_hws = (const struct clk_hw *[]) {
 855			&gcc_qdss_tsctr_clk_src.clkr.hw
 856		},
 857		.num_parents = 1,
 858		.ops = &clk_fixed_factor_ops,
 859	},
 860};
 861
 862static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = {
 863	F(24000000, P_XO, 1, 0, 0),
 864	F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
 865	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 866	F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
 867	{ }
 868};
 869
 870static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
 871	.cmd_rcgr = 0x2e004,
 872	.freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,
 873	.hid_width = 5,
 874	.parent_map = gcc_parent_map_9,
 875	.clkr.hw.init = &(const struct clk_init_data) {
 876		.name = "gcc_system_noc_bfdcd_clk_src",
 877		.parent_data = gcc_parent_data_9,
 878		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
 879		.ops = &clk_rcg2_ops,
 880	},
 881};
 882
 883static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = {
 884	F(24000000, P_XO, 1, 0, 0),
 885	F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 886	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 887	{ }
 888};
 889
 890static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = {
 891	.cmd_rcgr = 0x31004,
 892	.mnd_width = 0,
 893	.hid_width = 5,
 894	.parent_map = gcc_parent_map_0,
 895	.freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src,
 896	.clkr.hw.init = &(const struct clk_init_data) {
 897		.name = "gcc_pcnoc_bfdcd_clk_src",
 898		.parent_data = gcc_parent_data_0,
 899		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
 900		.ops = &clk_rcg2_ops,
 901	},
 902};
 903
 904static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = {
 905	F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
 906	{ }
 907};
 908
 909static struct clk_rcg2 gcc_lpass_sway_clk_src = {
 910	.cmd_rcgr = 0x27004,
 911	.mnd_width = 0,
 912	.hid_width = 5,
 913	.parent_map = gcc_parent_map_1,
 914	.freq_tbl = ftbl_gcc_lpass_sway_clk_src,
 915	.clkr.hw.init = &(const struct clk_init_data) {
 916		.name = "gcc_lpass_sway_clk_src",
 917		.parent_data = gcc_parent_data_1,
 918		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 919		.ops = &clk_rcg2_ops,
 920	},
 921};
 922
 923static struct clk_rcg2 gcc_lpass_axim_clk_src = {
 924	.cmd_rcgr = 0x2700c,
 925	.mnd_width = 0,
 926	.hid_width = 5,
 927	.parent_map = gcc_parent_map_1,
 928	.freq_tbl = ftbl_gcc_lpass_sway_clk_src,
 929	.clkr.hw.init = &(const struct clk_init_data) {
 930		.name = "gcc_lpass_axim_clk_src",
 931		.parent_data = gcc_parent_data_1,
 932		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
 933		.ops = &clk_rcg2_ops,
 934	},
 935};
 936
 937static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
 938	.mult = 1,
 939	.div = 6,
 940	.hw.init = &(const struct clk_init_data) {
 941		.name = "gcc_eud_at_div_clk_src",
 942		.parent_hws = (const struct clk_hw *[]) {
 943			&gcc_qdss_at_clk_src.clkr.hw },
 944		.num_parents = 1,
 945		.flags = CLK_SET_RATE_PARENT,
 946		.ops = &clk_fixed_factor_ops,
 947	},
 948};
 949
 950static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = {
 951	F(32000, P_SLEEP_CLK, 1, 0, 0),
 952	{ }
 953};
 954
 955static struct clk_rcg2 gcc_sleep_clk_src = {
 956	.cmd_rcgr = 0x3400c,
 957	.mnd_width = 0,
 958	.hid_width = 5,
 959	.parent_map = gcc_parent_map_6,
 960	.freq_tbl = ftbl_gcc_sleep_clk_src,
 961	.clkr.hw.init = &(const struct clk_init_data) {
 962		.name = "gcc_sleep_clk_src",
 963		.parent_data = gcc_parent_data_6,
 964		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
 965		.ops = &clk_rcg2_ops,
 966	},
 967};
 968
 969static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = {
 970	F(24000000, P_XO, 1, 0, 0),
 971	F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 972	F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 973	F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 974	F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 975	{ }
 976};
 977
 978static struct clk_rcg2 gcc_qpic_io_macro_clk_src = {
 979	.cmd_rcgr = 0x32004,
 980	.mnd_width = 0,
 981	.hid_width = 5,
 982	.parent_map = gcc_parent_map_11,
 983	.freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
 984	.clkr.hw.init = &(const struct clk_init_data) {
 985		.name = "gcc_qpic_io_macro_clk_src",
 986		.parent_data = gcc_parent_data_11,
 987		.num_parents = ARRAY_SIZE(gcc_parent_data_11),
 988		.ops = &clk_rcg2_ops,
 989	},
 990};
 991
 992static struct clk_rcg2 gcc_qpic_clk_src = {
 993	.cmd_rcgr = 0x32020,
 994	.mnd_width = 0,
 995	.hid_width = 5,
 996	.parent_map = gcc_parent_map_11,
 997	.freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
 998	.clkr.hw.init = &(const struct clk_init_data) {
 999		.name = "gcc_qpic_clk_src",
1000		.parent_data = gcc_parent_data_11,
1001		.num_parents = ARRAY_SIZE(gcc_parent_data_11),
1002		.ops = &clk_rcg2_ops,
1003	},
1004};
1005
1006static struct clk_rcg2 gcc_pcie0_rchng_clk_src = {
1007	.cmd_rcgr = 0x28028,
1008	.mnd_width = 0,
1009	.hid_width = 5,
1010	.parent_map = gcc_parent_map_1,
1011	.freq_tbl = ftbl_gcc_adss_pwm_clk_src,
1012	.clkr.hw.init = &(const struct clk_init_data) {
1013		.name = "gcc_pcie0_rchng_clk_src",
1014		.parent_data = gcc_parent_data_1,
1015		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1016		.ops = &clk_rcg2_ops,
1017	},
1018};
1019
1020static struct clk_rcg2 gcc_pcie1_rchng_clk_src = {
1021	.cmd_rcgr = 0x29028,
1022	.mnd_width = 0,
1023	.hid_width = 5,
1024	.parent_map = gcc_parent_map_1,
1025	.freq_tbl = ftbl_gcc_adss_pwm_clk_src,
1026	.clkr.hw.init = &(const struct clk_init_data) {
1027		.name = "gcc_pcie1_rchng_clk_src",
1028		.parent_data = gcc_parent_data_1,
1029		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1030		.ops = &clk_rcg2_ops,
1031	},
1032};
1033
1034static struct clk_rcg2 gcc_pcie2_rchng_clk_src = {
1035	.cmd_rcgr = 0x2a028,
1036	.mnd_width = 0,
1037	.hid_width = 5,
1038	.parent_map = gcc_parent_map_1,
1039	.freq_tbl = ftbl_gcc_adss_pwm_clk_src,
1040	.clkr.hw.init = &(const struct clk_init_data) {
1041		.name = "gcc_pcie2_rchng_clk_src",
1042		.parent_data = gcc_parent_data_1,
1043		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1044		.ops = &clk_rcg2_ops,
1045	},
1046};
1047
1048static struct clk_rcg2 gcc_pcie3_rchng_clk_src = {
1049	.cmd_rcgr = 0x2b028,
1050	.mnd_width = 0,
1051	.hid_width = 5,
1052	.parent_map = gcc_parent_map_1,
1053	.freq_tbl = ftbl_gcc_adss_pwm_clk_src,
1054	.clkr.hw.init = &(const struct clk_init_data) {
1055		.name = "gcc_pcie3_rchng_clk_src",
1056		.parent_data = gcc_parent_data_1,
1057		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1058		.ops = &clk_rcg2_ops,
1059	},
1060};
1061
1062static struct clk_regmap_div gcc_qupv3_i2c0_div_clk_src = {
1063	.reg = 0x2020,
1064	.shift = 0,
1065	.width = 2,
1066	.clkr.hw.init = &(const struct clk_init_data) {
1067		.name = "gcc_qupv3_i2c0_div_clk_src",
1068		.parent_hws = (const struct clk_hw*[]) {
1069			&gcc_qupv3_i2c0_clk_src.clkr.hw,
1070		},
1071		.num_parents = 1,
1072		.flags = CLK_SET_RATE_PARENT,
1073		.ops = &clk_regmap_div_ro_ops,
1074	},
1075};
1076
1077static struct clk_regmap_div gcc_qupv3_i2c1_div_clk_src = {
1078	.reg = 0x3020,
1079	.shift = 0,
1080	.width = 2,
1081	.clkr.hw.init = &(const struct clk_init_data) {
1082		.name = "gcc_qupv3_i2c1_div_clk_src",
1083		.parent_hws = (const struct clk_hw*[]) {
1084			&gcc_qupv3_i2c1_clk_src.clkr.hw,
1085		},
1086		.num_parents = 1,
1087		.flags = CLK_SET_RATE_PARENT,
1088		.ops = &clk_regmap_div_ro_ops,
1089	},
1090};
1091
1092static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = {
1093	.reg = 0x2c040,
1094	.shift = 0,
1095	.width = 2,
1096	.clkr.hw.init = &(const struct clk_init_data) {
1097		.name = "gcc_usb0_mock_utmi_div_clk_src",
1098		.parent_hws = (const struct clk_hw*[]) {
1099			&gcc_usb0_mock_utmi_clk_src.clkr.hw,
1100		},
1101		.num_parents = 1,
1102		.flags = CLK_SET_RATE_PARENT,
1103		.ops = &clk_regmap_div_ro_ops,
1104	},
1105};
1106
1107static struct clk_regmap_div gcc_usb1_mock_utmi_div_clk_src = {
1108	.reg = 0x3c018,
1109	.shift = 0,
1110	.width = 2,
1111	.clkr.hw.init = &(const struct clk_init_data) {
1112		.name = "gcc_usb1_mock_utmi_div_clk_src",
1113		.parent_hws = (const struct clk_hw*[]) {
1114			&gcc_usb1_mock_utmi_clk_src.clkr.hw,
1115		},
1116		.num_parents = 1,
1117		.flags = CLK_SET_RATE_PARENT,
1118		.ops = &clk_regmap_div_ro_ops,
1119	},
1120};
1121
1122static struct clk_branch gcc_adss_pwm_clk = {
1123	.halt_reg = 0x1c00c,
1124	.halt_check = BRANCH_HALT,
1125	.clkr = {
1126		.enable_reg = 0x1c00c,
1127		.enable_mask = BIT(0),
1128		.hw.init = &(const struct clk_init_data) {
1129			.name = "gcc_adss_pwm_clk",
1130			.parent_hws = (const struct clk_hw*[]) {
1131				&gcc_adss_pwm_clk_src.clkr.hw,
1132			},
1133			.num_parents = 1,
1134			.flags = CLK_SET_RATE_PARENT,
1135			.ops = &clk_branch2_ops,
1136		},
1137	},
1138};
1139
1140static struct clk_branch gcc_cnoc_pcie0_1lane_s_clk = {
1141	.halt_reg = 0x31088,
1142	.halt_check = BRANCH_HALT,
1143	.clkr = {
1144		.enable_reg = 0x31088,
1145		.enable_mask = BIT(0),
1146		.hw.init = &(const struct clk_init_data) {
1147			.name = "gcc_cnoc_pcie0_1lane_s_clk",
1148			.parent_hws = (const struct clk_hw*[]) {
1149				&gcc_pcie0_axi_s_clk_src.clkr.hw,
1150			},
1151			.num_parents = 1,
1152			.flags = CLK_SET_RATE_PARENT,
1153			.ops = &clk_branch2_ops,
1154		},
1155	},
1156};
1157
1158static struct clk_branch gcc_cnoc_pcie1_1lane_s_clk = {
1159	.halt_reg = 0x3108c,
1160	.halt_check = BRANCH_HALT,
1161	.clkr = {
1162		.enable_reg = 0x3108c,
1163		.enable_mask = BIT(0),
1164		.hw.init = &(const struct clk_init_data) {
1165			.name = "gcc_cnoc_pcie1_1lane_s_clk",
1166			.parent_hws = (const struct clk_hw*[]) {
1167				&gcc_pcie1_axi_s_clk_src.clkr.hw,
1168			},
1169			.num_parents = 1,
1170			.flags = CLK_SET_RATE_PARENT,
1171			.ops = &clk_branch2_ops,
1172		},
1173	},
1174};
1175
1176static struct clk_branch gcc_cnoc_pcie2_2lane_s_clk = {
1177	.halt_reg = 0x31090,
1178	.halt_check = BRANCH_HALT,
1179	.clkr = {
1180		.enable_reg = 0x31090,
1181		.enable_mask = BIT(0),
1182		.hw.init = &(const struct clk_init_data) {
1183			.name = "gcc_cnoc_pcie2_2lane_s_clk",
1184			.parent_hws = (const struct clk_hw*[]) {
1185				&gcc_pcie2_axi_s_clk_src.clkr.hw,
1186			},
1187			.num_parents = 1,
1188			.flags = CLK_SET_RATE_PARENT,
1189			.ops = &clk_branch2_ops,
1190		},
1191	},
1192};
1193
1194static struct clk_branch gcc_cnoc_pcie3_2lane_s_clk = {
1195	.halt_reg = 0x31094,
1196	.halt_check = BRANCH_HALT,
1197	.clkr = {
1198		.enable_reg = 0x31094,
1199		.enable_mask = BIT(0),
1200		.hw.init = &(const struct clk_init_data) {
1201			.name = "gcc_cnoc_pcie3_2lane_s_clk",
1202			.parent_hws = (const struct clk_hw*[]) {
1203				&gcc_pcie3_axi_s_clk_src.clkr.hw,
1204			},
1205			.num_parents = 1,
1206			.flags = CLK_SET_RATE_PARENT,
1207			.ops = &clk_branch2_ops,
1208		},
1209	},
1210};
1211
1212static struct clk_branch gcc_cnoc_usb_clk = {
1213	.halt_reg = 0x310a8,
1214	.halt_check = BRANCH_HALT_VOTED,
1215	.clkr = {
1216		.enable_reg = 0x310a8,
1217		.enable_mask = BIT(0),
1218		.hw.init = &(const struct clk_init_data) {
1219			.name = "gcc_cnoc_usb_clk",
1220			.parent_hws = (const struct clk_hw*[]) {
1221				&gcc_usb0_master_clk_src.clkr.hw,
1222			},
1223			.num_parents = 1,
1224			.flags = CLK_SET_RATE_PARENT,
1225			.ops = &clk_branch2_ops,
1226		},
1227	},
1228};
1229
1230static struct clk_branch gcc_mdio_ahb_clk = {
1231	.halt_reg = 0x17040,
1232	.halt_check = BRANCH_HALT,
1233	.clkr = {
1234		.enable_reg = 0x17040,
1235		.enable_mask = BIT(0),
1236		.hw.init = &(const struct clk_init_data) {
1237			.name = "gcc_mdio_ahb_clk",
1238			.parent_hws = (const struct clk_hw*[]) {
1239				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1240			},
1241			.num_parents = 1,
1242			.flags = CLK_SET_RATE_PARENT,
1243			.ops = &clk_branch2_ops,
1244		},
1245	},
1246};
1247
1248static struct clk_branch gcc_nss_ts_clk = {
1249	.halt_reg = 0x17018,
1250	.halt_check = BRANCH_HALT_VOTED,
1251	.clkr = {
1252		.enable_reg = 0x17018,
1253		.enable_mask = BIT(0),
1254		.hw.init = &(const struct clk_init_data) {
1255			.name = "gcc_nss_ts_clk",
1256			.parent_hws = (const struct clk_hw*[]) {
1257				&gcc_nss_ts_clk_src.clkr.hw,
1258			},
1259			.num_parents = 1,
1260			.flags = CLK_SET_RATE_PARENT,
1261			.ops = &clk_branch2_ops,
1262		},
1263	},
1264};
1265
1266static struct clk_branch gcc_nsscc_clk = {
1267	.halt_reg = 0x17034,
1268	.halt_check = BRANCH_HALT,
1269	.clkr = {
1270		.enable_reg = 0x17034,
1271		.enable_mask = BIT(0),
1272		.hw.init = &(const struct clk_init_data) {
1273			.name = "gcc_nsscc_clk",
1274			.parent_hws = (const struct clk_hw*[]) {
1275				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1276			},
1277			.num_parents = 1,
1278			.flags = CLK_SET_RATE_PARENT,
1279			.ops = &clk_branch2_ops,
1280		},
1281	},
1282};
1283
1284static struct clk_branch gcc_nsscfg_clk = {
1285	.halt_reg = 0x1702c,
1286	.halt_check = BRANCH_HALT,
1287	.clkr = {
1288		.enable_reg = 0x1702c,
1289		.enable_mask = BIT(0),
1290		.hw.init = &(const struct clk_init_data) {
1291			.name = "gcc_nsscfg_clk",
1292			.parent_hws = (const struct clk_hw*[]) {
1293				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1294			},
1295			.num_parents = 1,
1296			.flags = CLK_SET_RATE_PARENT,
1297			.ops = &clk_branch2_ops,
1298		},
1299	},
1300};
1301
1302static struct clk_branch gcc_nssnoc_atb_clk = {
1303	.halt_reg = 0x17014,
1304	.halt_check = BRANCH_HALT,
1305	.clkr = {
1306		.enable_reg = 0x17014,
1307		.enable_mask = BIT(0),
1308		.hw.init = &(const struct clk_init_data) {
1309			.name = "gcc_nssnoc_atb_clk",
1310			.parent_hws = (const struct clk_hw*[]) {
1311				&gcc_qdss_at_clk_src.clkr.hw,
1312			},
1313			.num_parents = 1,
1314			.flags = CLK_SET_RATE_PARENT,
1315			.ops = &clk_branch2_ops,
1316		},
1317	},
1318};
1319
1320static struct clk_branch gcc_nssnoc_nsscc_clk = {
1321	.halt_reg = 0x17030,
1322	.halt_check = BRANCH_HALT,
1323	.clkr = {
1324		.enable_reg = 0x17030,
1325		.enable_mask = BIT(0),
1326		.hw.init = &(const struct clk_init_data) {
1327			.name = "gcc_nssnoc_nsscc_clk",
1328			.parent_hws = (const struct clk_hw*[]) {
1329				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1330			},
1331			.num_parents = 1,
1332			.flags = CLK_SET_RATE_PARENT,
1333			.ops = &clk_branch2_ops,
1334		},
1335	},
1336};
1337
1338static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
1339	.halt_reg = 0x17080,
1340	.halt_check = BRANCH_HALT,
1341	.clkr = {
1342		.enable_reg = 0x17080,
1343		.enable_mask = BIT(0),
1344		.hw.init = &(const struct clk_init_data) {
1345			.name = "gcc_nssnoc_pcnoc_1_clk",
1346			.parent_hws = (const struct clk_hw*[]) {
1347				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1348			},
1349			.num_parents = 1,
1350			.flags = CLK_SET_RATE_PARENT,
1351			.ops = &clk_branch2_ops,
1352		},
1353	},
1354};
1355
1356static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
1357	.halt_reg = 0x1701c,
1358	.halt_check = BRANCH_HALT,
1359	.clkr = {
1360		.enable_reg = 0x1701c,
1361		.enable_mask = BIT(0),
1362		.hw.init = &(const struct clk_init_data) {
1363			.name = "gcc_nssnoc_qosgen_ref_clk",
1364			.parent_hws = (const struct clk_hw *[]) {
1365				&gcc_xo_div4_clk_src.hw
1366			},
1367			.num_parents = 1,
1368			.flags = CLK_SET_RATE_PARENT,
1369			.ops = &clk_branch2_ops,
1370		},
1371	},
1372};
1373
1374static struct clk_branch gcc_nssnoc_snoc_1_clk = {
1375	.halt_reg = 0x1707c,
1376	.halt_check = BRANCH_HALT,
1377	.clkr = {
1378		.enable_reg = 0x1707c,
1379		.enable_mask = BIT(0),
1380		.hw.init = &(const struct clk_init_data) {
1381			.name = "gcc_nssnoc_snoc_1_clk",
1382			.parent_hws = (const struct clk_hw*[]) {
1383				&gcc_system_noc_bfdcd_clk_src.clkr.hw
1384			},
1385			.num_parents = 1,
1386			.flags = CLK_SET_RATE_PARENT,
1387			.ops = &clk_branch2_ops,
1388		},
1389	},
1390};
1391
1392static struct clk_branch gcc_nssnoc_snoc_clk = {
1393	.halt_reg = 0x17028,
1394	.halt_check = BRANCH_HALT,
1395	.clkr = {
1396		.enable_reg = 0x17028,
1397		.enable_mask = BIT(0),
1398		.hw.init = &(const struct clk_init_data) {
1399			.name = "gcc_nssnoc_snoc_clk",
1400			.parent_hws = (const struct clk_hw*[]) {
1401				&gcc_system_noc_bfdcd_clk_src.clkr.hw
1402			},
1403			.num_parents = 1,
1404			.flags = CLK_SET_RATE_PARENT,
1405			.ops = &clk_branch2_ops,
1406		},
1407	},
1408};
1409
1410static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
1411	.halt_reg = 0x17020,
1412	.halt_check = BRANCH_HALT,
1413	.clkr = {
1414		.enable_reg = 0x17020,
1415		.enable_mask = BIT(0),
1416		.hw.init = &(const struct clk_init_data) {
1417			.name = "gcc_nssnoc_timeout_ref_clk",
1418			.parent_hws = (const struct clk_hw*[]) {
1419				&gcc_xo_div4_clk_src.hw,
1420			},
1421			.num_parents = 1,
1422			.flags = CLK_SET_RATE_PARENT,
1423			.ops = &clk_branch2_ops,
1424		},
1425	},
1426};
1427
1428static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
1429	.halt_reg = 0x17074,
1430	.halt_check = BRANCH_HALT,
1431	.clkr = {
1432		.enable_reg = 0x17074,
1433		.enable_mask = BIT(0),
1434		.hw.init = &(const struct clk_init_data) {
1435			.name = "gcc_nssnoc_xo_dcd_clk",
1436			.parent_hws = (const struct clk_hw*[]) {
1437				&gcc_xo_clk_src.clkr.hw,
1438			},
1439			.num_parents = 1,
1440			.flags = CLK_SET_RATE_PARENT,
1441			.ops = &clk_branch2_ops,
1442		},
1443	},
1444};
1445
1446static struct clk_branch gcc_pcie0_ahb_clk = {
1447	.halt_reg = 0x28030,
1448	.halt_check = BRANCH_HALT,
1449	.clkr = {
1450		.enable_reg = 0x28030,
1451		.enable_mask = BIT(0),
1452		.hw.init = &(const struct clk_init_data) {
1453			.name = "gcc_pcie0_ahb_clk",
1454			.parent_hws = (const struct clk_hw*[]) {
1455				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1456			},
1457			.num_parents = 1,
1458			.flags = CLK_SET_RATE_PARENT,
1459			.ops = &clk_branch2_ops,
1460		},
1461	},
1462};
1463
1464static struct clk_branch gcc_pcie0_aux_clk = {
1465	.halt_reg = 0x28070,
1466	.halt_check = BRANCH_HALT,
1467	.clkr = {
1468		.enable_reg = 0x28070,
1469		.enable_mask = BIT(0),
1470		.hw.init = &(const struct clk_init_data) {
1471			.name = "gcc_pcie0_aux_clk",
1472			.parent_hws = (const struct clk_hw*[]) {
1473				&gcc_pcie_aux_clk_src.clkr.hw,
1474			},
1475			.num_parents = 1,
1476			.flags = CLK_SET_RATE_PARENT,
1477			.ops = &clk_branch2_ops,
1478		},
1479	},
1480};
1481
1482static struct clk_branch gcc_pcie0_axi_m_clk = {
1483	.halt_reg = 0x28038,
1484	.halt_check = BRANCH_HALT,
1485	.clkr = {
1486		.enable_reg = 0x28038,
1487		.enable_mask = BIT(0),
1488		.hw.init = &(const struct clk_init_data) {
1489			.name = "gcc_pcie0_axi_m_clk",
1490			.parent_hws = (const struct clk_hw*[]) {
1491				&gcc_pcie0_axi_m_clk_src.clkr.hw,
1492			},
1493			.num_parents = 1,
1494			.flags = CLK_SET_RATE_PARENT,
1495			.ops = &clk_branch2_ops,
1496		},
1497	},
1498};
1499
1500static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = {
1501	.halt_reg = 0x2e07c,
1502	.halt_check = BRANCH_HALT,
1503	.clkr = {
1504		.enable_reg = 0x2e07c,
1505		.enable_mask = BIT(0),
1506		.hw.init = &(const struct clk_init_data) {
1507			.name = "gcc_anoc_pcie0_1lane_m_clk",
1508			.parent_hws = (const struct clk_hw*[]) {
1509				&gcc_pcie0_axi_m_clk_src.clkr.hw,
1510			},
1511			.num_parents = 1,
1512			.flags = CLK_SET_RATE_PARENT,
1513			.ops = &clk_branch2_ops,
1514		},
1515	},
1516};
1517
1518static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
1519	.halt_reg = 0x28048,
1520	.halt_check = BRANCH_HALT,
1521	.clkr = {
1522		.enable_reg = 0x28048,
1523		.enable_mask = BIT(0),
1524		.hw.init = &(const struct clk_init_data) {
1525			.name = "gcc_pcie0_axi_s_bridge_clk",
1526			.parent_hws = (const struct clk_hw*[]) {
1527				&gcc_pcie0_axi_s_clk_src.clkr.hw,
1528			},
1529			.num_parents = 1,
1530			.flags = CLK_SET_RATE_PARENT,
1531			.ops = &clk_branch2_ops,
1532		},
1533	},
1534};
1535
1536static struct clk_branch gcc_pcie0_axi_s_clk = {
1537	.halt_reg = 0x28040,
1538	.halt_check = BRANCH_HALT,
1539	.clkr = {
1540		.enable_reg = 0x28040,
1541		.enable_mask = BIT(0),
1542		.hw.init = &(const struct clk_init_data) {
1543			.name = "gcc_pcie0_axi_s_clk",
1544			.parent_hws = (const struct clk_hw*[]) {
1545				&gcc_pcie0_axi_s_clk_src.clkr.hw,
1546			},
1547			.num_parents = 1,
1548			.flags = CLK_SET_RATE_PARENT,
1549			.ops = &clk_branch2_ops,
1550		},
1551	},
1552};
1553
1554static struct clk_regmap_phy_mux gcc_pcie0_pipe_clk_src = {
1555	.reg = 0x28064,
1556	.clkr = {
1557		.hw.init = &(const struct clk_init_data) {
1558			.name = "pcie0_pipe_clk_src",
1559			.parent_data = &(const struct clk_parent_data) {
1560				.index = DT_PCIE30_PHY0_PIPE_CLK,
1561			},
1562			.num_parents = 1,
1563			.ops = &clk_regmap_phy_mux_ops,
1564		},
1565	},
1566};
1567
1568static struct clk_branch gcc_pcie0_pipe_clk = {
1569	.halt_reg = 0x28068,
1570	.halt_check = BRANCH_HALT_DELAY,
1571	.clkr = {
1572		.enable_reg = 0x28068,
1573		.enable_mask = BIT(0),
1574		.hw.init = &(const struct clk_init_data) {
1575			.name = "gcc_pcie0_pipe_clk",
1576			.parent_hws = (const struct clk_hw *[]) {
1577				&gcc_pcie0_pipe_clk_src.clkr.hw
1578			},
1579			.num_parents = 1,
1580			.flags = CLK_SET_RATE_PARENT,
1581			.ops = &clk_branch2_ops,
1582		},
1583	},
1584};
1585
1586static struct clk_branch gcc_pcie1_ahb_clk = {
1587	.halt_reg = 0x29030,
1588	.halt_check = BRANCH_HALT,
1589	.clkr = {
1590		.enable_reg = 0x29030,
1591		.enable_mask = BIT(0),
1592		.hw.init = &(const struct clk_init_data) {
1593			.name = "gcc_pcie1_ahb_clk",
1594			.parent_hws = (const struct clk_hw*[]) {
1595				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1596			},
1597			.num_parents = 1,
1598			.flags = CLK_SET_RATE_PARENT,
1599			.ops = &clk_branch2_ops,
1600		},
1601	},
1602};
1603
1604static struct clk_branch gcc_pcie1_aux_clk = {
1605	.halt_reg = 0x29074,
1606	.halt_check = BRANCH_HALT,
1607	.clkr = {
1608		.enable_reg = 0x29074,
1609		.enable_mask = BIT(0),
1610		.hw.init = &(const struct clk_init_data) {
1611			.name = "gcc_pcie1_aux_clk",
1612			.parent_hws = (const struct clk_hw*[]) {
1613				&gcc_pcie_aux_clk_src.clkr.hw,
1614			},
1615			.num_parents = 1,
1616			.flags = CLK_SET_RATE_PARENT,
1617			.ops = &clk_branch2_ops,
1618		},
1619	},
1620};
1621
1622static struct clk_branch gcc_pcie1_axi_m_clk = {
1623	.halt_reg = 0x29038,
1624	.halt_check = BRANCH_HALT,
1625	.clkr = {
1626		.enable_reg = 0x29038,
1627		.enable_mask = BIT(0),
1628		.hw.init = &(const struct clk_init_data) {
1629			.name = "gcc_pcie1_axi_m_clk",
1630			.parent_hws = (const struct clk_hw*[]) {
1631				&gcc_pcie1_axi_m_clk_src.clkr.hw,
1632			},
1633			.num_parents = 1,
1634			.flags = CLK_SET_RATE_PARENT,
1635			.ops = &clk_branch2_ops,
1636		},
1637	},
1638};
1639
1640static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = {
1641	.halt_reg = 0x2e084,
1642	.halt_check = BRANCH_HALT,
1643	.clkr = {
1644		.enable_reg = 0x2e084,
1645		.enable_mask = BIT(0),
1646		.hw.init = &(const struct clk_init_data) {
1647			.name = "gcc_anoc_pcie1_1lane_m_clk",
1648			.parent_hws = (const struct clk_hw*[]) {
1649				&gcc_pcie1_axi_m_clk_src.clkr.hw,
1650			},
1651			.num_parents = 1,
1652			.flags = CLK_SET_RATE_PARENT,
1653			.ops = &clk_branch2_ops,
1654		},
1655	},
1656};
1657
1658static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
1659	.halt_reg = 0x29048,
1660	.halt_check = BRANCH_HALT,
1661	.clkr = {
1662		.enable_reg = 0x29048,
1663		.enable_mask = BIT(0),
1664		.hw.init = &(const struct clk_init_data) {
1665			.name = "gcc_pcie1_axi_s_bridge_clk",
1666			.parent_hws = (const struct clk_hw*[]) {
1667				&gcc_pcie1_axi_s_clk_src.clkr.hw,
1668			},
1669			.num_parents = 1,
1670			.flags = CLK_SET_RATE_PARENT,
1671			.ops = &clk_branch2_ops,
1672		},
1673	},
1674};
1675
1676static struct clk_branch gcc_pcie1_axi_s_clk = {
1677	.halt_reg = 0x29040,
1678	.halt_check = BRANCH_HALT,
1679	.clkr = {
1680		.enable_reg = 0x29040,
1681		.enable_mask = BIT(0),
1682		.hw.init = &(const struct clk_init_data) {
1683			.name = "gcc_pcie1_axi_s_clk",
1684			.parent_hws = (const struct clk_hw*[]) {
1685				&gcc_pcie1_axi_s_clk_src.clkr.hw,
1686			},
1687			.num_parents = 1,
1688			.flags = CLK_SET_RATE_PARENT,
1689			.ops = &clk_branch2_ops,
1690		},
1691	},
1692};
1693
1694static struct clk_regmap_phy_mux gcc_pcie1_pipe_clk_src = {
1695	.reg = 0x29064,
1696	.clkr = {
1697		.hw.init = &(const struct clk_init_data) {
1698			.name = "pcie1_pipe_clk_src",
1699			.parent_data = &(const struct clk_parent_data) {
1700				.index = DT_PCIE30_PHY1_PIPE_CLK,
1701			},
1702			.num_parents = 1,
1703			.ops = &clk_regmap_phy_mux_ops,
1704		},
1705	},
1706};
1707
1708static struct clk_branch gcc_pcie1_pipe_clk = {
1709	.halt_reg = 0x29068,
1710	.halt_check = BRANCH_HALT_DELAY,
1711	.clkr = {
1712		.enable_reg = 0x29068,
1713		.enable_mask = BIT(0),
1714		.hw.init = &(const struct clk_init_data) {
1715			.name = "gcc_pcie1_pipe_clk",
1716			.parent_hws = (const struct clk_hw *[]) {
1717				&gcc_pcie1_pipe_clk_src.clkr.hw
1718			},
1719			.num_parents = 1,
1720			.flags = CLK_SET_RATE_PARENT,
1721
1722			.ops = &clk_branch2_ops,
1723		},
1724	},
1725};
1726
1727static struct clk_branch gcc_pcie2_ahb_clk = {
1728	.halt_reg = 0x2a030,
1729	.halt_check = BRANCH_HALT,
1730	.clkr = {
1731		.enable_reg = 0x2a030,
1732		.enable_mask = BIT(0),
1733		.hw.init = &(const struct clk_init_data) {
1734			.name = "gcc_pcie2_ahb_clk",
1735			.parent_hws = (const struct clk_hw*[]) {
1736				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1737			},
1738			.num_parents = 1,
1739			.flags = CLK_SET_RATE_PARENT,
1740			.ops = &clk_branch2_ops,
1741		},
1742	},
1743};
1744
1745static struct clk_branch gcc_pcie2_aux_clk = {
1746	.halt_reg = 0x2a078,
1747	.halt_check = BRANCH_HALT,
1748	.clkr = {
1749		.enable_reg = 0x2a078,
1750		.enable_mask = BIT(0),
1751		.hw.init = &(const struct clk_init_data) {
1752			.name = "gcc_pcie2_aux_clk",
1753			.parent_hws = (const struct clk_hw*[]) {
1754				&gcc_pcie_aux_clk_src.clkr.hw,
1755			},
1756			.num_parents = 1,
1757			.flags = CLK_SET_RATE_PARENT,
1758			.ops = &clk_branch2_ops,
1759		},
1760	},
1761};
1762
1763static struct clk_branch gcc_pcie2_axi_m_clk = {
1764	.halt_reg = 0x2a038,
1765	.halt_check = BRANCH_HALT,
1766	.clkr = {
1767		.enable_reg = 0x2a038,
1768		.enable_mask = BIT(0),
1769		.hw.init = &(const struct clk_init_data) {
1770			.name = "gcc_pcie2_axi_m_clk",
1771			.parent_hws = (const struct clk_hw*[]) {
1772				&gcc_pcie2_axi_m_clk_src.clkr.hw,
1773			},
1774			.num_parents = 1,
1775			.flags = CLK_SET_RATE_PARENT,
1776			.ops = &clk_branch2_ops,
1777		},
1778	},
1779};
1780
1781static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = {
1782	.halt_reg = 0x2e080,
1783	.halt_check = BRANCH_HALT,
1784	.clkr = {
1785		.enable_reg = 0x2e080,
1786		.enable_mask = BIT(0),
1787		.hw.init = &(const struct clk_init_data) {
1788			.name = "gcc_anoc_pcie2_2lane_m_clk",
1789			.parent_hws = (const struct clk_hw*[]) {
1790				&gcc_pcie2_axi_m_clk_src.clkr.hw,
1791			},
1792			.num_parents = 1,
1793			.flags = CLK_SET_RATE_PARENT,
1794			.ops = &clk_branch2_ops,
1795		},
1796	},
1797};
1798
1799static struct clk_branch gcc_pcie2_axi_s_bridge_clk = {
1800	.halt_reg = 0x2a048,
1801	.halt_check = BRANCH_HALT,
1802	.clkr = {
1803		.enable_reg = 0x2a048,
1804		.enable_mask = BIT(0),
1805		.hw.init = &(const struct clk_init_data) {
1806			.name = "gcc_pcie2_axi_s_bridge_clk",
1807			.parent_hws = (const struct clk_hw*[]) {
1808				&gcc_pcie2_axi_s_clk_src.clkr.hw,
1809			},
1810			.num_parents = 1,
1811			.flags = CLK_SET_RATE_PARENT,
1812			.ops = &clk_branch2_ops,
1813		},
1814	},
1815};
1816
1817static struct clk_branch gcc_pcie2_axi_s_clk = {
1818	.halt_reg = 0x2a040,
1819	.halt_check = BRANCH_HALT,
1820	.clkr = {
1821		.enable_reg = 0x2a040,
1822		.enable_mask = BIT(0),
1823		.hw.init = &(const struct clk_init_data) {
1824			.name = "gcc_pcie2_axi_s_clk",
1825			.parent_hws = (const struct clk_hw*[]) {
1826				&gcc_pcie2_axi_s_clk_src.clkr.hw,
1827			},
1828			.num_parents = 1,
1829			.flags = CLK_SET_RATE_PARENT,
1830			.ops = &clk_branch2_ops,
1831		},
1832	},
1833};
1834
1835static struct clk_regmap_phy_mux gcc_pcie2_pipe_clk_src = {
1836	.reg = 0x2a064,
1837	.clkr = {
1838		.hw.init = &(const struct clk_init_data) {
1839			.name = "pcie2_pipe_clk_src",
1840			.parent_data = &(const struct clk_parent_data) {
1841				.index = DT_PCIE30_PHY2_PIPE_CLK,
1842			},
1843			.num_parents = 1,
1844			.ops = &clk_regmap_phy_mux_ops,
1845		},
1846	},
1847};
1848
1849static struct clk_branch gcc_pcie2_pipe_clk = {
1850	.halt_reg = 0x2a068,
1851	.halt_check = BRANCH_HALT_DELAY,
1852	.clkr = {
1853		.enable_reg = 0x2a068,
1854		.enable_mask = BIT(0),
1855		.hw.init = &(const struct clk_init_data) {
1856			.name = "gcc_pcie2_pipe_clk",
1857			.parent_hws = (const struct clk_hw *[]) {
1858				&gcc_pcie2_pipe_clk_src.clkr.hw
1859			},
1860			.num_parents = 1,
1861			.flags = CLK_SET_RATE_PARENT,
1862			.ops = &clk_branch2_ops,
1863		},
1864	},
1865};
1866
1867static struct clk_branch gcc_pcie3_ahb_clk = {
1868	.halt_reg = 0x2b030,
1869	.halt_check = BRANCH_HALT,
1870	.clkr = {
1871		.enable_reg = 0x2b030,
1872		.enable_mask = BIT(0),
1873		.hw.init = &(const struct clk_init_data) {
1874			.name = "gcc_pcie3_ahb_clk",
1875			.parent_hws = (const struct clk_hw*[]) {
1876				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1877			},
1878			.num_parents = 1,
1879			.flags = CLK_SET_RATE_PARENT,
1880			.ops = &clk_branch2_ops,
1881		},
1882	},
1883};
1884
1885static struct clk_branch gcc_pcie3_aux_clk = {
1886	.halt_reg = 0x2b07c,
1887	.halt_check = BRANCH_HALT,
1888	.clkr = {
1889		.enable_reg = 0x2b07c,
1890		.enable_mask = BIT(0),
1891		.hw.init = &(const struct clk_init_data) {
1892			.name = "gcc_pcie3_aux_clk",
1893			.parent_hws = (const struct clk_hw*[]) {
1894				&gcc_pcie_aux_clk_src.clkr.hw,
1895			},
1896			.num_parents = 1,
1897			.flags = CLK_SET_RATE_PARENT,
1898			.ops = &clk_branch2_ops,
1899		},
1900	},
1901};
1902
1903static struct clk_branch gcc_pcie3_axi_m_clk = {
1904	.halt_reg = 0x2b038,
1905	.halt_check = BRANCH_HALT,
1906	.clkr = {
1907		.enable_reg = 0x2b038,
1908		.enable_mask = BIT(0),
1909		.hw.init = &(const struct clk_init_data) {
1910			.name = "gcc_pcie3_axi_m_clk",
1911			.parent_hws = (const struct clk_hw*[]) {
1912				&gcc_pcie3_axi_m_clk_src.clkr.hw,
1913			},
1914			.num_parents = 1,
1915			.flags = CLK_SET_RATE_PARENT,
1916			.ops = &clk_branch2_ops,
1917		},
1918	},
1919};
1920
1921static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = {
1922	.halt_reg = 0x2e090,
1923	.halt_check = BRANCH_HALT,
1924	.clkr = {
1925		.enable_reg = 0x2e090,
1926		.enable_mask = BIT(0),
1927		.hw.init = &(const struct clk_init_data) {
1928			.name = "gcc_anoc_pcie3_2lane_m_clk",
1929			.parent_hws = (const struct clk_hw*[]) {
1930				&gcc_pcie3_axi_m_clk_src.clkr.hw,
1931			},
1932			.num_parents = 1,
1933			.flags = CLK_SET_RATE_PARENT,
1934			.ops = &clk_branch2_ops,
1935		},
1936	},
1937};
1938
1939static struct clk_branch gcc_pcie3_axi_s_bridge_clk = {
1940	.halt_reg = 0x2b048,
1941	.halt_check = BRANCH_HALT,
1942	.clkr = {
1943		.enable_reg = 0x2b048,
1944		.enable_mask = BIT(0),
1945		.hw.init = &(const struct clk_init_data) {
1946			.name = "gcc_pcie3_axi_s_bridge_clk",
1947			.parent_hws = (const struct clk_hw*[]) {
1948				&gcc_pcie3_axi_s_clk_src.clkr.hw,
1949			},
1950			.num_parents = 1,
1951			.flags = CLK_SET_RATE_PARENT,
1952			.ops = &clk_branch2_ops,
1953		},
1954	},
1955};
1956
1957static struct clk_branch gcc_pcie3_axi_s_clk = {
1958	.halt_reg = 0x2b040,
1959	.halt_check = BRANCH_HALT,
1960	.clkr = {
1961		.enable_reg = 0x2b040,
1962		.enable_mask = BIT(0),
1963		.hw.init = &(const struct clk_init_data) {
1964			.name = "gcc_pcie3_axi_s_clk",
1965			.parent_hws = (const struct clk_hw*[]) {
1966				&gcc_pcie3_axi_s_clk_src.clkr.hw,
1967			},
1968			.num_parents = 1,
1969			.flags = CLK_SET_RATE_PARENT,
1970			.ops = &clk_branch2_ops,
1971		},
1972	},
1973};
1974
1975static struct clk_regmap_phy_mux gcc_pcie3_pipe_clk_src = {
1976	.reg = 0x2b064,
1977	.clkr = {
1978		.hw.init = &(const struct clk_init_data) {
1979			.name = "pcie3_pipe_clk_src",
1980			.parent_data = &(const struct clk_parent_data) {
1981				.index = DT_PCIE30_PHY3_PIPE_CLK,
1982			},
1983			.num_parents = 1,
1984			.ops = &clk_regmap_phy_mux_ops,
1985		},
1986	},
1987};
1988
1989static struct clk_branch gcc_pcie3_pipe_clk = {
1990	.halt_reg = 0x2b068,
1991	.halt_check = BRANCH_HALT_DELAY,
1992	.clkr = {
1993		.enable_reg = 0x2b068,
1994		.enable_mask = BIT(0),
1995		.hw.init = &(const struct clk_init_data) {
1996			.name = "gcc_pcie3_pipe_clk",
1997			.parent_hws = (const struct clk_hw *[]) {
1998				&gcc_pcie3_pipe_clk_src.clkr.hw
1999			},
2000			.num_parents = 1,
2001			.flags = CLK_SET_RATE_PARENT,
2002			.ops = &clk_branch2_ops,
2003		},
2004	},
2005};
2006
2007static struct clk_branch gcc_prng_ahb_clk = {
2008	.halt_reg = 0x13024,
2009	.halt_check = BRANCH_HALT_VOTED,
2010	.clkr = {
2011		.enable_reg = 0xb004,
2012		.enable_mask = BIT(10),
2013		.hw.init = &(const struct clk_init_data) {
2014			.name = "gcc_prng_ahb_clk",
2015			.parent_hws = (const struct clk_hw*[]) {
2016				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2017			},
2018			.num_parents = 1,
2019			.flags = CLK_SET_RATE_PARENT,
2020			.ops = &clk_branch2_ops,
2021		},
2022	},
2023};
2024
2025static struct clk_branch gcc_qupv3_ahb_mst_clk = {
2026	.halt_reg = 0x1014,
2027	.halt_check = BRANCH_HALT_VOTED,
2028	.clkr = {
2029		.enable_reg = 0xb004,
2030		.enable_mask = BIT(14),
2031		.hw.init = &(const struct clk_init_data) {
2032			.name = "gcc_qupv3_ahb_mst_clk",
2033			.parent_hws = (const struct clk_hw*[]) {
2034				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2035			},
2036			.num_parents = 1,
2037			.flags = CLK_SET_RATE_PARENT,
2038			.ops = &clk_branch2_ops,
2039		},
2040	},
2041};
2042
2043static struct clk_branch gcc_qupv3_ahb_slv_clk = {
2044	.halt_reg = 0x102c,
2045	.halt_check = BRANCH_HALT_VOTED,
2046	.clkr = {
2047		.enable_reg = 0xb004,
2048		.enable_mask = BIT(4),
2049		.hw.init = &(const struct clk_init_data) {
2050			.name = "gcc_qupv3_ahb_slv_clk",
2051			.parent_hws = (const struct clk_hw*[]) {
2052				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2053			},
2054			.num_parents = 1,
2055			.flags = CLK_SET_RATE_PARENT,
2056			.ops = &clk_branch2_ops,
2057		},
2058	},
2059};
2060
2061static struct clk_branch gcc_qupv3_i2c0_clk = {
2062	.halt_reg = 0x2024,
2063	.halt_check = BRANCH_HALT,
2064	.clkr = {
2065		.enable_reg = 0x2024,
2066		.enable_mask = BIT(0),
2067		.hw.init = &(const struct clk_init_data) {
2068			.name = "gcc_qupv3_i2c0_clk",
2069			.parent_hws = (const struct clk_hw*[]) {
2070				&gcc_qupv3_i2c0_div_clk_src.clkr.hw,
2071			},
2072			.num_parents = 1,
2073			.flags = CLK_SET_RATE_PARENT,
2074			.ops = &clk_branch2_ops,
2075		},
2076	},
2077};
2078
2079static struct clk_branch gcc_qupv3_i2c1_clk = {
2080	.halt_reg = 0x3024,
2081	.halt_check = BRANCH_HALT,
2082	.clkr = {
2083		.enable_reg = 0x3024,
2084		.enable_mask = BIT(0),
2085		.hw.init = &(const struct clk_init_data) {
2086			.name = "gcc_qupv3_i2c1_clk",
2087			.parent_hws = (const struct clk_hw*[]) {
2088				&gcc_qupv3_i2c1_div_clk_src.clkr.hw,
2089			},
2090			.num_parents = 1,
2091			.flags = CLK_SET_RATE_PARENT,
2092			.ops = &clk_branch2_ops,
2093		},
2094	},
2095};
2096
2097static struct clk_branch gcc_qupv3_spi0_clk = {
2098	.halt_reg = 0x4020,
2099	.halt_check = BRANCH_HALT,
2100	.clkr = {
2101		.enable_reg = 0x4020,
2102		.enable_mask = BIT(0),
2103		.hw.init = &(const struct clk_init_data) {
2104			.name = "gcc_qupv3_spi0_clk",
2105			.parent_hws = (const struct clk_hw*[]) {
2106				&gcc_qupv3_spi0_clk_src.clkr.hw,
2107			},
2108			.num_parents = 1,
2109			.flags = CLK_SET_RATE_PARENT,
2110			.ops = &clk_branch2_ops,
2111		},
2112	},
2113};
2114
2115static struct clk_branch gcc_qupv3_spi1_clk = {
2116	.halt_reg = 0x5020,
2117	.halt_check = BRANCH_HALT,
2118	.clkr = {
2119		.enable_reg = 0x5020,
2120		.enable_mask = BIT(0),
2121		.hw.init = &(const struct clk_init_data) {
2122			.name = "gcc_qupv3_spi1_clk",
2123			.parent_hws = (const struct clk_hw*[]) {
2124				&gcc_qupv3_spi1_clk_src.clkr.hw,
2125			},
2126			.num_parents = 1,
2127			.flags = CLK_SET_RATE_PARENT,
2128			.ops = &clk_branch2_ops,
2129		},
2130	},
2131};
2132
2133static struct clk_branch gcc_qupv3_uart0_clk = {
2134	.halt_reg = 0x2040,
2135	.halt_check = BRANCH_HALT,
2136	.clkr = {
2137		.enable_reg = 0x2040,
2138		.enable_mask = BIT(0),
2139		.hw.init = &(const struct clk_init_data) {
2140			.name = "gcc_qupv3_uart0_clk",
2141			.parent_hws = (const struct clk_hw*[]) {
2142				&gcc_qupv3_uart0_clk_src.clkr.hw,
2143			},
2144			.num_parents = 1,
2145			.flags = CLK_SET_RATE_PARENT,
2146			.ops = &clk_branch2_ops,
2147		},
2148	},
2149};
2150
2151static struct clk_branch gcc_qupv3_uart1_clk = {
2152	.halt_reg = 0x3040,
2153	.halt_check = BRANCH_HALT,
2154	.clkr = {
2155		.enable_reg = 0x3040,
2156		.enable_mask = BIT(0),
2157		.hw.init = &(const struct clk_init_data) {
2158			.name = "gcc_qupv3_uart1_clk",
2159			.parent_hws = (const struct clk_hw*[]) {
2160				&gcc_qupv3_uart1_clk_src.clkr.hw,
2161			},
2162			.num_parents = 1,
2163			.flags = CLK_SET_RATE_PARENT,
2164			.ops = &clk_branch2_ops,
2165		},
2166	},
2167};
2168
2169static struct clk_branch gcc_sdcc1_ahb_clk = {
2170	.halt_reg = 0x3303c,
2171	.halt_check = BRANCH_HALT,
2172	.clkr = {
2173		.enable_reg = 0x3303c,
2174		.enable_mask = BIT(0),
2175		.hw.init = &(const struct clk_init_data) {
2176			.name = "gcc_sdcc1_ahb_clk",
2177			.parent_hws = (const struct clk_hw*[]) {
2178				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2179			},
2180			.num_parents = 1,
2181			.flags = CLK_SET_RATE_PARENT,
2182			.ops = &clk_branch2_ops,
2183		},
2184	},
2185};
2186
2187static struct clk_branch gcc_sdcc1_apps_clk = {
2188	.halt_reg = 0x3302c,
2189	.halt_check = BRANCH_HALT,
2190	.clkr = {
2191		.enable_reg = 0x3302c,
2192		.enable_mask = BIT(0),
2193		.hw.init = &(const struct clk_init_data) {
2194			.name = "gcc_sdcc1_apps_clk",
2195			.parent_hws = (const struct clk_hw*[]) {
2196				&gcc_sdcc1_apps_clk_src.clkr.hw,
2197			},
2198			.num_parents = 1,
2199			.flags = CLK_SET_RATE_PARENT,
2200			.ops = &clk_branch2_ops,
2201		},
2202	},
2203};
2204
2205static struct clk_branch gcc_sdcc1_ice_core_clk = {
2206	.halt_reg = 0x33034,
2207	.halt_check = BRANCH_HALT,
2208	.clkr = {
2209		.enable_reg = 0x33034,
2210		.enable_mask = BIT(0),
2211		.hw.init = &(const struct clk_init_data) {
2212			.name = "gcc_sdcc1_ice_core_clk",
2213			.parent_hws = (const struct clk_hw*[]) {
2214				&gcc_sdcc1_ice_core_clk_src.clkr.hw,
2215			},
2216			.num_parents = 1,
2217			.flags = CLK_SET_RATE_PARENT,
2218			.ops = &clk_branch2_ops,
2219		},
2220	},
2221};
2222
2223static struct clk_branch gcc_uniphy0_ahb_clk = {
2224	.halt_reg = 0x1704c,
2225	.halt_check = BRANCH_HALT,
2226	.clkr = {
2227		.enable_reg = 0x1704c,
2228		.enable_mask = BIT(0),
2229		.hw.init = &(const struct clk_init_data) {
2230			.name = "gcc_uniphy0_ahb_clk",
2231			.parent_hws = (const struct clk_hw*[]) {
2232				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2233			},
2234			.num_parents = 1,
2235			.flags = CLK_SET_RATE_PARENT,
2236			.ops = &clk_branch2_ops,
2237		},
2238	},
2239};
2240
2241static struct clk_branch gcc_uniphy0_sys_clk = {
2242	.halt_reg = 0x17048,
2243	.halt_check = BRANCH_HALT_VOTED,
2244	.clkr = {
2245		.enable_reg = 0x17048,
2246		.enable_mask = BIT(0),
2247		.hw.init = &(const struct clk_init_data) {
2248			.name = "gcc_uniphy0_sys_clk",
2249			.parent_hws = (const struct clk_hw*[]) {
2250				&gcc_uniphy_sys_clk_src.clkr.hw,
2251			},
2252			.num_parents = 1,
2253			.flags = CLK_SET_RATE_PARENT,
2254			.ops = &clk_branch2_ops,
2255		},
2256	},
2257};
2258
2259static struct clk_branch gcc_uniphy1_ahb_clk = {
2260	.halt_reg = 0x1705c,
2261	.halt_check = BRANCH_HALT,
2262	.clkr = {
2263		.enable_reg = 0x1705c,
2264		.enable_mask = BIT(0),
2265		.hw.init = &(const struct clk_init_data) {
2266			.name = "gcc_uniphy1_ahb_clk",
2267			.parent_hws = (const struct clk_hw*[]) {
2268				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2269			},
2270			.num_parents = 1,
2271			.flags = CLK_SET_RATE_PARENT,
2272			.ops = &clk_branch2_ops,
2273		},
2274	},
2275};
2276
2277static struct clk_branch gcc_uniphy1_sys_clk = {
2278	.halt_reg = 0x17058,
2279	.halt_check = BRANCH_HALT_VOTED,
2280	.clkr = {
2281		.enable_reg = 0x17058,
2282		.enable_mask = BIT(0),
2283		.hw.init = &(const struct clk_init_data) {
2284			.name = "gcc_uniphy1_sys_clk",
2285			.parent_hws = (const struct clk_hw*[]) {
2286				&gcc_uniphy_sys_clk_src.clkr.hw,
2287			},
2288			.num_parents = 1,
2289			.flags = CLK_SET_RATE_PARENT,
2290			.ops = &clk_branch2_ops,
2291		},
2292	},
2293};
2294
2295static struct clk_branch gcc_uniphy2_ahb_clk = {
2296	.halt_reg = 0x1706c,
2297	.halt_check = BRANCH_HALT,
2298	.clkr = {
2299		.enable_reg = 0x1706c,
2300		.enable_mask = BIT(0),
2301		.hw.init = &(const struct clk_init_data) {
2302			.name = "gcc_uniphy2_ahb_clk",
2303			.parent_hws = (const struct clk_hw*[]) {
2304				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2305			},
2306			.num_parents = 1,
2307			.flags = CLK_SET_RATE_PARENT,
2308			.ops = &clk_branch2_ops,
2309		},
2310	},
2311};
2312
2313static struct clk_branch gcc_uniphy2_sys_clk = {
2314	.halt_reg = 0x17068,
2315	.halt_check = BRANCH_HALT_VOTED,
2316	.clkr = {
2317		.enable_reg = 0x17068,
2318		.enable_mask = BIT(0),
2319		.hw.init = &(const struct clk_init_data) {
2320			.name = "gcc_uniphy2_sys_clk",
2321			.parent_hws = (const struct clk_hw*[]) {
2322				&gcc_uniphy_sys_clk_src.clkr.hw,
2323			},
2324			.num_parents = 1,
2325			.flags = CLK_SET_RATE_PARENT,
2326			.ops = &clk_branch2_ops,
2327		},
2328	},
2329};
2330
2331static struct clk_branch gcc_usb0_aux_clk = {
2332	.halt_reg = 0x2c04c,
2333	.halt_check = BRANCH_HALT_VOTED,
2334	.clkr = {
2335		.enable_reg = 0x2c04c,
2336		.enable_mask = BIT(0),
2337		.hw.init = &(const struct clk_init_data) {
2338			.name = "gcc_usb0_aux_clk",
2339			.parent_hws = (const struct clk_hw*[]) {
2340				&gcc_usb0_aux_clk_src.clkr.hw,
2341			},
2342			.num_parents = 1,
2343			.flags = CLK_SET_RATE_PARENT,
2344			.ops = &clk_branch2_ops,
2345		},
2346	},
2347};
2348
2349static struct clk_branch gcc_usb0_master_clk = {
2350	.halt_reg = 0x2c044,
2351	.halt_check = BRANCH_HALT_VOTED,
2352	.clkr = {
2353		.enable_reg = 0x2c044,
2354		.enable_mask = BIT(0),
2355		.hw.init = &(const struct clk_init_data) {
2356			.name = "gcc_usb0_master_clk",
2357			.parent_hws = (const struct clk_hw*[]) {
2358				&gcc_usb0_master_clk_src.clkr.hw,
2359			},
2360			.num_parents = 1,
2361			.flags = CLK_SET_RATE_PARENT,
2362			.ops = &clk_branch2_ops,
2363		},
2364	},
2365};
2366
2367static struct clk_branch gcc_usb0_mock_utmi_clk = {
2368	.halt_reg = 0x2c050,
2369	.halt_check = BRANCH_HALT_VOTED,
2370	.clkr = {
2371		.enable_reg = 0x2c050,
2372		.enable_mask = BIT(0),
2373		.hw.init = &(const struct clk_init_data) {
2374			.name = "gcc_usb0_mock_utmi_clk",
2375			.parent_hws = (const struct clk_hw*[]) {
2376				&gcc_usb0_mock_utmi_div_clk_src.clkr.hw,
2377			},
2378			.num_parents = 1,
2379			.flags = CLK_SET_RATE_PARENT,
2380			.ops = &clk_branch2_ops,
2381		},
2382	},
2383};
2384
2385static struct clk_branch gcc_usb1_mock_utmi_clk = {
2386	.halt_reg = 0x3c024,
2387	.halt_check = BRANCH_HALT_VOTED,
2388	.clkr = {
2389		.enable_reg = 0x3c024,
2390		.enable_mask = BIT(0),
2391		.hw.init = &(const struct clk_init_data) {
2392			.name = "gcc_usb1_mock_utmi_clk",
2393			.parent_hws = (const struct clk_hw*[]) {
2394				&gcc_usb1_mock_utmi_div_clk_src.clkr.hw,
2395			},
2396			.num_parents = 1,
2397			.flags = CLK_SET_RATE_PARENT,
2398			.ops = &clk_branch2_ops,
2399		},
2400	},
2401};
2402
2403static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2404	.halt_reg = 0x2c05c,
2405	.halt_check = BRANCH_HALT_VOTED,
2406	.clkr = {
2407		.enable_reg = 0x2c05c,
2408		.enable_mask = BIT(0),
2409		.hw.init = &(const struct clk_init_data) {
2410			.name = "gcc_usb0_phy_cfg_ahb_clk",
2411			.parent_hws = (const struct clk_hw*[]) {
2412				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2413			},
2414			.num_parents = 1,
2415			.flags = CLK_SET_RATE_PARENT,
2416			.ops = &clk_branch2_ops,
2417		},
2418	},
2419};
2420
2421static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
2422	.halt_reg = 0x3c01c,
2423	.halt_check = BRANCH_HALT_VOTED,
2424	.clkr = {
2425		.enable_reg = 0x3c01c,
2426		.enable_mask = BIT(0),
2427		.hw.init = &(const struct clk_init_data) {
2428			.name = "gcc_usb1_phy_cfg_ahb_clk",
2429			.parent_hws = (const struct clk_hw*[]) {
2430				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2431			},
2432			.num_parents = 1,
2433			.flags = CLK_SET_RATE_PARENT,
2434			.ops = &clk_branch2_ops,
2435		},
2436	},
2437};
2438
2439static struct clk_branch gcc_usb1_master_clk = {
2440	.halt_reg = 0x3c028,
2441	.halt_check = BRANCH_HALT_VOTED,
2442	.clkr = {
2443		.enable_reg = 0x3c028,
2444		.enable_mask = BIT(0),
2445		.hw.init = &(const struct clk_init_data) {
2446			.name = "gcc_usb1_master_clk",
2447			.parent_hws = (const struct clk_hw*[]) {
2448				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2449			},
2450			.num_parents = 1,
2451			.flags = CLK_SET_RATE_PARENT,
2452			.ops = &clk_branch2_ops,
2453		},
2454	},
2455};
2456
2457static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
2458	.reg = 0x2c074,
2459	.clkr = {
2460		.hw.init = &(const struct clk_init_data) {
2461			.name = "gcc_usb0_pipe_clk_src",
2462			.parent_data = &(const struct clk_parent_data) {
2463				.index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
2464			},
2465			.num_parents = 1,
2466			.ops = &clk_regmap_phy_mux_ops,
2467		},
2468	},
2469};
2470
2471static struct clk_branch gcc_usb0_pipe_clk = {
2472	.halt_reg = 0x2c054,
2473	.halt_check = BRANCH_HALT_DELAY,
2474	.clkr = {
2475		.enable_reg = 0x2c054,
2476		.enable_mask = BIT(0),
2477		.hw.init = &(const struct clk_init_data) {
2478			.name = "gcc_usb0_pipe_clk",
2479			.parent_hws = (const struct clk_hw *[]) {
2480				&gcc_usb0_pipe_clk_src.clkr.hw
2481			},
2482			.num_parents = 1,
2483			.flags = CLK_SET_RATE_PARENT,
2484			.ops = &clk_branch2_ops,
2485		},
2486	},
2487};
2488
2489static struct clk_branch gcc_usb0_sleep_clk = {
2490	.halt_reg = 0x2c058,
2491	.halt_check = BRANCH_HALT_VOTED,
2492	.clkr = {
2493		.enable_reg = 0x2c058,
2494		.enable_mask = BIT(0),
2495		.hw.init = &(const struct clk_init_data) {
2496			.name = "gcc_usb0_sleep_clk",
2497			.parent_hws = (const struct clk_hw*[]) {
2498				&gcc_sleep_clk_src.clkr.hw,
2499			},
2500			.num_parents = 1,
2501			.flags = CLK_SET_RATE_PARENT,
2502			.ops = &clk_branch2_ops,
2503		},
2504	},
2505};
2506
2507static struct clk_branch gcc_usb1_sleep_clk = {
2508	.halt_reg = 0x3c020,
2509	.halt_check = BRANCH_HALT_VOTED,
2510	.clkr = {
2511		.enable_reg = 0x3c020,
2512		.enable_mask = BIT(0),
2513		.hw.init = &(const struct clk_init_data) {
2514			.name = "gcc_usb1_sleep_clk",
2515			.parent_hws = (const struct clk_hw*[]) {
2516				&gcc_sleep_clk_src.clkr.hw,
2517			},
2518			.num_parents = 1,
2519			.flags = CLK_SET_RATE_PARENT,
2520			.ops = &clk_branch2_ops,
2521		},
2522	},
2523};
2524
2525static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
2526	.halt_reg = 0x3a004,
2527	.halt_check = BRANCH_HALT,
2528	.clkr = {
2529		.enable_reg = 0x3a004,
2530		.enable_mask = BIT(0),
2531		.hw.init = &(const struct clk_init_data) {
2532			.name = "gcc_cmn_12gpll_ahb_clk",
2533			.parent_hws = (const struct clk_hw*[]) {
2534				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2535			},
2536			.num_parents = 1,
2537			.flags = CLK_SET_RATE_PARENT,
2538			.ops = &clk_branch2_ops,
2539		},
2540	},
2541};
2542
2543static struct clk_branch gcc_cmn_12gpll_sys_clk = {
2544	.halt_reg = 0x3a008,
2545	.halt_check = BRANCH_HALT,
2546	.clkr = {
2547		.enable_reg = 0x3a008,
2548		.enable_mask = BIT(0),
2549		.hw.init = &(const struct clk_init_data) {
2550			.name = "gcc_cmn_12gpll_sys_clk",
2551			.parent_hws = (const struct clk_hw*[]) {
2552				&gcc_uniphy_sys_clk_src.clkr.hw,
2553			},
2554			.num_parents = 1,
2555			.flags = CLK_SET_RATE_PARENT,
2556			.ops = &clk_branch2_ops,
2557		},
2558	},
2559};
2560
2561static struct clk_branch gcc_lpass_sway_clk = {
2562	.halt_reg = 0x27014,
2563	.halt_check = BRANCH_HALT,
2564	.clkr = {
2565		.enable_reg = 0x27014,
2566		.enable_mask = BIT(0),
2567		.hw.init = &(const struct clk_init_data) {
2568			.name = "gcc_lpass_sway_clk",
2569			.parent_hws = (const struct clk_hw*[]) {
2570				&gcc_lpass_sway_clk_src.clkr.hw,
2571			},
2572			.num_parents = 1,
2573			.flags = CLK_SET_RATE_PARENT,
2574			.ops = &clk_branch2_ops,
2575		},
2576	},
2577};
2578
2579static struct clk_branch gcc_cnoc_lpass_cfg_clk = {
2580	.halt_reg = 0x2e028,
2581	.halt_check = BRANCH_HALT,
2582	.clkr = {
2583		.enable_reg = 0x2e028,
2584		.enable_mask = BIT(0),
2585		.hw.init = &(const struct clk_init_data) {
2586			.name = "gcc_cnoc_lpass_cfg_clk",
2587			.parent_hws = (const struct clk_hw*[]) {
2588				&gcc_lpass_sway_clk_src.clkr.hw,
2589			},
2590			.num_parents = 1,
2591			.flags = CLK_SET_RATE_PARENT,
2592			.ops = &clk_branch2_ops,
2593		},
2594	},
2595};
2596
2597static struct clk_branch gcc_lpass_core_axim_clk = {
2598	.halt_reg = 0x27018,
2599	.halt_check = BRANCH_HALT_VOTED,
2600	.clkr = {
2601		.enable_reg = 0x27018,
2602		.enable_mask = BIT(0),
2603		.hw.init = &(const struct clk_init_data) {
2604			.name = "gcc_lpass_core_axim_clk",
2605			.parent_hws = (const struct clk_hw*[]) {
2606				&gcc_lpass_axim_clk_src.clkr.hw,
2607			},
2608			.num_parents = 1,
2609			.flags = CLK_SET_RATE_PARENT,
2610			.ops = &clk_branch2_ops,
2611		},
2612	},
2613};
2614
2615static struct clk_branch gcc_snoc_lpass_clk = {
2616	.halt_reg = 0x31020,
2617	.halt_check = BRANCH_HALT_VOTED,
2618	.clkr = {
2619		.enable_reg = 0x31020,
2620		.enable_mask = BIT(0),
2621		.hw.init = &(const struct clk_init_data) {
2622			.name = "gcc_snoc_lpass_clk",
2623			.parent_hws = (const struct clk_hw*[]) {
2624				&gcc_lpass_axim_clk_src.clkr.hw,
2625			},
2626			.num_parents = 1,
2627			.flags = CLK_SET_RATE_PARENT,
2628			.ops = &clk_branch2_ops,
2629		},
2630	},
2631};
2632
2633static struct clk_branch gcc_usb0_eud_at_clk = {
2634	.halt_reg = 0x30004,
2635	.halt_check = BRANCH_HALT_VOTED,
2636	.clkr = {
2637		.enable_reg = 0x30004,
2638		.enable_mask = BIT(0),
2639		.hw.init = &(const struct clk_init_data) {
2640			.name = "gcc_usb0_eud_at_clk",
2641			.parent_hws = (const struct clk_hw*[]) {
2642				&gcc_eud_at_div_clk_src.hw,
2643			},
2644			.num_parents = 1,
2645			.flags = CLK_SET_RATE_PARENT,
2646			.ops = &clk_branch2_ops,
2647		},
2648	},
2649};
2650
2651static struct clk_branch gcc_qpic_ahb_clk = {
2652	.halt_reg = 0x32010,
2653	.halt_check = BRANCH_HALT,
2654	.clkr = {
2655		.enable_reg = 0x32010,
2656		.enable_mask = BIT(0),
2657		.hw.init = &(const struct clk_init_data) {
2658			.name = "gcc_qpic_ahb_clk",
2659			.parent_hws = (const struct clk_hw*[]) {
2660				&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2661			},
2662			.num_parents = 1,
2663			.flags = CLK_SET_RATE_PARENT,
2664			.ops = &clk_branch2_ops,
2665		},
2666	},
2667};
2668
2669static struct clk_branch gcc_qpic_clk = {
2670	.halt_reg = 0x32028,
2671	.halt_check = BRANCH_HALT,
2672	.clkr = {
2673		.enable_reg = 0x32028,
2674		.enable_mask = BIT(0),
2675		.hw.init = &(const struct clk_init_data) {
2676			.name = "gcc_qpic_clk",
2677			.parent_hws = (const struct clk_hw*[]) {
2678				&gcc_qpic_clk_src.clkr.hw,
2679			},
2680			.num_parents = 1,
2681			.flags = CLK_SET_RATE_PARENT,
2682			.ops = &clk_branch2_ops,
2683		},
2684	},
2685};
2686
2687static struct clk_branch gcc_qpic_io_macro_clk = {
2688	.halt_reg = 0x3200c,
2689	.halt_check = BRANCH_HALT,
2690	.clkr = {
2691		.enable_reg = 0x3200c,
2692		.enable_mask = BIT(0),
2693		.hw.init = &(const struct clk_init_data) {
2694			.name = "gcc_qpic_io_macro_clk",
2695			.parent_hws = (const struct clk_hw*[]) {
2696				&gcc_qpic_io_macro_clk_src.clkr.hw,
2697			},
2698			.num_parents = 1,
2699			.flags = CLK_SET_RATE_PARENT,
2700			.ops = &clk_branch2_ops,
2701		},
2702	},
2703};
2704
2705static struct clk_branch gcc_qdss_dap_clk = {
2706	.halt_reg = 0x2d058,
2707	.clkr = {
2708		.enable_reg = 0x2d058,
2709		.enable_mask = BIT(0),
2710		.hw.init = &(const struct clk_init_data) {
2711			.name = "gcc_qdss_dap_clk",
2712			.parent_hws = (const struct clk_hw *[]) {
2713				&gcc_qdss_dap_sync_clk_src.hw
2714			},
2715			.num_parents = 1,
2716			.flags = CLK_SET_RATE_PARENT,
2717			.ops = &clk_branch2_ops,
2718		},
2719	},
2720};
2721
2722static struct clk_branch gcc_qdss_at_clk = {
2723	.halt_reg = 0x2d034,
2724	.clkr = {
2725		.enable_reg = 0x2d034,
2726		.enable_mask = BIT(0),
2727		.hw.init = &(const struct clk_init_data) {
2728			.name = "gcc_qdss_at_clk",
2729			.parent_hws = (const struct clk_hw *[]) {
2730				&gcc_qdss_at_clk_src.clkr.hw
2731			},
2732			.num_parents = 1,
2733			.flags = CLK_SET_RATE_PARENT,
2734			.ops = &clk_branch2_ops,
2735		},
2736	},
2737};
2738
2739static struct clk_branch gcc_pcie0_rchng_clk = {
2740	.halt_reg = 0x28028,
2741	.clkr = {
2742		.enable_reg = 0x28028,
2743		.enable_mask = BIT(1),
2744		.hw.init = &(const struct clk_init_data) {
2745			.name = "gcc_pcie0_rchng_clk",
2746			.parent_hws = (const struct clk_hw *[]) {
2747				&gcc_pcie0_rchng_clk_src.clkr.hw
2748			},
2749			.num_parents = 1,
2750			.flags = CLK_SET_RATE_PARENT,
2751			.ops = &clk_branch2_ops,
2752		},
2753	},
2754};
2755
2756static struct clk_branch gcc_pcie1_rchng_clk = {
2757	.halt_reg = 0x29028,
2758	.clkr = {
2759		.enable_reg = 0x29028,
2760		.enable_mask = BIT(1),
2761		.hw.init = &(const struct clk_init_data) {
2762			.name = "gcc_pcie1_rchng_clk",
2763			.parent_hws = (const struct clk_hw *[]) {
2764				&gcc_pcie1_rchng_clk_src.clkr.hw
2765			},
2766			.num_parents = 1,
2767			.flags = CLK_SET_RATE_PARENT,
2768			.ops = &clk_branch2_ops,
2769		},
2770	},
2771};
2772
2773static struct clk_branch gcc_pcie2_rchng_clk = {
2774	.halt_reg = 0x2a028,
2775	.clkr = {
2776		.enable_reg = 0x2a028,
2777		.enable_mask = BIT(1),
2778		.hw.init = &(const struct clk_init_data) {
2779			.name = "gcc_pcie2_rchng_clk",
2780			.parent_hws = (const struct clk_hw *[]) {
2781				&gcc_pcie2_rchng_clk_src.clkr.hw
2782			},
2783			.num_parents = 1,
2784			.flags = CLK_SET_RATE_PARENT,
2785			.ops = &clk_branch2_ops,
2786		},
2787	},
2788};
2789
2790static struct clk_branch gcc_pcie3_rchng_clk = {
2791	.halt_reg = 0x2b028,
2792	.clkr = {
2793		.enable_reg = 0x2b028,
2794		.enable_mask = BIT(1),
2795		.hw.init = &(const struct clk_init_data) {
2796			.name = "gcc_pcie3_rchng_clk",
2797			.parent_hws = (const struct clk_hw *[]) {
2798				&gcc_pcie3_rchng_clk_src.clkr.hw
2799			},
2800			.num_parents = 1,
2801			.flags = CLK_SET_RATE_PARENT,
2802			.ops = &clk_branch2_ops,
2803		},
2804	},
2805};
2806
2807static struct clk_regmap *gcc_ipq5424_clocks[] = {
2808	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
2809	[GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
2810	[GCC_CNOC_PCIE0_1LANE_S_CLK] = &gcc_cnoc_pcie0_1lane_s_clk.clkr,
2811	[GCC_CNOC_PCIE1_1LANE_S_CLK] = &gcc_cnoc_pcie1_1lane_s_clk.clkr,
2812	[GCC_CNOC_PCIE2_2LANE_S_CLK] = &gcc_cnoc_pcie2_2lane_s_clk.clkr,
2813	[GCC_CNOC_PCIE3_2LANE_S_CLK] = &gcc_cnoc_pcie3_2lane_s_clk.clkr,
2814	[GCC_CNOC_USB_CLK] = &gcc_cnoc_usb_clk.clkr,
2815	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
2816	[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
2817	[GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,
2818	[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
2819	[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
2820	[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
2821	[GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
2822	[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
2823	[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
2824	[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
2825	[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
2826	[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
2827	[GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
2828	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
2829	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
2830	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
2831	[GCC_PCIE0_AXI_M_CLK_SRC] = &gcc_pcie0_axi_m_clk_src.clkr,
2832	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
2833	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
2834	[GCC_PCIE0_AXI_S_CLK_SRC] = &gcc_pcie0_axi_s_clk_src.clkr,
2835	[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
2836	[GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,
2837	[GCC_PCIE0_PIPE_CLK_SRC] = &gcc_pcie0_pipe_clk_src.clkr,
2838	[GCC_PCIE0_RCHNG_CLK_SRC] = &gcc_pcie0_rchng_clk_src.clkr,
2839	[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
2840	[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
2841	[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
2842	[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
2843	[GCC_PCIE1_AXI_M_CLK_SRC] = &gcc_pcie1_axi_m_clk_src.clkr,
2844	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
2845	[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
2846	[GCC_PCIE1_AXI_S_CLK_SRC] = &gcc_pcie1_axi_s_clk_src.clkr,
2847	[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
2848	[GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr,
2849	[GCC_PCIE1_PIPE_CLK_SRC] = &gcc_pcie1_pipe_clk_src.clkr,
2850	[GCC_PCIE1_RCHNG_CLK_SRC] = &gcc_pcie1_rchng_clk_src.clkr,
2851	[GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
2852	[GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr,
2853	[GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr,
2854	[GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr,
2855	[GCC_PCIE2_AXI_M_CLK_SRC] = &gcc_pcie2_axi_m_clk_src.clkr,
2856	[GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr,
2857	[GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr,
2858	[GCC_PCIE2_AXI_S_CLK_SRC] = &gcc_pcie2_axi_s_clk_src.clkr,
2859	[GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
2860	[GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr,
2861	[GCC_PCIE2_PIPE_CLK_SRC] = &gcc_pcie2_pipe_clk_src.clkr,
2862	[GCC_PCIE2_RCHNG_CLK_SRC] = &gcc_pcie2_rchng_clk_src.clkr,
2863	[GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr,
2864	[GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr,
2865	[GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr,
2866	[GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr,
2867	[GCC_PCIE3_AXI_M_CLK_SRC] = &gcc_pcie3_axi_m_clk_src.clkr,
2868	[GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
2869	[GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
2870	[GCC_PCIE3_AXI_S_CLK_SRC] = &gcc_pcie3_axi_s_clk_src.clkr,
2871	[GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
2872	[GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr,
2873	[GCC_PCIE3_PIPE_CLK_SRC] = &gcc_pcie3_pipe_clk_src.clkr,
2874	[GCC_PCIE3_RCHNG_CLK_SRC] = &gcc_pcie3_rchng_clk_src.clkr,
2875	[GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr,
2876	[GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
2877	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2878	[GCC_QUPV3_AHB_MST_CLK] = &gcc_qupv3_ahb_mst_clk.clkr,
2879	[GCC_QUPV3_AHB_SLV_CLK] = &gcc_qupv3_ahb_slv_clk.clkr,
2880	[GCC_QUPV3_I2C0_CLK] = &gcc_qupv3_i2c0_clk.clkr,
2881	[GCC_QUPV3_I2C0_CLK_SRC] = &gcc_qupv3_i2c0_clk_src.clkr,
2882	[GCC_QUPV3_I2C0_DIV_CLK_SRC] = &gcc_qupv3_i2c0_div_clk_src.clkr,
2883	[GCC_QUPV3_I2C1_CLK] = &gcc_qupv3_i2c1_clk.clkr,
2884	[GCC_QUPV3_I2C1_CLK_SRC] = &gcc_qupv3_i2c1_clk_src.clkr,
2885	[GCC_QUPV3_I2C1_DIV_CLK_SRC] = &gcc_qupv3_i2c1_div_clk_src.clkr,
2886	[GCC_QUPV3_SPI0_CLK] = &gcc_qupv3_spi0_clk.clkr,
2887	[GCC_QUPV3_SPI0_CLK_SRC] = &gcc_qupv3_spi0_clk_src.clkr,
2888	[GCC_QUPV3_SPI1_CLK] = &gcc_qupv3_spi1_clk.clkr,
2889	[GCC_QUPV3_SPI1_CLK_SRC] = &gcc_qupv3_spi1_clk_src.clkr,
2890	[GCC_QUPV3_UART0_CLK] = &gcc_qupv3_uart0_clk.clkr,
2891	[GCC_QUPV3_UART0_CLK_SRC] = &gcc_qupv3_uart0_clk_src.clkr,
2892	[GCC_QUPV3_UART1_CLK] = &gcc_qupv3_uart1_clk.clkr,
2893	[GCC_QUPV3_UART1_CLK_SRC] = &gcc_qupv3_uart1_clk_src.clkr,
2894	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2895	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2896	[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2897	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2898	[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2899	[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
2900	[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
2901	[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
2902	[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
2903	[GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
2904	[GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
2905	[GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr,
2906	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
2907	[GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr,
2908	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
2909	[GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr,
2910	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
2911	[GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr,
2912	[GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr,
2913	[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
2914	[GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr,
2915	[GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
2916	[GCC_USB1_MOCK_UTMI_CLK_SRC] = &gcc_usb1_mock_utmi_clk_src.clkr,
2917	[GCC_USB1_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb1_mock_utmi_div_clk_src.clkr,
2918	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
2919	[GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
2920	[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
2921	[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
2922	[GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
2923	[GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
2924	[GCC_WCSS_AHB_CLK_SRC] = &gcc_wcss_ahb_clk_src.clkr,
2925	[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
2926	[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
2927	[GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
2928	[GCC_CNOC_LPASS_CFG_CLK] = &gcc_cnoc_lpass_cfg_clk.clkr,
2929	[GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
2930	[GCC_SNOC_LPASS_CLK] = &gcc_snoc_lpass_clk.clkr,
2931	[GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr,
2932	[GCC_QDSS_TSCTR_CLK_SRC] = &gcc_qdss_tsctr_clk_src.clkr,
2933	[GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr,
2934	[GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr,
2935	[GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,
2936	[GCC_LPASS_AXIM_CLK_SRC] = &gcc_lpass_axim_clk_src.clkr,
2937	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
2938	[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
2939	[GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr,
2940	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
2941	[GCC_QPIC_CLK_SRC] = &gcc_qpic_clk_src.clkr,
2942	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
2943	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
2944	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
2945	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
2946	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
2947	[GPLL0] = &gpll0.clkr,
2948	[GPLL2] = &gpll2.clkr,
2949	[GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
2950	[GPLL4] = &gpll4.clkr,
2951	[GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
2952};
2953
2954static const struct qcom_reset_map gcc_ipq5424_resets[] = {
2955	[GCC_QUPV3_BCR] = { 0x01000, 0 },
2956	[GCC_QUPV3_I2C0_BCR] = { 0x02000, 0 },
2957	[GCC_QUPV3_UART0_BCR] = { 0x02020, 0 },
2958	[GCC_QUPV3_I2C1_BCR] = { 0x03000, 0 },
2959	[GCC_QUPV3_UART1_BCR] = { 0x03028, 0 },
2960	[GCC_QUPV3_SPI0_BCR] = { 0x04000, 0 },
2961	[GCC_QUPV3_SPI1_BCR] = { 0x05000, 0 },
2962	[GCC_IMEM_BCR] = { 0x0e000, 0 },
2963	[GCC_TME_BCR] = { 0x100000, 0 },
2964	[GCC_DDRSS_BCR] = { 0x11000, 0 },
2965	[GCC_PRNG_BCR] = { 0x13020, 0 },
2966	[GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
2967	[GCC_NSS_BCR] = { 0x17000, 0 },
2968	[GCC_MDIO_BCR] = { 0x1703c, 0 },
2969	[GCC_UNIPHY0_BCR] = { 0x17044, 0 },
2970	[GCC_UNIPHY1_BCR] = { 0x17054, 0 },
2971	[GCC_UNIPHY2_BCR] = { 0x17064, 0 },
2972	[GCC_WCSS_BCR] = { 0x18004, 0 },
2973	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
2974	[GCC_TME_SEC_BUS_BCR] = { 0xa1030, 0 },
2975	[GCC_ADSS_BCR] = { 0x1c000, 0 },
2976	[GCC_LPASS_BCR] = { 0x27000, 0 },
2977	[GCC_PCIE0_BCR] = { 0x28000, 0 },
2978	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
2979	[GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
2980	[GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
2981	[GCC_PCIE1_BCR] = { 0x29000, 0 },
2982	[GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
2983	[GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
2984	[GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
2985	[GCC_PCIE2_BCR] = { 0x2a000, 0 },
2986	[GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
2987	[GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
2988	[GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
2989	[GCC_PCIE3_BCR] = { 0x2b000, 0 },
2990	[GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
2991	[GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
2992	[GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 },
2993	[GCC_USB_BCR] = { 0x2c000, 0 },
2994	[GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
2995	[GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
2996	[GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
2997	[GCC_QDSS_BCR] = { 0x2d000, 0 },
2998	[GCC_SNOC_BCR] = { 0x2e000, 0 },
2999	[GCC_ANOC_BCR] = { 0x2e074, 0 },
3000	[GCC_PCNOC_BCR] = { 0x31000, 0 },
3001	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
3002	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
3003	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
3004	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
3005	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
3006	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
3007	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
3008	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
3009	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
3010	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
3011	[GCC_QPIC_BCR] = { 0x32000, 0 },
3012	[GCC_SDCC_BCR] = { 0x33000, 0 },
3013	[GCC_DCC_BCR] = { 0x35000, 0 },
3014	[GCC_SPDM_BCR] = { 0x36000, 0 },
3015	[GCC_MPM_BCR] = { 0x37000, 0 },
3016	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
3017	[GCC_RBCPR_BCR] = { 0x39000, 0 },
3018	[GCC_CMN_BLK_BCR] = { 0x3a000, 0 },
3019	[GCC_TCSR_BCR] = { 0x3d000, 0 },
3020	[GCC_TLMM_BCR] = { 0x3e000, 0 },
3021	[GCC_QUPV3_AHB_MST_ARES] = { 0x01014, 2 },
3022	[GCC_QUPV3_CORE_ARES] = { 0x01018, 2 },
3023	[GCC_QUPV3_2X_CORE_ARES] = { 0x01020, 2 },
3024	[GCC_QUPV3_SLEEP_ARES] = { 0x01028, 2 },
3025	[GCC_QUPV3_AHB_SLV_ARES] = { 0x0102c, 2 },
3026	[GCC_QUPV3_I2C0_ARES] = { 0x02024, 2 },
3027	[GCC_QUPV3_UART0_ARES] = { 0x02040, 2 },
3028	[GCC_QUPV3_I2C1_ARES] = { 0x03024, 2 },
3029	[GCC_QUPV3_UART1_ARES] = { 0x03040, 2 },
3030	[GCC_QUPV3_SPI0_ARES] = { 0x04020, 2 },
3031	[GCC_QUPV3_SPI1_ARES] = { 0x05020, 2 },
3032	[GCC_DEBUG_ARES] = { 0x06068, 2 },
3033	[GCC_GP1_ARES] = { 0x08018, 2 },
3034	[GCC_GP2_ARES] = { 0x09018, 2 },
3035	[GCC_GP3_ARES] = { 0x0a018, 2 },
3036	[GCC_IMEM_AXI_ARES] = { 0x0e004, 2 },
3037	[GCC_IMEM_CFG_AHB_ARES] = { 0x0e00c, 2 },
3038	[GCC_TME_ARES] = { 0x100b4, 2 },
3039	[GCC_TME_TS_ARES] = { 0x100c0, 2 },
3040	[GCC_TME_SLOW_ARES] = { 0x100d0, 2 },
3041	[GCC_TME_RTC_TOGGLE_ARES] = { 0x100d8, 2 },
3042	[GCC_TIC_ARES] = { 0x12004, 2 },
3043	[GCC_PRNG_AHB_ARES] = { 0x13024, 2 },
3044	[GCC_BOOT_ROM_AHB_ARES] = { 0x1302c, 2 },
3045	[GCC_NSSNOC_ATB_ARES] = { 0x17014, 2 },
3046	[GCC_NSS_TS_ARES] = { 0x17018, 2 },
3047	[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x1701c, 2 },
3048	[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17020, 2 },
3049	[GCC_NSSNOC_MEMNOC_ARES] = { 0x17024, 2 },
3050	[GCC_NSSNOC_SNOC_ARES] = { 0x17028, 2 },
3051	[GCC_NSSCFG_ARES] = { 0x1702c, 2 },
3052	[GCC_NSSNOC_NSSCC_ARES] = { 0x17030, 2 },
3053	[GCC_NSSCC_ARES] = { 0x17034, 2 },
3054	[GCC_MDIO_AHB_ARES] = { 0x17040, 2 },
3055	[GCC_UNIPHY0_SYS_ARES] = { 0x17048, 2 },
3056	[GCC_UNIPHY0_AHB_ARES] = { 0x1704c, 2 },
3057	[GCC_UNIPHY1_SYS_ARES] = { 0x17058, 2 },
3058	[GCC_UNIPHY1_AHB_ARES] = { 0x1705c, 2 },
3059	[GCC_UNIPHY2_SYS_ARES] = { 0x17068, 2 },
3060	[GCC_UNIPHY2_AHB_ARES] = { 0x1706c, 2 },
3061	[GCC_NSSNOC_XO_DCD_ARES] = { 0x17074, 2 },
3062	[GCC_NSSNOC_SNOC_1_ARES] = { 0x1707c, 2 },
3063	[GCC_NSSNOC_PCNOC_1_ARES] = { 0x17080, 2 },
3064	[GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17084, 2 },
3065	[GCC_DDRSS_ATB_ARES] = { 0x19004, 2 },
3066	[GCC_DDRSS_AHB_ARES] = { 0x19008, 2 },
3067	[GCC_GEMNOC_AHB_ARES] = { 0x1900c, 2 },
3068	[GCC_GEMNOC_Q6_AXI_ARES] = { 0x19010, 2 },
3069	[GCC_GEMNOC_NSSNOC_ARES] = { 0x19014, 2 },
3070	[GCC_GEMNOC_SNOC_ARES] = { 0x19018, 2 },
3071	[GCC_GEMNOC_APSS_ARES] = { 0x1901c, 2 },
3072	[GCC_GEMNOC_QOSGEN_EXTREF_ARES] = { 0x19024, 2 },
3073	[GCC_GEMNOC_TS_ARES] = { 0x19028, 2 },
3074	[GCC_DDRSS_SMS_SLOW_ARES] = { 0x1902c, 2 },
3075	[GCC_GEMNOC_CNOC_ARES] = { 0x19038, 2 },
3076	[GCC_GEMNOC_XO_DBG_ARES] = { 0x19040, 2 },
3077	[GCC_GEMNOC_ANOC_ARES] = { 0x19048, 2 },
3078	[GCC_DDRSS_LLCC_ATB_ARES] = { 0x1904c, 2 },
3079	[GCC_LLCC_TPDM_CFG_ARES] = { 0x19050, 2 },
3080	[GCC_TME_BUS_ARES] = { 0x1a014, 2 },
3081	[GCC_SEC_CTRL_ACC_ARES] = { 0x1a018, 2 },
3082	[GCC_SEC_CTRL_ARES] = { 0x1a020, 2 },
3083	[GCC_SEC_CTRL_SENSE_ARES] = { 0x1a028, 2 },
3084	[GCC_SEC_CTRL_AHB_ARES] = { 0x1a038, 2 },
3085	[GCC_SEC_CTRL_BOOT_ROM_PATCH_ARES] = { 0x1a03c, 2 },
3086	[GCC_ADSS_PWM_ARES] = { 0x1c00c, 2 },
3087	[GCC_TME_ATB_ARES] = { 0x1e030, 2 },
3088	[GCC_TME_DBGAPB_ARES] = { 0x1e034, 2 },
3089	[GCC_TME_DEBUG_ARES] = { 0x1e038, 2 },
3090	[GCC_TME_AT_ARES] = { 0x1e03C, 2 },
3091	[GCC_TME_APB_ARES] = { 0x1e040, 2 },
3092	[GCC_TME_DMI_DBG_HS_ARES] = { 0x1e044, 2 },
3093	[GCC_APSS_AHB_ARES] = { 0x24014, 2 },
3094	[GCC_APSS_AXI_ARES] = { 0x24018, 2 },
3095	[GCC_CPUSS_TRIG_ARES] = { 0x2401c, 2 },
3096	[GCC_APSS_DBG_ARES] = { 0x2402c, 2 },
3097	[GCC_APSS_TS_ARES] = { 0x24030, 2 },
3098	[GCC_APSS_ATB_ARES] = { 0x24034, 2 },
3099	[GCC_Q6_AXIM_ARES] = { 0x2500c, 2 },
3100	[GCC_Q6_AXIS_ARES] = { 0x25010, 2 },
3101	[GCC_Q6_AHB_ARES] = { 0x25014, 2 },
3102	[GCC_Q6_AHB_S_ARES] = { 0x25018, 2 },
3103	[GCC_Q6SS_ATBM_ARES] = { 0x2501c, 2 },
3104	[GCC_Q6_TSCTR_1TO2_ARES] = { 0x25020, 2 },
3105	[GCC_Q6SS_PCLKDBG_ARES] = { 0x25024, 2 },
3106	[GCC_Q6SS_TRIG_ARES] = { 0x25028, 2 },
3107	[GCC_Q6SS_BOOT_CBCR_ARES] = { 0x2502c, 2 },
3108	[GCC_WCSS_DBG_IFC_APB_ARES] = { 0x25038, 2 },
3109	[GCC_WCSS_DBG_IFC_ATB_ARES] = { 0x2503c, 2 },
3110	[GCC_WCSS_DBG_IFC_NTS_ARES] = { 0x25040, 2 },
3111	[GCC_WCSS_DBG_IFC_DAPBUS_ARES] = { 0x25044, 2 },
3112	[GCC_WCSS_DBG_IFC_APB_BDG_ARES] = { 0x25048, 2 },
3113	[GCC_WCSS_DBG_IFC_NTS_BDG_ARES] = { 0x25050, 2 },
3114	[GCC_WCSS_DBG_IFC_DAPBUS_BDG_ARES] = { 0x25054, 2 },
3115	[GCC_WCSS_ECAHB_ARES] = { 0x25058, 2 },
3116	[GCC_WCSS_ACMT_ARES] = { 0x2505c, 2 },
3117	[GCC_WCSS_AHB_S_ARES] = { 0x25060, 2 },
3118	[GCC_WCSS_AXI_M_ARES] = { 0x25064, 2 },
3119	[GCC_PCNOC_WAPSS_ARES] = { 0x25080, 2 },
3120	[GCC_SNOC_WAPSS_ARES] = { 0x25090, 2 },
3121	[GCC_LPASS_SWAY_ARES] = { 0x27014, 2 },
3122	[GCC_LPASS_CORE_AXIM_ARES] = { 0x27018, 2 },
3123	[GCC_PCIE0_AHB_ARES] = { 0x28030, 2 },
3124	[GCC_PCIE0_AXI_M_ARES] = { 0x28038, 2 },
3125	[GCC_PCIE0_AXI_S_ARES] = { 0x28040, 2 },
3126	[GCC_PCIE0_AXI_S_BRIDGE_ARES] = { 0x28048, 2},
3127	[GCC_PCIE0_PIPE_ARES] = { 0x28068, 2},
3128	[GCC_PCIE0_AUX_ARES] = { 0x28070, 2 },
3129	[GCC_PCIE1_AHB_ARES] = { 0x29030, 2 },
3130	[GCC_PCIE1_AXI_M_ARES] = { 0x29038, 2 },
3131	[GCC_PCIE1_AXI_S_ARES] = { 0x29040, 2 },
3132	[GCC_PCIE1_AXI_S_BRIDGE_ARES] = { 0x29048, 2 },
3133	[GCC_PCIE1_PIPE_ARES] = { 0x29068, 2 },
3134	[GCC_PCIE1_AUX_ARES] = { 0x29074, 2 },
3135	[GCC_PCIE2_AHB_ARES] = { 0x2a030, 2 },
3136	[GCC_PCIE2_AXI_M_ARES] = { 0x2a038, 2 },
3137	[GCC_PCIE2_AXI_S_ARES] = { 0x2a040, 2 },
3138	[GCC_PCIE2_AXI_S_BRIDGE_ARES] = { 0x2a048, 2 },
3139	[GCC_PCIE2_PIPE_ARES] = { 0x2a068, 2 },
3140	[GCC_PCIE2_AUX_ARES] = { 0x2a078, 2 },
3141	[GCC_PCIE3_AHB_ARES] = { 0x2b030, 2 },
3142	[GCC_PCIE3_AXI_M_ARES] = { 0x2b038, 2 },
3143	[GCC_PCIE3_AXI_S_ARES] = { 0x2b040, 2 },
3144	[GCC_PCIE3_AXI_S_BRIDGE_ARES] = { 0x2b048, 2 },
3145	[GCC_PCIE3_PIPE_ARES] = { 0x2b068, 2 },
3146	[GCC_PCIE3_AUX_ARES] = { 0x2b07C, 2 },
3147	[GCC_USB0_MASTER_ARES] = { 0x2c044, 2 },
3148	[GCC_USB0_AUX_ARES] = { 0x2c04c, 2 },
3149	[GCC_USB0_MOCK_UTMI_ARES] = { 0x2c050, 2 },
3150	[GCC_USB0_PIPE_ARES] = { 0x2c054, 2 },
3151	[GCC_USB0_SLEEP_ARES] = { 0x2c058, 2 },
3152	[GCC_USB0_PHY_CFG_AHB_ARES] = { 0x2c05c, 2 },
3153	[GCC_QDSS_AT_ARES] = { 0x2d034, 2 },
3154	[GCC_QDSS_STM_ARES] = { 0x2d03C, 2 },
3155	[GCC_QDSS_TRACECLKIN_ARES] = { 0x2d040, 2 },
3156	[GCC_QDSS_TSCTR_DIV2_ARES] = { 0x2d044, 2 },
3157	[GCC_QDSS_TSCTR_DIV3_ARES] = { 0x2d048, 2 },
3158	[GCC_QDSS_TSCTR_DIV4_ARES] = { 0x2d04c, 2 },
3159	[GCC_QDSS_TSCTR_DIV8_ARES] = { 0x2d050, 2 },
3160	[GCC_QDSS_TSCTR_DIV16_ARES] = { 0x2d054, 2 },
3161	[GCC_QDSS_DAP_ARES] = { 0x2d058, 2 },
3162	[GCC_QDSS_APB2JTAG_ARES] = { 0x2d05c, 2 },
3163	[GCC_QDSS_ETR_USB_ARES] = { 0x2d060, 2 },
3164	[GCC_QDSS_DAP_AHB_ARES] = { 0x2d064, 2 },
3165	[GCC_QDSS_CFG_AHB_ARES] = { 0x2d068, 2 },
3166	[GCC_QDSS_EUD_AT_ARES] = { 0x2d06c, 2 },
3167	[GCC_QDSS_TS_ARES] = { 0x2d078, 2 },
3168	[GCC_QDSS_USB_ARES] = { 0x2d07c, 2 },
3169	[GCC_SYS_NOC_AXI_ARES] = { 0x2e01c, 2 },
3170	[GCC_SNOC_QOSGEN_EXTREF_ARES] = { 0x2e020, 2 },
3171	[GCC_CNOC_LPASS_CFG_ARES] = { 0x2e028, 2 },
3172	[GCC_SYS_NOC_AT_ARES] = { 0x2e038, 2 },
3173	[GCC_SNOC_PCNOC_AHB_ARES] = { 0x2e03c, 2 },
3174	[GCC_SNOC_TME_ARES] = { 0x2e05c, 2 },
3175	[GCC_SNOC_XO_DCD_ARES] = { 0x2e060, 2 },
3176	[GCC_SNOC_TS_ARES] = { 0x2e068, 2 },
3177	[GCC_ANOC0_AXI_ARES] = { 0x2e078, 2 },
3178	[GCC_ANOC_PCIE0_1LANE_M_ARES] = { 0x2e07c, 2 },
3179	[GCC_ANOC_PCIE2_2LANE_M_ARES] = { 0x2e080, 2 },
3180	[GCC_ANOC_PCIE1_1LANE_M_ARES] = { 0x2e084, 2 },
3181	[GCC_ANOC_PCIE3_2LANE_M_ARES] = { 0x2e090, 2 },
3182	[GCC_ANOC_PCNOC_AHB_ARES] = { 0x2e094, 2 },
3183	[GCC_ANOC_QOSGEN_EXTREF_ARES] = { 0x2e098, 2 },
3184	[GCC_ANOC_XO_DCD_ARES] = { 0x2e09C, 2 },
3185	[GCC_SNOC_XO_DBG_ARES] = { 0x2e0a0, 2 },
3186	[GCC_AGGRNOC_ATB_ARES] = { 0x2e0ac, 2 },
3187	[GCC_AGGRNOC_TS_ARES] = { 0x2e0b0, 2 },
3188	[GCC_USB0_EUD_AT_ARES] = { 0x30004, 2 },
3189	[GCC_PCNOC_TIC_ARES] = { 0x31014, 2 },
3190	[GCC_PCNOC_AHB_ARES] = { 0x31018, 2 },
3191	[GCC_PCNOC_XO_DBG_ARES] = { 0x3101c, 2 },
3192	[GCC_SNOC_LPASS_ARES] = { 0x31020, 2 },
3193	[GCC_PCNOC_AT_ARES] = { 0x31024, 2 },
3194	[GCC_PCNOC_XO_DCD_ARES] = { 0x31028, 2 },
3195	[GCC_PCNOC_TS_ARES] = { 0x3102c, 2 },
3196	[GCC_PCNOC_BUS_TIMEOUT0_AHB_ARES] = { 0x31034, 2 },
3197	[GCC_PCNOC_BUS_TIMEOUT1_AHB_ARES] = { 0x3103c, 2 },
3198	[GCC_PCNOC_BUS_TIMEOUT2_AHB_ARES] = { 0x31044, 2 },
3199	[GCC_PCNOC_BUS_TIMEOUT3_AHB_ARES] = { 0x3104c, 2 },
3200	[GCC_PCNOC_BUS_TIMEOUT4_AHB_ARES] = { 0x31054, 2 },
3201	[GCC_PCNOC_BUS_TIMEOUT5_AHB_ARES] = { 0x3105c, 2 },
3202	[GCC_PCNOC_BUS_TIMEOUT6_AHB_ARES] = { 0x31064, 2 },
3203	[GCC_PCNOC_BUS_TIMEOUT7_AHB_ARES] = { 0x3106c, 2 },
3204	[GCC_Q6_AXIM_RESET] = { 0x2506c, 0 },
3205	[GCC_Q6_AXIS_RESET] = { 0x2506c, 1 },
3206	[GCC_Q6_AHB_S_RESET] = { 0x2506c, 2 },
3207	[GCC_Q6_AHB_RESET] = { 0x2506c, 3 },
3208	[GCC_Q6SS_DBG_RESET] = { 0x2506c, 4 },
3209	[GCC_WCSS_ECAHB_RESET] = { 0x25070, 0 },
3210	[GCC_WCSS_DBG_BDG_RESET] = { 0x25070, 1 },
3211	[GCC_WCSS_DBG_RESET] = { 0x25070, 2 },
3212	[GCC_WCSS_AXI_M_RESET] = { 0x25070, 3 },
3213	[GCC_WCSS_AHB_S_RESET] = { 0x25070, 4 },
3214	[GCC_WCSS_ACMT_RESET] = { 0x25070, 5 },
3215	[GCC_WCSSAON_RESET] = { 0x25074, 0 },
3216	[GCC_PCIE0_PIPE_RESET] = { 0x28058, 0 },
3217	[GCC_PCIE0_CORE_STICKY_RESET] = { 0x28058, 1 },
3218	[GCC_PCIE0_AXI_S_STICKY_RESET] = { 0x28058, 2 },
3219	[GCC_PCIE0_AXI_S_RESET] = { 0x28058, 3 },
3220	[GCC_PCIE0_AXI_M_STICKY_RESET] = { 0x28058, 4 },
3221	[GCC_PCIE0_AXI_M_RESET] = { 0x28058, 5 },
3222	[GCC_PCIE0_AUX_RESET] = { 0x28058, 6 },
3223	[GCC_PCIE0_AHB_RESET] = { 0x28058, 7 },
3224	[GCC_PCIE1_PIPE_RESET] = { 0x29058, 0 },
3225	[GCC_PCIE1_CORE_STICKY_RESET] = { 0x29058, 1 },
3226	[GCC_PCIE1_AXI_S_STICKY_RESET] = { 0x29058, 2 },
3227	[GCC_PCIE1_AXI_S_RESET] = { 0x29058, 3 },
3228	[GCC_PCIE1_AXI_M_STICKY_RESET] = { 0x29058, 4 },
3229	[GCC_PCIE1_AXI_M_RESET] = { 0x29058, 5 },
3230	[GCC_PCIE1_AUX_RESET] = { 0x29058, 6 },
3231	[GCC_PCIE1_AHB_RESET] = { 0x29058, 7 },
3232	[GCC_PCIE2_PIPE_RESET] = { 0x2a058, 0 },
3233	[GCC_PCIE2_CORE_STICKY_RESET] = { 0x2a058, 1 },
3234	[GCC_PCIE2_AXI_S_STICKY_RESET] = { 0x2a058, 2 },
3235	[GCC_PCIE2_AXI_S_RESET] = { 0x2a058, 3 },
3236	[GCC_PCIE2_AXI_M_STICKY_RESET] = { 0x2a058, 4 },
3237	[GCC_PCIE2_AXI_M_RESET] = { 0x2a058, 5 },
3238	[GCC_PCIE2_AUX_RESET] = { 0x2a058, 6 },
3239	[GCC_PCIE2_AHB_RESET] = { 0x2a058, 7 },
3240	[GCC_PCIE3_PIPE_RESET] = { 0x2b058, 0 },
3241	[GCC_PCIE3_CORE_STICKY_RESET] = { 0x2b058, 1 },
3242	[GCC_PCIE3_AXI_S_STICKY_RESET] = { 0x2b058, 2 },
3243	[GCC_PCIE3_AXI_S_RESET] = { 0x2b058, 3 },
3244	[GCC_PCIE3_AXI_M_STICKY_RESET] = { 0x2b058, 4 },
3245	[GCC_PCIE3_AXI_M_RESET] = { 0x2b058, 5 },
3246	[GCC_PCIE3_AUX_RESET] = { 0x2b058, 6 },
3247	[GCC_PCIE3_AHB_RESET] = { 0x2b058, 7 },
3248	[GCC_NSS_PARTIAL_RESET] = { 0x17078, 0 },
3249	[GCC_UNIPHY0_XPCS_ARES] = { 0x17050, 2 },
3250	[GCC_UNIPHY1_XPCS_ARES] = { 0x17060, 2 },
3251	[GCC_UNIPHY2_XPCS_ARES] = { 0x17070, 2 },
3252	[GCC_USB1_BCR] = { 0x3C000, 0 },
3253	[GCC_QUSB2_1_PHY_BCR] = { 0x3C030, 0 },
3254};
3255
3256#define IPQ_APPS_ID			5424	/* some unique value */
3257
3258static const struct qcom_icc_hws_data icc_ipq5424_hws[] = {
3259	{ MASTER_ANOC_PCIE0, SLAVE_ANOC_PCIE0, GCC_ANOC_PCIE0_1LANE_M_CLK },
3260	{ MASTER_CNOC_PCIE0, SLAVE_CNOC_PCIE0, GCC_CNOC_PCIE0_1LANE_S_CLK },
3261	{ MASTER_ANOC_PCIE1, SLAVE_ANOC_PCIE1, GCC_ANOC_PCIE1_1LANE_M_CLK },
3262	{ MASTER_CNOC_PCIE1, SLAVE_CNOC_PCIE1, GCC_CNOC_PCIE1_1LANE_S_CLK },
3263	{ MASTER_ANOC_PCIE2, SLAVE_ANOC_PCIE2, GCC_ANOC_PCIE2_2LANE_M_CLK },
3264	{ MASTER_CNOC_PCIE2, SLAVE_CNOC_PCIE2, GCC_CNOC_PCIE2_2LANE_S_CLK },
3265	{ MASTER_ANOC_PCIE3, SLAVE_ANOC_PCIE3, GCC_ANOC_PCIE3_2LANE_M_CLK },
3266	{ MASTER_CNOC_PCIE3, SLAVE_CNOC_PCIE3, GCC_CNOC_PCIE3_2LANE_S_CLK },
3267	{ MASTER_CNOC_USB, SLAVE_CNOC_USB, GCC_CNOC_USB_CLK },
3268	{ MASTER_NSSNOC_NSSCC, SLAVE_NSSNOC_NSSCC, GCC_NSSNOC_NSSCC_CLK },
3269	{ MASTER_NSSNOC_SNOC_0, SLAVE_NSSNOC_SNOC_0, GCC_NSSNOC_SNOC_CLK },
3270	{ MASTER_NSSNOC_SNOC_1, SLAVE_NSSNOC_SNOC_1, GCC_NSSNOC_SNOC_1_CLK },
3271	{ MASTER_NSSNOC_PCNOC_1, SLAVE_NSSNOC_PCNOC_1, GCC_NSSNOC_PCNOC_1_CLK },
3272	{ MASTER_NSSNOC_QOSGEN_REF, SLAVE_NSSNOC_QOSGEN_REF, GCC_NSSNOC_QOSGEN_REF_CLK },
3273	{ MASTER_NSSNOC_TIMEOUT_REF, SLAVE_NSSNOC_TIMEOUT_REF, GCC_NSSNOC_TIMEOUT_REF_CLK },
3274	{ MASTER_NSSNOC_XO_DCD, SLAVE_NSSNOC_XO_DCD, GCC_NSSNOC_XO_DCD_CLK },
3275	{ MASTER_NSSNOC_ATB, SLAVE_NSSNOC_ATB, GCC_NSSNOC_ATB_CLK },
3276	{ MASTER_CNOC_LPASS_CFG, SLAVE_CNOC_LPASS_CFG, GCC_CNOC_LPASS_CFG_CLK },
3277	{ MASTER_SNOC_LPASS, SLAVE_SNOC_LPASS, GCC_SNOC_LPASS_CLK },
3278};
3279
3280static const struct of_device_id gcc_ipq5424_match_table[] = {
3281	{ .compatible = "qcom,ipq5424-gcc" },
3282	{ }
3283};
3284MODULE_DEVICE_TABLE(of, gcc_ipq5424_match_table);
3285
3286static const struct regmap_config gcc_ipq5424_regmap_config = {
3287	.reg_bits       = 32,
3288	.reg_stride     = 4,
3289	.val_bits       = 32,
3290	.max_register   = 0x3f024,
3291	.fast_io	= true,
3292};
3293
3294static struct clk_hw *gcc_ipq5424_hws[] = {
3295	&gpll0_div2.hw,
3296	&gcc_xo_div4_clk_src.hw,
3297	&gcc_qdss_tsctr_div2_clk_src.hw,
3298	&gcc_qdss_dap_sync_clk_src.hw,
3299	&gcc_eud_at_div_clk_src.hw,
3300};
3301
3302static const struct qcom_cc_desc gcc_ipq5424_desc = {
3303	.config = &gcc_ipq5424_regmap_config,
3304	.clks = gcc_ipq5424_clocks,
3305	.num_clks = ARRAY_SIZE(gcc_ipq5424_clocks),
3306	.resets = gcc_ipq5424_resets,
3307	.num_resets = ARRAY_SIZE(gcc_ipq5424_resets),
3308	.clk_hws = gcc_ipq5424_hws,
3309	.num_clk_hws = ARRAY_SIZE(gcc_ipq5424_hws),
3310	.icc_hws = icc_ipq5424_hws,
3311	.num_icc_hws = ARRAY_SIZE(icc_ipq5424_hws),
3312	.icc_first_node_id = IPQ_APPS_ID,
3313};
3314
3315static int gcc_ipq5424_probe(struct platform_device *pdev)
3316{
3317	return qcom_cc_probe(pdev, &gcc_ipq5424_desc);
3318}
3319
3320static struct platform_driver gcc_ipq5424_driver = {
3321	.probe = gcc_ipq5424_probe,
3322	.driver = {
3323		.name   = "qcom,gcc-ipq5424",
3324		.of_match_table = gcc_ipq5424_match_table,
3325		.sync_state = icc_sync_state,
3326	},
3327};
3328
3329static int __init gcc_ipq5424_init(void)
3330{
3331	return platform_driver_register(&gcc_ipq5424_driver);
3332}
3333core_initcall(gcc_ipq5424_init);
3334
3335static void __exit gcc_ipq5424_exit(void)
3336{
3337	platform_driver_unregister(&gcc_ipq5424_driver);
3338}
3339module_exit(gcc_ipq5424_exit);
3340
3341MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5424 Driver");
3342MODULE_LICENSE("GPL");