gcc-ipq5018.c

   1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2/*
   3 * Copyright (c) 2023, The Linux Foundation. All rights reserved.
   4 */
   5#include <linux/clk-provider.h>
   6#include <linux/mod_devicetable.h>
   7#include <linux/module.h>
   8#include <linux/platform_device.h>
   9#include <linux/regmap.h>
  10
  11#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
  12#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
  13
  14#include "clk-alpha-pll.h"
  15#include "clk-branch.h"
  16#include "clk-rcg.h"
  17#include "clk-regmap.h"
  18#include "clk-regmap-divider.h"
  19#include "clk-regmap-mux.h"
  20#include "clk-regmap-phy-mux.h"
  21#include "reset.h"
  22
  23/* Need to match the order of clocks in DT binding */
  24enum {
  25	DT_XO,
  26	DT_SLEEP_CLK,
  27	DT_PCIE20_PHY0_PIPE_CLK,
  28	DT_PCIE20_PHY1_PIPE_CLK,
  29	DT_USB3_PHY0_CC_PIPE_CLK,
  30	DT_GEPHY_RX_CLK,
  31	DT_GEPHY_TX_CLK,
  32	DT_UNIPHY_RX_CLK,
  33	DT_UNIPHY_TX_CLK,
  34};
  35
  36enum {
  37	P_XO,
  38	P_CORE_PI_SLEEP_CLK,
  39	P_PCIE20_PHY0_PIPE,
  40	P_PCIE20_PHY1_PIPE,
  41	P_USB3PHY_0_PIPE,
  42	P_GEPHY_RX,
  43	P_GEPHY_TX,
  44	P_UNIPHY_RX,
  45	P_UNIPHY_TX,
  46	P_GPLL0,
  47	P_GPLL0_DIV2,
  48	P_GPLL2,
  49	P_GPLL4,
  50	P_UBI32_PLL,
  51};
  52
  53static const struct clk_parent_data gcc_xo_data[] = {
  54	{ .index = DT_XO },
  55};
  56
  57static const struct clk_parent_data gcc_sleep_clk_data[] = {
  58	{ .index = DT_SLEEP_CLK },
  59};
  60
  61static struct clk_alpha_pll gpll0_main = {
  62	.offset = 0x21000,
  63	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  64	.clkr = {
  65		.enable_reg = 0x0b000,
  66		.enable_mask = BIT(0),
  67		.hw.init = &(struct clk_init_data) {
  68			.name = "gpll0_main",
  69			.parent_data = gcc_xo_data,
  70			.num_parents = ARRAY_SIZE(gcc_xo_data),
  71			.ops = &clk_alpha_pll_stromer_ops,
  72		},
  73	},
  74};
  75
  76static struct clk_alpha_pll gpll2_main = {
  77	.offset = 0x4a000,
  78	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  79	.clkr = {
  80		.enable_reg = 0x0b000,
  81		.enable_mask = BIT(2),
  82		.hw.init = &(struct clk_init_data) {
  83			.name = "gpll2_main",
  84			.parent_data = gcc_xo_data,
  85			.num_parents = ARRAY_SIZE(gcc_xo_data),
  86			.ops = &clk_alpha_pll_stromer_ops,
  87		},
  88	},
  89};
  90
  91static struct clk_alpha_pll gpll4_main = {
  92	.offset = 0x24000,
  93	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  94	.clkr = {
  95		.enable_reg = 0x0b000,
  96		.enable_mask = BIT(5),
  97		.hw.init = &(struct clk_init_data) {
  98			.name = "gpll4_main",
  99			.parent_data = gcc_xo_data,
 100			.num_parents = ARRAY_SIZE(gcc_xo_data),
 101			.ops = &clk_alpha_pll_stromer_ops,
 102		},
 103	},
 104};
 105
 106static struct clk_alpha_pll ubi32_pll_main = {
 107	.offset = 0x25000,
 108	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 109	.clkr = {
 110		.enable_reg = 0x0b000,
 111		.enable_mask = BIT(6),
 112		.hw.init = &(struct clk_init_data) {
 113			.name = "ubi32_pll_main",
 114			.parent_data = gcc_xo_data,
 115			.num_parents = ARRAY_SIZE(gcc_xo_data),
 116			.ops = &clk_alpha_pll_stromer_ops,
 117		},
 118	},
 119};
 120
 121static struct clk_alpha_pll_postdiv gpll0 = {
 122	.offset = 0x21000,
 123	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 124	.width = 4,
 125	.clkr.hw.init = &(struct clk_init_data) {
 126		.name = "gpll0",
 127		.parent_hws = (const struct clk_hw *[]) {
 128			&gpll0_main.clkr.hw,
 129		},
 130		.num_parents = 1,
 131		.ops = &clk_alpha_pll_postdiv_ro_ops,
 132	},
 133};
 134
 135static struct clk_alpha_pll_postdiv gpll2 = {
 136	.offset = 0x4a000,
 137	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 138	.width = 4,
 139	.clkr.hw.init = &(struct clk_init_data) {
 140		.name = "gpll2",
 141		.parent_hws = (const struct clk_hw *[]) {
 142			&gpll2_main.clkr.hw,
 143		},
 144		.num_parents = 1,
 145		.ops = &clk_alpha_pll_postdiv_ro_ops,
 146	},
 147};
 148
 149static struct clk_alpha_pll_postdiv gpll4 = {
 150	.offset = 0x24000,
 151	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 152	.width = 4,
 153	.clkr.hw.init = &(struct clk_init_data) {
 154		.name = "gpll4",
 155		.parent_hws = (const struct clk_hw *[]) {
 156			&gpll4_main.clkr.hw,
 157		},
 158		.num_parents = 1,
 159		.ops = &clk_alpha_pll_postdiv_ro_ops,
 160	},
 161};
 162
 163static struct clk_alpha_pll_postdiv ubi32_pll = {
 164	.offset = 0x25000,
 165	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 166	.width = 4,
 167	.clkr.hw.init = &(struct clk_init_data) {
 168		.name = "ubi32_pll",
 169		.parent_hws = (const struct clk_hw *[]) {
 170			&ubi32_pll_main.clkr.hw,
 171		},
 172		.num_parents = 1,
 173		.ops = &clk_alpha_pll_postdiv_ro_ops,
 174		.flags = CLK_SET_RATE_PARENT,
 175	},
 176};
 177
 178static struct clk_fixed_factor gpll0_out_main_div2 = {
 179	.mult = 1,
 180	.div = 2,
 181	.hw.init = &(struct clk_init_data) {
 182		.name = "gpll0_out_main_div2",
 183		.parent_hws = (const struct clk_hw *[]) {
 184			&gpll0_main.clkr.hw,
 185		},
 186		.num_parents = 1,
 187		.ops = &clk_fixed_factor_ops,
 188		.flags = CLK_SET_RATE_PARENT,
 189	},
 190};
 191
 192static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
 193	{ .index = DT_XO },
 194	{ .hw = &gpll0.clkr.hw },
 195	{ .hw = &gpll0_out_main_div2.hw },
 196};
 197
 198static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
 199	{ P_XO, 0 },
 200	{ P_GPLL0, 1 },
 201	{ P_GPLL0_DIV2, 4 },
 202};
 203
 204static const struct clk_parent_data gcc_xo_gpll0[] = {
 205	{ .index = DT_XO },
 206	{ .hw = &gpll0.clkr.hw },
 207};
 208
 209static const struct parent_map gcc_xo_gpll0_map[] = {
 210	{ P_XO, 0 },
 211	{ P_GPLL0, 1 },
 212};
 213
 214static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
 215	{ .index = DT_XO },
 216	{ .hw = &gpll0_out_main_div2.hw },
 217	{ .hw = &gpll0.clkr.hw },
 218};
 219
 220static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 221	{ P_XO, 0 },
 222	{ P_GPLL0_DIV2, 2 },
 223	{ P_GPLL0, 1 },
 224};
 225
 226static const struct clk_parent_data gcc_xo_ubi32_gpll0[] = {
 227	{ .index = DT_XO },
 228	{ .hw = &ubi32_pll.clkr.hw },
 229	{ .hw = &gpll0.clkr.hw },
 230};
 231
 232static const struct parent_map gcc_xo_ubi32_gpll0_map[] = {
 233	{ P_XO, 0 },
 234	{ P_UBI32_PLL, 1 },
 235	{ P_GPLL0, 2 },
 236};
 237
 238static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
 239	{ .index = DT_XO },
 240	{ .hw = &gpll0.clkr.hw },
 241	{ .hw = &gpll2.clkr.hw },
 242};
 243
 244static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
 245	{ P_XO, 0 },
 246	{ P_GPLL0, 1 },
 247	{ P_GPLL2, 2 },
 248};
 249
 250static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4[] = {
 251	{ .index = DT_XO },
 252	{ .hw = &gpll0.clkr.hw },
 253	{ .hw = &gpll2.clkr.hw },
 254	{ .hw = &gpll4.clkr.hw },
 255};
 256
 257static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
 258	{ P_XO, 0 },
 259	{ P_GPLL0, 1 },
 260	{ P_GPLL2, 2 },
 261	{ P_GPLL4, 3 },
 262};
 263
 264static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
 265	{ .index = DT_XO },
 266	{ .hw = &gpll0.clkr.hw },
 267	{ .hw = &gpll4.clkr.hw },
 268};
 269
 270static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 271	{ P_XO, 0 },
 272	{ P_GPLL0, 1 },
 273	{ P_GPLL4, 2 },
 274};
 275
 276static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
 277	{ .index = DT_XO },
 278	{ .hw = &gpll0.clkr.hw },
 279	{ .index = DT_SLEEP_CLK },
 280};
 281
 282static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
 283	{ P_XO, 0 },
 284	{ P_GPLL0, 2 },
 285	{ P_CORE_PI_SLEEP_CLK, 6 },
 286};
 287
 288static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk[] = {
 289	{ .index = DT_XO },
 290	{ .hw = &gpll0.clkr.hw },
 291	{ .hw = &gpll0_out_main_div2.hw },
 292	{ .index = DT_SLEEP_CLK },
 293};
 294
 295static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map[] = {
 296	{ P_XO, 0 },
 297	{ P_GPLL0, 1 },
 298	{ P_GPLL0_DIV2, 4 },
 299	{ P_CORE_PI_SLEEP_CLK, 6 },
 300};
 301
 302static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
 303	{ .index = DT_XO },
 304	{ .hw = &gpll0.clkr.hw },
 305	{ .hw = &gpll2.clkr.hw },
 306	{ .hw = &gpll0_out_main_div2.hw },
 307};
 308
 309static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
 310	{ P_XO, 0 },
 311	{ P_GPLL0, 1 },
 312	{ P_GPLL2, 2 },
 313	{ P_GPLL0_DIV2, 4 },
 314};
 315
 316static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
 317	{ .index = DT_XO },
 318	{ .hw = &gpll4.clkr.hw },
 319	{ .hw = &gpll0.clkr.hw },
 320	{ .hw = &gpll0_out_main_div2.hw },
 321};
 322
 323static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1[] = {
 324	{ P_XO, 0 },
 325	{ P_GPLL4, 1 },
 326	{ P_GPLL0, 2 },
 327	{ P_GPLL0_DIV2, 4 },
 328};
 329
 330static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2[] = {
 331	{ P_XO, 0 },
 332	{ P_GPLL4, 1 },
 333	{ P_GPLL0, 3 },
 334	{ P_GPLL0_DIV2, 4 },
 335};
 336
 337static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = {
 338	{ .index = DT_XO },
 339	{ .index = DT_GEPHY_RX_CLK },
 340	{ .index = DT_GEPHY_TX_CLK },
 341	{ .hw = &ubi32_pll.clkr.hw },
 342	{ .hw = &gpll0.clkr.hw },
 343};
 344
 345static const struct parent_map gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map[] = {
 346	{ P_XO, 0 },
 347	{ P_GEPHY_RX, 1 },
 348	{ P_GEPHY_TX, 2 },
 349	{ P_UBI32_PLL, 3 },
 350	{ P_GPLL0, 4 },
 351};
 352
 353static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = {
 354	{ .index = DT_XO },
 355	{ .index = DT_GEPHY_TX_CLK },
 356	{ .index = DT_GEPHY_RX_CLK },
 357	{ .hw = &ubi32_pll.clkr.hw },
 358	{ .hw = &gpll0.clkr.hw },
 359};
 360
 361static const struct parent_map gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map[] = {
 362	{ P_XO, 0 },
 363	{ P_GEPHY_TX, 1 },
 364	{ P_GEPHY_RX, 2 },
 365	{ P_UBI32_PLL, 3 },
 366	{ P_GPLL0, 4 },
 367};
 368
 369static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
 370	{ .index = DT_XO },
 371	{ .index = DT_UNIPHY_RX_CLK },
 372	{ .index = DT_UNIPHY_TX_CLK },
 373	{ .hw = &ubi32_pll.clkr.hw },
 374	{ .hw = &gpll0.clkr.hw },
 375};
 376
 377static const struct parent_map gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map[] = {
 378	{ P_XO, 0 },
 379	{ P_UNIPHY_RX, 1 },
 380	{ P_UNIPHY_TX, 2 },
 381	{ P_UBI32_PLL, 3 },
 382	{ P_GPLL0, 4 },
 383};
 384
 385static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
 386	{ .index = DT_XO },
 387	{ .index = DT_UNIPHY_TX_CLK },
 388	{ .index = DT_UNIPHY_RX_CLK },
 389	{ .hw = &ubi32_pll.clkr.hw },
 390	{ .hw = &gpll0.clkr.hw },
 391};
 392
 393static const struct parent_map gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map[] = {
 394	{ P_XO, 0 },
 395	{ P_UNIPHY_TX, 1 },
 396	{ P_UNIPHY_RX, 2 },
 397	{ P_UBI32_PLL, 3 },
 398	{ P_GPLL0, 4 },
 399};
 400
 401static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
 402	{ .index = DT_PCIE20_PHY0_PIPE_CLK },
 403	{ .index = DT_XO },
 404};
 405
 406static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
 407	{ P_PCIE20_PHY0_PIPE, 0 },
 408	{ P_XO, 2 },
 409};
 410
 411static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
 412	{ .index = DT_PCIE20_PHY1_PIPE_CLK },
 413	{ .index = DT_XO },
 414};
 415
 416static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
 417	{ P_PCIE20_PHY1_PIPE, 0 },
 418	{ P_XO, 2 },
 419};
 420
 421static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
 422	{ .index = DT_USB3_PHY0_CC_PIPE_CLK },
 423	{ .index = DT_XO },
 424};
 425
 426static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
 427	{ P_USB3PHY_0_PIPE, 0 },
 428	{ P_XO, 2 },
 429};
 430
 431static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
 432	F(24000000, P_XO, 1, 0, 0),
 433	F(100000000, P_GPLL0, 8, 0, 0),
 434	{ }
 435};
 436
 437static struct clk_rcg2 adss_pwm_clk_src = {
 438	.cmd_rcgr = 0x1f008,
 439	.freq_tbl = ftbl_adss_pwm_clk_src,
 440	.hid_width = 5,
 441	.parent_map = gcc_xo_gpll0_map,
 442	.clkr.hw.init = &(struct clk_init_data) {
 443		.name = "adss_pwm_clk_src",
 444		.parent_data = gcc_xo_gpll0,
 445		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 446		.ops = &clk_rcg2_ops,
 447	},
 448};
 449
 450static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
 451	F(50000000, P_GPLL0, 16, 0, 0),
 452	{ }
 453};
 454
 455static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 456	.cmd_rcgr = 0x0200c,
 457	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 458	.hid_width = 5,
 459	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 460	.clkr.hw.init = &(struct clk_init_data) {
 461		.name = "blsp1_qup1_i2c_apps_clk_src",
 462		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 463		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 464		.ops = &clk_rcg2_ops,
 465	},
 466};
 467
 468static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 469	.cmd_rcgr = 0x03000,
 470	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 471	.hid_width = 5,
 472	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 473	.clkr.hw.init = &(struct clk_init_data) {
 474		.name = "blsp1_qup2_i2c_apps_clk_src",
 475		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 476		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 477		.ops = &clk_rcg2_ops,
 478	},
 479};
 480
 481static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 482	.cmd_rcgr = 0x04000,
 483	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 484	.hid_width = 5,
 485	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 486	.clkr.hw.init = &(struct clk_init_data) {
 487		.name = "blsp1_qup3_i2c_apps_clk_src",
 488		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 489		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 490		.ops = &clk_rcg2_ops,
 491	},
 492};
 493
 494static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
 495	F(960000, P_XO, 10, 2, 5),
 496	F(4800000, P_XO, 5, 0, 0),
 497	F(9600000, P_XO, 2, 4, 5),
 498	F(16000000, P_GPLL0, 10, 1, 5),
 499	F(24000000, P_XO, 1, 0, 0),
 500	F(50000000, P_GPLL0, 16, 0, 0),
 501	{ }
 502};
 503
 504static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 505	.cmd_rcgr = 0x02024,
 506	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 507	.mnd_width = 8,
 508	.hid_width = 5,
 509	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 510	.clkr.hw.init = &(struct clk_init_data) {
 511		.name = "blsp1_qup1_spi_apps_clk_src",
 512		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 513		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 514		.ops = &clk_rcg2_ops,
 515	},
 516};
 517
 518static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 519	.cmd_rcgr = 0x03014,
 520	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 521	.mnd_width = 8,
 522	.hid_width = 5,
 523	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 524	.clkr.hw.init = &(struct clk_init_data) {
 525		.name = "blsp1_qup2_spi_apps_clk_src",
 526		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 527		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 528		.ops = &clk_rcg2_ops,
 529	},
 530};
 531
 532static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 533	.cmd_rcgr = 0x04014,
 534	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 535	.mnd_width = 8,
 536	.hid_width = 5,
 537	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 538	.clkr.hw.init = &(struct clk_init_data) {
 539		.name = "blsp1_qup3_spi_apps_clk_src",
 540		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 541		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 542		.ops = &clk_rcg2_ops,
 543	},
 544};
 545
 546static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
 547	F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 548	F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 549	F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 550	F(24000000, P_XO, 1, 0, 0),
 551	F(25000000, P_GPLL0, 16, 1, 2),
 552	F(40000000, P_GPLL0, 1, 1, 20),
 553	F(46400000, P_GPLL0, 1, 29, 500),
 554	F(48000000, P_GPLL0, 1, 3, 50),
 555	F(51200000, P_GPLL0, 1, 8, 125),
 556	F(56000000, P_GPLL0, 1, 7, 100),
 557	F(58982400, P_GPLL0, 1, 1152, 15625),
 558	F(60000000, P_GPLL0, 1, 3, 40),
 559	F(64000000, P_GPLL0, 10, 4, 5),
 560	{ }
 561};
 562
 563static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 564	.cmd_rcgr = 0x02044,
 565	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 566	.mnd_width = 16,
 567	.hid_width = 5,
 568	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 569	.clkr.hw.init = &(struct clk_init_data) {
 570		.name = "blsp1_uart1_apps_clk_src",
 571		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 572		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 573		.ops = &clk_rcg2_ops,
 574	},
 575};
 576
 577static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 578	.cmd_rcgr = 0x03034,
 579	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 580	.mnd_width = 16,
 581	.hid_width = 5,
 582	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 583	.clkr.hw.init = &(struct clk_init_data) {
 584		.name = "blsp1_uart2_apps_clk_src",
 585		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 586		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 587		.ops = &clk_rcg2_ops,
 588	},
 589};
 590
 591static const struct freq_tbl ftbl_crypto_clk_src[] = {
 592	F(160000000, P_GPLL0, 5, 0, 0),
 593	{ }
 594};
 595
 596static struct clk_rcg2 crypto_clk_src = {
 597	.cmd_rcgr = 0x16004,
 598	.freq_tbl = ftbl_crypto_clk_src,
 599	.hid_width = 5,
 600	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 601	.clkr.hw.init = &(struct clk_init_data) {
 602		.name = "crypto_clk_src",
 603		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 604		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 605		.ops = &clk_rcg2_ops,
 606	},
 607};
 608
 609static const struct freq_tbl ftbl_gmac0_tx_clk_src[] = {
 610	F(2500000, P_GEPHY_TX, 5, 0, 0),
 611	F(24000000, P_XO, 1, 0, 0),
 612	F(25000000, P_GEPHY_TX, 5, 0, 0),
 613	F(125000000, P_GEPHY_TX, 1, 0, 0),
 614	{ }
 615};
 616
 617static struct clk_rcg2 gmac0_rx_clk_src = {
 618	.cmd_rcgr = 0x68020,
 619	.parent_map = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map,
 620	.hid_width = 5,
 621	.freq_tbl = ftbl_gmac0_tx_clk_src,
 622	.clkr.hw.init = &(struct clk_init_data) {
 623		.name = "gmac0_rx_clk_src",
 624		.parent_data = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0,
 625		.num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0),
 626		.ops = &clk_rcg2_ops,
 627	},
 628};
 629
 630static struct clk_regmap_div gmac0_rx_div_clk_src = {
 631	.reg = 0x68420,
 632	.shift = 0,
 633	.width = 4,
 634	.clkr = {
 635		.hw.init = &(struct clk_init_data) {
 636			.name = "gmac0_rx_div_clk_src",
 637			.parent_hws = (const struct clk_hw *[]) {
 638				&gmac0_rx_clk_src.clkr.hw,
 639			},
 640			.num_parents = 1,
 641			.ops = &clk_regmap_div_ops,
 642			.flags = CLK_SET_RATE_PARENT,
 643		},
 644	},
 645};
 646
 647static struct clk_rcg2 gmac0_tx_clk_src = {
 648	.cmd_rcgr = 0x68028,
 649	.parent_map = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map,
 650	.hid_width = 5,
 651	.freq_tbl = ftbl_gmac0_tx_clk_src,
 652	.clkr.hw.init = &(struct clk_init_data) {
 653		.name = "gmac0_tx_clk_src",
 654		.parent_data = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0,
 655		.num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0),
 656		.ops = &clk_rcg2_ops,
 657	},
 658};
 659
 660static struct clk_regmap_div gmac0_tx_div_clk_src = {
 661	.reg = 0x68424,
 662	.shift = 0,
 663	.width = 4,
 664	.clkr = {
 665		.hw.init = &(struct clk_init_data) {
 666			.name = "gmac0_tx_div_clk_src",
 667			.parent_hws = (const struct clk_hw *[]) {
 668				&gmac0_tx_clk_src.clkr.hw,
 669			},
 670			.num_parents = 1,
 671			.ops = &clk_regmap_div_ops,
 672			.flags = CLK_SET_RATE_PARENT,
 673		},
 674	},
 675};
 676
 677static const struct freq_tbl ftbl_gmac1_rx_clk_src[] = {
 678	F(2500000, P_UNIPHY_RX, 12.5, 0, 0),
 679	F(24000000, P_XO, 1, 0, 0),
 680	F(25000000, P_UNIPHY_RX, 2.5, 0, 0),
 681	F(125000000, P_UNIPHY_RX, 2.5, 0, 0),
 682	F(125000000, P_UNIPHY_RX, 1, 0, 0),
 683	F(312500000, P_UNIPHY_RX, 1, 0, 0),
 684	{ }
 685};
 686
 687static struct clk_rcg2 gmac1_rx_clk_src = {
 688	.cmd_rcgr = 0x68030,
 689	.parent_map = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map,
 690	.hid_width = 5,
 691	.freq_tbl = ftbl_gmac1_rx_clk_src,
 692	.clkr.hw.init = &(struct clk_init_data) {
 693		.name = "gmac1_rx_clk_src",
 694		.parent_data = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0,
 695		.num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0),
 696		.ops = &clk_rcg2_ops,
 697	},
 698};
 699
 700static struct clk_regmap_div gmac1_rx_div_clk_src = {
 701	.reg = 0x68430,
 702	.shift = 0,
 703	.width = 4,
 704	.clkr = {
 705		.hw.init = &(struct clk_init_data) {
 706			.name = "gmac1_rx_div_clk_src",
 707			.parent_hws = (const struct clk_hw *[]) {
 708				&gmac1_rx_clk_src.clkr.hw,
 709			},
 710			.num_parents = 1,
 711			.ops = &clk_regmap_div_ops,
 712			.flags = CLK_SET_RATE_PARENT,
 713		},
 714	},
 715};
 716
 717static const struct freq_tbl ftbl_gmac1_tx_clk_src[] = {
 718	F(2500000, P_UNIPHY_TX, 12.5, 0, 0),
 719	F(24000000, P_XO, 1, 0, 0),
 720	F(25000000, P_UNIPHY_TX, 2.5, 0, 0),
 721	F(125000000, P_UNIPHY_TX, 2.5, 0, 0),
 722	F(125000000, P_UNIPHY_TX, 1, 0, 0),
 723	F(312500000, P_UNIPHY_TX, 1, 0, 0),
 724	{ }
 725};
 726
 727static struct clk_rcg2 gmac1_tx_clk_src = {
 728	.cmd_rcgr = 0x68038,
 729	.parent_map = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map,
 730	.hid_width = 5,
 731	.freq_tbl = ftbl_gmac1_tx_clk_src,
 732	.clkr.hw.init = &(struct clk_init_data) {
 733		.name = "gmac1_tx_clk_src",
 734		.parent_data = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0,
 735		.num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0),
 736		.ops = &clk_rcg2_ops,
 737	},
 738};
 739
 740static struct clk_regmap_div gmac1_tx_div_clk_src = {
 741	.reg = 0x68434,
 742	.shift = 0,
 743	.width = 4,
 744	.clkr = {
 745		.hw.init = &(struct clk_init_data) {
 746			.name = "gmac1_tx_div_clk_src",
 747			.parent_hws = (const struct clk_hw *[]) {
 748				&gmac1_tx_clk_src.clkr.hw,
 749			},
 750			.num_parents = 1,
 751			.ops = &clk_regmap_div_ops,
 752			.flags = CLK_SET_RATE_PARENT,
 753		},
 754	},
 755};
 756
 757static const struct freq_tbl ftbl_gmac_clk_src[] = {
 758	F(240000000, P_GPLL4, 5, 0, 0),
 759	{ }
 760};
 761
 762static struct clk_rcg2 gmac_clk_src = {
 763	.cmd_rcgr = 0x68080,
 764	.parent_map = gcc_xo_gpll0_gpll4_map,
 765	.hid_width = 5,
 766	.freq_tbl = ftbl_gmac_clk_src,
 767	.clkr.hw.init = &(struct clk_init_data) {
 768		.name = "gmac_clk_src",
 769		.parent_data = gcc_xo_gpll0_gpll4,
 770		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
 771		.ops = &clk_rcg2_ops,
 772	},
 773};
 774
 775static const struct freq_tbl ftbl_gp_clk_src[] = {
 776	F(200000000, P_GPLL0, 4, 0, 0),
 777	{ }
 778};
 779
 780static struct clk_rcg2 gp1_clk_src = {
 781	.cmd_rcgr = 0x08004,
 782	.freq_tbl = ftbl_gp_clk_src,
 783	.mnd_width = 8,
 784	.hid_width = 5,
 785	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
 786	.clkr.hw.init = &(struct clk_init_data) {
 787		.name = "gp1_clk_src",
 788		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
 789		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
 790		.ops = &clk_rcg2_ops,
 791	},
 792};
 793
 794static struct clk_rcg2 gp2_clk_src = {
 795	.cmd_rcgr = 0x09004,
 796	.freq_tbl = ftbl_gp_clk_src,
 797	.mnd_width = 8,
 798	.hid_width = 5,
 799	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
 800	.clkr.hw.init = &(struct clk_init_data) {
 801		.name = "gp2_clk_src",
 802		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
 803		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
 804		.ops = &clk_rcg2_ops,
 805	},
 806};
 807
 808static struct clk_rcg2 gp3_clk_src = {
 809	.cmd_rcgr = 0x0a004,
 810	.freq_tbl = ftbl_gp_clk_src,
 811	.mnd_width = 8,
 812	.hid_width = 5,
 813	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
 814	.clkr.hw.init = &(struct clk_init_data) {
 815		.name = "gp3_clk_src",
 816		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
 817		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
 818		.ops = &clk_rcg2_ops,
 819	},
 820};
 821
 822static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
 823	F(133333334, P_GPLL0, 6, 0, 0),
 824	{ }
 825};
 826
 827static struct clk_rcg2 lpass_axim_clk_src = {
 828	.cmd_rcgr = 0x2e028,
 829	.freq_tbl = ftbl_lpass_axim_clk_src,
 830	.hid_width = 5,
 831	.parent_map = gcc_xo_gpll0_map,
 832	.clkr.hw.init = &(struct clk_init_data) {
 833		.name = "lpass_axim_clk_src",
 834		.parent_data = gcc_xo_gpll0,
 835		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 836		.ops = &clk_rcg2_ops,
 837	},
 838};
 839
 840static const struct freq_tbl ftbl_lpass_sway_clk_src[] = {
 841	F(66666667, P_GPLL0, 12, 0, 0),
 842	{ }
 843};
 844
 845static struct clk_rcg2 lpass_sway_clk_src = {
 846	.cmd_rcgr = 0x2e040,
 847	.freq_tbl = ftbl_lpass_sway_clk_src,
 848	.hid_width = 5,
 849	.parent_map = gcc_xo_gpll0_map,
 850	.clkr.hw.init = &(struct clk_init_data) {
 851		.name = "lpass_sway_clk_src",
 852		.parent_data = gcc_xo_gpll0,
 853		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 854		.ops = &clk_rcg2_ops,
 855	},
 856};
 857
 858static const struct freq_tbl ftbl_pcie0_aux_clk_src[] = {
 859	F(2000000, P_XO, 12, 0, 0),
 860	{ }
 861};
 862
 863static struct clk_rcg2 pcie0_aux_clk_src = {
 864	.cmd_rcgr = 0x75020,
 865	.freq_tbl = ftbl_pcie0_aux_clk_src,
 866	.mnd_width = 16,
 867	.hid_width = 5,
 868	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
 869	.clkr.hw.init = &(struct clk_init_data) {
 870		.name = "pcie0_aux_clk_src",
 871		.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
 872		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
 873		.ops = &clk_rcg2_ops,
 874	},
 875};
 876
 877static const struct freq_tbl ftbl_pcie0_axi_clk_src[] = {
 878	F(240000000, P_GPLL4, 5, 0, 0),
 879	{ }
 880};
 881
 882static struct clk_rcg2 pcie0_axi_clk_src = {
 883	.cmd_rcgr = 0x75050,
 884	.freq_tbl = ftbl_pcie0_axi_clk_src,
 885	.hid_width = 5,
 886	.parent_map = gcc_xo_gpll0_gpll4_map,
 887	.clkr.hw.init = &(struct clk_init_data) {
 888		.name = "pcie0_axi_clk_src",
 889		.parent_data = gcc_xo_gpll0_gpll4,
 890		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
 891		.ops = &clk_rcg2_ops,
 892	},
 893};
 894
 895static struct clk_rcg2 pcie1_aux_clk_src = {
 896	.cmd_rcgr = 0x76020,
 897	.freq_tbl = ftbl_pcie0_aux_clk_src,
 898	.mnd_width = 16,
 899	.hid_width = 5,
 900	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
 901	.clkr.hw.init = &(struct clk_init_data) {
 902		.name = "pcie1_aux_clk_src",
 903		.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
 904		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
 905		.ops = &clk_rcg2_ops,
 906	},
 907};
 908
 909static struct clk_rcg2 pcie1_axi_clk_src = {
 910	.cmd_rcgr = 0x76050,
 911	.freq_tbl = ftbl_gp_clk_src,
 912	.hid_width = 5,
 913	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 914	.clkr.hw.init = &(struct clk_init_data) {
 915		.name = "pcie1_axi_clk_src",
 916		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 917		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 918		.ops = &clk_rcg2_ops,
 919	},
 920};
 921
 922static struct clk_regmap_mux pcie0_pipe_clk_src = {
 923	.reg = 0x7501c,
 924	.shift = 8,
 925	.width = 2,
 926	.parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
 927	.clkr = {
 928		.hw.init = &(struct clk_init_data) {
 929			.name = "pcie0_pipe_clk_src",
 930			.parent_data = gcc_pcie20_phy0_pipe_clk_xo,
 931			.num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
 932			.ops = &clk_regmap_mux_closest_ops,
 933			.flags = CLK_SET_RATE_PARENT,
 934		},
 935	},
 936};
 937
 938static struct clk_regmap_mux pcie1_pipe_clk_src = {
 939	.reg = 0x7601c,
 940	.shift = 8,
 941	.width = 2,
 942	.parent_map = gcc_pcie20_phy1_pipe_clk_xo_map, .clkr = {
 943		.hw.init = &(struct clk_init_data) {
 944			.name = "pcie1_pipe_clk_src",
 945			.parent_data = gcc_pcie20_phy1_pipe_clk_xo,
 946			.num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
 947			.ops = &clk_regmap_mux_closest_ops,
 948			.flags = CLK_SET_RATE_PARENT,
 949		},
 950	},
 951};
 952
 953static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 954	F(100000000, P_GPLL0, 8, 0, 0),
 955	{ }
 956};
 957
 958static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 959	.cmd_rcgr = 0x27000,
 960	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 961	.hid_width = 5,
 962	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 963	.clkr.hw.init = &(struct clk_init_data) {
 964		.name = "pcnoc_bfdcd_clk_src",
 965		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
 966		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
 967		.ops = &clk_rcg2_ops,
 968	},
 969};
 970
 971static struct clk_fixed_factor pcnoc_clk_src = {
 972	.mult = 1,
 973	.div = 1,
 974	.hw.init = &(struct clk_init_data) {
 975		.name = "pcnoc_clk_src",
 976		.parent_hws = (const struct clk_hw *[]) {
 977			&pcnoc_bfdcd_clk_src.clkr.hw,
 978		},
 979		.num_parents = 1,
 980		.ops = &clk_fixed_factor_ops,
 981		.flags = CLK_SET_RATE_PARENT,
 982	},
 983};
 984
 985static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
 986	F(240000000, P_GPLL4, 5, 0, 0),
 987	{ }
 988};
 989
 990static struct clk_rcg2 qdss_at_clk_src = {
 991	.cmd_rcgr = 0x2900c,
 992	.freq_tbl = ftbl_qdss_at_clk_src,
 993	.hid_width = 5,
 994	.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
 995	.clkr.hw.init = &(struct clk_init_data) {
 996		.name = "qdss_at_clk_src",
 997		.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
 998		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
 999		.ops = &clk_rcg2_ops,
1000	},
1001};
1002
1003static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
1004	F(200000000, P_GPLL0, 4, 0, 0),
1005	{ }
1006};
1007
1008static struct clk_rcg2 qdss_stm_clk_src = {
1009	.cmd_rcgr = 0x2902c,
1010	.freq_tbl = ftbl_qdss_stm_clk_src,
1011	.hid_width = 5,
1012	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1013	.clkr.hw.init = &(struct clk_init_data) {
1014		.name = "qdss_stm_clk_src",
1015		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1016		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
1017		.ops = &clk_rcg2_ops,
1018	},
1019};
1020
1021static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
1022	F(266666667, P_GPLL0, 3, 0, 0),
1023	{ }
1024};
1025
1026static struct clk_rcg2 qdss_traceclkin_clk_src = {
1027	.cmd_rcgr = 0x29048,
1028	.freq_tbl = ftbl_qdss_traceclkin_clk_src,
1029	.hid_width = 5,
1030	.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
1031	.clkr.hw.init = &(struct clk_init_data) {
1032		.name = "qdss_traceclkin_clk_src",
1033		.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1034		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1035		.ops = &clk_rcg2_ops,
1036	},
1037};
1038
1039static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
1040	F(600000000, P_GPLL4, 2, 0, 0),
1041	{ }
1042};
1043
1044static struct clk_rcg2 qdss_tsctr_clk_src = {
1045	.cmd_rcgr = 0x29064,
1046	.freq_tbl = ftbl_qdss_tsctr_clk_src,
1047	.hid_width = 5,
1048	.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
1049	.clkr.hw.init = &(struct clk_init_data) {
1050		.name = "qdss_tsctr_clk_src",
1051		.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1052		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1053		.ops = &clk_rcg2_ops,
1054	},
1055};
1056
1057static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
1058	.mult = 1,
1059	.div = 2,
1060	.hw.init = &(struct clk_init_data) {
1061		.name = "qdss_tsctr_div2_clk_src",
1062		.parent_hws = (const struct clk_hw *[]) {
1063			&qdss_tsctr_clk_src.clkr.hw,
1064		},
1065		.num_parents = 1,
1066		.flags = CLK_SET_RATE_PARENT,
1067		.ops = &clk_fixed_factor_ops,
1068	},
1069};
1070
1071static struct clk_fixed_factor qdss_dap_sync_clk_src = {
1072	.mult = 1,
1073	.div = 4,
1074	.hw.init = &(struct clk_init_data) {
1075		.name = "qdss_dap_sync_clk_src",
1076		.parent_hws = (const struct clk_hw *[]) {
1077			&qdss_tsctr_clk_src.clkr.hw,
1078		},
1079		.num_parents = 1,
1080		.ops = &clk_fixed_factor_ops,
1081	},
1082};
1083
1084static struct clk_fixed_factor eud_at_clk_src = {
1085	.mult = 1,
1086	.div = 6,
1087	.hw.init = &(struct clk_init_data) {
1088		.name = "eud_at_clk_src",
1089		.parent_hws = (const struct clk_hw *[]) {
1090			&qdss_at_clk_src.clkr.hw,
1091		},
1092		.num_parents = 1,
1093		.ops = &clk_fixed_factor_ops,
1094		.flags = CLK_SET_RATE_PARENT,
1095	},
1096};
1097
1098static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
1099	F(24000000, P_XO, 1, 0, 0),
1100	F(100000000, P_GPLL0, 8, 0, 0),
1101	F(200000000, P_GPLL0, 4, 0, 0),
1102	F(320000000, P_GPLL0, 2.5, 0, 0),
1103	{ }
1104};
1105
1106static struct clk_rcg2 qpic_io_macro_clk_src = {
1107	.cmd_rcgr = 0x57010,
1108	.freq_tbl = ftbl_qpic_io_macro_clk_src,
1109	.hid_width = 5,
1110	.parent_map = gcc_xo_gpll0_gpll2_map,
1111	.clkr.hw.init = &(struct clk_init_data) {
1112		.name = "qpic_io_macro_clk_src",
1113		.parent_data = gcc_xo_gpll0_gpll2,
1114		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
1115		.ops = &clk_rcg2_ops,
1116	},
1117};
1118
1119static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1120	F(143713, P_XO, 1, 1, 167),
1121	F(400000, P_XO, 1, 1, 60),
1122	F(24000000, P_XO, 1, 0, 0),
1123	F(48000000, P_GPLL2, 12, 1, 2),
1124	F(96000000, P_GPLL2, 12, 0, 0),
1125	F(177777778, P_GPLL0, 1, 2, 9),
1126	F(192000000, P_GPLL2, 6, 0, 0),
1127	F(200000000, P_GPLL0, 4, 0, 0),
1128	{ }
1129};
1130
1131static struct clk_rcg2 sdcc1_apps_clk_src = {
1132	.cmd_rcgr = 0x42004,
1133	.freq_tbl = ftbl_sdcc1_apps_clk_src,
1134	.mnd_width = 8,
1135	.hid_width = 5,
1136	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1137	.clkr.hw.init = &(struct clk_init_data) {
1138		.name = "sdcc1_apps_clk_src",
1139		.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1140		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
1141		.ops = &clk_rcg2_floor_ops,
1142	},
1143};
1144
1145static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1146	F(266666667, P_GPLL0, 3, 0, 0),
1147	{ }
1148};
1149
1150static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1151	.cmd_rcgr = 0x26004,
1152	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1153	.hid_width = 5,
1154	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1155	.clkr.hw.init = &(struct clk_init_data) {
1156		.name = "system_noc_bfdcd_clk_src",
1157		.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1158		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
1159		.ops = &clk_rcg2_ops,
1160	},
1161};
1162
1163static struct clk_fixed_factor system_noc_clk_src = {
1164	.mult = 1,
1165	.div = 1,
1166	.hw.init = &(struct clk_init_data) {
1167		.name = "system_noc_clk_src",
1168		.parent_hws = (const struct clk_hw *[]) {
1169			&system_noc_bfdcd_clk_src.clkr.hw,
1170		},
1171		.num_parents = 1,
1172		.ops = &clk_fixed_factor_ops,
1173		.flags = CLK_SET_RATE_PARENT,
1174	},
1175};
1176
1177static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
1178	F(400000000, P_GPLL0, 2, 0, 0),
1179	{ }
1180};
1181
1182static struct clk_rcg2 ubi0_axi_clk_src = {
1183	.cmd_rcgr = 0x68088,
1184	.freq_tbl = ftbl_apss_axi_clk_src,
1185	.hid_width = 5,
1186	.parent_map = gcc_xo_gpll0_gpll2_map,
1187	.clkr.hw.init = &(struct clk_init_data) {
1188		.name = "ubi0_axi_clk_src",
1189		.parent_data = gcc_xo_gpll0_gpll2,
1190		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
1191		.ops = &clk_rcg2_ops,
1192		.flags = CLK_SET_RATE_PARENT,
1193	},
1194};
1195
1196static const struct freq_tbl ftbl_ubi0_core_clk_src[] = {
1197	F(850000000, P_UBI32_PLL, 1, 0, 0),
1198	F(1000000000, P_UBI32_PLL, 1, 0, 0),
1199	{ }
1200};
1201
1202static struct clk_rcg2 ubi0_core_clk_src = {
1203	.cmd_rcgr = 0x68100,
1204	.freq_tbl = ftbl_ubi0_core_clk_src,
1205	.hid_width = 5,
1206	.parent_map = gcc_xo_ubi32_gpll0_map,
1207	.clkr.hw.init = &(struct clk_init_data) {
1208		.name = "ubi0_core_clk_src",
1209		.parent_data = gcc_xo_ubi32_gpll0,
1210		.num_parents = ARRAY_SIZE(gcc_xo_ubi32_gpll0),
1211		.ops = &clk_rcg2_ops,
1212		.flags = CLK_SET_RATE_PARENT,
1213	},
1214};
1215
1216static struct clk_rcg2 usb0_aux_clk_src = {
1217	.cmd_rcgr = 0x3e05c,
1218	.freq_tbl = ftbl_pcie0_aux_clk_src,
1219	.mnd_width = 16,
1220	.hid_width = 5,
1221	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1222	.clkr.hw.init = &(struct clk_init_data) {
1223		.name = "usb0_aux_clk_src",
1224		.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1225		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
1226		.ops = &clk_rcg2_ops,
1227	},
1228};
1229
1230static const struct freq_tbl ftbl_usb0_lfps_clk_src[] = {
1231	F(25000000, P_GPLL0, 16, 1, 2),
1232	{ }
1233};
1234
1235static struct clk_rcg2 usb0_lfps_clk_src = {
1236	.cmd_rcgr = 0x3e090,
1237	.freq_tbl = ftbl_usb0_lfps_clk_src,
1238	.mnd_width = 8,
1239	.hid_width = 5,
1240	.parent_map = gcc_xo_gpll0_map,
1241	.clkr.hw.init = &(struct clk_init_data) {
1242		.name = "usb0_lfps_clk_src",
1243		.parent_data = gcc_xo_gpll0,
1244		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1245		.ops = &clk_rcg2_ops,
1246	},
1247};
1248
1249static struct clk_rcg2 usb0_master_clk_src = {
1250	.cmd_rcgr = 0x3e00c,
1251	.freq_tbl = ftbl_gp_clk_src,
1252	.mnd_width = 8,
1253	.hid_width = 5,
1254	.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1255	.clkr.hw.init = &(struct clk_init_data) {
1256		.name = "usb0_master_clk_src",
1257		.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
1258		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
1259		.ops = &clk_rcg2_ops,
1260	},
1261};
1262
1263static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
1264	F(60000000, P_GPLL4, 10, 1, 2),
1265	{ }
1266};
1267
1268static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1269	.cmd_rcgr = 0x3e020,
1270	.freq_tbl = ftbl_usb0_mock_utmi_clk_src,
1271	.mnd_width = 8,
1272	.hid_width = 5,
1273	.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2,
1274	.clkr.hw.init = &(struct clk_init_data) {
1275		.name = "usb0_mock_utmi_clk_src",
1276		.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1277		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1278		.ops = &clk_rcg2_ops,
1279	},
1280};
1281
1282static struct clk_regmap_mux usb0_pipe_clk_src = {
1283	.reg = 0x3e048,
1284	.shift = 8,
1285	.width = 2,
1286	.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1287	.clkr = {
1288		.hw.init = &(struct clk_init_data) {
1289			.name = "usb0_pipe_clk_src",
1290			.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
1291			.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
1292			.ops = &clk_regmap_mux_closest_ops,
1293			.flags = CLK_SET_RATE_PARENT,
1294		},
1295	},
1296};
1297
1298static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
1299	F(400000000, P_GPLL0, 2, 0, 0),
1300	{ }
1301};
1302
1303static struct clk_rcg2 q6_axi_clk_src = {
1304	.cmd_rcgr = 0x59120,
1305	.freq_tbl = ftbl_q6_axi_clk_src,
1306	.hid_width = 5,
1307	.parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
1308	.clkr.hw.init = &(struct clk_init_data) {
1309		.name = "q6_axi_clk_src",
1310		.parent_data = gcc_xo_gpll0_gpll2_gpll4,
1311		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4),
1312		.ops = &clk_rcg2_ops,
1313	},
1314};
1315
1316static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
1317	F(133333333, P_GPLL0, 6, 0, 0),
1318	{ }
1319};
1320
1321static struct clk_rcg2 wcss_ahb_clk_src = {
1322	.cmd_rcgr = 0x59020,
1323	.freq_tbl = ftbl_wcss_ahb_clk_src,
1324	.hid_width = 5,
1325	.parent_map = gcc_xo_gpll0_map,
1326	.clkr.hw.init = &(struct clk_init_data) {
1327		.name = "wcss_ahb_clk_src",
1328		.parent_data = gcc_xo_gpll0,
1329		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1330		.ops = &clk_rcg2_ops,
1331	},
1332};
1333
1334static struct clk_branch gcc_sleep_clk_src = {
1335	.halt_reg = 0x30000,
1336	.clkr = {
1337		.enable_reg = 0x30000,
1338		.enable_mask = BIT(1),
1339		.hw.init = &(struct clk_init_data) {
1340			.name = "gcc_sleep_clk_src",
1341			.parent_data = gcc_sleep_clk_data,
1342			.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
1343			.flags = CLK_IS_CRITICAL,
1344			.ops = &clk_branch2_ops,
1345		},
1346	},
1347};
1348
1349static struct clk_branch gcc_xo_clk_src = {
1350	.halt_reg = 0x30018,
1351	.clkr = {
1352		.enable_reg = 0x30018,
1353		.enable_mask = BIT(1),
1354		.hw.init = &(struct clk_init_data) {
1355			.name = "gcc_xo_clk_src",
1356			.parent_data = gcc_xo_data,
1357			.num_parents = ARRAY_SIZE(gcc_xo_data),
1358			.flags = CLK_SET_RATE_PARENT,
1359			.ops = &clk_branch2_ops,
1360		},
1361	},
1362};
1363
1364static struct clk_branch gcc_xo_clk = {
1365	.halt_reg = 0x30030,
1366	.clkr = {
1367		.enable_reg = 0x30030,
1368		.enable_mask = BIT(0),
1369		.hw.init = &(struct clk_init_data) {
1370			.name = "gcc_xo_clk",
1371			.parent_hws = (const struct clk_hw *[]) {
1372				&gcc_xo_clk_src.clkr.hw,
1373			},
1374			.num_parents = 1,
1375			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1376			.ops = &clk_branch2_ops,
1377		},
1378	},
1379};
1380
1381static struct clk_branch gcc_adss_pwm_clk = {
1382	.halt_reg = 0x1f020,
1383	.clkr = {
1384		.enable_reg = 0x1f020,
1385		.enable_mask = BIT(0),
1386		.hw.init = &(struct clk_init_data) {
1387			.name = "gcc_adss_pwm_clk",
1388			.parent_hws = (const struct clk_hw *[]) {
1389				&adss_pwm_clk_src.clkr.hw,
1390			},
1391			.num_parents = 1,
1392			.flags = CLK_SET_RATE_PARENT,
1393			.ops = &clk_branch2_ops,
1394		},
1395	},
1396};
1397
1398static struct clk_branch gcc_blsp1_ahb_clk = {
1399	.halt_reg = 0x01008,
1400	.halt_check = BRANCH_HALT_VOTED,
1401	.clkr = {
1402		.enable_reg = 0x0b004,
1403		.enable_mask = BIT(10),
1404		.hw.init = &(struct clk_init_data) {
1405			.name = "gcc_blsp1_ahb_clk",
1406			.parent_hws = (const struct clk_hw *[]) {
1407				&pcnoc_clk_src.hw,
1408			},
1409			.num_parents = 1,
1410			.flags = CLK_SET_RATE_PARENT,
1411			.ops = &clk_branch2_ops,
1412		},
1413	},
1414};
1415
1416static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1417	.halt_reg = 0x02008,
1418	.clkr = {
1419		.enable_reg = 0x02008,
1420		.enable_mask = BIT(0),
1421		.hw.init = &(struct clk_init_data) {
1422			.name = "gcc_blsp1_qup1_i2c_apps_clk",
1423			.parent_hws = (const struct clk_hw *[]) {
1424				&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1425			},
1426			.num_parents = 1,
1427			.flags = CLK_SET_RATE_PARENT,
1428			.ops = &clk_branch2_ops,
1429		},
1430	},
1431};
1432
1433static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1434	.halt_reg = 0x02004,
1435	.clkr = {
1436		.enable_reg = 0x02004,
1437		.enable_mask = BIT(0),
1438		.hw.init = &(struct clk_init_data) {
1439			.name = "gcc_blsp1_qup1_spi_apps_clk",
1440			.parent_hws = (const struct clk_hw *[]) {
1441				&blsp1_qup1_spi_apps_clk_src.clkr.hw,
1442			},
1443			.num_parents = 1,
1444			.flags = CLK_SET_RATE_PARENT,
1445			.ops = &clk_branch2_ops,
1446		},
1447	},
1448};
1449
1450static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1451	.halt_reg = 0x03010,
1452	.clkr = {
1453		.enable_reg = 0x03010,
1454		.enable_mask = BIT(0),
1455		.hw.init = &(struct clk_init_data) {
1456			.name = "gcc_blsp1_qup2_i2c_apps_clk",
1457			.parent_hws = (const struct clk_hw *[]) {
1458				&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1459			},
1460			.num_parents = 1,
1461			.flags = CLK_SET_RATE_PARENT,
1462			.ops = &clk_branch2_ops,
1463		},
1464	},
1465};
1466
1467static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1468	.halt_reg = 0x0300c,
1469	.clkr = {
1470		.enable_reg = 0x0300c,
1471		.enable_mask = BIT(0),
1472		.hw.init = &(struct clk_init_data) {
1473			.name = "gcc_blsp1_qup2_spi_apps_clk",
1474			.parent_hws = (const struct clk_hw *[]) {
1475				&blsp1_qup2_spi_apps_clk_src.clkr.hw,
1476			},
1477			.num_parents = 1,
1478			.flags = CLK_SET_RATE_PARENT,
1479			.ops = &clk_branch2_ops,
1480		},
1481	},
1482};
1483
1484static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1485	.halt_reg = 0x04010,
1486	.clkr = {
1487		.enable_reg = 0x04010,
1488		.enable_mask = BIT(0),
1489		.hw.init = &(struct clk_init_data) {
1490			.name = "gcc_blsp1_qup3_i2c_apps_clk",
1491			.parent_hws = (const struct clk_hw *[]) {
1492				&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1493			},
1494			.num_parents = 1,
1495			.flags = CLK_SET_RATE_PARENT,
1496			.ops = &clk_branch2_ops,
1497		},
1498	},
1499};
1500
1501static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1502	.halt_reg = 0x0400c,
1503	.clkr = {
1504		.enable_reg = 0x0400c,
1505		.enable_mask = BIT(0),
1506		.hw.init = &(struct clk_init_data) {
1507			.name = "gcc_blsp1_qup3_spi_apps_clk",
1508			.parent_hws = (const struct clk_hw *[]) {
1509				&blsp1_qup3_spi_apps_clk_src.clkr.hw,
1510			},
1511			.num_parents = 1,
1512			.flags = CLK_SET_RATE_PARENT,
1513			.ops = &clk_branch2_ops,
1514		},
1515	},
1516};
1517
1518static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1519	.halt_reg = 0x0203c,
1520	.clkr = {
1521		.enable_reg = 0x0203c,
1522		.enable_mask = BIT(0),
1523		.hw.init = &(struct clk_init_data) {
1524			.name = "gcc_blsp1_uart1_apps_clk",
1525			.parent_hws = (const struct clk_hw *[]) {
1526				&blsp1_uart1_apps_clk_src.clkr.hw,
1527			},
1528			.num_parents = 1,
1529			.flags = CLK_SET_RATE_PARENT,
1530			.ops = &clk_branch2_ops,
1531		},
1532	},
1533};
1534
1535static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1536	.halt_reg = 0x0302c,
1537	.clkr = {
1538		.enable_reg = 0x0302c,
1539		.enable_mask = BIT(0),
1540		.hw.init = &(struct clk_init_data) {
1541			.name = "gcc_blsp1_uart2_apps_clk",
1542			.parent_hws = (const struct clk_hw *[]) {
1543				&blsp1_uart2_apps_clk_src.clkr.hw,
1544			},
1545			.num_parents = 1,
1546			.flags = CLK_SET_RATE_PARENT,
1547			.ops = &clk_branch2_ops,
1548		},
1549	},
1550};
1551
1552static struct clk_branch gcc_btss_lpo_clk = {
1553	.halt_reg = 0x1c004,
1554	.clkr = {
1555		.enable_reg = 0x1c004,
1556		.enable_mask = BIT(0),
1557		.hw.init = &(struct clk_init_data) {
1558			.name = "gcc_btss_lpo_clk",
1559			.ops = &clk_branch2_ops,
1560		},
1561	},
1562};
1563
1564static struct clk_branch gcc_cmn_blk_ahb_clk = {
1565	.halt_reg = 0x56308,
1566	.clkr = {
1567		.enable_reg = 0x56308,
1568		.enable_mask = BIT(0),
1569		.hw.init = &(struct clk_init_data) {
1570			.name = "gcc_cmn_blk_ahb_clk",
1571			.parent_hws = (const struct clk_hw *[]) {
1572				&pcnoc_clk_src.hw,
1573			},
1574			.num_parents = 1,
1575			.flags = CLK_SET_RATE_PARENT,
1576			.ops = &clk_branch2_ops,
1577		},
1578	},
1579};
1580
1581static struct clk_branch gcc_cmn_blk_sys_clk = {
1582	.halt_reg = 0x5630c,
1583	.clkr = {
1584		.enable_reg = 0x5630c,
1585		.enable_mask = BIT(0),
1586		.hw.init = &(struct clk_init_data) {
1587			.name = "gcc_cmn_blk_sys_clk",
1588			.parent_hws = (const struct clk_hw *[]) {
1589				&gcc_xo_clk_src.clkr.hw,
1590			},
1591			.num_parents = 1,
1592			.flags = CLK_SET_RATE_PARENT,
1593			.ops = &clk_branch2_ops,
1594		},
1595	},
1596};
1597
1598static struct clk_branch gcc_crypto_ahb_clk = {
1599	.halt_reg = 0x16024,
1600	.halt_check = BRANCH_HALT_VOTED,
1601	.clkr = {
1602		.enable_reg = 0x0b004,
1603		.enable_mask = BIT(0),
1604		.hw.init = &(struct clk_init_data) {
1605			.name = "gcc_crypto_ahb_clk",
1606			.parent_hws = (const struct clk_hw *[]) {
1607				&pcnoc_clk_src.hw,
1608			},
1609			.num_parents = 1,
1610			.flags = CLK_SET_RATE_PARENT,
1611			.ops = &clk_branch2_ops,
1612		},
1613	},
1614};
1615
1616static struct clk_branch gcc_crypto_axi_clk = {
1617	.halt_reg = 0x16020,
1618	.halt_check = BRANCH_HALT_VOTED,
1619	.clkr = {
1620		.enable_reg = 0x0b004,
1621		.enable_mask = BIT(1),
1622		.hw.init = &(struct clk_init_data) {
1623			.name = "gcc_crypto_axi_clk",
1624			.parent_hws = (const struct clk_hw *[]) {
1625				&pcnoc_clk_src.hw,
1626			},
1627			.num_parents = 1,
1628			.flags = CLK_SET_RATE_PARENT,
1629			.ops = &clk_branch2_ops,
1630		},
1631	},
1632};
1633
1634static struct clk_branch gcc_crypto_clk = {
1635	.halt_reg = 0x1601c,
1636	.halt_check = BRANCH_HALT_VOTED,
1637	.clkr = {
1638		.enable_reg = 0x0b004,
1639		.enable_mask = BIT(2),
1640		.hw.init = &(struct clk_init_data) {
1641			.name = "gcc_crypto_clk",
1642			.parent_hws = (const struct clk_hw *[]) {
1643				&crypto_clk_src.clkr.hw,
1644			},
1645			.num_parents = 1,
1646			.flags = CLK_SET_RATE_PARENT,
1647			.ops = &clk_branch2_ops,
1648		},
1649	},
1650};
1651
1652static struct clk_branch gcc_dcc_clk = {
1653	.halt_reg = 0x77004,
1654	.clkr = {
1655		.enable_reg = 0x77004,
1656		.enable_mask = BIT(0),
1657		.hw.init = &(struct clk_init_data) {
1658			.name = "gcc_dcc_clk",
1659			.parent_hws = (const struct clk_hw *[]) {
1660				&pcnoc_clk_src.hw,
1661			},
1662			.num_parents = 1,
1663			.flags = CLK_SET_RATE_PARENT,
1664			.ops = &clk_branch2_ops,
1665		},
1666	},
1667};
1668
1669static struct clk_branch gcc_gephy_rx_clk = {
1670	.halt_reg = 0x56010,
1671	.halt_check = BRANCH_HALT_DELAY,
1672	.clkr = {
1673		.enable_reg = 0x56010,
1674		.enable_mask = BIT(0),
1675		.hw.init = &(struct clk_init_data) {
1676			.name = "gcc_gephy_rx_clk",
1677			.parent_hws = (const struct clk_hw *[]) {
1678				&gmac0_rx_div_clk_src.clkr.hw,
1679			},
1680			.num_parents = 1,
1681			.ops = &clk_branch2_ops,
1682			.flags = CLK_SET_RATE_PARENT,
1683		},
1684	},
1685};
1686
1687static struct clk_branch gcc_gephy_tx_clk = {
1688	.halt_reg = 0x56014,
1689	.halt_check = BRANCH_HALT_DELAY,
1690	.clkr = {
1691		.enable_reg = 0x56014,
1692		.enable_mask = BIT(0),
1693		.hw.init = &(struct clk_init_data) {
1694			.name = "gcc_gephy_tx_clk",
1695			.parent_hws = (const struct clk_hw *[]) {
1696				&gmac0_tx_div_clk_src.clkr.hw,
1697			},
1698			.num_parents = 1,
1699			.ops = &clk_branch2_ops,
1700			.flags = CLK_SET_RATE_PARENT,
1701		},
1702	},
1703};
1704
1705static struct clk_branch gcc_gmac0_cfg_clk = {
1706	.halt_reg = 0x68304,
1707	.clkr = {
1708		.enable_reg = 0x68304,
1709		.enable_mask = BIT(0),
1710		.hw.init = &(struct clk_init_data) {
1711			.name = "gcc_gmac0_cfg_clk",
1712			.parent_hws = (const struct clk_hw *[]) {
1713				&gmac_clk_src.clkr.hw,
1714			},
1715			.num_parents = 1,
1716			.flags = CLK_SET_RATE_PARENT,
1717			.ops = &clk_branch2_ops,
1718		},
1719	},
1720};
1721
1722static struct clk_branch gcc_gmac0_ptp_clk = {
1723	.halt_reg = 0x68300,
1724	.clkr = {
1725		.enable_reg = 0x68300,
1726		.enable_mask = BIT(0),
1727		.hw.init = &(struct clk_init_data) {
1728			.name = "gcc_gmac0_ptp_clk",
1729			.parent_hws = (const struct clk_hw *[]) {
1730				&gmac_clk_src.clkr.hw,
1731			},
1732			.num_parents = 1,
1733			.flags = CLK_SET_RATE_PARENT,
1734			.ops = &clk_branch2_ops,
1735		},
1736	},
1737};
1738
1739static struct clk_branch gcc_gmac0_rx_clk = {
1740	.halt_reg = 0x68240,
1741	.clkr = {
1742		.enable_reg = 0x68240,
1743		.enable_mask = BIT(0),
1744		.hw.init = &(struct clk_init_data) {
1745			.name = "gcc_gmac0_rx_clk",
1746			.parent_hws = (const struct clk_hw *[]) {
1747				&gmac0_rx_div_clk_src.clkr.hw,
1748			},
1749			.num_parents = 1,
1750			.ops = &clk_branch2_ops,
1751			.flags = CLK_SET_RATE_PARENT,
1752		},
1753	},
1754};
1755
1756static struct clk_branch gcc_gmac0_sys_clk = {
1757	.halt_reg = 0x68190,
1758	.halt_check = BRANCH_HALT_DELAY,
1759	.halt_bit = 31,
1760	.clkr = {
1761		.enable_reg = 0x68190,
1762		.enable_mask = BIT(0),
1763		.hw.init = &(struct clk_init_data) {
1764			.name = "gcc_gmac0_sys_clk",
1765			.parent_hws = (const struct clk_hw *[]) {
1766				&gmac_clk_src.clkr.hw,
1767			},
1768			.num_parents = 1,
1769			.flags = CLK_SET_RATE_PARENT,
1770			.ops = &clk_branch2_ops,
1771		},
1772	},
1773};
1774
1775static struct clk_branch gcc_gmac0_tx_clk = {
1776	.halt_reg = 0x68244,
1777	.clkr = {
1778		.enable_reg = 0x68244,
1779		.enable_mask = BIT(0),
1780		.hw.init = &(struct clk_init_data) {
1781			.name = "gcc_gmac0_tx_clk",
1782			.parent_hws = (const struct clk_hw *[]) {
1783				&gmac0_tx_div_clk_src.clkr.hw,
1784			},
1785			.num_parents = 1,
1786			.ops = &clk_branch2_ops,
1787			.flags = CLK_SET_RATE_PARENT,
1788		},
1789	},
1790};
1791
1792static struct clk_branch gcc_gmac1_cfg_clk = {
1793	.halt_reg = 0x68324,
1794	.clkr = {
1795		.enable_reg = 0x68324,
1796		.enable_mask = BIT(0),
1797		.hw.init = &(struct clk_init_data) {
1798			.name = "gcc_gmac1_cfg_clk",
1799			.parent_hws = (const struct clk_hw *[]) {
1800				&gmac_clk_src.clkr.hw,
1801			},
1802			.num_parents = 1,
1803			.flags = CLK_SET_RATE_PARENT,
1804			.ops = &clk_branch2_ops,
1805		},
1806	},
1807};
1808
1809static struct clk_branch gcc_gmac1_ptp_clk = {
1810	.halt_reg = 0x68320,
1811	.clkr = {
1812		.enable_reg = 0x68320,
1813		.enable_mask = BIT(0),
1814		.hw.init = &(struct clk_init_data) {
1815			.name = "gcc_gmac1_ptp_clk",
1816			.parent_hws = (const struct clk_hw *[]) {
1817				&gmac_clk_src.clkr.hw,
1818			},
1819			.num_parents = 1,
1820			.flags = CLK_SET_RATE_PARENT,
1821			.ops = &clk_branch2_ops,
1822		},
1823	},
1824};
1825
1826static struct clk_branch gcc_gmac1_rx_clk = {
1827	.halt_reg = 0x68248,
1828	.clkr = {
1829		.enable_reg = 0x68248,
1830		.enable_mask = BIT(0),
1831		.hw.init = &(struct clk_init_data) {
1832			.name = "gcc_gmac1_rx_clk",
1833			.parent_hws = (const struct clk_hw *[]) {
1834				&gmac1_rx_div_clk_src.clkr.hw,
1835			},
1836			.num_parents = 1,
1837			.ops = &clk_branch2_ops,
1838			.flags = CLK_SET_RATE_PARENT,
1839		},
1840	},
1841};
1842
1843static struct clk_branch gcc_gmac1_sys_clk = {
1844	.halt_reg = 0x68310,
1845	.clkr = {
1846		.enable_reg = 0x68310,
1847		.enable_mask = BIT(0),
1848		.hw.init = &(struct clk_init_data) {
1849			.name = "gcc_gmac1_sys_clk",
1850			.parent_hws = (const struct clk_hw *[]) {
1851				&gmac_clk_src.clkr.hw,
1852			},
1853			.num_parents = 1,
1854			.flags = CLK_SET_RATE_PARENT,
1855			.ops = &clk_branch2_ops,
1856		},
1857	},
1858};
1859
1860static struct clk_branch gcc_gmac1_tx_clk = {
1861	.halt_reg = 0x6824c,
1862	.clkr = {
1863		.enable_reg = 0x6824c,
1864		.enable_mask = BIT(0),
1865		.hw.init = &(struct clk_init_data) {
1866			.name = "gcc_gmac1_tx_clk",
1867			.parent_hws = (const struct clk_hw *[]) {
1868				&gmac1_tx_div_clk_src.clkr.hw,
1869			},
1870			.num_parents = 1,
1871			.ops = &clk_branch2_ops,
1872			.flags = CLK_SET_RATE_PARENT,
1873		},
1874	},
1875};
1876
1877static struct clk_branch gcc_gp1_clk = {
1878	.halt_reg = 0x08000,
1879	.clkr = {
1880		.enable_reg = 0x08000,
1881		.enable_mask = BIT(0),
1882		.hw.init = &(struct clk_init_data) {
1883			.name = "gcc_gp1_clk",
1884			.parent_hws = (const struct clk_hw *[]) {
1885				&gp1_clk_src.clkr.hw,
1886			},
1887			.num_parents = 1,
1888			.flags = CLK_SET_RATE_PARENT,
1889			.ops = &clk_branch2_ops,
1890		},
1891	},
1892};
1893
1894static struct clk_branch gcc_gp2_clk = {
1895	.halt_reg = 0x09000,
1896	.clkr = {
1897		.enable_reg = 0x09000,
1898		.enable_mask = BIT(0),
1899		.hw.init = &(struct clk_init_data) {
1900			.name = "gcc_gp2_clk",
1901			.parent_hws = (const struct clk_hw *[]) {
1902				&gp2_clk_src.clkr.hw,
1903			},
1904			.num_parents = 1,
1905			.flags = CLK_SET_RATE_PARENT,
1906			.ops = &clk_branch2_ops,
1907		},
1908	},
1909};
1910
1911static struct clk_branch gcc_gp3_clk = {
1912	.halt_reg = 0x0a000,
1913	.clkr = {
1914		.enable_reg = 0x0a000,
1915		.enable_mask = BIT(0),
1916		.hw.init = &(struct clk_init_data) {
1917			.name = "gcc_gp3_clk",
1918			.parent_hws = (const struct clk_hw *[]) {
1919				&gp3_clk_src.clkr.hw,
1920			},
1921			.num_parents = 1,
1922			.flags = CLK_SET_RATE_PARENT,
1923			.ops = &clk_branch2_ops,
1924		},
1925	},
1926};
1927
1928static struct clk_branch gcc_lpass_core_axim_clk = {
1929	.halt_reg = 0x2e048,
1930	.halt_check = BRANCH_VOTED,
1931	.clkr = {
1932		.enable_reg = 0x2e048,
1933		.enable_mask = BIT(0),
1934		.hw.init = &(struct clk_init_data) {
1935			.name = "gcc_lpass_core_axim_clk",
1936			.parent_hws = (const struct clk_hw *[]) {
1937				&lpass_axim_clk_src.clkr.hw,
1938			},
1939			.num_parents = 1,
1940			.flags = CLK_SET_RATE_PARENT,
1941			.ops = &clk_branch2_ops,
1942		},
1943	},
1944};
1945
1946static struct clk_branch gcc_lpass_sway_clk = {
1947	.halt_reg = 0x2e04c,
1948	.clkr = {
1949		.enable_reg = 0x2e04c,
1950		.enable_mask = BIT(0),
1951		.hw.init = &(struct clk_init_data) {
1952			.name = "gcc_lpass_sway_clk",
1953			.parent_hws = (const struct clk_hw *[]) {
1954				&lpass_sway_clk_src.clkr.hw,
1955			},
1956			.num_parents = 1,
1957			.flags = CLK_SET_RATE_PARENT,
1958			.ops = &clk_branch2_ops,
1959		},
1960	},
1961};
1962
1963static struct clk_branch gcc_mdio0_ahb_clk = {
1964	.halt_reg = 0x58004,
1965	.clkr = {
1966		.enable_reg = 0x58004,
1967		.enable_mask = BIT(0),
1968		.hw.init = &(struct clk_init_data) {
1969			.name = "gcc_mdioi0_ahb_clk",
1970			.parent_hws = (const struct clk_hw *[]) {
1971				&pcnoc_clk_src.hw,
1972			},
1973			.num_parents = 1,
1974			.flags = CLK_SET_RATE_PARENT,
1975			.ops = &clk_branch2_ops,
1976		},
1977	},
1978};
1979
1980static struct clk_branch gcc_mdio1_ahb_clk = {
1981	.halt_reg = 0x58014,
1982	.clkr = {
1983		.enable_reg = 0x58014,
1984		.enable_mask = BIT(0),
1985		.hw.init = &(struct clk_init_data) {
1986			.name = "gcc_mdio1_ahb_clk",
1987			.parent_hws = (const struct clk_hw *[]) {
1988				&pcnoc_clk_src.hw,
1989			},
1990			.num_parents = 1,
1991			.flags = CLK_SET_RATE_PARENT,
1992			.ops = &clk_branch2_ops,
1993		},
1994	},
1995};
1996
1997static struct clk_branch gcc_pcie0_ahb_clk = {
1998	.halt_reg = 0x75010,
1999	.clkr = {
2000		.enable_reg = 0x75010,
2001		.enable_mask = BIT(0),
2002		.hw.init = &(struct clk_init_data) {
2003			.name = "gcc_pcie0_ahb_clk",
2004			.parent_hws = (const struct clk_hw *[]) {
2005				&pcnoc_clk_src.hw,
2006			},
2007			.num_parents = 1,
2008			.flags = CLK_SET_RATE_PARENT,
2009			.ops = &clk_branch2_ops,
2010		},
2011	},
2012};
2013
2014static struct clk_branch gcc_pcie0_aux_clk = {
2015	.halt_reg = 0x75014,
2016	.clkr = {
2017		.enable_reg = 0x75014,
2018		.enable_mask = BIT(0),
2019		.hw.init = &(struct clk_init_data) {
2020			.name = "gcc_pcie0_aux_clk",
2021			.parent_hws = (const struct clk_hw *[]) {
2022				&pcie0_aux_clk_src.clkr.hw,
2023			},
2024			.num_parents = 1,
2025			.flags = CLK_SET_RATE_PARENT,
2026			.ops = &clk_branch2_ops,
2027		},
2028	},
2029};
2030
2031static struct clk_branch gcc_pcie0_axi_m_clk = {
2032	.halt_reg = 0x75008,
2033	.clkr = {
2034		.enable_reg = 0x75008,
2035		.enable_mask = BIT(0),
2036		.hw.init = &(struct clk_init_data) {
2037			.name = "gcc_pcie0_axi_m_clk",
2038			.parent_hws = (const struct clk_hw *[]) {
2039				&pcie0_axi_clk_src.clkr.hw,
2040			},
2041			.num_parents = 1,
2042			.flags = CLK_SET_RATE_PARENT,
2043			.ops = &clk_branch2_ops,
2044		},
2045	},
2046};
2047
2048static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
2049	.halt_reg = 0x75048,
2050	.clkr = {
2051		.enable_reg = 0x75048,
2052		.enable_mask = BIT(0),
2053		.hw.init = &(struct clk_init_data) {
2054			.name = "gcc_pcie0_axi_s_bridge_clk",
2055			.parent_hws = (const struct clk_hw *[]) {
2056				&pcie0_axi_clk_src.clkr.hw,
2057			},
2058			.num_parents = 1,
2059			.flags = CLK_SET_RATE_PARENT,
2060			.ops = &clk_branch2_ops,
2061		},
2062	},
2063};
2064
2065static struct clk_branch gcc_pcie0_axi_s_clk = {
2066	.halt_reg = 0x7500c,
2067	.clkr = {
2068		.enable_reg = 0x7500c,
2069		.enable_mask = BIT(0),
2070		.hw.init = &(struct clk_init_data) {
2071			.name = "gcc_pcie0_axi_s_clk",
2072			.parent_hws = (const struct clk_hw *[]) {
2073				&pcie0_axi_clk_src.clkr.hw,
2074			},
2075			.num_parents = 1,
2076			.flags = CLK_SET_RATE_PARENT,
2077			.ops = &clk_branch2_ops,
2078		},
2079	},
2080};
2081
2082static struct clk_branch gcc_pcie0_pipe_clk = {
2083	.halt_reg = 0x75018,
2084	.halt_check = BRANCH_HALT_DELAY,
2085	.halt_bit = 31,
2086	.clkr = {
2087		.enable_reg = 0x75018,
2088		.enable_mask = BIT(0),
2089		.hw.init = &(struct clk_init_data) {
2090			.name = "gcc_pcie0_pipe_clk",
2091			.parent_hws = (const struct clk_hw *[]) {
2092				&pcie0_pipe_clk_src.clkr.hw,
2093			},
2094			.num_parents = 1,
2095			.flags = CLK_SET_RATE_PARENT,
2096			.ops = &clk_branch2_ops,
2097		},
2098	},
2099};
2100
2101static struct clk_branch gcc_pcie1_ahb_clk = {
2102	.halt_reg = 0x76010,
2103	.clkr = {
2104		.enable_reg = 0x76010,
2105		.enable_mask = BIT(0),
2106		.hw.init = &(struct clk_init_data) {
2107			.name = "gcc_pcie1_ahb_clk",
2108			.parent_hws = (const struct clk_hw *[]) {
2109				&pcnoc_clk_src.hw,
2110			},
2111			.num_parents = 1,
2112			.flags = CLK_SET_RATE_PARENT,
2113			.ops = &clk_branch2_ops,
2114		},
2115	},
2116};
2117
2118static struct clk_branch gcc_pcie1_aux_clk = {
2119	.halt_reg = 0x76014,
2120	.clkr = {
2121		.enable_reg = 0x76014,
2122		.enable_mask = BIT(0),
2123		.hw.init = &(struct clk_init_data) {
2124			.name = "gcc_pcie1_aux_clk",
2125			.parent_hws = (const struct clk_hw *[]) {
2126				&pcie1_aux_clk_src.clkr.hw,
2127			},
2128			.num_parents = 1,
2129			.flags = CLK_SET_RATE_PARENT,
2130			.ops = &clk_branch2_ops,
2131		},
2132	},
2133};
2134
2135static struct clk_branch gcc_pcie1_axi_m_clk = {
2136	.halt_reg = 0x76008,
2137	.clkr = {
2138		.enable_reg = 0x76008,
2139		.enable_mask = BIT(0),
2140		.hw.init = &(struct clk_init_data) {
2141			.name = "gcc_pcie1_axi_m_clk",
2142			.parent_hws = (const struct clk_hw *[]) {
2143				&pcie1_axi_clk_src.clkr.hw,
2144			},
2145			.num_parents = 1,
2146			.flags = CLK_SET_RATE_PARENT,
2147			.ops = &clk_branch2_ops,
2148		},
2149	},
2150};
2151
2152static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
2153	.halt_reg = 0x76048,
2154	.clkr = {
2155		.enable_reg = 0x76048,
2156		.enable_mask = BIT(0),
2157		.hw.init = &(struct clk_init_data) {
2158			.name = "gcc_pcie1_axi_s_bridge_clk",
2159			.parent_hws = (const struct clk_hw *[]) {
2160				&pcie1_axi_clk_src.clkr.hw,
2161			},
2162			.num_parents = 1,
2163			.flags = CLK_SET_RATE_PARENT,
2164			.ops = &clk_branch2_ops,
2165		},
2166	},
2167};
2168
2169static struct clk_branch gcc_pcie1_axi_s_clk = {
2170	.halt_reg = 0x7600c,
2171	.clkr = {
2172		.enable_reg = 0x7600c,
2173		.enable_mask = BIT(0),
2174		.hw.init = &(struct clk_init_data) {
2175			.name = "gcc_pcie1_axi_s_clk",
2176			.parent_hws = (const struct clk_hw *[]) {
2177				&pcie1_axi_clk_src.clkr.hw,
2178			},
2179			.num_parents = 1,
2180			.flags = CLK_SET_RATE_PARENT,
2181			.ops = &clk_branch2_ops,
2182		},
2183	},
2184};
2185
2186static struct clk_branch gcc_pcie1_pipe_clk = {
2187	.halt_reg = 0x76018,
2188	.halt_check = BRANCH_HALT_DELAY,
2189	.halt_bit = 31,
2190	.clkr = {
2191		.enable_reg = 0x76018,
2192		.enable_mask = BIT(0),
2193		.hw.init = &(struct clk_init_data) {
2194			.name = "gcc_pcie1_pipe_clk",
2195			.parent_hws = (const struct clk_hw *[]) {
2196				&pcie1_pipe_clk_src.clkr.hw,
2197			},
2198			.num_parents = 1,
2199			.flags = CLK_SET_RATE_PARENT,
2200			.ops = &clk_branch2_ops,
2201		},
2202	},
2203};
2204
2205static struct clk_branch gcc_prng_ahb_clk = {
2206	.halt_reg = 0x13004,
2207	.halt_check = BRANCH_HALT_VOTED,
2208	.clkr = {
2209		.enable_reg = 0x0b004,
2210		.enable_mask = BIT(8),
2211		.hw.init = &(struct clk_init_data) {
2212			.name = "gcc_prng_ahb_clk",
2213			.parent_hws = (const struct clk_hw *[]) {
2214				&pcnoc_clk_src.hw,
2215			},
2216			.num_parents = 1,
2217			.flags = CLK_SET_RATE_PARENT,
2218			.ops = &clk_branch2_ops,
2219		},
2220	},
2221};
2222
2223static struct clk_branch gcc_q6_ahb_clk = {
2224	.halt_reg = 0x59138,
2225	.clkr = {
2226		.enable_reg = 0x59138,
2227		.enable_mask = BIT(0),
2228		.hw.init = &(struct clk_init_data) {
2229			.name = "gcc_q6_ahb_clk",
2230			.parent_hws = (const struct clk_hw *[]) {
2231				&wcss_ahb_clk_src.clkr.hw,
2232			},
2233			.num_parents = 1,
2234			.flags = CLK_SET_RATE_PARENT,
2235			.ops = &clk_branch2_ops,
2236		},
2237	},
2238};
2239
2240static struct clk_branch gcc_q6_ahb_s_clk = {
2241	.halt_reg = 0x5914c,
2242	.clkr = {
2243		.enable_reg = 0x5914c,
2244		.enable_mask = BIT(0),
2245		.hw.init = &(struct clk_init_data) {
2246			.name = "gcc_q6_ahb_s_clk",
2247			.parent_hws = (const struct clk_hw *[]) {
2248				&wcss_ahb_clk_src.clkr.hw,
2249			},
2250			.num_parents = 1,
2251			.flags = CLK_SET_RATE_PARENT,
2252			.ops = &clk_branch2_ops,
2253		},
2254	},
2255};
2256
2257static struct clk_branch gcc_q6_axim_clk = {
2258	.halt_reg = 0x5913c,
2259	.clkr = {
2260		.enable_reg = 0x5913c,
2261		.enable_mask = BIT(0),
2262		.hw.init = &(struct clk_init_data) {
2263			.name = "gcc_q6_axim_clk",
2264			.parent_hws = (const struct clk_hw *[]) {
2265				&q6_axi_clk_src.clkr.hw,
2266			},
2267			.num_parents = 1,
2268			.flags = CLK_SET_RATE_PARENT,
2269			.ops = &clk_branch2_ops,
2270		},
2271	},
2272};
2273
2274static struct clk_branch gcc_q6_axim2_clk = {
2275	.halt_reg = 0x59150,
2276	.clkr = {
2277		.enable_reg = 0x59150,
2278		.enable_mask = BIT(0),
2279		.hw.init = &(struct clk_init_data) {
2280			.name = "gcc_q6_axim2_clk",
2281			.parent_hws = (const struct clk_hw *[]) {
2282				&q6_axi_clk_src.clkr.hw,
2283			},
2284			.num_parents = 1,
2285			.flags = CLK_SET_RATE_PARENT,
2286			.ops = &clk_branch2_ops,
2287		},
2288	},
2289};
2290
2291static struct clk_branch gcc_q6_axis_clk = {
2292	.halt_reg = 0x59154,
2293	.clkr = {
2294		.enable_reg = 0x59154,
2295		.enable_mask = BIT(0),
2296		.hw.init = &(struct clk_init_data) {
2297			.name = "gcc_q6_axis_clk",
2298			.parent_hws = (const struct clk_hw *[]) {
2299				&system_noc_clk_src.hw,
2300			},
2301			.num_parents = 1,
2302			.flags = CLK_SET_RATE_PARENT,
2303			.ops = &clk_branch2_ops,
2304		},
2305	},
2306};
2307
2308static struct clk_branch gcc_q6_tsctr_1to2_clk = {
2309	.halt_reg = 0x59148,
2310	.clkr = {
2311		.enable_reg = 0x59148,
2312		.enable_mask = BIT(0),
2313		.hw.init = &(struct clk_init_data) {
2314			.name = "gcc_q6_tsctr_1to2_clk",
2315			.parent_hws = (const struct clk_hw *[]) {
2316				&qdss_tsctr_div2_clk_src.hw,
2317			},
2318			.num_parents = 1,
2319			.flags = CLK_SET_RATE_PARENT,
2320			.ops = &clk_branch2_ops,
2321		},
2322	},
2323};
2324
2325static struct clk_branch gcc_q6ss_atbm_clk = {
2326	.halt_reg = 0x59144,
2327	.clkr = {
2328		.enable_reg = 0x59144,
2329		.enable_mask = BIT(0),
2330		.hw.init = &(struct clk_init_data) {
2331			.name = "gcc_q6ss_atbm_clk",
2332			.parent_hws = (const struct clk_hw *[]) {
2333				&qdss_at_clk_src.clkr.hw,
2334			},
2335			.num_parents = 1,
2336			.flags = CLK_SET_RATE_PARENT,
2337			.ops = &clk_branch2_ops,
2338		},
2339	},
2340};
2341
2342static struct clk_branch gcc_q6ss_pclkdbg_clk = {
2343	.halt_reg = 0x59140,
2344	.clkr = {
2345		.enable_reg = 0x59140,
2346		.enable_mask = BIT(0),
2347		.hw.init = &(struct clk_init_data) {
2348			.name = "gcc_q6ss_pclkdbg_clk",
2349			.parent_hws = (const struct clk_hw *[]) {
2350				&qdss_dap_sync_clk_src.hw,
2351			},
2352			.num_parents = 1,
2353			.flags = CLK_SET_RATE_PARENT,
2354			.ops = &clk_branch2_ops,
2355		},
2356	},
2357};
2358
2359static struct clk_branch gcc_q6ss_trig_clk = {
2360	.halt_reg = 0x59128,
2361	.clkr = {
2362		.enable_reg = 0x59128,
2363		.enable_mask = BIT(0),
2364		.hw.init = &(struct clk_init_data) {
2365			.name = "gcc_q6ss_trig_clk",
2366			.parent_hws = (const struct clk_hw *[]) {
2367				&qdss_dap_sync_clk_src.hw,
2368			},
2369			.num_parents = 1,
2370			.flags = CLK_SET_RATE_PARENT,
2371			.ops = &clk_branch2_ops,
2372		},
2373	},
2374};
2375
2376static struct clk_branch gcc_qdss_at_clk = {
2377	.halt_reg = 0x29024,
2378	.clkr = {
2379		.enable_reg = 0x29024,
2380		.enable_mask = BIT(0),
2381		.hw.init = &(struct clk_init_data) {
2382			.name = "gcc_qdss_at_clk",
2383			.parent_hws = (const struct clk_hw *[]) {
2384				&qdss_at_clk_src.clkr.hw,
2385			},
2386			.num_parents = 1,
2387			.flags = CLK_SET_RATE_PARENT,
2388			.ops = &clk_branch2_ops,
2389		},
2390	},
2391};
2392
2393static struct clk_branch gcc_qdss_dap_clk = {
2394	.halt_reg = 0x29084,
2395	.clkr = {
2396		.enable_reg = 0x29084,
2397		.enable_mask = BIT(0),
2398		.hw.init = &(struct clk_init_data) {
2399			.name = "gcc_qdss_dap_clk",
2400			.parent_hws = (const struct clk_hw *[]) {
2401				&qdss_tsctr_clk_src.clkr.hw,
2402			},
2403			.num_parents = 1,
2404			.flags = CLK_SET_RATE_PARENT,
2405			.ops = &clk_branch2_ops,
2406		},
2407	},
2408};
2409
2410static struct clk_branch gcc_qdss_cfg_ahb_clk = {
2411	.halt_reg = 0x29008,
2412	.clkr = {
2413		.enable_reg = 0x29008,
2414		.enable_mask = BIT(0),
2415		.hw.init = &(struct clk_init_data) {
2416			.name = "gcc_qdss_cfg_ahb_clk",
2417			.parent_hws = (const struct clk_hw *[]) {
2418				&pcnoc_clk_src.hw,
2419			},
2420			.num_parents = 1,
2421			.flags = CLK_SET_RATE_PARENT,
2422			.ops = &clk_branch2_ops,
2423		},
2424	},
2425};
2426
2427static struct clk_branch gcc_qdss_dap_ahb_clk = {
2428	.halt_reg = 0x29004,
2429	.clkr = {
2430		.enable_reg = 0x29004,
2431		.enable_mask = BIT(0),
2432		.hw.init = &(struct clk_init_data) {
2433			.name = "gcc_qdss_dap_ahb_clk",
2434			.parent_hws = (const struct clk_hw *[]) {
2435				&pcnoc_clk_src.hw,
2436			},
2437			.num_parents = 1,
2438			.flags = CLK_SET_RATE_PARENT,
2439			.ops = &clk_branch2_ops,
2440		},
2441	},
2442};
2443
2444static struct clk_branch gcc_qdss_etr_usb_clk = {
2445	.halt_reg = 0x29028,
2446	.clkr = {
2447		.enable_reg = 0x29028,
2448		.enable_mask = BIT(0),
2449		.hw.init = &(struct clk_init_data) {
2450			.name = "gcc_qdss_etr_usb_clk",
2451			.parent_hws = (const struct clk_hw *[]) {
2452				&system_noc_clk_src.hw,
2453			},
2454			.num_parents = 1,
2455			.flags = CLK_SET_RATE_PARENT,
2456			.ops = &clk_branch2_ops,
2457		},
2458	},
2459};
2460
2461static struct clk_branch gcc_qdss_eud_at_clk = {
2462	.halt_reg = 0x29020,
2463	.clkr = {
2464		.enable_reg = 0x29020,
2465		.enable_mask = BIT(0),
2466		.hw.init = &(struct clk_init_data) {
2467			.name = "gcc_qdss_eud_at_clk",
2468			.parent_hws = (const struct clk_hw *[]) {
2469				&eud_at_clk_src.hw,
2470			},
2471			.num_parents = 1,
2472			.flags = CLK_SET_RATE_PARENT,
2473			.ops = &clk_branch2_ops,
2474		},
2475	},
2476};
2477
2478static struct clk_branch gcc_qdss_stm_clk = {
2479	.halt_reg = 0x29044,
2480	.clkr = {
2481		.enable_reg = 0x29044,
2482		.enable_mask = BIT(0),
2483		.hw.init = &(struct clk_init_data) {
2484			.name = "gcc_qdss_stm_clk",
2485			.parent_hws = (const struct clk_hw *[]) {
2486				&qdss_stm_clk_src.clkr.hw,
2487			},
2488			.num_parents = 1,
2489			.flags = CLK_SET_RATE_PARENT,
2490			.ops = &clk_branch2_ops,
2491		},
2492	},
2493};
2494
2495static struct clk_branch gcc_qdss_traceclkin_clk = {
2496	.halt_reg = 0x29060,
2497	.clkr = {
2498		.enable_reg = 0x29060,
2499		.enable_mask = BIT(0),
2500		.hw.init = &(struct clk_init_data) {
2501			.name = "gcc_qdss_traceclkin_clk",
2502			.parent_hws = (const struct clk_hw *[]) {
2503				&qdss_traceclkin_clk_src.clkr.hw,
2504			},
2505			.num_parents = 1,
2506			.flags = CLK_SET_RATE_PARENT,
2507			.ops = &clk_branch2_ops,
2508		},
2509	},
2510};
2511
2512static struct clk_branch gcc_qdss_tsctr_div8_clk = {
2513	.halt_reg = 0x2908c,
2514	.clkr = {
2515		.enable_reg = 0x2908c,
2516		.enable_mask = BIT(0),
2517		.hw.init = &(struct clk_init_data) {
2518			.name = "gcc_qdss_tsctr_div8_clk",
2519			.parent_hws = (const struct clk_hw *[]) {
2520				&qdss_tsctr_clk_src.clkr.hw,
2521			},
2522			.num_parents = 1,
2523			.flags = CLK_SET_RATE_PARENT,
2524			.ops = &clk_branch2_ops,
2525		},
2526	},
2527};
2528
2529static struct clk_branch gcc_qpic_ahb_clk = {
2530	.halt_reg = 0x57024,
2531	.clkr = {
2532		.enable_reg = 0x57024,
2533		.enable_mask = BIT(0),
2534		.hw.init = &(struct clk_init_data) {
2535			.name = "gcc_qpic_ahb_clk",
2536			.parent_hws = (const struct clk_hw *[]) {
2537				&pcnoc_clk_src.hw,
2538			},
2539			.num_parents = 1,
2540			.flags = CLK_SET_RATE_PARENT,
2541			.ops = &clk_branch2_ops,
2542		},
2543	},
2544};
2545
2546static struct clk_branch gcc_qpic_clk = {
2547	.halt_reg = 0x57020,
2548	.clkr = {
2549		.enable_reg = 0x57020,
2550		.enable_mask = BIT(0),
2551		.hw.init = &(struct clk_init_data) {
2552			.name = "gcc_qpic_clk",
2553			.parent_hws = (const struct clk_hw *[]) {
2554				&pcnoc_clk_src.hw,
2555			},
2556			.num_parents = 1,
2557			.flags = CLK_SET_RATE_PARENT,
2558			.ops = &clk_branch2_ops,
2559		},
2560	},
2561};
2562
2563static struct clk_branch gcc_qpic_io_macro_clk = {
2564	.halt_reg = 0x5701c,
2565	.clkr = {
2566		.enable_reg = 0x5701c,
2567		.enable_mask = BIT(0),
2568		.hw.init = &(struct clk_init_data) {
2569			.name = "gcc_qpic_io_macro_clk",
2570			.parent_hws = (const struct clk_hw *[]) {
2571				&qpic_io_macro_clk_src.clkr.hw,
2572			},
2573			.num_parents = 1,
2574			.flags = CLK_SET_RATE_PARENT,
2575			.ops = &clk_branch2_ops,
2576		},
2577	},
2578};
2579
2580static struct clk_branch gcc_sdcc1_ahb_clk = {
2581	.halt_reg = 0x4201c,
2582	.clkr = {
2583		.enable_reg = 0x4201c,
2584		.enable_mask = BIT(0),
2585		.hw.init = &(struct clk_init_data) {
2586			.name = "gcc_sdcc1_ahb_clk",
2587			.parent_hws = (const struct clk_hw *[]) {
2588				&pcnoc_clk_src.hw,
2589			},
2590			.num_parents = 1,
2591			.flags = CLK_SET_RATE_PARENT,
2592			.ops = &clk_branch2_ops,
2593		},
2594	},
2595};
2596
2597static struct clk_branch gcc_sdcc1_apps_clk = {
2598	.halt_reg = 0x42018,
2599	.clkr = {
2600		.enable_reg = 0x42018,
2601		.enable_mask = BIT(0),
2602		.hw.init = &(struct clk_init_data) {
2603			.name = "gcc_sdcc1_apps_clk",
2604			.parent_hws = (const struct clk_hw *[]) {
2605				&sdcc1_apps_clk_src.clkr.hw,
2606			},
2607			.num_parents = 1,
2608			.flags = CLK_SET_RATE_PARENT,
2609			.ops = &clk_branch2_ops,
2610		},
2611	},
2612};
2613
2614static struct clk_branch gcc_snoc_gmac0_ahb_clk = {
2615	.halt_reg = 0x260a0,
2616	.clkr = {
2617		.enable_reg = 0x260a0,
2618		.enable_mask = BIT(0),
2619		.hw.init = &(struct clk_init_data) {
2620			.name = "gcc_snoc_gmac0_ahb_clk",
2621			.parent_hws = (const struct clk_hw *[]) {
2622				&gmac_clk_src.clkr.hw,
2623			},
2624			.num_parents = 1,
2625			.flags = CLK_SET_RATE_PARENT,
2626			.ops = &clk_branch2_ops,
2627		},
2628	},
2629};
2630
2631static struct clk_branch gcc_snoc_gmac0_axi_clk = {
2632	.halt_reg = 0x26084,
2633	.clkr = {
2634		.enable_reg = 0x26084,
2635		.enable_mask = BIT(0),
2636		.hw.init = &(struct clk_init_data) {
2637			.name = "gcc_snoc_gmac0_axi_clk",
2638			.parent_hws = (const struct clk_hw *[]) {
2639				&gmac_clk_src.clkr.hw,
2640			},
2641			.num_parents = 1,
2642			.flags = CLK_SET_RATE_PARENT,
2643			.ops = &clk_branch2_ops,
2644		},
2645	},
2646};
2647
2648static struct clk_branch gcc_snoc_gmac1_ahb_clk = {
2649	.halt_reg = 0x260a4,
2650	.clkr = {
2651		.enable_reg = 0x260a4,
2652		.enable_mask = BIT(0),
2653		.hw.init = &(struct clk_init_data) {
2654			.name = "gcc_snoc_gmac1_ahb_clk",
2655			.parent_hws = (const struct clk_hw *[]) {
2656				&gmac_clk_src.clkr.hw,
2657			},
2658			.num_parents = 1,
2659			.flags = CLK_SET_RATE_PARENT,
2660			.ops = &clk_branch2_ops,
2661		},
2662	},
2663};
2664
2665static struct clk_branch gcc_snoc_gmac1_axi_clk = {
2666	.halt_reg = 0x26088,
2667	.clkr = {
2668		.enable_reg = 0x26088,
2669		.enable_mask = BIT(0),
2670		.hw.init = &(struct clk_init_data) {
2671			.name = "gcc_snoc_gmac1_axi_clk",
2672			.parent_hws = (const struct clk_hw *[]) {
2673				&gmac_clk_src.clkr.hw,
2674			},
2675			.num_parents = 1,
2676			.flags = CLK_SET_RATE_PARENT,
2677			.ops = &clk_branch2_ops,
2678		},
2679	},
2680};
2681
2682static struct clk_branch gcc_snoc_lpass_axim_clk = {
2683	.halt_reg = 0x26074,
2684	.clkr = {
2685		.enable_reg = 0x26074,
2686		.enable_mask = BIT(0),
2687		.hw.init = &(struct clk_init_data) {
2688			.name = "gcc_snoc_lpass_axim_clk",
2689			.parent_hws = (const struct clk_hw *[]) {
2690				&lpass_axim_clk_src.clkr.hw,
2691			},
2692			.num_parents = 1,
2693			.flags = CLK_SET_RATE_PARENT,
2694			.ops = &clk_branch2_ops,
2695		},
2696	},
2697};
2698
2699static struct clk_branch gcc_snoc_lpass_sway_clk = {
2700	.halt_reg = 0x26078,
2701	.clkr = {
2702		.enable_reg = 0x26078,
2703		.enable_mask = BIT(0),
2704		.hw.init = &(struct clk_init_data) {
2705			.name = "gcc_snoc_lpass_sway_clk",
2706			.parent_hws = (const struct clk_hw *[]) {
2707				&lpass_sway_clk_src.clkr.hw,
2708			},
2709			.num_parents = 1,
2710			.flags = CLK_SET_RATE_PARENT,
2711			.ops = &clk_branch2_ops,
2712		},
2713	},
2714};
2715
2716static struct clk_branch gcc_snoc_ubi0_axi_clk = {
2717	.halt_reg = 0x26094,
2718	.clkr = {
2719		.enable_reg = 0x26094,
2720		.enable_mask = BIT(0),
2721		.hw.init = &(struct clk_init_data) {
2722			.name = "gcc_snoc_ubi0_axi_clk",
2723			.parent_hws = (const struct clk_hw *[]) {
2724				&ubi0_axi_clk_src.clkr.hw,
2725			},
2726			.num_parents = 1,
2727			.flags = CLK_SET_RATE_PARENT,
2728			.ops = &clk_branch2_ops,
2729		},
2730	},
2731};
2732
2733static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
2734	.halt_reg = 0x26048,
2735	.clkr = {
2736		.enable_reg = 0x26048,
2737		.enable_mask = BIT(0),
2738		.hw.init = &(struct clk_init_data) {
2739			.name = "gcc_sys_noc_pcie0_axi_clk",
2740			.parent_hws = (const struct clk_hw *[]) {
2741				&pcie0_axi_clk_src.clkr.hw,
2742			},
2743			.num_parents = 1,
2744			.flags = CLK_SET_RATE_PARENT,
2745			.ops = &clk_branch2_ops,
2746		},
2747	},
2748};
2749
2750static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
2751	.halt_reg = 0x2604c,
2752	.clkr = {
2753		.enable_reg = 0x2604c,
2754		.enable_mask = BIT(0),
2755		.hw.init = &(struct clk_init_data) {
2756			.name = "gcc_sys_noc_pcie1_axi_clk",
2757			.parent_hws = (const struct clk_hw *[]) {
2758				&pcie1_axi_clk_src.clkr.hw,
2759			},
2760			.num_parents = 1,
2761			.flags = CLK_SET_RATE_PARENT,
2762			.ops = &clk_branch2_ops,
2763		},
2764	},
2765};
2766
2767static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
2768	.halt_reg = 0x26024,
2769	.clkr = {
2770		.enable_reg = 0x26024,
2771		.enable_mask = BIT(0),
2772		.hw.init = &(struct clk_init_data) {
2773			.name = "gcc_sys_noc_qdss_stm_axi_clk",
2774			.parent_hws = (const struct clk_hw *[]) {
2775				&qdss_stm_clk_src.clkr.hw,
2776			},
2777			.num_parents = 1,
2778			.flags = CLK_SET_RATE_PARENT,
2779			.ops = &clk_branch2_ops,
2780		},
2781	},
2782};
2783
2784static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
2785	.halt_reg = 0x26040,
2786	.clkr = {
2787		.enable_reg = 0x26040,
2788		.enable_mask = BIT(0),
2789		.hw.init = &(struct clk_init_data) {
2790			.name = "gcc_sys_noc_usb0_axi_clk",
2791			.parent_hws = (const struct clk_hw *[]) {
2792				&usb0_master_clk_src.clkr.hw,
2793			},
2794			.num_parents = 1,
2795			.flags = CLK_SET_RATE_PARENT,
2796			.ops = &clk_branch2_ops,
2797		},
2798	},
2799};
2800
2801static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
2802	.halt_reg = 0x26034,
2803	.clkr = {
2804		.enable_reg = 0x26034,
2805		.enable_mask = BIT(0),
2806		.hw.init = &(struct clk_init_data) {
2807			.name = "gcc_sys_noc_wcss_ahb_clk",
2808			.parent_hws = (const struct clk_hw *[]) {
2809				&wcss_ahb_clk_src.clkr.hw,
2810			},
2811			.num_parents = 1,
2812			.flags = CLK_SET_RATE_PARENT,
2813			.ops = &clk_branch2_ops,
2814		},
2815	},
2816};
2817
2818static struct clk_branch gcc_ubi0_axi_clk = {
2819	.halt_reg = 0x68200,
2820	.halt_check = BRANCH_HALT_DELAY,
2821	.clkr = {
2822		.enable_reg = 0x68200,
2823		.enable_mask = BIT(0),
2824		.hw.init = &(struct clk_init_data) {
2825			.name = "gcc_ubi0_axi_clk",
2826			.parent_hws = (const struct clk_hw *[]) {
2827				&ubi0_axi_clk_src.clkr.hw,
2828			},
2829			.num_parents = 1,
2830			.flags = CLK_SET_RATE_PARENT,
2831			.ops = &clk_branch2_ops,
2832		},
2833	},
2834};
2835
2836static struct clk_branch gcc_ubi0_cfg_clk = {
2837	.halt_reg = 0x68160,
2838	.halt_check = BRANCH_HALT_DELAY,
2839	.clkr = {
2840		.enable_reg = 0x68160,
2841		.enable_mask = BIT(0),
2842		.hw.init = &(struct clk_init_data) {
2843			.name = "gcc_ubi0_cfg_clk",
2844			.parent_hws = (const struct clk_hw *[]) {
2845				&pcnoc_clk_src.hw,
2846			},
2847			.num_parents = 1,
2848			.flags = CLK_SET_RATE_PARENT,
2849			.ops = &clk_branch2_ops,
2850		},
2851	},
2852};
2853
2854static struct clk_branch gcc_ubi0_dbg_clk = {
2855	.halt_reg = 0x68214,
2856	.halt_check = BRANCH_HALT_DELAY,
2857	.clkr = {
2858		.enable_reg = 0x68214,
2859		.enable_mask = BIT(0),
2860		.hw.init = &(struct clk_init_data) {
2861			.name = "gcc_ubi0_dbg_clk",
2862			.parent_hws = (const struct clk_hw *[]) {
2863				&qdss_tsctr_clk_src.clkr.hw,
2864			},
2865			.num_parents = 1,
2866			.flags = CLK_SET_RATE_PARENT,
2867			.ops = &clk_branch2_ops,
2868		},
2869	},
2870};
2871
2872static struct clk_branch gcc_ubi0_core_clk = {
2873	.halt_reg = 0x68210,
2874	.halt_check = BRANCH_HALT_DELAY,
2875	.clkr = {
2876		.enable_reg = 0x68210,
2877		.enable_mask = BIT(0),
2878		.hw.init = &(struct clk_init_data) {
2879			.name = "gcc_ubi0_core_clk",
2880			.parent_hws = (const struct clk_hw *[]) {
2881				&ubi0_core_clk_src.clkr.hw,
2882			},
2883			.num_parents = 1,
2884			.flags = CLK_SET_RATE_PARENT,
2885			.ops = &clk_branch2_ops,
2886		},
2887	},
2888};
2889
2890static struct clk_branch gcc_ubi0_nc_axi_clk = {
2891	.halt_reg = 0x68204,
2892	.halt_check = BRANCH_HALT_DELAY,
2893	.clkr = {
2894		.enable_reg = 0x68204,
2895		.enable_mask = BIT(0),
2896		.hw.init = &(struct clk_init_data) {
2897			.name = "gcc_ubi0_nc_axi_clk",
2898			.parent_hws = (const struct clk_hw *[]) {
2899				&system_noc_clk_src.hw,
2900			},
2901			.num_parents = 1,
2902			.flags = CLK_SET_RATE_PARENT,
2903			.ops = &clk_branch2_ops,
2904		},
2905	},
2906};
2907
2908static struct clk_branch gcc_ubi0_utcm_clk = {
2909	.halt_reg = 0x68208,
2910	.halt_check = BRANCH_HALT_DELAY,
2911	.clkr = {
2912		.enable_reg = 0x68208,
2913		.enable_mask = BIT(0),
2914		.hw.init = &(struct clk_init_data) {
2915			.name = "gcc_ubi0_utcm_clk",
2916			.parent_hws = (const struct clk_hw *[]) {
2917				&system_noc_clk_src.hw,
2918			},
2919			.num_parents = 1,
2920			.flags = CLK_SET_RATE_PARENT,
2921			.ops = &clk_branch2_ops,
2922		},
2923	},
2924};
2925
2926static struct clk_branch gcc_uniphy_ahb_clk = {
2927	.halt_reg = 0x56108,
2928	.clkr = {
2929		.enable_reg = 0x56108,
2930		.enable_mask = BIT(0),
2931		.hw.init = &(struct clk_init_data) {
2932			.name = "gcc_uniphy_ahb_clk",
2933			.parent_hws = (const struct clk_hw *[]) {
2934				&pcnoc_clk_src.hw,
2935			},
2936			.num_parents = 1,
2937			.flags = CLK_SET_RATE_PARENT,
2938			.ops = &clk_branch2_ops,
2939		},
2940	},
2941};
2942
2943static struct clk_branch gcc_uniphy_rx_clk = {
2944	.halt_reg = 0x56110,
2945	.clkr = {
2946		.enable_reg = 0x56110,
2947		.enable_mask = BIT(0),
2948		.hw.init = &(struct clk_init_data) {
2949			.name = "gcc_uniphy_rx_clk",
2950			.parent_hws = (const struct clk_hw *[]) {
2951				&gmac1_rx_div_clk_src.clkr.hw,
2952			},
2953			.num_parents = 1,
2954			.ops = &clk_branch2_ops,
2955			.flags = CLK_SET_RATE_PARENT,
2956		},
2957	},
2958};
2959
2960static struct clk_branch gcc_uniphy_tx_clk = {
2961	.halt_reg = 0x56114,
2962	.clkr = {
2963		.enable_reg = 0x56114,
2964		.enable_mask = BIT(0),
2965		.hw.init = &(struct clk_init_data) {
2966			.name = "gcc_uniphy_tx_clk",
2967			.parent_hws = (const struct clk_hw *[]) {
2968				&gmac1_tx_div_clk_src.clkr.hw,
2969			},
2970			.num_parents = 1,
2971			.ops = &clk_branch2_ops,
2972			.flags = CLK_SET_RATE_PARENT,
2973		},
2974	},
2975};
2976
2977static struct clk_branch gcc_uniphy_sys_clk = {
2978	.halt_reg = 0x5610c,
2979	.clkr = {
2980		.enable_reg = 0x5610c,
2981		.enable_mask = BIT(0),
2982		.hw.init = &(struct clk_init_data) {
2983			.name = "gcc_uniphy_sys_clk",
2984			.parent_hws = (const struct clk_hw *[]) {
2985				&gcc_xo_clk_src.clkr.hw,
2986			},
2987			.num_parents = 1,
2988			.flags = CLK_SET_RATE_PARENT,
2989			.ops = &clk_branch2_ops,
2990		},
2991	},
2992};
2993
2994static struct clk_branch gcc_usb0_aux_clk = {
2995	.halt_reg = 0x3e044,
2996	.clkr = {
2997		.enable_reg = 0x3e044,
2998		.enable_mask = BIT(0),
2999		.hw.init = &(struct clk_init_data) {
3000			.name = "gcc_usb0_aux_clk",
3001			.parent_hws = (const struct clk_hw *[]) {
3002				&usb0_aux_clk_src.clkr.hw,
3003			},
3004			.num_parents = 1,
3005			.flags = CLK_SET_RATE_PARENT,
3006			.ops = &clk_branch2_ops,
3007		},
3008	},
3009};
3010
3011static struct clk_branch gcc_usb0_eud_at_clk = {
3012	.halt_reg = 0x3e04c,
3013	.halt_check = BRANCH_HALT_VOTED,
3014	.clkr = {
3015		.enable_reg = 0x3e04c,
3016		.enable_mask = BIT(0),
3017		.hw.init = &(struct clk_init_data) {
3018			.name = "gcc_usb0_eud_at_clk",
3019			.parent_hws = (const struct clk_hw *[]) {
3020				&eud_at_clk_src.hw,
3021			},
3022			.num_parents = 1,
3023			.flags = CLK_SET_RATE_PARENT,
3024			.ops = &clk_branch2_ops,
3025		},
3026	},
3027};
3028
3029static struct clk_branch gcc_usb0_lfps_clk = {
3030	.halt_reg = 0x3e050,
3031	.clkr = {
3032		.enable_reg = 0x3e050,
3033		.enable_mask = BIT(0),
3034		.hw.init = &(struct clk_init_data) {
3035			.name = "gcc_usb0_lfps_clk",
3036			.parent_hws = (const struct clk_hw *[]) {
3037				&usb0_lfps_clk_src.clkr.hw,
3038			},
3039			.num_parents = 1,
3040			.flags = CLK_SET_RATE_PARENT,
3041			.ops = &clk_branch2_ops,
3042		},
3043	},
3044};
3045
3046static struct clk_branch gcc_usb0_master_clk = {
3047	.halt_reg = 0x3e000,
3048	.clkr = {
3049		.enable_reg = 0x3e000,
3050		.enable_mask = BIT(0),
3051		.hw.init = &(struct clk_init_data) {
3052			.name = "gcc_usb0_master_clk",
3053			.parent_hws = (const struct clk_hw *[]) {
3054				&usb0_master_clk_src.clkr.hw,
3055			},
3056			.num_parents = 1,
3057			.flags = CLK_SET_RATE_PARENT,
3058			.ops = &clk_branch2_ops,
3059		},
3060	},
3061};
3062
3063static struct clk_branch gcc_usb0_mock_utmi_clk = {
3064	.halt_reg = 0x3e008,
3065	.clkr = {
3066		.enable_reg = 0x3e008,
3067		.enable_mask = BIT(0),
3068		.hw.init = &(struct clk_init_data) {
3069			.name = "gcc_usb0_mock_utmi_clk",
3070			.parent_hws = (const struct clk_hw *[]) {
3071				&usb0_mock_utmi_clk_src.clkr.hw,
3072			},
3073			.num_parents = 1,
3074			.flags = CLK_SET_RATE_PARENT,
3075			.ops = &clk_branch2_ops,
3076		},
3077	},
3078};
3079
3080static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
3081	.halt_reg = 0x3e080,
3082	.clkr = {
3083		.enable_reg = 0x3e080,
3084		.enable_mask = BIT(0),
3085		.hw.init = &(struct clk_init_data) {
3086			.name = "gcc_usb0_phy_cfg_ahb_clk",
3087			.parent_hws = (const struct clk_hw *[]) {
3088				&pcnoc_clk_src.hw,
3089			},
3090			.num_parents = 1,
3091			.flags = CLK_SET_RATE_PARENT,
3092			.ops = &clk_branch2_ops,
3093		},
3094	},
3095};
3096
3097static struct clk_branch gcc_usb0_sleep_clk = {
3098	.halt_reg = 0x3e004,
3099	.clkr = {
3100		.enable_reg = 0x3e004,
3101		.enable_mask = BIT(0),
3102		.hw.init = &(struct clk_init_data) {
3103			.name = "gcc_usb0_sleep_clk",
3104			.parent_hws = (const struct clk_hw *[]) {
3105				&gcc_sleep_clk_src.clkr.hw,
3106			},
3107			.num_parents = 1,
3108			.flags = CLK_SET_RATE_PARENT,
3109			.ops = &clk_branch2_ops,
3110		},
3111	},
3112};
3113
3114static struct clk_branch gcc_usb0_pipe_clk = {
3115	.halt_reg = 0x3e040,
3116	.halt_check = BRANCH_HALT_DELAY,
3117	.clkr = {
3118		.enable_reg = 0x3e040,
3119		.enable_mask = BIT(0),
3120		.hw.init = &(struct clk_init_data) {
3121			.name = "gcc_usb0_pipe_clk",
3122			.parent_hws = (const struct clk_hw *[]) {
3123				&usb0_pipe_clk_src.clkr.hw,
3124			},
3125			.num_parents = 1,
3126			.flags = CLK_SET_RATE_PARENT,
3127			.ops = &clk_branch2_ops,
3128		},
3129	},
3130};
3131
3132static struct clk_branch gcc_wcss_acmt_clk = {
3133	.halt_reg = 0x59064,
3134	.clkr = {
3135		.enable_reg = 0x59064,
3136		.enable_mask = BIT(0),
3137		.hw.init = &(struct clk_init_data) {
3138			.name = "gcc_wcss_acmt_clk",
3139			.parent_hws = (const struct clk_hw *[]) {
3140				&wcss_ahb_clk_src.clkr.hw,
3141			},
3142			.num_parents = 1,
3143			.flags = CLK_SET_RATE_PARENT,
3144			.ops = &clk_branch2_ops,
3145		},
3146	},
3147};
3148
3149static struct clk_branch gcc_wcss_ahb_s_clk = {
3150	.halt_reg = 0x59034,
3151	.clkr = {
3152		.enable_reg = 0x59034,
3153		.enable_mask = BIT(0),
3154		.hw.init = &(struct clk_init_data) {
3155			.name = "gcc_wcss_ahb_s_clk",
3156			.parent_hws = (const struct clk_hw *[]) {
3157				&wcss_ahb_clk_src.clkr.hw,
3158			},
3159			.num_parents = 1,
3160			.flags = CLK_SET_RATE_PARENT,
3161			.ops = &clk_branch2_ops,
3162		},
3163	},
3164};
3165
3166static struct clk_branch gcc_wcss_axi_m_clk = {
3167	.halt_reg = 0x5903c,
3168	.clkr = {
3169		.enable_reg = 0x5903c,
3170		.enable_mask = BIT(0),
3171		.hw.init = &(struct clk_init_data) {
3172			.name = "gcc_wcss_axi_m_clk",
3173			.parent_hws = (const struct clk_hw *[]) {
3174				&system_noc_clk_src.hw,
3175			},
3176			.num_parents = 1,
3177			.flags = CLK_SET_RATE_PARENT,
3178			.ops = &clk_branch2_ops,
3179		},
3180	},
3181};
3182
3183static struct clk_branch gcc_wcss_axi_s_clk = {
3184	.halt_reg = 0x59068,
3185	.clkr = {
3186		.enable_reg = 0x59068,
3187		.enable_mask = BIT(0),
3188		.hw.init = &(struct clk_init_data) {
3189			.name = "gcc_wi_s_clk",
3190			.parent_hws = (const struct clk_hw *[]) {
3191				&system_noc_clk_src.hw,
3192			},
3193			.num_parents = 1,
3194			.flags = CLK_SET_RATE_PARENT,
3195			.ops = &clk_branch2_ops,
3196		},
3197	},
3198};
3199
3200static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
3201	.halt_reg = 0x59050,
3202	.clkr = {
3203		.enable_reg = 0x59050,
3204		.enable_mask = BIT(0),
3205		.hw.init = &(struct clk_init_data) {
3206			.name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
3207			.parent_hws = (const struct clk_hw *[]) {
3208				&qdss_dap_sync_clk_src.hw,
3209			},
3210			.num_parents = 1,
3211			.flags = CLK_SET_RATE_PARENT,
3212			.ops = &clk_branch2_ops,
3213		},
3214	},
3215};
3216
3217static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
3218	.halt_reg = 0x59040,
3219	.clkr = {
3220		.enable_reg = 0x59040,
3221		.enable_mask = BIT(0),
3222		.hw.init = &(struct clk_init_data) {
3223			.name = "gcc_wcss_dbg_ifc_apb_clk",
3224			.parent_hws = (const struct clk_hw *[]) {
3225				&qdss_dap_sync_clk_src.hw,
3226			},
3227			.num_parents = 1,
3228			.flags = CLK_SET_RATE_PARENT,
3229			.ops = &clk_branch2_ops,
3230		},
3231	},
3232};
3233
3234static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
3235	.halt_reg = 0x59054,
3236	.clkr = {
3237		.enable_reg = 0x59054,
3238		.enable_mask = BIT(0),
3239		.hw.init = &(struct clk_init_data) {
3240			.name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
3241			.parent_hws = (const struct clk_hw *[]) {
3242				&qdss_at_clk_src.clkr.hw,
3243			},
3244			.num_parents = 1,
3245			.flags = CLK_SET_RATE_PARENT,
3246			.ops = &clk_branch2_ops,
3247		},
3248	},
3249};
3250
3251static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
3252	.halt_reg = 0x59044,
3253	.clkr = {
3254		.enable_reg = 0x59044,
3255		.enable_mask = BIT(0),
3256		.hw.init = &(struct clk_init_data) {
3257			.name = "gcc_wcss_dbg_ifc_atb_clk",
3258			.parent_hws = (const struct clk_hw *[]) {
3259				&qdss_at_clk_src.clkr.hw,
3260			},
3261			.num_parents = 1,
3262			.flags = CLK_SET_RATE_PARENT,
3263			.ops = &clk_branch2_ops,
3264		},
3265	},
3266};
3267
3268static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = {
3269	.halt_reg = 0x59060,
3270	.clkr = {
3271		.enable_reg = 0x59060,
3272		.enable_mask = BIT(0),
3273		.hw.init = &(struct clk_init_data) {
3274			.name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk",
3275			.parent_hws = (const struct clk_hw *[]) {
3276				&qdss_dap_sync_clk_src.hw,
3277			},
3278			.num_parents = 1,
3279			.flags = CLK_SET_RATE_PARENT,
3280			.ops = &clk_branch2_ops,
3281		},
3282	},
3283};
3284
3285static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
3286	.halt_reg = 0x5905c,
3287	.clkr = {
3288		.enable_reg = 0x5905c,
3289		.enable_mask = BIT(0),
3290		.hw.init = &(struct clk_init_data) {
3291			.name = "gcc_wcss_dbg_ifc_dapbus_clk",
3292			.parent_hws = (const struct clk_hw *[]) {
3293				&qdss_dap_sync_clk_src.hw,
3294			},
3295			.num_parents = 1,
3296			.flags = CLK_SET_RATE_PARENT,
3297			.ops = &clk_branch2_ops,
3298		},
3299	},
3300};
3301
3302static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
3303	.halt_reg = 0x59058,
3304	.clkr = {
3305		.enable_reg = 0x59058,
3306		.enable_mask = BIT(0),
3307		.hw.init = &(struct clk_init_data) {
3308			.name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
3309			.parent_hws = (const struct clk_hw *[]) {
3310				&qdss_tsctr_div2_clk_src.hw,
3311			},
3312			.num_parents = 1,
3313			.flags = CLK_SET_RATE_PARENT,
3314			.ops = &clk_branch2_ops,
3315		},
3316	},
3317};
3318
3319static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
3320	.halt_reg = 0x59048,
3321	.clkr = {
3322		.enable_reg = 0x59048,
3323		.enable_mask = BIT(0),
3324		.hw.init = &(struct clk_init_data) {
3325			.name = "gcc_wcss_dbg_ifc_nts_clk",
3326			.parent_hws = (const struct clk_hw *[]) {
3327				&qdss_tsctr_div2_clk_src.hw,
3328			},
3329			.num_parents = 1,
3330			.flags = CLK_SET_RATE_PARENT,
3331			.ops = &clk_branch2_ops,
3332		},
3333	},
3334};
3335
3336static struct clk_branch gcc_wcss_ecahb_clk = {
3337	.halt_reg = 0x59038,
3338	.clkr = {
3339		.enable_reg = 0x59038,
3340		.enable_mask = BIT(0),
3341		.hw.init = &(struct clk_init_data) {
3342			.name = "gcc_wcss_ecahb_clk",
3343			.parent_hws = (const struct clk_hw *[]) {
3344				&wcss_ahb_clk_src.clkr.hw,
3345			},
3346			.num_parents = 1,
3347			.flags = CLK_SET_RATE_PARENT,
3348			.ops = &clk_branch2_ops,
3349		},
3350	},
3351};
3352
3353static struct clk_hw *gcc_ipq5018_hws[] = {
3354	&gpll0_out_main_div2.hw,
3355	&pcnoc_clk_src.hw,
3356	&system_noc_clk_src.hw,
3357	&qdss_dap_sync_clk_src.hw,
3358	&qdss_tsctr_div2_clk_src.hw,
3359	&eud_at_clk_src.hw,
3360};
3361
3362static const struct alpha_pll_config ubi32_pll_config = {
3363	.l = 0x29,
3364	.alpha = 0xaaaaaaaa,
3365	.alpha_hi = 0xaa,
3366	.config_ctl_val = 0x4001075b,
3367	.main_output_mask = BIT(0),
3368	.aux_output_mask = BIT(1),
3369	.alpha_en_mask = BIT(24),
3370	.vco_val = 0x1,
3371	.vco_mask = GENMASK(21, 20),
3372	.test_ctl_val = 0x0,
3373	.test_ctl_hi_val = 0x0,
3374};
3375
3376static struct clk_regmap *gcc_ipq5018_clks[] = {
3377	[GPLL0_MAIN] = &gpll0_main.clkr,
3378	[GPLL0] = &gpll0.clkr,
3379	[GPLL2_MAIN] = &gpll2_main.clkr,
3380	[GPLL2] = &gpll2.clkr,
3381	[GPLL4_MAIN] = &gpll4_main.clkr,
3382	[GPLL4] = &gpll4.clkr,
3383	[UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
3384	[UBI32_PLL] = &ubi32_pll.clkr,
3385	[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
3386	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3387	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3388	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3389	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3390	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3391	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3392	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3393	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3394	[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3395	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
3396	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3397	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3398	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3399	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3400	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3401	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3402	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3403	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3404	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3405	[GCC_BTSS_LPO_CLK] = &gcc_btss_lpo_clk.clkr,
3406	[GCC_CMN_BLK_AHB_CLK] = &gcc_cmn_blk_ahb_clk.clkr,
3407	[GCC_CMN_BLK_SYS_CLK] = &gcc_cmn_blk_sys_clk.clkr,
3408	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3409	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3410	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3411	[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
3412	[GCC_GEPHY_RX_CLK] = &gcc_gephy_rx_clk.clkr,
3413	[GCC_GEPHY_TX_CLK] = &gcc_gephy_tx_clk.clkr,
3414	[GCC_GMAC0_CFG_CLK] = &gcc_gmac0_cfg_clk.clkr,
3415	[GCC_GMAC0_PTP_CLK] = &gcc_gmac0_ptp_clk.clkr,
3416	[GCC_GMAC0_RX_CLK] = &gcc_gmac0_rx_clk.clkr,
3417	[GCC_GMAC0_SYS_CLK] = &gcc_gmac0_sys_clk.clkr,
3418	[GCC_GMAC0_TX_CLK] = &gcc_gmac0_tx_clk.clkr,
3419	[GCC_GMAC1_CFG_CLK] = &gcc_gmac1_cfg_clk.clkr,
3420	[GCC_GMAC1_PTP_CLK] = &gcc_gmac1_ptp_clk.clkr,
3421	[GCC_GMAC1_RX_CLK] = &gcc_gmac1_rx_clk.clkr,
3422	[GCC_GMAC1_SYS_CLK] = &gcc_gmac1_sys_clk.clkr,
3423	[GCC_GMAC1_TX_CLK] = &gcc_gmac1_tx_clk.clkr,
3424	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3425	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3426	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3427	[GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
3428	[GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
3429	[GCC_MDIO0_AHB_CLK] = &gcc_mdio0_ahb_clk.clkr,
3430	[GCC_MDIO1_AHB_CLK] = &gcc_mdio1_ahb_clk.clkr,
3431	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
3432	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
3433	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
3434	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
3435	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
3436	[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
3437	[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
3438	[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
3439	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
3440	[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
3441	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3442	[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
3443	[GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr,
3444	[GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,
3445	[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
3446	[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
3447	[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
3448	[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
3449	[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
3450	[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
3451	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
3452	[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
3453	[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
3454	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3455	[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
3456	[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
3457	[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
3458	[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
3459	[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
3460	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
3461	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
3462	[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
3463	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3464	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3465	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3466	[GCC_SNOC_GMAC0_AHB_CLK] = &gcc_snoc_gmac0_ahb_clk.clkr,
3467	[GCC_SNOC_GMAC0_AXI_CLK] = &gcc_snoc_gmac0_axi_clk.clkr,
3468	[GCC_SNOC_GMAC1_AHB_CLK] = &gcc_snoc_gmac1_ahb_clk.clkr,
3469	[GCC_SNOC_GMAC1_AXI_CLK] = &gcc_snoc_gmac1_axi_clk.clkr,
3470	[GCC_SNOC_LPASS_AXIM_CLK] = &gcc_snoc_lpass_axim_clk.clkr,
3471	[GCC_SNOC_LPASS_SWAY_CLK] = &gcc_snoc_lpass_sway_clk.clkr,
3472	[GCC_SNOC_UBI0_AXI_CLK] = &gcc_snoc_ubi0_axi_clk.clkr,
3473	[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
3474	[GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
3475	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
3476	[GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
3477	[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
3478	[GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
3479	[GCC_UBI0_CFG_CLK] = &gcc_ubi0_cfg_clk.clkr,
3480	[GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
3481	[GCC_UBI0_DBG_CLK] = &gcc_ubi0_dbg_clk.clkr,
3482	[GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
3483	[GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
3484	[GCC_UNIPHY_AHB_CLK] = &gcc_uniphy_ahb_clk.clkr,
3485	[GCC_UNIPHY_RX_CLK] = &gcc_uniphy_rx_clk.clkr,
3486	[GCC_UNIPHY_SYS_CLK] = &gcc_uniphy_sys_clk.clkr,
3487	[GCC_UNIPHY_TX_CLK] = &gcc_uniphy_tx_clk.clkr,
3488	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
3489	[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
3490	[GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,
3491	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
3492	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
3493	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
3494	[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
3495	[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
3496	[GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr,
3497	[GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr,
3498	[GCC_WCSS_AXI_S_CLK] = &gcc_wcss_axi_s_clk.clkr,
3499	[GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,
3500	[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
3501	[GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,
3502	[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
3503	[GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr,
3504	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
3505	[GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,
3506	[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
3507	[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
3508	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
3509	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
3510	[GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr,
3511	[GMAC0_RX_DIV_CLK_SRC] = &gmac0_rx_div_clk_src.clkr,
3512	[GMAC0_TX_CLK_SRC] = &gmac0_tx_clk_src.clkr,
3513	[GMAC0_TX_DIV_CLK_SRC] = &gmac0_tx_div_clk_src.clkr,
3514	[GMAC1_RX_CLK_SRC] = &gmac1_rx_clk_src.clkr,
3515	[GMAC1_RX_DIV_CLK_SRC] = &gmac1_rx_div_clk_src.clkr,
3516	[GMAC1_TX_CLK_SRC] = &gmac1_tx_clk_src.clkr,
3517	[GMAC1_TX_DIV_CLK_SRC] = &gmac1_tx_div_clk_src.clkr,
3518	[GMAC_CLK_SRC] = &gmac_clk_src.clkr,
3519	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
3520	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
3521	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
3522	[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
3523	[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
3524	[PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
3525	[PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
3526	[PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
3527	[PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
3528	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3529	[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
3530	[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
3531	[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
3532	[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
3533	[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
3534	[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
3535	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3536	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3537	[UBI0_AXI_CLK_SRC] = &ubi0_axi_clk_src.clkr,
3538	[UBI0_CORE_CLK_SRC] = &ubi0_core_clk_src.clkr,
3539	[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
3540	[USB0_LFPS_CLK_SRC] = &usb0_lfps_clk_src.clkr,
3541	[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
3542	[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
3543	[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
3544	[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
3545	[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
3546	[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
3547	[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
3548	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
3549	[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
3550};
3551
3552static const struct qcom_reset_map gcc_ipq5018_resets[] = {
3553	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
3554	[GCC_BLSP1_BCR] = { 0x01000, 0 },
3555	[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
3556	[GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
3557	[GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
3558	[GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
3559	[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
3560	[GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
3561	[GCC_BTSS_BCR] = { 0x1c000, 0 },
3562	[GCC_CMN_BLK_BCR] = { 0x56300, 0 },
3563	[GCC_CMN_LDO_BCR] = { 0x33000, 0 },
3564	[GCC_CE_BCR] = { 0x33014, 0 },
3565	[GCC_CRYPTO_BCR] = { 0x16000, 0 },
3566	[GCC_DCC_BCR] = { 0x77000, 0 },
3567	[GCC_DCD_BCR] = { 0x2a000, 0 },
3568	[GCC_DDRSS_BCR] = { 0x1e000, 0 },
3569	[GCC_EDPD_BCR] = { 0x3a000, 0 },
3570	[GCC_GEPHY_BCR] = { 0x56000, 0 },
3571	[GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 },
3572	[GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 },
3573	[GCC_GEPHY_RX_ARES] = { 0x56004, 2 },
3574	[GCC_GEPHY_TX_ARES] = { 0x56004, 3 },
3575	[GCC_GMAC0_BCR] = { 0x19000, 0 },
3576	[GCC_GMAC0_CFG_ARES] = { 0x68428, 0 },
3577	[GCC_GMAC0_SYS_ARES] = { 0x68428, 1 },
3578	[GCC_GMAC1_BCR] = { 0x19100, 0 },
3579	[GCC_GMAC1_CFG_ARES] = { 0x68438, 0 },
3580	[GCC_GMAC1_SYS_ARES] = { 0x68438, 1 },
3581	[GCC_IMEM_BCR] = { 0x0e000, 0 },
3582	[GCC_LPASS_BCR] = { 0x2e000, 0 },
3583	[GCC_MDIO0_BCR] = { 0x58000, 0 },
3584	[GCC_MDIO1_BCR] = { 0x58010, 0 },
3585	[GCC_MPM_BCR] = { 0x2c000, 0 },
3586	[GCC_PCIE0_BCR] = { 0x75004, 0 },
3587	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 },
3588	[GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
3589	[GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
3590	[GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
3591	[GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
3592	[GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
3593	[GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
3594	[GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
3595	[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
3596	[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
3597	[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
3598	[GCC_PCIE1_BCR] = { 0x76004, 0 },
3599	[GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
3600	[GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
3601	[GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
3602	[GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
3603	[GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
3604	[GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
3605	[GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
3606	[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
3607	[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
3608	[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
3609	[GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 },
3610	[GCC_PCNOC_BCR] = { 0x27018, 0 },
3611	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
3612	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
3613	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
3614	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
3615	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
3616	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
3617	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
3618	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
3619	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
3620	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
3621	[GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 },
3622	[GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 },
3623	[GCC_PRNG_BCR] = { 0x13000, 0 },
3624	[GCC_Q6SS_DBG_ARES] = { 0x59110, 0 },
3625	[GCC_Q6_AHB_S_ARES] = { 0x59110, 1 },
3626	[GCC_Q6_AHB_ARES] = { 0x59110, 2 },
3627	[GCC_Q6_AXIM2_ARES] = { 0x59110, 3 },
3628	[GCC_Q6_AXIM_ARES] = { 0x59110, 4 },
3629	[GCC_Q6_AXIS_ARES] = { 0x59158, 0 },
3630	[GCC_QDSS_BCR] = { 0x29000, 0 },
3631	[GCC_QPIC_BCR] = { 0x57018, 0 },
3632	[GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 },
3633	[GCC_SDCC1_BCR] = { 0x42000, 0 },
3634	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
3635	[GCC_SPDM_BCR] = { 0x2f000, 0 },
3636	[GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
3637	[GCC_TCSR_BCR] = { 0x28000, 0 },
3638	[GCC_TLMM_BCR] = { 0x34000, 0 },
3639	[GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
3640	[GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
3641	[GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
3642	[GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
3643	[GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
3644	[GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
3645	[GCC_UBI32_BCR] = { 0x19064, 0 },
3646	[GCC_UNIPHY_BCR] = { 0x56100, 0 },
3647	[GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 },
3648	[GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
3649	[GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
3650	[GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },
3651	[GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },
3652	[GCC_USB0_BCR] = { 0x3e070, 0 },
3653	[GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
3654	[GCC_WCSS_BCR] = { 0x18000, 0 },
3655	[GCC_WCSS_DBG_ARES] = { 0x59008, 0 },
3656	[GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 },
3657	[GCC_WCSS_ACMT_ARES] = { 0x59008, 2 },
3658	[GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 },
3659	[GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 },
3660	[GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 },
3661	[GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
3662	[GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
3663	[GCC_WCSSAON_RESET] = { 0x59010, 0},
3664	[GCC_GEPHY_MISC_ARES] = { 0x56004, .bitmask = GENMASK(3, 0) },
3665};
3666
3667static const struct of_device_id gcc_ipq5018_match_table[] = {
3668	{ .compatible = "qcom,gcc-ipq5018" },
3669	{ }
3670};
3671MODULE_DEVICE_TABLE(of, gcc_ipq5018_match_table);
3672
3673static const struct regmap_config gcc_ipq5018_regmap_config = {
3674	.reg_bits = 32,
3675	.reg_stride = 4,
3676	.val_bits = 32,
3677	.max_register = 0x7fffc,
3678	.fast_io = true,
3679};
3680
3681static const struct qcom_cc_desc gcc_ipq5018_desc = {
3682	.config = &gcc_ipq5018_regmap_config,
3683	.clks = gcc_ipq5018_clks,
3684	.num_clks = ARRAY_SIZE(gcc_ipq5018_clks),
3685	.resets = gcc_ipq5018_resets,
3686	.num_resets = ARRAY_SIZE(gcc_ipq5018_resets),
3687	.clk_hws = gcc_ipq5018_hws,
3688	.num_clk_hws = ARRAY_SIZE(gcc_ipq5018_hws),
3689};
3690
3691static int gcc_ipq5018_probe(struct platform_device *pdev)
3692{
3693	struct regmap *regmap;
3694	struct qcom_cc_desc ipq5018_desc = gcc_ipq5018_desc;
3695
3696	regmap = qcom_cc_map(pdev, &ipq5018_desc);
3697	if (IS_ERR(regmap))
3698		return PTR_ERR(regmap);
3699
3700	clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
3701
3702	return qcom_cc_really_probe(&pdev->dev, &ipq5018_desc, regmap);
3703}
3704
3705static struct platform_driver gcc_ipq5018_driver = {
3706	.probe = gcc_ipq5018_probe,
3707	.driver = {
3708		.name = "qcom,gcc-ipq5018",
3709		.of_match_table = gcc_ipq5018_match_table,
3710	},
3711};
3712
3713static int __init gcc_ipq5018_init(void)
3714{
3715	return platform_driver_register(&gcc_ipq5018_driver);
3716}
3717core_initcall(gcc_ipq5018_init);
3718
3719static void __exit gcc_ipq5018_exit(void)
3720{
3721	platform_driver_unregister(&gcc_ipq5018_driver);
3722}
3723module_exit(gcc_ipq5018_exit);
3724
3725MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5018 Driver");
3726MODULE_LICENSE("GPL");