gcc-glymur.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/mod_devicetable.h>
   8#include <linux/module.h>
   9#include <linux/of.h>
  10#include <linux/platform_device.h>
  11#include <linux/regmap.h>
  12
  13#include <dt-bindings/clock/qcom,glymur-gcc.h>
  14
  15#include "clk-alpha-pll.h"
  16#include "clk-branch.h"
  17#include "clk-pll.h"
  18#include "clk-rcg.h"
  19#include "clk-regmap.h"
  20#include "clk-regmap-divider.h"
  21#include "clk-regmap-mux.h"
  22#include "clk-regmap-phy-mux.h"
  23#include "common.h"
  24#include "gdsc.h"
  25#include "reset.h"
  26
  27enum {
  28	DT_BI_TCXO,
  29	DT_BI_TCXO_AO,
  30	DT_SLEEP_CLK,
  31	DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
  32	DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
  33	DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
  34	DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
  35	DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
  36	DT_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC,
  37	DT_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC,
  38	DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
  39	DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
  40	DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
  41	DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
  42	DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
  43	DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
  44	DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
  45	DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
  46	DT_PCIE_3A_PIPE_CLK,
  47	DT_PCIE_3B_PIPE_CLK,
  48	DT_PCIE_4_PIPE_CLK,
  49	DT_PCIE_5_PIPE_CLK,
  50	DT_PCIE_6_PIPE_CLK,
  51	DT_QUSB4PHY_0_GCC_USB4_RX0_CLK,
  52	DT_QUSB4PHY_0_GCC_USB4_RX1_CLK,
  53	DT_QUSB4PHY_1_GCC_USB4_RX0_CLK,
  54	DT_QUSB4PHY_1_GCC_USB4_RX1_CLK,
  55	DT_QUSB4PHY_2_GCC_USB4_RX0_CLK,
  56	DT_QUSB4PHY_2_GCC_USB4_RX1_CLK,
  57	DT_UFS_PHY_RX_SYMBOL_0_CLK,
  58	DT_UFS_PHY_RX_SYMBOL_1_CLK,
  59	DT_UFS_PHY_TX_SYMBOL_0_CLK,
  60	DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,
  61	DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,
  62	DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,
  63	DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK,
  64	DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK,
  65	DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
  66	DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
  67	DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
  68	DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
  69	DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
  70	DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
  71};
  72
  73enum {
  74	P_BI_TCXO,
  75	P_GCC_GPLL0_OUT_EVEN,
  76	P_GCC_GPLL0_OUT_MAIN,
  77	P_GCC_GPLL14_OUT_EVEN,
  78	P_GCC_GPLL14_OUT_MAIN,
  79	P_GCC_GPLL1_OUT_MAIN,
  80	P_GCC_GPLL4_OUT_MAIN,
  81	P_GCC_GPLL5_OUT_MAIN,
  82	P_GCC_GPLL7_OUT_MAIN,
  83	P_GCC_GPLL8_OUT_MAIN,
  84	P_GCC_GPLL9_OUT_MAIN,
  85	P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC,
  86	P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC,
  87	P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC,
  88	P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
  89	P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
  90	P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
  91	P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
  92	P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
  93	P_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC,
  94	P_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC,
  95	P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
  96	P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
  97	P_GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC,
  98	P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
  99	P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
 100	P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
 101	P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
 102	P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
 103	P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
 104	P_PCIE_3A_PIPE_CLK,
 105	P_PCIE_3B_PIPE_CLK,
 106	P_PCIE_4_PIPE_CLK,
 107	P_PCIE_5_PIPE_CLK,
 108	P_PCIE_6_PIPE_CLK,
 109	P_QUSB4PHY_0_GCC_USB4_RX0_CLK,
 110	P_QUSB4PHY_0_GCC_USB4_RX1_CLK,
 111	P_QUSB4PHY_1_GCC_USB4_RX0_CLK,
 112	P_QUSB4PHY_1_GCC_USB4_RX1_CLK,
 113	P_QUSB4PHY_2_GCC_USB4_RX0_CLK,
 114	P_QUSB4PHY_2_GCC_USB4_RX1_CLK,
 115	P_SLEEP_CLK,
 116	P_UFS_PHY_RX_SYMBOL_0_CLK,
 117	P_UFS_PHY_RX_SYMBOL_1_CLK,
 118	P_UFS_PHY_TX_SYMBOL_0_CLK,
 119	P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,
 120	P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,
 121	P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,
 122	P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK,
 123	P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK,
 124	P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
 125	P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
 126	P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
 127	P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
 128	P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
 129	P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
 130};
 131
 132static struct clk_alpha_pll gcc_gpll0 = {
 133	.offset = 0x0,
 134	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
 135	.clkr = {
 136		.enable_reg = 0x62040,
 137		.enable_mask = BIT(0),
 138		.hw.init = &(const struct clk_init_data) {
 139			.name = "gcc_gpll0",
 140			.parent_data = &(const struct clk_parent_data) {
 141				.index = DT_BI_TCXO,
 142			},
 143			.num_parents = 1,
 144			.ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
 145		},
 146	},
 147};
 148
 149static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
 150	{ 0x1, 2 },
 151	{ }
 152};
 153
 154static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
 155	.offset = 0x0,
 156	.post_div_shift = 10,
 157	.post_div_table = post_div_table_gcc_gpll0_out_even,
 158	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
 159	.width = 4,
 160	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
 161	.clkr.hw.init = &(const struct clk_init_data) {
 162		.name = "gcc_gpll0_out_even",
 163		.parent_hws = (const struct clk_hw*[]) {
 164			&gcc_gpll0.clkr.hw,
 165		},
 166		.num_parents = 1,
 167		.ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops,
 168	},
 169};
 170
 171static struct clk_alpha_pll gcc_gpll1 = {
 172	.offset = 0x1000,
 173	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
 174	.clkr = {
 175		.enable_reg = 0x62040,
 176		.enable_mask = BIT(1),
 177		.hw.init = &(const struct clk_init_data) {
 178			.name = "gcc_gpll1",
 179			.parent_data = &(const struct clk_parent_data) {
 180				.index = DT_BI_TCXO,
 181			},
 182			.num_parents = 1,
 183			.ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
 184		},
 185	},
 186};
 187
 188static struct clk_alpha_pll gcc_gpll14 = {
 189	.offset = 0xe000,
 190	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
 191	.clkr = {
 192		.enable_reg = 0x62040,
 193		.enable_mask = BIT(14),
 194		.hw.init = &(const struct clk_init_data) {
 195			.name = "gcc_gpll14",
 196			.parent_data = &(const struct clk_parent_data) {
 197				.index = DT_BI_TCXO,
 198			},
 199			.num_parents = 1,
 200			.ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
 201		},
 202	},
 203};
 204
 205static const struct clk_div_table post_div_table_gcc_gpll14_out_even[] = {
 206	{ 0x1, 2 },
 207	{ }
 208};
 209
 210static struct clk_alpha_pll_postdiv gcc_gpll14_out_even = {
 211	.offset = 0xe000,
 212	.post_div_shift = 10,
 213	.post_div_table = post_div_table_gcc_gpll14_out_even,
 214	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll14_out_even),
 215	.width = 4,
 216	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
 217	.clkr.hw.init = &(const struct clk_init_data) {
 218		.name = "gcc_gpll14_out_even",
 219		.parent_hws = (const struct clk_hw*[]) {
 220			&gcc_gpll14.clkr.hw,
 221		},
 222		.num_parents = 1,
 223		.ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops,
 224	},
 225};
 226
 227static struct clk_alpha_pll gcc_gpll4 = {
 228	.offset = 0x4000,
 229	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
 230	.clkr = {
 231		.enable_reg = 0x62040,
 232		.enable_mask = BIT(4),
 233		.hw.init = &(const struct clk_init_data) {
 234			.name = "gcc_gpll4",
 235			.parent_data = &(const struct clk_parent_data) {
 236				.index = DT_BI_TCXO,
 237			},
 238			.num_parents = 1,
 239			.ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
 240		},
 241	},
 242};
 243
 244static struct clk_alpha_pll gcc_gpll5 = {
 245	.offset = 0x5000,
 246	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
 247	.clkr = {
 248		.enable_reg = 0x62040,
 249		.enable_mask = BIT(5),
 250		.hw.init = &(const struct clk_init_data) {
 251			.name = "gcc_gpll5",
 252			.parent_data = &(const struct clk_parent_data) {
 253				.index = DT_BI_TCXO,
 254			},
 255			.num_parents = 1,
 256			.ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
 257		},
 258	},
 259};
 260
 261static struct clk_alpha_pll gcc_gpll7 = {
 262	.offset = 0x7000,
 263	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
 264	.clkr = {
 265		.enable_reg = 0x62040,
 266		.enable_mask = BIT(7),
 267		.hw.init = &(const struct clk_init_data) {
 268			.name = "gcc_gpll7",
 269			.parent_data = &(const struct clk_parent_data) {
 270				.index = DT_BI_TCXO,
 271			},
 272			.num_parents = 1,
 273			.ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
 274		},
 275	},
 276};
 277
 278static struct clk_alpha_pll gcc_gpll8 = {
 279	.offset = 0x8000,
 280	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
 281	.clkr = {
 282		.enable_reg = 0x62040,
 283		.enable_mask = BIT(8),
 284		.hw.init = &(const struct clk_init_data) {
 285			.name = "gcc_gpll8",
 286			.parent_data = &(const struct clk_parent_data) {
 287				.index = DT_BI_TCXO,
 288			},
 289			.num_parents = 1,
 290			.ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
 291		},
 292	},
 293};
 294
 295static struct clk_alpha_pll gcc_gpll9 = {
 296	.offset = 0x9000,
 297	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
 298	.clkr = {
 299		.enable_reg = 0x62040,
 300		.enable_mask = BIT(9),
 301		.hw.init = &(const struct clk_init_data) {
 302			.name = "gcc_gpll9",
 303			.parent_data = &(const struct clk_parent_data) {
 304				.index = DT_BI_TCXO,
 305			},
 306			.num_parents = 1,
 307			.ops = &clk_alpha_pll_fixed_taycan_eko_t_ops,
 308		},
 309	},
 310};
 311
 312static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src;
 313static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src;
 314static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src;
 315
 316static struct clk_rcg2 gcc_usb4_1_phy_pll_pipe_clk_src;
 317
 318static const struct parent_map gcc_parent_map_0[] = {
 319	{ P_BI_TCXO, 0 },
 320	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 321	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 322};
 323
 324static const struct clk_parent_data gcc_parent_data_0[] = {
 325	{ .index = DT_BI_TCXO },
 326	{ .hw = &gcc_gpll0.clkr.hw },
 327	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 328};
 329
 330static const struct parent_map gcc_parent_map_1[] = {
 331	{ P_BI_TCXO, 0 },
 332	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 333	{ P_GCC_GPLL1_OUT_MAIN, 4 },
 334	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 335};
 336
 337static const struct clk_parent_data gcc_parent_data_1[] = {
 338	{ .index = DT_BI_TCXO },
 339	{ .hw = &gcc_gpll0.clkr.hw },
 340	{ .hw = &gcc_gpll1.clkr.hw },
 341	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 342};
 343
 344static const struct parent_map gcc_parent_map_2[] = {
 345	{ P_BI_TCXO, 0 },
 346	{ P_SLEEP_CLK, 5 },
 347};
 348
 349static const struct clk_parent_data gcc_parent_data_2[] = {
 350	{ .index = DT_BI_TCXO },
 351	{ .index = DT_SLEEP_CLK },
 352};
 353
 354static const struct parent_map gcc_parent_map_3[] = {
 355	{ P_BI_TCXO, 0 },
 356	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 357	{ P_GCC_GPLL1_OUT_MAIN, 4 },
 358	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 359	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 360};
 361
 362static const struct clk_parent_data gcc_parent_data_3[] = {
 363	{ .index = DT_BI_TCXO },
 364	{ .hw = &gcc_gpll0.clkr.hw },
 365	{ .hw = &gcc_gpll1.clkr.hw },
 366	{ .hw = &gcc_gpll4.clkr.hw },
 367	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 368};
 369
 370static const struct parent_map gcc_parent_map_4[] = {
 371	{ P_BI_TCXO, 0 },
 372	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 373	{ P_SLEEP_CLK, 5 },
 374	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 375};
 376
 377static const struct clk_parent_data gcc_parent_data_4[] = {
 378	{ .index = DT_BI_TCXO },
 379	{ .hw = &gcc_gpll0.clkr.hw },
 380	{ .index = DT_SLEEP_CLK },
 381	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 382};
 383
 384static const struct parent_map gcc_parent_map_5[] = {
 385	{ P_BI_TCXO, 0 },
 386};
 387
 388static const struct clk_parent_data gcc_parent_data_5[] = {
 389	{ .index = DT_BI_TCXO },
 390};
 391
 392static const struct parent_map gcc_parent_map_6[] = {
 393	{ P_BI_TCXO, 0 },
 394	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 395	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 396	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 397};
 398
 399static const struct clk_parent_data gcc_parent_data_6[] = {
 400	{ .index = DT_BI_TCXO },
 401	{ .hw = &gcc_gpll0.clkr.hw },
 402	{ .hw = &gcc_gpll4.clkr.hw },
 403	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 404};
 405
 406static const struct parent_map gcc_parent_map_7[] = {
 407	{ P_BI_TCXO, 0 },
 408	{ P_GCC_GPLL14_OUT_MAIN, 1 },
 409	{ P_GCC_GPLL14_OUT_EVEN, 6 },
 410};
 411
 412static const struct clk_parent_data gcc_parent_data_7[] = {
 413	{ .index = DT_BI_TCXO },
 414	{ .hw = &gcc_gpll14.clkr.hw },
 415	{ .hw = &gcc_gpll14_out_even.clkr.hw },
 416};
 417
 418static const struct parent_map gcc_parent_map_8[] = {
 419	{ P_BI_TCXO, 0 },
 420	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 421};
 422
 423static const struct clk_parent_data gcc_parent_data_8[] = {
 424	{ .index = DT_BI_TCXO },
 425	{ .hw = &gcc_gpll4.clkr.hw },
 426};
 427
 428static const struct parent_map gcc_parent_map_9[] = {
 429	{ P_BI_TCXO, 0 },
 430	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 431	{ P_GCC_GPLL8_OUT_MAIN, 2 },
 432	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 433};
 434
 435static const struct clk_parent_data gcc_parent_data_9[] = {
 436	{ .index = DT_BI_TCXO },
 437	{ .hw = &gcc_gpll0.clkr.hw },
 438	{ .hw = &gcc_gpll8.clkr.hw },
 439	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 440};
 441
 442static const struct parent_map gcc_parent_map_10[] = {
 443	{ P_BI_TCXO, 0 },
 444	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 445	{ P_GCC_GPLL7_OUT_MAIN, 2 },
 446};
 447
 448static const struct clk_parent_data gcc_parent_data_10[] = {
 449	{ .index = DT_BI_TCXO },
 450	{ .hw = &gcc_gpll0.clkr.hw },
 451	{ .hw = &gcc_gpll7.clkr.hw },
 452};
 453
 454static const struct parent_map gcc_parent_map_11[] = {
 455	{ P_BI_TCXO, 0 },
 456	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 457	{ P_GCC_GPLL7_OUT_MAIN, 2 },
 458	{ P_GCC_GPLL8_OUT_MAIN, 3 },
 459	{ P_SLEEP_CLK, 5 },
 460};
 461
 462static const struct clk_parent_data gcc_parent_data_11[] = {
 463	{ .index = DT_BI_TCXO },
 464	{ .hw = &gcc_gpll0.clkr.hw },
 465	{ .hw = &gcc_gpll7.clkr.hw },
 466	{ .hw = &gcc_gpll8.clkr.hw },
 467	{ .index = DT_SLEEP_CLK },
 468};
 469
 470static const struct parent_map gcc_parent_map_17[] = {
 471	{ P_BI_TCXO, 0 },
 472	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 473	{ P_GCC_GPLL9_OUT_MAIN, 2 },
 474	{ P_GCC_GPLL4_OUT_MAIN, 5 },
 475	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 476};
 477
 478static const struct clk_parent_data gcc_parent_data_17[] = {
 479	{ .index = DT_BI_TCXO },
 480	{ .hw = &gcc_gpll0.clkr.hw },
 481	{ .hw = &gcc_gpll9.clkr.hw },
 482	{ .hw = &gcc_gpll4.clkr.hw },
 483	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 484};
 485
 486static const struct parent_map gcc_parent_map_18[] = {
 487	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
 488	{ P_BI_TCXO, 2 },
 489};
 490
 491static const struct clk_parent_data gcc_parent_data_18[] = {
 492	{ .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
 493	{ .index = DT_BI_TCXO },
 494};
 495
 496static const struct parent_map gcc_parent_map_19[] = {
 497	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
 498	{ P_BI_TCXO, 2 },
 499};
 500
 501static const struct clk_parent_data gcc_parent_data_19[] = {
 502	{ .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
 503	{ .index = DT_BI_TCXO },
 504};
 505
 506static const struct parent_map gcc_parent_map_20[] = {
 507	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
 508	{ P_BI_TCXO, 2 },
 509};
 510
 511static const struct clk_parent_data gcc_parent_data_20[] = {
 512	{ .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
 513	{ .index = DT_BI_TCXO },
 514};
 515
 516static const struct parent_map gcc_parent_map_21[] = {
 517	{ P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },
 518	{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
 519	{ P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 3 },
 520};
 521
 522static const struct clk_parent_data gcc_parent_data_21[] = {
 523	{ .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw },
 524	{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 525	{ .index = DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC },
 526};
 527
 528static const struct parent_map gcc_parent_map_22[] = {
 529	{ P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 },
 530	{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
 531	{ P_GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC, 2 },
 532	{ P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 },
 533};
 534
 535static const struct clk_parent_data gcc_parent_data_22[] = {
 536	{ .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw },
 537	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 538	{ .hw = &gcc_usb4_1_phy_pll_pipe_clk_src.clkr.hw },
 539	{ .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC },
 540};
 541
 542static const struct parent_map gcc_parent_map_23[] = {
 543	{ P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 0 },
 544	{ P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
 545	{ P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 3 },
 546};
 547
 548static const struct clk_parent_data gcc_parent_data_23[] = {
 549	{ .hw = &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw },
 550	{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 551	{ .index = DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC },
 552};
 553
 554static const struct parent_map gcc_parent_map_24[] = {
 555	{ P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK, 0 },
 556	{ P_BI_TCXO, 2 },
 557};
 558
 559static const struct clk_parent_data gcc_parent_data_24[] = {
 560	{ .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_0_CLK },
 561	{ .index = DT_BI_TCXO },
 562};
 563
 564static const struct parent_map gcc_parent_map_25[] = {
 565	{ P_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK, 0 },
 566	{ P_BI_TCXO, 2 },
 567};
 568
 569static const struct clk_parent_data gcc_parent_data_25[] = {
 570	{ .index = DT_USB3_UNI_PHY_MP_GCC_USB30_PIPE_1_CLK },
 571	{ .index = DT_BI_TCXO },
 572};
 573
 574static const struct parent_map gcc_parent_map_26[] = {
 575	{ P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 576	{ P_BI_TCXO, 2 },
 577};
 578
 579static const struct clk_parent_data gcc_parent_data_26[] = {
 580	{ .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK },
 581	{ .index = DT_BI_TCXO },
 582};
 583
 584static const struct parent_map gcc_parent_map_27[] = {
 585	{ P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 586	{ P_BI_TCXO, 2 },
 587};
 588
 589static const struct clk_parent_data gcc_parent_data_27[] = {
 590	{ .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK },
 591	{ .index = DT_BI_TCXO },
 592};
 593
 594static const struct parent_map gcc_parent_map_28[] = {
 595	{ P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 596	{ P_BI_TCXO, 2 },
 597};
 598
 599static const struct clk_parent_data gcc_parent_data_28[] = {
 600	{ .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK },
 601	{ .index = DT_BI_TCXO },
 602};
 603
 604static const struct parent_map gcc_parent_map_29[] = {
 605	{ P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC, 0 },
 606	{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
 607};
 608
 609static const struct clk_parent_data gcc_parent_data_29[] = {
 610	{ .index = DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC },
 611	{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 612};
 613
 614static const struct parent_map gcc_parent_map_30[] = {
 615	{ P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC, 0 },
 616	{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
 617};
 618
 619static const struct clk_parent_data gcc_parent_data_30[] = {
 620	{ .index = DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC },
 621	{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 622};
 623
 624static const struct parent_map gcc_parent_map_31[] = {
 625	{ P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
 626	{ P_BI_TCXO, 2 },
 627};
 628
 629static const struct clk_parent_data gcc_parent_data_31[] = {
 630	{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
 631	{ .index = DT_BI_TCXO },
 632};
 633
 634static const struct parent_map gcc_parent_map_32[] = {
 635	{ P_BI_TCXO, 0 },
 636	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 637	{ P_GCC_GPLL7_OUT_MAIN, 2 },
 638	{ P_SLEEP_CLK, 5 },
 639};
 640
 641static const struct clk_parent_data gcc_parent_data_32[] = {
 642	{ .index = DT_BI_TCXO },
 643	{ .hw = &gcc_gpll0.clkr.hw },
 644	{ .hw = &gcc_gpll7.clkr.hw },
 645	{ .index = DT_SLEEP_CLK },
 646};
 647
 648static const struct parent_map gcc_parent_map_33[] = {
 649	{ P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
 650	{ P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
 651};
 652
 653static const struct clk_parent_data gcc_parent_data_33[] = {
 654	{ .index = DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC },
 655	{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
 656};
 657
 658static const struct parent_map gcc_parent_map_34[] = {
 659	{ P_QUSB4PHY_0_GCC_USB4_RX0_CLK, 0 },
 660	{ P_BI_TCXO, 2 },
 661};
 662
 663static const struct clk_parent_data gcc_parent_data_34[] = {
 664	{ .index = DT_QUSB4PHY_0_GCC_USB4_RX0_CLK },
 665	{ .index = DT_BI_TCXO },
 666};
 667
 668static const struct parent_map gcc_parent_map_35[] = {
 669	{ P_QUSB4PHY_0_GCC_USB4_RX1_CLK, 0 },
 670	{ P_BI_TCXO, 2 },
 671};
 672
 673static const struct clk_parent_data gcc_parent_data_35[] = {
 674	{ .index = DT_QUSB4PHY_0_GCC_USB4_RX1_CLK },
 675	{ .index = DT_BI_TCXO },
 676};
 677
 678static const struct parent_map gcc_parent_map_36[] = {
 679	{ P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
 680	{ P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
 681};
 682
 683static const struct clk_parent_data gcc_parent_data_36[] = {
 684	{ .index = DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC },
 685	{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
 686};
 687
 688static const struct parent_map gcc_parent_map_37[] = {
 689	{ P_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC, 0 },
 690	{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
 691};
 692
 693static const struct clk_parent_data gcc_parent_data_37[] = {
 694	{ .index = DT_GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC },
 695	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 696};
 697
 698static const struct parent_map gcc_parent_map_38[] = {
 699	{ P_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC, 0 },
 700	{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
 701};
 702
 703static const struct clk_parent_data gcc_parent_data_38[] = {
 704	{ .index = DT_GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC },
 705	{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 706};
 707
 708static const struct parent_map gcc_parent_map_39[] = {
 709	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
 710	{ P_BI_TCXO, 2 },
 711};
 712
 713static const struct clk_parent_data gcc_parent_data_39[] = {
 714	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
 715	{ .index = DT_BI_TCXO },
 716};
 717
 718static const struct parent_map gcc_parent_map_40[] = {
 719	{ P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
 720	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
 721};
 722
 723static const struct clk_parent_data gcc_parent_data_40[] = {
 724	{ .index = DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC },
 725	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
 726};
 727
 728static const struct parent_map gcc_parent_map_41[] = {
 729	{ P_BI_TCXO, 0 },
 730	{ P_GCC_GPLL0_OUT_MAIN, 1 },
 731	{ P_GCC_GPLL5_OUT_MAIN, 3 },
 732	{ P_GCC_GPLL0_OUT_EVEN, 6 },
 733};
 734
 735static const struct clk_parent_data gcc_parent_data_41[] = {
 736	{ .index = DT_BI_TCXO },
 737	{ .hw = &gcc_gpll0.clkr.hw },
 738	{ .hw = &gcc_gpll5.clkr.hw },
 739	{ .hw = &gcc_gpll0_out_even.clkr.hw },
 740};
 741
 742static const struct parent_map gcc_parent_map_42[] = {
 743	{ P_QUSB4PHY_1_GCC_USB4_RX0_CLK, 0 },
 744	{ P_BI_TCXO, 2 },
 745};
 746
 747static const struct clk_parent_data gcc_parent_data_42[] = {
 748	{ .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK },
 749	{ .index = DT_BI_TCXO },
 750};
 751
 752static const struct parent_map gcc_parent_map_43[] = {
 753	{ P_QUSB4PHY_1_GCC_USB4_RX1_CLK, 0 },
 754	{ P_BI_TCXO, 2 },
 755};
 756
 757static const struct clk_parent_data gcc_parent_data_43[] = {
 758	{ .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK },
 759	{ .index = DT_BI_TCXO },
 760};
 761
 762static const struct parent_map gcc_parent_map_44[] = {
 763	{ P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
 764	{ P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
 765};
 766
 767static const struct clk_parent_data gcc_parent_data_44[] = {
 768	{ .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },
 769	{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
 770};
 771
 772static const struct parent_map gcc_parent_map_45[] = {
 773	{ P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC, 0 },
 774	{ P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
 775};
 776
 777static const struct clk_parent_data gcc_parent_data_45[] = {
 778	{ .index = DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC },
 779	{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 780};
 781
 782static const struct parent_map gcc_parent_map_46[] = {
 783	{ P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC, 0 },
 784	{ P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 2 },
 785};
 786
 787static const struct clk_parent_data gcc_parent_data_46[] = {
 788	{ .index = DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC },
 789	{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
 790};
 791
 792static const struct parent_map gcc_parent_map_47[] = {
 793	{ P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 0 },
 794	{ P_BI_TCXO, 2 },
 795};
 796
 797static const struct clk_parent_data gcc_parent_data_47[] = {
 798	{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
 799	{ .index = DT_BI_TCXO },
 800};
 801
 802static const struct parent_map gcc_parent_map_48[] = {
 803	{ P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC, 0 },
 804	{ P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 1 },
 805};
 806
 807static const struct clk_parent_data gcc_parent_data_48[] = {
 808	{ .index = DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC },
 809	{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
 810};
 811
 812static const struct parent_map gcc_parent_map_49[] = {
 813	{ P_QUSB4PHY_2_GCC_USB4_RX0_CLK, 0 },
 814	{ P_BI_TCXO, 2 },
 815};
 816
 817static const struct clk_parent_data gcc_parent_data_49[] = {
 818	{ .index = DT_QUSB4PHY_2_GCC_USB4_RX0_CLK },
 819	{ .index = DT_BI_TCXO },
 820};
 821
 822static const struct parent_map gcc_parent_map_50[] = {
 823	{ P_QUSB4PHY_2_GCC_USB4_RX1_CLK, 0 },
 824	{ P_BI_TCXO, 2 },
 825};
 826
 827static const struct clk_parent_data gcc_parent_data_50[] = {
 828	{ .index = DT_QUSB4PHY_2_GCC_USB4_RX1_CLK },
 829	{ .index = DT_BI_TCXO },
 830};
 831
 832static const struct parent_map gcc_parent_map_51[] = {
 833	{ P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC, 0 },
 834	{ P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, 2 },
 835};
 836
 837static const struct clk_parent_data gcc_parent_data_51[] = {
 838	{ .index = DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC },
 839	{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
 840};
 841
 842static struct clk_regmap_phy_mux gcc_pcie_3a_pipe_clk_src = {
 843	.reg = 0xdc088,
 844	.clkr = {
 845		.hw.init = &(const struct clk_init_data) {
 846			.name = "gcc_pcie_3a_pipe_clk_src",
 847			.parent_data = &(const struct clk_parent_data){
 848				.index = DT_PCIE_3A_PIPE_CLK,
 849			},
 850			.num_parents = 1,
 851			.ops = &clk_regmap_phy_mux_ops,
 852		},
 853	},
 854};
 855
 856static struct clk_regmap_phy_mux gcc_pcie_3b_pipe_clk_src = {
 857	.reg = 0x941b4,
 858	.clkr = {
 859		.hw.init = &(const struct clk_init_data) {
 860			.name = "gcc_pcie_3b_pipe_clk_src",
 861			.parent_data = &(const struct clk_parent_data){
 862				.index = DT_PCIE_3B_PIPE_CLK,
 863			},
 864			.num_parents = 1,
 865			.ops = &clk_regmap_phy_mux_ops,
 866		},
 867	},
 868};
 869
 870static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = {
 871	.reg = 0x881a4,
 872	.clkr = {
 873		.hw.init = &(const struct clk_init_data) {
 874			.name = "gcc_pcie_4_pipe_clk_src",
 875			.parent_data = &(const struct clk_parent_data){
 876				.index = DT_PCIE_4_PIPE_CLK,
 877			},
 878			.num_parents = 1,
 879			.ops = &clk_regmap_phy_mux_ops,
 880		},
 881	},
 882};
 883
 884static struct clk_regmap_phy_mux gcc_pcie_5_pipe_clk_src = {
 885	.reg = 0xc309c,
 886	.clkr = {
 887		.hw.init = &(const struct clk_init_data) {
 888			.name = "gcc_pcie_5_pipe_clk_src",
 889			.parent_data = &(const struct clk_parent_data){
 890				.index = DT_PCIE_5_PIPE_CLK,
 891			},
 892			.num_parents = 1,
 893			.ops = &clk_regmap_phy_mux_ops,
 894		},
 895	},
 896};
 897
 898static struct clk_regmap_phy_mux gcc_pcie_6_pipe_clk_src = {
 899	.reg = 0x8a1a4,
 900	.clkr = {
 901		.hw.init = &(const struct clk_init_data) {
 902			.name = "gcc_pcie_6_pipe_clk_src",
 903			.parent_data = &(const struct clk_parent_data){
 904				.index = DT_PCIE_6_PIPE_CLK,
 905			},
 906			.num_parents = 1,
 907			.ops = &clk_regmap_phy_mux_ops,
 908		},
 909	},
 910};
 911
 912static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
 913	.reg = 0x7706c,
 914	.shift = 0,
 915	.width = 2,
 916	.parent_map = gcc_parent_map_18,
 917	.clkr = {
 918		.hw.init = &(const struct clk_init_data) {
 919			.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
 920			.parent_data = gcc_parent_data_18,
 921			.num_parents = ARRAY_SIZE(gcc_parent_data_18),
 922			.ops = &clk_regmap_mux_closest_ops,
 923		},
 924	},
 925};
 926
 927static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
 928	.reg = 0x770f0,
 929	.shift = 0,
 930	.width = 2,
 931	.parent_map = gcc_parent_map_19,
 932	.clkr = {
 933		.hw.init = &(const struct clk_init_data) {
 934			.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
 935			.parent_data = gcc_parent_data_19,
 936			.num_parents = ARRAY_SIZE(gcc_parent_data_19),
 937			.ops = &clk_regmap_mux_closest_ops,
 938		},
 939	},
 940};
 941
 942static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
 943	.reg = 0x7705c,
 944	.shift = 0,
 945	.width = 2,
 946	.parent_map = gcc_parent_map_20,
 947	.clkr = {
 948		.hw.init = &(const struct clk_init_data) {
 949			.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
 950			.parent_data = gcc_parent_data_20,
 951			.num_parents = ARRAY_SIZE(gcc_parent_data_20),
 952			.ops = &clk_regmap_mux_closest_ops,
 953		},
 954	},
 955};
 956
 957static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = {
 958	.reg = 0x2b0b8,
 959	.shift = 0,
 960	.width = 2,
 961	.parent_map = gcc_parent_map_21,
 962	.clkr = {
 963		.hw.init = &(const struct clk_init_data) {
 964			.name = "gcc_usb34_prim_phy_pipe_clk_src",
 965			.parent_data = gcc_parent_data_21,
 966			.num_parents = ARRAY_SIZE(gcc_parent_data_21),
 967			.ops = &clk_regmap_mux_closest_ops,
 968		},
 969	},
 970};
 971
 972static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = {
 973	.reg = 0x2d0c4,
 974	.shift = 0,
 975	.width = 2,
 976	.parent_map = gcc_parent_map_22,
 977	.clkr = {
 978		.hw.init = &(const struct clk_init_data) {
 979			.name = "gcc_usb34_sec_phy_pipe_clk_src",
 980			.parent_data = gcc_parent_data_22,
 981			.num_parents = ARRAY_SIZE(gcc_parent_data_22),
 982			.ops = &clk_regmap_mux_closest_ops,
 983		},
 984	},
 985};
 986
 987static struct clk_regmap_mux gcc_usb34_tert_phy_pipe_clk_src = {
 988	.reg = 0xe00bc,
 989	.shift = 0,
 990	.width = 2,
 991	.parent_map = gcc_parent_map_23,
 992	.clkr = {
 993		.hw.init = &(const struct clk_init_data) {
 994			.name = "gcc_usb34_tert_phy_pipe_clk_src",
 995			.parent_data = gcc_parent_data_23,
 996			.num_parents = ARRAY_SIZE(gcc_parent_data_23),
 997			.ops = &clk_regmap_mux_closest_ops,
 998		},
 999	},
1000};
1001
1002static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_0_clk_src = {
1003	.reg = 0x9a07c,
1004	.shift = 0,
1005	.width = 2,
1006	.parent_map = gcc_parent_map_24,
1007	.clkr = {
1008		.hw.init = &(const struct clk_init_data) {
1009			.name = "gcc_usb3_mp_phy_pipe_0_clk_src",
1010			.parent_data = gcc_parent_data_24,
1011			.num_parents = ARRAY_SIZE(gcc_parent_data_24),
1012			.ops = &clk_regmap_mux_closest_ops,
1013		},
1014	},
1015};
1016
1017static struct clk_regmap_mux gcc_usb3_mp_phy_pipe_1_clk_src = {
1018	.reg = 0x9a084,
1019	.shift = 0,
1020	.width = 2,
1021	.parent_map = gcc_parent_map_25,
1022	.clkr = {
1023		.hw.init = &(const struct clk_init_data) {
1024			.name = "gcc_usb3_mp_phy_pipe_1_clk_src",
1025			.parent_data = gcc_parent_data_25,
1026			.num_parents = ARRAY_SIZE(gcc_parent_data_25),
1027			.ops = &clk_regmap_mux_closest_ops,
1028		},
1029	},
1030};
1031
1032static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
1033	.reg = 0x3f08c,
1034	.shift = 0,
1035	.width = 2,
1036	.parent_map = gcc_parent_map_26,
1037	.clkr = {
1038		.hw.init = &(const struct clk_init_data) {
1039			.name = "gcc_usb3_prim_phy_pipe_clk_src",
1040			.parent_data = gcc_parent_data_26,
1041			.num_parents = ARRAY_SIZE(gcc_parent_data_26),
1042			.ops = &clk_regmap_mux_closest_ops,
1043		},
1044	},
1045};
1046
1047static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
1048	.reg = 0xe207c,
1049	.shift = 0,
1050	.width = 2,
1051	.parent_map = gcc_parent_map_27,
1052	.clkr = {
1053		.hw.init = &(const struct clk_init_data) {
1054			.name = "gcc_usb3_sec_phy_pipe_clk_src",
1055			.parent_data = gcc_parent_data_27,
1056			.num_parents = ARRAY_SIZE(gcc_parent_data_27),
1057			.ops = &clk_regmap_mux_closest_ops,
1058		},
1059	},
1060};
1061
1062static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = {
1063	.reg = 0xe107c,
1064	.shift = 0,
1065	.width = 2,
1066	.parent_map = gcc_parent_map_28,
1067	.clkr = {
1068		.hw.init = &(const struct clk_init_data) {
1069			.name = "gcc_usb3_tert_phy_pipe_clk_src",
1070			.parent_data = gcc_parent_data_28,
1071			.num_parents = ARRAY_SIZE(gcc_parent_data_28),
1072			.ops = &clk_regmap_mux_closest_ops,
1073		},
1074	},
1075};
1076
1077static struct clk_regmap_mux gcc_usb4_0_phy_dp0_clk_src = {
1078	.reg = 0x2b080,
1079	.shift = 0,
1080	.width = 2,
1081	.parent_map = gcc_parent_map_29,
1082	.clkr = {
1083		.hw.init = &(const struct clk_init_data) {
1084			.name = "gcc_usb4_0_phy_dp0_clk_src",
1085			.parent_data = gcc_parent_data_29,
1086			.num_parents = ARRAY_SIZE(gcc_parent_data_29),
1087			.ops = &clk_regmap_mux_closest_ops,
1088		},
1089	},
1090};
1091
1092static struct clk_regmap_mux gcc_usb4_0_phy_dp1_clk_src = {
1093	.reg = 0x2b134,
1094	.shift = 0,
1095	.width = 2,
1096	.parent_map = gcc_parent_map_30,
1097	.clkr = {
1098		.hw.init = &(const struct clk_init_data) {
1099			.name = "gcc_usb4_0_phy_dp1_clk_src",
1100			.parent_data = gcc_parent_data_30,
1101			.num_parents = ARRAY_SIZE(gcc_parent_data_30),
1102			.ops = &clk_regmap_mux_closest_ops,
1103		},
1104	},
1105};
1106
1107static struct clk_regmap_mux gcc_usb4_0_phy_p2rr2p_pipe_clk_src = {
1108	.reg = 0x2b0f0,
1109	.shift = 0,
1110	.width = 2,
1111	.parent_map = gcc_parent_map_31,
1112	.clkr = {
1113		.hw.init = &(const struct clk_init_data) {
1114			.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk_src",
1115			.parent_data = gcc_parent_data_31,
1116			.num_parents = ARRAY_SIZE(gcc_parent_data_31),
1117			.ops = &clk_regmap_mux_closest_ops,
1118		},
1119	},
1120};
1121
1122static struct clk_regmap_mux gcc_usb4_0_phy_pcie_pipe_mux_clk_src = {
1123	.reg = 0x2b120,
1124	.shift = 0,
1125	.width = 1,
1126	.parent_map = gcc_parent_map_33,
1127	.clkr = {
1128		.hw.init = &(const struct clk_init_data) {
1129			.name = "gcc_usb4_0_phy_pcie_pipe_mux_clk_src",
1130			.parent_data = gcc_parent_data_33,
1131			.num_parents = ARRAY_SIZE(gcc_parent_data_33),
1132			.ops = &clk_regmap_mux_closest_ops,
1133		},
1134	},
1135};
1136
1137static struct clk_regmap_mux gcc_usb4_0_phy_rx0_clk_src = {
1138	.reg = 0x2b0c0,
1139	.shift = 0,
1140	.width = 2,
1141	.parent_map = gcc_parent_map_34,
1142	.clkr = {
1143		.hw.init = &(const struct clk_init_data) {
1144			.name = "gcc_usb4_0_phy_rx0_clk_src",
1145			.parent_data = gcc_parent_data_34,
1146			.num_parents = ARRAY_SIZE(gcc_parent_data_34),
1147			.ops = &clk_regmap_mux_closest_ops,
1148		},
1149	},
1150};
1151
1152static struct clk_regmap_mux gcc_usb4_0_phy_rx1_clk_src = {
1153	.reg = 0x2b0d4,
1154	.shift = 0,
1155	.width = 2,
1156	.parent_map = gcc_parent_map_35,
1157	.clkr = {
1158		.hw.init = &(const struct clk_init_data) {
1159			.name = "gcc_usb4_0_phy_rx1_clk_src",
1160			.parent_data = gcc_parent_data_35,
1161			.num_parents = ARRAY_SIZE(gcc_parent_data_35),
1162			.ops = &clk_regmap_mux_closest_ops,
1163		},
1164	},
1165};
1166
1167static struct clk_regmap_mux gcc_usb4_0_phy_sys_clk_src = {
1168	.reg = 0x2b100,
1169	.shift = 0,
1170	.width = 2,
1171	.parent_map = gcc_parent_map_36,
1172	.clkr = {
1173		.hw.init = &(const struct clk_init_data) {
1174			.name = "gcc_usb4_0_phy_sys_clk_src",
1175			.parent_data = gcc_parent_data_36,
1176			.num_parents = ARRAY_SIZE(gcc_parent_data_36),
1177			.ops = &clk_regmap_mux_closest_ops,
1178		},
1179	},
1180};
1181
1182static struct clk_regmap_mux gcc_usb4_1_phy_dp0_clk_src = {
1183	.reg = 0x2d08c,
1184	.shift = 0,
1185	.width = 2,
1186	.parent_map = gcc_parent_map_37,
1187	.clkr = {
1188		.hw.init = &(const struct clk_init_data) {
1189			.name = "gcc_usb4_1_phy_dp0_clk_src",
1190			.parent_data = gcc_parent_data_37,
1191			.num_parents = ARRAY_SIZE(gcc_parent_data_37),
1192			.ops = &clk_regmap_mux_closest_ops,
1193		},
1194	},
1195};
1196
1197static struct clk_regmap_mux gcc_usb4_1_phy_dp1_clk_src = {
1198	.reg = 0x2d154,
1199	.shift = 0,
1200	.width = 2,
1201	.parent_map = gcc_parent_map_38,
1202	.clkr = {
1203		.hw.init = &(const struct clk_init_data) {
1204			.name = "gcc_usb4_1_phy_dp1_clk_src",
1205			.parent_data = gcc_parent_data_38,
1206			.num_parents = ARRAY_SIZE(gcc_parent_data_38),
1207			.ops = &clk_regmap_mux_closest_ops,
1208		},
1209	},
1210};
1211
1212static struct clk_regmap_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = {
1213	.reg = 0x2d114,
1214	.shift = 0,
1215	.width = 2,
1216	.parent_map = gcc_parent_map_39,
1217	.clkr = {
1218		.hw.init = &(const struct clk_init_data) {
1219			.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src",
1220			.parent_data = gcc_parent_data_39,
1221			.num_parents = ARRAY_SIZE(gcc_parent_data_39),
1222			.ops = &clk_regmap_mux_closest_ops,
1223		},
1224	},
1225};
1226
1227static struct clk_regmap_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = {
1228	.reg = 0x2d140,
1229	.shift = 0,
1230	.width = 1,
1231	.parent_map = gcc_parent_map_40,
1232	.clkr = {
1233		.hw.init = &(const struct clk_init_data) {
1234			.name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src",
1235			.parent_data = gcc_parent_data_40,
1236			.num_parents = ARRAY_SIZE(gcc_parent_data_40),
1237			.ops = &clk_regmap_mux_closest_ops,
1238		},
1239	},
1240};
1241
1242static struct clk_regmap_mux gcc_usb4_1_phy_rx0_clk_src = {
1243	.reg = 0x2d0e4,
1244	.shift = 0,
1245	.width = 2,
1246	.parent_map = gcc_parent_map_42,
1247	.clkr = {
1248		.hw.init = &(const struct clk_init_data) {
1249			.name = "gcc_usb4_1_phy_rx0_clk_src",
1250			.parent_data = gcc_parent_data_42,
1251			.num_parents = ARRAY_SIZE(gcc_parent_data_42),
1252			.ops = &clk_regmap_mux_closest_ops,
1253		},
1254	},
1255};
1256
1257static struct clk_regmap_mux gcc_usb4_1_phy_rx1_clk_src = {
1258	.reg = 0x2d0f8,
1259	.shift = 0,
1260	.width = 2,
1261	.parent_map = gcc_parent_map_43,
1262	.clkr = {
1263		.hw.init = &(const struct clk_init_data) {
1264			.name = "gcc_usb4_1_phy_rx1_clk_src",
1265			.parent_data = gcc_parent_data_43,
1266			.num_parents = ARRAY_SIZE(gcc_parent_data_43),
1267			.ops = &clk_regmap_mux_closest_ops,
1268		},
1269	},
1270};
1271
1272static struct clk_regmap_mux gcc_usb4_1_phy_sys_clk_src = {
1273	.reg = 0x2d124,
1274	.shift = 0,
1275	.width = 2,
1276	.parent_map = gcc_parent_map_44,
1277	.clkr = {
1278		.hw.init = &(const struct clk_init_data) {
1279			.name = "gcc_usb4_1_phy_sys_clk_src",
1280			.parent_data = gcc_parent_data_44,
1281			.num_parents = ARRAY_SIZE(gcc_parent_data_44),
1282			.ops = &clk_regmap_mux_closest_ops,
1283		},
1284	},
1285};
1286
1287static struct clk_regmap_mux gcc_usb4_2_phy_dp0_clk_src = {
1288	.reg = 0xe0084,
1289	.shift = 0,
1290	.width = 2,
1291	.parent_map = gcc_parent_map_45,
1292	.clkr = {
1293		.hw.init = &(const struct clk_init_data) {
1294			.name = "gcc_usb4_2_phy_dp0_clk_src",
1295			.parent_data = gcc_parent_data_45,
1296			.num_parents = ARRAY_SIZE(gcc_parent_data_45),
1297			.ops = &clk_regmap_mux_closest_ops,
1298		},
1299	},
1300};
1301
1302static struct clk_regmap_mux gcc_usb4_2_phy_dp1_clk_src = {
1303	.reg = 0xe013c,
1304	.shift = 0,
1305	.width = 2,
1306	.parent_map = gcc_parent_map_46,
1307	.clkr = {
1308		.hw.init = &(const struct clk_init_data) {
1309			.name = "gcc_usb4_2_phy_dp1_clk_src",
1310			.parent_data = gcc_parent_data_46,
1311			.num_parents = ARRAY_SIZE(gcc_parent_data_46),
1312			.ops = &clk_regmap_mux_closest_ops,
1313		},
1314	},
1315};
1316
1317static struct clk_regmap_mux gcc_usb4_2_phy_p2rr2p_pipe_clk_src = {
1318	.reg = 0xe00f4,
1319	.shift = 0,
1320	.width = 2,
1321	.parent_map = gcc_parent_map_47,
1322	.clkr = {
1323		.hw.init = &(const struct clk_init_data) {
1324			.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk_src",
1325			.parent_data = gcc_parent_data_47,
1326			.num_parents = ARRAY_SIZE(gcc_parent_data_47),
1327			.ops = &clk_regmap_mux_closest_ops,
1328		},
1329	},
1330};
1331
1332static struct clk_regmap_mux gcc_usb4_2_phy_pcie_pipe_mux_clk_src = {
1333	.reg = 0xe0124,
1334	.shift = 0,
1335	.width = 1,
1336	.parent_map = gcc_parent_map_48,
1337	.clkr = {
1338		.hw.init = &(const struct clk_init_data) {
1339			.name = "gcc_usb4_2_phy_pcie_pipe_mux_clk_src",
1340			.parent_data = gcc_parent_data_48,
1341			.num_parents = ARRAY_SIZE(gcc_parent_data_48),
1342			.ops = &clk_regmap_mux_closest_ops,
1343		},
1344	},
1345};
1346
1347static struct clk_regmap_mux gcc_usb4_2_phy_rx0_clk_src = {
1348	.reg = 0xe00c4,
1349	.shift = 0,
1350	.width = 2,
1351	.parent_map = gcc_parent_map_49,
1352	.clkr = {
1353		.hw.init = &(const struct clk_init_data) {
1354			.name = "gcc_usb4_2_phy_rx0_clk_src",
1355			.parent_data = gcc_parent_data_49,
1356			.num_parents = ARRAY_SIZE(gcc_parent_data_49),
1357			.ops = &clk_regmap_mux_closest_ops,
1358		},
1359	},
1360};
1361
1362static struct clk_regmap_mux gcc_usb4_2_phy_rx1_clk_src = {
1363	.reg = 0xe00d8,
1364	.shift = 0,
1365	.width = 2,
1366	.parent_map = gcc_parent_map_50,
1367	.clkr = {
1368		.hw.init = &(const struct clk_init_data) {
1369			.name = "gcc_usb4_2_phy_rx1_clk_src",
1370			.parent_data = gcc_parent_data_50,
1371			.num_parents = ARRAY_SIZE(gcc_parent_data_50),
1372			.ops = &clk_regmap_mux_closest_ops,
1373		},
1374	},
1375};
1376
1377static struct clk_regmap_mux gcc_usb4_2_phy_sys_clk_src = {
1378	.reg = 0xe0104,
1379	.shift = 0,
1380	.width = 2,
1381	.parent_map = gcc_parent_map_51,
1382	.clkr = {
1383		.hw.init = &(const struct clk_init_data) {
1384			.name = "gcc_usb4_2_phy_sys_clk_src",
1385			.parent_data = gcc_parent_data_51,
1386			.num_parents = ARRAY_SIZE(gcc_parent_data_51),
1387			.ops = &clk_regmap_mux_closest_ops,
1388		},
1389	},
1390};
1391
1392static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
1393	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1394	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1395	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1396	{ }
1397};
1398
1399static struct clk_rcg2 gcc_gp1_clk_src = {
1400	.cmd_rcgr = 0x64004,
1401	.mnd_width = 16,
1402	.hid_width = 5,
1403	.parent_map = gcc_parent_map_4,
1404	.freq_tbl = ftbl_gcc_gp1_clk_src,
1405	.clkr.hw.init = &(const struct clk_init_data) {
1406		.name = "gcc_gp1_clk_src",
1407		.parent_data = gcc_parent_data_4,
1408		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
1409		.flags = CLK_SET_RATE_PARENT,
1410		.ops = &clk_rcg2_shared_no_init_park_ops,
1411	},
1412};
1413
1414static struct clk_rcg2 gcc_gp2_clk_src = {
1415	.cmd_rcgr = 0x92004,
1416	.mnd_width = 16,
1417	.hid_width = 5,
1418	.parent_map = gcc_parent_map_4,
1419	.freq_tbl = ftbl_gcc_gp1_clk_src,
1420	.clkr.hw.init = &(const struct clk_init_data) {
1421		.name = "gcc_gp2_clk_src",
1422		.parent_data = gcc_parent_data_4,
1423		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
1424		.flags = CLK_SET_RATE_PARENT,
1425		.ops = &clk_rcg2_shared_no_init_park_ops,
1426	},
1427};
1428
1429static struct clk_rcg2 gcc_gp3_clk_src = {
1430	.cmd_rcgr = 0x93004,
1431	.mnd_width = 16,
1432	.hid_width = 5,
1433	.parent_map = gcc_parent_map_4,
1434	.freq_tbl = ftbl_gcc_gp1_clk_src,
1435	.clkr.hw.init = &(const struct clk_init_data) {
1436		.name = "gcc_gp3_clk_src",
1437		.parent_data = gcc_parent_data_4,
1438		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
1439		.flags = CLK_SET_RATE_PARENT,
1440		.ops = &clk_rcg2_shared_no_init_park_ops,
1441	},
1442};
1443
1444static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
1445	F(19200000, P_BI_TCXO, 1, 0, 0),
1446	{ }
1447};
1448
1449static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
1450	.cmd_rcgr = 0xc8168,
1451	.mnd_width = 16,
1452	.hid_width = 5,
1453	.parent_map = gcc_parent_map_2,
1454	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1455	.clkr.hw.init = &(const struct clk_init_data) {
1456		.name = "gcc_pcie_0_aux_clk_src",
1457		.parent_data = gcc_parent_data_2,
1458		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1459		.flags = CLK_SET_RATE_PARENT,
1460		.ops = &clk_rcg2_shared_no_init_park_ops,
1461	},
1462};
1463
1464static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
1465	F(19200000, P_BI_TCXO, 1, 0, 0),
1466	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1467	{ }
1468};
1469
1470static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
1471	.cmd_rcgr = 0xc803c,
1472	.mnd_width = 0,
1473	.hid_width = 5,
1474	.parent_map = gcc_parent_map_0,
1475	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1476	.clkr.hw.init = &(const struct clk_init_data) {
1477		.name = "gcc_pcie_0_phy_rchng_clk_src",
1478		.parent_data = gcc_parent_data_0,
1479		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1480		.flags = CLK_SET_RATE_PARENT,
1481		.ops = &clk_rcg2_shared_no_init_park_ops,
1482	},
1483};
1484
1485static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
1486	.cmd_rcgr = 0x2e168,
1487	.mnd_width = 16,
1488	.hid_width = 5,
1489	.parent_map = gcc_parent_map_2,
1490	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1491	.clkr.hw.init = &(const struct clk_init_data) {
1492		.name = "gcc_pcie_1_aux_clk_src",
1493		.parent_data = gcc_parent_data_2,
1494		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1495		.flags = CLK_SET_RATE_PARENT,
1496		.ops = &clk_rcg2_shared_no_init_park_ops,
1497	},
1498};
1499
1500static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
1501	.cmd_rcgr = 0x2e03c,
1502	.mnd_width = 0,
1503	.hid_width = 5,
1504	.parent_map = gcc_parent_map_0,
1505	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1506	.clkr.hw.init = &(const struct clk_init_data) {
1507		.name = "gcc_pcie_1_phy_rchng_clk_src",
1508		.parent_data = gcc_parent_data_0,
1509		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1510		.flags = CLK_SET_RATE_PARENT,
1511		.ops = &clk_rcg2_shared_no_init_park_ops,
1512	},
1513};
1514
1515static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
1516	.cmd_rcgr = 0xc0168,
1517	.mnd_width = 16,
1518	.hid_width = 5,
1519	.parent_map = gcc_parent_map_2,
1520	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1521	.clkr.hw.init = &(const struct clk_init_data) {
1522		.name = "gcc_pcie_2_aux_clk_src",
1523		.parent_data = gcc_parent_data_2,
1524		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1525		.flags = CLK_SET_RATE_PARENT,
1526		.ops = &clk_rcg2_shared_no_init_park_ops,
1527	},
1528};
1529
1530static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = {
1531	.cmd_rcgr = 0xc003c,
1532	.mnd_width = 0,
1533	.hid_width = 5,
1534	.parent_map = gcc_parent_map_0,
1535	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1536	.clkr.hw.init = &(const struct clk_init_data) {
1537		.name = "gcc_pcie_2_phy_rchng_clk_src",
1538		.parent_data = gcc_parent_data_0,
1539		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1540		.flags = CLK_SET_RATE_PARENT,
1541		.ops = &clk_rcg2_shared_no_init_park_ops,
1542	},
1543};
1544
1545static struct clk_rcg2 gcc_pcie_3a_aux_clk_src = {
1546	.cmd_rcgr = 0xdc08c,
1547	.mnd_width = 16,
1548	.hid_width = 5,
1549	.parent_map = gcc_parent_map_2,
1550	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1551	.clkr.hw.init = &(const struct clk_init_data) {
1552		.name = "gcc_pcie_3a_aux_clk_src",
1553		.parent_data = gcc_parent_data_2,
1554		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1555		.flags = CLK_SET_RATE_PARENT,
1556		.ops = &clk_rcg2_shared_no_init_park_ops,
1557	},
1558};
1559
1560static struct clk_rcg2 gcc_pcie_3a_phy_rchng_clk_src = {
1561	.cmd_rcgr = 0xdc070,
1562	.mnd_width = 0,
1563	.hid_width = 5,
1564	.parent_map = gcc_parent_map_0,
1565	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1566	.clkr.hw.init = &(const struct clk_init_data) {
1567		.name = "gcc_pcie_3a_phy_rchng_clk_src",
1568		.parent_data = gcc_parent_data_0,
1569		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1570		.flags = CLK_SET_RATE_PARENT,
1571		.ops = &clk_rcg2_shared_no_init_park_ops,
1572	},
1573};
1574
1575static struct clk_rcg2 gcc_pcie_3b_aux_clk_src = {
1576	.cmd_rcgr = 0x941b8,
1577	.mnd_width = 16,
1578	.hid_width = 5,
1579	.parent_map = gcc_parent_map_2,
1580	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1581	.clkr.hw.init = &(const struct clk_init_data) {
1582		.name = "gcc_pcie_3b_aux_clk_src",
1583		.parent_data = gcc_parent_data_2,
1584		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1585		.flags = CLK_SET_RATE_PARENT,
1586		.ops = &clk_rcg2_shared_no_init_park_ops,
1587	},
1588};
1589
1590static struct clk_rcg2 gcc_pcie_3b_phy_rchng_clk_src = {
1591	.cmd_rcgr = 0x94088,
1592	.mnd_width = 0,
1593	.hid_width = 5,
1594	.parent_map = gcc_parent_map_0,
1595	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1596	.clkr.hw.init = &(const struct clk_init_data) {
1597		.name = "gcc_pcie_3b_phy_rchng_clk_src",
1598		.parent_data = gcc_parent_data_0,
1599		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1600		.flags = CLK_SET_RATE_PARENT,
1601		.ops = &clk_rcg2_shared_no_init_park_ops,
1602	},
1603};
1604
1605static struct clk_rcg2 gcc_pcie_4_aux_clk_src = {
1606	.cmd_rcgr = 0x881a8,
1607	.mnd_width = 16,
1608	.hid_width = 5,
1609	.parent_map = gcc_parent_map_2,
1610	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1611	.clkr.hw.init = &(const struct clk_init_data) {
1612		.name = "gcc_pcie_4_aux_clk_src",
1613		.parent_data = gcc_parent_data_2,
1614		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1615		.flags = CLK_SET_RATE_PARENT,
1616		.ops = &clk_rcg2_shared_no_init_park_ops,
1617	},
1618};
1619
1620static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = {
1621	.cmd_rcgr = 0x88078,
1622	.mnd_width = 0,
1623	.hid_width = 5,
1624	.parent_map = gcc_parent_map_0,
1625	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1626	.clkr.hw.init = &(const struct clk_init_data) {
1627		.name = "gcc_pcie_4_phy_rchng_clk_src",
1628		.parent_data = gcc_parent_data_0,
1629		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1630		.flags = CLK_SET_RATE_PARENT,
1631		.ops = &clk_rcg2_shared_no_init_park_ops,
1632	},
1633};
1634
1635static struct clk_rcg2 gcc_pcie_5_aux_clk_src = {
1636	.cmd_rcgr = 0xc30a0,
1637	.mnd_width = 16,
1638	.hid_width = 5,
1639	.parent_map = gcc_parent_map_2,
1640	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1641	.clkr.hw.init = &(const struct clk_init_data) {
1642		.name = "gcc_pcie_5_aux_clk_src",
1643		.parent_data = gcc_parent_data_2,
1644		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1645		.flags = CLK_SET_RATE_PARENT,
1646		.ops = &clk_rcg2_shared_no_init_park_ops,
1647	},
1648};
1649
1650static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = {
1651	.cmd_rcgr = 0xc3084,
1652	.mnd_width = 0,
1653	.hid_width = 5,
1654	.parent_map = gcc_parent_map_0,
1655	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1656	.clkr.hw.init = &(const struct clk_init_data) {
1657		.name = "gcc_pcie_5_phy_rchng_clk_src",
1658		.parent_data = gcc_parent_data_0,
1659		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1660		.flags = CLK_SET_RATE_PARENT,
1661		.ops = &clk_rcg2_shared_no_init_park_ops,
1662	},
1663};
1664
1665static struct clk_rcg2 gcc_pcie_6_aux_clk_src = {
1666	.cmd_rcgr = 0x8a1a8,
1667	.mnd_width = 16,
1668	.hid_width = 5,
1669	.parent_map = gcc_parent_map_2,
1670	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1671	.clkr.hw.init = &(const struct clk_init_data) {
1672		.name = "gcc_pcie_6_aux_clk_src",
1673		.parent_data = gcc_parent_data_2,
1674		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1675		.flags = CLK_SET_RATE_PARENT,
1676		.ops = &clk_rcg2_shared_no_init_park_ops,
1677	},
1678};
1679
1680static struct clk_rcg2 gcc_pcie_6_phy_rchng_clk_src = {
1681	.cmd_rcgr = 0x8a078,
1682	.mnd_width = 0,
1683	.hid_width = 5,
1684	.parent_map = gcc_parent_map_0,
1685	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
1686	.clkr.hw.init = &(const struct clk_init_data) {
1687		.name = "gcc_pcie_6_phy_rchng_clk_src",
1688		.parent_data = gcc_parent_data_0,
1689		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1690		.flags = CLK_SET_RATE_PARENT,
1691		.ops = &clk_rcg2_shared_no_init_park_ops,
1692	},
1693};
1694
1695static struct clk_rcg2 gcc_pcie_phy_3a_aux_clk_src = {
1696	.cmd_rcgr = 0x6c01c,
1697	.mnd_width = 16,
1698	.hid_width = 5,
1699	.parent_map = gcc_parent_map_2,
1700	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1701	.clkr.hw.init = &(const struct clk_init_data) {
1702		.name = "gcc_pcie_phy_3a_aux_clk_src",
1703		.parent_data = gcc_parent_data_2,
1704		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1705		.flags = CLK_SET_RATE_PARENT,
1706		.ops = &clk_rcg2_shared_no_init_park_ops,
1707	},
1708};
1709
1710static struct clk_rcg2 gcc_pcie_phy_3b_aux_clk_src = {
1711	.cmd_rcgr = 0x7501c,
1712	.mnd_width = 16,
1713	.hid_width = 5,
1714	.parent_map = gcc_parent_map_2,
1715	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1716	.clkr.hw.init = &(const struct clk_init_data) {
1717		.name = "gcc_pcie_phy_3b_aux_clk_src",
1718		.parent_data = gcc_parent_data_2,
1719		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1720		.flags = CLK_SET_RATE_PARENT,
1721		.ops = &clk_rcg2_shared_no_init_park_ops,
1722	},
1723};
1724
1725static struct clk_rcg2 gcc_pcie_phy_4_aux_clk_src = {
1726	.cmd_rcgr = 0xd3018,
1727	.mnd_width = 16,
1728	.hid_width = 5,
1729	.parent_map = gcc_parent_map_2,
1730	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1731	.clkr.hw.init = &(const struct clk_init_data) {
1732		.name = "gcc_pcie_phy_4_aux_clk_src",
1733		.parent_data = gcc_parent_data_2,
1734		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1735		.flags = CLK_SET_RATE_PARENT,
1736		.ops = &clk_rcg2_shared_no_init_park_ops,
1737	},
1738};
1739
1740static struct clk_rcg2 gcc_pcie_phy_5_aux_clk_src = {
1741	.cmd_rcgr = 0xd2018,
1742	.mnd_width = 16,
1743	.hid_width = 5,
1744	.parent_map = gcc_parent_map_2,
1745	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1746	.clkr.hw.init = &(const struct clk_init_data) {
1747		.name = "gcc_pcie_phy_5_aux_clk_src",
1748		.parent_data = gcc_parent_data_2,
1749		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1750		.flags = CLK_SET_RATE_PARENT,
1751		.ops = &clk_rcg2_shared_no_init_park_ops,
1752	},
1753};
1754
1755static struct clk_rcg2 gcc_pcie_phy_6_aux_clk_src = {
1756	.cmd_rcgr = 0xd4018,
1757	.mnd_width = 16,
1758	.hid_width = 5,
1759	.parent_map = gcc_parent_map_2,
1760	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1761	.clkr.hw.init = &(const struct clk_init_data) {
1762		.name = "gcc_pcie_phy_6_aux_clk_src",
1763		.parent_data = gcc_parent_data_2,
1764		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1765		.flags = CLK_SET_RATE_PARENT,
1766		.ops = &clk_rcg2_shared_no_init_park_ops,
1767	},
1768};
1769
1770static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
1771	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
1772	{ }
1773};
1774
1775static struct clk_rcg2 gcc_pdm2_clk_src = {
1776	.cmd_rcgr = 0x33010,
1777	.mnd_width = 0,
1778	.hid_width = 5,
1779	.parent_map = gcc_parent_map_0,
1780	.freq_tbl = ftbl_gcc_pdm2_clk_src,
1781	.clkr.hw.init = &(const struct clk_init_data) {
1782		.name = "gcc_pdm2_clk_src",
1783		.parent_data = gcc_parent_data_0,
1784		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1785		.flags = CLK_SET_RATE_PARENT,
1786		.ops = &clk_rcg2_shared_no_init_park_ops,
1787	},
1788};
1789
1790static const struct freq_tbl ftbl_gcc_qupv3_oob_qspi_s0_clk_src[] = {
1791	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1792	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1793	F(19200000, P_BI_TCXO, 1, 0, 0),
1794	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1795	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1796	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1797	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1798	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1799	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1800	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1801	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1802	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1803	F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1804	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1805	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1806	{ }
1807};
1808
1809static struct clk_init_data gcc_qupv3_oob_qspi_s0_clk_src_init = {
1810	.name = "gcc_qupv3_oob_qspi_s0_clk_src",
1811	.parent_data = gcc_parent_data_3,
1812	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1813	.flags = CLK_SET_RATE_PARENT,
1814	.ops = &clk_rcg2_shared_no_init_park_ops,
1815};
1816
1817static struct clk_rcg2 gcc_qupv3_oob_qspi_s0_clk_src = {
1818	.cmd_rcgr = 0xe7044,
1819	.mnd_width = 16,
1820	.hid_width = 5,
1821	.parent_map = gcc_parent_map_3,
1822	.freq_tbl = ftbl_gcc_qupv3_oob_qspi_s0_clk_src,
1823	.clkr.hw.init = &gcc_qupv3_oob_qspi_s0_clk_src_init,
1824};
1825
1826static const struct freq_tbl ftbl_gcc_qupv3_oob_qspi_s1_clk_src[] = {
1827	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1828	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1829	F(19200000, P_BI_TCXO, 1, 0, 0),
1830	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1831	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1832	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1833	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1834	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1835	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1836	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1837	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1838	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1839	F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1840	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1841	{ }
1842};
1843
1844static struct clk_init_data gcc_qupv3_oob_qspi_s1_clk_src_init = {
1845	.name = "gcc_qupv3_oob_qspi_s1_clk_src",
1846	.parent_data = gcc_parent_data_1,
1847	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1848	.flags = CLK_SET_RATE_PARENT,
1849	.ops = &clk_rcg2_shared_no_init_park_ops,
1850};
1851
1852static struct clk_rcg2 gcc_qupv3_oob_qspi_s1_clk_src = {
1853	.cmd_rcgr = 0xe7170,
1854	.mnd_width = 16,
1855	.hid_width = 5,
1856	.parent_map = gcc_parent_map_1,
1857	.freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
1858	.clkr.hw.init = &gcc_qupv3_oob_qspi_s1_clk_src_init,
1859};
1860
1861static struct clk_init_data gcc_qupv3_wrap0_qspi_s2_clk_src_init = {
1862	.name = "gcc_qupv3_wrap0_qspi_s2_clk_src",
1863	.parent_data = gcc_parent_data_1,
1864	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1865	.flags = CLK_SET_RATE_PARENT,
1866	.ops = &clk_rcg2_shared_no_init_park_ops,
1867};
1868
1869static struct clk_rcg2 gcc_qupv3_wrap0_qspi_s2_clk_src = {
1870	.cmd_rcgr = 0x287a0,
1871	.mnd_width = 16,
1872	.hid_width = 5,
1873	.parent_map = gcc_parent_map_1,
1874	.freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
1875	.clkr.hw.init = &gcc_qupv3_wrap0_qspi_s2_clk_src_init,
1876};
1877
1878static struct clk_init_data gcc_qupv3_wrap0_qspi_s3_clk_src_init = {
1879	.name = "gcc_qupv3_wrap0_qspi_s3_clk_src",
1880	.parent_data = gcc_parent_data_1,
1881	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1882	.flags = CLK_SET_RATE_PARENT,
1883	.ops = &clk_rcg2_shared_no_init_park_ops,
1884};
1885
1886static struct clk_rcg2 gcc_qupv3_wrap0_qspi_s3_clk_src = {
1887	.cmd_rcgr = 0x288d0,
1888	.mnd_width = 16,
1889	.hid_width = 5,
1890	.parent_map = gcc_parent_map_1,
1891	.freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
1892	.clkr.hw.init = &gcc_qupv3_wrap0_qspi_s3_clk_src_init,
1893};
1894
1895static struct clk_init_data gcc_qupv3_wrap0_qspi_s6_clk_src_init = {
1896	.name = "gcc_qupv3_wrap0_qspi_s6_clk_src",
1897	.parent_data = gcc_parent_data_1,
1898	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1899	.flags = CLK_SET_RATE_PARENT,
1900	.ops = &clk_rcg2_shared_no_init_park_ops,
1901};
1902
1903static struct clk_rcg2 gcc_qupv3_wrap0_qspi_s6_clk_src = {
1904	.cmd_rcgr = 0x2866c,
1905	.mnd_width = 16,
1906	.hid_width = 5,
1907	.parent_map = gcc_parent_map_1,
1908	.freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
1909	.clkr.hw.init = &gcc_qupv3_wrap0_qspi_s6_clk_src_init,
1910};
1911
1912static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
1913	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1914	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1915	F(19200000, P_BI_TCXO, 1, 0, 0),
1916	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1917	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1918	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1919	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1920	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1921	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1922	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1923	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1924	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1925	{ }
1926};
1927
1928static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
1929	.name = "gcc_qupv3_wrap0_s0_clk_src",
1930	.parent_data = gcc_parent_data_1,
1931	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1932	.flags = CLK_SET_RATE_PARENT,
1933	.ops = &clk_rcg2_shared_no_init_park_ops,
1934};
1935
1936static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
1937	.cmd_rcgr = 0x28014,
1938	.mnd_width = 16,
1939	.hid_width = 5,
1940	.parent_map = gcc_parent_map_1,
1941	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1942	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
1943};
1944
1945static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
1946	.name = "gcc_qupv3_wrap0_s1_clk_src",
1947	.parent_data = gcc_parent_data_1,
1948	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1949	.flags = CLK_SET_RATE_PARENT,
1950	.ops = &clk_rcg2_shared_no_init_park_ops,
1951};
1952
1953static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
1954	.cmd_rcgr = 0x28150,
1955	.mnd_width = 16,
1956	.hid_width = 5,
1957	.parent_map = gcc_parent_map_1,
1958	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1959	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
1960};
1961
1962static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = {
1963	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1964	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1965	F(19200000, P_BI_TCXO, 1, 0, 0),
1966	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1967	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1968	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1969	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1970	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1971	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1972	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1973	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1974	{ }
1975};
1976
1977static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
1978	.name = "gcc_qupv3_wrap0_s4_clk_src",
1979	.parent_data = gcc_parent_data_1,
1980	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1981	.flags = CLK_SET_RATE_PARENT,
1982	.ops = &clk_rcg2_shared_no_init_park_ops,
1983};
1984
1985static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
1986	.cmd_rcgr = 0x282b4,
1987	.mnd_width = 16,
1988	.hid_width = 5,
1989	.parent_map = gcc_parent_map_1,
1990	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1991	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
1992};
1993
1994static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
1995	.name = "gcc_qupv3_wrap0_s5_clk_src",
1996	.parent_data = gcc_parent_data_1,
1997	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1998	.flags = CLK_SET_RATE_PARENT,
1999	.ops = &clk_rcg2_shared_no_init_park_ops,
2000};
2001
2002static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
2003	.cmd_rcgr = 0x283f0,
2004	.mnd_width = 16,
2005	.hid_width = 5,
2006	.parent_map = gcc_parent_map_1,
2007	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2008	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
2009};
2010
2011static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
2012	.name = "gcc_qupv3_wrap0_s7_clk_src",
2013	.parent_data = gcc_parent_data_1,
2014	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2015	.flags = CLK_SET_RATE_PARENT,
2016	.ops = &clk_rcg2_shared_no_init_park_ops,
2017};
2018
2019static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
2020	.cmd_rcgr = 0x28540,
2021	.mnd_width = 16,
2022	.hid_width = 5,
2023	.parent_map = gcc_parent_map_1,
2024	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2025	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
2026};
2027
2028static struct clk_init_data gcc_qupv3_wrap1_qspi_s2_clk_src_init = {
2029	.name = "gcc_qupv3_wrap1_qspi_s2_clk_src",
2030	.parent_data = gcc_parent_data_1,
2031	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2032	.flags = CLK_SET_RATE_PARENT,
2033	.ops = &clk_rcg2_shared_no_init_park_ops,
2034};
2035
2036static struct clk_rcg2 gcc_qupv3_wrap1_qspi_s2_clk_src = {
2037	.cmd_rcgr = 0xb37a0,
2038	.mnd_width = 16,
2039	.hid_width = 5,
2040	.parent_map = gcc_parent_map_1,
2041	.freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
2042	.clkr.hw.init = &gcc_qupv3_wrap1_qspi_s2_clk_src_init,
2043};
2044
2045static struct clk_init_data gcc_qupv3_wrap1_qspi_s3_clk_src_init = {
2046	.name = "gcc_qupv3_wrap1_qspi_s3_clk_src",
2047	.parent_data = gcc_parent_data_1,
2048	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2049	.flags = CLK_SET_RATE_PARENT,
2050	.ops = &clk_rcg2_shared_no_init_park_ops,
2051};
2052
2053static struct clk_rcg2 gcc_qupv3_wrap1_qspi_s3_clk_src = {
2054	.cmd_rcgr = 0xb38d0,
2055	.mnd_width = 16,
2056	.hid_width = 5,
2057	.parent_map = gcc_parent_map_1,
2058	.freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
2059	.clkr.hw.init = &gcc_qupv3_wrap1_qspi_s3_clk_src_init,
2060};
2061
2062static struct clk_init_data gcc_qupv3_wrap1_qspi_s6_clk_src_init = {
2063	.name = "gcc_qupv3_wrap1_qspi_s6_clk_src",
2064	.parent_data = gcc_parent_data_1,
2065	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2066	.flags = CLK_SET_RATE_PARENT,
2067	.ops = &clk_rcg2_shared_no_init_park_ops,
2068};
2069
2070static struct clk_rcg2 gcc_qupv3_wrap1_qspi_s6_clk_src = {
2071	.cmd_rcgr = 0xb366c,
2072	.mnd_width = 16,
2073	.hid_width = 5,
2074	.parent_map = gcc_parent_map_1,
2075	.freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
2076	.clkr.hw.init = &gcc_qupv3_wrap1_qspi_s6_clk_src_init,
2077};
2078
2079static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
2080	.name = "gcc_qupv3_wrap1_s0_clk_src",
2081	.parent_data = gcc_parent_data_1,
2082	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2083	.flags = CLK_SET_RATE_PARENT,
2084	.ops = &clk_rcg2_shared_no_init_park_ops,
2085};
2086
2087static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
2088	.cmd_rcgr = 0xb3014,
2089	.mnd_width = 16,
2090	.hid_width = 5,
2091	.parent_map = gcc_parent_map_1,
2092	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
2093	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
2094};
2095
2096static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
2097	.name = "gcc_qupv3_wrap1_s1_clk_src",
2098	.parent_data = gcc_parent_data_1,
2099	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2100	.flags = CLK_SET_RATE_PARENT,
2101	.ops = &clk_rcg2_shared_no_init_park_ops,
2102};
2103
2104static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
2105	.cmd_rcgr = 0xb3150,
2106	.mnd_width = 16,
2107	.hid_width = 5,
2108	.parent_map = gcc_parent_map_1,
2109	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
2110	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
2111};
2112
2113static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
2114	.name = "gcc_qupv3_wrap1_s4_clk_src",
2115	.parent_data = gcc_parent_data_1,
2116	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2117	.flags = CLK_SET_RATE_PARENT,
2118	.ops = &clk_rcg2_shared_no_init_park_ops,
2119};
2120
2121static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
2122	.cmd_rcgr = 0xb32b4,
2123	.mnd_width = 16,
2124	.hid_width = 5,
2125	.parent_map = gcc_parent_map_1,
2126	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2127	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
2128};
2129
2130static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
2131	.name = "gcc_qupv3_wrap1_s5_clk_src",
2132	.parent_data = gcc_parent_data_1,
2133	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2134	.flags = CLK_SET_RATE_PARENT,
2135	.ops = &clk_rcg2_shared_no_init_park_ops,
2136};
2137
2138static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
2139	.cmd_rcgr = 0xb33f0,
2140	.mnd_width = 16,
2141	.hid_width = 5,
2142	.parent_map = gcc_parent_map_1,
2143	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2144	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
2145};
2146
2147static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
2148	.name = "gcc_qupv3_wrap1_s7_clk_src",
2149	.parent_data = gcc_parent_data_1,
2150	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2151	.flags = CLK_SET_RATE_PARENT,
2152	.ops = &clk_rcg2_shared_no_init_park_ops,
2153};
2154
2155static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
2156	.cmd_rcgr = 0xb3540,
2157	.mnd_width = 16,
2158	.hid_width = 5,
2159	.parent_map = gcc_parent_map_1,
2160	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2161	.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
2162};
2163
2164static struct clk_init_data gcc_qupv3_wrap2_qspi_s2_clk_src_init = {
2165	.name = "gcc_qupv3_wrap2_qspi_s2_clk_src",
2166	.parent_data = gcc_parent_data_1,
2167	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2168	.flags = CLK_SET_RATE_PARENT,
2169	.ops = &clk_rcg2_shared_no_init_park_ops,
2170};
2171
2172static struct clk_rcg2 gcc_qupv3_wrap2_qspi_s2_clk_src = {
2173	.cmd_rcgr = 0xb47a0,
2174	.mnd_width = 16,
2175	.hid_width = 5,
2176	.parent_map = gcc_parent_map_1,
2177	.freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
2178	.clkr.hw.init = &gcc_qupv3_wrap2_qspi_s2_clk_src_init,
2179};
2180
2181static struct clk_init_data gcc_qupv3_wrap2_qspi_s3_clk_src_init = {
2182	.name = "gcc_qupv3_wrap2_qspi_s3_clk_src",
2183	.parent_data = gcc_parent_data_1,
2184	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2185	.flags = CLK_SET_RATE_PARENT,
2186	.ops = &clk_rcg2_shared_no_init_park_ops,
2187};
2188
2189static struct clk_rcg2 gcc_qupv3_wrap2_qspi_s3_clk_src = {
2190	.cmd_rcgr = 0xb48d0,
2191	.mnd_width = 16,
2192	.hid_width = 5,
2193	.parent_map = gcc_parent_map_1,
2194	.freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
2195	.clkr.hw.init = &gcc_qupv3_wrap2_qspi_s3_clk_src_init,
2196};
2197
2198static struct clk_init_data gcc_qupv3_wrap2_qspi_s6_clk_src_init = {
2199	.name = "gcc_qupv3_wrap2_qspi_s6_clk_src",
2200	.parent_data = gcc_parent_data_1,
2201	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2202	.flags = CLK_SET_RATE_PARENT,
2203	.ops = &clk_rcg2_shared_no_init_park_ops,
2204};
2205
2206static struct clk_rcg2 gcc_qupv3_wrap2_qspi_s6_clk_src = {
2207	.cmd_rcgr = 0xb466c,
2208	.mnd_width = 16,
2209	.hid_width = 5,
2210	.parent_map = gcc_parent_map_1,
2211	.freq_tbl = ftbl_gcc_qupv3_oob_qspi_s1_clk_src,
2212	.clkr.hw.init = &gcc_qupv3_wrap2_qspi_s6_clk_src_init,
2213};
2214
2215static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
2216	.name = "gcc_qupv3_wrap2_s0_clk_src",
2217	.parent_data = gcc_parent_data_1,
2218	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2219	.flags = CLK_SET_RATE_PARENT,
2220	.ops = &clk_rcg2_shared_no_init_park_ops,
2221};
2222
2223static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
2224	.cmd_rcgr = 0xb4014,
2225	.mnd_width = 16,
2226	.hid_width = 5,
2227	.parent_map = gcc_parent_map_1,
2228	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
2229	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
2230};
2231
2232static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
2233	.name = "gcc_qupv3_wrap2_s1_clk_src",
2234	.parent_data = gcc_parent_data_1,
2235	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2236	.flags = CLK_SET_RATE_PARENT,
2237	.ops = &clk_rcg2_shared_no_init_park_ops,
2238};
2239
2240static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
2241	.cmd_rcgr = 0xb4150,
2242	.mnd_width = 16,
2243	.hid_width = 5,
2244	.parent_map = gcc_parent_map_1,
2245	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
2246	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
2247};
2248
2249static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
2250	.name = "gcc_qupv3_wrap2_s4_clk_src",
2251	.parent_data = gcc_parent_data_1,
2252	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2253	.flags = CLK_SET_RATE_PARENT,
2254	.ops = &clk_rcg2_shared_no_init_park_ops,
2255};
2256
2257static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
2258	.cmd_rcgr = 0xb42b4,
2259	.mnd_width = 16,
2260	.hid_width = 5,
2261	.parent_map = gcc_parent_map_1,
2262	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2263	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
2264};
2265
2266static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
2267	.name = "gcc_qupv3_wrap2_s5_clk_src",
2268	.parent_data = gcc_parent_data_1,
2269	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2270	.flags = CLK_SET_RATE_PARENT,
2271	.ops = &clk_rcg2_shared_no_init_park_ops,
2272};
2273
2274static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
2275	.cmd_rcgr = 0xb43f0,
2276	.mnd_width = 16,
2277	.hid_width = 5,
2278	.parent_map = gcc_parent_map_1,
2279	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2280	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
2281};
2282
2283static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
2284	.name = "gcc_qupv3_wrap2_s7_clk_src",
2285	.parent_data = gcc_parent_data_1,
2286	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
2287	.flags = CLK_SET_RATE_PARENT,
2288	.ops = &clk_rcg2_shared_no_init_park_ops,
2289};
2290
2291static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
2292	.cmd_rcgr = 0xb4540,
2293	.mnd_width = 16,
2294	.hid_width = 5,
2295	.parent_map = gcc_parent_map_1,
2296	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
2297	.clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
2298};
2299
2300static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
2301	F(400000, P_BI_TCXO, 12, 1, 4),
2302	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
2303	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
2304	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
2305	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
2306	{ }
2307};
2308
2309static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
2310	.cmd_rcgr = 0xb001c,
2311	.mnd_width = 8,
2312	.hid_width = 5,
2313	.parent_map = gcc_parent_map_17,
2314	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
2315	.clkr.hw.init = &(const struct clk_init_data) {
2316		.name = "gcc_sdcc2_apps_clk_src",
2317		.parent_data = gcc_parent_data_17,
2318		.num_parents = ARRAY_SIZE(gcc_parent_data_17),
2319		.flags = CLK_SET_RATE_PARENT,
2320		.ops = &clk_rcg2_shared_floor_ops,
2321	},
2322};
2323
2324static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
2325	F(400000, P_BI_TCXO, 12, 1, 4),
2326	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
2327	F(75000000, P_GCC_GPLL0_OUT_MAIN, 8, 0, 0),
2328	{ }
2329};
2330
2331static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
2332	.cmd_rcgr = 0xdf01c,
2333	.mnd_width = 8,
2334	.hid_width = 5,
2335	.parent_map = gcc_parent_map_3,
2336	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
2337	.clkr.hw.init = &(const struct clk_init_data) {
2338		.name = "gcc_sdcc4_apps_clk_src",
2339		.parent_data = gcc_parent_data_3,
2340		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
2341		.flags = CLK_SET_RATE_PARENT,
2342		.ops = &clk_rcg2_shared_floor_ops,
2343	},
2344};
2345
2346static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
2347	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
2348	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
2349	F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
2350	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
2351	{ }
2352};
2353
2354static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
2355	.cmd_rcgr = 0x77038,
2356	.mnd_width = 8,
2357	.hid_width = 5,
2358	.parent_map = gcc_parent_map_6,
2359	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
2360	.clkr.hw.init = &(const struct clk_init_data) {
2361		.name = "gcc_ufs_phy_axi_clk_src",
2362		.parent_data = gcc_parent_data_6,
2363		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
2364		.flags = CLK_SET_RATE_PARENT,
2365		.ops = &clk_rcg2_shared_no_init_park_ops,
2366	},
2367};
2368
2369static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
2370	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
2371	F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
2372	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
2373	{ }
2374};
2375
2376static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
2377	.cmd_rcgr = 0x77090,
2378	.mnd_width = 0,
2379	.hid_width = 5,
2380	.parent_map = gcc_parent_map_6,
2381	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
2382	.clkr.hw.init = &(const struct clk_init_data) {
2383		.name = "gcc_ufs_phy_ice_core_clk_src",
2384		.parent_data = gcc_parent_data_6,
2385		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
2386		.flags = CLK_SET_RATE_PARENT,
2387		.ops = &clk_rcg2_shared_no_init_park_ops,
2388	},
2389};
2390
2391static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
2392	.cmd_rcgr = 0x770c4,
2393	.mnd_width = 0,
2394	.hid_width = 5,
2395	.parent_map = gcc_parent_map_5,
2396	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2397	.clkr.hw.init = &(const struct clk_init_data) {
2398		.name = "gcc_ufs_phy_phy_aux_clk_src",
2399		.parent_data = gcc_parent_data_5,
2400		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
2401		.flags = CLK_SET_RATE_PARENT,
2402		.ops = &clk_rcg2_shared_no_init_park_ops,
2403	},
2404};
2405
2406static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
2407	.cmd_rcgr = 0x770a8,
2408	.mnd_width = 0,
2409	.hid_width = 5,
2410	.parent_map = gcc_parent_map_6,
2411	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
2412	.clkr.hw.init = &(const struct clk_init_data) {
2413		.name = "gcc_ufs_phy_unipro_core_clk_src",
2414		.parent_data = gcc_parent_data_6,
2415		.num_parents = ARRAY_SIZE(gcc_parent_data_6),
2416		.flags = CLK_SET_RATE_PARENT,
2417		.ops = &clk_rcg2_shared_no_init_park_ops,
2418	},
2419};
2420
2421static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
2422	F(60000000, P_GCC_GPLL14_OUT_MAIN, 10, 0, 0),
2423	F(120000000, P_GCC_GPLL14_OUT_MAIN, 5, 0, 0),
2424	{ }
2425};
2426
2427static struct clk_rcg2 gcc_usb20_master_clk_src = {
2428	.cmd_rcgr = 0xbc030,
2429	.mnd_width = 8,
2430	.hid_width = 5,
2431	.parent_map = gcc_parent_map_7,
2432	.freq_tbl = ftbl_gcc_usb20_master_clk_src,
2433	.clkr.hw.init = &(const struct clk_init_data) {
2434		.name = "gcc_usb20_master_clk_src",
2435		.parent_data = gcc_parent_data_7,
2436		.num_parents = ARRAY_SIZE(gcc_parent_data_7),
2437		.flags = CLK_SET_RATE_PARENT,
2438		.ops = &clk_rcg2_shared_no_init_park_ops,
2439	},
2440};
2441
2442static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = {
2443	.cmd_rcgr = 0xbc048,
2444	.mnd_width = 0,
2445	.hid_width = 5,
2446	.parent_map = gcc_parent_map_7,
2447	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2448	.clkr.hw.init = &(const struct clk_init_data) {
2449		.name = "gcc_usb20_mock_utmi_clk_src",
2450		.parent_data = gcc_parent_data_7,
2451		.num_parents = ARRAY_SIZE(gcc_parent_data_7),
2452		.flags = CLK_SET_RATE_PARENT,
2453		.ops = &clk_rcg2_shared_no_init_park_ops,
2454	},
2455};
2456
2457static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {
2458	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
2459	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
2460	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
2461	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
2462	{ }
2463};
2464
2465static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {
2466	.cmd_rcgr = 0x9a03c,
2467	.mnd_width = 8,
2468	.hid_width = 5,
2469	.parent_map = gcc_parent_map_0,
2470	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
2471	.clkr.hw.init = &(const struct clk_init_data) {
2472		.name = "gcc_usb30_mp_master_clk_src",
2473		.parent_data = gcc_parent_data_0,
2474		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2475		.flags = CLK_SET_RATE_PARENT,
2476		.ops = &clk_rcg2_shared_no_init_park_ops,
2477	},
2478};
2479
2480static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
2481	.cmd_rcgr = 0x9a054,
2482	.mnd_width = 0,
2483	.hid_width = 5,
2484	.parent_map = gcc_parent_map_0,
2485	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2486	.clkr.hw.init = &(const struct clk_init_data) {
2487		.name = "gcc_usb30_mp_mock_utmi_clk_src",
2488		.parent_data = gcc_parent_data_0,
2489		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2490		.flags = CLK_SET_RATE_PARENT,
2491		.ops = &clk_rcg2_shared_no_init_park_ops,
2492	},
2493};
2494
2495static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
2496	.cmd_rcgr = 0x3f04c,
2497	.mnd_width = 8,
2498	.hid_width = 5,
2499	.parent_map = gcc_parent_map_0,
2500	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
2501	.clkr.hw.init = &(const struct clk_init_data) {
2502		.name = "gcc_usb30_prim_master_clk_src",
2503		.parent_data = gcc_parent_data_0,
2504		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2505		.flags = CLK_SET_RATE_PARENT,
2506		.ops = &clk_rcg2_shared_no_init_park_ops,
2507	},
2508};
2509
2510static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
2511	.cmd_rcgr = 0x3f064,
2512	.mnd_width = 0,
2513	.hid_width = 5,
2514	.parent_map = gcc_parent_map_0,
2515	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2516	.clkr.hw.init = &(const struct clk_init_data) {
2517		.name = "gcc_usb30_prim_mock_utmi_clk_src",
2518		.parent_data = gcc_parent_data_0,
2519		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2520		.flags = CLK_SET_RATE_PARENT,
2521		.ops = &clk_rcg2_shared_no_init_park_ops,
2522	},
2523};
2524
2525static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
2526	.cmd_rcgr = 0xe203c,
2527	.mnd_width = 8,
2528	.hid_width = 5,
2529	.parent_map = gcc_parent_map_0,
2530	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
2531	.clkr.hw.init = &(const struct clk_init_data) {
2532		.name = "gcc_usb30_sec_master_clk_src",
2533		.parent_data = gcc_parent_data_0,
2534		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2535		.flags = CLK_SET_RATE_PARENT,
2536		.ops = &clk_rcg2_shared_no_init_park_ops,
2537	},
2538};
2539
2540static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
2541	.cmd_rcgr = 0xe2054,
2542	.mnd_width = 0,
2543	.hid_width = 5,
2544	.parent_map = gcc_parent_map_0,
2545	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2546	.clkr.hw.init = &(const struct clk_init_data) {
2547		.name = "gcc_usb30_sec_mock_utmi_clk_src",
2548		.parent_data = gcc_parent_data_0,
2549		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2550		.flags = CLK_SET_RATE_PARENT,
2551		.ops = &clk_rcg2_shared_no_init_park_ops,
2552	},
2553};
2554
2555static struct clk_rcg2 gcc_usb30_tert_master_clk_src = {
2556	.cmd_rcgr = 0xe103c,
2557	.mnd_width = 8,
2558	.hid_width = 5,
2559	.parent_map = gcc_parent_map_0,
2560	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
2561	.clkr.hw.init = &(const struct clk_init_data) {
2562		.name = "gcc_usb30_tert_master_clk_src",
2563		.parent_data = gcc_parent_data_0,
2564		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2565		.flags = CLK_SET_RATE_PARENT,
2566		.ops = &clk_rcg2_shared_no_init_park_ops,
2567	},
2568};
2569
2570static struct clk_rcg2 gcc_usb30_tert_mock_utmi_clk_src = {
2571	.cmd_rcgr = 0xe1054,
2572	.mnd_width = 0,
2573	.hid_width = 5,
2574	.parent_map = gcc_parent_map_0,
2575	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2576	.clkr.hw.init = &(const struct clk_init_data) {
2577		.name = "gcc_usb30_tert_mock_utmi_clk_src",
2578		.parent_data = gcc_parent_data_0,
2579		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
2580		.flags = CLK_SET_RATE_PARENT,
2581		.ops = &clk_rcg2_shared_no_init_park_ops,
2582	},
2583};
2584
2585static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {
2586	.cmd_rcgr = 0x9a088,
2587	.mnd_width = 0,
2588	.hid_width = 5,
2589	.parent_map = gcc_parent_map_8,
2590	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2591	.clkr.hw.init = &(const struct clk_init_data) {
2592		.name = "gcc_usb3_mp_phy_aux_clk_src",
2593		.parent_data = gcc_parent_data_8,
2594		.num_parents = ARRAY_SIZE(gcc_parent_data_8),
2595		.flags = CLK_SET_RATE_PARENT,
2596		.ops = &clk_rcg2_shared_no_init_park_ops,
2597	},
2598};
2599
2600static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
2601	.cmd_rcgr = 0x3f090,
2602	.mnd_width = 0,
2603	.hid_width = 5,
2604	.parent_map = gcc_parent_map_8,
2605	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2606	.clkr.hw.init = &(const struct clk_init_data) {
2607		.name = "gcc_usb3_prim_phy_aux_clk_src",
2608		.parent_data = gcc_parent_data_8,
2609		.num_parents = ARRAY_SIZE(gcc_parent_data_8),
2610		.flags = CLK_SET_RATE_PARENT,
2611		.ops = &clk_rcg2_shared_no_init_park_ops,
2612	},
2613};
2614
2615static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
2616	.cmd_rcgr = 0xe2080,
2617	.mnd_width = 0,
2618	.hid_width = 5,
2619	.parent_map = gcc_parent_map_8,
2620	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2621	.clkr.hw.init = &(const struct clk_init_data) {
2622		.name = "gcc_usb3_sec_phy_aux_clk_src",
2623		.parent_data = gcc_parent_data_8,
2624		.num_parents = ARRAY_SIZE(gcc_parent_data_8),
2625		.flags = CLK_SET_RATE_PARENT,
2626		.ops = &clk_rcg2_shared_no_init_park_ops,
2627	},
2628};
2629
2630static struct clk_rcg2 gcc_usb3_tert_phy_aux_clk_src = {
2631	.cmd_rcgr = 0xe1080,
2632	.mnd_width = 0,
2633	.hid_width = 5,
2634	.parent_map = gcc_parent_map_8,
2635	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2636	.clkr.hw.init = &(const struct clk_init_data) {
2637		.name = "gcc_usb3_tert_phy_aux_clk_src",
2638		.parent_data = gcc_parent_data_8,
2639		.num_parents = ARRAY_SIZE(gcc_parent_data_8),
2640		.flags = CLK_SET_RATE_PARENT,
2641		.ops = &clk_rcg2_shared_no_init_park_ops,
2642	},
2643};
2644
2645static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] = {
2646	F(177666750, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
2647	F(355333500, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
2648	{ }
2649};
2650
2651static struct clk_rcg2 gcc_usb4_0_master_clk_src = {
2652	.cmd_rcgr = 0x2b02c,
2653	.mnd_width = 8,
2654	.hid_width = 5,
2655	.parent_map = gcc_parent_map_9,
2656	.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
2657	.clkr.hw.init = &(const struct clk_init_data) {
2658		.name = "gcc_usb4_0_master_clk_src",
2659		.parent_data = gcc_parent_data_9,
2660		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
2661		.flags = CLK_SET_RATE_PARENT,
2662		.ops = &clk_rcg2_shared_no_init_park_ops,
2663	},
2664};
2665
2666static const struct freq_tbl ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src[] = {
2667	F(19200000, P_BI_TCXO, 1, 0, 0),
2668	F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
2669	F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
2670	{ }
2671};
2672
2673static struct clk_rcg2 gcc_usb4_0_phy_pcie_pipe_clk_src = {
2674	.cmd_rcgr = 0x2b104,
2675	.mnd_width = 0,
2676	.hid_width = 5,
2677	.parent_map = gcc_parent_map_32,
2678	.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
2679	.clkr.hw.init = &(const struct clk_init_data) {
2680		.name = "gcc_usb4_0_phy_pcie_pipe_clk_src",
2681		.parent_data = gcc_parent_data_32,
2682		.num_parents = ARRAY_SIZE(gcc_parent_data_32),
2683		.flags = CLK_SET_RATE_PARENT,
2684		.ops = &clk_rcg2_shared_no_init_park_ops,
2685	},
2686};
2687
2688static struct clk_rcg2 gcc_usb4_0_sb_if_clk_src = {
2689	.cmd_rcgr = 0x2b0a0,
2690	.mnd_width = 0,
2691	.hid_width = 5,
2692	.parent_map = gcc_parent_map_5,
2693	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2694	.clkr.hw.init = &(const struct clk_init_data) {
2695		.name = "gcc_usb4_0_sb_if_clk_src",
2696		.parent_data = gcc_parent_data_5,
2697		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
2698		.flags = CLK_SET_RATE_PARENT,
2699		.ops = &clk_rcg2_shared_no_init_park_ops,
2700	},
2701};
2702
2703static struct clk_rcg2 gcc_usb4_0_tmu_clk_src = {
2704	.cmd_rcgr = 0x2b084,
2705	.mnd_width = 0,
2706	.hid_width = 5,
2707	.parent_map = gcc_parent_map_10,
2708	.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
2709	.clkr.hw.init = &(const struct clk_init_data) {
2710		.name = "gcc_usb4_0_tmu_clk_src",
2711		.parent_data = gcc_parent_data_10,
2712		.num_parents = ARRAY_SIZE(gcc_parent_data_10),
2713		.flags = CLK_SET_RATE_PARENT,
2714		.ops = &clk_rcg2_shared_no_init_park_ops,
2715	},
2716};
2717
2718static struct clk_rcg2 gcc_usb4_1_master_clk_src = {
2719	.cmd_rcgr = 0x2d02c,
2720	.mnd_width = 8,
2721	.hid_width = 5,
2722	.parent_map = gcc_parent_map_9,
2723	.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
2724	.clkr.hw.init = &(const struct clk_init_data) {
2725		.name = "gcc_usb4_1_master_clk_src",
2726		.parent_data = gcc_parent_data_9,
2727		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
2728		.flags = CLK_SET_RATE_PARENT,
2729		.ops = &clk_rcg2_shared_no_init_park_ops,
2730	},
2731};
2732
2733static const struct freq_tbl ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src[] = {
2734	F(19200000, P_BI_TCXO, 1, 0, 0),
2735	F(177666750, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
2736	F(355333500, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
2737	{ }
2738};
2739
2740static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = {
2741	.cmd_rcgr = 0x2d128,
2742	.mnd_width = 0,
2743	.hid_width = 5,
2744	.parent_map = gcc_parent_map_11,
2745	.freq_tbl = ftbl_gcc_usb4_1_phy_pcie_pipe_clk_src,
2746	.clkr.hw.init = &(const struct clk_init_data) {
2747		.name = "gcc_usb4_1_phy_pcie_pipe_clk_src",
2748		.parent_data = gcc_parent_data_11,
2749		.num_parents = ARRAY_SIZE(gcc_parent_data_11),
2750		.flags = CLK_SET_RATE_PARENT,
2751		.ops = &clk_rcg2_shared_no_init_park_ops,
2752	},
2753};
2754
2755static const struct freq_tbl ftbl_gcc_usb4_1_phy_pll_pipe_clk_src[] = {
2756	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
2757	F(311000000, P_GCC_GPLL5_OUT_MAIN, 3, 0, 0),
2758	{ }
2759};
2760
2761static struct clk_rcg2 gcc_usb4_1_phy_pll_pipe_clk_src = {
2762	.cmd_rcgr = 0x2d0c8,
2763	.mnd_width = 0,
2764	.hid_width = 5,
2765	.parent_map = gcc_parent_map_41,
2766	.freq_tbl = ftbl_gcc_usb4_1_phy_pll_pipe_clk_src,
2767	.clkr.hw.init = &(const struct clk_init_data) {
2768		.name = "gcc_usb4_1_phy_pll_pipe_clk_src",
2769		.parent_data = gcc_parent_data_41,
2770		.num_parents = ARRAY_SIZE(gcc_parent_data_41),
2771		.flags = CLK_SET_RATE_PARENT,
2772		.ops = &clk_rcg2_shared_no_init_park_ops,
2773	},
2774};
2775
2776static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = {
2777	.cmd_rcgr = 0x2d0ac,
2778	.mnd_width = 0,
2779	.hid_width = 5,
2780	.parent_map = gcc_parent_map_5,
2781	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2782	.clkr.hw.init = &(const struct clk_init_data) {
2783		.name = "gcc_usb4_1_sb_if_clk_src",
2784		.parent_data = gcc_parent_data_5,
2785		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
2786		.flags = CLK_SET_RATE_PARENT,
2787		.ops = &clk_rcg2_shared_no_init_park_ops,
2788	},
2789};
2790
2791static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = {
2792	.cmd_rcgr = 0x2d090,
2793	.mnd_width = 0,
2794	.hid_width = 5,
2795	.parent_map = gcc_parent_map_10,
2796	.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
2797	.clkr.hw.init = &(const struct clk_init_data) {
2798		.name = "gcc_usb4_1_tmu_clk_src",
2799		.parent_data = gcc_parent_data_10,
2800		.num_parents = ARRAY_SIZE(gcc_parent_data_10),
2801		.flags = CLK_SET_RATE_PARENT,
2802		.ops = &clk_rcg2_shared_no_init_park_ops,
2803	},
2804};
2805
2806static struct clk_rcg2 gcc_usb4_2_master_clk_src = {
2807	.cmd_rcgr = 0xe002c,
2808	.mnd_width = 8,
2809	.hid_width = 5,
2810	.parent_map = gcc_parent_map_9,
2811	.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
2812	.clkr.hw.init = &(const struct clk_init_data) {
2813		.name = "gcc_usb4_2_master_clk_src",
2814		.parent_data = gcc_parent_data_9,
2815		.num_parents = ARRAY_SIZE(gcc_parent_data_9),
2816		.flags = CLK_SET_RATE_PARENT,
2817		.ops = &clk_rcg2_shared_no_init_park_ops,
2818	},
2819};
2820
2821static struct clk_rcg2 gcc_usb4_2_phy_pcie_pipe_clk_src = {
2822	.cmd_rcgr = 0xe0108,
2823	.mnd_width = 0,
2824	.hid_width = 5,
2825	.parent_map = gcc_parent_map_11,
2826	.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
2827	.clkr.hw.init = &(const struct clk_init_data) {
2828		.name = "gcc_usb4_2_phy_pcie_pipe_clk_src",
2829		.parent_data = gcc_parent_data_11,
2830		.num_parents = ARRAY_SIZE(gcc_parent_data_11),
2831		.flags = CLK_SET_RATE_PARENT,
2832		.ops = &clk_rcg2_shared_no_init_park_ops,
2833	},
2834};
2835
2836static struct clk_rcg2 gcc_usb4_2_sb_if_clk_src = {
2837	.cmd_rcgr = 0xe00a4,
2838	.mnd_width = 0,
2839	.hid_width = 5,
2840	.parent_map = gcc_parent_map_5,
2841	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
2842	.clkr.hw.init = &(const struct clk_init_data) {
2843		.name = "gcc_usb4_2_sb_if_clk_src",
2844		.parent_data = gcc_parent_data_5,
2845		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
2846		.flags = CLK_SET_RATE_PARENT,
2847		.ops = &clk_rcg2_shared_no_init_park_ops,
2848	},
2849};
2850
2851static struct clk_rcg2 gcc_usb4_2_tmu_clk_src = {
2852	.cmd_rcgr = 0xe0088,
2853	.mnd_width = 0,
2854	.hid_width = 5,
2855	.parent_map = gcc_parent_map_10,
2856	.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
2857	.clkr.hw.init = &(const struct clk_init_data) {
2858		.name = "gcc_usb4_2_tmu_clk_src",
2859		.parent_data = gcc_parent_data_10,
2860		.num_parents = ARRAY_SIZE(gcc_parent_data_10),
2861		.flags = CLK_SET_RATE_PARENT,
2862		.ops = &clk_rcg2_shared_no_init_park_ops,
2863	},
2864};
2865
2866static struct clk_regmap_div gcc_pcie_3b_pipe_div_clk_src = {
2867	.reg = 0x94070,
2868	.shift = 0,
2869	.width = 4,
2870	.clkr.hw.init = &(const struct clk_init_data) {
2871		.name = "gcc_pcie_3b_pipe_div_clk_src",
2872		.parent_hws = (const struct clk_hw*[]) {
2873			&gcc_pcie_3b_pipe_clk_src.clkr.hw,
2874		},
2875		.num_parents = 1,
2876		.flags = CLK_SET_RATE_PARENT,
2877		.ops = &clk_regmap_div_ro_ops,
2878	},
2879};
2880
2881static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = {
2882	.reg = 0x88060,
2883	.shift = 0,
2884	.width = 4,
2885	.clkr.hw.init = &(const struct clk_init_data) {
2886		.name = "gcc_pcie_4_pipe_div_clk_src",
2887		.parent_hws = (const struct clk_hw*[]) {
2888			&gcc_pcie_4_pipe_clk_src.clkr.hw,
2889		},
2890		.num_parents = 1,
2891		.flags = CLK_SET_RATE_PARENT,
2892		.ops = &clk_regmap_div_ro_ops,
2893	},
2894};
2895
2896static struct clk_regmap_div gcc_pcie_5_pipe_div_clk_src = {
2897	.reg = 0xc306c,
2898	.shift = 0,
2899	.width = 4,
2900	.clkr.hw.init = &(const struct clk_init_data) {
2901		.name = "gcc_pcie_5_pipe_div_clk_src",
2902		.parent_hws = (const struct clk_hw*[]) {
2903			&gcc_pcie_5_pipe_clk_src.clkr.hw,
2904		},
2905		.num_parents = 1,
2906		.flags = CLK_SET_RATE_PARENT,
2907		.ops = &clk_regmap_div_ro_ops,
2908	},
2909};
2910
2911static struct clk_regmap_div gcc_pcie_6_pipe_div_clk_src = {
2912	.reg = 0x8a060,
2913	.shift = 0,
2914	.width = 4,
2915	.clkr.hw.init = &(const struct clk_init_data) {
2916		.name = "gcc_pcie_6_pipe_div_clk_src",
2917		.parent_hws = (const struct clk_hw*[]) {
2918			&gcc_pcie_6_pipe_clk_src.clkr.hw,
2919		},
2920		.num_parents = 1,
2921		.flags = CLK_SET_RATE_PARENT,
2922		.ops = &clk_regmap_div_ro_ops,
2923	},
2924};
2925
2926static struct clk_regmap_div gcc_qupv3_oob_s0_clk_src = {
2927	.reg = 0xe7024,
2928	.shift = 0,
2929	.width = 4,
2930	.clkr.hw.init = &(const struct clk_init_data) {
2931		.name = "gcc_qupv3_oob_s0_clk_src",
2932		.parent_hws = (const struct clk_hw*[]) {
2933			&gcc_qupv3_oob_qspi_s0_clk_src.clkr.hw,
2934		},
2935		.num_parents = 1,
2936		.flags = CLK_SET_RATE_PARENT,
2937		.ops = &clk_regmap_div_ro_ops,
2938	},
2939};
2940
2941static struct clk_regmap_div gcc_qupv3_oob_s1_clk_src = {
2942	.reg = 0xe7038,
2943	.shift = 0,
2944	.width = 4,
2945	.clkr.hw.init = &(const struct clk_init_data) {
2946		.name = "gcc_qupv3_oob_s1_clk_src",
2947		.parent_hws = (const struct clk_hw*[]) {
2948			&gcc_qupv3_oob_qspi_s1_clk_src.clkr.hw,
2949		},
2950		.num_parents = 1,
2951		.flags = CLK_SET_RATE_PARENT,
2952		.ops = &clk_regmap_div_ro_ops,
2953	},
2954};
2955
2956static struct clk_regmap_div gcc_qupv3_wrap0_s2_clk_src = {
2957	.reg = 0x2828c,
2958	.shift = 0,
2959	.width = 4,
2960	.clkr.hw.init = &(const struct clk_init_data) {
2961		.name = "gcc_qupv3_wrap0_s2_clk_src",
2962		.parent_hws = (const struct clk_hw*[]) {
2963			&gcc_qupv3_wrap0_qspi_s2_clk_src.clkr.hw,
2964		},
2965		.num_parents = 1,
2966		.flags = CLK_SET_RATE_PARENT,
2967		.ops = &clk_regmap_div_ro_ops,
2968	},
2969};
2970
2971static struct clk_regmap_div gcc_qupv3_wrap0_s3_clk_src = {
2972	.reg = 0x282a0,
2973	.shift = 0,
2974	.width = 4,
2975	.clkr.hw.init = &(const struct clk_init_data) {
2976		.name = "gcc_qupv3_wrap0_s3_clk_src",
2977		.parent_hws = (const struct clk_hw*[]) {
2978			&gcc_qupv3_wrap0_qspi_s3_clk_src.clkr.hw,
2979		},
2980		.num_parents = 1,
2981		.flags = CLK_SET_RATE_PARENT,
2982		.ops = &clk_regmap_div_ro_ops,
2983	},
2984};
2985
2986static struct clk_regmap_div gcc_qupv3_wrap0_s6_clk_src = {
2987	.reg = 0x2852c,
2988	.shift = 0,
2989	.width = 4,
2990	.clkr.hw.init = &(const struct clk_init_data) {
2991		.name = "gcc_qupv3_wrap0_s6_clk_src",
2992		.parent_hws = (const struct clk_hw*[]) {
2993			&gcc_qupv3_wrap0_qspi_s6_clk_src.clkr.hw,
2994		},
2995		.num_parents = 1,
2996		.flags = CLK_SET_RATE_PARENT,
2997		.ops = &clk_regmap_div_ro_ops,
2998	},
2999};
3000
3001static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = {
3002	.reg = 0xb328c,
3003	.shift = 0,
3004	.width = 4,
3005	.clkr.hw.init = &(const struct clk_init_data) {
3006		.name = "gcc_qupv3_wrap1_s2_clk_src",
3007		.parent_hws = (const struct clk_hw*[]) {
3008			&gcc_qupv3_wrap1_qspi_s2_clk_src.clkr.hw,
3009		},
3010		.num_parents = 1,
3011		.flags = CLK_SET_RATE_PARENT,
3012		.ops = &clk_regmap_div_ro_ops,
3013	},
3014};
3015
3016static struct clk_regmap_div gcc_qupv3_wrap1_s3_clk_src = {
3017	.reg = 0xb32a0,
3018	.shift = 0,
3019	.width = 4,
3020	.clkr.hw.init = &(const struct clk_init_data) {
3021		.name = "gcc_qupv3_wrap1_s3_clk_src",
3022		.parent_hws = (const struct clk_hw*[]) {
3023			&gcc_qupv3_wrap1_qspi_s3_clk_src.clkr.hw,
3024		},
3025		.num_parents = 1,
3026		.flags = CLK_SET_RATE_PARENT,
3027		.ops = &clk_regmap_div_ro_ops,
3028	},
3029};
3030
3031static struct clk_regmap_div gcc_qupv3_wrap1_s6_clk_src = {
3032	.reg = 0xb352c,
3033	.shift = 0,
3034	.width = 4,
3035	.clkr.hw.init = &(const struct clk_init_data) {
3036		.name = "gcc_qupv3_wrap1_s6_clk_src",
3037		.parent_hws = (const struct clk_hw*[]) {
3038			&gcc_qupv3_wrap1_qspi_s6_clk_src.clkr.hw,
3039		},
3040		.num_parents = 1,
3041		.flags = CLK_SET_RATE_PARENT,
3042		.ops = &clk_regmap_div_ro_ops,
3043	},
3044};
3045
3046static struct clk_regmap_div gcc_qupv3_wrap2_s2_clk_src = {
3047	.reg = 0xb428c,
3048	.shift = 0,
3049	.width = 4,
3050	.clkr.hw.init = &(const struct clk_init_data) {
3051		.name = "gcc_qupv3_wrap2_s2_clk_src",
3052		.parent_hws = (const struct clk_hw*[]) {
3053			&gcc_qupv3_wrap2_qspi_s2_clk_src.clkr.hw,
3054		},
3055		.num_parents = 1,
3056		.flags = CLK_SET_RATE_PARENT,
3057		.ops = &clk_regmap_div_ro_ops,
3058	},
3059};
3060
3061static struct clk_regmap_div gcc_qupv3_wrap2_s3_clk_src = {
3062	.reg = 0xb42a0,
3063	.shift = 0,
3064	.width = 4,
3065	.clkr.hw.init = &(const struct clk_init_data) {
3066		.name = "gcc_qupv3_wrap2_s3_clk_src",
3067		.parent_hws = (const struct clk_hw*[]) {
3068			&gcc_qupv3_wrap2_qspi_s3_clk_src.clkr.hw,
3069		},
3070		.num_parents = 1,
3071		.flags = CLK_SET_RATE_PARENT,
3072		.ops = &clk_regmap_div_ro_ops,
3073	},
3074};
3075
3076static struct clk_regmap_div gcc_qupv3_wrap2_s6_clk_src = {
3077	.reg = 0xb452c,
3078	.shift = 0,
3079	.width = 4,
3080	.clkr.hw.init = &(const struct clk_init_data) {
3081		.name = "gcc_qupv3_wrap2_s6_clk_src",
3082		.parent_hws = (const struct clk_hw*[]) {
3083			&gcc_qupv3_wrap2_qspi_s6_clk_src.clkr.hw,
3084		},
3085		.num_parents = 1,
3086		.flags = CLK_SET_RATE_PARENT,
3087		.ops = &clk_regmap_div_ro_ops,
3088	},
3089};
3090
3091static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = {
3092	.reg = 0xbc174,
3093	.shift = 0,
3094	.width = 4,
3095	.clkr.hw.init = &(const struct clk_init_data) {
3096		.name = "gcc_usb20_mock_utmi_postdiv_clk_src",
3097		.parent_hws = (const struct clk_hw*[]) {
3098			&gcc_usb20_mock_utmi_clk_src.clkr.hw,
3099		},
3100		.num_parents = 1,
3101		.flags = CLK_SET_RATE_PARENT,
3102		.ops = &clk_regmap_div_ro_ops,
3103	},
3104};
3105
3106static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = {
3107	.reg = 0x9a06c,
3108	.shift = 0,
3109	.width = 4,
3110	.clkr.hw.init = &(const struct clk_init_data) {
3111		.name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src",
3112		.parent_hws = (const struct clk_hw*[]) {
3113			&gcc_usb30_mp_mock_utmi_clk_src.clkr.hw,
3114		},
3115		.num_parents = 1,
3116		.flags = CLK_SET_RATE_PARENT,
3117		.ops = &clk_regmap_div_ro_ops,
3118	},
3119};
3120
3121static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
3122	.reg = 0x3f07c,
3123	.shift = 0,
3124	.width = 4,
3125	.clkr.hw.init = &(const struct clk_init_data) {
3126		.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
3127		.parent_hws = (const struct clk_hw*[]) {
3128			&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
3129		},
3130		.num_parents = 1,
3131		.flags = CLK_SET_RATE_PARENT,
3132		.ops = &clk_regmap_div_ro_ops,
3133	},
3134};
3135
3136static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
3137	.reg = 0xe206c,
3138	.shift = 0,
3139	.width = 4,
3140	.clkr.hw.init = &(const struct clk_init_data) {
3141		.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
3142		.parent_hws = (const struct clk_hw*[]) {
3143			&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
3144		},
3145		.num_parents = 1,
3146		.flags = CLK_SET_RATE_PARENT,
3147		.ops = &clk_regmap_div_ro_ops,
3148	},
3149};
3150
3151static struct clk_regmap_div gcc_usb30_tert_mock_utmi_postdiv_clk_src = {
3152	.reg = 0xe106c,
3153	.shift = 0,
3154	.width = 4,
3155	.clkr.hw.init = &(const struct clk_init_data) {
3156		.name = "gcc_usb30_tert_mock_utmi_postdiv_clk_src",
3157		.parent_hws = (const struct clk_hw*[]) {
3158			&gcc_usb30_tert_mock_utmi_clk_src.clkr.hw,
3159		},
3160		.num_parents = 1,
3161		.flags = CLK_SET_RATE_PARENT,
3162		.ops = &clk_regmap_div_ro_ops,
3163	},
3164};
3165
3166static struct clk_branch gcc_aggre_noc_pcie_3a_west_sf_axi_clk = {
3167	.halt_reg = 0xdc0bc,
3168	.halt_check = BRANCH_HALT_VOTED,
3169	.clkr = {
3170		.enable_reg = 0x62008,
3171		.enable_mask = BIT(27),
3172		.hw.init = &(const struct clk_init_data) {
3173			.name = "gcc_aggre_noc_pcie_3a_west_sf_axi_clk",
3174			.ops = &clk_branch2_ops,
3175		},
3176	},
3177};
3178
3179static struct clk_branch gcc_aggre_noc_pcie_3b_west_sf_axi_clk = {
3180	.halt_reg = 0x941ec,
3181	.halt_check = BRANCH_HALT_VOTED,
3182	.clkr = {
3183		.enable_reg = 0x62008,
3184		.enable_mask = BIT(28),
3185		.hw.init = &(const struct clk_init_data) {
3186			.name = "gcc_aggre_noc_pcie_3b_west_sf_axi_clk",
3187			.ops = &clk_branch2_ops,
3188		},
3189	},
3190};
3191
3192static struct clk_branch gcc_aggre_noc_pcie_4_west_sf_axi_clk = {
3193	.halt_reg = 0x881d0,
3194	.halt_check = BRANCH_HALT_VOTED,
3195	.clkr = {
3196		.enable_reg = 0x62008,
3197		.enable_mask = BIT(29),
3198		.hw.init = &(const struct clk_init_data) {
3199			.name = "gcc_aggre_noc_pcie_4_west_sf_axi_clk",
3200			.ops = &clk_branch2_ops,
3201		},
3202	},
3203};
3204
3205static struct clk_branch gcc_aggre_noc_pcie_5_east_sf_axi_clk = {
3206	.halt_reg = 0xc30d0,
3207	.halt_check = BRANCH_HALT_VOTED,
3208	.clkr = {
3209		.enable_reg = 0x62008,
3210		.enable_mask = BIT(30),
3211		.hw.init = &(const struct clk_init_data) {
3212			.name = "gcc_aggre_noc_pcie_5_east_sf_axi_clk",
3213			.ops = &clk_branch2_ops,
3214		},
3215	},
3216};
3217
3218static struct clk_branch gcc_aggre_noc_pcie_6_west_sf_axi_clk = {
3219	.halt_reg = 0x8a1d0,
3220	.halt_check = BRANCH_HALT_VOTED,
3221	.clkr = {
3222		.enable_reg = 0x62008,
3223		.enable_mask = BIT(31),
3224		.hw.init = &(const struct clk_init_data) {
3225			.name = "gcc_aggre_noc_pcie_6_west_sf_axi_clk",
3226			.ops = &clk_branch2_ops,
3227		},
3228	},
3229};
3230
3231static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
3232	.halt_reg = 0x77000,
3233	.halt_check = BRANCH_HALT_VOTED,
3234	.hwcg_reg = 0x77000,
3235	.hwcg_bit = 1,
3236	.clkr = {
3237		.enable_reg = 0x77000,
3238		.enable_mask = BIT(0),
3239		.hw.init = &(const struct clk_init_data) {
3240			.name = "gcc_aggre_ufs_phy_axi_clk",
3241			.parent_hws = (const struct clk_hw*[]) {
3242				&gcc_ufs_phy_axi_clk_src.clkr.hw,
3243			},
3244			.num_parents = 1,
3245			.flags = CLK_SET_RATE_PARENT,
3246			.ops = &clk_branch2_ops,
3247		},
3248	},
3249};
3250
3251static struct clk_branch gcc_aggre_usb2_prim_axi_clk = {
3252	.halt_reg = 0xbc17c,
3253	.halt_check = BRANCH_HALT_VOTED,
3254	.hwcg_reg = 0xbc17c,
3255	.hwcg_bit = 1,
3256	.clkr = {
3257		.enable_reg = 0xbc17c,
3258		.enable_mask = BIT(0),
3259		.hw.init = &(const struct clk_init_data) {
3260			.name = "gcc_aggre_usb2_prim_axi_clk",
3261			.parent_hws = (const struct clk_hw*[]) {
3262				&gcc_usb20_master_clk_src.clkr.hw,
3263			},
3264			.num_parents = 1,
3265			.flags = CLK_SET_RATE_PARENT,
3266			.ops = &clk_branch2_ops,
3267		},
3268	},
3269};
3270
3271static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {
3272	.halt_reg = 0x9a004,
3273	.halt_check = BRANCH_HALT_VOTED,
3274	.hwcg_reg = 0x9a004,
3275	.hwcg_bit = 1,
3276	.clkr = {
3277		.enable_reg = 0x9a004,
3278		.enable_mask = BIT(0),
3279		.hw.init = &(const struct clk_init_data) {
3280			.name = "gcc_aggre_usb3_mp_axi_clk",
3281			.parent_hws = (const struct clk_hw*[]) {
3282				&gcc_usb30_mp_master_clk_src.clkr.hw,
3283			},
3284			.num_parents = 1,
3285			.flags = CLK_SET_RATE_PARENT,
3286			.ops = &clk_branch2_ops,
3287		},
3288	},
3289};
3290
3291static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
3292	.halt_reg = 0x3f00c,
3293	.halt_check = BRANCH_HALT_VOTED,
3294	.hwcg_reg = 0x3f00c,
3295	.hwcg_bit = 1,
3296	.clkr = {
3297		.enable_reg = 0x3f00c,
3298		.enable_mask = BIT(0),
3299		.hw.init = &(const struct clk_init_data) {
3300			.name = "gcc_aggre_usb3_prim_axi_clk",
3301			.parent_hws = (const struct clk_hw*[]) {
3302				&gcc_usb30_prim_master_clk_src.clkr.hw,
3303			},
3304			.num_parents = 1,
3305			.flags = CLK_SET_RATE_PARENT,
3306			.ops = &clk_branch2_ops,
3307		},
3308	},
3309};
3310
3311static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
3312	.halt_reg = 0xe2004,
3313	.halt_check = BRANCH_HALT_VOTED,
3314	.hwcg_reg = 0xe2004,
3315	.hwcg_bit = 1,
3316	.clkr = {
3317		.enable_reg = 0xe2004,
3318		.enable_mask = BIT(0),
3319		.hw.init = &(const struct clk_init_data) {
3320			.name = "gcc_aggre_usb3_sec_axi_clk",
3321			.parent_hws = (const struct clk_hw*[]) {
3322				&gcc_usb30_sec_master_clk_src.clkr.hw,
3323			},
3324			.num_parents = 1,
3325			.flags = CLK_SET_RATE_PARENT,
3326			.ops = &clk_branch2_ops,
3327		},
3328	},
3329};
3330
3331static struct clk_branch gcc_aggre_usb3_tert_axi_clk = {
3332	.halt_reg = 0xe1004,
3333	.halt_check = BRANCH_HALT_VOTED,
3334	.hwcg_reg = 0xe1004,
3335	.hwcg_bit = 1,
3336	.clkr = {
3337		.enable_reg = 0xe1004,
3338		.enable_mask = BIT(0),
3339		.hw.init = &(const struct clk_init_data) {
3340			.name = "gcc_aggre_usb3_tert_axi_clk",
3341			.parent_hws = (const struct clk_hw*[]) {
3342				&gcc_usb30_tert_master_clk_src.clkr.hw,
3343			},
3344			.num_parents = 1,
3345			.flags = CLK_SET_RATE_PARENT,
3346			.ops = &clk_branch2_ops,
3347		},
3348	},
3349};
3350
3351static struct clk_branch gcc_aggre_usb4_0_axi_clk = {
3352	.halt_reg = 0x2b000,
3353	.halt_check = BRANCH_HALT_VOTED,
3354	.hwcg_reg = 0x2b000,
3355	.hwcg_bit = 1,
3356	.clkr = {
3357		.enable_reg = 0x2b000,
3358		.enable_mask = BIT(0),
3359		.hw.init = &(const struct clk_init_data) {
3360			.name = "gcc_aggre_usb4_0_axi_clk",
3361			.parent_hws = (const struct clk_hw*[]) {
3362				&gcc_usb4_0_master_clk_src.clkr.hw,
3363			},
3364			.num_parents = 1,
3365			.flags = CLK_SET_RATE_PARENT,
3366			.ops = &clk_branch2_ops,
3367		},
3368	},
3369};
3370
3371static struct clk_branch gcc_aggre_usb4_1_axi_clk = {
3372	.halt_reg = 0x2d000,
3373	.halt_check = BRANCH_HALT_VOTED,
3374	.hwcg_reg = 0x2d000,
3375	.hwcg_bit = 1,
3376	.clkr = {
3377		.enable_reg = 0x2d000,
3378		.enable_mask = BIT(0),
3379		.hw.init = &(const struct clk_init_data) {
3380			.name = "gcc_aggre_usb4_1_axi_clk",
3381			.parent_hws = (const struct clk_hw*[]) {
3382				&gcc_usb4_1_master_clk_src.clkr.hw,
3383			},
3384			.num_parents = 1,
3385			.flags = CLK_SET_RATE_PARENT,
3386			.ops = &clk_branch2_ops,
3387		},
3388	},
3389};
3390
3391static struct clk_branch gcc_aggre_usb4_2_axi_clk = {
3392	.halt_reg = 0xe0000,
3393	.halt_check = BRANCH_HALT_VOTED,
3394	.hwcg_reg = 0xe0000,
3395	.hwcg_bit = 1,
3396	.clkr = {
3397		.enable_reg = 0xe0000,
3398		.enable_mask = BIT(0),
3399		.hw.init = &(const struct clk_init_data) {
3400			.name = "gcc_aggre_usb4_2_axi_clk",
3401			.parent_hws = (const struct clk_hw*[]) {
3402				&gcc_usb4_2_master_clk_src.clkr.hw,
3403			},
3404			.num_parents = 1,
3405			.flags = CLK_SET_RATE_PARENT,
3406			.ops = &clk_branch2_ops,
3407		},
3408	},
3409};
3410
3411static struct clk_branch gcc_av1e_ahb_clk = {
3412	.halt_reg = 0x9b02c,
3413	.halt_check = BRANCH_HALT_VOTED,
3414	.hwcg_reg = 0x9b02c,
3415	.hwcg_bit = 1,
3416	.clkr = {
3417		.enable_reg = 0x9b02c,
3418		.enable_mask = BIT(0),
3419		.hw.init = &(const struct clk_init_data) {
3420			.name = "gcc_av1e_ahb_clk",
3421			.ops = &clk_branch2_ops,
3422		},
3423	},
3424};
3425
3426static struct clk_branch gcc_av1e_axi_clk = {
3427	.halt_reg = 0x9b030,
3428	.halt_check = BRANCH_HALT_SKIP,
3429	.hwcg_reg = 0x9b030,
3430	.hwcg_bit = 1,
3431	.clkr = {
3432		.enable_reg = 0x9b030,
3433		.enable_mask = BIT(0),
3434		.hw.init = &(const struct clk_init_data) {
3435			.name = "gcc_av1e_axi_clk",
3436			.ops = &clk_branch2_ops,
3437		},
3438	},
3439};
3440
3441static struct clk_branch gcc_av1e_xo_clk = {
3442	.halt_reg = 0x9b044,
3443	.halt_check = BRANCH_HALT,
3444	.clkr = {
3445		.enable_reg = 0x9b044,
3446		.enable_mask = BIT(0),
3447		.hw.init = &(const struct clk_init_data) {
3448			.name = "gcc_av1e_xo_clk",
3449			.ops = &clk_branch2_ops,
3450		},
3451	},
3452};
3453
3454static struct clk_branch gcc_boot_rom_ahb_clk = {
3455	.halt_reg = 0x34038,
3456	.halt_check = BRANCH_HALT_VOTED,
3457	.hwcg_reg = 0x34038,
3458	.hwcg_bit = 1,
3459	.clkr = {
3460		.enable_reg = 0x62020,
3461		.enable_mask = BIT(27),
3462		.hw.init = &(const struct clk_init_data) {
3463			.name = "gcc_boot_rom_ahb_clk",
3464			.ops = &clk_branch2_ops,
3465		},
3466	},
3467};
3468
3469static struct clk_branch gcc_camera_hf_axi_clk = {
3470	.halt_reg = 0x26014,
3471	.halt_check = BRANCH_HALT_SKIP,
3472	.hwcg_reg = 0x26014,
3473	.hwcg_bit = 1,
3474	.clkr = {
3475		.enable_reg = 0x26014,
3476		.enable_mask = BIT(0),
3477		.hw.init = &(const struct clk_init_data) {
3478			.name = "gcc_camera_hf_axi_clk",
3479			.ops = &clk_branch2_ops,
3480		},
3481	},
3482};
3483
3484static struct clk_branch gcc_camera_sf_axi_clk = {
3485	.halt_reg = 0x26028,
3486	.halt_check = BRANCH_HALT_SKIP,
3487	.hwcg_reg = 0x26028,
3488	.hwcg_bit = 1,
3489	.clkr = {
3490		.enable_reg = 0x26028,
3491		.enable_mask = BIT(0),
3492		.hw.init = &(const struct clk_init_data) {
3493			.name = "gcc_camera_sf_axi_clk",
3494			.ops = &clk_branch2_ops,
3495		},
3496	},
3497};
3498
3499static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
3500	.halt_reg = 0x82004,
3501	.halt_check = BRANCH_HALT_VOTED,
3502	.hwcg_reg = 0x82004,
3503	.hwcg_bit = 1,
3504	.clkr = {
3505		.enable_reg = 0x62008,
3506		.enable_mask = BIT(19),
3507		.hw.init = &(const struct clk_init_data) {
3508			.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
3509			.ops = &clk_branch2_ops,
3510		},
3511	},
3512};
3513
3514static struct clk_branch gcc_cfg_noc_pcie_anoc_south_ahb_clk = {
3515	.halt_reg = 0xba2ec,
3516	.halt_check = BRANCH_HALT_VOTED,
3517	.hwcg_reg = 0xba2ec,
3518	.hwcg_bit = 1,
3519	.clkr = {
3520		.enable_reg = 0x62008,
3521		.enable_mask = BIT(16),
3522		.hw.init = &(const struct clk_init_data) {
3523			.name = "gcc_cfg_noc_pcie_anoc_south_ahb_clk",
3524			.ops = &clk_branch2_ops,
3525		},
3526	},
3527};
3528
3529static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = {
3530	.halt_reg = 0xbc178,
3531	.halt_check = BRANCH_HALT_VOTED,
3532	.hwcg_reg = 0xbc178,
3533	.hwcg_bit = 1,
3534	.clkr = {
3535		.enable_reg = 0xbc178,
3536		.enable_mask = BIT(0),
3537		.hw.init = &(const struct clk_init_data) {
3538			.name = "gcc_cfg_noc_usb2_prim_axi_clk",
3539			.parent_hws = (const struct clk_hw*[]) {
3540				&gcc_usb20_master_clk_src.clkr.hw,
3541			},
3542			.num_parents = 1,
3543			.flags = CLK_SET_RATE_PARENT,
3544			.ops = &clk_branch2_ops,
3545		},
3546	},
3547};
3548
3549static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {
3550	.halt_reg = 0x9a000,
3551	.halt_check = BRANCH_HALT_VOTED,
3552	.hwcg_reg = 0x9a000,
3553	.hwcg_bit = 1,
3554	.clkr = {
3555		.enable_reg = 0x9a000,
3556		.enable_mask = BIT(0),
3557		.hw.init = &(const struct clk_init_data) {
3558			.name = "gcc_cfg_noc_usb3_mp_axi_clk",
3559			.parent_hws = (const struct clk_hw*[]) {
3560				&gcc_usb30_mp_master_clk_src.clkr.hw,
3561			},
3562			.num_parents = 1,
3563			.flags = CLK_SET_RATE_PARENT,
3564			.ops = &clk_branch2_ops,
3565		},
3566	},
3567};
3568
3569static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
3570	.halt_reg = 0x3f000,
3571	.halt_check = BRANCH_HALT_VOTED,
3572	.hwcg_reg = 0x3f000,
3573	.hwcg_bit = 1,
3574	.clkr = {
3575		.enable_reg = 0x3f000,
3576		.enable_mask = BIT(0),
3577		.hw.init = &(const struct clk_init_data) {
3578			.name = "gcc_cfg_noc_usb3_prim_axi_clk",
3579			.parent_hws = (const struct clk_hw*[]) {
3580				&gcc_usb30_prim_master_clk_src.clkr.hw,
3581			},
3582			.num_parents = 1,
3583			.flags = CLK_SET_RATE_PARENT,
3584			.ops = &clk_branch2_ops,
3585		},
3586	},
3587};
3588
3589static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
3590	.halt_reg = 0xe2000,
3591	.halt_check = BRANCH_HALT_VOTED,
3592	.hwcg_reg = 0xe2000,
3593	.hwcg_bit = 1,
3594	.clkr = {
3595		.enable_reg = 0xe2000,
3596		.enable_mask = BIT(0),
3597		.hw.init = &(const struct clk_init_data) {
3598			.name = "gcc_cfg_noc_usb3_sec_axi_clk",
3599			.parent_hws = (const struct clk_hw*[]) {
3600				&gcc_usb30_sec_master_clk_src.clkr.hw,
3601			},
3602			.num_parents = 1,
3603			.flags = CLK_SET_RATE_PARENT,
3604			.ops = &clk_branch2_ops,
3605		},
3606	},
3607};
3608
3609static struct clk_branch gcc_cfg_noc_usb3_tert_axi_clk = {
3610	.halt_reg = 0xe1000,
3611	.halt_check = BRANCH_HALT_VOTED,
3612	.hwcg_reg = 0xe1000,
3613	.hwcg_bit = 1,
3614	.clkr = {
3615		.enable_reg = 0xe1000,
3616		.enable_mask = BIT(0),
3617		.hw.init = &(const struct clk_init_data) {
3618			.name = "gcc_cfg_noc_usb3_tert_axi_clk",
3619			.parent_hws = (const struct clk_hw*[]) {
3620				&gcc_usb30_tert_master_clk_src.clkr.hw,
3621			},
3622			.num_parents = 1,
3623			.flags = CLK_SET_RATE_PARENT,
3624			.ops = &clk_branch2_ops,
3625		},
3626	},
3627};
3628
3629static struct clk_branch gcc_cfg_noc_usb_anoc_ahb_clk = {
3630	.halt_reg = 0x3f004,
3631	.halt_check = BRANCH_HALT_VOTED,
3632	.hwcg_reg = 0x3f004,
3633	.hwcg_bit = 1,
3634	.clkr = {
3635		.enable_reg = 0x62008,
3636		.enable_mask = BIT(17),
3637		.hw.init = &(const struct clk_init_data) {
3638			.name = "gcc_cfg_noc_usb_anoc_ahb_clk",
3639			.ops = &clk_branch2_ops,
3640		},
3641	},
3642};
3643
3644static struct clk_branch gcc_cfg_noc_usb_anoc_south_ahb_clk = {
3645	.halt_reg = 0x3f008,
3646	.halt_check = BRANCH_HALT_VOTED,
3647	.hwcg_reg = 0x3f008,
3648	.hwcg_bit = 1,
3649	.clkr = {
3650		.enable_reg = 0x62008,
3651		.enable_mask = BIT(18),
3652		.hw.init = &(const struct clk_init_data) {
3653			.name = "gcc_cfg_noc_usb_anoc_south_ahb_clk",
3654			.ops = &clk_branch2_ops,
3655		},
3656	},
3657};
3658
3659static struct clk_branch gcc_disp_hf_axi_clk = {
3660	.halt_reg = 0x27008,
3661	.halt_check = BRANCH_HALT_SKIP,
3662	.clkr = {
3663		.enable_reg = 0x27008,
3664		.enable_mask = BIT(0),
3665		.hw.init = &(const struct clk_init_data) {
3666			.name = "gcc_disp_hf_axi_clk",
3667			.ops = &clk_branch2_ops,
3668			.flags = CLK_IS_CRITICAL,
3669		},
3670	},
3671};
3672
3673static struct clk_branch gcc_eva_ahb_clk = {
3674	.halt_reg = 0x9b004,
3675	.halt_check = BRANCH_HALT_VOTED,
3676	.hwcg_reg = 0x9b004,
3677	.hwcg_bit = 1,
3678	.clkr = {
3679		.enable_reg = 0x9b004,
3680		.enable_mask = BIT(0),
3681		.hw.init = &(const struct clk_init_data) {
3682			.name = "gcc_eva_ahb_clk",
3683			.ops = &clk_branch2_ops,
3684		},
3685	},
3686};
3687
3688static struct clk_branch gcc_eva_axi0_clk = {
3689	.halt_reg = 0x9b008,
3690	.halt_check = BRANCH_HALT_SKIP,
3691	.hwcg_reg = 0x9b008,
3692	.hwcg_bit = 1,
3693	.clkr = {
3694		.enable_reg = 0x9b008,
3695		.enable_mask = BIT(0),
3696		.hw.init = &(const struct clk_init_data) {
3697			.name = "gcc_eva_axi0_clk",
3698			.ops = &clk_branch2_ops,
3699		},
3700	},
3701};
3702
3703static struct clk_branch gcc_eva_axi0c_clk = {
3704	.halt_reg = 0x9b01c,
3705	.halt_check = BRANCH_HALT_VOTED,
3706	.hwcg_reg = 0x9b01c,
3707	.hwcg_bit = 1,
3708	.clkr = {
3709		.enable_reg = 0x9b01c,
3710		.enable_mask = BIT(0),
3711		.hw.init = &(const struct clk_init_data) {
3712			.name = "gcc_eva_axi0c_clk",
3713			.ops = &clk_branch2_ops,
3714		},
3715	},
3716};
3717
3718static struct clk_branch gcc_eva_xo_clk = {
3719	.halt_reg = 0x9b024,
3720	.halt_check = BRANCH_HALT,
3721	.clkr = {
3722		.enable_reg = 0x9b024,
3723		.enable_mask = BIT(0),
3724		.hw.init = &(const struct clk_init_data) {
3725			.name = "gcc_eva_xo_clk",
3726			.ops = &clk_branch2_ops,
3727		},
3728	},
3729};
3730
3731static struct clk_branch gcc_gp1_clk = {
3732	.halt_reg = 0x64000,
3733	.halt_check = BRANCH_HALT,
3734	.clkr = {
3735		.enable_reg = 0x64000,
3736		.enable_mask = BIT(0),
3737		.hw.init = &(const struct clk_init_data) {
3738			.name = "gcc_gp1_clk",
3739			.parent_hws = (const struct clk_hw*[]) {
3740				&gcc_gp1_clk_src.clkr.hw,
3741			},
3742			.num_parents = 1,
3743			.flags = CLK_SET_RATE_PARENT,
3744			.ops = &clk_branch2_ops,
3745		},
3746	},
3747};
3748
3749static struct clk_branch gcc_gp2_clk = {
3750	.halt_reg = 0x92000,
3751	.halt_check = BRANCH_HALT,
3752	.clkr = {
3753		.enable_reg = 0x92000,
3754		.enable_mask = BIT(0),
3755		.hw.init = &(const struct clk_init_data) {
3756			.name = "gcc_gp2_clk",
3757			.parent_hws = (const struct clk_hw*[]) {
3758				&gcc_gp2_clk_src.clkr.hw,
3759			},
3760			.num_parents = 1,
3761			.flags = CLK_SET_RATE_PARENT,
3762			.ops = &clk_branch2_ops,
3763		},
3764	},
3765};
3766
3767static struct clk_branch gcc_gp3_clk = {
3768	.halt_reg = 0x93000,
3769	.halt_check = BRANCH_HALT,
3770	.clkr = {
3771		.enable_reg = 0x93000,
3772		.enable_mask = BIT(0),
3773		.hw.init = &(const struct clk_init_data) {
3774			.name = "gcc_gp3_clk",
3775			.parent_hws = (const struct clk_hw*[]) {
3776				&gcc_gp3_clk_src.clkr.hw,
3777			},
3778			.num_parents = 1,
3779			.flags = CLK_SET_RATE_PARENT,
3780			.ops = &clk_branch2_ops,
3781		},
3782	},
3783};
3784
3785static struct clk_branch gcc_gpu_gemnoc_gfx_clk = {
3786	.halt_reg = 0x71010,
3787	.halt_check = BRANCH_HALT_VOTED,
3788	.hwcg_reg = 0x71010,
3789	.hwcg_bit = 1,
3790	.clkr = {
3791		.enable_reg = 0x71010,
3792		.enable_mask = BIT(0),
3793		.hw.init = &(const struct clk_init_data) {
3794			.name = "gcc_gpu_gemnoc_gfx_clk",
3795			.ops = &clk_branch2_ops,
3796		},
3797	},
3798};
3799
3800static struct clk_branch gcc_gpu_gpll0_clk_src = {
3801	.halt_reg = 0x71024,
3802	.halt_check = BRANCH_HALT_VOTED,
3803	.hwcg_reg = 0x71024,
3804	.hwcg_bit = 1,
3805	.clkr = {
3806		.enable_reg = 0x62038,
3807		.enable_mask = BIT(0),
3808		.hw.init = &(const struct clk_init_data) {
3809			.name = "gcc_gpu_gpll0_clk_src",
3810			.parent_hws = (const struct clk_hw*[]) {
3811				&gcc_gpll0.clkr.hw,
3812			},
3813			.num_parents = 1,
3814			.flags = CLK_SET_RATE_PARENT,
3815			.ops = &clk_branch2_ops,
3816		},
3817	},
3818};
3819
3820static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
3821	.halt_reg = 0x7102c,
3822	.halt_check = BRANCH_HALT_VOTED,
3823	.hwcg_reg = 0x7102c,
3824	.hwcg_bit = 1,
3825	.clkr = {
3826		.enable_reg = 0x62038,
3827		.enable_mask = BIT(1),
3828		.hw.init = &(const struct clk_init_data) {
3829			.name = "gcc_gpu_gpll0_div_clk_src",
3830			.parent_hws = (const struct clk_hw*[]) {
3831				&gcc_gpll0_out_even.clkr.hw,
3832			},
3833			.num_parents = 1,
3834			.flags = CLK_SET_RATE_PARENT,
3835			.ops = &clk_branch2_ops,
3836		},
3837	},
3838};
3839
3840static struct clk_branch gcc_pcie_0_aux_clk = {
3841	.halt_reg = 0xc8018,
3842	.halt_check = BRANCH_HALT_VOTED,
3843	.clkr = {
3844		.enable_reg = 0x62010,
3845		.enable_mask = BIT(25),
3846		.hw.init = &(const struct clk_init_data) {
3847			.name = "gcc_pcie_0_aux_clk",
3848			.parent_hws = (const struct clk_hw*[]) {
3849				&gcc_pcie_0_aux_clk_src.clkr.hw,
3850			},
3851			.num_parents = 1,
3852			.flags = CLK_SET_RATE_PARENT,
3853			.ops = &clk_branch2_ops,
3854		},
3855	},
3856};
3857
3858static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
3859	.halt_reg = 0xba4a8,
3860	.halt_check = BRANCH_HALT_VOTED,
3861	.hwcg_reg = 0xba4a8,
3862	.hwcg_bit = 1,
3863	.clkr = {
3864		.enable_reg = 0x62010,
3865		.enable_mask = BIT(24),
3866		.hw.init = &(const struct clk_init_data) {
3867			.name = "gcc_pcie_0_cfg_ahb_clk",
3868			.ops = &clk_branch2_ops,
3869		},
3870	},
3871};
3872
3873static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
3874	.halt_reg = 0xba498,
3875	.halt_check = BRANCH_HALT_SKIP,
3876	.hwcg_reg = 0xba498,
3877	.hwcg_bit = 1,
3878	.clkr = {
3879		.enable_reg = 0x62010,
3880		.enable_mask = BIT(23),
3881		.hw.init = &(const struct clk_init_data) {
3882			.name = "gcc_pcie_0_mstr_axi_clk",
3883			.ops = &clk_branch2_ops,
3884		},
3885	},
3886};
3887
3888static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
3889	.halt_reg = 0xc8038,
3890	.halt_check = BRANCH_HALT_VOTED,
3891	.clkr = {
3892		.enable_reg = 0x62010,
3893		.enable_mask = BIT(27),
3894		.hw.init = &(const struct clk_init_data) {
3895			.name = "gcc_pcie_0_phy_rchng_clk",
3896			.parent_hws = (const struct clk_hw*[]) {
3897				&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
3898			},
3899			.num_parents = 1,
3900			.flags = CLK_SET_RATE_PARENT,
3901			.ops = &clk_branch2_ops,
3902		},
3903	},
3904};
3905
3906static struct clk_branch gcc_pcie_0_pipe_clk = {
3907	.halt_reg = 0xc8028,
3908	.halt_check = BRANCH_HALT_SKIP,
3909	.clkr = {
3910		.enable_reg = 0x62010,
3911		.enable_mask = BIT(26),
3912		.hw.init = &(const struct clk_init_data) {
3913			.name = "gcc_pcie_0_pipe_clk",
3914			.parent_hws = (const struct clk_hw*[]) {
3915				&gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
3916			},
3917			.num_parents = 1,
3918			.flags = CLK_SET_RATE_PARENT,
3919			.ops = &clk_branch2_ops,
3920		},
3921	},
3922};
3923
3924static struct clk_branch gcc_pcie_0_slv_axi_clk = {
3925	.halt_reg = 0xba488,
3926	.halt_check = BRANCH_HALT_VOTED,
3927	.hwcg_reg = 0xba488,
3928	.hwcg_bit = 1,
3929	.clkr = {
3930		.enable_reg = 0x62010,
3931		.enable_mask = BIT(22),
3932		.hw.init = &(const struct clk_init_data) {
3933			.name = "gcc_pcie_0_slv_axi_clk",
3934			.ops = &clk_branch2_ops,
3935		},
3936	},
3937};
3938
3939static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
3940	.halt_reg = 0xba484,
3941	.halt_check = BRANCH_HALT_VOTED,
3942	.clkr = {
3943		.enable_reg = 0x62010,
3944		.enable_mask = BIT(21),
3945		.hw.init = &(const struct clk_init_data) {
3946			.name = "gcc_pcie_0_slv_q2a_axi_clk",
3947			.ops = &clk_branch2_ops,
3948		},
3949	},
3950};
3951
3952static struct clk_branch gcc_pcie_1_aux_clk = {
3953	.halt_reg = 0x2e018,
3954	.halt_check = BRANCH_HALT_VOTED,
3955	.clkr = {
3956		.enable_reg = 0x62010,
3957		.enable_mask = BIT(18),
3958		.hw.init = &(const struct clk_init_data) {
3959			.name = "gcc_pcie_1_aux_clk",
3960			.parent_hws = (const struct clk_hw*[]) {
3961				&gcc_pcie_1_aux_clk_src.clkr.hw,
3962			},
3963			.num_parents = 1,
3964			.flags = CLK_SET_RATE_PARENT,
3965			.ops = &clk_branch2_ops,
3966		},
3967	},
3968};
3969
3970static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
3971	.halt_reg = 0xba480,
3972	.halt_check = BRANCH_HALT_VOTED,
3973	.hwcg_reg = 0xba480,
3974	.hwcg_bit = 1,
3975	.clkr = {
3976		.enable_reg = 0x62010,
3977		.enable_mask = BIT(17),
3978		.hw.init = &(const struct clk_init_data) {
3979			.name = "gcc_pcie_1_cfg_ahb_clk",
3980			.ops = &clk_branch2_ops,
3981		},
3982	},
3983};
3984
3985static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
3986	.halt_reg = 0xba470,
3987	.halt_check = BRANCH_HALT_SKIP,
3988	.hwcg_reg = 0xba470,
3989	.hwcg_bit = 1,
3990	.clkr = {
3991		.enable_reg = 0x62010,
3992		.enable_mask = BIT(16),
3993		.hw.init = &(const struct clk_init_data) {
3994			.name = "gcc_pcie_1_mstr_axi_clk",
3995			.ops = &clk_branch2_ops,
3996		},
3997	},
3998};
3999
4000static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
4001	.halt_reg = 0x2e038,
4002	.halt_check = BRANCH_HALT_VOTED,
4003	.clkr = {
4004		.enable_reg = 0x62010,
4005		.enable_mask = BIT(20),
4006		.hw.init = &(const struct clk_init_data) {
4007			.name = "gcc_pcie_1_phy_rchng_clk",
4008			.parent_hws = (const struct clk_hw*[]) {
4009				&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
4010			},
4011			.num_parents = 1,
4012			.flags = CLK_SET_RATE_PARENT,
4013			.ops = &clk_branch2_ops,
4014		},
4015	},
4016};
4017
4018static struct clk_branch gcc_pcie_1_pipe_clk = {
4019	.halt_reg = 0x2e028,
4020	.halt_check = BRANCH_HALT_SKIP,
4021	.clkr = {
4022		.enable_reg = 0x62010,
4023		.enable_mask = BIT(19),
4024		.hw.init = &(const struct clk_init_data) {
4025			.name = "gcc_pcie_1_pipe_clk",
4026			.parent_hws = (const struct clk_hw*[]) {
4027				&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
4028			},
4029			.num_parents = 1,
4030			.flags = CLK_SET_RATE_PARENT,
4031			.ops = &clk_branch2_ops,
4032		},
4033	},
4034};
4035
4036static struct clk_branch gcc_pcie_1_slv_axi_clk = {
4037	.halt_reg = 0xba460,
4038	.halt_check = BRANCH_HALT_VOTED,
4039	.hwcg_reg = 0xba460,
4040	.hwcg_bit = 1,
4041	.clkr = {
4042		.enable_reg = 0x62010,
4043		.enable_mask = BIT(15),
4044		.hw.init = &(const struct clk_init_data) {
4045			.name = "gcc_pcie_1_slv_axi_clk",
4046			.ops = &clk_branch2_ops,
4047		},
4048	},
4049};
4050
4051static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
4052	.halt_reg = 0xba45c,
4053	.halt_check = BRANCH_HALT_VOTED,
4054	.clkr = {
4055		.enable_reg = 0x62010,
4056		.enable_mask = BIT(14),
4057		.hw.init = &(const struct clk_init_data) {
4058			.name = "gcc_pcie_1_slv_q2a_axi_clk",
4059			.ops = &clk_branch2_ops,
4060		},
4061	},
4062};
4063
4064static struct clk_branch gcc_pcie_2_aux_clk = {
4065	.halt_reg = 0xc0018,
4066	.halt_check = BRANCH_HALT_VOTED,
4067	.clkr = {
4068		.enable_reg = 0x62018,
4069		.enable_mask = BIT(0),
4070		.hw.init = &(const struct clk_init_data) {
4071			.name = "gcc_pcie_2_aux_clk",
4072			.parent_hws = (const struct clk_hw*[]) {
4073				&gcc_pcie_2_aux_clk_src.clkr.hw,
4074			},
4075			.num_parents = 1,
4076			.flags = CLK_SET_RATE_PARENT,
4077			.ops = &clk_branch2_ops,
4078		},
4079	},
4080};
4081
4082static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
4083	.halt_reg = 0xba4d0,
4084	.halt_check = BRANCH_HALT_VOTED,
4085	.hwcg_reg = 0xba4d0,
4086	.hwcg_bit = 1,
4087	.clkr = {
4088		.enable_reg = 0x62010,
4089		.enable_mask = BIT(31),
4090		.hw.init = &(const struct clk_init_data) {
4091			.name = "gcc_pcie_2_cfg_ahb_clk",
4092			.ops = &clk_branch2_ops,
4093		},
4094	},
4095};
4096
4097static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
4098	.halt_reg = 0xba4c0,
4099	.halt_check = BRANCH_HALT_SKIP,
4100	.hwcg_reg = 0xba4c0,
4101	.hwcg_bit = 1,
4102	.clkr = {
4103		.enable_reg = 0x62010,
4104		.enable_mask = BIT(30),
4105		.hw.init = &(const struct clk_init_data) {
4106			.name = "gcc_pcie_2_mstr_axi_clk",
4107			.ops = &clk_branch2_ops,
4108		},
4109	},
4110};
4111
4112static struct clk_branch gcc_pcie_2_phy_rchng_clk = {
4113	.halt_reg = 0xc0038,
4114	.halt_check = BRANCH_HALT_VOTED,
4115	.clkr = {
4116		.enable_reg = 0x62018,
4117		.enable_mask = BIT(2),
4118		.hw.init = &(const struct clk_init_data) {
4119			.name = "gcc_pcie_2_phy_rchng_clk",
4120			.parent_hws = (const struct clk_hw*[]) {
4121				&gcc_pcie_2_phy_rchng_clk_src.clkr.hw,
4122			},
4123			.num_parents = 1,
4124			.flags = CLK_SET_RATE_PARENT,
4125			.ops = &clk_branch2_ops,
4126		},
4127	},
4128};
4129
4130static struct clk_branch gcc_pcie_2_pipe_clk = {
4131	.halt_reg = 0xc0028,
4132	.halt_check = BRANCH_HALT_SKIP,
4133	.clkr = {
4134		.enable_reg = 0x62018,
4135		.enable_mask = BIT(1),
4136		.hw.init = &(const struct clk_init_data) {
4137			.name = "gcc_pcie_2_pipe_clk",
4138			.parent_hws = (const struct clk_hw*[]) {
4139				&gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
4140			},
4141			.num_parents = 1,
4142			.flags = CLK_SET_RATE_PARENT,
4143			.ops = &clk_branch2_ops,
4144		},
4145	},
4146};
4147
4148static struct clk_branch gcc_pcie_2_slv_axi_clk = {
4149	.halt_reg = 0xba4b0,
4150	.halt_check = BRANCH_HALT_VOTED,
4151	.hwcg_reg = 0xba4b0,
4152	.hwcg_bit = 1,
4153	.clkr = {
4154		.enable_reg = 0x62010,
4155		.enable_mask = BIT(29),
4156		.hw.init = &(const struct clk_init_data) {
4157			.name = "gcc_pcie_2_slv_axi_clk",
4158			.ops = &clk_branch2_ops,
4159		},
4160	},
4161};
4162
4163static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
4164	.halt_reg = 0xba4ac,
4165	.halt_check = BRANCH_HALT_VOTED,
4166	.clkr = {
4167		.enable_reg = 0x62010,
4168		.enable_mask = BIT(28),
4169		.hw.init = &(const struct clk_init_data) {
4170			.name = "gcc_pcie_2_slv_q2a_axi_clk",
4171			.ops = &clk_branch2_ops,
4172		},
4173	},
4174};
4175
4176static struct clk_branch gcc_pcie_3a_aux_clk = {
4177	.halt_reg = 0xdc04c,
4178	.halt_check = BRANCH_HALT_VOTED,
4179	.hwcg_reg = 0xdc04c,
4180	.hwcg_bit = 1,
4181	.clkr = {
4182		.enable_reg = 0x62028,
4183		.enable_mask = BIT(16),
4184		.hw.init = &(const struct clk_init_data) {
4185			.name = "gcc_pcie_3a_aux_clk",
4186			.parent_hws = (const struct clk_hw*[]) {
4187				&gcc_pcie_3a_aux_clk_src.clkr.hw,
4188			},
4189			.num_parents = 1,
4190			.flags = CLK_SET_RATE_PARENT,
4191			.ops = &clk_branch2_ops,
4192		},
4193	},
4194};
4195
4196static struct clk_branch gcc_pcie_3a_cfg_ahb_clk = {
4197	.halt_reg = 0xba4f0,
4198	.halt_check = BRANCH_HALT_VOTED,
4199	.hwcg_reg = 0xba4f0,
4200	.hwcg_bit = 1,
4201	.clkr = {
4202		.enable_reg = 0x62028,
4203		.enable_mask = BIT(15),
4204		.hw.init = &(const struct clk_init_data) {
4205			.name = "gcc_pcie_3a_cfg_ahb_clk",
4206			.ops = &clk_branch2_ops,
4207		},
4208	},
4209};
4210
4211static struct clk_branch gcc_pcie_3a_mstr_axi_clk = {
4212	.halt_reg = 0xdc038,
4213	.halt_check = BRANCH_HALT_SKIP,
4214	.hwcg_reg = 0xdc038,
4215	.hwcg_bit = 1,
4216	.clkr = {
4217		.enable_reg = 0x62028,
4218		.enable_mask = BIT(14),
4219		.hw.init = &(const struct clk_init_data) {
4220			.name = "gcc_pcie_3a_mstr_axi_clk",
4221			.ops = &clk_branch2_ops,
4222		},
4223	},
4224};
4225
4226static struct clk_branch gcc_pcie_3a_phy_rchng_clk = {
4227	.halt_reg = 0xdc06c,
4228	.halt_check = BRANCH_HALT_VOTED,
4229	.hwcg_reg = 0xdc06c,
4230	.hwcg_bit = 1,
4231	.clkr = {
4232		.enable_reg = 0x62028,
4233		.enable_mask = BIT(18),
4234		.hw.init = &(const struct clk_init_data) {
4235			.name = "gcc_pcie_3a_phy_rchng_clk",
4236			.parent_hws = (const struct clk_hw*[]) {
4237				&gcc_pcie_3a_phy_rchng_clk_src.clkr.hw,
4238			},
4239			.num_parents = 1,
4240			.flags = CLK_SET_RATE_PARENT,
4241			.ops = &clk_branch2_ops,
4242		},
4243	},
4244};
4245
4246static struct clk_branch gcc_pcie_3a_pipe_clk = {
4247	.halt_reg = 0xdc05c,
4248	.halt_check = BRANCH_HALT_SKIP,
4249	.hwcg_reg = 0xdc05c,
4250	.hwcg_bit = 1,
4251	.clkr = {
4252		.enable_reg = 0x62028,
4253		.enable_mask = BIT(17),
4254		.hw.init = &(const struct clk_init_data) {
4255			.name = "gcc_pcie_3a_pipe_clk",
4256			.parent_hws = (const struct clk_hw*[]) {
4257				&gcc_pcie_3a_pipe_clk_src.clkr.hw,
4258			},
4259			.num_parents = 1,
4260			.flags = CLK_SET_RATE_PARENT,
4261			.ops = &clk_branch2_ops,
4262		},
4263	},
4264};
4265
4266static struct clk_branch gcc_pcie_3a_slv_axi_clk = {
4267	.halt_reg = 0xdc024,
4268	.halt_check = BRANCH_HALT_VOTED,
4269	.hwcg_reg = 0xdc024,
4270	.hwcg_bit = 1,
4271	.clkr = {
4272		.enable_reg = 0x62028,
4273		.enable_mask = BIT(13),
4274		.hw.init = &(const struct clk_init_data) {
4275			.name = "gcc_pcie_3a_slv_axi_clk",
4276			.ops = &clk_branch2_ops,
4277		},
4278	},
4279};
4280
4281static struct clk_branch gcc_pcie_3a_slv_q2a_axi_clk = {
4282	.halt_reg = 0xdc01c,
4283	.halt_check = BRANCH_HALT_VOTED,
4284	.hwcg_reg = 0xdc01c,
4285	.hwcg_bit = 1,
4286	.clkr = {
4287		.enable_reg = 0x62028,
4288		.enable_mask = BIT(12),
4289		.hw.init = &(const struct clk_init_data) {
4290			.name = "gcc_pcie_3a_slv_q2a_axi_clk",
4291			.ops = &clk_branch2_ops,
4292		},
4293	},
4294};
4295
4296static struct clk_branch gcc_pcie_3b_aux_clk = {
4297	.halt_reg = 0x94050,
4298	.halt_check = BRANCH_HALT_VOTED,
4299	.clkr = {
4300		.enable_reg = 0x62028,
4301		.enable_mask = BIT(25),
4302		.hw.init = &(const struct clk_init_data) {
4303			.name = "gcc_pcie_3b_aux_clk",
4304			.parent_hws = (const struct clk_hw*[]) {
4305				&gcc_pcie_3b_aux_clk_src.clkr.hw,
4306			},
4307			.num_parents = 1,
4308			.flags = CLK_SET_RATE_PARENT,
4309			.ops = &clk_branch2_ops,
4310		},
4311	},
4312};
4313
4314static struct clk_branch gcc_pcie_3b_cfg_ahb_clk = {
4315	.halt_reg = 0xba4f4,
4316	.halt_check = BRANCH_HALT_VOTED,
4317	.hwcg_reg = 0xba4f4,
4318	.hwcg_bit = 1,
4319	.clkr = {
4320		.enable_reg = 0x62028,
4321		.enable_mask = BIT(24),
4322		.hw.init = &(const struct clk_init_data) {
4323			.name = "gcc_pcie_3b_cfg_ahb_clk",
4324			.ops = &clk_branch2_ops,
4325		},
4326	},
4327};
4328
4329static struct clk_branch gcc_pcie_3b_mstr_axi_clk = {
4330	.halt_reg = 0x94038,
4331	.halt_check = BRANCH_HALT_SKIP,
4332	.hwcg_reg = 0x94038,
4333	.hwcg_bit = 1,
4334	.clkr = {
4335		.enable_reg = 0x62028,
4336		.enable_mask = BIT(23),
4337		.hw.init = &(const struct clk_init_data) {
4338			.name = "gcc_pcie_3b_mstr_axi_clk",
4339			.ops = &clk_branch2_ops,
4340		},
4341	},
4342};
4343
4344static struct clk_branch gcc_pcie_3b_phy_rchng_clk = {
4345	.halt_reg = 0x94084,
4346	.halt_check = BRANCH_HALT_VOTED,
4347	.clkr = {
4348		.enable_reg = 0x62028,
4349		.enable_mask = BIT(28),
4350		.hw.init = &(const struct clk_init_data) {
4351			.name = "gcc_pcie_3b_phy_rchng_clk",
4352			.parent_hws = (const struct clk_hw*[]) {
4353				&gcc_pcie_3b_phy_rchng_clk_src.clkr.hw,
4354			},
4355			.num_parents = 1,
4356			.flags = CLK_SET_RATE_PARENT,
4357			.ops = &clk_branch2_ops,
4358		},
4359	},
4360};
4361
4362static struct clk_branch gcc_pcie_3b_pipe_clk = {
4363	.halt_reg = 0x94060,
4364	.halt_check = BRANCH_HALT_SKIP,
4365	.clkr = {
4366		.enable_reg = 0x62028,
4367		.enable_mask = BIT(26),
4368		.hw.init = &(const struct clk_init_data) {
4369			.name = "gcc_pcie_3b_pipe_clk",
4370			.parent_hws = (const struct clk_hw*[]) {
4371				&gcc_pcie_3b_pipe_clk_src.clkr.hw,
4372			},
4373			.num_parents = 1,
4374			.flags = CLK_SET_RATE_PARENT,
4375			.ops = &clk_branch2_ops,
4376		},
4377	},
4378};
4379
4380static struct clk_branch gcc_pcie_3b_pipe_div2_clk = {
4381	.halt_reg = 0x94074,
4382	.halt_check = BRANCH_HALT_SKIP,
4383	.clkr = {
4384		.enable_reg = 0x62028,
4385		.enable_mask = BIT(27),
4386		.hw.init = &(const struct clk_init_data) {
4387			.name = "gcc_pcie_3b_pipe_div2_clk",
4388			.parent_hws = (const struct clk_hw*[]) {
4389				&gcc_pcie_3b_pipe_div_clk_src.clkr.hw,
4390			},
4391			.num_parents = 1,
4392			.flags = CLK_SET_RATE_PARENT,
4393			.ops = &clk_branch2_ops,
4394		},
4395	},
4396};
4397
4398static struct clk_branch gcc_pcie_3b_slv_axi_clk = {
4399	.halt_reg = 0x94024,
4400	.halt_check = BRANCH_HALT_VOTED,
4401	.hwcg_reg = 0x94024,
4402	.hwcg_bit = 1,
4403	.clkr = {
4404		.enable_reg = 0x62028,
4405		.enable_mask = BIT(22),
4406		.hw.init = &(const struct clk_init_data) {
4407			.name = "gcc_pcie_3b_slv_axi_clk",
4408			.ops = &clk_branch2_ops,
4409		},
4410	},
4411};
4412
4413static struct clk_branch gcc_pcie_3b_slv_q2a_axi_clk = {
4414	.halt_reg = 0x9401c,
4415	.halt_check = BRANCH_HALT_VOTED,
4416	.clkr = {
4417		.enable_reg = 0x62028,
4418		.enable_mask = BIT(21),
4419		.hw.init = &(const struct clk_init_data) {
4420			.name = "gcc_pcie_3b_slv_q2a_axi_clk",
4421			.ops = &clk_branch2_ops,
4422		},
4423	},
4424};
4425
4426static struct clk_branch gcc_pcie_4_aux_clk = {
4427	.halt_reg = 0x88040,
4428	.halt_check = BRANCH_HALT_VOTED,
4429	.clkr = {
4430		.enable_reg = 0x62030,
4431		.enable_mask = BIT(17),
4432		.hw.init = &(const struct clk_init_data) {
4433			.name = "gcc_pcie_4_aux_clk",
4434			.parent_hws = (const struct clk_hw*[]) {
4435				&gcc_pcie_4_aux_clk_src.clkr.hw,
4436			},
4437			.num_parents = 1,
4438			.flags = CLK_SET_RATE_PARENT,
4439			.ops = &clk_branch2_ops,
4440		},
4441	},
4442};
4443
4444static struct clk_branch gcc_pcie_4_cfg_ahb_clk = {
4445	.halt_reg = 0xba4fc,
4446	.halt_check = BRANCH_HALT_VOTED,
4447	.hwcg_reg = 0xba4fc,
4448	.hwcg_bit = 1,
4449	.clkr = {
4450		.enable_reg = 0x62030,
4451		.enable_mask = BIT(16),
4452		.hw.init = &(const struct clk_init_data) {
4453			.name = "gcc_pcie_4_cfg_ahb_clk",
4454			.ops = &clk_branch2_ops,
4455		},
4456	},
4457};
4458
4459static struct clk_branch gcc_pcie_4_mstr_axi_clk = {
4460	.halt_reg = 0x88030,
4461	.halt_check = BRANCH_HALT_SKIP,
4462	.hwcg_reg = 0x88030,
4463	.hwcg_bit = 1,
4464	.clkr = {
4465		.enable_reg = 0x62030,
4466		.enable_mask = BIT(15),
4467		.hw.init = &(const struct clk_init_data) {
4468			.name = "gcc_pcie_4_mstr_axi_clk",
4469			.ops = &clk_branch2_ops,
4470		},
4471	},
4472};
4473
4474static struct clk_branch gcc_pcie_4_phy_rchng_clk = {
4475	.halt_reg = 0x88074,
4476	.halt_check = BRANCH_HALT_VOTED,
4477	.clkr = {
4478		.enable_reg = 0x62030,
4479		.enable_mask = BIT(20),
4480		.hw.init = &(const struct clk_init_data) {
4481			.name = "gcc_pcie_4_phy_rchng_clk",
4482			.parent_hws = (const struct clk_hw*[]) {
4483				&gcc_pcie_4_phy_rchng_clk_src.clkr.hw,
4484			},
4485			.num_parents = 1,
4486			.flags = CLK_SET_RATE_PARENT,
4487			.ops = &clk_branch2_ops,
4488		},
4489	},
4490};
4491
4492static struct clk_branch gcc_pcie_4_pipe_clk = {
4493	.halt_reg = 0x88050,
4494	.halt_check = BRANCH_HALT_SKIP,
4495	.clkr = {
4496		.enable_reg = 0x62030,
4497		.enable_mask = BIT(18),
4498		.hw.init = &(const struct clk_init_data) {
4499			.name = "gcc_pcie_4_pipe_clk",
4500			.parent_hws = (const struct clk_hw*[]) {
4501				&gcc_pcie_4_pipe_clk_src.clkr.hw,
4502			},
4503			.num_parents = 1,
4504			.flags = CLK_SET_RATE_PARENT,
4505			.ops = &clk_branch2_ops,
4506		},
4507	},
4508};
4509
4510static struct clk_branch gcc_pcie_4_pipe_div2_clk = {
4511	.halt_reg = 0x88064,
4512	.halt_check = BRANCH_HALT_SKIP,
4513	.clkr = {
4514		.enable_reg = 0x62030,
4515		.enable_mask = BIT(19),
4516		.hw.init = &(const struct clk_init_data) {
4517			.name = "gcc_pcie_4_pipe_div2_clk",
4518			.parent_hws = (const struct clk_hw*[]) {
4519				&gcc_pcie_4_pipe_div_clk_src.clkr.hw,
4520			},
4521			.num_parents = 1,
4522			.flags = CLK_SET_RATE_PARENT,
4523			.ops = &clk_branch2_ops,
4524		},
4525	},
4526};
4527
4528static struct clk_branch gcc_pcie_4_slv_axi_clk = {
4529	.halt_reg = 0x88020,
4530	.halt_check = BRANCH_HALT_VOTED,
4531	.hwcg_reg = 0x88020,
4532	.hwcg_bit = 1,
4533	.clkr = {
4534		.enable_reg = 0x62030,
4535		.enable_mask = BIT(14),
4536		.hw.init = &(const struct clk_init_data) {
4537			.name = "gcc_pcie_4_slv_axi_clk",
4538			.ops = &clk_branch2_ops,
4539		},
4540	},
4541};
4542
4543static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = {
4544	.halt_reg = 0x8801c,
4545	.halt_check = BRANCH_HALT_VOTED,
4546	.clkr = {
4547		.enable_reg = 0x62030,
4548		.enable_mask = BIT(13),
4549		.hw.init = &(const struct clk_init_data) {
4550			.name = "gcc_pcie_4_slv_q2a_axi_clk",
4551			.ops = &clk_branch2_ops,
4552		},
4553	},
4554};
4555
4556static struct clk_branch gcc_pcie_5_aux_clk = {
4557	.halt_reg = 0xc304c,
4558	.halt_check = BRANCH_HALT_VOTED,
4559	.clkr = {
4560		.enable_reg = 0x62030,
4561		.enable_mask = BIT(5),
4562		.hw.init = &(const struct clk_init_data) {
4563			.name = "gcc_pcie_5_aux_clk",
4564			.parent_hws = (const struct clk_hw*[]) {
4565				&gcc_pcie_5_aux_clk_src.clkr.hw,
4566			},
4567			.num_parents = 1,
4568			.flags = CLK_SET_RATE_PARENT,
4569			.ops = &clk_branch2_ops,
4570		},
4571	},
4572};
4573
4574static struct clk_branch gcc_pcie_5_cfg_ahb_clk = {
4575	.halt_reg = 0xba4f8,
4576	.halt_check = BRANCH_HALT_VOTED,
4577	.hwcg_reg = 0xba4f8,
4578	.hwcg_bit = 1,
4579	.clkr = {
4580		.enable_reg = 0x62030,
4581		.enable_mask = BIT(4),
4582		.hw.init = &(const struct clk_init_data) {
4583			.name = "gcc_pcie_5_cfg_ahb_clk",
4584			.ops = &clk_branch2_ops,
4585		},
4586	},
4587};
4588
4589static struct clk_branch gcc_pcie_5_mstr_axi_clk = {
4590	.halt_reg = 0xc3038,
4591	.halt_check = BRANCH_HALT_SKIP,
4592	.hwcg_reg = 0xc3038,
4593	.hwcg_bit = 1,
4594	.clkr = {
4595		.enable_reg = 0x62030,
4596		.enable_mask = BIT(3),
4597		.hw.init = &(const struct clk_init_data) {
4598			.name = "gcc_pcie_5_mstr_axi_clk",
4599			.ops = &clk_branch2_ops,
4600		},
4601	},
4602};
4603
4604static struct clk_branch gcc_pcie_5_phy_rchng_clk = {
4605	.halt_reg = 0xc3080,
4606	.halt_check = BRANCH_HALT_VOTED,
4607	.clkr = {
4608		.enable_reg = 0x62030,
4609		.enable_mask = BIT(8),
4610		.hw.init = &(const struct clk_init_data) {
4611			.name = "gcc_pcie_5_phy_rchng_clk",
4612			.parent_hws = (const struct clk_hw*[]) {
4613				&gcc_pcie_5_phy_rchng_clk_src.clkr.hw,
4614			},
4615			.num_parents = 1,
4616			.flags = CLK_SET_RATE_PARENT,
4617			.ops = &clk_branch2_ops,
4618		},
4619	},
4620};
4621
4622static struct clk_branch gcc_pcie_5_pipe_clk = {
4623	.halt_reg = 0xc305c,
4624	.halt_check = BRANCH_HALT_SKIP,
4625	.clkr = {
4626		.enable_reg = 0x62030,
4627		.enable_mask = BIT(6),
4628		.hw.init = &(const struct clk_init_data) {
4629			.name = "gcc_pcie_5_pipe_clk",
4630			.parent_hws = (const struct clk_hw*[]) {
4631				&gcc_pcie_5_pipe_clk_src.clkr.hw,
4632			},
4633			.num_parents = 1,
4634			.flags = CLK_SET_RATE_PARENT,
4635			.ops = &clk_branch2_ops,
4636		},
4637	},
4638};
4639
4640static struct clk_branch gcc_pcie_5_pipe_div2_clk = {
4641	.halt_reg = 0xc3070,
4642	.halt_check = BRANCH_HALT_SKIP,
4643	.clkr = {
4644		.enable_reg = 0x62030,
4645		.enable_mask = BIT(7),
4646		.hw.init = &(const struct clk_init_data) {
4647			.name = "gcc_pcie_5_pipe_div2_clk",
4648			.parent_hws = (const struct clk_hw*[]) {
4649				&gcc_pcie_5_pipe_div_clk_src.clkr.hw,
4650			},
4651			.num_parents = 1,
4652			.flags = CLK_SET_RATE_PARENT,
4653			.ops = &clk_branch2_ops,
4654		},
4655	},
4656};
4657
4658static struct clk_branch gcc_pcie_5_slv_axi_clk = {
4659	.halt_reg = 0xc3024,
4660	.halt_check = BRANCH_HALT_VOTED,
4661	.hwcg_reg = 0xc3024,
4662	.hwcg_bit = 1,
4663	.clkr = {
4664		.enable_reg = 0x62030,
4665		.enable_mask = BIT(2),
4666		.hw.init = &(const struct clk_init_data) {
4667			.name = "gcc_pcie_5_slv_axi_clk",
4668			.ops = &clk_branch2_ops,
4669		},
4670	},
4671};
4672
4673static struct clk_branch gcc_pcie_5_slv_q2a_axi_clk = {
4674	.halt_reg = 0xc301c,
4675	.halt_check = BRANCH_HALT_VOTED,
4676	.clkr = {
4677		.enable_reg = 0x62030,
4678		.enable_mask = BIT(1),
4679		.hw.init = &(const struct clk_init_data) {
4680			.name = "gcc_pcie_5_slv_q2a_axi_clk",
4681			.ops = &clk_branch2_ops,
4682		},
4683	},
4684};
4685
4686static struct clk_branch gcc_pcie_6_aux_clk = {
4687	.halt_reg = 0x8a040,
4688	.halt_check = BRANCH_HALT_VOTED,
4689	.clkr = {
4690		.enable_reg = 0x62030,
4691		.enable_mask = BIT(27),
4692		.hw.init = &(const struct clk_init_data) {
4693			.name = "gcc_pcie_6_aux_clk",
4694			.parent_hws = (const struct clk_hw*[]) {
4695				&gcc_pcie_6_aux_clk_src.clkr.hw,
4696			},
4697			.num_parents = 1,
4698			.flags = CLK_SET_RATE_PARENT,
4699			.ops = &clk_branch2_ops,
4700		},
4701	},
4702};
4703
4704static struct clk_branch gcc_pcie_6_cfg_ahb_clk = {
4705	.halt_reg = 0xba500,
4706	.halt_check = BRANCH_HALT_VOTED,
4707	.hwcg_reg = 0xba500,
4708	.hwcg_bit = 1,
4709	.clkr = {
4710		.enable_reg = 0x62030,
4711		.enable_mask = BIT(26),
4712		.hw.init = &(const struct clk_init_data) {
4713			.name = "gcc_pcie_6_cfg_ahb_clk",
4714			.ops = &clk_branch2_ops,
4715		},
4716	},
4717};
4718
4719static struct clk_branch gcc_pcie_6_mstr_axi_clk = {
4720	.halt_reg = 0x8a030,
4721	.halt_check = BRANCH_HALT_SKIP,
4722	.hwcg_reg = 0x8a030,
4723	.hwcg_bit = 1,
4724	.clkr = {
4725		.enable_reg = 0x62030,
4726		.enable_mask = BIT(25),
4727		.hw.init = &(const struct clk_init_data) {
4728			.name = "gcc_pcie_6_mstr_axi_clk",
4729			.ops = &clk_branch2_ops,
4730		},
4731	},
4732};
4733
4734static struct clk_branch gcc_pcie_6_phy_rchng_clk = {
4735	.halt_reg = 0x8a074,
4736	.halt_check = BRANCH_HALT_VOTED,
4737	.clkr = {
4738		.enable_reg = 0x62030,
4739		.enable_mask = BIT(30),
4740		.hw.init = &(const struct clk_init_data) {
4741			.name = "gcc_pcie_6_phy_rchng_clk",
4742			.parent_hws = (const struct clk_hw*[]) {
4743				&gcc_pcie_6_phy_rchng_clk_src.clkr.hw,
4744			},
4745			.num_parents = 1,
4746			.flags = CLK_SET_RATE_PARENT,
4747			.ops = &clk_branch2_ops,
4748		},
4749	},
4750};
4751
4752static struct clk_branch gcc_pcie_6_pipe_clk = {
4753	.halt_reg = 0x8a050,
4754	.halt_check = BRANCH_HALT_SKIP,
4755	.clkr = {
4756		.enable_reg = 0x62030,
4757		.enable_mask = BIT(28),
4758		.hw.init = &(const struct clk_init_data) {
4759			.name = "gcc_pcie_6_pipe_clk",
4760			.parent_hws = (const struct clk_hw*[]) {
4761				&gcc_pcie_6_pipe_clk_src.clkr.hw,
4762			},
4763			.num_parents = 1,
4764			.flags = CLK_SET_RATE_PARENT,
4765			.ops = &clk_branch2_ops,
4766		},
4767	},
4768};
4769
4770static struct clk_branch gcc_pcie_6_pipe_div2_clk = {
4771	.halt_reg = 0x8a064,
4772	.halt_check = BRANCH_HALT_SKIP,
4773	.clkr = {
4774		.enable_reg = 0x62030,
4775		.enable_mask = BIT(29),
4776		.hw.init = &(const struct clk_init_data) {
4777			.name = "gcc_pcie_6_pipe_div2_clk",
4778			.parent_hws = (const struct clk_hw*[]) {
4779				&gcc_pcie_6_pipe_div_clk_src.clkr.hw,
4780			},
4781			.num_parents = 1,
4782			.flags = CLK_SET_RATE_PARENT,
4783			.ops = &clk_branch2_ops,
4784		},
4785	},
4786};
4787
4788static struct clk_branch gcc_pcie_6_slv_axi_clk = {
4789	.halt_reg = 0x8a020,
4790	.halt_check = BRANCH_HALT_VOTED,
4791	.hwcg_reg = 0x8a020,
4792	.hwcg_bit = 1,
4793	.clkr = {
4794		.enable_reg = 0x62030,
4795		.enable_mask = BIT(24),
4796		.hw.init = &(const struct clk_init_data) {
4797			.name = "gcc_pcie_6_slv_axi_clk",
4798			.ops = &clk_branch2_ops,
4799		},
4800	},
4801};
4802
4803static struct clk_branch gcc_pcie_6_slv_q2a_axi_clk = {
4804	.halt_reg = 0x8a01c,
4805	.halt_check = BRANCH_HALT_VOTED,
4806	.clkr = {
4807		.enable_reg = 0x62030,
4808		.enable_mask = BIT(23),
4809		.hw.init = &(const struct clk_init_data) {
4810			.name = "gcc_pcie_6_slv_q2a_axi_clk",
4811			.ops = &clk_branch2_ops,
4812		},
4813	},
4814};
4815
4816static struct clk_branch gcc_pcie_noc_pwrctl_clk = {
4817	.halt_reg = 0xba2ac,
4818	.halt_check = BRANCH_HALT_VOTED,
4819	.clkr = {
4820		.enable_reg = 0x62008,
4821		.enable_mask = BIT(7),
4822		.hw.init = &(const struct clk_init_data) {
4823			.name = "gcc_pcie_noc_pwrctl_clk",
4824			.ops = &clk_branch2_ops,
4825		},
4826	},
4827};
4828
4829static struct clk_branch gcc_pcie_noc_qosgen_extref_clk = {
4830	.halt_reg = 0xba2a8,
4831	.halt_check = BRANCH_HALT_VOTED,
4832	.clkr = {
4833		.enable_reg = 0x62008,
4834		.enable_mask = BIT(6),
4835		.hw.init = &(const struct clk_init_data) {
4836			.name = "gcc_pcie_noc_qosgen_extref_clk",
4837			.ops = &clk_branch2_ops,
4838		},
4839	},
4840};
4841
4842static struct clk_branch gcc_pcie_noc_sf_center_clk = {
4843	.halt_reg = 0xba2b0,
4844	.halt_check = BRANCH_HALT_VOTED,
4845	.hwcg_reg = 0xba2b0,
4846	.hwcg_bit = 1,
4847	.clkr = {
4848		.enable_reg = 0x62008,
4849		.enable_mask = BIT(8),
4850		.hw.init = &(const struct clk_init_data) {
4851			.name = "gcc_pcie_noc_sf_center_clk",
4852			.ops = &clk_branch2_ops,
4853		},
4854	},
4855};
4856
4857static struct clk_branch gcc_pcie_noc_slave_sf_east_clk = {
4858	.halt_reg = 0xba2b8,
4859	.halt_check = BRANCH_HALT_VOTED,
4860	.hwcg_reg = 0xba2b8,
4861	.hwcg_bit = 1,
4862	.clkr = {
4863		.enable_reg = 0x62008,
4864		.enable_mask = BIT(9),
4865		.hw.init = &(const struct clk_init_data) {
4866			.name = "gcc_pcie_noc_slave_sf_east_clk",
4867			.ops = &clk_branch2_ops,
4868		},
4869	},
4870};
4871
4872static struct clk_branch gcc_pcie_noc_slave_sf_west_clk = {
4873	.halt_reg = 0xba2c0,
4874	.halt_check = BRANCH_HALT_VOTED,
4875	.hwcg_reg = 0xba2c0,
4876	.hwcg_bit = 1,
4877	.clkr = {
4878		.enable_reg = 0x62008,
4879		.enable_mask = BIT(10),
4880		.hw.init = &(const struct clk_init_data) {
4881			.name = "gcc_pcie_noc_slave_sf_west_clk",
4882			.ops = &clk_branch2_ops,
4883		},
4884	},
4885};
4886
4887static struct clk_branch gcc_pcie_noc_tsctr_clk = {
4888	.halt_reg = 0xba2a4,
4889	.halt_check = BRANCH_HALT_VOTED,
4890	.hwcg_reg = 0xba2a4,
4891	.hwcg_bit = 1,
4892	.clkr = {
4893		.enable_reg = 0x62008,
4894		.enable_mask = BIT(5),
4895		.hw.init = &(const struct clk_init_data) {
4896			.name = "gcc_pcie_noc_tsctr_clk",
4897			.ops = &clk_branch2_ops,
4898		},
4899	},
4900};
4901
4902static struct clk_branch gcc_pcie_phy_3a_aux_clk = {
4903	.halt_reg = 0x6c038,
4904	.halt_check = BRANCH_HALT_VOTED,
4905	.hwcg_reg = 0x6c038,
4906	.hwcg_bit = 1,
4907	.clkr = {
4908		.enable_reg = 0x62028,
4909		.enable_mask = BIT(19),
4910		.hw.init = &(const struct clk_init_data) {
4911			.name = "gcc_pcie_phy_3a_aux_clk",
4912			.parent_hws = (const struct clk_hw*[]) {
4913				&gcc_pcie_phy_3a_aux_clk_src.clkr.hw,
4914			},
4915			.num_parents = 1,
4916			.flags = CLK_SET_RATE_PARENT,
4917			.ops = &clk_branch2_ops,
4918		},
4919	},
4920};
4921
4922static struct clk_branch gcc_pcie_phy_3b_aux_clk = {
4923	.halt_reg = 0x75034,
4924	.halt_check = BRANCH_HALT_VOTED,
4925	.clkr = {
4926		.enable_reg = 0x62028,
4927		.enable_mask = BIT(31),
4928		.hw.init = &(const struct clk_init_data) {
4929			.name = "gcc_pcie_phy_3b_aux_clk",
4930			.parent_hws = (const struct clk_hw*[]) {
4931				&gcc_pcie_phy_3b_aux_clk_src.clkr.hw,
4932			},
4933			.num_parents = 1,
4934			.flags = CLK_SET_RATE_PARENT,
4935			.ops = &clk_branch2_ops,
4936		},
4937	},
4938};
4939
4940static struct clk_branch gcc_pcie_phy_4_aux_clk = {
4941	.halt_reg = 0xd3030,
4942	.halt_check = BRANCH_HALT_VOTED,
4943	.clkr = {
4944		.enable_reg = 0x62030,
4945		.enable_mask = BIT(21),
4946		.hw.init = &(const struct clk_init_data) {
4947			.name = "gcc_pcie_phy_4_aux_clk",
4948			.parent_hws = (const struct clk_hw*[]) {
4949				&gcc_pcie_phy_4_aux_clk_src.clkr.hw,
4950			},
4951			.num_parents = 1,
4952			.flags = CLK_SET_RATE_PARENT,
4953			.ops = &clk_branch2_ops,
4954		},
4955	},
4956};
4957
4958static struct clk_branch gcc_pcie_phy_5_aux_clk = {
4959	.halt_reg = 0xd2030,
4960	.halt_check = BRANCH_HALT_VOTED,
4961	.clkr = {
4962		.enable_reg = 0x62030,
4963		.enable_mask = BIT(11),
4964		.hw.init = &(const struct clk_init_data) {
4965			.name = "gcc_pcie_phy_5_aux_clk",
4966			.parent_hws = (const struct clk_hw*[]) {
4967				&gcc_pcie_phy_5_aux_clk_src.clkr.hw,
4968			},
4969			.num_parents = 1,
4970			.flags = CLK_SET_RATE_PARENT,
4971			.ops = &clk_branch2_ops,
4972		},
4973	},
4974};
4975
4976static struct clk_branch gcc_pcie_phy_6_aux_clk = {
4977	.halt_reg = 0xd4030,
4978	.halt_check = BRANCH_HALT_VOTED,
4979	.clkr = {
4980		.enable_reg = 0x62030,
4981		.enable_mask = BIT(31),
4982		.hw.init = &(const struct clk_init_data) {
4983			.name = "gcc_pcie_phy_6_aux_clk",
4984			.parent_hws = (const struct clk_hw*[]) {
4985				&gcc_pcie_phy_6_aux_clk_src.clkr.hw,
4986			},
4987			.num_parents = 1,
4988			.flags = CLK_SET_RATE_PARENT,
4989			.ops = &clk_branch2_ops,
4990		},
4991	},
4992};
4993
4994static struct clk_branch gcc_pcie_rscc_cfg_ahb_clk = {
4995	.halt_reg = 0xb8004,
4996	.halt_check = BRANCH_HALT_VOTED,
4997	.hwcg_reg = 0xb8004,
4998	.hwcg_bit = 1,
4999	.clkr = {
5000		.enable_reg = 0x62038,
5001		.enable_mask = BIT(2),
5002		.hw.init = &(const struct clk_init_data) {
5003			.name = "gcc_pcie_rscc_cfg_ahb_clk",
5004			.ops = &clk_branch2_ops,
5005		},
5006	},
5007};
5008
5009static struct clk_branch gcc_pcie_rscc_xo_clk = {
5010	.halt_reg = 0xb8008,
5011	.halt_check = BRANCH_HALT_VOTED,
5012	.clkr = {
5013		.enable_reg = 0x62038,
5014		.enable_mask = BIT(3),
5015		.hw.init = &(const struct clk_init_data) {
5016			.name = "gcc_pcie_rscc_xo_clk",
5017			.ops = &clk_branch2_ops,
5018		},
5019	},
5020};
5021
5022static struct clk_branch gcc_pdm2_clk = {
5023	.halt_reg = 0x3300c,
5024	.halt_check = BRANCH_HALT,
5025	.clkr = {
5026		.enable_reg = 0x3300c,
5027		.enable_mask = BIT(0),
5028		.hw.init = &(const struct clk_init_data) {
5029			.name = "gcc_pdm2_clk",
5030			.parent_hws = (const struct clk_hw*[]) {
5031				&gcc_pdm2_clk_src.clkr.hw,
5032			},
5033			.num_parents = 1,
5034			.flags = CLK_SET_RATE_PARENT,
5035			.ops = &clk_branch2_ops,
5036		},
5037	},
5038};
5039
5040static struct clk_branch gcc_pdm_ahb_clk = {
5041	.halt_reg = 0x33004,
5042	.halt_check = BRANCH_HALT_VOTED,
5043	.hwcg_reg = 0x33004,
5044	.hwcg_bit = 1,
5045	.clkr = {
5046		.enable_reg = 0x33004,
5047		.enable_mask = BIT(0),
5048		.hw.init = &(const struct clk_init_data) {
5049			.name = "gcc_pdm_ahb_clk",
5050			.ops = &clk_branch2_ops,
5051		},
5052	},
5053};
5054
5055static struct clk_branch gcc_pdm_xo4_clk = {
5056	.halt_reg = 0x33008,
5057	.halt_check = BRANCH_HALT,
5058	.clkr = {
5059		.enable_reg = 0x33008,
5060		.enable_mask = BIT(0),
5061		.hw.init = &(const struct clk_init_data) {
5062			.name = "gcc_pdm_xo4_clk",
5063			.ops = &clk_branch2_ops,
5064		},
5065	},
5066};
5067
5068static struct clk_branch gcc_qmip_av1e_ahb_clk = {
5069	.halt_reg = 0x9b048,
5070	.halt_check = BRANCH_HALT_VOTED,
5071	.hwcg_reg = 0x9b048,
5072	.hwcg_bit = 1,
5073	.clkr = {
5074		.enable_reg = 0x9b048,
5075		.enable_mask = BIT(0),
5076		.hw.init = &(const struct clk_init_data) {
5077			.name = "gcc_qmip_av1e_ahb_clk",
5078			.ops = &clk_branch2_ops,
5079		},
5080	},
5081};
5082
5083static struct clk_branch gcc_qmip_camera_cmd_ahb_clk = {
5084	.halt_reg = 0x26010,
5085	.halt_check = BRANCH_HALT_VOTED,
5086	.hwcg_reg = 0x26010,
5087	.hwcg_bit = 1,
5088	.clkr = {
5089		.enable_reg = 0x26010,
5090		.enable_mask = BIT(0),
5091		.hw.init = &(const struct clk_init_data) {
5092			.name = "gcc_qmip_camera_cmd_ahb_clk",
5093			.ops = &clk_branch2_ops,
5094		},
5095	},
5096};
5097
5098static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
5099	.halt_reg = 0x26008,
5100	.halt_check = BRANCH_HALT_VOTED,
5101	.hwcg_reg = 0x26008,
5102	.hwcg_bit = 1,
5103	.clkr = {
5104		.enable_reg = 0x26008,
5105		.enable_mask = BIT(0),
5106		.hw.init = &(const struct clk_init_data) {
5107			.name = "gcc_qmip_camera_nrt_ahb_clk",
5108			.ops = &clk_branch2_ops,
5109		},
5110	},
5111};
5112
5113static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
5114	.halt_reg = 0x2600c,
5115	.halt_check = BRANCH_HALT_VOTED,
5116	.hwcg_reg = 0x2600c,
5117	.hwcg_bit = 1,
5118	.clkr = {
5119		.enable_reg = 0x2600c,
5120		.enable_mask = BIT(0),
5121		.hw.init = &(const struct clk_init_data) {
5122			.name = "gcc_qmip_camera_rt_ahb_clk",
5123			.ops = &clk_branch2_ops,
5124		},
5125	},
5126};
5127
5128static struct clk_branch gcc_qmip_gpu_ahb_clk = {
5129	.halt_reg = 0x71008,
5130	.halt_check = BRANCH_HALT_VOTED,
5131	.hwcg_reg = 0x71008,
5132	.hwcg_bit = 1,
5133	.clkr = {
5134		.enable_reg = 0x71008,
5135		.enable_mask = BIT(0),
5136		.hw.init = &(const struct clk_init_data) {
5137			.name = "gcc_qmip_gpu_ahb_clk",
5138			.ops = &clk_branch2_ops,
5139		},
5140	},
5141};
5142
5143static struct clk_branch gcc_qmip_pcie_3a_ahb_clk = {
5144	.halt_reg = 0xdc018,
5145	.halt_check = BRANCH_HALT_VOTED,
5146	.hwcg_reg = 0xdc018,
5147	.hwcg_bit = 1,
5148	.clkr = {
5149		.enable_reg = 0x62028,
5150		.enable_mask = BIT(11),
5151		.hw.init = &(const struct clk_init_data) {
5152			.name = "gcc_qmip_pcie_3a_ahb_clk",
5153			.ops = &clk_branch2_ops,
5154		},
5155	},
5156};
5157
5158static struct clk_branch gcc_qmip_pcie_3b_ahb_clk = {
5159	.halt_reg = 0x94018,
5160	.halt_check = BRANCH_HALT_VOTED,
5161	.hwcg_reg = 0x94018,
5162	.hwcg_bit = 1,
5163	.clkr = {
5164		.enable_reg = 0x62028,
5165		.enable_mask = BIT(20),
5166		.hw.init = &(const struct clk_init_data) {
5167			.name = "gcc_qmip_pcie_3b_ahb_clk",
5168			.ops = &clk_branch2_ops,
5169		},
5170	},
5171};
5172
5173static struct clk_branch gcc_qmip_pcie_4_ahb_clk = {
5174	.halt_reg = 0x88018,
5175	.halt_check = BRANCH_HALT_VOTED,
5176	.hwcg_reg = 0x88018,
5177	.hwcg_bit = 1,
5178	.clkr = {
5179		.enable_reg = 0x62030,
5180		.enable_mask = BIT(12),
5181		.hw.init = &(const struct clk_init_data) {
5182			.name = "gcc_qmip_pcie_4_ahb_clk",
5183			.ops = &clk_branch2_ops,
5184		},
5185	},
5186};
5187
5188static struct clk_branch gcc_qmip_pcie_5_ahb_clk = {
5189	.halt_reg = 0xc3018,
5190	.halt_check = BRANCH_HALT_VOTED,
5191	.hwcg_reg = 0xc3018,
5192	.hwcg_bit = 1,
5193	.clkr = {
5194		.enable_reg = 0x62030,
5195		.enable_mask = BIT(0),
5196		.hw.init = &(const struct clk_init_data) {
5197			.name = "gcc_qmip_pcie_5_ahb_clk",
5198			.ops = &clk_branch2_ops,
5199		},
5200	},
5201};
5202
5203static struct clk_branch gcc_qmip_pcie_6_ahb_clk = {
5204	.halt_reg = 0x8a018,
5205	.halt_check = BRANCH_HALT_VOTED,
5206	.hwcg_reg = 0x8a018,
5207	.hwcg_bit = 1,
5208	.clkr = {
5209		.enable_reg = 0x62030,
5210		.enable_mask = BIT(22),
5211		.hw.init = &(const struct clk_init_data) {
5212			.name = "gcc_qmip_pcie_6_ahb_clk",
5213			.ops = &clk_branch2_ops,
5214		},
5215	},
5216};
5217
5218static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
5219	.halt_reg = 0x32018,
5220	.halt_check = BRANCH_HALT_VOTED,
5221	.hwcg_reg = 0x32018,
5222	.hwcg_bit = 1,
5223	.clkr = {
5224		.enable_reg = 0x32018,
5225		.enable_mask = BIT(0),
5226		.hw.init = &(const struct clk_init_data) {
5227			.name = "gcc_qmip_video_cv_cpu_ahb_clk",
5228			.ops = &clk_branch2_ops,
5229		},
5230	},
5231};
5232
5233static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
5234	.halt_reg = 0x32008,
5235	.halt_check = BRANCH_HALT_VOTED,
5236	.hwcg_reg = 0x32008,
5237	.hwcg_bit = 1,
5238	.clkr = {
5239		.enable_reg = 0x32008,
5240		.enable_mask = BIT(0),
5241		.hw.init = &(const struct clk_init_data) {
5242			.name = "gcc_qmip_video_cvp_ahb_clk",
5243			.ops = &clk_branch2_ops,
5244		},
5245	},
5246};
5247
5248static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
5249	.halt_reg = 0x32014,
5250	.halt_check = BRANCH_HALT_VOTED,
5251	.hwcg_reg = 0x32014,
5252	.hwcg_bit = 1,
5253	.clkr = {
5254		.enable_reg = 0x32014,
5255		.enable_mask = BIT(0),
5256		.hw.init = &(const struct clk_init_data) {
5257			.name = "gcc_qmip_video_v_cpu_ahb_clk",
5258			.ops = &clk_branch2_ops,
5259		},
5260	},
5261};
5262
5263static struct clk_branch gcc_qmip_video_vcodec1_ahb_clk = {
5264	.halt_reg = 0x32010,
5265	.halt_check = BRANCH_HALT_VOTED,
5266	.hwcg_reg = 0x32010,
5267	.hwcg_bit = 1,
5268	.clkr = {
5269		.enable_reg = 0x32010,
5270		.enable_mask = BIT(0),
5271		.hw.init = &(const struct clk_init_data) {
5272			.name = "gcc_qmip_video_vcodec1_ahb_clk",
5273			.ops = &clk_branch2_ops,
5274		},
5275	},
5276};
5277
5278static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
5279	.halt_reg = 0x3200c,
5280	.halt_check = BRANCH_HALT_VOTED,
5281	.hwcg_reg = 0x3200c,
5282	.hwcg_bit = 1,
5283	.clkr = {
5284		.enable_reg = 0x3200c,
5285		.enable_mask = BIT(0),
5286		.hw.init = &(const struct clk_init_data) {
5287			.name = "gcc_qmip_video_vcodec_ahb_clk",
5288			.ops = &clk_branch2_ops,
5289		},
5290	},
5291};
5292
5293static struct clk_branch gcc_qupv3_oob_core_2x_clk = {
5294	.halt_reg = 0xc5040,
5295	.halt_check = BRANCH_HALT_VOTED,
5296	.clkr = {
5297		.enable_reg = 0x62018,
5298		.enable_mask = BIT(5),
5299		.hw.init = &(const struct clk_init_data) {
5300			.name = "gcc_qupv3_oob_core_2x_clk",
5301			.ops = &clk_branch2_ops,
5302		},
5303	},
5304};
5305
5306static struct clk_branch gcc_qupv3_oob_core_clk = {
5307	.halt_reg = 0xc502c,
5308	.halt_check = BRANCH_HALT_VOTED,
5309	.clkr = {
5310		.enable_reg = 0x62018,
5311		.enable_mask = BIT(4),
5312		.hw.init = &(const struct clk_init_data) {
5313			.name = "gcc_qupv3_oob_core_clk",
5314			.ops = &clk_branch2_ops,
5315		},
5316	},
5317};
5318
5319static struct clk_branch gcc_qupv3_oob_m_ahb_clk = {
5320	.halt_reg = 0xe7004,
5321	.halt_check = BRANCH_HALT_VOTED,
5322	.hwcg_reg = 0xe7004,
5323	.hwcg_bit = 1,
5324	.clkr = {
5325		.enable_reg = 0xe7004,
5326		.enable_mask = BIT(0),
5327		.hw.init = &(const struct clk_init_data) {
5328			.name = "gcc_qupv3_oob_m_ahb_clk",
5329			.ops = &clk_branch2_ops,
5330		},
5331	},
5332};
5333
5334static struct clk_branch gcc_qupv3_oob_qspi_s0_clk = {
5335	.halt_reg = 0xe7040,
5336	.halt_check = BRANCH_HALT_VOTED,
5337	.clkr = {
5338		.enable_reg = 0x62018,
5339		.enable_mask = BIT(9),
5340		.hw.init = &(const struct clk_init_data) {
5341			.name = "gcc_qupv3_oob_qspi_s0_clk",
5342			.parent_hws = (const struct clk_hw*[]) {
5343				&gcc_qupv3_oob_qspi_s0_clk_src.clkr.hw,
5344			},
5345			.num_parents = 1,
5346			.flags = CLK_SET_RATE_PARENT,
5347			.ops = &clk_branch2_ops,
5348		},
5349	},
5350};
5351
5352static struct clk_branch gcc_qupv3_oob_qspi_s1_clk = {
5353	.halt_reg = 0xe729c,
5354	.halt_check = BRANCH_HALT_VOTED,
5355	.clkr = {
5356		.enable_reg = 0x62018,
5357		.enable_mask = BIT(10),
5358		.hw.init = &(const struct clk_init_data) {
5359			.name = "gcc_qupv3_oob_qspi_s1_clk",
5360			.parent_hws = (const struct clk_hw*[]) {
5361				&gcc_qupv3_oob_qspi_s1_clk_src.clkr.hw,
5362			},
5363			.num_parents = 1,
5364			.flags = CLK_SET_RATE_PARENT,
5365			.ops = &clk_branch2_ops,
5366		},
5367	},
5368};
5369
5370static struct clk_branch gcc_qupv3_oob_s0_clk = {
5371	.halt_reg = 0xe7014,
5372	.halt_check = BRANCH_HALT_VOTED,
5373	.clkr = {
5374		.enable_reg = 0x62018,
5375		.enable_mask = BIT(6),
5376		.hw.init = &(const struct clk_init_data) {
5377			.name = "gcc_qupv3_oob_s0_clk",
5378			.parent_hws = (const struct clk_hw*[]) {
5379				&gcc_qupv3_oob_s0_clk_src.clkr.hw,
5380			},
5381			.num_parents = 1,
5382			.flags = CLK_SET_RATE_PARENT,
5383			.ops = &clk_branch2_ops,
5384		},
5385	},
5386};
5387
5388static struct clk_branch gcc_qupv3_oob_s1_clk = {
5389	.halt_reg = 0xe7028,
5390	.halt_check = BRANCH_HALT_VOTED,
5391	.clkr = {
5392		.enable_reg = 0x62018,
5393		.enable_mask = BIT(7),
5394		.hw.init = &(const struct clk_init_data) {
5395			.name = "gcc_qupv3_oob_s1_clk",
5396			.parent_hws = (const struct clk_hw*[]) {
5397				&gcc_qupv3_oob_s1_clk_src.clkr.hw,
5398			},
5399			.num_parents = 1,
5400			.flags = CLK_SET_RATE_PARENT,
5401			.ops = &clk_branch2_ops,
5402		},
5403	},
5404};
5405
5406static struct clk_branch gcc_qupv3_oob_s_ahb_clk = {
5407	.halt_reg = 0xc5028,
5408	.halt_check = BRANCH_HALT_VOTED,
5409	.hwcg_reg = 0xc5028,
5410	.hwcg_bit = 1,
5411	.clkr = {
5412		.enable_reg = 0x62018,
5413		.enable_mask = BIT(3),
5414		.hw.init = &(const struct clk_init_data) {
5415			.name = "gcc_qupv3_oob_s_ahb_clk",
5416			.ops = &clk_branch2_ops,
5417		},
5418	},
5419};
5420
5421static struct clk_branch gcc_qupv3_oob_tcxo_clk = {
5422	.halt_reg = 0xe703c,
5423	.halt_check = BRANCH_HALT_VOTED,
5424	.clkr = {
5425		.enable_reg = 0x62018,
5426		.enable_mask = BIT(8),
5427		.hw.init = &(const struct clk_init_data) {
5428			.name = "gcc_qupv3_oob_tcxo_clk",
5429			.ops = &clk_branch2_ops,
5430		},
5431	},
5432};
5433
5434static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
5435	.halt_reg = 0xc5448,
5436	.halt_check = BRANCH_HALT_VOTED,
5437	.clkr = {
5438		.enable_reg = 0x62020,
5439		.enable_mask = BIT(12),
5440		.hw.init = &(const struct clk_init_data) {
5441			.name = "gcc_qupv3_wrap0_core_2x_clk",
5442			.ops = &clk_branch2_ops,
5443		},
5444	},
5445};
5446
5447static struct clk_branch gcc_qupv3_wrap0_core_clk = {
5448	.halt_reg = 0xc5434,
5449	.halt_check = BRANCH_HALT_VOTED,
5450	.clkr = {
5451		.enable_reg = 0x62020,
5452		.enable_mask = BIT(11),
5453		.hw.init = &(const struct clk_init_data) {
5454			.name = "gcc_qupv3_wrap0_core_clk",
5455			.ops = &clk_branch2_ops,
5456		},
5457	},
5458};
5459
5460static struct clk_branch gcc_qupv3_wrap0_qspi_s2_clk = {
5461	.halt_reg = 0x2879c,
5462	.halt_check = BRANCH_HALT_VOTED,
5463	.clkr = {
5464		.enable_reg = 0x62020,
5465		.enable_mask = BIT(22),
5466		.hw.init = &(const struct clk_init_data) {
5467			.name = "gcc_qupv3_wrap0_qspi_s2_clk",
5468			.parent_hws = (const struct clk_hw*[]) {
5469				&gcc_qupv3_wrap0_qspi_s2_clk_src.clkr.hw,
5470			},
5471			.num_parents = 1,
5472			.flags = CLK_SET_RATE_PARENT,
5473			.ops = &clk_branch2_ops,
5474		},
5475	},
5476};
5477
5478static struct clk_branch gcc_qupv3_wrap0_qspi_s3_clk = {
5479	.halt_reg = 0x288cc,
5480	.halt_check = BRANCH_HALT_VOTED,
5481	.clkr = {
5482		.enable_reg = 0x62020,
5483		.enable_mask = BIT(23),
5484		.hw.init = &(const struct clk_init_data) {
5485			.name = "gcc_qupv3_wrap0_qspi_s3_clk",
5486			.parent_hws = (const struct clk_hw*[]) {
5487				&gcc_qupv3_wrap0_qspi_s3_clk_src.clkr.hw,
5488			},
5489			.num_parents = 1,
5490			.flags = CLK_SET_RATE_PARENT,
5491			.ops = &clk_branch2_ops,
5492		},
5493	},
5494};
5495
5496static struct clk_branch gcc_qupv3_wrap0_qspi_s6_clk = {
5497	.halt_reg = 0x28798,
5498	.halt_check = BRANCH_HALT_VOTED,
5499	.clkr = {
5500		.enable_reg = 0x62020,
5501		.enable_mask = BIT(21),
5502		.hw.init = &(const struct clk_init_data) {
5503			.name = "gcc_qupv3_wrap0_qspi_s6_clk",
5504			.parent_hws = (const struct clk_hw*[]) {
5505				&gcc_qupv3_wrap0_qspi_s6_clk_src.clkr.hw,
5506			},
5507			.num_parents = 1,
5508			.flags = CLK_SET_RATE_PARENT,
5509			.ops = &clk_branch2_ops,
5510		},
5511	},
5512};
5513
5514static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
5515	.halt_reg = 0x28004,
5516	.halt_check = BRANCH_HALT_VOTED,
5517	.clkr = {
5518		.enable_reg = 0x62020,
5519		.enable_mask = BIT(13),
5520		.hw.init = &(const struct clk_init_data) {
5521			.name = "gcc_qupv3_wrap0_s0_clk",
5522			.parent_hws = (const struct clk_hw*[]) {
5523				&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
5524			},
5525			.num_parents = 1,
5526			.flags = CLK_SET_RATE_PARENT,
5527			.ops = &clk_branch2_ops,
5528		},
5529	},
5530};
5531
5532static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
5533	.halt_reg = 0x28140,
5534	.halt_check = BRANCH_HALT_VOTED,
5535	.clkr = {
5536		.enable_reg = 0x62020,
5537		.enable_mask = BIT(14),
5538		.hw.init = &(const struct clk_init_data) {
5539			.name = "gcc_qupv3_wrap0_s1_clk",
5540			.parent_hws = (const struct clk_hw*[]) {
5541				&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
5542			},
5543			.num_parents = 1,
5544			.flags = CLK_SET_RATE_PARENT,
5545			.ops = &clk_branch2_ops,
5546		},
5547	},
5548};
5549
5550static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
5551	.halt_reg = 0x2827c,
5552	.halt_check = BRANCH_HALT_VOTED,
5553	.clkr = {
5554		.enable_reg = 0x62020,
5555		.enable_mask = BIT(15),
5556		.hw.init = &(const struct clk_init_data) {
5557			.name = "gcc_qupv3_wrap0_s2_clk",
5558			.parent_hws = (const struct clk_hw*[]) {
5559				&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
5560			},
5561			.num_parents = 1,
5562			.flags = CLK_SET_RATE_PARENT,
5563			.ops = &clk_branch2_ops,
5564		},
5565	},
5566};
5567
5568static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
5569	.halt_reg = 0x28290,
5570	.halt_check = BRANCH_HALT_VOTED,
5571	.clkr = {
5572		.enable_reg = 0x62020,
5573		.enable_mask = BIT(16),
5574		.hw.init = &(const struct clk_init_data) {
5575			.name = "gcc_qupv3_wrap0_s3_clk",
5576			.parent_hws = (const struct clk_hw*[]) {
5577				&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
5578			},
5579			.num_parents = 1,
5580			.flags = CLK_SET_RATE_PARENT,
5581			.ops = &clk_branch2_ops,
5582		},
5583	},
5584};
5585
5586static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
5587	.halt_reg = 0x282a4,
5588	.halt_check = BRANCH_HALT_VOTED,
5589	.clkr = {
5590		.enable_reg = 0x62020,
5591		.enable_mask = BIT(17),
5592		.hw.init = &(const struct clk_init_data) {
5593			.name = "gcc_qupv3_wrap0_s4_clk",
5594			.parent_hws = (const struct clk_hw*[]) {
5595				&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
5596			},
5597			.num_parents = 1,
5598			.flags = CLK_SET_RATE_PARENT,
5599			.ops = &clk_branch2_ops,
5600		},
5601	},
5602};
5603
5604static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
5605	.halt_reg = 0x283e0,
5606	.halt_check = BRANCH_HALT_VOTED,
5607	.clkr = {
5608		.enable_reg = 0x62020,
5609		.enable_mask = BIT(18),
5610		.hw.init = &(const struct clk_init_data) {
5611			.name = "gcc_qupv3_wrap0_s5_clk",
5612			.parent_hws = (const struct clk_hw*[]) {
5613				&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
5614			},
5615			.num_parents = 1,
5616			.flags = CLK_SET_RATE_PARENT,
5617			.ops = &clk_branch2_ops,
5618		},
5619	},
5620};
5621
5622static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
5623	.halt_reg = 0x2851c,
5624	.halt_check = BRANCH_HALT_VOTED,
5625	.clkr = {
5626		.enable_reg = 0x62020,
5627		.enable_mask = BIT(19),
5628		.hw.init = &(const struct clk_init_data) {
5629			.name = "gcc_qupv3_wrap0_s6_clk",
5630			.parent_hws = (const struct clk_hw*[]) {
5631				&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
5632			},
5633			.num_parents = 1,
5634			.flags = CLK_SET_RATE_PARENT,
5635			.ops = &clk_branch2_ops,
5636		},
5637	},
5638};
5639
5640static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
5641	.halt_reg = 0x28530,
5642	.halt_check = BRANCH_HALT_VOTED,
5643	.clkr = {
5644		.enable_reg = 0x62020,
5645		.enable_mask = BIT(20),
5646		.hw.init = &(const struct clk_init_data) {
5647			.name = "gcc_qupv3_wrap0_s7_clk",
5648			.parent_hws = (const struct clk_hw*[]) {
5649				&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
5650			},
5651			.num_parents = 1,
5652			.flags = CLK_SET_RATE_PARENT,
5653			.ops = &clk_branch2_ops,
5654		},
5655	},
5656};
5657
5658static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
5659	.halt_reg = 0xc5198,
5660	.halt_check = BRANCH_HALT_VOTED,
5661	.clkr = {
5662		.enable_reg = 0x62018,
5663		.enable_mask = BIT(14),
5664		.hw.init = &(const struct clk_init_data) {
5665			.name = "gcc_qupv3_wrap1_core_2x_clk",
5666			.ops = &clk_branch2_ops,
5667		},
5668	},
5669};
5670
5671static struct clk_branch gcc_qupv3_wrap1_core_clk = {
5672	.halt_reg = 0xc5184,
5673	.halt_check = BRANCH_HALT_VOTED,
5674	.clkr = {
5675		.enable_reg = 0x62018,
5676		.enable_mask = BIT(13),
5677		.hw.init = &(const struct clk_init_data) {
5678			.name = "gcc_qupv3_wrap1_core_clk",
5679			.ops = &clk_branch2_ops,
5680		},
5681	},
5682};
5683
5684static struct clk_branch gcc_qupv3_wrap1_qspi_s2_clk = {
5685	.halt_reg = 0xb379c,
5686	.halt_check = BRANCH_HALT_VOTED,
5687	.clkr = {
5688		.enable_reg = 0x62018,
5689		.enable_mask = BIT(24),
5690		.hw.init = &(const struct clk_init_data) {
5691			.name = "gcc_qupv3_wrap1_qspi_s2_clk",
5692			.parent_hws = (const struct clk_hw*[]) {
5693				&gcc_qupv3_wrap1_qspi_s2_clk_src.clkr.hw,
5694			},
5695			.num_parents = 1,
5696			.flags = CLK_SET_RATE_PARENT,
5697			.ops = &clk_branch2_ops,
5698		},
5699	},
5700};
5701
5702static struct clk_branch gcc_qupv3_wrap1_qspi_s3_clk = {
5703	.halt_reg = 0xb38cc,
5704	.halt_check = BRANCH_HALT_VOTED,
5705	.clkr = {
5706		.enable_reg = 0x62018,
5707		.enable_mask = BIT(25),
5708		.hw.init = &(const struct clk_init_data) {
5709			.name = "gcc_qupv3_wrap1_qspi_s3_clk",
5710			.parent_hws = (const struct clk_hw*[]) {
5711				&gcc_qupv3_wrap1_qspi_s3_clk_src.clkr.hw,
5712			},
5713			.num_parents = 1,
5714			.flags = CLK_SET_RATE_PARENT,
5715			.ops = &clk_branch2_ops,
5716		},
5717	},
5718};
5719
5720static struct clk_branch gcc_qupv3_wrap1_qspi_s6_clk = {
5721	.halt_reg = 0xb3798,
5722	.halt_check = BRANCH_HALT_VOTED,
5723	.clkr = {
5724		.enable_reg = 0x62018,
5725		.enable_mask = BIT(23),
5726		.hw.init = &(const struct clk_init_data) {
5727			.name = "gcc_qupv3_wrap1_qspi_s6_clk",
5728			.parent_hws = (const struct clk_hw*[]) {
5729				&gcc_qupv3_wrap1_qspi_s6_clk_src.clkr.hw,
5730			},
5731			.num_parents = 1,
5732			.flags = CLK_SET_RATE_PARENT,
5733			.ops = &clk_branch2_ops,
5734		},
5735	},
5736};
5737
5738static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
5739	.halt_reg = 0xb3004,
5740	.halt_check = BRANCH_HALT_VOTED,
5741	.clkr = {
5742		.enable_reg = 0x62018,
5743		.enable_mask = BIT(15),
5744		.hw.init = &(const struct clk_init_data) {
5745			.name = "gcc_qupv3_wrap1_s0_clk",
5746			.parent_hws = (const struct clk_hw*[]) {
5747				&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
5748			},
5749			.num_parents = 1,
5750			.flags = CLK_SET_RATE_PARENT,
5751			.ops = &clk_branch2_ops,
5752		},
5753	},
5754};
5755
5756static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
5757	.halt_reg = 0xb3140,
5758	.halt_check = BRANCH_HALT_VOTED,
5759	.clkr = {
5760		.enable_reg = 0x62018,
5761		.enable_mask = BIT(16),
5762		.hw.init = &(const struct clk_init_data) {
5763			.name = "gcc_qupv3_wrap1_s1_clk",
5764			.parent_hws = (const struct clk_hw*[]) {
5765				&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
5766			},
5767			.num_parents = 1,
5768			.flags = CLK_SET_RATE_PARENT,
5769			.ops = &clk_branch2_ops,
5770		},
5771	},
5772};
5773
5774static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
5775	.halt_reg = 0xb327c,
5776	.halt_check = BRANCH_HALT_VOTED,
5777	.clkr = {
5778		.enable_reg = 0x62018,
5779		.enable_mask = BIT(17),
5780		.hw.init = &(const struct clk_init_data) {
5781			.name = "gcc_qupv3_wrap1_s2_clk",
5782			.parent_hws = (const struct clk_hw*[]) {
5783				&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
5784			},
5785			.num_parents = 1,
5786			.flags = CLK_SET_RATE_PARENT,
5787			.ops = &clk_branch2_ops,
5788		},
5789	},
5790};
5791
5792static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
5793	.halt_reg = 0xb3290,
5794	.halt_check = BRANCH_HALT_VOTED,
5795	.clkr = {
5796		.enable_reg = 0x62018,
5797		.enable_mask = BIT(18),
5798		.hw.init = &(const struct clk_init_data) {
5799			.name = "gcc_qupv3_wrap1_s3_clk",
5800			.parent_hws = (const struct clk_hw*[]) {
5801				&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
5802			},
5803			.num_parents = 1,
5804			.flags = CLK_SET_RATE_PARENT,
5805			.ops = &clk_branch2_ops,
5806		},
5807	},
5808};
5809
5810static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
5811	.halt_reg = 0xb32a4,
5812	.halt_check = BRANCH_HALT_VOTED,
5813	.clkr = {
5814		.enable_reg = 0x62018,
5815		.enable_mask = BIT(19),
5816		.hw.init = &(const struct clk_init_data) {
5817			.name = "gcc_qupv3_wrap1_s4_clk",
5818			.parent_hws = (const struct clk_hw*[]) {
5819				&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
5820			},
5821			.num_parents = 1,
5822			.flags = CLK_SET_RATE_PARENT,
5823			.ops = &clk_branch2_ops,
5824		},
5825	},
5826};
5827
5828static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
5829	.halt_reg = 0xb33e0,
5830	.halt_check = BRANCH_HALT_VOTED,
5831	.clkr = {
5832		.enable_reg = 0x62018,
5833		.enable_mask = BIT(20),
5834		.hw.init = &(const struct clk_init_data) {
5835			.name = "gcc_qupv3_wrap1_s5_clk",
5836			.parent_hws = (const struct clk_hw*[]) {
5837				&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
5838			},
5839			.num_parents = 1,
5840			.flags = CLK_SET_RATE_PARENT,
5841			.ops = &clk_branch2_ops,
5842		},
5843	},
5844};
5845
5846static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
5847	.halt_reg = 0xb351c,
5848	.halt_check = BRANCH_HALT_VOTED,
5849	.clkr = {
5850		.enable_reg = 0x62018,
5851		.enable_mask = BIT(21),
5852		.hw.init = &(const struct clk_init_data) {
5853			.name = "gcc_qupv3_wrap1_s6_clk",
5854			.parent_hws = (const struct clk_hw*[]) {
5855				&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
5856			},
5857			.num_parents = 1,
5858			.flags = CLK_SET_RATE_PARENT,
5859			.ops = &clk_branch2_ops,
5860		},
5861	},
5862};
5863
5864static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
5865	.halt_reg = 0xb3530,
5866	.halt_check = BRANCH_HALT_VOTED,
5867	.clkr = {
5868		.enable_reg = 0x62018,
5869		.enable_mask = BIT(22),
5870		.hw.init = &(const struct clk_init_data) {
5871			.name = "gcc_qupv3_wrap1_s7_clk",
5872			.parent_hws = (const struct clk_hw*[]) {
5873				&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
5874			},
5875			.num_parents = 1,
5876			.flags = CLK_SET_RATE_PARENT,
5877			.ops = &clk_branch2_ops,
5878		},
5879	},
5880};
5881
5882static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
5883	.halt_reg = 0xc52f0,
5884	.halt_check = BRANCH_HALT_VOTED,
5885	.clkr = {
5886		.enable_reg = 0x62018,
5887		.enable_mask = BIT(29),
5888		.hw.init = &(const struct clk_init_data) {
5889			.name = "gcc_qupv3_wrap2_core_2x_clk",
5890			.ops = &clk_branch2_ops,
5891		},
5892	},
5893};
5894
5895static struct clk_branch gcc_qupv3_wrap2_core_clk = {
5896	.halt_reg = 0xc52dc,
5897	.halt_check = BRANCH_HALT_VOTED,
5898	.clkr = {
5899		.enable_reg = 0x62018,
5900		.enable_mask = BIT(28),
5901		.hw.init = &(const struct clk_init_data) {
5902			.name = "gcc_qupv3_wrap2_core_clk",
5903			.ops = &clk_branch2_ops,
5904		},
5905	},
5906};
5907
5908static struct clk_branch gcc_qupv3_wrap2_qspi_s2_clk = {
5909	.halt_reg = 0xb479c,
5910	.halt_check = BRANCH_HALT_VOTED,
5911	.clkr = {
5912		.enable_reg = 0x62020,
5913		.enable_mask = BIT(7),
5914		.hw.init = &(const struct clk_init_data) {
5915			.name = "gcc_qupv3_wrap2_qspi_s2_clk",
5916			.parent_hws = (const struct clk_hw*[]) {
5917				&gcc_qupv3_wrap2_qspi_s2_clk_src.clkr.hw,
5918			},
5919			.num_parents = 1,
5920			.flags = CLK_SET_RATE_PARENT,
5921			.ops = &clk_branch2_ops,
5922		},
5923	},
5924};
5925
5926static struct clk_branch gcc_qupv3_wrap2_qspi_s3_clk = {
5927	.halt_reg = 0xb48cc,
5928	.halt_check = BRANCH_HALT_VOTED,
5929	.clkr = {
5930		.enable_reg = 0x62020,
5931		.enable_mask = BIT(8),
5932		.hw.init = &(const struct clk_init_data) {
5933			.name = "gcc_qupv3_wrap2_qspi_s3_clk",
5934			.parent_hws = (const struct clk_hw*[]) {
5935				&gcc_qupv3_wrap2_qspi_s3_clk_src.clkr.hw,
5936			},
5937			.num_parents = 1,
5938			.flags = CLK_SET_RATE_PARENT,
5939			.ops = &clk_branch2_ops,
5940		},
5941	},
5942};
5943
5944static struct clk_branch gcc_qupv3_wrap2_qspi_s6_clk = {
5945	.halt_reg = 0xb4798,
5946	.halt_check = BRANCH_HALT_VOTED,
5947	.clkr = {
5948		.enable_reg = 0x62020,
5949		.enable_mask = BIT(6),
5950		.hw.init = &(const struct clk_init_data) {
5951			.name = "gcc_qupv3_wrap2_qspi_s6_clk",
5952			.parent_hws = (const struct clk_hw*[]) {
5953				&gcc_qupv3_wrap2_qspi_s6_clk_src.clkr.hw,
5954			},
5955			.num_parents = 1,
5956			.flags = CLK_SET_RATE_PARENT,
5957			.ops = &clk_branch2_ops,
5958		},
5959	},
5960};
5961
5962static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
5963	.halt_reg = 0xb4004,
5964	.halt_check = BRANCH_HALT_VOTED,
5965	.clkr = {
5966		.enable_reg = 0x62018,
5967		.enable_mask = BIT(30),
5968		.hw.init = &(const struct clk_init_data) {
5969			.name = "gcc_qupv3_wrap2_s0_clk",
5970			.parent_hws = (const struct clk_hw*[]) {
5971				&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
5972			},
5973			.num_parents = 1,
5974			.flags = CLK_SET_RATE_PARENT,
5975			.ops = &clk_branch2_ops,
5976		},
5977	},
5978};
5979
5980static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
5981	.halt_reg = 0xb4140,
5982	.halt_check = BRANCH_HALT_VOTED,
5983	.clkr = {
5984		.enable_reg = 0x62018,
5985		.enable_mask = BIT(31),
5986		.hw.init = &(const struct clk_init_data) {
5987			.name = "gcc_qupv3_wrap2_s1_clk",
5988			.parent_hws = (const struct clk_hw*[]) {
5989				&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
5990			},
5991			.num_parents = 1,
5992			.flags = CLK_SET_RATE_PARENT,
5993			.ops = &clk_branch2_ops,
5994		},
5995	},
5996};
5997
5998static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
5999	.halt_reg = 0xb427c,
6000	.halt_check = BRANCH_HALT_VOTED,
6001	.clkr = {
6002		.enable_reg = 0x62020,
6003		.enable_mask = BIT(0),
6004		.hw.init = &(const struct clk_init_data) {
6005			.name = "gcc_qupv3_wrap2_s2_clk",
6006			.parent_hws = (const struct clk_hw*[]) {
6007				&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
6008			},
6009			.num_parents = 1,
6010			.flags = CLK_SET_RATE_PARENT,
6011			.ops = &clk_branch2_ops,
6012		},
6013	},
6014};
6015
6016static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
6017	.halt_reg = 0xb4290,
6018	.halt_check = BRANCH_HALT_VOTED,
6019	.clkr = {
6020		.enable_reg = 0x62020,
6021		.enable_mask = BIT(1),
6022		.hw.init = &(const struct clk_init_data) {
6023			.name = "gcc_qupv3_wrap2_s3_clk",
6024			.parent_hws = (const struct clk_hw*[]) {
6025				&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
6026			},
6027			.num_parents = 1,
6028			.flags = CLK_SET_RATE_PARENT,
6029			.ops = &clk_branch2_ops,
6030		},
6031	},
6032};
6033
6034static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
6035	.halt_reg = 0xb42a4,
6036	.halt_check = BRANCH_HALT_VOTED,
6037	.clkr = {
6038		.enable_reg = 0x62020,
6039		.enable_mask = BIT(2),
6040		.hw.init = &(const struct clk_init_data) {
6041			.name = "gcc_qupv3_wrap2_s4_clk",
6042			.parent_hws = (const struct clk_hw*[]) {
6043				&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
6044			},
6045			.num_parents = 1,
6046			.flags = CLK_SET_RATE_PARENT,
6047			.ops = &clk_branch2_ops,
6048		},
6049	},
6050};
6051
6052static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
6053	.halt_reg = 0xb43e0,
6054	.halt_check = BRANCH_HALT_VOTED,
6055	.clkr = {
6056		.enable_reg = 0x62020,
6057		.enable_mask = BIT(3),
6058		.hw.init = &(const struct clk_init_data) {
6059			.name = "gcc_qupv3_wrap2_s5_clk",
6060			.parent_hws = (const struct clk_hw*[]) {
6061				&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
6062			},
6063			.num_parents = 1,
6064			.flags = CLK_SET_RATE_PARENT,
6065			.ops = &clk_branch2_ops,
6066		},
6067	},
6068};
6069
6070static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
6071	.halt_reg = 0xb451c,
6072	.halt_check = BRANCH_HALT_VOTED,
6073	.clkr = {
6074		.enable_reg = 0x62020,
6075		.enable_mask = BIT(4),
6076		.hw.init = &(const struct clk_init_data) {
6077			.name = "gcc_qupv3_wrap2_s6_clk",
6078			.parent_hws = (const struct clk_hw*[]) {
6079				&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
6080			},
6081			.num_parents = 1,
6082			.flags = CLK_SET_RATE_PARENT,
6083			.ops = &clk_branch2_ops,
6084		},
6085	},
6086};
6087
6088static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
6089	.halt_reg = 0xb4530,
6090	.halt_check = BRANCH_HALT_VOTED,
6091	.clkr = {
6092		.enable_reg = 0x62020,
6093		.enable_mask = BIT(5),
6094		.hw.init = &(const struct clk_init_data) {
6095			.name = "gcc_qupv3_wrap2_s7_clk",
6096			.parent_hws = (const struct clk_hw*[]) {
6097				&gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
6098			},
6099			.num_parents = 1,
6100			.flags = CLK_SET_RATE_PARENT,
6101			.ops = &clk_branch2_ops,
6102		},
6103	},
6104};
6105
6106static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
6107	.halt_reg = 0xc542c,
6108	.halt_check = BRANCH_HALT_VOTED,
6109	.hwcg_reg = 0xc542c,
6110	.hwcg_bit = 1,
6111	.clkr = {
6112		.enable_reg = 0x62020,
6113		.enable_mask = BIT(9),
6114		.hw.init = &(const struct clk_init_data) {
6115			.name = "gcc_qupv3_wrap_0_m_ahb_clk",
6116			.ops = &clk_branch2_ops,
6117		},
6118	},
6119};
6120
6121static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
6122	.halt_reg = 0xc5430,
6123	.halt_check = BRANCH_HALT_VOTED,
6124	.hwcg_reg = 0xc5430,
6125	.hwcg_bit = 1,
6126	.clkr = {
6127		.enable_reg = 0x62020,
6128		.enable_mask = BIT(10),
6129		.hw.init = &(const struct clk_init_data) {
6130			.name = "gcc_qupv3_wrap_0_s_ahb_clk",
6131			.ops = &clk_branch2_ops,
6132		},
6133	},
6134};
6135
6136static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
6137	.halt_reg = 0xc517c,
6138	.halt_check = BRANCH_HALT_VOTED,
6139	.hwcg_reg = 0xc517c,
6140	.hwcg_bit = 1,
6141	.clkr = {
6142		.enable_reg = 0x62018,
6143		.enable_mask = BIT(11),
6144		.hw.init = &(const struct clk_init_data) {
6145			.name = "gcc_qupv3_wrap_1_m_ahb_clk",
6146			.ops = &clk_branch2_ops,
6147		},
6148	},
6149};
6150
6151static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
6152	.halt_reg = 0xc5180,
6153	.halt_check = BRANCH_HALT_VOTED,
6154	.hwcg_reg = 0xc5180,
6155	.hwcg_bit = 1,
6156	.clkr = {
6157		.enable_reg = 0x62018,
6158		.enable_mask = BIT(12),
6159		.hw.init = &(const struct clk_init_data) {
6160			.name = "gcc_qupv3_wrap_1_s_ahb_clk",
6161			.ops = &clk_branch2_ops,
6162		},
6163	},
6164};
6165
6166static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
6167	.halt_reg = 0xc52d4,
6168	.halt_check = BRANCH_HALT_VOTED,
6169	.hwcg_reg = 0xc52d4,
6170	.hwcg_bit = 1,
6171	.clkr = {
6172		.enable_reg = 0x62018,
6173		.enable_mask = BIT(26),
6174		.hw.init = &(const struct clk_init_data) {
6175			.name = "gcc_qupv3_wrap_2_m_ahb_clk",
6176			.ops = &clk_branch2_ops,
6177		},
6178	},
6179};
6180
6181static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
6182	.halt_reg = 0xc52d8,
6183	.halt_check = BRANCH_HALT_VOTED,
6184	.hwcg_reg = 0xc52d8,
6185	.hwcg_bit = 1,
6186	.clkr = {
6187		.enable_reg = 0x62018,
6188		.enable_mask = BIT(27),
6189		.hw.init = &(const struct clk_init_data) {
6190			.name = "gcc_qupv3_wrap_2_s_ahb_clk",
6191			.ops = &clk_branch2_ops,
6192		},
6193	},
6194};
6195
6196static struct clk_branch gcc_sdcc2_ahb_clk = {
6197	.halt_reg = 0xb0014,
6198	.halt_check = BRANCH_HALT,
6199	.clkr = {
6200		.enable_reg = 0xb0014,
6201		.enable_mask = BIT(0),
6202		.hw.init = &(const struct clk_init_data) {
6203			.name = "gcc_sdcc2_ahb_clk",
6204			.ops = &clk_branch2_ops,
6205		},
6206	},
6207};
6208
6209static struct clk_branch gcc_sdcc2_apps_clk = {
6210	.halt_reg = 0xb0004,
6211	.halt_check = BRANCH_HALT,
6212	.clkr = {
6213		.enable_reg = 0xb0004,
6214		.enable_mask = BIT(0),
6215		.hw.init = &(const struct clk_init_data) {
6216			.name = "gcc_sdcc2_apps_clk",
6217			.parent_hws = (const struct clk_hw*[]) {
6218				&gcc_sdcc2_apps_clk_src.clkr.hw,
6219			},
6220			.num_parents = 1,
6221			.flags = CLK_SET_RATE_PARENT,
6222			.ops = &clk_branch2_ops,
6223		},
6224	},
6225};
6226
6227static struct clk_branch gcc_sdcc4_ahb_clk = {
6228	.halt_reg = 0xdf014,
6229	.halt_check = BRANCH_HALT,
6230	.clkr = {
6231		.enable_reg = 0xdf014,
6232		.enable_mask = BIT(0),
6233		.hw.init = &(const struct clk_init_data) {
6234			.name = "gcc_sdcc4_ahb_clk",
6235			.ops = &clk_branch2_ops,
6236		},
6237	},
6238};
6239
6240static struct clk_branch gcc_sdcc4_apps_clk = {
6241	.halt_reg = 0xdf004,
6242	.halt_check = BRANCH_HALT,
6243	.clkr = {
6244		.enable_reg = 0xdf004,
6245		.enable_mask = BIT(0),
6246		.hw.init = &(const struct clk_init_data) {
6247			.name = "gcc_sdcc4_apps_clk",
6248			.parent_hws = (const struct clk_hw*[]) {
6249				&gcc_sdcc4_apps_clk_src.clkr.hw,
6250			},
6251			.num_parents = 1,
6252			.flags = CLK_SET_RATE_PARENT,
6253			.ops = &clk_branch2_ops,
6254		},
6255	},
6256};
6257
6258static struct clk_branch gcc_ufs_phy_ahb_clk = {
6259	.halt_reg = 0xba504,
6260	.halt_check = BRANCH_HALT_VOTED,
6261	.hwcg_reg = 0xba504,
6262	.hwcg_bit = 1,
6263	.clkr = {
6264		.enable_reg = 0xba504,
6265		.enable_mask = BIT(0),
6266		.hw.init = &(const struct clk_init_data) {
6267			.name = "gcc_ufs_phy_ahb_clk",
6268			.ops = &clk_branch2_ops,
6269		},
6270	},
6271};
6272
6273static struct clk_branch gcc_ufs_phy_axi_clk = {
6274	.halt_reg = 0x7701c,
6275	.halt_check = BRANCH_HALT_VOTED,
6276	.hwcg_reg = 0x7701c,
6277	.hwcg_bit = 1,
6278	.clkr = {
6279		.enable_reg = 0x7701c,
6280		.enable_mask = BIT(0),
6281		.hw.init = &(const struct clk_init_data) {
6282			.name = "gcc_ufs_phy_axi_clk",
6283			.parent_hws = (const struct clk_hw*[]) {
6284				&gcc_ufs_phy_axi_clk_src.clkr.hw,
6285			},
6286			.num_parents = 1,
6287			.flags = CLK_SET_RATE_PARENT,
6288			.ops = &clk_branch2_ops,
6289		},
6290	},
6291};
6292
6293static struct clk_branch gcc_ufs_phy_ice_core_clk = {
6294	.halt_reg = 0x77080,
6295	.halt_check = BRANCH_HALT_VOTED,
6296	.hwcg_reg = 0x77080,
6297	.hwcg_bit = 1,
6298	.clkr = {
6299		.enable_reg = 0x77080,
6300		.enable_mask = BIT(0),
6301		.hw.init = &(const struct clk_init_data) {
6302			.name = "gcc_ufs_phy_ice_core_clk",
6303			.parent_hws = (const struct clk_hw*[]) {
6304				&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
6305			},
6306			.num_parents = 1,
6307			.flags = CLK_SET_RATE_PARENT,
6308			.ops = &clk_branch2_ops,
6309		},
6310	},
6311};
6312
6313static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
6314	.halt_reg = 0x770c0,
6315	.halt_check = BRANCH_HALT_VOTED,
6316	.hwcg_reg = 0x770c0,
6317	.hwcg_bit = 1,
6318	.clkr = {
6319		.enable_reg = 0x770c0,
6320		.enable_mask = BIT(0),
6321		.hw.init = &(const struct clk_init_data) {
6322			.name = "gcc_ufs_phy_phy_aux_clk",
6323			.parent_hws = (const struct clk_hw*[]) {
6324				&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
6325			},
6326			.num_parents = 1,
6327			.flags = CLK_SET_RATE_PARENT,
6328			.ops = &clk_branch2_ops,
6329		},
6330	},
6331};
6332
6333static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
6334	.halt_reg = 0x77034,
6335	.halt_check = BRANCH_HALT_DELAY,
6336	.clkr = {
6337		.enable_reg = 0x77034,
6338		.enable_mask = BIT(0),
6339		.hw.init = &(const struct clk_init_data) {
6340			.name = "gcc_ufs_phy_rx_symbol_0_clk",
6341			.parent_hws = (const struct clk_hw*[]) {
6342				&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
6343			},
6344			.num_parents = 1,
6345			.flags = CLK_SET_RATE_PARENT,
6346			.ops = &clk_branch2_ops,
6347		},
6348	},
6349};
6350
6351static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
6352	.halt_reg = 0x770dc,
6353	.halt_check = BRANCH_HALT_DELAY,
6354	.clkr = {
6355		.enable_reg = 0x770dc,
6356		.enable_mask = BIT(0),
6357		.hw.init = &(const struct clk_init_data) {
6358			.name = "gcc_ufs_phy_rx_symbol_1_clk",
6359			.parent_hws = (const struct clk_hw*[]) {
6360				&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
6361			},
6362			.num_parents = 1,
6363			.flags = CLK_SET_RATE_PARENT,
6364			.ops = &clk_branch2_ops,
6365		},
6366	},
6367};
6368
6369static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
6370	.halt_reg = 0x77030,
6371	.halt_check = BRANCH_HALT_DELAY,
6372	.clkr = {
6373		.enable_reg = 0x77030,
6374		.enable_mask = BIT(0),
6375		.hw.init = &(const struct clk_init_data) {
6376			.name = "gcc_ufs_phy_tx_symbol_0_clk",
6377			.parent_hws = (const struct clk_hw*[]) {
6378				&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
6379			},
6380			.num_parents = 1,
6381			.flags = CLK_SET_RATE_PARENT,
6382			.ops = &clk_branch2_ops,
6383		},
6384	},
6385};
6386
6387static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
6388	.halt_reg = 0x77070,
6389	.halt_check = BRANCH_HALT_VOTED,
6390	.hwcg_reg = 0x77070,
6391	.hwcg_bit = 1,
6392	.clkr = {
6393		.enable_reg = 0x77070,
6394		.enable_mask = BIT(0),
6395		.hw.init = &(const struct clk_init_data) {
6396			.name = "gcc_ufs_phy_unipro_core_clk",
6397			.parent_hws = (const struct clk_hw*[]) {
6398				&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
6399			},
6400			.num_parents = 1,
6401			.flags = CLK_SET_RATE_PARENT,
6402			.ops = &clk_branch2_ops,
6403		},
6404	},
6405};
6406
6407static struct clk_branch gcc_usb20_master_clk = {
6408	.halt_reg = 0xbc018,
6409	.halt_check = BRANCH_HALT,
6410	.clkr = {
6411		.enable_reg = 0xbc018,
6412		.enable_mask = BIT(0),
6413		.hw.init = &(const struct clk_init_data) {
6414			.name = "gcc_usb20_master_clk",
6415			.parent_hws = (const struct clk_hw*[]) {
6416				&gcc_usb20_master_clk_src.clkr.hw,
6417			},
6418			.num_parents = 1,
6419			.flags = CLK_SET_RATE_PARENT,
6420			.ops = &clk_branch2_ops,
6421		},
6422	},
6423};
6424
6425static struct clk_branch gcc_usb20_mock_utmi_clk = {
6426	.halt_reg = 0xbc02c,
6427	.halt_check = BRANCH_HALT,
6428	.clkr = {
6429		.enable_reg = 0xbc02c,
6430		.enable_mask = BIT(0),
6431		.hw.init = &(const struct clk_init_data) {
6432			.name = "gcc_usb20_mock_utmi_clk",
6433			.parent_hws = (const struct clk_hw*[]) {
6434				&gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw,
6435			},
6436			.num_parents = 1,
6437			.flags = CLK_SET_RATE_PARENT,
6438			.ops = &clk_branch2_ops,
6439		},
6440	},
6441};
6442
6443static struct clk_branch gcc_usb20_sleep_clk = {
6444	.halt_reg = 0xbc028,
6445	.halt_check = BRANCH_HALT,
6446	.clkr = {
6447		.enable_reg = 0xbc028,
6448		.enable_mask = BIT(0),
6449		.hw.init = &(const struct clk_init_data) {
6450			.name = "gcc_usb20_sleep_clk",
6451			.ops = &clk_branch2_ops,
6452		},
6453	},
6454};
6455
6456static struct clk_branch gcc_usb30_mp_master_clk = {
6457	.halt_reg = 0x9a024,
6458	.halt_check = BRANCH_HALT,
6459	.clkr = {
6460		.enable_reg = 0x9a024,
6461		.enable_mask = BIT(0),
6462		.hw.init = &(const struct clk_init_data) {
6463			.name = "gcc_usb30_mp_master_clk",
6464			.parent_hws = (const struct clk_hw*[]) {
6465				&gcc_usb30_mp_master_clk_src.clkr.hw,
6466			},
6467			.num_parents = 1,
6468			.flags = CLK_SET_RATE_PARENT,
6469			.ops = &clk_branch2_ops,
6470		},
6471	},
6472};
6473
6474static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {
6475	.halt_reg = 0x9a038,
6476	.halt_check = BRANCH_HALT,
6477	.clkr = {
6478		.enable_reg = 0x9a038,
6479		.enable_mask = BIT(0),
6480		.hw.init = &(const struct clk_init_data) {
6481			.name = "gcc_usb30_mp_mock_utmi_clk",
6482			.parent_hws = (const struct clk_hw*[]) {
6483				&gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw,
6484			},
6485			.num_parents = 1,
6486			.flags = CLK_SET_RATE_PARENT,
6487			.ops = &clk_branch2_ops,
6488		},
6489	},
6490};
6491
6492static struct clk_branch gcc_usb30_mp_sleep_clk = {
6493	.halt_reg = 0x9a034,
6494	.halt_check = BRANCH_HALT,
6495	.clkr = {
6496		.enable_reg = 0x9a034,
6497		.enable_mask = BIT(0),
6498		.hw.init = &(const struct clk_init_data) {
6499			.name = "gcc_usb30_mp_sleep_clk",
6500			.ops = &clk_branch2_ops,
6501		},
6502	},
6503};
6504
6505static struct clk_branch gcc_usb30_prim_master_clk = {
6506	.halt_reg = 0x3f030,
6507	.halt_check = BRANCH_HALT,
6508	.clkr = {
6509		.enable_reg = 0x3f030,
6510		.enable_mask = BIT(0),
6511		.hw.init = &(const struct clk_init_data) {
6512			.name = "gcc_usb30_prim_master_clk",
6513			.parent_hws = (const struct clk_hw*[]) {
6514				&gcc_usb30_prim_master_clk_src.clkr.hw,
6515			},
6516			.num_parents = 1,
6517			.flags = CLK_SET_RATE_PARENT,
6518			.ops = &clk_branch2_ops,
6519		},
6520	},
6521};
6522
6523static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
6524	.halt_reg = 0x3f048,
6525	.halt_check = BRANCH_HALT,
6526	.clkr = {
6527		.enable_reg = 0x3f048,
6528		.enable_mask = BIT(0),
6529		.hw.init = &(const struct clk_init_data) {
6530			.name = "gcc_usb30_prim_mock_utmi_clk",
6531			.parent_hws = (const struct clk_hw*[]) {
6532				&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
6533			},
6534			.num_parents = 1,
6535			.flags = CLK_SET_RATE_PARENT,
6536			.ops = &clk_branch2_ops,
6537		},
6538	},
6539};
6540
6541static struct clk_branch gcc_usb30_prim_sleep_clk = {
6542	.halt_reg = 0x3f044,
6543	.halt_check = BRANCH_HALT,
6544	.clkr = {
6545		.enable_reg = 0x3f044,
6546		.enable_mask = BIT(0),
6547		.hw.init = &(const struct clk_init_data) {
6548			.name = "gcc_usb30_prim_sleep_clk",
6549			.ops = &clk_branch2_ops,
6550		},
6551	},
6552};
6553
6554static struct clk_branch gcc_usb30_sec_master_clk = {
6555	.halt_reg = 0xe2024,
6556	.halt_check = BRANCH_HALT,
6557	.clkr = {
6558		.enable_reg = 0xe2024,
6559		.enable_mask = BIT(0),
6560		.hw.init = &(const struct clk_init_data) {
6561			.name = "gcc_usb30_sec_master_clk",
6562			.parent_hws = (const struct clk_hw*[]) {
6563				&gcc_usb30_sec_master_clk_src.clkr.hw,
6564			},
6565			.num_parents = 1,
6566			.flags = CLK_SET_RATE_PARENT,
6567			.ops = &clk_branch2_ops,
6568		},
6569	},
6570};
6571
6572static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
6573	.halt_reg = 0xe2038,
6574	.halt_check = BRANCH_HALT,
6575	.clkr = {
6576		.enable_reg = 0xe2038,
6577		.enable_mask = BIT(0),
6578		.hw.init = &(const struct clk_init_data) {
6579			.name = "gcc_usb30_sec_mock_utmi_clk",
6580			.parent_hws = (const struct clk_hw*[]) {
6581				&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
6582			},
6583			.num_parents = 1,
6584			.flags = CLK_SET_RATE_PARENT,
6585			.ops = &clk_branch2_ops,
6586		},
6587	},
6588};
6589
6590static struct clk_branch gcc_usb30_sec_sleep_clk = {
6591	.halt_reg = 0xe2034,
6592	.halt_check = BRANCH_HALT,
6593	.clkr = {
6594		.enable_reg = 0xe2034,
6595		.enable_mask = BIT(0),
6596		.hw.init = &(const struct clk_init_data) {
6597			.name = "gcc_usb30_sec_sleep_clk",
6598			.ops = &clk_branch2_ops,
6599		},
6600	},
6601};
6602
6603static struct clk_branch gcc_usb30_tert_master_clk = {
6604	.halt_reg = 0xe1024,
6605	.halt_check = BRANCH_HALT,
6606	.clkr = {
6607		.enable_reg = 0xe1024,
6608		.enable_mask = BIT(0),
6609		.hw.init = &(const struct clk_init_data) {
6610			.name = "gcc_usb30_tert_master_clk",
6611			.parent_hws = (const struct clk_hw*[]) {
6612				&gcc_usb30_tert_master_clk_src.clkr.hw,
6613			},
6614			.num_parents = 1,
6615			.flags = CLK_SET_RATE_PARENT,
6616			.ops = &clk_branch2_ops,
6617		},
6618	},
6619};
6620
6621static struct clk_branch gcc_usb30_tert_mock_utmi_clk = {
6622	.halt_reg = 0xe1038,
6623	.halt_check = BRANCH_HALT,
6624	.clkr = {
6625		.enable_reg = 0xe1038,
6626		.enable_mask = BIT(0),
6627		.hw.init = &(const struct clk_init_data) {
6628			.name = "gcc_usb30_tert_mock_utmi_clk",
6629			.parent_hws = (const struct clk_hw*[]) {
6630				&gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr.hw,
6631			},
6632			.num_parents = 1,
6633			.flags = CLK_SET_RATE_PARENT,
6634			.ops = &clk_branch2_ops,
6635		},
6636	},
6637};
6638
6639static struct clk_branch gcc_usb30_tert_sleep_clk = {
6640	.halt_reg = 0xe1034,
6641	.halt_check = BRANCH_HALT,
6642	.clkr = {
6643		.enable_reg = 0xe1034,
6644		.enable_mask = BIT(0),
6645		.hw.init = &(const struct clk_init_data) {
6646			.name = "gcc_usb30_tert_sleep_clk",
6647			.ops = &clk_branch2_ops,
6648		},
6649	},
6650};
6651
6652static struct clk_branch gcc_usb3_mp_phy_aux_clk = {
6653	.halt_reg = 0x9a070,
6654	.halt_check = BRANCH_HALT,
6655	.clkr = {
6656		.enable_reg = 0x9a070,
6657		.enable_mask = BIT(0),
6658		.hw.init = &(const struct clk_init_data) {
6659			.name = "gcc_usb3_mp_phy_aux_clk",
6660			.parent_hws = (const struct clk_hw*[]) {
6661				&gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
6662			},
6663			.num_parents = 1,
6664			.flags = CLK_SET_RATE_PARENT,
6665			.ops = &clk_branch2_ops,
6666		},
6667	},
6668};
6669
6670static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {
6671	.halt_reg = 0x9a074,
6672	.halt_check = BRANCH_HALT,
6673	.clkr = {
6674		.enable_reg = 0x9a074,
6675		.enable_mask = BIT(0),
6676		.hw.init = &(const struct clk_init_data) {
6677			.name = "gcc_usb3_mp_phy_com_aux_clk",
6678			.parent_hws = (const struct clk_hw*[]) {
6679				&gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
6680			},
6681			.num_parents = 1,
6682			.flags = CLK_SET_RATE_PARENT,
6683			.ops = &clk_branch2_ops,
6684		},
6685	},
6686};
6687
6688static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {
6689	.halt_reg = 0x9a078,
6690	.halt_check = BRANCH_HALT_SKIP,
6691	.clkr = {
6692		.enable_reg = 0x9a078,
6693		.enable_mask = BIT(0),
6694		.hw.init = &(const struct clk_init_data) {
6695			.name = "gcc_usb3_mp_phy_pipe_0_clk",
6696			.parent_hws = (const struct clk_hw*[]) {
6697				&gcc_usb3_mp_phy_pipe_0_clk_src.clkr.hw,
6698			},
6699			.num_parents = 1,
6700			.flags = CLK_SET_RATE_PARENT,
6701			.ops = &clk_branch2_ops,
6702		},
6703	},
6704};
6705
6706static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {
6707	.halt_reg = 0x9a080,
6708	.halt_check = BRANCH_HALT_SKIP,
6709	.clkr = {
6710		.enable_reg = 0x9a080,
6711		.enable_mask = BIT(0),
6712		.hw.init = &(const struct clk_init_data) {
6713			.name = "gcc_usb3_mp_phy_pipe_1_clk",
6714			.parent_hws = (const struct clk_hw*[]) {
6715				&gcc_usb3_mp_phy_pipe_1_clk_src.clkr.hw,
6716			},
6717			.num_parents = 1,
6718			.flags = CLK_SET_RATE_PARENT,
6719			.ops = &clk_branch2_ops,
6720		},
6721	},
6722};
6723
6724static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
6725	.halt_reg = 0x3f080,
6726	.halt_check = BRANCH_HALT,
6727	.clkr = {
6728		.enable_reg = 0x3f080,
6729		.enable_mask = BIT(0),
6730		.hw.init = &(const struct clk_init_data) {
6731			.name = "gcc_usb3_prim_phy_aux_clk",
6732			.parent_hws = (const struct clk_hw*[]) {
6733				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
6734			},
6735			.num_parents = 1,
6736			.flags = CLK_SET_RATE_PARENT,
6737			.ops = &clk_branch2_ops,
6738		},
6739	},
6740};
6741
6742static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
6743	.halt_reg = 0x3f084,
6744	.halt_check = BRANCH_HALT,
6745	.clkr = {
6746		.enable_reg = 0x3f084,
6747		.enable_mask = BIT(0),
6748		.hw.init = &(const struct clk_init_data) {
6749			.name = "gcc_usb3_prim_phy_com_aux_clk",
6750			.parent_hws = (const struct clk_hw*[]) {
6751				&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
6752			},
6753			.num_parents = 1,
6754			.flags = CLK_SET_RATE_PARENT,
6755			.ops = &clk_branch2_ops,
6756		},
6757	},
6758};
6759
6760static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
6761	.halt_reg = 0x3f088,
6762	.halt_check = BRANCH_HALT_SKIP,
6763	.hwcg_reg = 0x3f088,
6764	.hwcg_bit = 1,
6765	.clkr = {
6766		.enable_reg = 0x3f088,
6767		.enable_mask = BIT(0),
6768		.hw.init = &(const struct clk_init_data) {
6769			.name = "gcc_usb3_prim_phy_pipe_clk",
6770			.parent_hws = (const struct clk_hw*[]) {
6771				&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
6772			},
6773			.num_parents = 1,
6774			.flags = CLK_SET_RATE_PARENT,
6775			.ops = &clk_branch2_ops,
6776		},
6777	},
6778};
6779
6780static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
6781	.halt_reg = 0xe2070,
6782	.halt_check = BRANCH_HALT,
6783	.clkr = {
6784		.enable_reg = 0xe2070,
6785		.enable_mask = BIT(0),
6786		.hw.init = &(const struct clk_init_data) {
6787			.name = "gcc_usb3_sec_phy_aux_clk",
6788			.parent_hws = (const struct clk_hw*[]) {
6789				&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
6790			},
6791			.num_parents = 1,
6792			.flags = CLK_SET_RATE_PARENT,
6793			.ops = &clk_branch2_ops,
6794		},
6795	},
6796};
6797
6798static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
6799	.halt_reg = 0xe2074,
6800	.halt_check = BRANCH_HALT,
6801	.clkr = {
6802		.enable_reg = 0xe2074,
6803		.enable_mask = BIT(0),
6804		.hw.init = &(const struct clk_init_data) {
6805			.name = "gcc_usb3_sec_phy_com_aux_clk",
6806			.parent_hws = (const struct clk_hw*[]) {
6807				&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
6808			},
6809			.num_parents = 1,
6810			.flags = CLK_SET_RATE_PARENT,
6811			.ops = &clk_branch2_ops,
6812		},
6813	},
6814};
6815
6816static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
6817	.halt_reg = 0xe2078,
6818	.halt_check = BRANCH_HALT_SKIP,
6819	.hwcg_reg = 0xe2078,
6820	.hwcg_bit = 1,
6821	.clkr = {
6822		.enable_reg = 0xe2078,
6823		.enable_mask = BIT(0),
6824		.hw.init = &(const struct clk_init_data) {
6825			.name = "gcc_usb3_sec_phy_pipe_clk",
6826			.parent_hws = (const struct clk_hw*[]) {
6827				&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
6828			},
6829			.num_parents = 1,
6830			.flags = CLK_SET_RATE_PARENT,
6831			.ops = &clk_branch2_ops,
6832		},
6833	},
6834};
6835
6836static struct clk_branch gcc_usb3_tert_phy_aux_clk = {
6837	.halt_reg = 0xe1070,
6838	.halt_check = BRANCH_HALT,
6839	.clkr = {
6840		.enable_reg = 0xe1070,
6841		.enable_mask = BIT(0),
6842		.hw.init = &(const struct clk_init_data) {
6843			.name = "gcc_usb3_tert_phy_aux_clk",
6844			.parent_hws = (const struct clk_hw*[]) {
6845				&gcc_usb3_tert_phy_aux_clk_src.clkr.hw,
6846			},
6847			.num_parents = 1,
6848			.flags = CLK_SET_RATE_PARENT,
6849			.ops = &clk_branch2_ops,
6850		},
6851	},
6852};
6853
6854static struct clk_branch gcc_usb3_tert_phy_com_aux_clk = {
6855	.halt_reg = 0xe1074,
6856	.halt_check = BRANCH_HALT,
6857	.clkr = {
6858		.enable_reg = 0xe1074,
6859		.enable_mask = BIT(0),
6860		.hw.init = &(const struct clk_init_data) {
6861			.name = "gcc_usb3_tert_phy_com_aux_clk",
6862			.parent_hws = (const struct clk_hw*[]) {
6863				&gcc_usb3_tert_phy_aux_clk_src.clkr.hw,
6864			},
6865			.num_parents = 1,
6866			.flags = CLK_SET_RATE_PARENT,
6867			.ops = &clk_branch2_ops,
6868		},
6869	},
6870};
6871
6872static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
6873	.halt_reg = 0xe1078,
6874	.halt_check = BRANCH_HALT_SKIP,
6875	.hwcg_reg = 0xe1078,
6876	.hwcg_bit = 1,
6877	.clkr = {
6878		.enable_reg = 0xe1078,
6879		.enable_mask = BIT(0),
6880		.hw.init = &(const struct clk_init_data) {
6881			.name = "gcc_usb3_tert_phy_pipe_clk",
6882			.parent_hws = (const struct clk_hw*[]) {
6883				&gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
6884			},
6885			.num_parents = 1,
6886			.flags = CLK_SET_RATE_PARENT,
6887			.ops = &clk_branch2_ops,
6888		},
6889	},
6890};
6891
6892static struct clk_branch gcc_usb4_0_cfg_ahb_clk = {
6893	.halt_reg = 0xba450,
6894	.halt_check = BRANCH_HALT_VOTED,
6895	.hwcg_reg = 0xba450,
6896	.hwcg_bit = 1,
6897	.clkr = {
6898		.enable_reg = 0xba450,
6899		.enable_mask = BIT(0),
6900		.hw.init = &(const struct clk_init_data) {
6901			.name = "gcc_usb4_0_cfg_ahb_clk",
6902			.ops = &clk_branch2_ops,
6903		},
6904	},
6905};
6906
6907static struct clk_branch gcc_usb4_0_dp0_clk = {
6908	.halt_reg = 0x2b070,
6909	.halt_check = BRANCH_HALT,
6910	.clkr = {
6911		.enable_reg = 0x2b070,
6912		.enable_mask = BIT(0),
6913		.hw.init = &(const struct clk_init_data) {
6914			.name = "gcc_usb4_0_dp0_clk",
6915			.parent_hws = (const struct clk_hw*[]) {
6916				&gcc_usb4_0_phy_dp0_clk_src.clkr.hw,
6917			},
6918			.num_parents = 1,
6919			.flags = CLK_SET_RATE_PARENT,
6920			.ops = &clk_branch2_ops,
6921		},
6922	},
6923};
6924
6925static struct clk_branch gcc_usb4_0_dp1_clk = {
6926	.halt_reg = 0x2b124,
6927	.halt_check = BRANCH_HALT,
6928	.clkr = {
6929		.enable_reg = 0x2b124,
6930		.enable_mask = BIT(0),
6931		.hw.init = &(const struct clk_init_data) {
6932			.name = "gcc_usb4_0_dp1_clk",
6933			.parent_hws = (const struct clk_hw*[]) {
6934				&gcc_usb4_0_phy_dp1_clk_src.clkr.hw,
6935			},
6936			.num_parents = 1,
6937			.flags = CLK_SET_RATE_PARENT,
6938			.ops = &clk_branch2_ops,
6939		},
6940	},
6941};
6942
6943static struct clk_branch gcc_usb4_0_master_clk = {
6944	.halt_reg = 0x2b01c,
6945	.halt_check = BRANCH_HALT,
6946	.clkr = {
6947		.enable_reg = 0x2b01c,
6948		.enable_mask = BIT(0),
6949		.hw.init = &(const struct clk_init_data) {
6950			.name = "gcc_usb4_0_master_clk",
6951			.parent_hws = (const struct clk_hw*[]) {
6952				&gcc_usb4_0_master_clk_src.clkr.hw,
6953			},
6954			.num_parents = 1,
6955			.flags = CLK_SET_RATE_PARENT,
6956			.ops = &clk_branch2_ops,
6957		},
6958	},
6959};
6960
6961static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = {
6962	.halt_reg = 0x2b0f4,
6963	.halt_check = BRANCH_HALT_SKIP,
6964	.clkr = {
6965		.enable_reg = 0x2b0f4,
6966		.enable_mask = BIT(0),
6967		.hw.init = &(const struct clk_init_data) {
6968			.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk",
6969			.parent_hws = (const struct clk_hw*[]) {
6970				&gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr.hw,
6971			},
6972			.num_parents = 1,
6973			.flags = CLK_SET_RATE_PARENT,
6974			.ops = &clk_branch2_ops,
6975		},
6976	},
6977};
6978
6979static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = {
6980	.halt_reg = 0x2b04c,
6981	.halt_check = BRANCH_HALT_SKIP,
6982	.clkr = {
6983		.enable_reg = 0x62010,
6984		.enable_mask = BIT(11),
6985		.hw.init = &(const struct clk_init_data) {
6986			.name = "gcc_usb4_0_phy_pcie_pipe_clk",
6987			.parent_hws = (const struct clk_hw*[]) {
6988				&gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
6989			},
6990			.num_parents = 1,
6991			.flags = CLK_SET_RATE_PARENT,
6992			.ops = &clk_branch2_ops,
6993		},
6994	},
6995};
6996
6997static struct clk_branch gcc_usb4_0_phy_rx0_clk = {
6998	.halt_reg = 0x2b0c4,
6999	.halt_check = BRANCH_HALT,
7000	.clkr = {
7001		.enable_reg = 0x2b0c4,
7002		.enable_mask = BIT(0),
7003		.hw.init = &(const struct clk_init_data) {
7004			.name = "gcc_usb4_0_phy_rx0_clk",
7005			.parent_hws = (const struct clk_hw*[]) {
7006				&gcc_usb4_0_phy_rx0_clk_src.clkr.hw,
7007			},
7008			.num_parents = 1,
7009			.flags = CLK_SET_RATE_PARENT,
7010			.ops = &clk_branch2_ops,
7011		},
7012	},
7013};
7014
7015static struct clk_branch gcc_usb4_0_phy_rx1_clk = {
7016	.halt_reg = 0x2b0d8,
7017	.halt_check = BRANCH_HALT,
7018	.clkr = {
7019		.enable_reg = 0x2b0d8,
7020		.enable_mask = BIT(0),
7021		.hw.init = &(const struct clk_init_data) {
7022			.name = "gcc_usb4_0_phy_rx1_clk",
7023			.parent_hws = (const struct clk_hw*[]) {
7024				&gcc_usb4_0_phy_rx1_clk_src.clkr.hw,
7025			},
7026			.num_parents = 1,
7027			.flags = CLK_SET_RATE_PARENT,
7028			.ops = &clk_branch2_ops,
7029		},
7030	},
7031};
7032
7033static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = {
7034	.halt_reg = 0x2b0bc,
7035	.halt_check = BRANCH_HALT_SKIP,
7036	.hwcg_reg = 0x2b0bc,
7037	.hwcg_bit = 1,
7038	.clkr = {
7039		.enable_reg = 0x2b0bc,
7040		.enable_mask = BIT(0),
7041		.hw.init = &(const struct clk_init_data) {
7042			.name = "gcc_usb4_0_phy_usb_pipe_clk",
7043			.parent_hws = (const struct clk_hw*[]) {
7044				&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
7045			},
7046			.num_parents = 1,
7047			.flags = CLK_SET_RATE_PARENT,
7048			.ops = &clk_branch2_ops,
7049		},
7050	},
7051};
7052
7053static struct clk_branch gcc_usb4_0_sb_if_clk = {
7054	.halt_reg = 0x2b048,
7055	.halt_check = BRANCH_HALT,
7056	.clkr = {
7057		.enable_reg = 0x2b048,
7058		.enable_mask = BIT(0),
7059		.hw.init = &(const struct clk_init_data) {
7060			.name = "gcc_usb4_0_sb_if_clk",
7061			.parent_hws = (const struct clk_hw*[]) {
7062				&gcc_usb4_0_sb_if_clk_src.clkr.hw,
7063			},
7064			.num_parents = 1,
7065			.flags = CLK_SET_RATE_PARENT,
7066			.ops = &clk_branch2_ops,
7067		},
7068	},
7069};
7070
7071static struct clk_branch gcc_usb4_0_sys_clk = {
7072	.halt_reg = 0x2b05c,
7073	.halt_check = BRANCH_HALT,
7074	.clkr = {
7075		.enable_reg = 0x2b05c,
7076		.enable_mask = BIT(0),
7077		.hw.init = &(const struct clk_init_data) {
7078			.name = "gcc_usb4_0_sys_clk",
7079			.parent_hws = (const struct clk_hw*[]) {
7080				&gcc_usb4_0_phy_sys_clk_src.clkr.hw,
7081			},
7082			.num_parents = 1,
7083			.flags = CLK_SET_RATE_PARENT,
7084			.ops = &clk_branch2_ops,
7085		},
7086	},
7087};
7088
7089static struct clk_branch gcc_usb4_0_tmu_clk = {
7090	.halt_reg = 0x2b09c,
7091	.halt_check = BRANCH_HALT_VOTED,
7092	.hwcg_reg = 0x2b09c,
7093	.hwcg_bit = 1,
7094	.clkr = {
7095		.enable_reg = 0x2b09c,
7096		.enable_mask = BIT(0),
7097		.hw.init = &(const struct clk_init_data) {
7098			.name = "gcc_usb4_0_tmu_clk",
7099			.parent_hws = (const struct clk_hw*[]) {
7100				&gcc_usb4_0_tmu_clk_src.clkr.hw,
7101			},
7102			.num_parents = 1,
7103			.flags = CLK_SET_RATE_PARENT,
7104			.ops = &clk_branch2_ops,
7105		},
7106	},
7107};
7108
7109static struct clk_branch gcc_usb4_0_uc_hrr_clk = {
7110	.halt_reg = 0x2b06c,
7111	.halt_check = BRANCH_HALT,
7112	.clkr = {
7113		.enable_reg = 0x2b06c,
7114		.enable_mask = BIT(0),
7115		.hw.init = &(const struct clk_init_data) {
7116			.name = "gcc_usb4_0_uc_hrr_clk",
7117			.parent_hws = (const struct clk_hw*[]) {
7118				&gcc_usb4_0_phy_sys_clk_src.clkr.hw,
7119			},
7120			.num_parents = 1,
7121			.flags = CLK_SET_RATE_PARENT,
7122			.ops = &clk_branch2_ops,
7123		},
7124	},
7125};
7126
7127static struct clk_branch gcc_usb4_1_cfg_ahb_clk = {
7128	.halt_reg = 0xba454,
7129	.halt_check = BRANCH_HALT_VOTED,
7130	.hwcg_reg = 0xba454,
7131	.hwcg_bit = 1,
7132	.clkr = {
7133		.enable_reg = 0xba454,
7134		.enable_mask = BIT(0),
7135		.hw.init = &(const struct clk_init_data) {
7136			.name = "gcc_usb4_1_cfg_ahb_clk",
7137			.ops = &clk_branch2_ops,
7138		},
7139	},
7140};
7141
7142static struct clk_branch gcc_usb4_1_dp0_clk = {
7143	.halt_reg = 0x2d07c,
7144	.halt_check = BRANCH_HALT,
7145	.clkr = {
7146		.enable_reg = 0x2d07c,
7147		.enable_mask = BIT(0),
7148		.hw.init = &(const struct clk_init_data) {
7149			.name = "gcc_usb4_1_dp0_clk",
7150			.parent_hws = (const struct clk_hw*[]) {
7151				&gcc_usb4_1_phy_dp0_clk_src.clkr.hw,
7152			},
7153			.num_parents = 1,
7154			.flags = CLK_SET_RATE_PARENT,
7155			.ops = &clk_branch2_ops,
7156		},
7157	},
7158};
7159
7160static struct clk_branch gcc_usb4_1_dp1_clk = {
7161	.halt_reg = 0x2d144,
7162	.halt_check = BRANCH_HALT,
7163	.clkr = {
7164		.enable_reg = 0x2d144,
7165		.enable_mask = BIT(0),
7166		.hw.init = &(const struct clk_init_data) {
7167			.name = "gcc_usb4_1_dp1_clk",
7168			.parent_hws = (const struct clk_hw*[]) {
7169				&gcc_usb4_1_phy_dp1_clk_src.clkr.hw,
7170			},
7171			.num_parents = 1,
7172			.flags = CLK_SET_RATE_PARENT,
7173			.ops = &clk_branch2_ops,
7174		},
7175	},
7176};
7177
7178static struct clk_branch gcc_usb4_1_master_clk = {
7179	.halt_reg = 0x2d01c,
7180	.halt_check = BRANCH_HALT,
7181	.clkr = {
7182		.enable_reg = 0x2d01c,
7183		.enable_mask = BIT(0),
7184		.hw.init = &(const struct clk_init_data) {
7185			.name = "gcc_usb4_1_master_clk",
7186			.parent_hws = (const struct clk_hw*[]) {
7187				&gcc_usb4_1_master_clk_src.clkr.hw,
7188			},
7189			.num_parents = 1,
7190			.flags = CLK_SET_RATE_PARENT,
7191			.ops = &clk_branch2_ops,
7192		},
7193	},
7194};
7195
7196static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
7197	.halt_reg = 0x2d118,
7198	.halt_check = BRANCH_HALT_SKIP,
7199	.clkr = {
7200		.enable_reg = 0x2d118,
7201		.enable_mask = BIT(0),
7202		.hw.init = &(const struct clk_init_data) {
7203			.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk",
7204			.parent_hws = (const struct clk_hw*[]) {
7205				&gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw,
7206			},
7207			.num_parents = 1,
7208			.flags = CLK_SET_RATE_PARENT,
7209			.ops = &clk_branch2_ops,
7210		},
7211	},
7212};
7213
7214static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
7215	.halt_reg = 0x2d04c,
7216	.halt_check = BRANCH_HALT_SKIP,
7217	.clkr = {
7218		.enable_reg = 0x62010,
7219		.enable_mask = BIT(12),
7220		.hw.init = &(const struct clk_init_data) {
7221			.name = "gcc_usb4_1_phy_pcie_pipe_clk",
7222			.parent_hws = (const struct clk_hw*[]) {
7223				&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
7224			},
7225			.num_parents = 1,
7226			.flags = CLK_SET_RATE_PARENT,
7227			.ops = &clk_branch2_ops,
7228		},
7229	},
7230};
7231
7232static struct clk_branch gcc_usb4_1_phy_rx0_clk = {
7233	.halt_reg = 0x2d0e8,
7234	.halt_check = BRANCH_HALT,
7235	.clkr = {
7236		.enable_reg = 0x2d0e8,
7237		.enable_mask = BIT(0),
7238		.hw.init = &(const struct clk_init_data) {
7239			.name = "gcc_usb4_1_phy_rx0_clk",
7240			.parent_hws = (const struct clk_hw*[]) {
7241				&gcc_usb4_1_phy_rx0_clk_src.clkr.hw,
7242			},
7243			.num_parents = 1,
7244			.flags = CLK_SET_RATE_PARENT,
7245			.ops = &clk_branch2_ops,
7246		},
7247	},
7248};
7249
7250static struct clk_branch gcc_usb4_1_phy_rx1_clk = {
7251	.halt_reg = 0x2d0fc,
7252	.halt_check = BRANCH_HALT,
7253	.clkr = {
7254		.enable_reg = 0x2d0fc,
7255		.enable_mask = BIT(0),
7256		.hw.init = &(const struct clk_init_data) {
7257			.name = "gcc_usb4_1_phy_rx1_clk",
7258			.parent_hws = (const struct clk_hw*[]) {
7259				&gcc_usb4_1_phy_rx1_clk_src.clkr.hw,
7260			},
7261			.num_parents = 1,
7262			.flags = CLK_SET_RATE_PARENT,
7263			.ops = &clk_branch2_ops,
7264		},
7265	},
7266};
7267
7268static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {
7269	.halt_reg = 0x2d0e0,
7270	.halt_check = BRANCH_HALT_SKIP,
7271	.hwcg_reg = 0x2d0e0,
7272	.hwcg_bit = 1,
7273	.clkr = {
7274		.enable_reg = 0x2d0e0,
7275		.enable_mask = BIT(0),
7276		.hw.init = &(const struct clk_init_data) {
7277			.name = "gcc_usb4_1_phy_usb_pipe_clk",
7278			.parent_hws = (const struct clk_hw*[]) {
7279				&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
7280			},
7281			.num_parents = 1,
7282			.flags = CLK_SET_RATE_PARENT,
7283			.ops = &clk_branch2_ops,
7284		},
7285	},
7286};
7287
7288static struct clk_branch gcc_usb4_1_sb_if_clk = {
7289	.halt_reg = 0x2d048,
7290	.halt_check = BRANCH_HALT,
7291	.clkr = {
7292		.enable_reg = 0x2d048,
7293		.enable_mask = BIT(0),
7294		.hw.init = &(const struct clk_init_data) {
7295			.name = "gcc_usb4_1_sb_if_clk",
7296			.parent_hws = (const struct clk_hw*[]) {
7297				&gcc_usb4_1_sb_if_clk_src.clkr.hw,
7298			},
7299			.num_parents = 1,
7300			.flags = CLK_SET_RATE_PARENT,
7301			.ops = &clk_branch2_ops,
7302		},
7303	},
7304};
7305
7306static struct clk_branch gcc_usb4_1_sys_clk = {
7307	.halt_reg = 0x2d05c,
7308	.halt_check = BRANCH_HALT,
7309	.clkr = {
7310		.enable_reg = 0x2d05c,
7311		.enable_mask = BIT(0),
7312		.hw.init = &(const struct clk_init_data) {
7313			.name = "gcc_usb4_1_sys_clk",
7314			.parent_hws = (const struct clk_hw*[]) {
7315				&gcc_usb4_1_phy_sys_clk_src.clkr.hw,
7316			},
7317			.num_parents = 1,
7318			.flags = CLK_SET_RATE_PARENT,
7319			.ops = &clk_branch2_ops,
7320		},
7321	},
7322};
7323
7324static struct clk_branch gcc_usb4_1_tmu_clk = {
7325	.halt_reg = 0x2d0a8,
7326	.halt_check = BRANCH_HALT_VOTED,
7327	.hwcg_reg = 0x2d0a8,
7328	.hwcg_bit = 1,
7329	.clkr = {
7330		.enable_reg = 0x2d0a8,
7331		.enable_mask = BIT(0),
7332		.hw.init = &(const struct clk_init_data) {
7333			.name = "gcc_usb4_1_tmu_clk",
7334			.parent_hws = (const struct clk_hw*[]) {
7335				&gcc_usb4_1_tmu_clk_src.clkr.hw,
7336			},
7337			.num_parents = 1,
7338			.flags = CLK_SET_RATE_PARENT,
7339			.ops = &clk_branch2_ops,
7340		},
7341	},
7342};
7343
7344static struct clk_branch gcc_usb4_1_uc_hrr_clk = {
7345	.halt_reg = 0x2d06c,
7346	.halt_check = BRANCH_HALT,
7347	.clkr = {
7348		.enable_reg = 0x2d06c,
7349		.enable_mask = BIT(0),
7350		.hw.init = &(const struct clk_init_data) {
7351			.name = "gcc_usb4_1_uc_hrr_clk",
7352			.parent_hws = (const struct clk_hw*[]) {
7353				&gcc_usb4_1_phy_sys_clk_src.clkr.hw,
7354			},
7355			.num_parents = 1,
7356			.flags = CLK_SET_RATE_PARENT,
7357			.ops = &clk_branch2_ops,
7358		},
7359	},
7360};
7361
7362static struct clk_branch gcc_usb4_2_cfg_ahb_clk = {
7363	.halt_reg = 0xba458,
7364	.halt_check = BRANCH_HALT_VOTED,
7365	.hwcg_reg = 0xba458,
7366	.hwcg_bit = 1,
7367	.clkr = {
7368		.enable_reg = 0xba458,
7369		.enable_mask = BIT(0),
7370		.hw.init = &(const struct clk_init_data) {
7371			.name = "gcc_usb4_2_cfg_ahb_clk",
7372			.ops = &clk_branch2_ops,
7373		},
7374	},
7375};
7376
7377static struct clk_branch gcc_usb4_2_dp0_clk = {
7378	.halt_reg = 0xe0070,
7379	.halt_check = BRANCH_HALT,
7380	.clkr = {
7381		.enable_reg = 0xe0070,
7382		.enable_mask = BIT(0),
7383		.hw.init = &(const struct clk_init_data) {
7384			.name = "gcc_usb4_2_dp0_clk",
7385			.parent_hws = (const struct clk_hw*[]) {
7386				&gcc_usb4_2_phy_dp0_clk_src.clkr.hw,
7387			},
7388			.num_parents = 1,
7389			.flags = CLK_SET_RATE_PARENT,
7390			.ops = &clk_branch2_ops,
7391		},
7392	},
7393};
7394
7395static struct clk_branch gcc_usb4_2_dp1_clk = {
7396	.halt_reg = 0xe0128,
7397	.halt_check = BRANCH_HALT,
7398	.clkr = {
7399		.enable_reg = 0xe0128,
7400		.enable_mask = BIT(0),
7401		.hw.init = &(const struct clk_init_data) {
7402			.name = "gcc_usb4_2_dp1_clk",
7403			.parent_hws = (const struct clk_hw*[]) {
7404				&gcc_usb4_2_phy_dp1_clk_src.clkr.hw,
7405			},
7406			.num_parents = 1,
7407			.flags = CLK_SET_RATE_PARENT,
7408			.ops = &clk_branch2_ops,
7409		},
7410	},
7411};
7412
7413static struct clk_branch gcc_usb4_2_master_clk = {
7414	.halt_reg = 0xe001c,
7415	.halt_check = BRANCH_HALT,
7416	.clkr = {
7417		.enable_reg = 0xe001c,
7418		.enable_mask = BIT(0),
7419		.hw.init = &(const struct clk_init_data) {
7420			.name = "gcc_usb4_2_master_clk",
7421			.parent_hws = (const struct clk_hw*[]) {
7422				&gcc_usb4_2_master_clk_src.clkr.hw,
7423			},
7424			.num_parents = 1,
7425			.flags = CLK_SET_RATE_PARENT,
7426			.ops = &clk_branch2_ops,
7427		},
7428	},
7429};
7430
7431static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = {
7432	.halt_reg = 0xe00f8,
7433	.halt_check = BRANCH_HALT_SKIP,
7434	.clkr = {
7435		.enable_reg = 0xe00f8,
7436		.enable_mask = BIT(0),
7437		.hw.init = &(const struct clk_init_data) {
7438			.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk",
7439			.parent_hws = (const struct clk_hw*[]) {
7440				&gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr.hw,
7441			},
7442			.num_parents = 1,
7443			.flags = CLK_SET_RATE_PARENT,
7444			.ops = &clk_branch2_ops,
7445		},
7446	},
7447};
7448
7449static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = {
7450	.halt_reg = 0xe004c,
7451	.halt_check = BRANCH_HALT_SKIP,
7452	.clkr = {
7453		.enable_reg = 0x62010,
7454		.enable_mask = BIT(13),
7455		.hw.init = &(const struct clk_init_data) {
7456			.name = "gcc_usb4_2_phy_pcie_pipe_clk",
7457			.parent_hws = (const struct clk_hw*[]) {
7458				&gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
7459			},
7460			.num_parents = 1,
7461			.flags = CLK_SET_RATE_PARENT,
7462			.ops = &clk_branch2_ops,
7463		},
7464	},
7465};
7466
7467static struct clk_branch gcc_usb4_2_phy_rx0_clk = {
7468	.halt_reg = 0xe00c8,
7469	.halt_check = BRANCH_HALT,
7470	.clkr = {
7471		.enable_reg = 0xe00c8,
7472		.enable_mask = BIT(0),
7473		.hw.init = &(const struct clk_init_data) {
7474			.name = "gcc_usb4_2_phy_rx0_clk",
7475			.parent_hws = (const struct clk_hw*[]) {
7476				&gcc_usb4_2_phy_rx0_clk_src.clkr.hw,
7477			},
7478			.num_parents = 1,
7479			.flags = CLK_SET_RATE_PARENT,
7480			.ops = &clk_branch2_ops,
7481		},
7482	},
7483};
7484
7485static struct clk_branch gcc_usb4_2_phy_rx1_clk = {
7486	.halt_reg = 0xe00dc,
7487	.halt_check = BRANCH_HALT,
7488	.clkr = {
7489		.enable_reg = 0xe00dc,
7490		.enable_mask = BIT(0),
7491		.hw.init = &(const struct clk_init_data) {
7492			.name = "gcc_usb4_2_phy_rx1_clk",
7493			.parent_hws = (const struct clk_hw*[]) {
7494				&gcc_usb4_2_phy_rx1_clk_src.clkr.hw,
7495			},
7496			.num_parents = 1,
7497			.flags = CLK_SET_RATE_PARENT,
7498			.ops = &clk_branch2_ops,
7499		},
7500	},
7501};
7502
7503static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = {
7504	.halt_reg = 0xe00c0,
7505	.halt_check = BRANCH_HALT_SKIP,
7506	.hwcg_reg = 0xe00c0,
7507	.hwcg_bit = 1,
7508	.clkr = {
7509		.enable_reg = 0xe00c0,
7510		.enable_mask = BIT(0),
7511		.hw.init = &(const struct clk_init_data) {
7512			.name = "gcc_usb4_2_phy_usb_pipe_clk",
7513			.parent_hws = (const struct clk_hw*[]) {
7514				&gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
7515			},
7516			.num_parents = 1,
7517			.flags = CLK_SET_RATE_PARENT,
7518			.ops = &clk_branch2_ops,
7519		},
7520	},
7521};
7522
7523static struct clk_branch gcc_usb4_2_sb_if_clk = {
7524	.halt_reg = 0xe0048,
7525	.halt_check = BRANCH_HALT,
7526	.clkr = {
7527		.enable_reg = 0xe0048,
7528		.enable_mask = BIT(0),
7529		.hw.init = &(const struct clk_init_data) {
7530			.name = "gcc_usb4_2_sb_if_clk",
7531			.parent_hws = (const struct clk_hw*[]) {
7532				&gcc_usb4_2_sb_if_clk_src.clkr.hw,
7533			},
7534			.num_parents = 1,
7535			.flags = CLK_SET_RATE_PARENT,
7536			.ops = &clk_branch2_ops,
7537		},
7538	},
7539};
7540
7541static struct clk_branch gcc_usb4_2_sys_clk = {
7542	.halt_reg = 0xe005c,
7543	.halt_check = BRANCH_HALT,
7544	.clkr = {
7545		.enable_reg = 0xe005c,
7546		.enable_mask = BIT(0),
7547		.hw.init = &(const struct clk_init_data) {
7548			.name = "gcc_usb4_2_sys_clk",
7549			.parent_hws = (const struct clk_hw*[]) {
7550				&gcc_usb4_2_phy_sys_clk_src.clkr.hw,
7551			},
7552			.num_parents = 1,
7553			.flags = CLK_SET_RATE_PARENT,
7554			.ops = &clk_branch2_ops,
7555		},
7556	},
7557};
7558
7559static struct clk_branch gcc_usb4_2_tmu_clk = {
7560	.halt_reg = 0xe00a0,
7561	.halt_check = BRANCH_HALT_VOTED,
7562	.hwcg_reg = 0xe00a0,
7563	.hwcg_bit = 1,
7564	.clkr = {
7565		.enable_reg = 0xe00a0,
7566		.enable_mask = BIT(0),
7567		.hw.init = &(const struct clk_init_data) {
7568			.name = "gcc_usb4_2_tmu_clk",
7569			.parent_hws = (const struct clk_hw*[]) {
7570				&gcc_usb4_2_tmu_clk_src.clkr.hw,
7571			},
7572			.num_parents = 1,
7573			.flags = CLK_SET_RATE_PARENT,
7574			.ops = &clk_branch2_ops,
7575		},
7576	},
7577};
7578
7579static struct clk_branch gcc_usb4_2_uc_hrr_clk = {
7580	.halt_reg = 0xe006c,
7581	.halt_check = BRANCH_HALT,
7582	.clkr = {
7583		.enable_reg = 0xe006c,
7584		.enable_mask = BIT(0),
7585		.hw.init = &(const struct clk_init_data) {
7586			.name = "gcc_usb4_2_uc_hrr_clk",
7587			.parent_hws = (const struct clk_hw*[]) {
7588				&gcc_usb4_2_phy_sys_clk_src.clkr.hw,
7589			},
7590			.num_parents = 1,
7591			.flags = CLK_SET_RATE_PARENT,
7592			.ops = &clk_branch2_ops,
7593		},
7594	},
7595};
7596
7597static struct clk_branch gcc_video_axi0_clk = {
7598	.halt_reg = 0x3201c,
7599	.halt_check = BRANCH_HALT_SKIP,
7600	.hwcg_reg = 0x3201c,
7601	.hwcg_bit = 1,
7602	.clkr = {
7603		.enable_reg = 0x3201c,
7604		.enable_mask = BIT(0),
7605		.hw.init = &(const struct clk_init_data) {
7606			.name = "gcc_video_axi0_clk",
7607			.ops = &clk_branch2_ops,
7608		},
7609	},
7610};
7611
7612static struct clk_branch gcc_video_axi0c_clk = {
7613	.halt_reg = 0x32030,
7614	.halt_check = BRANCH_HALT_SKIP,
7615	.hwcg_reg = 0x32030,
7616	.hwcg_bit = 1,
7617	.clkr = {
7618		.enable_reg = 0x32030,
7619		.enable_mask = BIT(0),
7620		.hw.init = &(const struct clk_init_data) {
7621			.name = "gcc_video_axi0c_clk",
7622			.ops = &clk_branch2_ops,
7623		},
7624	},
7625};
7626
7627static struct clk_branch gcc_video_axi1_clk = {
7628	.halt_reg = 0x32044,
7629	.halt_check = BRANCH_HALT_SKIP,
7630	.hwcg_reg = 0x32044,
7631	.hwcg_bit = 1,
7632	.clkr = {
7633		.enable_reg = 0x32044,
7634		.enable_mask = BIT(0),
7635		.hw.init = &(const struct clk_init_data) {
7636			.name = "gcc_video_axi1_clk",
7637			.ops = &clk_branch2_ops,
7638		},
7639	},
7640};
7641
7642static struct gdsc gcc_pcie_0_tunnel_gdsc = {
7643	.gdscr = 0xc8004,
7644	.en_rest_wait_val = 0x2,
7645	.en_few_wait_val = 0x2,
7646	.clk_dis_wait_val = 0xf,
7647	.pd = {
7648		.name = "gcc_pcie_0_tunnel_gdsc",
7649	},
7650	.pwrsts = PWRSTS_OFF_ON,
7651	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7652};
7653
7654static struct gdsc gcc_pcie_1_tunnel_gdsc = {
7655	.gdscr = 0x2e004,
7656	.en_rest_wait_val = 0x2,
7657	.en_few_wait_val = 0x2,
7658	.clk_dis_wait_val = 0xf,
7659	.pd = {
7660		.name = "gcc_pcie_1_tunnel_gdsc",
7661	},
7662	.pwrsts = PWRSTS_OFF_ON,
7663	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7664};
7665
7666static struct gdsc gcc_pcie_2_tunnel_gdsc = {
7667	.gdscr = 0xc0004,
7668	.en_rest_wait_val = 0x2,
7669	.en_few_wait_val = 0x2,
7670	.clk_dis_wait_val = 0xf,
7671	.pd = {
7672		.name = "gcc_pcie_2_tunnel_gdsc",
7673	},
7674	.pwrsts = PWRSTS_OFF_ON,
7675	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7676};
7677
7678static struct gdsc gcc_pcie_3a_gdsc = {
7679	.gdscr = 0xdc004,
7680	.en_rest_wait_val = 0x2,
7681	.en_few_wait_val = 0x2,
7682	.clk_dis_wait_val = 0xf,
7683	.pd = {
7684		.name = "gcc_pcie_3a_gdsc",
7685	},
7686	.pwrsts = PWRSTS_OFF_ON,
7687	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7688};
7689
7690static struct gdsc gcc_pcie_3a_phy_gdsc = {
7691	.gdscr = 0x6c004,
7692	.en_rest_wait_val = 0x2,
7693	.en_few_wait_val = 0x2,
7694	.clk_dis_wait_val = 0x2,
7695	.pd = {
7696		.name = "gcc_pcie_3a_phy_gdsc",
7697	},
7698	.pwrsts = PWRSTS_OFF_ON,
7699	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7700};
7701
7702static struct gdsc gcc_pcie_3b_gdsc = {
7703	.gdscr = 0x94004,
7704	.en_rest_wait_val = 0x2,
7705	.en_few_wait_val = 0x2,
7706	.clk_dis_wait_val = 0xf,
7707	.pd = {
7708		.name = "gcc_pcie_3b_gdsc",
7709	},
7710	.pwrsts = PWRSTS_OFF_ON,
7711	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7712};
7713
7714static struct gdsc gcc_pcie_3b_phy_gdsc = {
7715	.gdscr = 0x75004,
7716	.en_rest_wait_val = 0x2,
7717	.en_few_wait_val = 0x2,
7718	.clk_dis_wait_val = 0x2,
7719	.pd = {
7720		.name = "gcc_pcie_3b_phy_gdsc",
7721	},
7722	.pwrsts = PWRSTS_OFF_ON,
7723	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7724};
7725
7726static struct gdsc gcc_pcie_4_gdsc = {
7727	.gdscr = 0x88004,
7728	.en_rest_wait_val = 0x2,
7729	.en_few_wait_val = 0x2,
7730	.clk_dis_wait_val = 0xf,
7731	.pd = {
7732		.name = "gcc_pcie_4_gdsc",
7733	},
7734	.pwrsts = PWRSTS_OFF_ON,
7735	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7736};
7737
7738static struct gdsc gcc_pcie_4_phy_gdsc = {
7739	.gdscr = 0xd3004,
7740	.en_rest_wait_val = 0x2,
7741	.en_few_wait_val = 0x2,
7742	.clk_dis_wait_val = 0x2,
7743	.pd = {
7744		.name = "gcc_pcie_4_phy_gdsc",
7745	},
7746	.pwrsts = PWRSTS_OFF_ON,
7747	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7748};
7749
7750static struct gdsc gcc_pcie_5_gdsc = {
7751	.gdscr = 0xc3004,
7752	.en_rest_wait_val = 0x2,
7753	.en_few_wait_val = 0x2,
7754	.clk_dis_wait_val = 0xf,
7755	.pd = {
7756		.name = "gcc_pcie_5_gdsc",
7757	},
7758	.pwrsts = PWRSTS_OFF_ON,
7759	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7760};
7761
7762static struct gdsc gcc_pcie_5_phy_gdsc = {
7763	.gdscr = 0xd2004,
7764	.en_rest_wait_val = 0x2,
7765	.en_few_wait_val = 0x2,
7766	.clk_dis_wait_val = 0x2,
7767	.pd = {
7768		.name = "gcc_pcie_5_phy_gdsc",
7769	},
7770	.pwrsts = PWRSTS_OFF_ON,
7771	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7772};
7773
7774static struct gdsc gcc_pcie_6_gdsc = {
7775	.gdscr = 0x8a004,
7776	.en_rest_wait_val = 0x2,
7777	.en_few_wait_val = 0x2,
7778	.clk_dis_wait_val = 0xf,
7779	.pd = {
7780		.name = "gcc_pcie_6_gdsc",
7781	},
7782	.pwrsts = PWRSTS_OFF_ON,
7783	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7784};
7785
7786static struct gdsc gcc_pcie_6_phy_gdsc = {
7787	.gdscr = 0xd4004,
7788	.en_rest_wait_val = 0x2,
7789	.en_few_wait_val = 0x2,
7790	.clk_dis_wait_val = 0x2,
7791	.pd = {
7792		.name = "gcc_pcie_6_phy_gdsc",
7793	},
7794	.pwrsts = PWRSTS_OFF_ON,
7795	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
7796};
7797
7798static struct gdsc gcc_ufs_phy_gdsc = {
7799	.gdscr = 0x77008,
7800	.en_rest_wait_val = 0x2,
7801	.en_few_wait_val = 0x2,
7802	.clk_dis_wait_val = 0xf,
7803	.pd = {
7804		.name = "gcc_ufs_phy_gdsc",
7805	},
7806	.pwrsts = PWRSTS_OFF_ON,
7807	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7808};
7809
7810static struct gdsc gcc_usb20_prim_gdsc = {
7811	.gdscr = 0xbc004,
7812	.en_rest_wait_val = 0x2,
7813	.en_few_wait_val = 0x2,
7814	.clk_dis_wait_val = 0xf,
7815	.pd = {
7816		.name = "gcc_usb20_prim_gdsc",
7817	},
7818	.pwrsts = PWRSTS_OFF_ON,
7819	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7820};
7821
7822static struct gdsc gcc_usb30_mp_gdsc = {
7823	.gdscr = 0x9a010,
7824	.en_rest_wait_val = 0x2,
7825	.en_few_wait_val = 0x2,
7826	.clk_dis_wait_val = 0xf,
7827	.pd = {
7828		.name = "gcc_usb30_mp_gdsc",
7829	},
7830	.pwrsts = PWRSTS_OFF_ON,
7831	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7832};
7833
7834static struct gdsc gcc_usb30_prim_gdsc = {
7835	.gdscr = 0x3f01c,
7836	.en_rest_wait_val = 0x2,
7837	.en_few_wait_val = 0x2,
7838	.clk_dis_wait_val = 0xf,
7839	.pd = {
7840		.name = "gcc_usb30_prim_gdsc",
7841	},
7842	.pwrsts = PWRSTS_OFF_ON,
7843	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7844};
7845
7846static struct gdsc gcc_usb30_sec_gdsc = {
7847	.gdscr = 0xe2010,
7848	.en_rest_wait_val = 0x2,
7849	.en_few_wait_val = 0x2,
7850	.clk_dis_wait_val = 0xf,
7851	.pd = {
7852		.name = "gcc_usb30_sec_gdsc",
7853	},
7854	.pwrsts = PWRSTS_OFF_ON,
7855	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7856};
7857
7858static struct gdsc gcc_usb30_tert_gdsc = {
7859	.gdscr = 0xe1010,
7860	.en_rest_wait_val = 0x2,
7861	.en_few_wait_val = 0x2,
7862	.clk_dis_wait_val = 0xf,
7863	.pd = {
7864		.name = "gcc_usb30_tert_gdsc",
7865	},
7866	.pwrsts = PWRSTS_OFF_ON,
7867	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7868};
7869
7870static struct gdsc gcc_usb3_mp_ss0_phy_gdsc = {
7871	.gdscr = 0x5400c,
7872	.en_rest_wait_val = 0x2,
7873	.en_few_wait_val = 0x2,
7874	.clk_dis_wait_val = 0x2,
7875	.pd = {
7876		.name = "gcc_usb3_mp_ss0_phy_gdsc",
7877	},
7878	.pwrsts = PWRSTS_OFF_ON,
7879	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7880};
7881
7882static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = {
7883	.gdscr = 0x5402c,
7884	.en_rest_wait_val = 0x2,
7885	.en_few_wait_val = 0x2,
7886	.clk_dis_wait_val = 0x2,
7887	.pd = {
7888		.name = "gcc_usb3_mp_ss1_phy_gdsc",
7889	},
7890	.pwrsts = PWRSTS_OFF_ON,
7891	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7892};
7893
7894static struct gdsc gcc_usb4_0_gdsc = {
7895	.gdscr = 0x2b008,
7896	.en_rest_wait_val = 0x2,
7897	.en_few_wait_val = 0x2,
7898	.clk_dis_wait_val = 0xf,
7899	.pd = {
7900		.name = "gcc_usb4_0_gdsc",
7901	},
7902	.pwrsts = PWRSTS_OFF_ON,
7903	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7904};
7905
7906static struct gdsc gcc_usb4_1_gdsc = {
7907	.gdscr = 0x2d008,
7908	.en_rest_wait_val = 0x2,
7909	.en_few_wait_val = 0x2,
7910	.clk_dis_wait_val = 0xf,
7911	.pd = {
7912		.name = "gcc_usb4_1_gdsc",
7913	},
7914	.pwrsts = PWRSTS_OFF_ON,
7915	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7916};
7917
7918static struct gdsc gcc_usb4_2_gdsc = {
7919	.gdscr = 0xe0008,
7920	.en_rest_wait_val = 0x2,
7921	.en_few_wait_val = 0x2,
7922	.clk_dis_wait_val = 0xf,
7923	.pd = {
7924		.name = "gcc_usb4_2_gdsc",
7925	},
7926	.pwrsts = PWRSTS_OFF_ON,
7927	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7928};
7929
7930static struct gdsc gcc_usb_0_phy_gdsc = {
7931	.gdscr = 0xdb024,
7932	.en_rest_wait_val = 0x2,
7933	.en_few_wait_val = 0x2,
7934	.clk_dis_wait_val = 0x2,
7935	.pd = {
7936		.name = "gcc_usb_0_phy_gdsc",
7937	},
7938	.pwrsts = PWRSTS_OFF_ON,
7939	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7940};
7941
7942static struct gdsc gcc_usb_1_phy_gdsc = {
7943	.gdscr = 0x2c024,
7944	.en_rest_wait_val = 0x2,
7945	.en_few_wait_val = 0x2,
7946	.clk_dis_wait_val = 0x2,
7947	.pd = {
7948		.name = "gcc_usb_1_phy_gdsc",
7949	},
7950	.pwrsts = PWRSTS_OFF_ON,
7951	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7952};
7953
7954static struct gdsc gcc_usb_2_phy_gdsc = {
7955	.gdscr = 0xbe024,
7956	.en_rest_wait_val = 0x2,
7957	.en_few_wait_val = 0x2,
7958	.clk_dis_wait_val = 0x2,
7959	.pd = {
7960		.name = "gcc_usb_2_phy_gdsc",
7961	},
7962	.pwrsts = PWRSTS_OFF_ON,
7963	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
7964};
7965
7966static struct clk_regmap *gcc_glymur_clocks[] = {
7967	[GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_3a_west_sf_axi_clk.clkr,
7968	[GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_3b_west_sf_axi_clk.clkr,
7969	[GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_4_west_sf_axi_clk.clkr,
7970	[GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_5_east_sf_axi_clk.clkr,
7971	[GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK] = &gcc_aggre_noc_pcie_6_west_sf_axi_clk.clkr,
7972	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
7973	[GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr,
7974	[GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr,
7975	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
7976	[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
7977	[GCC_AGGRE_USB3_TERT_AXI_CLK] = &gcc_aggre_usb3_tert_axi_clk.clkr,
7978	[GCC_AGGRE_USB4_0_AXI_CLK] = &gcc_aggre_usb4_0_axi_clk.clkr,
7979	[GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr,
7980	[GCC_AGGRE_USB4_2_AXI_CLK] = &gcc_aggre_usb4_2_axi_clk.clkr,
7981	[GCC_AV1E_AHB_CLK] = &gcc_av1e_ahb_clk.clkr,
7982	[GCC_AV1E_AXI_CLK] = &gcc_av1e_axi_clk.clkr,
7983	[GCC_AV1E_XO_CLK] = &gcc_av1e_xo_clk.clkr,
7984	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
7985	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
7986	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
7987	[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
7988	[GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_south_ahb_clk.clkr,
7989	[GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr,
7990	[GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
7991	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
7992	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
7993	[GCC_CFG_NOC_USB3_TERT_AXI_CLK] = &gcc_cfg_noc_usb3_tert_axi_clk.clkr,
7994	[GCC_CFG_NOC_USB_ANOC_AHB_CLK] = &gcc_cfg_noc_usb_anoc_ahb_clk.clkr,
7995	[GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_south_ahb_clk.clkr,
7996	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
7997	[GCC_EVA_AHB_CLK] = &gcc_eva_ahb_clk.clkr,
7998	[GCC_EVA_AXI0_CLK] = &gcc_eva_axi0_clk.clkr,
7999	[GCC_EVA_AXI0C_CLK] = &gcc_eva_axi0c_clk.clkr,
8000	[GCC_EVA_XO_CLK] = &gcc_eva_xo_clk.clkr,
8001	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
8002	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
8003	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
8004	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
8005	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
8006	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
8007	[GCC_GPLL0] = &gcc_gpll0.clkr,
8008	[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
8009	[GCC_GPLL1] = &gcc_gpll1.clkr,
8010	[GCC_GPLL14] = &gcc_gpll14.clkr,
8011	[GCC_GPLL14_OUT_EVEN] = &gcc_gpll14_out_even.clkr,
8012	[GCC_GPLL4] = &gcc_gpll4.clkr,
8013	[GCC_GPLL5] = &gcc_gpll5.clkr,
8014	[GCC_GPLL7] = &gcc_gpll7.clkr,
8015	[GCC_GPLL8] = &gcc_gpll8.clkr,
8016	[GCC_GPLL9] = &gcc_gpll9.clkr,
8017	[GCC_GPU_GEMNOC_GFX_CLK] = &gcc_gpu_gemnoc_gfx_clk.clkr,
8018	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
8019	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
8020	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
8021	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
8022	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
8023	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
8024	[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
8025	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
8026	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
8027	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
8028	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
8029	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
8030	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
8031	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
8032	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
8033	[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
8034	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
8035	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
8036	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
8037	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
8038	[GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
8039	[GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,
8040	[GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
8041	[GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
8042	[GCC_PCIE_2_PHY_RCHNG_CLK] = &gcc_pcie_2_phy_rchng_clk.clkr,
8043	[GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr,
8044	[GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
8045	[GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
8046	[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
8047	[GCC_PCIE_3A_AUX_CLK] = &gcc_pcie_3a_aux_clk.clkr,
8048	[GCC_PCIE_3A_AUX_CLK_SRC] = &gcc_pcie_3a_aux_clk_src.clkr,
8049	[GCC_PCIE_3A_CFG_AHB_CLK] = &gcc_pcie_3a_cfg_ahb_clk.clkr,
8050	[GCC_PCIE_3A_MSTR_AXI_CLK] = &gcc_pcie_3a_mstr_axi_clk.clkr,
8051	[GCC_PCIE_3A_PHY_RCHNG_CLK] = &gcc_pcie_3a_phy_rchng_clk.clkr,
8052	[GCC_PCIE_3A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3a_phy_rchng_clk_src.clkr,
8053	[GCC_PCIE_3A_PIPE_CLK] = &gcc_pcie_3a_pipe_clk.clkr,
8054	[GCC_PCIE_3A_PIPE_CLK_SRC] = &gcc_pcie_3a_pipe_clk_src.clkr,
8055	[GCC_PCIE_3A_SLV_AXI_CLK] = &gcc_pcie_3a_slv_axi_clk.clkr,
8056	[GCC_PCIE_3A_SLV_Q2A_AXI_CLK] = &gcc_pcie_3a_slv_q2a_axi_clk.clkr,
8057	[GCC_PCIE_3B_AUX_CLK] = &gcc_pcie_3b_aux_clk.clkr,
8058	[GCC_PCIE_3B_AUX_CLK_SRC] = &gcc_pcie_3b_aux_clk_src.clkr,
8059	[GCC_PCIE_3B_CFG_AHB_CLK] = &gcc_pcie_3b_cfg_ahb_clk.clkr,
8060	[GCC_PCIE_3B_MSTR_AXI_CLK] = &gcc_pcie_3b_mstr_axi_clk.clkr,
8061	[GCC_PCIE_3B_PHY_RCHNG_CLK] = &gcc_pcie_3b_phy_rchng_clk.clkr,
8062	[GCC_PCIE_3B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3b_phy_rchng_clk_src.clkr,
8063	[GCC_PCIE_3B_PIPE_CLK] = &gcc_pcie_3b_pipe_clk.clkr,
8064	[GCC_PCIE_3B_PIPE_CLK_SRC] = &gcc_pcie_3b_pipe_clk_src.clkr,
8065	[GCC_PCIE_3B_PIPE_DIV2_CLK] = &gcc_pcie_3b_pipe_div2_clk.clkr,
8066	[GCC_PCIE_3B_PIPE_DIV_CLK_SRC] = &gcc_pcie_3b_pipe_div_clk_src.clkr,
8067	[GCC_PCIE_3B_SLV_AXI_CLK] = &gcc_pcie_3b_slv_axi_clk.clkr,
8068	[GCC_PCIE_3B_SLV_Q2A_AXI_CLK] = &gcc_pcie_3b_slv_q2a_axi_clk.clkr,
8069	[GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr,
8070	[GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr,
8071	[GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr,
8072	[GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr,
8073	[GCC_PCIE_4_PHY_RCHNG_CLK] = &gcc_pcie_4_phy_rchng_clk.clkr,
8074	[GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr,
8075	[GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr,
8076	[GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr,
8077	[GCC_PCIE_4_PIPE_DIV2_CLK] = &gcc_pcie_4_pipe_div2_clk.clkr,
8078	[GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr,
8079	[GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr,
8080	[GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr,
8081	[GCC_PCIE_5_AUX_CLK] = &gcc_pcie_5_aux_clk.clkr,
8082	[GCC_PCIE_5_AUX_CLK_SRC] = &gcc_pcie_5_aux_clk_src.clkr,
8083	[GCC_PCIE_5_CFG_AHB_CLK] = &gcc_pcie_5_cfg_ahb_clk.clkr,
8084	[GCC_PCIE_5_MSTR_AXI_CLK] = &gcc_pcie_5_mstr_axi_clk.clkr,
8085	[GCC_PCIE_5_PHY_RCHNG_CLK] = &gcc_pcie_5_phy_rchng_clk.clkr,
8086	[GCC_PCIE_5_PHY_RCHNG_CLK_SRC] = &gcc_pcie_5_phy_rchng_clk_src.clkr,
8087	[GCC_PCIE_5_PIPE_CLK] = &gcc_pcie_5_pipe_clk.clkr,
8088	[GCC_PCIE_5_PIPE_CLK_SRC] = &gcc_pcie_5_pipe_clk_src.clkr,
8089	[GCC_PCIE_5_PIPE_DIV2_CLK] = &gcc_pcie_5_pipe_div2_clk.clkr,
8090	[GCC_PCIE_5_PIPE_DIV_CLK_SRC] = &gcc_pcie_5_pipe_div_clk_src.clkr,
8091	[GCC_PCIE_5_SLV_AXI_CLK] = &gcc_pcie_5_slv_axi_clk.clkr,
8092	[GCC_PCIE_5_SLV_Q2A_AXI_CLK] = &gcc_pcie_5_slv_q2a_axi_clk.clkr,
8093	[GCC_PCIE_6_AUX_CLK] = &gcc_pcie_6_aux_clk.clkr,
8094	[GCC_PCIE_6_AUX_CLK_SRC] = &gcc_pcie_6_aux_clk_src.clkr,
8095	[GCC_PCIE_6_CFG_AHB_CLK] = &gcc_pcie_6_cfg_ahb_clk.clkr,
8096	[GCC_PCIE_6_MSTR_AXI_CLK] = &gcc_pcie_6_mstr_axi_clk.clkr,
8097	[GCC_PCIE_6_PHY_RCHNG_CLK] = &gcc_pcie_6_phy_rchng_clk.clkr,
8098	[GCC_PCIE_6_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6_phy_rchng_clk_src.clkr,
8099	[GCC_PCIE_6_PIPE_CLK] = &gcc_pcie_6_pipe_clk.clkr,
8100	[GCC_PCIE_6_PIPE_CLK_SRC] = &gcc_pcie_6_pipe_clk_src.clkr,
8101	[GCC_PCIE_6_PIPE_DIV2_CLK] = &gcc_pcie_6_pipe_div2_clk.clkr,
8102	[GCC_PCIE_6_PIPE_DIV_CLK_SRC] = &gcc_pcie_6_pipe_div_clk_src.clkr,
8103	[GCC_PCIE_6_SLV_AXI_CLK] = &gcc_pcie_6_slv_axi_clk.clkr,
8104	[GCC_PCIE_6_SLV_Q2A_AXI_CLK] = &gcc_pcie_6_slv_q2a_axi_clk.clkr,
8105	[GCC_PCIE_NOC_PWRCTL_CLK] = &gcc_pcie_noc_pwrctl_clk.clkr,
8106	[GCC_PCIE_NOC_QOSGEN_EXTREF_CLK] = &gcc_pcie_noc_qosgen_extref_clk.clkr,
8107	[GCC_PCIE_NOC_SF_CENTER_CLK] = &gcc_pcie_noc_sf_center_clk.clkr,
8108	[GCC_PCIE_NOC_SLAVE_SF_EAST_CLK] = &gcc_pcie_noc_slave_sf_east_clk.clkr,
8109	[GCC_PCIE_NOC_SLAVE_SF_WEST_CLK] = &gcc_pcie_noc_slave_sf_west_clk.clkr,
8110	[GCC_PCIE_NOC_TSCTR_CLK] = &gcc_pcie_noc_tsctr_clk.clkr,
8111	[GCC_PCIE_PHY_3A_AUX_CLK] = &gcc_pcie_phy_3a_aux_clk.clkr,
8112	[GCC_PCIE_PHY_3A_AUX_CLK_SRC] = &gcc_pcie_phy_3a_aux_clk_src.clkr,
8113	[GCC_PCIE_PHY_3B_AUX_CLK] = &gcc_pcie_phy_3b_aux_clk.clkr,
8114	[GCC_PCIE_PHY_3B_AUX_CLK_SRC] = &gcc_pcie_phy_3b_aux_clk_src.clkr,
8115	[GCC_PCIE_PHY_4_AUX_CLK] = &gcc_pcie_phy_4_aux_clk.clkr,
8116	[GCC_PCIE_PHY_4_AUX_CLK_SRC] = &gcc_pcie_phy_4_aux_clk_src.clkr,
8117	[GCC_PCIE_PHY_5_AUX_CLK] = &gcc_pcie_phy_5_aux_clk.clkr,
8118	[GCC_PCIE_PHY_5_AUX_CLK_SRC] = &gcc_pcie_phy_5_aux_clk_src.clkr,
8119	[GCC_PCIE_PHY_6_AUX_CLK] = &gcc_pcie_phy_6_aux_clk.clkr,
8120	[GCC_PCIE_PHY_6_AUX_CLK_SRC] = &gcc_pcie_phy_6_aux_clk_src.clkr,
8121	[GCC_PCIE_RSCC_CFG_AHB_CLK] = &gcc_pcie_rscc_cfg_ahb_clk.clkr,
8122	[GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr,
8123	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
8124	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
8125	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
8126	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
8127	[GCC_QMIP_AV1E_AHB_CLK] = &gcc_qmip_av1e_ahb_clk.clkr,
8128	[GCC_QMIP_CAMERA_CMD_AHB_CLK] = &gcc_qmip_camera_cmd_ahb_clk.clkr,
8129	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
8130	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
8131	[GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
8132	[GCC_QMIP_PCIE_3A_AHB_CLK] = &gcc_qmip_pcie_3a_ahb_clk.clkr,
8133	[GCC_QMIP_PCIE_3B_AHB_CLK] = &gcc_qmip_pcie_3b_ahb_clk.clkr,
8134	[GCC_QMIP_PCIE_4_AHB_CLK] = &gcc_qmip_pcie_4_ahb_clk.clkr,
8135	[GCC_QMIP_PCIE_5_AHB_CLK] = &gcc_qmip_pcie_5_ahb_clk.clkr,
8136	[GCC_QMIP_PCIE_6_AHB_CLK] = &gcc_qmip_pcie_6_ahb_clk.clkr,
8137	[GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
8138	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
8139	[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
8140	[GCC_QMIP_VIDEO_VCODEC1_AHB_CLK] = &gcc_qmip_video_vcodec1_ahb_clk.clkr,
8141	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
8142	[GCC_QUPV3_OOB_CORE_2X_CLK] = &gcc_qupv3_oob_core_2x_clk.clkr,
8143	[GCC_QUPV3_OOB_CORE_CLK] = &gcc_qupv3_oob_core_clk.clkr,
8144	[GCC_QUPV3_OOB_M_AHB_CLK] = &gcc_qupv3_oob_m_ahb_clk.clkr,
8145	[GCC_QUPV3_OOB_QSPI_S0_CLK] = &gcc_qupv3_oob_qspi_s0_clk.clkr,
8146	[GCC_QUPV3_OOB_QSPI_S0_CLK_SRC] = &gcc_qupv3_oob_qspi_s0_clk_src.clkr,
8147	[GCC_QUPV3_OOB_QSPI_S1_CLK] = &gcc_qupv3_oob_qspi_s1_clk.clkr,
8148	[GCC_QUPV3_OOB_QSPI_S1_CLK_SRC] = &gcc_qupv3_oob_qspi_s1_clk_src.clkr,
8149	[GCC_QUPV3_OOB_S0_CLK] = &gcc_qupv3_oob_s0_clk.clkr,
8150	[GCC_QUPV3_OOB_S0_CLK_SRC] = &gcc_qupv3_oob_s0_clk_src.clkr,
8151	[GCC_QUPV3_OOB_S1_CLK] = &gcc_qupv3_oob_s1_clk.clkr,
8152	[GCC_QUPV3_OOB_S1_CLK_SRC] = &gcc_qupv3_oob_s1_clk_src.clkr,
8153	[GCC_QUPV3_OOB_S_AHB_CLK] = &gcc_qupv3_oob_s_ahb_clk.clkr,
8154	[GCC_QUPV3_OOB_TCXO_CLK] = &gcc_qupv3_oob_tcxo_clk.clkr,
8155	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
8156	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
8157	[GCC_QUPV3_WRAP0_QSPI_S2_CLK] = &gcc_qupv3_wrap0_qspi_s2_clk.clkr,
8158	[GCC_QUPV3_WRAP0_QSPI_S2_CLK_SRC] = &gcc_qupv3_wrap0_qspi_s2_clk_src.clkr,
8159	[GCC_QUPV3_WRAP0_QSPI_S3_CLK] = &gcc_qupv3_wrap0_qspi_s3_clk.clkr,
8160	[GCC_QUPV3_WRAP0_QSPI_S3_CLK_SRC] = &gcc_qupv3_wrap0_qspi_s3_clk_src.clkr,
8161	[GCC_QUPV3_WRAP0_QSPI_S6_CLK] = &gcc_qupv3_wrap0_qspi_s6_clk.clkr,
8162	[GCC_QUPV3_WRAP0_QSPI_S6_CLK_SRC] = &gcc_qupv3_wrap0_qspi_s6_clk_src.clkr,
8163	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
8164	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
8165	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
8166	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
8167	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
8168	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
8169	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
8170	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
8171	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
8172	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
8173	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
8174	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
8175	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
8176	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
8177	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
8178	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
8179	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
8180	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
8181	[GCC_QUPV3_WRAP1_QSPI_S2_CLK] = &gcc_qupv3_wrap1_qspi_s2_clk.clkr,
8182	[GCC_QUPV3_WRAP1_QSPI_S2_CLK_SRC] = &gcc_qupv3_wrap1_qspi_s2_clk_src.clkr,
8183	[GCC_QUPV3_WRAP1_QSPI_S3_CLK] = &gcc_qupv3_wrap1_qspi_s3_clk.clkr,
8184	[GCC_QUPV3_WRAP1_QSPI_S3_CLK_SRC] = &gcc_qupv3_wrap1_qspi_s3_clk_src.clkr,
8185	[GCC_QUPV3_WRAP1_QSPI_S6_CLK] = &gcc_qupv3_wrap1_qspi_s6_clk.clkr,
8186	[GCC_QUPV3_WRAP1_QSPI_S6_CLK_SRC] = &gcc_qupv3_wrap1_qspi_s6_clk_src.clkr,
8187	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
8188	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
8189	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
8190	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
8191	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
8192	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
8193	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
8194	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
8195	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
8196	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
8197	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
8198	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
8199	[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
8200	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
8201	[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
8202	[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
8203	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
8204	[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
8205	[GCC_QUPV3_WRAP2_QSPI_S2_CLK] = &gcc_qupv3_wrap2_qspi_s2_clk.clkr,
8206	[GCC_QUPV3_WRAP2_QSPI_S2_CLK_SRC] = &gcc_qupv3_wrap2_qspi_s2_clk_src.clkr,
8207	[GCC_QUPV3_WRAP2_QSPI_S3_CLK] = &gcc_qupv3_wrap2_qspi_s3_clk.clkr,
8208	[GCC_QUPV3_WRAP2_QSPI_S3_CLK_SRC] = &gcc_qupv3_wrap2_qspi_s3_clk_src.clkr,
8209	[GCC_QUPV3_WRAP2_QSPI_S6_CLK] = &gcc_qupv3_wrap2_qspi_s6_clk.clkr,
8210	[GCC_QUPV3_WRAP2_QSPI_S6_CLK_SRC] = &gcc_qupv3_wrap2_qspi_s6_clk_src.clkr,
8211	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
8212	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
8213	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
8214	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
8215	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
8216	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
8217	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
8218	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
8219	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
8220	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
8221	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
8222	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
8223	[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
8224	[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
8225	[GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
8226	[GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
8227	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
8228	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
8229	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
8230	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
8231	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
8232	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
8233	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
8234	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
8235	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
8236	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
8237	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
8238	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
8239	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
8240	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
8241	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
8242	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
8243	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
8244	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
8245	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
8246	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
8247	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
8248	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
8249	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
8250	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
8251	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
8252	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
8253	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
8254	[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
8255	[GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
8256	[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
8257	[GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr,
8258	[GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr,
8259	[GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
8260	[GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr,
8261	[GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr,
8262	[GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr,
8263	[GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr,
8264	[GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr,
8265	[GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr,
8266	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
8267	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
8268	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
8269	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
8270	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
8271	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
8272	[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
8273	[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
8274	[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
8275	[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
8276	[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
8277	[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
8278	[GCC_USB30_TERT_MASTER_CLK] = &gcc_usb30_tert_master_clk.clkr,
8279	[GCC_USB30_TERT_MASTER_CLK_SRC] = &gcc_usb30_tert_master_clk_src.clkr,
8280	[GCC_USB30_TERT_MOCK_UTMI_CLK] = &gcc_usb30_tert_mock_utmi_clk.clkr,
8281	[GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr,
8282	[GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr,
8283	[GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr,
8284	[GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr,
8285	[GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr,
8286	[GCC_USB34_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb34_tert_phy_pipe_clk_src.clkr,
8287	[GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
8288	[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
8289	[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
8290	[GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,
8291	[GCC_USB3_MP_PHY_PIPE_0_CLK_SRC] = &gcc_usb3_mp_phy_pipe_0_clk_src.clkr,
8292	[GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,
8293	[GCC_USB3_MP_PHY_PIPE_1_CLK_SRC] = &gcc_usb3_mp_phy_pipe_1_clk_src.clkr,
8294	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
8295	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
8296	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
8297	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
8298	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
8299	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
8300	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
8301	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
8302	[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
8303	[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
8304	[GCC_USB3_TERT_PHY_AUX_CLK] = &gcc_usb3_tert_phy_aux_clk.clkr,
8305	[GCC_USB3_TERT_PHY_AUX_CLK_SRC] = &gcc_usb3_tert_phy_aux_clk_src.clkr,
8306	[GCC_USB3_TERT_PHY_COM_AUX_CLK] = &gcc_usb3_tert_phy_com_aux_clk.clkr,
8307	[GCC_USB3_TERT_PHY_PIPE_CLK] = &gcc_usb3_tert_phy_pipe_clk.clkr,
8308	[GCC_USB3_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb3_tert_phy_pipe_clk_src.clkr,
8309	[GCC_USB4_0_CFG_AHB_CLK] = &gcc_usb4_0_cfg_ahb_clk.clkr,
8310	[GCC_USB4_0_DP0_CLK] = &gcc_usb4_0_dp0_clk.clkr,
8311	[GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr,
8312	[GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr,
8313	[GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr,
8314	[GCC_USB4_0_PHY_DP0_CLK_SRC] = &gcc_usb4_0_phy_dp0_clk_src.clkr,
8315	[GCC_USB4_0_PHY_DP1_CLK_SRC] = &gcc_usb4_0_phy_dp1_clk_src.clkr,
8316	[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr,
8317	[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr,
8318	[GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr,
8319	[GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr,
8320	[GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr,
8321	[GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr,
8322	[GCC_USB4_0_PHY_RX0_CLK_SRC] = &gcc_usb4_0_phy_rx0_clk_src.clkr,
8323	[GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr,
8324	[GCC_USB4_0_PHY_RX1_CLK_SRC] = &gcc_usb4_0_phy_rx1_clk_src.clkr,
8325	[GCC_USB4_0_PHY_SYS_CLK_SRC] = &gcc_usb4_0_phy_sys_clk_src.clkr,
8326	[GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr,
8327	[GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr,
8328	[GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr,
8329	[GCC_USB4_0_SYS_CLK] = &gcc_usb4_0_sys_clk.clkr,
8330	[GCC_USB4_0_TMU_CLK] = &gcc_usb4_0_tmu_clk.clkr,
8331	[GCC_USB4_0_TMU_CLK_SRC] = &gcc_usb4_0_tmu_clk_src.clkr,
8332	[GCC_USB4_0_UC_HRR_CLK] = &gcc_usb4_0_uc_hrr_clk.clkr,
8333	[GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr,
8334	[GCC_USB4_1_DP0_CLK] = &gcc_usb4_1_dp0_clk.clkr,
8335	[GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr,
8336	[GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr,
8337	[GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr,
8338	[GCC_USB4_1_PHY_DP0_CLK_SRC] = &gcc_usb4_1_phy_dp0_clk_src.clkr,
8339	[GCC_USB4_1_PHY_DP1_CLK_SRC] = &gcc_usb4_1_phy_dp1_clk_src.clkr,
8340	[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr,
8341	[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr,
8342	[GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr,
8343	[GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr,
8344	[GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr,
8345	[GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pll_pipe_clk_src.clkr,
8346	[GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr,
8347	[GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr,
8348	[GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr,
8349	[GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr,
8350	[GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr,
8351	[GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr,
8352	[GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr,
8353	[GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr,
8354	[GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr,
8355	[GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr,
8356	[GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr,
8357	[GCC_USB4_1_UC_HRR_CLK] = &gcc_usb4_1_uc_hrr_clk.clkr,
8358	[GCC_USB4_2_CFG_AHB_CLK] = &gcc_usb4_2_cfg_ahb_clk.clkr,
8359	[GCC_USB4_2_DP0_CLK] = &gcc_usb4_2_dp0_clk.clkr,
8360	[GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr,
8361	[GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr,
8362	[GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr,
8363	[GCC_USB4_2_PHY_DP0_CLK_SRC] = &gcc_usb4_2_phy_dp0_clk_src.clkr,
8364	[GCC_USB4_2_PHY_DP1_CLK_SRC] = &gcc_usb4_2_phy_dp1_clk_src.clkr,
8365	[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr,
8366	[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr,
8367	[GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr,
8368	[GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr,
8369	[GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr,
8370	[GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr,
8371	[GCC_USB4_2_PHY_RX0_CLK_SRC] = &gcc_usb4_2_phy_rx0_clk_src.clkr,
8372	[GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr,
8373	[GCC_USB4_2_PHY_RX1_CLK_SRC] = &gcc_usb4_2_phy_rx1_clk_src.clkr,
8374	[GCC_USB4_2_PHY_SYS_CLK_SRC] = &gcc_usb4_2_phy_sys_clk_src.clkr,
8375	[GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr,
8376	[GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr,
8377	[GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr,
8378	[GCC_USB4_2_SYS_CLK] = &gcc_usb4_2_sys_clk.clkr,
8379	[GCC_USB4_2_TMU_CLK] = &gcc_usb4_2_tmu_clk.clkr,
8380	[GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr,
8381	[GCC_USB4_2_UC_HRR_CLK] = &gcc_usb4_2_uc_hrr_clk.clkr,
8382	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
8383	[GCC_VIDEO_AXI0C_CLK] = &gcc_video_axi0c_clk.clkr,
8384	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
8385};
8386
8387static struct gdsc *gcc_glymur_gdscs[] = {
8388	[GCC_PCIE_0_TUNNEL_GDSC] = &gcc_pcie_0_tunnel_gdsc,
8389	[GCC_PCIE_1_TUNNEL_GDSC] = &gcc_pcie_1_tunnel_gdsc,
8390	[GCC_PCIE_2_TUNNEL_GDSC] = &gcc_pcie_2_tunnel_gdsc,
8391	[GCC_PCIE_3A_GDSC] = &gcc_pcie_3a_gdsc,
8392	[GCC_PCIE_3A_PHY_GDSC] = &gcc_pcie_3a_phy_gdsc,
8393	[GCC_PCIE_3B_GDSC] = &gcc_pcie_3b_gdsc,
8394	[GCC_PCIE_3B_PHY_GDSC] = &gcc_pcie_3b_phy_gdsc,
8395	[GCC_PCIE_4_GDSC] = &gcc_pcie_4_gdsc,
8396	[GCC_PCIE_4_PHY_GDSC] = &gcc_pcie_4_phy_gdsc,
8397	[GCC_PCIE_5_GDSC] = &gcc_pcie_5_gdsc,
8398	[GCC_PCIE_5_PHY_GDSC] = &gcc_pcie_5_phy_gdsc,
8399	[GCC_PCIE_6_GDSC] = &gcc_pcie_6_gdsc,
8400	[GCC_PCIE_6_PHY_GDSC] = &gcc_pcie_6_phy_gdsc,
8401	[GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
8402	[GCC_USB20_PRIM_GDSC] = &gcc_usb20_prim_gdsc,
8403	[GCC_USB30_MP_GDSC] = &gcc_usb30_mp_gdsc,
8404	[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
8405	[GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc,
8406	[GCC_USB30_TERT_GDSC] = &gcc_usb30_tert_gdsc,
8407	[GCC_USB3_MP_SS0_PHY_GDSC] = &gcc_usb3_mp_ss0_phy_gdsc,
8408	[GCC_USB3_MP_SS1_PHY_GDSC] = &gcc_usb3_mp_ss1_phy_gdsc,
8409	[GCC_USB4_0_GDSC] = &gcc_usb4_0_gdsc,
8410	[GCC_USB4_1_GDSC] = &gcc_usb4_1_gdsc,
8411	[GCC_USB4_2_GDSC] = &gcc_usb4_2_gdsc,
8412	[GCC_USB_0_PHY_GDSC] = &gcc_usb_0_phy_gdsc,
8413	[GCC_USB_1_PHY_GDSC] = &gcc_usb_1_phy_gdsc,
8414	[GCC_USB_2_PHY_GDSC] = &gcc_usb_2_phy_gdsc,
8415};
8416
8417static const struct qcom_reset_map gcc_glymur_resets[] = {
8418	[GCC_AV1E_BCR] = { 0x9b028 },
8419	[GCC_CAMERA_BCR] = { 0x26000 },
8420	[GCC_DISPLAY_BCR] = { 0x27000 },
8421	[GCC_EVA_BCR] = { 0x9b000 },
8422	[GCC_GPU_BCR] = { 0x71000 },
8423	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbc2d0 },
8424	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbc2dc },
8425	[GCC_PCIE_0_PHY_BCR] = { 0xbc2d8 },
8426	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbc2e0 },
8427	[GCC_PCIE_0_TUNNEL_BCR] = { 0xc8000 },
8428	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x7f018 },
8429	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x7f024 },
8430	[GCC_PCIE_1_PHY_BCR] = { 0x7f020 },
8431	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x7f028 },
8432	[GCC_PCIE_1_TUNNEL_BCR] = { 0x2e000 },
8433	[GCC_PCIE_2_LINK_DOWN_BCR] = { 0x281d0 },
8434	[GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0x281dc },
8435	[GCC_PCIE_2_PHY_BCR] = { 0x281d8 },
8436	[GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0x281e0 },
8437	[GCC_PCIE_2_TUNNEL_BCR] = { 0xc0000 },
8438	[GCC_PCIE_3A_BCR] = { 0xdc000 },
8439	[GCC_PCIE_3A_LINK_DOWN_BCR] = { 0x7b0a0 },
8440	[GCC_PCIE_3A_NOCSR_COM_PHY_BCR] = { 0x7b0ac },
8441	[GCC_PCIE_3A_PHY_BCR] = { 0x6c000 },
8442	[GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR] = { 0x7b0b0 },
8443	[GCC_PCIE_3B_BCR] = { 0x94000 },
8444	[GCC_PCIE_3B_LINK_DOWN_BCR] = { 0x7a0c0 },
8445	[GCC_PCIE_3B_NOCSR_COM_PHY_BCR] = { 0x7a0cc },
8446	[GCC_PCIE_3B_PHY_BCR] = { 0x75000 },
8447	[GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR] = { 0x7a0c8 },
8448	[GCC_PCIE_4_BCR] = { 0x88000 },
8449	[GCC_PCIE_4_LINK_DOWN_BCR] = { 0x980c0 },
8450	[GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0x980cc },
8451	[GCC_PCIE_4_PHY_BCR] = { 0xd3000 },
8452	[GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0x980d0 },
8453	[GCC_PCIE_5_BCR] = { 0xc3000 },
8454	[GCC_PCIE_5_LINK_DOWN_BCR] = { 0x850c0 },
8455	[GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0x850cc },
8456	[GCC_PCIE_5_PHY_BCR] = { 0xd2000 },
8457	[GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0x850d0 },
8458	[GCC_PCIE_6_BCR] = { 0x8a000 },
8459	[GCC_PCIE_6_LINK_DOWN_BCR] = { 0x3a0b0 },
8460	[GCC_PCIE_6_NOCSR_COM_PHY_BCR] = { 0x3a0bc },
8461	[GCC_PCIE_6_PHY_BCR] = { 0xd4000 },
8462	[GCC_PCIE_6_PHY_NOCSR_COM_PHY_BCR] = { 0x3a0c0 },
8463	[GCC_PCIE_NOC_BCR] = { 0xba294 },
8464	[GCC_PCIE_PHY_BCR] = { 0x6f000 },
8465	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
8466	[GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
8467	[GCC_PCIE_RSCC_BCR] = { 0xb8000 },
8468	[GCC_PDM_BCR] = { 0x33000 },
8469	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x28000 },
8470	[GCC_QUPV3_WRAPPER_1_BCR] = { 0xb3000 },
8471	[GCC_QUPV3_WRAPPER_2_BCR] = { 0xb4000 },
8472	[GCC_QUPV3_WRAPPER_OOB_BCR] = { 0xe7000 },
8473	[GCC_QUSB2PHY_HS0_MP_BCR] = { 0xca000 },
8474	[GCC_QUSB2PHY_HS1_MP_BCR] = { 0xe6000 },
8475	[GCC_QUSB2PHY_PRIM_BCR] = { 0xad024 },
8476	[GCC_QUSB2PHY_SEC_BCR] = { 0xae000 },
8477	[GCC_QUSB2PHY_TERT_BCR] = { 0xc9000 },
8478	[GCC_QUSB2PHY_USB20_HS_BCR] = { 0xe9000 },
8479	[GCC_SDCC2_BCR] = { 0xb0000 },
8480	[GCC_SDCC4_BCR] = { 0xdf000 },
8481	[GCC_TCSR_PCIE_BCR] = { 0x281e4 },
8482	[GCC_UFS_PHY_BCR] = { 0x77004 },
8483	[GCC_USB20_PRIM_BCR] = { 0xbc000 },
8484	[GCC_USB30_MP_BCR] = { 0x9a00c },
8485	[GCC_USB30_PRIM_BCR] = { 0x3f018 },
8486	[GCC_USB30_SEC_BCR] = { 0xe200c },
8487	[GCC_USB30_TERT_BCR] = { 0xe100c },
8488	[GCC_USB3_MP_SS0_PHY_BCR] = { 0x54008 },
8489	[GCC_USB3_MP_SS1_PHY_BCR] = { 0x54028 },
8490	[GCC_USB3_PHY_PRIM_BCR] = { 0xdb000 },
8491	[GCC_USB3_PHY_SEC_BCR] = { 0x2c000 },
8492	[GCC_USB3_PHY_TERT_BCR] = { 0xbe000 },
8493	[GCC_USB3_UNIPHY_MP0_BCR] = { 0x54000 },
8494	[GCC_USB3_UNIPHY_MP1_BCR] = { 0x54020 },
8495	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0xdb004 },
8496	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x2c004 },
8497	[GCC_USB3PHY_PHY_TERT_BCR] = { 0xbe004 },
8498	[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x54004 },
8499	[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54024 },
8500	[GCC_USB4_0_BCR] = { 0x2b004 },
8501	[GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0xdb010 },
8502	[GCC_USB4_1_BCR] = { 0x2d004 },
8503	[GCC_USB4_2_BCR] = { 0xe0004 },
8504	[GCC_USB_0_PHY_BCR] = { 0xdb020 },
8505	[GCC_USB_1_PHY_BCR] = { 0x2c020 },
8506	[GCC_USB_2_PHY_BCR] = { 0xbe020 },
8507	[GCC_VIDEO_AXI0_CLK_ARES] = { 0x3201c, 2 },
8508	[GCC_VIDEO_AXI1_CLK_ARES] = { 0x32044, 2 },
8509	[GCC_VIDEO_BCR] = { 0x32000 },
8510};
8511
8512static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
8513	DEFINE_RCG_DFS(gcc_qupv3_oob_qspi_s0_clk_src),
8514	DEFINE_RCG_DFS(gcc_qupv3_oob_qspi_s1_clk_src),
8515	DEFINE_RCG_DFS(gcc_qupv3_wrap0_qspi_s2_clk_src),
8516	DEFINE_RCG_DFS(gcc_qupv3_wrap0_qspi_s3_clk_src),
8517	DEFINE_RCG_DFS(gcc_qupv3_wrap0_qspi_s6_clk_src),
8518	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
8519	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
8520	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
8521	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
8522	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
8523	DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_s2_clk_src),
8524	DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_s3_clk_src),
8525	DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_s6_clk_src),
8526	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
8527	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
8528	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
8529	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
8530	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
8531	DEFINE_RCG_DFS(gcc_qupv3_wrap2_qspi_s2_clk_src),
8532	DEFINE_RCG_DFS(gcc_qupv3_wrap2_qspi_s3_clk_src),
8533	DEFINE_RCG_DFS(gcc_qupv3_wrap2_qspi_s6_clk_src),
8534	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
8535	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
8536	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
8537	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
8538	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
8539};
8540
8541static u32 gcc_glymur_critical_cbcrs[] = {
8542	0x26004, /* GCC_CAMERA_AHB_CLK */
8543	0x26040, /* GCC_CAMERA_XO_CLK */
8544	0x27004, /* GCC_DISP_AHB_CLK */
8545	0x71004, /* GCC_GPU_CFG_AHB_CLK */
8546	0x32004, /* GCC_VIDEO_AHB_CLK */
8547	0x32058, /* GCC_VIDEO_XO_CLK */
8548};
8549
8550static const struct regmap_config gcc_glymur_regmap_config = {
8551	.reg_bits = 32,
8552	.reg_stride = 4,
8553	.val_bits = 32,
8554	.max_register = 0x1f8ff0,
8555	.fast_io = true,
8556};
8557
8558static void clk_glymur_regs_configure(struct device *dev, struct regmap *regmap)
8559{
8560	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
8561	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
8562}
8563
8564static struct qcom_cc_driver_data gcc_glymur_driver_data = {
8565	.clk_cbcrs = gcc_glymur_critical_cbcrs,
8566	.num_clk_cbcrs = ARRAY_SIZE(gcc_glymur_critical_cbcrs),
8567	.dfs_rcgs = gcc_dfs_clocks,
8568	.num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks),
8569	.clk_regs_configure = clk_glymur_regs_configure,
8570};
8571
8572static const struct qcom_cc_desc gcc_glymur_desc = {
8573	.config = &gcc_glymur_regmap_config,
8574	.clks = gcc_glymur_clocks,
8575	.num_clks = ARRAY_SIZE(gcc_glymur_clocks),
8576	.resets = gcc_glymur_resets,
8577	.num_resets = ARRAY_SIZE(gcc_glymur_resets),
8578	.gdscs = gcc_glymur_gdscs,
8579	.num_gdscs = ARRAY_SIZE(gcc_glymur_gdscs),
8580	.driver_data = &gcc_glymur_driver_data,
8581};
8582
8583static const struct of_device_id gcc_glymur_match_table[] = {
8584	{ .compatible = "qcom,glymur-gcc" },
8585	{ }
8586};
8587MODULE_DEVICE_TABLE(of, gcc_glymur_match_table);
8588
8589static int gcc_glymur_probe(struct platform_device *pdev)
8590{
8591	return qcom_cc_probe(pdev, &gcc_glymur_desc);
8592}
8593
8594static struct platform_driver gcc_glymur_driver = {
8595	.probe = gcc_glymur_probe,
8596	.driver = {
8597		.name = "gcc-glymur",
8598		.of_match_table = gcc_glymur_match_table,
8599	},
8600};
8601
8602static int __init gcc_glymur_init(void)
8603{
8604	return platform_driver_register(&gcc_glymur_driver);
8605}
8606subsys_initcall(gcc_glymur_init);
8607
8608static void __exit gcc_glymur_exit(void)
8609{
8610	platform_driver_unregister(&gcc_glymur_driver);
8611}
8612module_exit(gcc_glymur_exit);
8613
8614MODULE_DESCRIPTION("QTI GCC GLYMUR Driver");
8615MODULE_LICENSE("GPL");