ecpricc-qdu1000.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/mod_devicetable.h>
   8#include <linux/module.h>
   9#include <linux/platform_device.h>
  10#include <linux/regmap.h>
  11
  12#include <dt-bindings/clock/qcom,qdu1000-ecpricc.h>
  13
  14#include "clk-alpha-pll.h"
  15#include "clk-branch.h"
  16#include "clk-rcg.h"
  17#include "clk-regmap.h"
  18#include "clk-regmap-divider.h"
  19#include "clk-regmap-mux.h"
  20#include "common.h"
  21#include "reset.h"
  22
  23enum {
  24	DT_BI_TCXO,
  25	DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN,
  26	DT_GCC_ECPRI_CC_GPLL1_OUT_EVEN,
  27	DT_GCC_ECPRI_CC_GPLL2_OUT_MAIN,
  28	DT_GCC_ECPRI_CC_GPLL3_OUT_MAIN,
  29	DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN,
  30	DT_GCC_ECPRI_CC_GPLL5_OUT_EVEN,
  31};
  32
  33enum {
  34	P_BI_TCXO,
  35	P_ECPRI_CC_PLL0_OUT_MAIN,
  36	P_ECPRI_CC_PLL1_OUT_MAIN,
  37	P_GCC_ECPRI_CC_GPLL0_OUT_MAIN,
  38	P_GCC_ECPRI_CC_GPLL1_OUT_EVEN,
  39	P_GCC_ECPRI_CC_GPLL2_OUT_MAIN,
  40	P_GCC_ECPRI_CC_GPLL3_OUT_MAIN,
  41	P_GCC_ECPRI_CC_GPLL4_OUT_MAIN,
  42	P_GCC_ECPRI_CC_GPLL5_OUT_EVEN,
  43};
  44
  45static const struct pll_vco lucid_evo_vco[] = {
  46	{ 249600000, 2020000000, 0 },
  47};
  48
  49/* 700 MHz configuration */
  50static const struct alpha_pll_config ecpri_cc_pll0_config = {
  51	.l = 0x24,
  52	.alpha = 0x7555,
  53	.config_ctl_val = 0x20485699,
  54	.config_ctl_hi_val = 0x00182261,
  55	.config_ctl_hi1_val = 0x32aa299c,
  56	.user_ctl_val = 0x00000000,
  57	.user_ctl_hi_val = 0x00000805,
  58};
  59
  60static struct clk_alpha_pll ecpri_cc_pll0 = {
  61	.offset = 0x0,
  62	.vco_table = lucid_evo_vco,
  63	.num_vco = ARRAY_SIZE(lucid_evo_vco),
  64	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  65	.clkr = {
  66		.enable_reg = 0x0,
  67		.enable_mask = BIT(0),
  68		.hw.init = &(const struct clk_init_data) {
  69			.name = "ecpri_cc_pll0",
  70			.parent_data = &(const struct clk_parent_data) {
  71				.index = DT_BI_TCXO,
  72			},
  73			.num_parents = 1,
  74			.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
  75		},
  76	},
  77};
  78
  79/* 806 MHz configuration */
  80static const struct alpha_pll_config ecpri_cc_pll1_config = {
  81	.l = 0x29,
  82	.alpha = 0xfaaa,
  83	.config_ctl_val = 0x20485699,
  84	.config_ctl_hi_val = 0x00182261,
  85	.config_ctl_hi1_val = 0x32aa299c,
  86	.user_ctl_val = 0x00000000,
  87	.user_ctl_hi_val = 0x00000805,
  88};
  89
  90static struct clk_alpha_pll ecpri_cc_pll1 = {
  91	.offset = 0x1000,
  92	.vco_table = lucid_evo_vco,
  93	.num_vco = ARRAY_SIZE(lucid_evo_vco),
  94	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  95	.clkr = {
  96		.enable_reg = 0x0,
  97		.enable_mask = BIT(1),
  98		.hw.init = &(const struct clk_init_data) {
  99			.name = "ecpri_cc_pll1",
 100			.parent_data = &(const struct clk_parent_data) {
 101				.index = DT_BI_TCXO,
 102			},
 103			.num_parents = 1,
 104			.ops = &clk_alpha_pll_fixed_lucid_evo_ops,
 105		},
 106	},
 107};
 108
 109static const struct parent_map ecpri_cc_parent_map_0[] = {
 110	{ P_BI_TCXO, 0 },
 111	{ P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1 },
 112	{ P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 2 },
 113	{ P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 3 },
 114	{ P_ECPRI_CC_PLL1_OUT_MAIN, 4 },
 115	{ P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 5 },
 116	{ P_ECPRI_CC_PLL0_OUT_MAIN, 6 },
 117};
 118
 119static const struct clk_parent_data ecpri_cc_parent_data_0[] = {
 120	{ .index = DT_BI_TCXO },
 121	{ .index = DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN },
 122	{ .index = DT_GCC_ECPRI_CC_GPLL2_OUT_MAIN },
 123	{ .index = DT_GCC_ECPRI_CC_GPLL5_OUT_EVEN },
 124	{ .hw = &ecpri_cc_pll1.clkr.hw },
 125	{ .index = DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN },
 126	{ .hw = &ecpri_cc_pll0.clkr.hw },
 127};
 128
 129static const struct parent_map ecpri_cc_parent_map_1[] = {
 130	{ P_BI_TCXO, 0 },
 131	{ P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1 },
 132	{ P_GCC_ECPRI_CC_GPLL1_OUT_EVEN, 2 },
 133	{ P_GCC_ECPRI_CC_GPLL3_OUT_MAIN, 3 },
 134	{ P_ECPRI_CC_PLL1_OUT_MAIN, 4 },
 135	{ P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 5 },
 136	{ P_ECPRI_CC_PLL0_OUT_MAIN, 6 },
 137};
 138
 139static const struct clk_parent_data ecpri_cc_parent_data_1[] = {
 140	{ .index = DT_BI_TCXO },
 141	{ .index = DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN },
 142	{ .index = DT_GCC_ECPRI_CC_GPLL1_OUT_EVEN },
 143	{ .index = DT_GCC_ECPRI_CC_GPLL3_OUT_MAIN },
 144	{ .hw = &ecpri_cc_pll1.clkr.hw },
 145	{ .index = DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN },
 146	{ .hw = &ecpri_cc_pll0.clkr.hw },
 147};
 148
 149static const struct parent_map ecpri_cc_parent_map_2[] = {
 150	{ P_BI_TCXO, 0 },
 151	{ P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1 },
 152	{ P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 3 },
 153	{ P_ECPRI_CC_PLL1_OUT_MAIN, 4 },
 154	{ P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 5 },
 155	{ P_ECPRI_CC_PLL0_OUT_MAIN, 6 },
 156};
 157
 158static const struct clk_parent_data ecpri_cc_parent_data_2[] = {
 159	{ .index = DT_BI_TCXO },
 160	{ .index = DT_GCC_ECPRI_CC_GPLL0_OUT_MAIN },
 161	{ .index = DT_GCC_ECPRI_CC_GPLL5_OUT_EVEN },
 162	{ .hw = &ecpri_cc_pll1.clkr.hw },
 163	{ .index = DT_GCC_ECPRI_CC_GPLL4_OUT_MAIN },
 164	{ .hw = &ecpri_cc_pll0.clkr.hw },
 165};
 166
 167static const struct freq_tbl ftbl_ecpri_cc_ecpri_clk_src[] = {
 168	F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0),
 169	{ }
 170};
 171
 172static struct clk_rcg2 ecpri_cc_ecpri_clk_src = {
 173	.cmd_rcgr = 0x9034,
 174	.mnd_width = 0,
 175	.hid_width = 5,
 176	.parent_map = ecpri_cc_parent_map_2,
 177	.freq_tbl = ftbl_ecpri_cc_ecpri_clk_src,
 178	.clkr.hw.init = &(const struct clk_init_data) {
 179		.name = "ecpri_cc_ecpri_clk_src",
 180		.parent_data = ecpri_cc_parent_data_2,
 181		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_2),
 182		.ops = &clk_rcg2_shared_ops,
 183	},
 184};
 185
 186static const struct freq_tbl ftbl_ecpri_cc_ecpri_dma_clk_src[] = {
 187	F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0),
 188	F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0),
 189	{ }
 190};
 191
 192static struct clk_rcg2 ecpri_cc_ecpri_dma_clk_src = {
 193	.cmd_rcgr = 0x9080,
 194	.mnd_width = 0,
 195	.hid_width = 5,
 196	.parent_map = ecpri_cc_parent_map_0,
 197	.freq_tbl = ftbl_ecpri_cc_ecpri_dma_clk_src,
 198	.clkr.hw.init = &(const struct clk_init_data) {
 199		.name = "ecpri_cc_ecpri_dma_clk_src",
 200		.parent_data = ecpri_cc_parent_data_0,
 201		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),
 202		.ops = &clk_rcg2_shared_ops,
 203	},
 204};
 205
 206static const struct freq_tbl ftbl_ecpri_cc_ecpri_fast_clk_src[] = {
 207	F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0),
 208	F(600000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 1, 0, 0),
 209	{ }
 210};
 211
 212static struct clk_rcg2 ecpri_cc_ecpri_fast_clk_src = {
 213	.cmd_rcgr = 0x904c,
 214	.mnd_width = 0,
 215	.hid_width = 5,
 216	.parent_map = ecpri_cc_parent_map_0,
 217	.freq_tbl = ftbl_ecpri_cc_ecpri_fast_clk_src,
 218	.clkr.hw.init = &(const struct clk_init_data) {
 219		.name = "ecpri_cc_ecpri_fast_clk_src",
 220		.parent_data = ecpri_cc_parent_data_0,
 221		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),
 222		.ops = &clk_rcg2_shared_ops,
 223	},
 224};
 225
 226static const struct freq_tbl ftbl_ecpri_cc_ecpri_oran_clk_src[] = {
 227	F(500000000, P_GCC_ECPRI_CC_GPLL2_OUT_MAIN, 1, 0, 0),
 228	{ }
 229};
 230
 231static struct clk_rcg2 ecpri_cc_ecpri_oran_clk_src = {
 232	.cmd_rcgr = 0x9064,
 233	.mnd_width = 0,
 234	.hid_width = 5,
 235	.parent_map = ecpri_cc_parent_map_0,
 236	.freq_tbl = ftbl_ecpri_cc_ecpri_oran_clk_src,
 237	.clkr.hw.init = &(const struct clk_init_data) {
 238		.name = "ecpri_cc_ecpri_oran_clk_src",
 239		.parent_data = ecpri_cc_parent_data_0,
 240		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),
 241		.ops = &clk_rcg2_shared_ops,
 242	},
 243};
 244
 245static const struct freq_tbl ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src[] = {
 246	F(201500000, P_ECPRI_CC_PLL1_OUT_MAIN, 4, 0, 0),
 247	F(403000000, P_ECPRI_CC_PLL1_OUT_MAIN, 2, 0, 0),
 248	F(466500000, P_GCC_ECPRI_CC_GPLL5_OUT_EVEN, 1, 0, 0),
 249	{ }
 250};
 251
 252static struct clk_rcg2 ecpri_cc_eth_100g_c2c0_hm_ff_clk_src = {
 253	.cmd_rcgr = 0x81b0,
 254	.mnd_width = 0,
 255	.hid_width = 5,
 256	.parent_map = ecpri_cc_parent_map_0,
 257	.freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src,
 258	.clkr.hw.init = &(const struct clk_init_data) {
 259		.name = "ecpri_cc_eth_100g_c2c0_hm_ff_clk_src",
 260		.parent_data = ecpri_cc_parent_data_0,
 261		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),
 262		.ops = &clk_rcg2_shared_ops,
 263	},
 264};
 265
 266static const struct freq_tbl ftbl_ecpri_cc_eth_100g_c2c_hm_macsec_clk_src[] = {
 267	F(100000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 6, 0, 0),
 268	F(200000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 3, 0, 0),
 269	{ }
 270};
 271
 272static struct clk_rcg2 ecpri_cc_eth_100g_c2c_hm_macsec_clk_src = {
 273	.cmd_rcgr = 0x8150,
 274	.mnd_width = 0,
 275	.hid_width = 5,
 276	.parent_map = ecpri_cc_parent_map_0,
 277	.freq_tbl = ftbl_ecpri_cc_eth_100g_c2c_hm_macsec_clk_src,
 278	.clkr.hw.init = &(const struct clk_init_data) {
 279		.name = "ecpri_cc_eth_100g_c2c_hm_macsec_clk_src",
 280		.parent_data = ecpri_cc_parent_data_0,
 281		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),
 282		.ops = &clk_rcg2_shared_ops,
 283	},
 284};
 285
 286static struct clk_rcg2 ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src = {
 287	.cmd_rcgr = 0x81c8,
 288	.mnd_width = 0,
 289	.hid_width = 5,
 290	.parent_map = ecpri_cc_parent_map_0,
 291	.freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src,
 292	.clkr.hw.init = &(const struct clk_init_data) {
 293		.name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src",
 294		.parent_data = ecpri_cc_parent_data_0,
 295		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),
 296		.ops = &clk_rcg2_shared_ops,
 297	},
 298};
 299
 300static struct clk_rcg2 ecpri_cc_eth_100g_fh0_hm_ff_clk_src = {
 301	.cmd_rcgr = 0x8168,
 302	.mnd_width = 0,
 303	.hid_width = 5,
 304	.parent_map = ecpri_cc_parent_map_0,
 305	.freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src,
 306	.clkr.hw.init = &(const struct clk_init_data) {
 307		.name = "ecpri_cc_eth_100g_fh0_hm_ff_clk_src",
 308		.parent_data = ecpri_cc_parent_data_0,
 309		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),
 310		.ops = &clk_rcg2_shared_ops,
 311	},
 312};
 313
 314static struct clk_rcg2 ecpri_cc_eth_100g_fh0_macsec_clk_src = {
 315	.cmd_rcgr = 0x8108,
 316	.mnd_width = 0,
 317	.hid_width = 5,
 318	.parent_map = ecpri_cc_parent_map_0,
 319	.freq_tbl = ftbl_ecpri_cc_eth_100g_c2c_hm_macsec_clk_src,
 320	.clkr.hw.init = &(const struct clk_init_data) {
 321		.name = "ecpri_cc_eth_100g_fh0_macsec_clk_src",
 322		.parent_data = ecpri_cc_parent_data_0,
 323		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),
 324		.ops = &clk_rcg2_shared_ops,
 325	},
 326};
 327
 328static struct clk_rcg2 ecpri_cc_eth_100g_fh1_hm_ff_clk_src = {
 329	.cmd_rcgr = 0x8180,
 330	.mnd_width = 0,
 331	.hid_width = 5,
 332	.parent_map = ecpri_cc_parent_map_0,
 333	.freq_tbl = ftbl_ecpri_cc_ecpri_clk_src,
 334	.clkr.hw.init = &(const struct clk_init_data) {
 335		.name = "ecpri_cc_eth_100g_fh1_hm_ff_clk_src",
 336		.parent_data = ecpri_cc_parent_data_0,
 337		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),
 338		.ops = &clk_rcg2_shared_ops,
 339	},
 340};
 341
 342static const struct freq_tbl ftbl_ecpri_cc_eth_100g_fh1_macsec_clk_src[] = {
 343	F(200000000, P_GCC_ECPRI_CC_GPLL0_OUT_MAIN, 3, 0, 0),
 344	{ }
 345};
 346
 347static struct clk_rcg2 ecpri_cc_eth_100g_fh1_macsec_clk_src = {
 348	.cmd_rcgr = 0x8120,
 349	.mnd_width = 0,
 350	.hid_width = 5,
 351	.parent_map = ecpri_cc_parent_map_0,
 352	.freq_tbl = ftbl_ecpri_cc_eth_100g_fh1_macsec_clk_src,
 353	.clkr.hw.init = &(const struct clk_init_data) {
 354		.name = "ecpri_cc_eth_100g_fh1_macsec_clk_src",
 355		.parent_data = ecpri_cc_parent_data_0,
 356		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),
 357		.ops = &clk_rcg2_shared_ops,
 358	},
 359};
 360
 361static struct clk_rcg2 ecpri_cc_eth_100g_fh2_hm_ff_clk_src = {
 362	.cmd_rcgr = 0x8198,
 363	.mnd_width = 0,
 364	.hid_width = 5,
 365	.parent_map = ecpri_cc_parent_map_0,
 366	.freq_tbl = ftbl_ecpri_cc_eth_100g_c2c0_hm_ff_clk_src,
 367	.clkr.hw.init = &(const struct clk_init_data) {
 368		.name = "ecpri_cc_eth_100g_fh2_hm_ff_clk_src",
 369		.parent_data = ecpri_cc_parent_data_0,
 370		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),
 371		.ops = &clk_rcg2_shared_ops,
 372	},
 373};
 374
 375static struct clk_rcg2 ecpri_cc_eth_100g_fh2_macsec_clk_src = {
 376	.cmd_rcgr = 0x8138,
 377	.mnd_width = 0,
 378	.hid_width = 5,
 379	.parent_map = ecpri_cc_parent_map_0,
 380	.freq_tbl = ftbl_ecpri_cc_eth_100g_fh1_macsec_clk_src,
 381	.clkr.hw.init = &(const struct clk_init_data) {
 382		.name = "ecpri_cc_eth_100g_fh2_macsec_clk_src",
 383		.parent_data = ecpri_cc_parent_data_0,
 384		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_0),
 385		.ops = &clk_rcg2_shared_ops,
 386	},
 387};
 388
 389static const struct freq_tbl ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src[] = {
 390	F(533000000, P_GCC_ECPRI_CC_GPLL1_OUT_EVEN, 1, 0, 0),
 391	F(700000000, P_GCC_ECPRI_CC_GPLL3_OUT_MAIN, 1, 0, 0),
 392	F(806000000, P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 1, 0, 0),
 393	{ }
 394};
 395
 396static struct clk_rcg2 ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src = {
 397	.cmd_rcgr = 0x8228,
 398	.mnd_width = 0,
 399	.hid_width = 5,
 400	.parent_map = ecpri_cc_parent_map_1,
 401	.freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,
 402	.clkr.hw.init = &(const struct clk_init_data) {
 403		.name = "ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src",
 404		.parent_data = ecpri_cc_parent_data_1,
 405		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),
 406		.ops = &clk_rcg2_shared_ops,
 407	},
 408};
 409
 410static struct clk_rcg2 ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src = {
 411	.cmd_rcgr = 0x8240,
 412	.mnd_width = 0,
 413	.hid_width = 5,
 414	.parent_map = ecpri_cc_parent_map_1,
 415	.freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,
 416	.clkr.hw.init = &(const struct clk_init_data) {
 417		.name = "ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src",
 418		.parent_data = ecpri_cc_parent_data_1,
 419		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),
 420		.ops = &clk_rcg2_shared_ops,
 421	},
 422};
 423
 424static struct clk_rcg2 ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src = {
 425	.cmd_rcgr = 0x81e0,
 426	.mnd_width = 0,
 427	.hid_width = 5,
 428	.parent_map = ecpri_cc_parent_map_1,
 429	.freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,
 430	.clkr.hw.init = &(const struct clk_init_data) {
 431		.name = "ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src",
 432		.parent_data = ecpri_cc_parent_data_1,
 433		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),
 434		.ops = &clk_rcg2_shared_ops,
 435	},
 436};
 437
 438static struct clk_rcg2 ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src = {
 439	.cmd_rcgr = 0x81f8,
 440	.mnd_width = 0,
 441	.hid_width = 5,
 442	.parent_map = ecpri_cc_parent_map_1,
 443	.freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,
 444	.clkr.hw.init = &(const struct clk_init_data) {
 445		.name = "ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src",
 446		.parent_data = ecpri_cc_parent_data_1,
 447		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),
 448		.ops = &clk_rcg2_shared_ops,
 449	},
 450};
 451
 452static struct clk_rcg2 ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src = {
 453	.cmd_rcgr = 0x8210,
 454	.mnd_width = 0,
 455	.hid_width = 5,
 456	.parent_map = ecpri_cc_parent_map_1,
 457	.freq_tbl = ftbl_ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src,
 458	.clkr.hw.init = &(const struct clk_init_data) {
 459		.name = "ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src",
 460		.parent_data = ecpri_cc_parent_data_1,
 461		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_1),
 462		.ops = &clk_rcg2_shared_ops,
 463	},
 464};
 465
 466static const struct freq_tbl ftbl_ecpri_cc_mss_emac_clk_src[] = {
 467	F(403000000, P_GCC_ECPRI_CC_GPLL4_OUT_MAIN, 2, 0, 0),
 468	{ }
 469};
 470
 471static struct clk_rcg2 ecpri_cc_mss_emac_clk_src = {
 472	.cmd_rcgr = 0xe00c,
 473	.mnd_width = 0,
 474	.hid_width = 5,
 475	.parent_map = ecpri_cc_parent_map_2,
 476	.freq_tbl = ftbl_ecpri_cc_mss_emac_clk_src,
 477	.clkr.hw.init = &(const struct clk_init_data) {
 478		.name = "ecpri_cc_mss_emac_clk_src",
 479		.parent_data = ecpri_cc_parent_data_2,
 480		.num_parents = ARRAY_SIZE(ecpri_cc_parent_data_2),
 481		.ops = &clk_rcg2_shared_ops,
 482	},
 483};
 484
 485static struct clk_regmap_div ecpri_cc_ecpri_fast_div2_clk_src = {
 486	.reg = 0x907c,
 487	.shift = 0,
 488	.width = 4,
 489	.clkr.hw.init = &(const struct clk_init_data) {
 490		.name = "ecpri_cc_ecpri_fast_div2_clk_src",
 491		.parent_hws = (const struct clk_hw*[]) {
 492			&ecpri_cc_ecpri_fast_clk_src.clkr.hw,
 493		},
 494		.num_parents = 1,
 495		.flags = CLK_SET_RATE_PARENT,
 496		.ops = &clk_regmap_div_ro_ops,
 497	},
 498};
 499
 500static struct clk_regmap_div ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src = {
 501	.reg = 0x8290,
 502	.shift = 0,
 503	.width = 4,
 504	.clkr.hw.init = &(const struct clk_init_data) {
 505		.name = "ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src",
 506		.parent_hws = (const struct clk_hw*[]) {
 507			&ecpri_cc_eth_100g_c2c0_hm_ff_clk_src.clkr.hw,
 508		},
 509		.num_parents = 1,
 510		.flags = CLK_SET_RATE_PARENT,
 511		.ops = &clk_regmap_div_ro_ops,
 512	},
 513};
 514
 515static struct clk_regmap_div ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src = {
 516	.reg = 0x8294,
 517	.shift = 0,
 518	.width = 4,
 519	.clkr.hw.init = &(const struct clk_init_data) {
 520		.name = "ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src",
 521		.parent_hws = (const struct clk_hw*[]) {
 522			&ecpri_cc_eth_100g_c2c0_hm_ff_clk_src.clkr.hw,
 523		},
 524		.num_parents = 1,
 525		.flags = CLK_SET_RATE_PARENT,
 526		.ops = &clk_regmap_div_ro_ops,
 527	},
 528};
 529
 530static struct clk_regmap_div ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src = {
 531	.reg = 0x8298,
 532	.shift = 0,
 533	.width = 4,
 534	.clkr.hw.init = &(const struct clk_init_data) {
 535		.name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src",
 536		.parent_hws = (const struct clk_hw*[]) {
 537			&ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src.clkr.hw,
 538		},
 539		.num_parents = 1,
 540		.flags = CLK_SET_RATE_PARENT,
 541		.ops = &clk_regmap_div_ro_ops,
 542	},
 543};
 544
 545static struct clk_regmap_div ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src = {
 546	.reg = 0x829c,
 547	.shift = 0,
 548	.width = 4,
 549	.clkr.hw.init = &(const struct clk_init_data) {
 550		.name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src",
 551		.parent_hws = (const struct clk_hw*[]) {
 552			&ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src.clkr.hw,
 553		},
 554		.num_parents = 1,
 555		.flags = CLK_SET_RATE_PARENT,
 556		.ops = &clk_regmap_div_ro_ops,
 557	},
 558};
 559
 560static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src = {
 561	.reg = 0x8260,
 562	.shift = 0,
 563	.width = 4,
 564	.clkr.hw.init = &(const struct clk_init_data) {
 565		.name = "ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src",
 566		.parent_hws = (const struct clk_hw*[]) {
 567			&ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw,
 568		},
 569		.num_parents = 1,
 570		.flags = CLK_SET_RATE_PARENT,
 571		.ops = &clk_regmap_div_ro_ops,
 572	},
 573};
 574
 575static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src = {
 576	.reg = 0x8264,
 577	.shift = 0,
 578	.width = 4,
 579	.clkr.hw.init = &(const struct clk_init_data) {
 580		.name = "ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src",
 581		.parent_hws = (const struct clk_hw*[]) {
 582			&ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw,
 583		},
 584		.num_parents = 1,
 585		.flags = CLK_SET_RATE_PARENT,
 586		.ops = &clk_regmap_div_ro_ops,
 587	},
 588};
 589
 590static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src = {
 591	.reg = 0x8268,
 592	.shift = 0,
 593	.width = 4,
 594	.clkr.hw.init = &(const struct clk_init_data) {
 595		.name = "ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src",
 596		.parent_hws = (const struct clk_hw*[]) {
 597			&ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw,
 598		},
 599		.num_parents = 1,
 600		.flags = CLK_SET_RATE_PARENT,
 601		.ops = &clk_regmap_div_ro_ops,
 602	},
 603};
 604
 605static struct clk_regmap_div ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src = {
 606	.reg = 0x826c,
 607	.shift = 0,
 608	.width = 4,
 609	.clkr.hw.init = &(const struct clk_init_data) {
 610		.name = "ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src",
 611		.parent_hws = (const struct clk_hw*[]) {
 612			&ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr.hw,
 613		},
 614		.num_parents = 1,
 615		.flags = CLK_SET_RATE_PARENT,
 616		.ops = &clk_regmap_div_ro_ops,
 617	},
 618};
 619
 620static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src = {
 621	.reg = 0x8270,
 622	.shift = 0,
 623	.width = 4,
 624	.clkr.hw.init = &(const struct clk_init_data) {
 625		.name = "ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src",
 626		.parent_hws = (const struct clk_hw*[]) {
 627			&ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw,
 628		},
 629		.num_parents = 1,
 630		.flags = CLK_SET_RATE_PARENT,
 631		.ops = &clk_regmap_div_ro_ops,
 632	},
 633};
 634
 635static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src = {
 636	.reg = 0x8274,
 637	.shift = 0,
 638	.width = 4,
 639	.clkr.hw.init = &(const struct clk_init_data) {
 640		.name = "ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src",
 641		.parent_hws = (const struct clk_hw*[]) {
 642			&ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw,
 643		},
 644		.num_parents = 1,
 645		.flags = CLK_SET_RATE_PARENT,
 646		.ops = &clk_regmap_div_ro_ops,
 647	},
 648};
 649
 650static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src = {
 651	.reg = 0x8278,
 652	.shift = 0,
 653	.width = 4,
 654	.clkr.hw.init = &(const struct clk_init_data) {
 655		.name = "ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src",
 656		.parent_hws = (const struct clk_hw*[]) {
 657			&ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw,
 658		},
 659		.num_parents = 1,
 660		.flags = CLK_SET_RATE_PARENT,
 661		.ops = &clk_regmap_div_ro_ops,
 662	},
 663};
 664
 665static struct clk_regmap_div ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src = {
 666	.reg = 0x827c,
 667	.shift = 0,
 668	.width = 4,
 669	.clkr.hw.init = &(const struct clk_init_data) {
 670		.name = "ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src",
 671		.parent_hws = (const struct clk_hw*[]) {
 672			&ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr.hw,
 673		},
 674		.num_parents = 1,
 675		.flags = CLK_SET_RATE_PARENT,
 676		.ops = &clk_regmap_div_ro_ops,
 677	},
 678};
 679
 680static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src = {
 681	.reg = 0x8280,
 682	.shift = 0,
 683	.width = 4,
 684	.clkr.hw.init = &(const struct clk_init_data) {
 685		.name = "ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src",
 686		.parent_hws = (const struct clk_hw*[]) {
 687			&ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw,
 688		},
 689		.num_parents = 1,
 690		.flags = CLK_SET_RATE_PARENT,
 691		.ops = &clk_regmap_div_ro_ops,
 692	},
 693};
 694
 695static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src = {
 696	.reg = 0x8284,
 697	.shift = 0,
 698	.width = 4,
 699	.clkr.hw.init = &(const struct clk_init_data) {
 700		.name = "ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src",
 701		.parent_hws = (const struct clk_hw*[]) {
 702			&ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw,
 703		},
 704		.num_parents = 1,
 705		.flags = CLK_SET_RATE_PARENT,
 706		.ops = &clk_regmap_div_ro_ops,
 707	},
 708};
 709
 710static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src = {
 711	.reg = 0x8288,
 712	.shift = 0,
 713	.width = 4,
 714	.clkr.hw.init = &(const struct clk_init_data) {
 715		.name = "ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src",
 716		.parent_hws = (const struct clk_hw*[]) {
 717			&ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw,
 718		},
 719		.num_parents = 1,
 720		.flags = CLK_SET_RATE_PARENT,
 721		.ops = &clk_regmap_div_ro_ops,
 722	},
 723};
 724
 725static struct clk_regmap_div ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src = {
 726	.reg = 0x828c,
 727	.shift = 0,
 728	.width = 4,
 729	.clkr.hw.init = &(const struct clk_init_data) {
 730		.name = "ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src",
 731		.parent_hws = (const struct clk_hw*[]) {
 732			&ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr.hw,
 733		},
 734		.num_parents = 1,
 735		.flags = CLK_SET_RATE_PARENT,
 736		.ops = &clk_regmap_div_ro_ops,
 737	},
 738};
 739
 740static struct clk_branch ecpri_cc_ecpri_cg_clk = {
 741	.halt_reg = 0x900c,
 742	.halt_check = BRANCH_HALT,
 743	.clkr = {
 744		.enable_reg = 0x900c,
 745		.enable_mask = BIT(0),
 746		.hw.init = &(const struct clk_init_data) {
 747			.name = "ecpri_cc_ecpri_cg_clk",
 748			.parent_hws = (const struct clk_hw*[]) {
 749				&ecpri_cc_ecpri_clk_src.clkr.hw,
 750			},
 751			.num_parents = 1,
 752			.flags = CLK_SET_RATE_PARENT,
 753			.ops = &clk_branch2_ops,
 754		},
 755	},
 756};
 757
 758static struct clk_branch ecpri_cc_ecpri_dma_clk = {
 759	.halt_reg = 0x902c,
 760	.halt_check = BRANCH_HALT,
 761	.clkr = {
 762		.enable_reg = 0x902c,
 763		.enable_mask = BIT(0),
 764		.hw.init = &(const struct clk_init_data) {
 765			.name = "ecpri_cc_ecpri_dma_clk",
 766			.parent_hws = (const struct clk_hw*[]) {
 767				&ecpri_cc_ecpri_dma_clk_src.clkr.hw,
 768			},
 769			.num_parents = 1,
 770			.flags = CLK_SET_RATE_PARENT,
 771			.ops = &clk_branch2_ops,
 772		},
 773	},
 774};
 775
 776static struct clk_branch ecpri_cc_ecpri_dma_noc_clk = {
 777	.halt_reg = 0xf004,
 778	.halt_check = BRANCH_HALT,
 779	.clkr = {
 780		.enable_reg = 0xf004,
 781		.enable_mask = BIT(0),
 782		.hw.init = &(const struct clk_init_data) {
 783			.name = "ecpri_cc_ecpri_dma_noc_clk",
 784			.parent_hws = (const struct clk_hw*[]) {
 785				&ecpri_cc_ecpri_dma_clk_src.clkr.hw,
 786			},
 787			.num_parents = 1,
 788			.flags = CLK_SET_RATE_PARENT,
 789			.ops = &clk_branch2_ops,
 790		},
 791	},
 792};
 793
 794static struct clk_branch ecpri_cc_ecpri_fast_clk = {
 795	.halt_reg = 0x9014,
 796	.halt_check = BRANCH_HALT,
 797	.clkr = {
 798		.enable_reg = 0x9014,
 799		.enable_mask = BIT(0),
 800		.hw.init = &(const struct clk_init_data) {
 801			.name = "ecpri_cc_ecpri_fast_clk",
 802			.parent_hws = (const struct clk_hw*[]) {
 803				&ecpri_cc_ecpri_fast_clk_src.clkr.hw,
 804			},
 805			.num_parents = 1,
 806			.flags = CLK_SET_RATE_PARENT,
 807			.ops = &clk_branch2_ops,
 808		},
 809	},
 810};
 811
 812static struct clk_branch ecpri_cc_ecpri_fast_div2_clk = {
 813	.halt_reg = 0x901c,
 814	.halt_check = BRANCH_HALT,
 815	.clkr = {
 816		.enable_reg = 0x901c,
 817		.enable_mask = BIT(0),
 818		.hw.init = &(const struct clk_init_data) {
 819			.name = "ecpri_cc_ecpri_fast_div2_clk",
 820			.parent_hws = (const struct clk_hw*[]) {
 821				&ecpri_cc_ecpri_fast_div2_clk_src.clkr.hw,
 822			},
 823			.num_parents = 1,
 824			.flags = CLK_SET_RATE_PARENT,
 825			.ops = &clk_branch2_ops,
 826		},
 827	},
 828};
 829
 830static struct clk_branch ecpri_cc_ecpri_fast_div2_noc_clk = {
 831	.halt_reg = 0xf008,
 832	.halt_check = BRANCH_HALT,
 833	.clkr = {
 834		.enable_reg = 0xf008,
 835		.enable_mask = BIT(0),
 836		.hw.init = &(const struct clk_init_data) {
 837			.name = "ecpri_cc_ecpri_fast_div2_noc_clk",
 838			.parent_hws = (const struct clk_hw*[]) {
 839				&ecpri_cc_ecpri_fast_div2_clk_src.clkr.hw,
 840			},
 841			.num_parents = 1,
 842			.flags = CLK_SET_RATE_PARENT,
 843			.ops = &clk_branch2_ops,
 844		},
 845	},
 846};
 847
 848static struct clk_branch ecpri_cc_ecpri_fr_clk = {
 849	.halt_reg = 0x9004,
 850	.halt_check = BRANCH_HALT,
 851	.clkr = {
 852		.enable_reg = 0x9004,
 853		.enable_mask = BIT(0),
 854		.hw.init = &(const struct clk_init_data) {
 855			.name = "ecpri_cc_ecpri_fr_clk",
 856			.parent_hws = (const struct clk_hw*[]) {
 857				&ecpri_cc_ecpri_clk_src.clkr.hw,
 858			},
 859			.num_parents = 1,
 860			.flags = CLK_SET_RATE_PARENT,
 861			.ops = &clk_branch2_ops,
 862		},
 863	},
 864};
 865
 866static struct clk_branch ecpri_cc_ecpri_oran_div2_clk = {
 867	.halt_reg = 0x9024,
 868	.halt_check = BRANCH_HALT,
 869	.clkr = {
 870		.enable_reg = 0x9024,
 871		.enable_mask = BIT(0),
 872		.hw.init = &(const struct clk_init_data) {
 873			.name = "ecpri_cc_ecpri_oran_div2_clk",
 874			.parent_hws = (const struct clk_hw*[]) {
 875				&ecpri_cc_ecpri_oran_clk_src.clkr.hw,
 876			},
 877			.num_parents = 1,
 878			.flags = CLK_SET_RATE_PARENT,
 879			.ops = &clk_branch2_ops,
 880		},
 881	},
 882};
 883
 884static struct clk_branch ecpri_cc_eth_100g_c2c0_udp_fifo_clk = {
 885	.halt_reg = 0x80cc,
 886	.halt_check = BRANCH_HALT,
 887	.clkr = {
 888		.enable_reg = 0x80cc,
 889		.enable_mask = BIT(0),
 890		.hw.init = &(const struct clk_init_data) {
 891			.name = "ecpri_cc_eth_100g_c2c0_udp_fifo_clk",
 892			.parent_hws = (const struct clk_hw*[]) {
 893				&ecpri_cc_ecpri_clk_src.clkr.hw,
 894			},
 895			.num_parents = 1,
 896			.flags = CLK_SET_RATE_PARENT,
 897			.ops = &clk_branch2_ops,
 898		},
 899	},
 900};
 901
 902static struct clk_branch ecpri_cc_eth_100g_c2c1_udp_fifo_clk = {
 903	.halt_reg = 0x80d0,
 904	.halt_check = BRANCH_HALT,
 905	.clkr = {
 906		.enable_reg = 0x80d0,
 907		.enable_mask = BIT(0),
 908		.hw.init = &(const struct clk_init_data) {
 909			.name = "ecpri_cc_eth_100g_c2c1_udp_fifo_clk",
 910			.parent_hws = (const struct clk_hw*[]) {
 911				&ecpri_cc_ecpri_clk_src.clkr.hw,
 912			},
 913			.num_parents = 1,
 914			.flags = CLK_SET_RATE_PARENT,
 915			.ops = &clk_branch2_ops,
 916		},
 917	},
 918};
 919
 920static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk = {
 921	.mem_enable_reg = 0x8410,
 922	.mem_ack_reg = 0x8424,
 923	.mem_enable_mask = BIT(0),
 924	.mem_enable_ack_mask = BIT(0),
 925	.branch = {
 926		.halt_reg = 0x80b4,
 927		.halt_check = BRANCH_HALT,
 928		.clkr = {
 929			.enable_reg = 0x80b4,
 930			.enable_mask = BIT(0),
 931			.hw.init = &(const struct clk_init_data) {
 932				.name = "ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk",
 933				.parent_hws = (const struct clk_hw*[]) {
 934					&ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src.clkr.hw,
 935				},
 936				.num_parents = 1,
 937				.flags = CLK_SET_RATE_PARENT,
 938				.ops = &clk_branch2_mem_ops,
 939			},
 940		},
 941	},
 942};
 943
 944static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk = {
 945	.mem_enable_reg = 0x8410,
 946	.mem_ack_reg = 0x8424,
 947	.mem_enable_mask = BIT(1),
 948	.mem_enable_ack_mask = BIT(1),
 949	.branch = {
 950		.halt_reg = 0x80bc,
 951		.halt_check = BRANCH_HALT,
 952		.clkr = {
 953			.enable_reg = 0x80bc,
 954			.enable_mask = BIT(0),
 955			.hw.init = &(const struct clk_init_data) {
 956				.name = "ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk",
 957				.parent_hws = (const struct clk_hw*[]) {
 958					&ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src.clkr.hw,
 959				},
 960				.num_parents = 1,
 961				.flags = CLK_SET_RATE_PARENT,
 962				.ops = &clk_branch2_mem_ops,
 963			},
 964		},
 965	},
 966};
 967
 968static struct clk_mem_branch ecpri_cc_eth_100g_c2c_hm_macsec_clk = {
 969	.mem_enable_reg = 0x8410,
 970	.mem_ack_reg = 0x8424,
 971	.mem_enable_mask = BIT(4),
 972	.mem_enable_ack_mask = BIT(4),
 973	.branch = {
 974		.halt_reg = 0x80ac,
 975		.halt_check = BRANCH_HALT,
 976		.clkr = {
 977			.enable_reg = 0x80ac,
 978			.enable_mask = BIT(0),
 979			.hw.init = &(const struct clk_init_data) {
 980				.name = "ecpri_cc_eth_100g_c2c_hm_macsec_clk",
 981				.parent_hws = (const struct clk_hw*[]) {
 982					&ecpri_cc_eth_100g_c2c_hm_macsec_clk_src.clkr.hw,
 983				},
 984				.num_parents = 1,
 985				.flags = CLK_SET_RATE_PARENT,
 986				.ops = &clk_branch2_mem_ops,
 987			},
 988		},
 989	},
 990};
 991
 992static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk = {
 993	.mem_enable_reg = 0x8414,
 994	.mem_ack_reg = 0x8428,
 995	.mem_enable_mask = BIT(0),
 996	.mem_enable_ack_mask = BIT(0),
 997	.branch = {
 998		.halt_reg = 0x80d8,
 999		.halt_check = BRANCH_HALT,
1000		.clkr = {
1001			.enable_reg = 0x80d8,
1002			.enable_mask = BIT(0),
1003			.hw.init = &(const struct clk_init_data) {
1004				.name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk",
1005				.parent_hws = (const struct clk_hw*[]) {
1006					&ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src.clkr.hw,
1007				},
1008				.num_parents = 1,
1009				.flags = CLK_SET_RATE_PARENT,
1010				.ops = &clk_branch2_mem_ops,
1011			},
1012		},
1013	},
1014};
1015
1016static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk = {
1017	.mem_enable_reg = 0x8414,
1018	.mem_ack_reg = 0x8428,
1019	.mem_enable_mask = BIT(1),
1020	.mem_enable_ack_mask = BIT(1),
1021	.branch = {
1022		.halt_reg = 0x80e0,
1023		.halt_check = BRANCH_HALT,
1024		.clkr = {
1025			.enable_reg = 0x80e0,
1026			.enable_mask = BIT(0),
1027			.hw.init = &(const struct clk_init_data) {
1028				.name = "ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk",
1029				.parent_hws = (const struct clk_hw*[]) {
1030					&ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src.clkr.hw,
1031				},
1032				.num_parents = 1,
1033				.flags = CLK_SET_RATE_PARENT,
1034				.ops = &clk_branch2_mem_ops,
1035			},
1036		},
1037	},
1038};
1039
1040static struct clk_branch ecpri_cc_eth_100g_dbg_c2c_udp_fifo_clk = {
1041	.halt_reg = 0x80f0,
1042	.halt_check = BRANCH_HALT,
1043	.clkr = {
1044		.enable_reg = 0x80f0,
1045		.enable_mask = BIT(0),
1046		.hw.init = &(const struct clk_init_data) {
1047			.name = "ecpri_cc_eth_100g_dbg_c2c_udp_fifo_clk",
1048			.parent_hws = (const struct clk_hw*[]) {
1049				&ecpri_cc_ecpri_clk_src.clkr.hw,
1050			},
1051			.num_parents = 1,
1052			.flags = CLK_SET_RATE_PARENT,
1053			.ops = &clk_branch2_ops,
1054		},
1055	},
1056};
1057
1058static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_0_clk = {
1059	.mem_enable_reg = 0x8404,
1060	.mem_ack_reg = 0x8418,
1061	.mem_enable_mask = BIT(0),
1062	.mem_enable_ack_mask = BIT(0),
1063	.branch = {
1064		.halt_reg = 0x800c,
1065		.halt_check = BRANCH_HALT,
1066		.clkr = {
1067			.enable_reg = 0x800c,
1068			.enable_mask = BIT(0),
1069			.hw.init = &(const struct clk_init_data) {
1070				.name = "ecpri_cc_eth_100g_fh_0_hm_ff_0_clk",
1071				.parent_hws = (const struct clk_hw*[]) {
1072					&ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src.clkr.hw,
1073				},
1074				.num_parents = 1,
1075				.flags = CLK_SET_RATE_PARENT,
1076				.ops = &clk_branch2_mem_ops,
1077			},
1078		},
1079	},
1080};
1081
1082static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_1_clk = {
1083	.mem_enable_reg = 0x8404,
1084	.mem_ack_reg = 0x8418,
1085	.mem_enable_mask = BIT(1),
1086	.mem_enable_ack_mask = BIT(1),
1087	.branch = {
1088		.halt_reg = 0x8014,
1089		.halt_check = BRANCH_HALT,
1090		.clkr = {
1091			.enable_reg = 0x8014,
1092			.enable_mask = BIT(0),
1093			.hw.init = &(const struct clk_init_data) {
1094				.name = "ecpri_cc_eth_100g_fh_0_hm_ff_1_clk",
1095				.parent_hws = (const struct clk_hw*[]) {
1096					&ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src.clkr.hw,
1097				},
1098				.num_parents = 1,
1099				.flags = CLK_SET_RATE_PARENT,
1100				.ops = &clk_branch2_mem_ops,
1101			},
1102		},
1103	},
1104};
1105
1106static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_2_clk = {
1107	.mem_enable_reg = 0x8404,
1108	.mem_ack_reg = 0x8418,
1109	.mem_enable_mask = BIT(2),
1110	.mem_enable_ack_mask = BIT(2),
1111	.branch = {
1112		.halt_reg = 0x801c,
1113		.halt_check = BRANCH_HALT,
1114		.clkr = {
1115			.enable_reg = 0x801c,
1116			.enable_mask = BIT(0),
1117			.hw.init = &(const struct clk_init_data) {
1118				.name = "ecpri_cc_eth_100g_fh_0_hm_ff_2_clk",
1119				.parent_hws = (const struct clk_hw*[]) {
1120					&ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src.clkr.hw,
1121				},
1122				.num_parents = 1,
1123				.flags = CLK_SET_RATE_PARENT,
1124				.ops = &clk_branch2_mem_ops,
1125			},
1126		},
1127	},
1128};
1129
1130static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_3_clk = {
1131	.mem_enable_reg = 0x8404,
1132	.mem_ack_reg = 0x8418,
1133	.mem_enable_mask = BIT(3),
1134	.mem_enable_ack_mask = BIT(3),
1135	.branch = {
1136		.halt_reg = 0x8024,
1137		.halt_check = BRANCH_HALT,
1138		.clkr = {
1139			.enable_reg = 0x8024,
1140			.enable_mask = BIT(0),
1141			.hw.init = &(const struct clk_init_data) {
1142				.name = "ecpri_cc_eth_100g_fh_0_hm_ff_3_clk",
1143				.parent_hws = (const struct clk_hw*[]) {
1144					&ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src.clkr.hw,
1145				},
1146				.num_parents = 1,
1147				.flags = CLK_SET_RATE_PARENT,
1148				.ops = &clk_branch2_mem_ops,
1149			},
1150		},
1151	},
1152};
1153
1154static struct clk_branch ecpri_cc_eth_100g_fh_0_udp_fifo_clk = {
1155	.halt_reg = 0x8034,
1156	.halt_check = BRANCH_HALT,
1157	.clkr = {
1158		.enable_reg = 0x8034,
1159		.enable_mask = BIT(0),
1160		.hw.init = &(const struct clk_init_data) {
1161			.name = "ecpri_cc_eth_100g_fh_0_udp_fifo_clk",
1162			.parent_hws = (const struct clk_hw*[]) {
1163				&ecpri_cc_ecpri_clk_src.clkr.hw,
1164			},
1165			.num_parents = 1,
1166			.flags = CLK_SET_RATE_PARENT,
1167			.ops = &clk_branch2_ops,
1168		},
1169	},
1170};
1171
1172static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_0_clk = {
1173	.mem_enable_reg = 0x8408,
1174	.mem_ack_reg = 0x841c,
1175	.mem_enable_mask = BIT(0),
1176	.mem_enable_ack_mask = BIT(0),
1177	.branch = {
1178		.halt_reg = 0x8044,
1179		.halt_check = BRANCH_HALT,
1180		.clkr = {
1181			.enable_reg = 0x8044,
1182			.enable_mask = BIT(0),
1183			.hw.init = &(const struct clk_init_data) {
1184				.name = "ecpri_cc_eth_100g_fh_1_hm_ff_0_clk",
1185				.parent_hws = (const struct clk_hw*[]) {
1186					&ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src.clkr.hw,
1187				},
1188				.num_parents = 1,
1189				.flags = CLK_SET_RATE_PARENT,
1190				.ops = &clk_branch2_mem_ops,
1191			},
1192		},
1193	},
1194};
1195
1196static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_1_clk = {
1197	.mem_enable_reg = 0x8408,
1198	.mem_ack_reg = 0x841c,
1199	.mem_enable_mask = BIT(1),
1200	.mem_enable_ack_mask = BIT(1),
1201	.branch = {
1202		.halt_reg = 0x804c,
1203		.halt_check = BRANCH_HALT,
1204		.clkr = {
1205			.enable_reg = 0x804c,
1206			.enable_mask = BIT(0),
1207			.hw.init = &(const struct clk_init_data) {
1208				.name = "ecpri_cc_eth_100g_fh_1_hm_ff_1_clk",
1209				.parent_hws = (const struct clk_hw*[]) {
1210					&ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src.clkr.hw,
1211				},
1212				.num_parents = 1,
1213				.flags = CLK_SET_RATE_PARENT,
1214				.ops = &clk_branch2_mem_ops,
1215			},
1216		},
1217	},
1218};
1219
1220static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_2_clk = {
1221	.mem_enable_reg = 0x8408,
1222	.mem_ack_reg = 0x841c,
1223	.mem_enable_mask = BIT(2),
1224	.mem_enable_ack_mask = BIT(2),
1225	.branch = {
1226		.halt_reg = 0x8054,
1227		.halt_check = BRANCH_HALT,
1228		.clkr = {
1229			.enable_reg = 0x8054,
1230			.enable_mask = BIT(0),
1231			.hw.init = &(const struct clk_init_data) {
1232				.name = "ecpri_cc_eth_100g_fh_1_hm_ff_2_clk",
1233				.parent_hws = (const struct clk_hw*[]) {
1234					&ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src.clkr.hw,
1235				},
1236				.num_parents = 1,
1237				.flags = CLK_SET_RATE_PARENT,
1238				.ops = &clk_branch2_mem_ops,
1239			},
1240		},
1241	},
1242};
1243
1244static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_3_clk = {
1245	.mem_enable_reg = 0x8408,
1246	.mem_ack_reg = 0x841c,
1247	.mem_enable_mask = BIT(3),
1248	.mem_enable_ack_mask = BIT(3),
1249	.branch = {
1250		.halt_reg = 0x805c,
1251		.halt_check = BRANCH_HALT,
1252		.clkr = {
1253			.enable_reg = 0x805c,
1254			.enable_mask = BIT(0),
1255			.hw.init = &(const struct clk_init_data) {
1256				.name = "ecpri_cc_eth_100g_fh_1_hm_ff_3_clk",
1257				.parent_hws = (const struct clk_hw*[]) {
1258					&ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src.clkr.hw,
1259				},
1260				.num_parents = 1,
1261				.flags = CLK_SET_RATE_PARENT,
1262				.ops = &clk_branch2_mem_ops,
1263			},
1264		},
1265	},
1266};
1267
1268static struct clk_branch ecpri_cc_eth_100g_fh_1_udp_fifo_clk = {
1269	.halt_reg = 0x806c,
1270	.halt_check = BRANCH_HALT,
1271	.clkr = {
1272		.enable_reg = 0x806c,
1273		.enable_mask = BIT(0),
1274		.hw.init = &(const struct clk_init_data) {
1275			.name = "ecpri_cc_eth_100g_fh_1_udp_fifo_clk",
1276			.parent_hws = (const struct clk_hw*[]) {
1277				&ecpri_cc_ecpri_clk_src.clkr.hw,
1278			},
1279			.num_parents = 1,
1280			.flags = CLK_SET_RATE_PARENT,
1281			.ops = &clk_branch2_ops,
1282		},
1283	},
1284};
1285
1286static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_0_clk = {
1287	.mem_enable_reg = 0x840c,
1288	.mem_ack_reg = 0x8420,
1289	.mem_enable_mask = BIT(0),
1290	.mem_enable_ack_mask = BIT(0),
1291	.branch = {
1292		.halt_reg = 0x807c,
1293		.halt_check = BRANCH_HALT,
1294		.clkr = {
1295			.enable_reg = 0x807c,
1296			.enable_mask = BIT(0),
1297			.hw.init = &(const struct clk_init_data) {
1298				.name = "ecpri_cc_eth_100g_fh_2_hm_ff_0_clk",
1299				.parent_hws = (const struct clk_hw*[]) {
1300					&ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src.clkr.hw,
1301				},
1302				.num_parents = 1,
1303				.flags = CLK_SET_RATE_PARENT,
1304				.ops = &clk_branch2_mem_ops,
1305			},
1306		},
1307	},
1308};
1309
1310static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_1_clk = {
1311	.mem_enable_reg = 0x840c,
1312	.mem_ack_reg = 0x8420,
1313	.mem_enable_mask = BIT(1),
1314	.mem_enable_ack_mask = BIT(1),
1315	.branch = {
1316		.halt_reg = 0x8084,
1317		.halt_check = BRANCH_HALT,
1318		.clkr = {
1319			.enable_reg = 0x8084,
1320			.enable_mask = BIT(0),
1321			.hw.init = &(const struct clk_init_data) {
1322				.name = "ecpri_cc_eth_100g_fh_2_hm_ff_1_clk",
1323				.parent_hws = (const struct clk_hw*[]) {
1324					&ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src.clkr.hw,
1325				},
1326				.num_parents = 1,
1327				.flags = CLK_SET_RATE_PARENT,
1328				.ops = &clk_branch2_mem_ops,
1329			},
1330		},
1331	},
1332};
1333
1334static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_2_clk = {
1335	.mem_enable_reg = 0x840c,
1336	.mem_ack_reg = 0x8420,
1337	.mem_enable_mask = BIT(2),
1338	.mem_enable_ack_mask = BIT(2),
1339	.branch = {
1340		.halt_reg = 0x808c,
1341		.halt_check = BRANCH_HALT,
1342		.clkr = {
1343			.enable_reg = 0x808c,
1344			.enable_mask = BIT(0),
1345			.hw.init = &(const struct clk_init_data) {
1346				.name = "ecpri_cc_eth_100g_fh_2_hm_ff_2_clk",
1347				.parent_hws = (const struct clk_hw*[]) {
1348					&ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src.clkr.hw,
1349				},
1350				.num_parents = 1,
1351				.flags = CLK_SET_RATE_PARENT,
1352				.ops = &clk_branch2_mem_ops,
1353			},
1354		},
1355	},
1356};
1357
1358static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_3_clk = {
1359	.mem_enable_reg = 0x840c,
1360	.mem_ack_reg = 0x8420,
1361	.mem_enable_mask = BIT(3),
1362	.mem_enable_ack_mask = BIT(3),
1363	.branch = {
1364		.halt_reg = 0x8094,
1365		.halt_check = BRANCH_HALT,
1366		.clkr = {
1367			.enable_reg = 0x8094,
1368			.enable_mask = BIT(0),
1369			.hw.init = &(const struct clk_init_data) {
1370				.name = "ecpri_cc_eth_100g_fh_2_hm_ff_3_clk",
1371				.parent_hws = (const struct clk_hw*[]) {
1372					&ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src.clkr.hw,
1373				},
1374				.num_parents = 1,
1375				.flags = CLK_SET_RATE_PARENT,
1376				.ops = &clk_branch2_mem_ops,
1377			},
1378		},
1379	},
1380};
1381
1382static struct clk_branch ecpri_cc_eth_100g_fh_2_udp_fifo_clk = {
1383	.halt_reg = 0x80a4,
1384	.halt_check = BRANCH_HALT,
1385	.clkr = {
1386		.enable_reg = 0x80a4,
1387		.enable_mask = BIT(0),
1388		.hw.init = &(const struct clk_init_data) {
1389			.name = "ecpri_cc_eth_100g_fh_2_udp_fifo_clk",
1390			.parent_hws = (const struct clk_hw*[]) {
1391				&ecpri_cc_ecpri_clk_src.clkr.hw,
1392			},
1393			.num_parents = 1,
1394			.flags = CLK_SET_RATE_PARENT,
1395			.ops = &clk_branch2_ops,
1396		},
1397	},
1398};
1399
1400static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_0_clk = {
1401	.mem_enable_reg = 0x8404,
1402	.mem_ack_reg = 0x8418,
1403	.mem_enable_mask = BIT(4),
1404	.mem_enable_ack_mask = BIT(4),
1405	.branch = {
1406		.halt_reg = 0x8004,
1407		.halt_check = BRANCH_HALT,
1408		.clkr = {
1409			.enable_reg = 0x8004,
1410			.enable_mask = BIT(0),
1411			.hw.init = &(const struct clk_init_data) {
1412				.name = "ecpri_cc_eth_100g_fh_macsec_0_clk",
1413				.parent_hws = (const struct clk_hw*[]) {
1414					&ecpri_cc_eth_100g_fh0_macsec_clk_src.clkr.hw,
1415				},
1416				.num_parents = 1,
1417				.flags = CLK_SET_RATE_PARENT,
1418				.ops = &clk_branch2_mem_ops,
1419			},
1420		},
1421	},
1422};
1423
1424static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_1_clk = {
1425	.mem_enable_reg = 0x8408,
1426	.mem_ack_reg = 0x841c,
1427	.mem_enable_mask = BIT(4),
1428	.mem_enable_ack_mask = BIT(4),
1429	.branch = {
1430		.halt_reg = 0x803c,
1431		.halt_check = BRANCH_HALT,
1432		.clkr = {
1433			.enable_reg = 0x803c,
1434			.enable_mask = BIT(0),
1435			.hw.init = &(const struct clk_init_data) {
1436				.name = "ecpri_cc_eth_100g_fh_macsec_1_clk",
1437				.parent_hws = (const struct clk_hw*[]) {
1438					&ecpri_cc_eth_100g_fh1_macsec_clk_src.clkr.hw,
1439				},
1440				.num_parents = 1,
1441				.flags = CLK_SET_RATE_PARENT,
1442				.ops = &clk_branch2_mem_ops,
1443			},
1444		},
1445	},
1446};
1447
1448static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_2_clk = {
1449	.mem_enable_reg = 0x840c,
1450	.mem_ack_reg = 0x8420,
1451	.mem_enable_mask = BIT(4),
1452	.mem_enable_ack_mask = BIT(4),
1453	.branch = {
1454		.halt_reg = 0x8074,
1455		.halt_check = BRANCH_HALT,
1456		.clkr = {
1457			.enable_reg = 0x8074,
1458			.enable_mask = BIT(0),
1459			.hw.init = &(const struct clk_init_data) {
1460				.name = "ecpri_cc_eth_100g_fh_macsec_2_clk",
1461				.parent_hws = (const struct clk_hw*[]) {
1462					&ecpri_cc_eth_100g_fh2_macsec_clk_src.clkr.hw,
1463				},
1464				.num_parents = 1,
1465				.flags = CLK_SET_RATE_PARENT,
1466				.ops = &clk_branch2_mem_ops,
1467			},
1468		},
1469	},
1470};
1471
1472static struct clk_mem_branch ecpri_cc_eth_100g_mac_c2c_hm_ref_clk = {
1473	.mem_enable_reg = 0x8410,
1474	.mem_ack_reg = 0x8424,
1475	.mem_enable_mask = BIT(5),
1476	.mem_enable_ack_mask = BIT(5),
1477	.branch = {
1478		.halt_reg = 0x80c4,
1479		.halt_check = BRANCH_HALT,
1480		.clkr = {
1481			.enable_reg = 0x80c4,
1482			.enable_mask = BIT(0),
1483			.hw.init = &(const struct clk_init_data) {
1484				.name = "ecpri_cc_eth_100g_mac_c2c_hm_ref_clk",
1485				.parent_hws = (const struct clk_hw*[]) {
1486					&ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src.clkr.hw,
1487				},
1488				.num_parents = 1,
1489				.flags = CLK_SET_RATE_PARENT,
1490				.ops = &clk_branch2_mem_ops,
1491			},
1492		},
1493	},
1494};
1495
1496static struct clk_mem_branch ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk = {
1497	.mem_enable_reg = 0x8414,
1498	.mem_ack_reg = 0x8428,
1499	.mem_enable_mask = BIT(5),
1500	.mem_enable_ack_mask = BIT(5),
1501	.branch = {
1502		.halt_reg = 0x80e8,
1503		.halt_check = BRANCH_HALT,
1504		.clkr = {
1505			.enable_reg = 0x80e8,
1506			.enable_mask = BIT(0),
1507			.hw.init = &(const struct clk_init_data) {
1508				.name = "ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk",
1509				.parent_hws = (const struct clk_hw*[]) {
1510					&ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src.clkr.hw,
1511				},
1512				.num_parents = 1,
1513				.flags = CLK_SET_RATE_PARENT,
1514				.ops = &clk_branch2_mem_ops,
1515			},
1516		},
1517	},
1518};
1519
1520static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh0_hm_ref_clk = {
1521	.mem_enable_reg = 0x8404,
1522	.mem_ack_reg = 0x8418,
1523	.mem_enable_mask = BIT(5),
1524	.mem_enable_ack_mask = BIT(5),
1525	.branch = {
1526		.halt_reg = 0x802c,
1527		.halt_check = BRANCH_HALT,
1528		.clkr = {
1529			.enable_reg = 0x802c,
1530			.enable_mask = BIT(0),
1531			.hw.init = &(const struct clk_init_data) {
1532				.name = "ecpri_cc_eth_100g_mac_fh0_hm_ref_clk",
1533				.parent_hws = (const struct clk_hw*[]) {
1534					&ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src.clkr.hw,
1535				},
1536				.num_parents = 1,
1537				.flags = CLK_SET_RATE_PARENT,
1538				.ops = &clk_branch2_mem_ops,
1539			},
1540		},
1541	},
1542};
1543
1544static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh1_hm_ref_clk = {
1545	.mem_enable_reg = 0x8408,
1546	.mem_ack_reg = 0x841c,
1547	.mem_enable_mask = BIT(5),
1548	.mem_enable_ack_mask = BIT(5),
1549	.branch = {
1550		.halt_reg = 0x8064,
1551		.halt_check = BRANCH_HALT,
1552		.clkr = {
1553			.enable_reg = 0x8064,
1554			.enable_mask = BIT(0),
1555			.hw.init = &(const struct clk_init_data) {
1556				.name = "ecpri_cc_eth_100g_mac_fh1_hm_ref_clk",
1557				.parent_hws = (const struct clk_hw*[]) {
1558					&ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src.clkr.hw,
1559				},
1560				.num_parents = 1,
1561				.flags = CLK_SET_RATE_PARENT,
1562				.ops = &clk_branch2_mem_ops,
1563			},
1564		},
1565	},
1566};
1567
1568static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh2_hm_ref_clk = {
1569	.mem_enable_reg = 0x840c,
1570	.mem_ack_reg = 0x8420,
1571	.mem_enable_mask = BIT(5),
1572	.mem_enable_ack_mask = BIT(5),
1573	.branch = {
1574		.halt_reg = 0x809c,
1575		.halt_check = BRANCH_HALT,
1576		.clkr = {
1577			.enable_reg = 0x809c,
1578			.enable_mask = BIT(0),
1579			.hw.init = &(const struct clk_init_data) {
1580				.name = "ecpri_cc_eth_100g_mac_fh2_hm_ref_clk",
1581				.parent_hws = (const struct clk_hw*[]) {
1582					&ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src.clkr.hw,
1583				},
1584				.num_parents = 1,
1585				.flags = CLK_SET_RATE_PARENT,
1586				.ops = &clk_branch2_mem_ops,
1587			},
1588		},
1589	},
1590};
1591
1592static struct clk_branch ecpri_cc_eth_dbg_nfapi_axi_clk = {
1593	.halt_reg = 0x80f4,
1594	.halt_check = BRANCH_HALT,
1595	.clkr = {
1596		.enable_reg = 0x80f4,
1597		.enable_mask = BIT(0),
1598		.hw.init = &(const struct clk_init_data) {
1599			.name = "ecpri_cc_eth_dbg_nfapi_axi_clk",
1600			.parent_hws = (const struct clk_hw*[]) {
1601				&ecpri_cc_ecpri_dma_clk_src.clkr.hw,
1602			},
1603			.num_parents = 1,
1604			.flags = CLK_SET_RATE_PARENT,
1605			.ops = &clk_branch2_ops,
1606		},
1607	},
1608};
1609
1610static struct clk_branch ecpri_cc_eth_dbg_noc_axi_clk = {
1611	.halt_reg = 0x80fc,
1612	.halt_check = BRANCH_HALT,
1613	.clkr = {
1614		.enable_reg = 0x80fc,
1615		.enable_mask = BIT(0),
1616		.hw.init = &(const struct clk_init_data) {
1617			.name = "ecpri_cc_eth_dbg_noc_axi_clk",
1618			.parent_hws = (const struct clk_hw*[]) {
1619				&ecpri_cc_mss_emac_clk_src.clkr.hw,
1620			},
1621			.num_parents = 1,
1622			.flags = CLK_SET_RATE_PARENT,
1623			.ops = &clk_branch2_ops,
1624		},
1625	},
1626};
1627
1628static struct clk_mem_branch ecpri_cc_eth_phy_0_ock_sram_clk = {
1629	.mem_enable_reg = 0x8404,
1630	.mem_ack_reg = 0x8418,
1631	.mem_enable_mask = BIT(6),
1632	.mem_enable_ack_mask = BIT(6),
1633	.branch = {
1634		.halt_reg = 0xd140,
1635		.halt_check = BRANCH_HALT,
1636		.clkr = {
1637			.enable_reg = 0xd140,
1638			.enable_mask = BIT(0),
1639			.hw.init = &(const struct clk_init_data) {
1640				.name = "ecpri_cc_eth_phy_0_ock_sram_clk",
1641				.ops = &clk_branch2_mem_ops,
1642			},
1643		},
1644	},
1645};
1646
1647static struct clk_mem_branch ecpri_cc_eth_phy_1_ock_sram_clk = {
1648	.mem_enable_reg = 0x8408,
1649	.mem_ack_reg = 0x841C,
1650	.mem_enable_mask = BIT(6),
1651	.mem_enable_ack_mask = BIT(6),
1652	.branch = {
1653		.halt_reg = 0xd148,
1654		.halt_check = BRANCH_HALT,
1655		.clkr = {
1656			.enable_reg = 0xd148,
1657			.enable_mask = BIT(0),
1658			.hw.init = &(const struct clk_init_data) {
1659				.name = "ecpri_cc_eth_phy_1_ock_sram_clk",
1660				.ops = &clk_branch2_mem_ops,
1661			},
1662		},
1663	},
1664};
1665
1666static struct clk_mem_branch ecpri_cc_eth_phy_2_ock_sram_clk = {
1667	.mem_enable_reg = 0x840c,
1668	.mem_ack_reg = 0x8420,
1669	.mem_enable_mask = BIT(6),
1670	.mem_enable_ack_mask = BIT(6),
1671	.branch = {
1672		.halt_reg = 0xd150,
1673		.halt_check = BRANCH_HALT,
1674		.clkr = {
1675			.enable_reg = 0xd150,
1676			.enable_mask = BIT(0),
1677			.hw.init = &(const struct clk_init_data) {
1678				.name = "ecpri_cc_eth_phy_2_ock_sram_clk",
1679				.ops = &clk_branch2_mem_ops,
1680			},
1681		},
1682	},
1683};
1684
1685static struct clk_mem_branch ecpri_cc_eth_phy_3_ock_sram_clk = {
1686	.mem_enable_reg = 0x8410,
1687	.mem_ack_reg = 0x8424,
1688	.mem_enable_mask = BIT(6),
1689	.mem_enable_ack_mask = BIT(6),
1690	.branch = {
1691		.halt_reg = 0xd158,
1692		.halt_check = BRANCH_HALT,
1693		.clkr = {
1694			.enable_reg = 0xd158,
1695			.enable_mask = BIT(0),
1696			.hw.init = &(const struct clk_init_data) {
1697				.name = "ecpri_cc_eth_phy_3_ock_sram_clk",
1698				.ops = &clk_branch2_mem_ops,
1699			},
1700		},
1701	},
1702};
1703
1704static struct clk_mem_branch ecpri_cc_eth_phy_4_ock_sram_clk = {
1705	.mem_enable_reg = 0x8414,
1706	.mem_ack_reg = 0x8428,
1707	.mem_enable_mask = BIT(6),
1708	.mem_enable_ack_mask = BIT(6),
1709	.branch = {
1710		.halt_reg = 0xd160,
1711		.halt_check = BRANCH_HALT,
1712		.clkr = {
1713			.enable_reg = 0xd160,
1714			.enable_mask = BIT(0),
1715			.hw.init = &(const struct clk_init_data) {
1716				.name = "ecpri_cc_eth_phy_4_ock_sram_clk",
1717				.ops = &clk_branch2_mem_ops,
1718			},
1719		},
1720	},
1721};
1722
1723static struct clk_branch ecpri_cc_mss_emac_clk = {
1724	.halt_reg = 0xe008,
1725	.halt_check = BRANCH_HALT,
1726	.clkr = {
1727		.enable_reg = 0xe008,
1728		.enable_mask = BIT(0),
1729		.hw.init = &(const struct clk_init_data) {
1730			.name = "ecpri_cc_mss_emac_clk",
1731			.parent_hws = (const struct clk_hw*[]) {
1732				&ecpri_cc_mss_emac_clk_src.clkr.hw,
1733			},
1734			.num_parents = 1,
1735			.flags = CLK_SET_RATE_PARENT,
1736			.ops = &clk_branch2_ops,
1737		},
1738	},
1739};
1740
1741static struct clk_branch ecpri_cc_mss_oran_clk = {
1742	.halt_reg = 0xe004,
1743	.halt_check = BRANCH_HALT,
1744	.clkr = {
1745		.enable_reg = 0xe004,
1746		.enable_mask = BIT(0),
1747		.hw.init = &(const struct clk_init_data) {
1748			.name = "ecpri_cc_mss_oran_clk",
1749			.parent_hws = (const struct clk_hw*[]) {
1750				&ecpri_cc_ecpri_oran_clk_src.clkr.hw,
1751			},
1752			.num_parents = 1,
1753			.flags = CLK_SET_RATE_PARENT,
1754			.ops = &clk_branch2_ops,
1755		},
1756	},
1757};
1758
1759static struct clk_branch ecpri_cc_phy0_lane0_rx_clk = {
1760	.halt_reg = 0xd000,
1761	.halt_check = BRANCH_HALT,
1762	.clkr = {
1763		.enable_reg = 0xd000,
1764		.enable_mask = BIT(0),
1765		.hw.init = &(const struct clk_init_data) {
1766			.name = "ecpri_cc_phy0_lane0_rx_clk",
1767			.ops = &clk_branch2_ops,
1768		},
1769	},
1770};
1771
1772static struct clk_branch ecpri_cc_phy0_lane0_tx_clk = {
1773	.halt_reg = 0xd050,
1774	.halt_check = BRANCH_HALT,
1775	.clkr = {
1776		.enable_reg = 0xd050,
1777		.enable_mask = BIT(0),
1778		.hw.init = &(const struct clk_init_data) {
1779			.name = "ecpri_cc_phy0_lane0_tx_clk",
1780			.ops = &clk_branch2_ops,
1781		},
1782	},
1783};
1784
1785static struct clk_branch ecpri_cc_phy0_lane1_rx_clk = {
1786	.halt_reg = 0xd004,
1787	.halt_check = BRANCH_HALT,
1788	.clkr = {
1789		.enable_reg = 0xd004,
1790		.enable_mask = BIT(0),
1791		.hw.init = &(const struct clk_init_data) {
1792			.name = "ecpri_cc_phy0_lane1_rx_clk",
1793			.ops = &clk_branch2_ops,
1794		},
1795	},
1796};
1797
1798static struct clk_branch ecpri_cc_phy0_lane1_tx_clk = {
1799	.halt_reg = 0xd054,
1800	.halt_check = BRANCH_HALT,
1801	.clkr = {
1802		.enable_reg = 0xd054,
1803		.enable_mask = BIT(0),
1804		.hw.init = &(const struct clk_init_data) {
1805			.name = "ecpri_cc_phy0_lane1_tx_clk",
1806			.ops = &clk_branch2_ops,
1807		},
1808	},
1809};
1810
1811static struct clk_branch ecpri_cc_phy0_lane2_rx_clk = {
1812	.halt_reg = 0xd008,
1813	.halt_check = BRANCH_HALT,
1814	.clkr = {
1815		.enable_reg = 0xd008,
1816		.enable_mask = BIT(0),
1817		.hw.init = &(const struct clk_init_data) {
1818			.name = "ecpri_cc_phy0_lane2_rx_clk",
1819			.ops = &clk_branch2_ops,
1820		},
1821	},
1822};
1823
1824static struct clk_branch ecpri_cc_phy0_lane2_tx_clk = {
1825	.halt_reg = 0xd058,
1826	.halt_check = BRANCH_HALT,
1827	.clkr = {
1828		.enable_reg = 0xd058,
1829		.enable_mask = BIT(0),
1830		.hw.init = &(const struct clk_init_data) {
1831			.name = "ecpri_cc_phy0_lane2_tx_clk",
1832			.ops = &clk_branch2_ops,
1833		},
1834	},
1835};
1836
1837static struct clk_branch ecpri_cc_phy0_lane3_rx_clk = {
1838	.halt_reg = 0xd00c,
1839	.halt_check = BRANCH_HALT,
1840	.clkr = {
1841		.enable_reg = 0xd00c,
1842		.enable_mask = BIT(0),
1843		.hw.init = &(const struct clk_init_data) {
1844			.name = "ecpri_cc_phy0_lane3_rx_clk",
1845			.ops = &clk_branch2_ops,
1846		},
1847	},
1848};
1849
1850static struct clk_branch ecpri_cc_phy0_lane3_tx_clk = {
1851	.halt_reg = 0xd05c,
1852	.halt_check = BRANCH_HALT,
1853	.clkr = {
1854		.enable_reg = 0xd05c,
1855		.enable_mask = BIT(0),
1856		.hw.init = &(const struct clk_init_data) {
1857			.name = "ecpri_cc_phy0_lane3_tx_clk",
1858			.ops = &clk_branch2_ops,
1859		},
1860	},
1861};
1862
1863static struct clk_branch ecpri_cc_phy1_lane0_rx_clk = {
1864	.halt_reg = 0xd010,
1865	.halt_check = BRANCH_HALT,
1866	.clkr = {
1867		.enable_reg = 0xd010,
1868		.enable_mask = BIT(0),
1869		.hw.init = &(const struct clk_init_data) {
1870			.name = "ecpri_cc_phy1_lane0_rx_clk",
1871			.ops = &clk_branch2_ops,
1872		},
1873	},
1874};
1875
1876static struct clk_branch ecpri_cc_phy1_lane0_tx_clk = {
1877	.halt_reg = 0xd060,
1878	.halt_check = BRANCH_HALT,
1879	.clkr = {
1880		.enable_reg = 0xd060,
1881		.enable_mask = BIT(0),
1882		.hw.init = &(const struct clk_init_data) {
1883			.name = "ecpri_cc_phy1_lane0_tx_clk",
1884			.ops = &clk_branch2_ops,
1885		},
1886	},
1887};
1888
1889static struct clk_branch ecpri_cc_phy1_lane1_rx_clk = {
1890	.halt_reg = 0xd014,
1891	.halt_check = BRANCH_HALT,
1892	.clkr = {
1893		.enable_reg = 0xd014,
1894		.enable_mask = BIT(0),
1895		.hw.init = &(const struct clk_init_data) {
1896			.name = "ecpri_cc_phy1_lane1_rx_clk",
1897			.ops = &clk_branch2_ops,
1898		},
1899	},
1900};
1901
1902static struct clk_branch ecpri_cc_phy1_lane1_tx_clk = {
1903	.halt_reg = 0xd064,
1904	.halt_check = BRANCH_HALT,
1905	.clkr = {
1906		.enable_reg = 0xd064,
1907		.enable_mask = BIT(0),
1908		.hw.init = &(const struct clk_init_data) {
1909			.name = "ecpri_cc_phy1_lane1_tx_clk",
1910			.ops = &clk_branch2_ops,
1911		},
1912	},
1913};
1914
1915static struct clk_branch ecpri_cc_phy1_lane2_rx_clk = {
1916	.halt_reg = 0xd018,
1917	.halt_check = BRANCH_HALT,
1918	.clkr = {
1919		.enable_reg = 0xd018,
1920		.enable_mask = BIT(0),
1921		.hw.init = &(const struct clk_init_data) {
1922			.name = "ecpri_cc_phy1_lane2_rx_clk",
1923			.ops = &clk_branch2_ops,
1924		},
1925	},
1926};
1927
1928static struct clk_branch ecpri_cc_phy1_lane2_tx_clk = {
1929	.halt_reg = 0xd068,
1930	.halt_check = BRANCH_HALT,
1931	.clkr = {
1932		.enable_reg = 0xd068,
1933		.enable_mask = BIT(0),
1934		.hw.init = &(const struct clk_init_data) {
1935			.name = "ecpri_cc_phy1_lane2_tx_clk",
1936			.ops = &clk_branch2_ops,
1937		},
1938	},
1939};
1940
1941static struct clk_branch ecpri_cc_phy1_lane3_rx_clk = {
1942	.halt_reg = 0xd01c,
1943	.halt_check = BRANCH_HALT,
1944	.clkr = {
1945		.enable_reg = 0xd01c,
1946		.enable_mask = BIT(0),
1947		.hw.init = &(const struct clk_init_data) {
1948			.name = "ecpri_cc_phy1_lane3_rx_clk",
1949			.ops = &clk_branch2_ops,
1950		},
1951	},
1952};
1953
1954static struct clk_branch ecpri_cc_phy1_lane3_tx_clk = {
1955	.halt_reg = 0xd06c,
1956	.halt_check = BRANCH_HALT,
1957	.clkr = {
1958		.enable_reg = 0xd06c,
1959		.enable_mask = BIT(0),
1960		.hw.init = &(const struct clk_init_data) {
1961			.name = "ecpri_cc_phy1_lane3_tx_clk",
1962			.ops = &clk_branch2_ops,
1963		},
1964	},
1965};
1966
1967static struct clk_branch ecpri_cc_phy2_lane0_rx_clk = {
1968	.halt_reg = 0xd020,
1969	.halt_check = BRANCH_HALT,
1970	.clkr = {
1971		.enable_reg = 0xd020,
1972		.enable_mask = BIT(0),
1973		.hw.init = &(const struct clk_init_data) {
1974			.name = "ecpri_cc_phy2_lane0_rx_clk",
1975			.ops = &clk_branch2_ops,
1976		},
1977	},
1978};
1979
1980static struct clk_branch ecpri_cc_phy2_lane0_tx_clk = {
1981	.halt_reg = 0xd070,
1982	.halt_check = BRANCH_HALT,
1983	.clkr = {
1984		.enable_reg = 0xd070,
1985		.enable_mask = BIT(0),
1986		.hw.init = &(const struct clk_init_data) {
1987			.name = "ecpri_cc_phy2_lane0_tx_clk",
1988			.ops = &clk_branch2_ops,
1989		},
1990	},
1991};
1992
1993static struct clk_branch ecpri_cc_phy2_lane1_rx_clk = {
1994	.halt_reg = 0xd024,
1995	.halt_check = BRANCH_HALT,
1996	.clkr = {
1997		.enable_reg = 0xd024,
1998		.enable_mask = BIT(0),
1999		.hw.init = &(const struct clk_init_data) {
2000			.name = "ecpri_cc_phy2_lane1_rx_clk",
2001			.ops = &clk_branch2_ops,
2002		},
2003	},
2004};
2005
2006static struct clk_branch ecpri_cc_phy2_lane1_tx_clk = {
2007	.halt_reg = 0xd074,
2008	.halt_check = BRANCH_HALT,
2009	.clkr = {
2010		.enable_reg = 0xd074,
2011		.enable_mask = BIT(0),
2012		.hw.init = &(const struct clk_init_data) {
2013			.name = "ecpri_cc_phy2_lane1_tx_clk",
2014			.ops = &clk_branch2_ops,
2015		},
2016	},
2017};
2018
2019static struct clk_branch ecpri_cc_phy2_lane2_rx_clk = {
2020	.halt_reg = 0xd028,
2021	.halt_check = BRANCH_HALT,
2022	.clkr = {
2023		.enable_reg = 0xd028,
2024		.enable_mask = BIT(0),
2025		.hw.init = &(const struct clk_init_data) {
2026			.name = "ecpri_cc_phy2_lane2_rx_clk",
2027			.ops = &clk_branch2_ops,
2028		},
2029	},
2030};
2031
2032static struct clk_branch ecpri_cc_phy2_lane2_tx_clk = {
2033	.halt_reg = 0xd078,
2034	.halt_check = BRANCH_HALT,
2035	.clkr = {
2036		.enable_reg = 0xd078,
2037		.enable_mask = BIT(0),
2038		.hw.init = &(const struct clk_init_data) {
2039			.name = "ecpri_cc_phy2_lane2_tx_clk",
2040			.ops = &clk_branch2_ops,
2041		},
2042	},
2043};
2044
2045static struct clk_branch ecpri_cc_phy2_lane3_rx_clk = {
2046	.halt_reg = 0xd02c,
2047	.halt_check = BRANCH_HALT,
2048	.clkr = {
2049		.enable_reg = 0xd02c,
2050		.enable_mask = BIT(0),
2051		.hw.init = &(const struct clk_init_data) {
2052			.name = "ecpri_cc_phy2_lane3_rx_clk",
2053			.ops = &clk_branch2_ops,
2054		},
2055	},
2056};
2057
2058static struct clk_branch ecpri_cc_phy2_lane3_tx_clk = {
2059	.halt_reg = 0xd07c,
2060	.halt_check = BRANCH_HALT,
2061	.clkr = {
2062		.enable_reg = 0xd07c,
2063		.enable_mask = BIT(0),
2064		.hw.init = &(const struct clk_init_data) {
2065			.name = "ecpri_cc_phy2_lane3_tx_clk",
2066			.ops = &clk_branch2_ops,
2067		},
2068	},
2069};
2070
2071static struct clk_branch ecpri_cc_phy3_lane0_rx_clk = {
2072	.halt_reg = 0xd030,
2073	.halt_check = BRANCH_HALT,
2074	.clkr = {
2075		.enable_reg = 0xd030,
2076		.enable_mask = BIT(0),
2077		.hw.init = &(const struct clk_init_data) {
2078			.name = "ecpri_cc_phy3_lane0_rx_clk",
2079			.ops = &clk_branch2_ops,
2080		},
2081	},
2082};
2083
2084static struct clk_branch ecpri_cc_phy3_lane0_tx_clk = {
2085	.halt_reg = 0xd080,
2086	.halt_check = BRANCH_HALT,
2087	.clkr = {
2088		.enable_reg = 0xd080,
2089		.enable_mask = BIT(0),
2090		.hw.init = &(const struct clk_init_data) {
2091			.name = "ecpri_cc_phy3_lane0_tx_clk",
2092			.ops = &clk_branch2_ops,
2093		},
2094	},
2095};
2096
2097static struct clk_branch ecpri_cc_phy3_lane1_rx_clk = {
2098	.halt_reg = 0xd034,
2099	.halt_check = BRANCH_HALT,
2100	.clkr = {
2101		.enable_reg = 0xd034,
2102		.enable_mask = BIT(0),
2103		.hw.init = &(const struct clk_init_data) {
2104			.name = "ecpri_cc_phy3_lane1_rx_clk",
2105			.ops = &clk_branch2_ops,
2106		},
2107	},
2108};
2109
2110static struct clk_branch ecpri_cc_phy3_lane1_tx_clk = {
2111	.halt_reg = 0xd084,
2112	.halt_check = BRANCH_HALT,
2113	.clkr = {
2114		.enable_reg = 0xd084,
2115		.enable_mask = BIT(0),
2116		.hw.init = &(const struct clk_init_data) {
2117			.name = "ecpri_cc_phy3_lane1_tx_clk",
2118			.ops = &clk_branch2_ops,
2119		},
2120	},
2121};
2122
2123static struct clk_branch ecpri_cc_phy3_lane2_rx_clk = {
2124	.halt_reg = 0xd038,
2125	.halt_check = BRANCH_HALT,
2126	.clkr = {
2127		.enable_reg = 0xd038,
2128		.enable_mask = BIT(0),
2129		.hw.init = &(const struct clk_init_data) {
2130			.name = "ecpri_cc_phy3_lane2_rx_clk",
2131			.ops = &clk_branch2_ops,
2132		},
2133	},
2134};
2135
2136static struct clk_branch ecpri_cc_phy3_lane2_tx_clk = {
2137	.halt_reg = 0xd088,
2138	.halt_check = BRANCH_HALT,
2139	.clkr = {
2140		.enable_reg = 0xd088,
2141		.enable_mask = BIT(0),
2142		.hw.init = &(const struct clk_init_data) {
2143			.name = "ecpri_cc_phy3_lane2_tx_clk",
2144			.ops = &clk_branch2_ops,
2145		},
2146	},
2147};
2148
2149static struct clk_branch ecpri_cc_phy3_lane3_rx_clk = {
2150	.halt_reg = 0xd03c,
2151	.halt_check = BRANCH_HALT,
2152	.clkr = {
2153		.enable_reg = 0xd03c,
2154		.enable_mask = BIT(0),
2155		.hw.init = &(const struct clk_init_data) {
2156			.name = "ecpri_cc_phy3_lane3_rx_clk",
2157			.ops = &clk_branch2_ops,
2158		},
2159	},
2160};
2161
2162static struct clk_branch ecpri_cc_phy3_lane3_tx_clk = {
2163	.halt_reg = 0xd08c,
2164	.halt_check = BRANCH_HALT,
2165	.clkr = {
2166		.enable_reg = 0xd08c,
2167		.enable_mask = BIT(0),
2168		.hw.init = &(const struct clk_init_data) {
2169			.name = "ecpri_cc_phy3_lane3_tx_clk",
2170			.ops = &clk_branch2_ops,
2171		},
2172	},
2173};
2174
2175static struct clk_branch ecpri_cc_phy4_lane0_rx_clk = {
2176	.halt_reg = 0xd040,
2177	.halt_check = BRANCH_HALT,
2178	.clkr = {
2179		.enable_reg = 0xd040,
2180		.enable_mask = BIT(0),
2181		.hw.init = &(const struct clk_init_data) {
2182			.name = "ecpri_cc_phy4_lane0_rx_clk",
2183			.ops = &clk_branch2_ops,
2184		},
2185	},
2186};
2187
2188static struct clk_branch ecpri_cc_phy4_lane0_tx_clk = {
2189	.halt_reg = 0xd090,
2190	.halt_check = BRANCH_HALT,
2191	.clkr = {
2192		.enable_reg = 0xd090,
2193		.enable_mask = BIT(0),
2194		.hw.init = &(const struct clk_init_data) {
2195			.name = "ecpri_cc_phy4_lane0_tx_clk",
2196			.ops = &clk_branch2_ops,
2197		},
2198	},
2199};
2200
2201static struct clk_branch ecpri_cc_phy4_lane1_rx_clk = {
2202	.halt_reg = 0xd044,
2203	.halt_check = BRANCH_HALT,
2204	.clkr = {
2205		.enable_reg = 0xd044,
2206		.enable_mask = BIT(0),
2207		.hw.init = &(const struct clk_init_data) {
2208			.name = "ecpri_cc_phy4_lane1_rx_clk",
2209			.ops = &clk_branch2_ops,
2210		},
2211	},
2212};
2213
2214static struct clk_branch ecpri_cc_phy4_lane1_tx_clk = {
2215	.halt_reg = 0xd094,
2216	.halt_check = BRANCH_HALT,
2217	.clkr = {
2218		.enable_reg = 0xd094,
2219		.enable_mask = BIT(0),
2220		.hw.init = &(const struct clk_init_data) {
2221			.name = "ecpri_cc_phy4_lane1_tx_clk",
2222			.ops = &clk_branch2_ops,
2223		},
2224	},
2225};
2226
2227static struct clk_branch ecpri_cc_phy4_lane2_rx_clk = {
2228	.halt_reg = 0xd048,
2229	.halt_check = BRANCH_HALT,
2230	.clkr = {
2231		.enable_reg = 0xd048,
2232		.enable_mask = BIT(0),
2233		.hw.init = &(const struct clk_init_data) {
2234			.name = "ecpri_cc_phy4_lane2_rx_clk",
2235			.ops = &clk_branch2_ops,
2236		},
2237	},
2238};
2239
2240static struct clk_branch ecpri_cc_phy4_lane2_tx_clk = {
2241	.halt_reg = 0xd098,
2242	.halt_check = BRANCH_HALT,
2243	.clkr = {
2244		.enable_reg = 0xd098,
2245		.enable_mask = BIT(0),
2246		.hw.init = &(const struct clk_init_data) {
2247			.name = "ecpri_cc_phy4_lane2_tx_clk",
2248			.ops = &clk_branch2_ops,
2249		},
2250	},
2251};
2252
2253static struct clk_branch ecpri_cc_phy4_lane3_rx_clk = {
2254	.halt_reg = 0xd04c,
2255	.halt_check = BRANCH_HALT,
2256	.clkr = {
2257		.enable_reg = 0xd04c,
2258		.enable_mask = BIT(0),
2259		.hw.init = &(const struct clk_init_data) {
2260			.name = "ecpri_cc_phy4_lane3_rx_clk",
2261			.ops = &clk_branch2_ops,
2262		},
2263	},
2264};
2265
2266static struct clk_branch ecpri_cc_phy4_lane3_tx_clk = {
2267	.halt_reg = 0xd09c,
2268	.halt_check = BRANCH_HALT,
2269	.clkr = {
2270		.enable_reg = 0xd09c,
2271		.enable_mask = BIT(0),
2272		.hw.init = &(const struct clk_init_data) {
2273			.name = "ecpri_cc_phy4_lane3_tx_clk",
2274			.ops = &clk_branch2_ops,
2275		},
2276	},
2277};
2278
2279static struct clk_regmap *ecpri_cc_qdu1000_clocks[] = {
2280	[ECPRI_CC_ECPRI_CG_CLK] = &ecpri_cc_ecpri_cg_clk.clkr,
2281	[ECPRI_CC_ECPRI_CLK_SRC] = &ecpri_cc_ecpri_clk_src.clkr,
2282	[ECPRI_CC_ECPRI_DMA_CLK] = &ecpri_cc_ecpri_dma_clk.clkr,
2283	[ECPRI_CC_ECPRI_DMA_CLK_SRC] = &ecpri_cc_ecpri_dma_clk_src.clkr,
2284	[ECPRI_CC_ECPRI_DMA_NOC_CLK] = &ecpri_cc_ecpri_dma_noc_clk.clkr,
2285	[ECPRI_CC_ECPRI_FAST_CLK] = &ecpri_cc_ecpri_fast_clk.clkr,
2286	[ECPRI_CC_ECPRI_FAST_CLK_SRC] = &ecpri_cc_ecpri_fast_clk_src.clkr,
2287	[ECPRI_CC_ECPRI_FAST_DIV2_CLK] = &ecpri_cc_ecpri_fast_div2_clk.clkr,
2288	[ECPRI_CC_ECPRI_FAST_DIV2_CLK_SRC] = &ecpri_cc_ecpri_fast_div2_clk_src.clkr,
2289	[ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK] = &ecpri_cc_ecpri_fast_div2_noc_clk.clkr,
2290	[ECPRI_CC_ECPRI_FR_CLK] = &ecpri_cc_ecpri_fr_clk.clkr,
2291	[ECPRI_CC_ECPRI_ORAN_CLK_SRC] = &ecpri_cc_ecpri_oran_clk_src.clkr,
2292	[ECPRI_CC_ECPRI_ORAN_DIV2_CLK] = &ecpri_cc_ecpri_oran_div2_clk.clkr,
2293	[ECPRI_CC_ETH_100G_C2C0_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_c2c0_hm_ff_clk_src.clkr,
2294	[ECPRI_CC_ETH_100G_C2C0_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_c2c0_udp_fifo_clk.clkr,
2295	[ECPRI_CC_ETH_100G_C2C1_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_c2c1_udp_fifo_clk.clkr,
2296	[ECPRI_CC_ETH_100G_C2C_0_HM_FF_0_CLK] = &ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk.branch.clkr,
2297	[ECPRI_CC_ETH_100G_C2C_0_HM_FF_1_CLK] = &ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk.branch.clkr,
2298	[ECPRI_CC_ETH_100G_C2C_HM_FF_0_DIV_CLK_SRC] =
2299		&ecpri_cc_eth_100g_c2c_hm_ff_0_div_clk_src.clkr,
2300	[ECPRI_CC_ETH_100G_C2C_HM_FF_1_DIV_CLK_SRC] =
2301		&ecpri_cc_eth_100g_c2c_hm_ff_1_div_clk_src.clkr,
2302	[ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK] = &ecpri_cc_eth_100g_c2c_hm_macsec_clk.branch.clkr,
2303	[ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK_SRC] = &ecpri_cc_eth_100g_c2c_hm_macsec_clk_src.clkr,
2304	[ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_CLK] =
2305		&ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk.branch.clkr,
2306	[ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_DIV_CLK_SRC] =
2307		&ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_div_clk_src.clkr,
2308	[ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_CLK] =
2309		&ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk.branch.clkr,
2310	[ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_DIV_CLK_SRC] =
2311		&ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_div_clk_src.clkr,
2312	[ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_dbg_c2c_hm_ff_clk_src.clkr,
2313	[ECPRI_CC_ETH_100G_DBG_C2C_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_dbg_c2c_udp_fifo_clk.clkr,
2314	[ECPRI_CC_ETH_100G_FH0_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_fh0_hm_ff_clk_src.clkr,
2315	[ECPRI_CC_ETH_100G_FH0_MACSEC_CLK_SRC] = &ecpri_cc_eth_100g_fh0_macsec_clk_src.clkr,
2316	[ECPRI_CC_ETH_100G_FH1_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_fh1_hm_ff_clk_src.clkr,
2317	[ECPRI_CC_ETH_100G_FH1_MACSEC_CLK_SRC] = &ecpri_cc_eth_100g_fh1_macsec_clk_src.clkr,
2318	[ECPRI_CC_ETH_100G_FH2_HM_FF_CLK_SRC] = &ecpri_cc_eth_100g_fh2_hm_ff_clk_src.clkr,
2319	[ECPRI_CC_ETH_100G_FH2_MACSEC_CLK_SRC] = &ecpri_cc_eth_100g_fh2_macsec_clk_src.clkr,
2320	[ECPRI_CC_ETH_100G_FH_0_HM_FF_0_CLK] = &ecpri_cc_eth_100g_fh_0_hm_ff_0_clk.branch.clkr,
2321	[ECPRI_CC_ETH_100G_FH_0_HM_FF_0_DIV_CLK_SRC] =
2322		&ecpri_cc_eth_100g_fh_0_hm_ff_0_div_clk_src.clkr,
2323	[ECPRI_CC_ETH_100G_FH_0_HM_FF_1_CLK] = &ecpri_cc_eth_100g_fh_0_hm_ff_1_clk.branch.clkr,
2324	[ECPRI_CC_ETH_100G_FH_0_HM_FF_1_DIV_CLK_SRC] =
2325		&ecpri_cc_eth_100g_fh_0_hm_ff_1_div_clk_src.clkr,
2326	[ECPRI_CC_ETH_100G_FH_0_HM_FF_2_CLK] = &ecpri_cc_eth_100g_fh_0_hm_ff_2_clk.branch.clkr,
2327	[ECPRI_CC_ETH_100G_FH_0_HM_FF_2_DIV_CLK_SRC] =
2328		&ecpri_cc_eth_100g_fh_0_hm_ff_2_div_clk_src.clkr,
2329	[ECPRI_CC_ETH_100G_FH_0_HM_FF_3_CLK] = &ecpri_cc_eth_100g_fh_0_hm_ff_3_clk.branch.clkr,
2330	[ECPRI_CC_ETH_100G_FH_0_HM_FF_3_DIV_CLK_SRC] =
2331		&ecpri_cc_eth_100g_fh_0_hm_ff_3_div_clk_src.clkr,
2332	[ECPRI_CC_ETH_100G_FH_0_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_fh_0_udp_fifo_clk.clkr,
2333	[ECPRI_CC_ETH_100G_FH_1_HM_FF_0_CLK] = &ecpri_cc_eth_100g_fh_1_hm_ff_0_clk.branch.clkr,
2334	[ECPRI_CC_ETH_100G_FH_1_HM_FF_0_DIV_CLK_SRC] =
2335		&ecpri_cc_eth_100g_fh_1_hm_ff_0_div_clk_src.clkr,
2336	[ECPRI_CC_ETH_100G_FH_1_HM_FF_1_CLK] = &ecpri_cc_eth_100g_fh_1_hm_ff_1_clk.branch.clkr,
2337	[ECPRI_CC_ETH_100G_FH_1_HM_FF_1_DIV_CLK_SRC] =
2338		&ecpri_cc_eth_100g_fh_1_hm_ff_1_div_clk_src.clkr,
2339	[ECPRI_CC_ETH_100G_FH_1_HM_FF_2_CLK] = &ecpri_cc_eth_100g_fh_1_hm_ff_2_clk.branch.clkr,
2340	[ECPRI_CC_ETH_100G_FH_1_HM_FF_2_DIV_CLK_SRC] =
2341		&ecpri_cc_eth_100g_fh_1_hm_ff_2_div_clk_src.clkr,
2342	[ECPRI_CC_ETH_100G_FH_1_HM_FF_3_CLK] = &ecpri_cc_eth_100g_fh_1_hm_ff_3_clk.branch.clkr,
2343	[ECPRI_CC_ETH_100G_FH_1_HM_FF_3_DIV_CLK_SRC] =
2344		&ecpri_cc_eth_100g_fh_1_hm_ff_3_div_clk_src.clkr,
2345	[ECPRI_CC_ETH_100G_FH_1_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_fh_1_udp_fifo_clk.clkr,
2346	[ECPRI_CC_ETH_100G_FH_2_HM_FF_0_CLK] = &ecpri_cc_eth_100g_fh_2_hm_ff_0_clk.branch.clkr,
2347	[ECPRI_CC_ETH_100G_FH_2_HM_FF_0_DIV_CLK_SRC] =
2348		&ecpri_cc_eth_100g_fh_2_hm_ff_0_div_clk_src.clkr,
2349	[ECPRI_CC_ETH_100G_FH_2_HM_FF_1_CLK] = &ecpri_cc_eth_100g_fh_2_hm_ff_1_clk.branch.clkr,
2350	[ECPRI_CC_ETH_100G_FH_2_HM_FF_1_DIV_CLK_SRC] =
2351		&ecpri_cc_eth_100g_fh_2_hm_ff_1_div_clk_src.clkr,
2352	[ECPRI_CC_ETH_100G_FH_2_HM_FF_2_CLK] = &ecpri_cc_eth_100g_fh_2_hm_ff_2_clk.branch.clkr,
2353	[ECPRI_CC_ETH_100G_FH_2_HM_FF_2_DIV_CLK_SRC] =
2354		&ecpri_cc_eth_100g_fh_2_hm_ff_2_div_clk_src.clkr,
2355	[ECPRI_CC_ETH_100G_FH_2_HM_FF_3_CLK] = &ecpri_cc_eth_100g_fh_2_hm_ff_3_clk.branch.clkr,
2356	[ECPRI_CC_ETH_100G_FH_2_HM_FF_3_DIV_CLK_SRC] =
2357		&ecpri_cc_eth_100g_fh_2_hm_ff_3_div_clk_src.clkr,
2358	[ECPRI_CC_ETH_100G_FH_2_UDP_FIFO_CLK] = &ecpri_cc_eth_100g_fh_2_udp_fifo_clk.clkr,
2359	[ECPRI_CC_ETH_100G_FH_MACSEC_0_CLK] = &ecpri_cc_eth_100g_fh_macsec_0_clk.branch.clkr,
2360	[ECPRI_CC_ETH_100G_FH_MACSEC_1_CLK] = &ecpri_cc_eth_100g_fh_macsec_1_clk.branch.clkr,
2361	[ECPRI_CC_ETH_100G_FH_MACSEC_2_CLK] = &ecpri_cc_eth_100g_fh_macsec_2_clk.branch.clkr,
2362	[ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK] = &ecpri_cc_eth_100g_mac_c2c_hm_ref_clk.branch.clkr,
2363	[ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK_SRC] = &ecpri_cc_eth_100g_mac_c2c_hm_ref_clk_src.clkr,
2364	[ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK] =
2365		&ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk.branch.clkr,
2366	[ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK_SRC] =
2367		&ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk_src.clkr,
2368	[ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK] = &ecpri_cc_eth_100g_mac_fh0_hm_ref_clk.branch.clkr,
2369	[ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK_SRC] = &ecpri_cc_eth_100g_mac_fh0_hm_ref_clk_src.clkr,
2370	[ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK] = &ecpri_cc_eth_100g_mac_fh1_hm_ref_clk.branch.clkr,
2371	[ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK_SRC] = &ecpri_cc_eth_100g_mac_fh1_hm_ref_clk_src.clkr,
2372	[ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK] = &ecpri_cc_eth_100g_mac_fh2_hm_ref_clk.branch.clkr,
2373	[ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK_SRC] = &ecpri_cc_eth_100g_mac_fh2_hm_ref_clk_src.clkr,
2374	[ECPRI_CC_ETH_DBG_NFAPI_AXI_CLK] = &ecpri_cc_eth_dbg_nfapi_axi_clk.clkr,
2375	[ECPRI_CC_ETH_DBG_NOC_AXI_CLK] = &ecpri_cc_eth_dbg_noc_axi_clk.clkr,
2376	[ECPRI_CC_ETH_PHY_0_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_0_ock_sram_clk.branch.clkr,
2377	[ECPRI_CC_ETH_PHY_1_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_1_ock_sram_clk.branch.clkr,
2378	[ECPRI_CC_ETH_PHY_2_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_2_ock_sram_clk.branch.clkr,
2379	[ECPRI_CC_ETH_PHY_3_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_3_ock_sram_clk.branch.clkr,
2380	[ECPRI_CC_ETH_PHY_4_OCK_SRAM_CLK] = &ecpri_cc_eth_phy_4_ock_sram_clk.branch.clkr,
2381	[ECPRI_CC_MSS_EMAC_CLK] = &ecpri_cc_mss_emac_clk.clkr,
2382	[ECPRI_CC_MSS_EMAC_CLK_SRC] = &ecpri_cc_mss_emac_clk_src.clkr,
2383	[ECPRI_CC_MSS_ORAN_CLK] = &ecpri_cc_mss_oran_clk.clkr,
2384	[ECPRI_CC_PHY0_LANE0_RX_CLK] = &ecpri_cc_phy0_lane0_rx_clk.clkr,
2385	[ECPRI_CC_PHY0_LANE0_TX_CLK] = &ecpri_cc_phy0_lane0_tx_clk.clkr,
2386	[ECPRI_CC_PHY0_LANE1_RX_CLK] = &ecpri_cc_phy0_lane1_rx_clk.clkr,
2387	[ECPRI_CC_PHY0_LANE1_TX_CLK] = &ecpri_cc_phy0_lane1_tx_clk.clkr,
2388	[ECPRI_CC_PHY0_LANE2_RX_CLK] = &ecpri_cc_phy0_lane2_rx_clk.clkr,
2389	[ECPRI_CC_PHY0_LANE2_TX_CLK] = &ecpri_cc_phy0_lane2_tx_clk.clkr,
2390	[ECPRI_CC_PHY0_LANE3_RX_CLK] = &ecpri_cc_phy0_lane3_rx_clk.clkr,
2391	[ECPRI_CC_PHY0_LANE3_TX_CLK] = &ecpri_cc_phy0_lane3_tx_clk.clkr,
2392	[ECPRI_CC_PHY1_LANE0_RX_CLK] = &ecpri_cc_phy1_lane0_rx_clk.clkr,
2393	[ECPRI_CC_PHY1_LANE0_TX_CLK] = &ecpri_cc_phy1_lane0_tx_clk.clkr,
2394	[ECPRI_CC_PHY1_LANE1_RX_CLK] = &ecpri_cc_phy1_lane1_rx_clk.clkr,
2395	[ECPRI_CC_PHY1_LANE1_TX_CLK] = &ecpri_cc_phy1_lane1_tx_clk.clkr,
2396	[ECPRI_CC_PHY1_LANE2_RX_CLK] = &ecpri_cc_phy1_lane2_rx_clk.clkr,
2397	[ECPRI_CC_PHY1_LANE2_TX_CLK] = &ecpri_cc_phy1_lane2_tx_clk.clkr,
2398	[ECPRI_CC_PHY1_LANE3_RX_CLK] = &ecpri_cc_phy1_lane3_rx_clk.clkr,
2399	[ECPRI_CC_PHY1_LANE3_TX_CLK] = &ecpri_cc_phy1_lane3_tx_clk.clkr,
2400	[ECPRI_CC_PHY2_LANE0_RX_CLK] = &ecpri_cc_phy2_lane0_rx_clk.clkr,
2401	[ECPRI_CC_PHY2_LANE0_TX_CLK] = &ecpri_cc_phy2_lane0_tx_clk.clkr,
2402	[ECPRI_CC_PHY2_LANE1_RX_CLK] = &ecpri_cc_phy2_lane1_rx_clk.clkr,
2403	[ECPRI_CC_PHY2_LANE1_TX_CLK] = &ecpri_cc_phy2_lane1_tx_clk.clkr,
2404	[ECPRI_CC_PHY2_LANE2_RX_CLK] = &ecpri_cc_phy2_lane2_rx_clk.clkr,
2405	[ECPRI_CC_PHY2_LANE2_TX_CLK] = &ecpri_cc_phy2_lane2_tx_clk.clkr,
2406	[ECPRI_CC_PHY2_LANE3_RX_CLK] = &ecpri_cc_phy2_lane3_rx_clk.clkr,
2407	[ECPRI_CC_PHY2_LANE3_TX_CLK] = &ecpri_cc_phy2_lane3_tx_clk.clkr,
2408	[ECPRI_CC_PHY3_LANE0_RX_CLK] = &ecpri_cc_phy3_lane0_rx_clk.clkr,
2409	[ECPRI_CC_PHY3_LANE0_TX_CLK] = &ecpri_cc_phy3_lane0_tx_clk.clkr,
2410	[ECPRI_CC_PHY3_LANE1_RX_CLK] = &ecpri_cc_phy3_lane1_rx_clk.clkr,
2411	[ECPRI_CC_PHY3_LANE1_TX_CLK] = &ecpri_cc_phy3_lane1_tx_clk.clkr,
2412	[ECPRI_CC_PHY3_LANE2_RX_CLK] = &ecpri_cc_phy3_lane2_rx_clk.clkr,
2413	[ECPRI_CC_PHY3_LANE2_TX_CLK] = &ecpri_cc_phy3_lane2_tx_clk.clkr,
2414	[ECPRI_CC_PHY3_LANE3_RX_CLK] = &ecpri_cc_phy3_lane3_rx_clk.clkr,
2415	[ECPRI_CC_PHY3_LANE3_TX_CLK] = &ecpri_cc_phy3_lane3_tx_clk.clkr,
2416	[ECPRI_CC_PHY4_LANE0_RX_CLK] = &ecpri_cc_phy4_lane0_rx_clk.clkr,
2417	[ECPRI_CC_PHY4_LANE0_TX_CLK] = &ecpri_cc_phy4_lane0_tx_clk.clkr,
2418	[ECPRI_CC_PHY4_LANE1_RX_CLK] = &ecpri_cc_phy4_lane1_rx_clk.clkr,
2419	[ECPRI_CC_PHY4_LANE1_TX_CLK] = &ecpri_cc_phy4_lane1_tx_clk.clkr,
2420	[ECPRI_CC_PHY4_LANE2_RX_CLK] = &ecpri_cc_phy4_lane2_rx_clk.clkr,
2421	[ECPRI_CC_PHY4_LANE2_TX_CLK] = &ecpri_cc_phy4_lane2_tx_clk.clkr,
2422	[ECPRI_CC_PHY4_LANE3_RX_CLK] = &ecpri_cc_phy4_lane3_rx_clk.clkr,
2423	[ECPRI_CC_PHY4_LANE3_TX_CLK] = &ecpri_cc_phy4_lane3_tx_clk.clkr,
2424	[ECPRI_CC_PLL0] = &ecpri_cc_pll0.clkr,
2425	[ECPRI_CC_PLL1] = &ecpri_cc_pll1.clkr,
2426};
2427
2428static const struct qcom_reset_map ecpri_cc_qdu1000_resets[] = {
2429	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ECPRI_SS_BCR] = { 0x9000 },
2430	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_C2C_BCR] = { 0x80a8 },
2431	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH0_BCR] = { 0x8000 },
2432	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH1_BCR] = { 0x8038 },
2433	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH2_BCR] = { 0x8070 },
2434	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_WRAPPER_TOP_BCR] = { 0x8104 },
2435	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_MODEM_BCR] = { 0xe000 },
2436	[ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_NOC_BCR] = { 0xf000 },
2437};
2438
2439static const struct regmap_config ecpri_cc_qdu1000_regmap_config = {
2440	.reg_bits = 32,
2441	.reg_stride = 4,
2442	.val_bits = 32,
2443	.max_register = 0x31bf0,
2444	.fast_io = true,
2445};
2446
2447static const struct qcom_cc_desc ecpri_cc_qdu1000_desc = {
2448	.config = &ecpri_cc_qdu1000_regmap_config,
2449	.clks = ecpri_cc_qdu1000_clocks,
2450	.num_clks = ARRAY_SIZE(ecpri_cc_qdu1000_clocks),
2451	.resets = ecpri_cc_qdu1000_resets,
2452	.num_resets = ARRAY_SIZE(ecpri_cc_qdu1000_resets),
2453};
2454
2455static const struct of_device_id ecpri_cc_qdu1000_match_table[] = {
2456	{ .compatible = "qcom,qdu1000-ecpricc" },
2457	{ }
2458};
2459MODULE_DEVICE_TABLE(of, ecpri_cc_qdu1000_match_table);
2460
2461static int ecpri_cc_qdu1000_probe(struct platform_device *pdev)
2462{
2463	struct regmap *regmap;
2464
2465	regmap = qcom_cc_map(pdev, &ecpri_cc_qdu1000_desc);
2466	if (IS_ERR(regmap))
2467		return PTR_ERR(regmap);
2468
2469	clk_lucid_evo_pll_configure(&ecpri_cc_pll0, regmap, &ecpri_cc_pll0_config);
2470	clk_lucid_evo_pll_configure(&ecpri_cc_pll1, regmap, &ecpri_cc_pll1_config);
2471
2472	return qcom_cc_really_probe(&pdev->dev, &ecpri_cc_qdu1000_desc, regmap);
2473}
2474
2475static struct platform_driver ecpri_cc_qdu1000_driver = {
2476	.probe = ecpri_cc_qdu1000_probe,
2477	.driver = {
2478		.name = "ecpri_cc-qdu1000",
2479		.of_match_table = ecpri_cc_qdu1000_match_table,
2480	},
2481};
2482
2483module_platform_driver(ecpri_cc_qdu1000_driver);
2484
2485MODULE_DESCRIPTION("QTI ECPRICC QDU1000 Driver");
2486MODULE_LICENSE("GPL");