dispcc0-sa8775p.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/module.h>
   8#include <linux/mod_devicetable.h>
   9#include <linux/platform_device.h>
  10#include <linux/pm_runtime.h>
  11#include <linux/regmap.h>
  12
  13#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
  14
  15#include "clk-alpha-pll.h"
  16#include "clk-branch.h"
  17#include "clk-pll.h"
  18#include "clk-rcg.h"
  19#include "clk-regmap.h"
  20#include "clk-regmap-divider.h"
  21#include "clk-regmap-mux.h"
  22#include "common.h"
  23#include "gdsc.h"
  24#include "reset.h"
  25
  26enum {
  27	DT_IFACE,
  28	DT_BI_TCXO,
  29	DT_BI_TCXO_AO,
  30	DT_SLEEP_CLK,
  31	DT_DP0_PHY_PLL_LINK_CLK,
  32	DT_DP0_PHY_PLL_VCO_DIV_CLK,
  33	DT_DP1_PHY_PLL_LINK_CLK,
  34	DT_DP1_PHY_PLL_VCO_DIV_CLK,
  35	DT_DSI0_PHY_PLL_OUT_BYTECLK,
  36	DT_DSI0_PHY_PLL_OUT_DSICLK,
  37	DT_DSI1_PHY_PLL_OUT_BYTECLK,
  38	DT_DSI1_PHY_PLL_OUT_DSICLK,
  39};
  40
  41enum {
  42	P_BI_TCXO,
  43	P_DP0_PHY_PLL_LINK_CLK,
  44	P_DP0_PHY_PLL_VCO_DIV_CLK,
  45	P_DP1_PHY_PLL_LINK_CLK,
  46	P_DP1_PHY_PLL_VCO_DIV_CLK,
  47	P_DSI0_PHY_PLL_OUT_BYTECLK,
  48	P_DSI0_PHY_PLL_OUT_DSICLK,
  49	P_DSI1_PHY_PLL_OUT_BYTECLK,
  50	P_DSI1_PHY_PLL_OUT_DSICLK,
  51	P_MDSS_0_DISP_CC_PLL0_OUT_MAIN,
  52	P_MDSS_0_DISP_CC_PLL1_OUT_EVEN,
  53	P_MDSS_0_DISP_CC_PLL1_OUT_MAIN,
  54	P_SLEEP_CLK,
  55};
  56
  57static const struct pll_vco lucid_evo_vco[] = {
  58	{ 249600000, 2020000000, 0 },
  59};
  60
  61static const struct alpha_pll_config mdss_0_disp_cc_pll0_config = {
  62	.l = 0x3a,
  63	.alpha = 0x9800,
  64	.config_ctl_val = 0x20485699,
  65	.config_ctl_hi_val = 0x00182261,
  66	.config_ctl_hi1_val = 0x32aa299c,
  67	.user_ctl_val = 0x00000000,
  68	.user_ctl_hi_val = 0x00400805,
  69};
  70
  71static struct clk_alpha_pll mdss_0_disp_cc_pll0 = {
  72	.offset = 0x0,
  73	.vco_table = lucid_evo_vco,
  74	.num_vco = ARRAY_SIZE(lucid_evo_vco),
  75	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  76	.clkr = {
  77		.hw.init = &(const struct clk_init_data) {
  78			.name = "mdss_0_disp_cc_pll0",
  79			.parent_data = &(const struct clk_parent_data) {
  80				.index = DT_BI_TCXO,
  81			},
  82			.num_parents = 1,
  83			.ops = &clk_alpha_pll_lucid_evo_ops,
  84		},
  85	},
  86};
  87
  88static const struct alpha_pll_config mdss_0_disp_cc_pll1_config = {
  89	.l = 0x1f,
  90	.alpha = 0x4000,
  91	.config_ctl_val = 0x20485699,
  92	.config_ctl_hi_val = 0x00182261,
  93	.config_ctl_hi1_val = 0x32aa299c,
  94	.user_ctl_val = 0x00000000,
  95	.user_ctl_hi_val = 0x00400805,
  96};
  97
  98static struct clk_alpha_pll mdss_0_disp_cc_pll1 = {
  99	.offset = 0x1000,
 100	.vco_table = lucid_evo_vco,
 101	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 102	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 103	.clkr = {
 104		.hw.init = &(const struct clk_init_data) {
 105			.name = "mdss_0_disp_cc_pll1",
 106			.parent_data = &(const struct clk_parent_data) {
 107				.index = DT_BI_TCXO,
 108			},
 109			.num_parents = 1,
 110			.ops = &clk_alpha_pll_lucid_evo_ops,
 111		},
 112	},
 113};
 114
 115static const struct parent_map disp_cc_0_parent_map_0[] = {
 116	{ P_BI_TCXO, 0 },
 117	{ P_DP0_PHY_PLL_LINK_CLK, 1 },
 118	{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
 119	{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
 120};
 121
 122static const struct clk_parent_data disp_cc_0_parent_data_0[] = {
 123	{ .index = DT_BI_TCXO },
 124	{ .index = DT_DP0_PHY_PLL_LINK_CLK },
 125	{ .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
 126	{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
 127};
 128
 129static const struct parent_map disp_cc_0_parent_map_1[] = {
 130	{ P_BI_TCXO, 0 },
 131	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
 132	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
 133	{ P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
 134	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
 135};
 136
 137static const struct clk_parent_data disp_cc_0_parent_data_1[] = {
 138	{ .index = DT_BI_TCXO },
 139	{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
 140	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
 141	{ .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
 142	{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
 143};
 144
 145static const struct parent_map disp_cc_0_parent_map_2[] = {
 146	{ P_BI_TCXO, 0 },
 147};
 148
 149static const struct clk_parent_data disp_cc_0_parent_data_2[] = {
 150	{ .index = DT_BI_TCXO },
 151};
 152
 153static const struct clk_parent_data disp_cc_0_parent_data_2_ao[] = {
 154	{ .index = DT_BI_TCXO_AO },
 155};
 156
 157static const struct parent_map disp_cc_0_parent_map_3[] = {
 158	{ P_BI_TCXO, 0 },
 159	{ P_DP0_PHY_PLL_LINK_CLK, 1 },
 160	{ P_DP1_PHY_PLL_LINK_CLK, 2 },
 161};
 162
 163static const struct clk_parent_data disp_cc_0_parent_data_3[] = {
 164	{ .index = DT_BI_TCXO },
 165	{ .index = DT_DP0_PHY_PLL_LINK_CLK },
 166	{ .index = DT_DP1_PHY_PLL_LINK_CLK },
 167};
 168
 169static const struct parent_map disp_cc_0_parent_map_4[] = {
 170	{ P_BI_TCXO, 0 },
 171	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
 172	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
 173};
 174
 175static const struct clk_parent_data disp_cc_0_parent_data_4[] = {
 176	{ .index = DT_BI_TCXO },
 177	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
 178	{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
 179};
 180
 181static const struct parent_map disp_cc_0_parent_map_5[] = {
 182	{ P_BI_TCXO, 0 },
 183	{ P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 4 },
 184	{ P_MDSS_0_DISP_CC_PLL1_OUT_EVEN, 6 },
 185};
 186
 187static const struct clk_parent_data disp_cc_0_parent_data_5[] = {
 188	{ .index = DT_BI_TCXO },
 189	{ .hw = &mdss_0_disp_cc_pll1.clkr.hw },
 190	{ .hw = &mdss_0_disp_cc_pll1.clkr.hw },
 191};
 192
 193static const struct parent_map disp_cc_0_parent_map_6[] = {
 194	{ P_BI_TCXO, 0 },
 195	{ P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 1 },
 196	{ P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 4 },
 197	{ P_MDSS_0_DISP_CC_PLL1_OUT_EVEN, 6 },
 198};
 199
 200static const struct clk_parent_data disp_cc_0_parent_data_6[] = {
 201	{ .index = DT_BI_TCXO },
 202	{ .hw = &mdss_0_disp_cc_pll0.clkr.hw },
 203	{ .hw = &mdss_0_disp_cc_pll1.clkr.hw },
 204	{ .hw = &mdss_0_disp_cc_pll1.clkr.hw },
 205};
 206
 207static const struct parent_map disp_cc_0_parent_map_7[] = {
 208	{ P_SLEEP_CLK, 0 },
 209};
 210
 211static const struct clk_parent_data disp_cc_0_parent_data_7[] = {
 212	{ .index = DT_SLEEP_CLK },
 213};
 214
 215static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_ahb_clk_src[] = {
 216	F(37500000, P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
 217	F(75000000, P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
 218	{ }
 219};
 220
 221static struct clk_rcg2 mdss_0_disp_cc_mdss_ahb_clk_src = {
 222	.cmd_rcgr = 0x824c,
 223	.mnd_width = 0,
 224	.hid_width = 5,
 225	.parent_map = disp_cc_0_parent_map_5,
 226	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_ahb_clk_src,
 227	.clkr.hw.init = &(const struct clk_init_data) {
 228		.name = "mdss_0_disp_cc_mdss_ahb_clk_src",
 229		.parent_data = disp_cc_0_parent_data_5,
 230		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_5),
 231		.flags = CLK_SET_RATE_PARENT,
 232		.ops = &clk_rcg2_shared_ops,
 233	},
 234};
 235
 236static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_byte0_clk_src[] = {
 237	F(19200000, P_BI_TCXO, 1, 0, 0),
 238	{ }
 239};
 240
 241static struct clk_rcg2 mdss_0_disp_cc_mdss_byte0_clk_src = {
 242	.cmd_rcgr = 0x80ec,
 243	.mnd_width = 0,
 244	.hid_width = 5,
 245	.parent_map = disp_cc_0_parent_map_1,
 246	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 247	.clkr.hw.init = &(const struct clk_init_data) {
 248		.name = "mdss_0_disp_cc_mdss_byte0_clk_src",
 249		.parent_data = disp_cc_0_parent_data_1,
 250		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_1),
 251		.flags = CLK_SET_RATE_PARENT,
 252		.ops = &clk_byte2_ops,
 253	},
 254};
 255
 256static struct clk_rcg2 mdss_0_disp_cc_mdss_byte1_clk_src = {
 257	.cmd_rcgr = 0x8108,
 258	.mnd_width = 0,
 259	.hid_width = 5,
 260	.parent_map = disp_cc_0_parent_map_1,
 261	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 262	.clkr.hw.init = &(const struct clk_init_data) {
 263		.name = "mdss_0_disp_cc_mdss_byte1_clk_src",
 264		.parent_data = disp_cc_0_parent_data_1,
 265		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_1),
 266		.flags = CLK_SET_RATE_PARENT,
 267		.ops = &clk_byte2_ops,
 268	},
 269};
 270
 271static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_aux_clk_src = {
 272	.cmd_rcgr = 0x81b8,
 273	.mnd_width = 0,
 274	.hid_width = 5,
 275	.parent_map = disp_cc_0_parent_map_2,
 276	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 277	.clkr.hw.init = &(const struct clk_init_data) {
 278		.name = "mdss_0_disp_cc_mdss_dptx0_aux_clk_src",
 279		.parent_data = disp_cc_0_parent_data_2,
 280		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_2),
 281		.flags = CLK_SET_RATE_PARENT,
 282		.ops = &clk_rcg2_shared_ops,
 283	},
 284};
 285
 286static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_crypto_clk_src = {
 287	.cmd_rcgr = 0x8170,
 288	.mnd_width = 0,
 289	.hid_width = 5,
 290	.parent_map = disp_cc_0_parent_map_3,
 291	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 292	.clkr.hw.init = &(const struct clk_init_data) {
 293		.name = "mdss_0_disp_cc_mdss_dptx0_crypto_clk_src",
 294		.parent_data = disp_cc_0_parent_data_3,
 295		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_3),
 296		.flags = CLK_SET_RATE_PARENT,
 297		.ops = &clk_byte2_ops,
 298	},
 299};
 300
 301static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_link_clk_src = {
 302	.cmd_rcgr = 0x8154,
 303	.mnd_width = 0,
 304	.hid_width = 5,
 305	.parent_map = disp_cc_0_parent_map_3,
 306	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 307	.clkr.hw.init = &(const struct clk_init_data) {
 308		.name = "mdss_0_disp_cc_mdss_dptx0_link_clk_src",
 309		.parent_data = disp_cc_0_parent_data_3,
 310		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_3),
 311		.flags = CLK_SET_RATE_PARENT,
 312		.ops = &clk_byte2_ops,
 313	},
 314};
 315
 316static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src = {
 317	.cmd_rcgr = 0x8188,
 318	.mnd_width = 16,
 319	.hid_width = 5,
 320	.parent_map = disp_cc_0_parent_map_0,
 321	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 322	.clkr.hw.init = &(const struct clk_init_data) {
 323		.name = "mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src",
 324		.parent_data = disp_cc_0_parent_data_0,
 325		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
 326		.flags = CLK_SET_RATE_PARENT,
 327		.ops = &clk_dp_ops,
 328	},
 329};
 330
 331static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src = {
 332	.cmd_rcgr = 0x81a0,
 333	.mnd_width = 16,
 334	.hid_width = 5,
 335	.parent_map = disp_cc_0_parent_map_0,
 336	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 337	.clkr.hw.init = &(const struct clk_init_data) {
 338		.name = "mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src",
 339		.parent_data = disp_cc_0_parent_data_0,
 340		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
 341		.flags = CLK_SET_RATE_PARENT,
 342		.ops = &clk_dp_ops,
 343	},
 344};
 345
 346static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src = {
 347	.cmd_rcgr = 0x826c,
 348	.mnd_width = 16,
 349	.hid_width = 5,
 350	.parent_map = disp_cc_0_parent_map_0,
 351	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 352	.clkr.hw.init = &(const struct clk_init_data) {
 353		.name = "mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src",
 354		.parent_data = disp_cc_0_parent_data_0,
 355		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
 356		.flags = CLK_SET_RATE_PARENT,
 357		.ops = &clk_dp_ops,
 358	},
 359};
 360
 361static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src = {
 362	.cmd_rcgr = 0x8284,
 363	.mnd_width = 16,
 364	.hid_width = 5,
 365	.parent_map = disp_cc_0_parent_map_0,
 366	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 367	.clkr.hw.init = &(const struct clk_init_data) {
 368		.name = "mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src",
 369		.parent_data = disp_cc_0_parent_data_0,
 370		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
 371		.flags = CLK_SET_RATE_PARENT,
 372		.ops = &clk_dp_ops,
 373	},
 374};
 375
 376static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_aux_clk_src = {
 377	.cmd_rcgr = 0x8234,
 378	.mnd_width = 0,
 379	.hid_width = 5,
 380	.parent_map = disp_cc_0_parent_map_2,
 381	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 382	.clkr.hw.init = &(const struct clk_init_data) {
 383		.name = "mdss_0_disp_cc_mdss_dptx1_aux_clk_src",
 384		.parent_data = disp_cc_0_parent_data_2,
 385		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_2),
 386		.flags = CLK_SET_RATE_PARENT,
 387		.ops = &clk_rcg2_shared_ops,
 388	},
 389};
 390
 391static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_crypto_clk_src = {
 392	.cmd_rcgr = 0x821c,
 393	.mnd_width = 0,
 394	.hid_width = 5,
 395	.parent_map = disp_cc_0_parent_map_3,
 396	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 397	.clkr.hw.init = &(const struct clk_init_data) {
 398		.name = "mdss_0_disp_cc_mdss_dptx1_crypto_clk_src",
 399		.parent_data = disp_cc_0_parent_data_3,
 400		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_3),
 401		.flags = CLK_SET_RATE_PARENT,
 402		.ops = &clk_byte2_ops,
 403	},
 404};
 405
 406static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_link_clk_src = {
 407	.cmd_rcgr = 0x8200,
 408	.mnd_width = 0,
 409	.hid_width = 5,
 410	.parent_map = disp_cc_0_parent_map_3,
 411	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 412	.clkr.hw.init = &(const struct clk_init_data) {
 413		.name = "mdss_0_disp_cc_mdss_dptx1_link_clk_src",
 414		.parent_data = disp_cc_0_parent_data_3,
 415		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_3),
 416		.flags = CLK_SET_RATE_PARENT,
 417		.ops = &clk_byte2_ops,
 418	},
 419};
 420
 421static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src = {
 422	.cmd_rcgr = 0x81d0,
 423	.mnd_width = 16,
 424	.hid_width = 5,
 425	.parent_map = disp_cc_0_parent_map_0,
 426	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 427	.clkr.hw.init = &(const struct clk_init_data) {
 428		.name = "mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src",
 429		.parent_data = disp_cc_0_parent_data_0,
 430		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
 431		.flags = CLK_SET_RATE_PARENT,
 432		.ops = &clk_dp_ops,
 433	},
 434};
 435
 436static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src = {
 437	.cmd_rcgr = 0x81e8,
 438	.mnd_width = 16,
 439	.hid_width = 5,
 440	.parent_map = disp_cc_0_parent_map_0,
 441	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 442	.clkr.hw.init = &(const struct clk_init_data) {
 443		.name = "mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src",
 444		.parent_data = disp_cc_0_parent_data_0,
 445		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_0),
 446		.flags = CLK_SET_RATE_PARENT,
 447		.ops = &clk_dp_ops,
 448	},
 449};
 450
 451static struct clk_rcg2 mdss_0_disp_cc_mdss_esc0_clk_src = {
 452	.cmd_rcgr = 0x8124,
 453	.mnd_width = 0,
 454	.hid_width = 5,
 455	.parent_map = disp_cc_0_parent_map_4,
 456	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 457	.clkr.hw.init = &(const struct clk_init_data) {
 458		.name = "mdss_0_disp_cc_mdss_esc0_clk_src",
 459		.parent_data = disp_cc_0_parent_data_4,
 460		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_4),
 461		.flags = CLK_SET_RATE_PARENT,
 462		.ops = &clk_rcg2_shared_ops,
 463	},
 464};
 465
 466static struct clk_rcg2 mdss_0_disp_cc_mdss_esc1_clk_src = {
 467	.cmd_rcgr = 0x813c,
 468	.mnd_width = 0,
 469	.hid_width = 5,
 470	.parent_map = disp_cc_0_parent_map_4,
 471	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 472	.clkr.hw.init = &(const struct clk_init_data) {
 473		.name = "mdss_0_disp_cc_mdss_esc1_clk_src",
 474		.parent_data = disp_cc_0_parent_data_4,
 475		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_4),
 476		.flags = CLK_SET_RATE_PARENT,
 477		.ops = &clk_rcg2_shared_ops,
 478	},
 479};
 480
 481static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_mdp_clk_src[] = {
 482	F(375000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 483	F(500000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 484	F(575000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 485	F(650000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 486	{ }
 487};
 488
 489static struct clk_rcg2 mdss_0_disp_cc_mdss_mdp_clk_src = {
 490	.cmd_rcgr = 0x80bc,
 491	.mnd_width = 0,
 492	.hid_width = 5,
 493	.parent_map = disp_cc_0_parent_map_6,
 494	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_mdp_clk_src,
 495	.clkr.hw.init = &(const struct clk_init_data) {
 496		.name = "mdss_0_disp_cc_mdss_mdp_clk_src",
 497		.parent_data = disp_cc_0_parent_data_6,
 498		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_6),
 499		.flags = CLK_SET_RATE_PARENT,
 500		.ops = &clk_rcg2_shared_ops,
 501	},
 502};
 503
 504static struct clk_rcg2 mdss_0_disp_cc_mdss_pclk0_clk_src = {
 505	.cmd_rcgr = 0x808c,
 506	.mnd_width = 8,
 507	.hid_width = 5,
 508	.parent_map = disp_cc_0_parent_map_1,
 509	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 510	.clkr.hw.init = &(const struct clk_init_data) {
 511		.name = "mdss_0_disp_cc_mdss_pclk0_clk_src",
 512		.parent_data = disp_cc_0_parent_data_1,
 513		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_1),
 514		.flags = CLK_SET_RATE_PARENT,
 515		.ops = &clk_pixel_ops,
 516	},
 517};
 518
 519static struct clk_rcg2 mdss_0_disp_cc_mdss_pclk1_clk_src = {
 520	.cmd_rcgr = 0x80a4,
 521	.mnd_width = 8,
 522	.hid_width = 5,
 523	.parent_map = disp_cc_0_parent_map_1,
 524	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 525	.clkr.hw.init = &(const struct clk_init_data) {
 526		.name = "mdss_0_disp_cc_mdss_pclk1_clk_src",
 527		.parent_data = disp_cc_0_parent_data_1,
 528		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_1),
 529		.flags = CLK_SET_RATE_PARENT,
 530		.ops = &clk_pixel_ops,
 531	},
 532};
 533
 534static struct clk_rcg2 mdss_0_disp_cc_mdss_vsync_clk_src = {
 535	.cmd_rcgr = 0x80d4,
 536	.mnd_width = 0,
 537	.hid_width = 5,
 538	.parent_map = disp_cc_0_parent_map_2,
 539	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 540	.clkr.hw.init = &(const struct clk_init_data) {
 541		.name = "mdss_0_disp_cc_mdss_vsync_clk_src",
 542		.parent_data = disp_cc_0_parent_data_2,
 543		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_2),
 544		.flags = CLK_SET_RATE_PARENT,
 545		.ops = &clk_rcg2_shared_ops,
 546	},
 547};
 548
 549static const struct freq_tbl ftbl_mdss_0_disp_cc_sleep_clk_src[] = {
 550	F(32000, P_SLEEP_CLK, 1, 0, 0),
 551	{ }
 552};
 553
 554static struct clk_rcg2 mdss_0_disp_cc_sleep_clk_src = {
 555	.cmd_rcgr = 0xc058,
 556	.mnd_width = 0,
 557	.hid_width = 5,
 558	.parent_map = disp_cc_0_parent_map_7,
 559	.freq_tbl = ftbl_mdss_0_disp_cc_sleep_clk_src,
 560	.clkr.hw.init = &(const struct clk_init_data) {
 561		.name = "mdss_0_disp_cc_sleep_clk_src",
 562		.parent_data = disp_cc_0_parent_data_7,
 563		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_7),
 564		.flags = CLK_SET_RATE_PARENT,
 565		.ops = &clk_rcg2_shared_ops,
 566	},
 567};
 568
 569static struct clk_rcg2 mdss_0_disp_cc_xo_clk_src = {
 570	.cmd_rcgr = 0xc03c,
 571	.mnd_width = 0,
 572	.hid_width = 5,
 573	.parent_map = disp_cc_0_parent_map_2,
 574	.freq_tbl = ftbl_mdss_0_disp_cc_mdss_byte0_clk_src,
 575	.clkr.hw.init = &(const struct clk_init_data) {
 576		.name = "mdss_0_disp_cc_xo_clk_src",
 577		.parent_data = disp_cc_0_parent_data_2_ao,
 578		.num_parents = ARRAY_SIZE(disp_cc_0_parent_data_2_ao),
 579		.flags = CLK_SET_RATE_PARENT,
 580		.ops = &clk_rcg2_shared_ops,
 581	},
 582};
 583
 584static struct clk_regmap_div mdss_0_disp_cc_mdss_byte0_div_clk_src = {
 585	.reg = 0x8104,
 586	.shift = 0,
 587	.width = 4,
 588	.clkr.hw.init = &(const struct clk_init_data) {
 589		.name = "mdss_0_disp_cc_mdss_byte0_div_clk_src",
 590		.parent_hws = (const struct clk_hw*[]) {
 591			&mdss_0_disp_cc_mdss_byte0_clk_src.clkr.hw,
 592		},
 593		.num_parents = 1,
 594		.flags = CLK_SET_RATE_PARENT,
 595		.ops = &clk_regmap_div_ops,
 596	},
 597};
 598
 599static struct clk_regmap_div mdss_0_disp_cc_mdss_byte1_div_clk_src = {
 600	.reg = 0x8120,
 601	.shift = 0,
 602	.width = 4,
 603	.clkr.hw.init = &(const struct clk_init_data) {
 604		.name = "mdss_0_disp_cc_mdss_byte1_div_clk_src",
 605		.parent_hws = (const struct clk_hw*[]) {
 606			&mdss_0_disp_cc_mdss_byte1_clk_src.clkr.hw,
 607		},
 608		.num_parents = 1,
 609		.flags = CLK_SET_RATE_PARENT,
 610		.ops = &clk_regmap_div_ops,
 611	},
 612};
 613
 614static struct clk_regmap_div mdss_0_disp_cc_mdss_dptx0_link_div_clk_src = {
 615	.reg = 0x816c,
 616	.shift = 0,
 617	.width = 4,
 618	.clkr.hw.init = &(const struct clk_init_data) {
 619		.name = "mdss_0_disp_cc_mdss_dptx0_link_div_clk_src",
 620		.parent_hws = (const struct clk_hw*[]) {
 621			&mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
 622		},
 623		.num_parents = 1,
 624		.flags = CLK_SET_RATE_PARENT,
 625		.ops = &clk_regmap_div_ro_ops,
 626	},
 627};
 628
 629static struct clk_regmap_div mdss_0_disp_cc_mdss_dptx1_link_div_clk_src = {
 630	.reg = 0x8218,
 631	.shift = 0,
 632	.width = 4,
 633	.clkr.hw.init = &(const struct clk_init_data) {
 634		.name = "mdss_0_disp_cc_mdss_dptx1_link_div_clk_src",
 635		.parent_hws = (const struct clk_hw*[]) {
 636			&mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
 637		},
 638		.num_parents = 1,
 639		.flags = CLK_SET_RATE_PARENT,
 640		.ops = &clk_regmap_div_ro_ops,
 641	},
 642};
 643
 644static struct clk_branch mdss_0_disp_cc_mdss_ahb1_clk = {
 645	.halt_reg = 0x8088,
 646	.halt_check = BRANCH_HALT,
 647	.clkr = {
 648		.enable_reg = 0x8088,
 649		.enable_mask = BIT(0),
 650		.hw.init = &(const struct clk_init_data) {
 651			.name = "mdss_0_disp_cc_mdss_ahb1_clk",
 652			.parent_hws = (const struct clk_hw*[]) {
 653				&mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw,
 654			},
 655			.num_parents = 1,
 656			.flags = CLK_SET_RATE_PARENT,
 657			.ops = &clk_branch2_ops,
 658		},
 659	},
 660};
 661
 662static struct clk_branch mdss_0_disp_cc_mdss_ahb_clk = {
 663	.halt_reg = 0x8084,
 664	.halt_check = BRANCH_HALT,
 665	.clkr = {
 666		.enable_reg = 0x8084,
 667		.enable_mask = BIT(0),
 668		.hw.init = &(const struct clk_init_data) {
 669			.name = "mdss_0_disp_cc_mdss_ahb_clk",
 670			.parent_hws = (const struct clk_hw*[]) {
 671				&mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw,
 672			},
 673			.num_parents = 1,
 674			.flags = CLK_SET_RATE_PARENT,
 675			.ops = &clk_branch2_ops,
 676		},
 677	},
 678};
 679
 680static struct clk_branch mdss_0_disp_cc_mdss_byte0_clk = {
 681	.halt_reg = 0x8034,
 682	.halt_check = BRANCH_HALT,
 683	.clkr = {
 684		.enable_reg = 0x8034,
 685		.enable_mask = BIT(0),
 686		.hw.init = &(const struct clk_init_data) {
 687			.name = "mdss_0_disp_cc_mdss_byte0_clk",
 688			.parent_hws = (const struct clk_hw*[]) {
 689				&mdss_0_disp_cc_mdss_byte0_clk_src.clkr.hw,
 690			},
 691			.num_parents = 1,
 692			.flags = CLK_SET_RATE_PARENT,
 693			.ops = &clk_branch2_ops,
 694		},
 695	},
 696};
 697
 698static struct clk_branch mdss_0_disp_cc_mdss_byte0_intf_clk = {
 699	.halt_reg = 0x8038,
 700	.halt_check = BRANCH_HALT,
 701	.clkr = {
 702		.enable_reg = 0x8038,
 703		.enable_mask = BIT(0),
 704		.hw.init = &(const struct clk_init_data) {
 705			.name = "mdss_0_disp_cc_mdss_byte0_intf_clk",
 706			.parent_hws = (const struct clk_hw*[]) {
 707				&mdss_0_disp_cc_mdss_byte0_div_clk_src.clkr.hw,
 708			},
 709			.num_parents = 1,
 710			.flags = CLK_SET_RATE_PARENT,
 711			.ops = &clk_branch2_ops,
 712		},
 713	},
 714};
 715
 716static struct clk_branch mdss_0_disp_cc_mdss_byte1_clk = {
 717	.halt_reg = 0x803c,
 718	.halt_check = BRANCH_HALT,
 719	.clkr = {
 720		.enable_reg = 0x803c,
 721		.enable_mask = BIT(0),
 722		.hw.init = &(const struct clk_init_data) {
 723			.name = "mdss_0_disp_cc_mdss_byte1_clk",
 724			.parent_hws = (const struct clk_hw*[]) {
 725				&mdss_0_disp_cc_mdss_byte1_clk_src.clkr.hw,
 726			},
 727			.num_parents = 1,
 728			.flags = CLK_SET_RATE_PARENT,
 729			.ops = &clk_branch2_ops,
 730		},
 731	},
 732};
 733
 734static struct clk_branch mdss_0_disp_cc_mdss_byte1_intf_clk = {
 735	.halt_reg = 0x8040,
 736	.halt_check = BRANCH_HALT,
 737	.clkr = {
 738		.enable_reg = 0x8040,
 739		.enable_mask = BIT(0),
 740		.hw.init = &(const struct clk_init_data) {
 741			.name = "mdss_0_disp_cc_mdss_byte1_intf_clk",
 742			.parent_hws = (const struct clk_hw*[]) {
 743				&mdss_0_disp_cc_mdss_byte1_div_clk_src.clkr.hw,
 744			},
 745			.num_parents = 1,
 746			.flags = CLK_SET_RATE_PARENT,
 747			.ops = &clk_branch2_ops,
 748		},
 749	},
 750};
 751
 752static struct clk_branch mdss_0_disp_cc_mdss_dptx0_aux_clk = {
 753	.halt_reg = 0x805c,
 754	.halt_check = BRANCH_HALT,
 755	.clkr = {
 756		.enable_reg = 0x805c,
 757		.enable_mask = BIT(0),
 758		.hw.init = &(const struct clk_init_data) {
 759			.name = "mdss_0_disp_cc_mdss_dptx0_aux_clk",
 760			.parent_hws = (const struct clk_hw*[]) {
 761				&mdss_0_disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
 762			},
 763			.num_parents = 1,
 764			.flags = CLK_SET_RATE_PARENT,
 765			.ops = &clk_branch2_ops,
 766		},
 767	},
 768};
 769
 770static struct clk_branch mdss_0_disp_cc_mdss_dptx0_crypto_clk = {
 771	.halt_reg = 0x8058,
 772	.halt_check = BRANCH_HALT,
 773	.clkr = {
 774		.enable_reg = 0x8058,
 775		.enable_mask = BIT(0),
 776		.hw.init = &(const struct clk_init_data) {
 777			.name = "mdss_0_disp_cc_mdss_dptx0_crypto_clk",
 778			.parent_hws = (const struct clk_hw*[]) {
 779				&mdss_0_disp_cc_mdss_dptx0_crypto_clk_src.clkr.hw,
 780			},
 781			.num_parents = 1,
 782			.flags = CLK_SET_RATE_PARENT,
 783			.ops = &clk_branch2_ops,
 784		},
 785	},
 786};
 787
 788static struct clk_branch mdss_0_disp_cc_mdss_dptx0_link_clk = {
 789	.halt_reg = 0x804c,
 790	.halt_check = BRANCH_HALT,
 791	.clkr = {
 792		.enable_reg = 0x804c,
 793		.enable_mask = BIT(0),
 794		.hw.init = &(const struct clk_init_data) {
 795			.name = "mdss_0_disp_cc_mdss_dptx0_link_clk",
 796			.parent_hws = (const struct clk_hw*[]) {
 797				&mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
 798			},
 799			.num_parents = 1,
 800			.flags = CLK_SET_RATE_PARENT,
 801			.ops = &clk_branch2_ops,
 802		},
 803	},
 804};
 805
 806static struct clk_branch mdss_0_disp_cc_mdss_dptx0_link_intf_clk = {
 807	.halt_reg = 0x8050,
 808	.halt_check = BRANCH_HALT,
 809	.clkr = {
 810		.enable_reg = 0x8050,
 811		.enable_mask = BIT(0),
 812		.hw.init = &(const struct clk_init_data) {
 813			.name = "mdss_0_disp_cc_mdss_dptx0_link_intf_clk",
 814			.parent_hws = (const struct clk_hw*[]) {
 815				&mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
 816			},
 817			.num_parents = 1,
 818			.flags = CLK_SET_RATE_PARENT,
 819			.ops = &clk_branch2_ops,
 820		},
 821	},
 822};
 823
 824static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel0_clk = {
 825	.halt_reg = 0x8060,
 826	.halt_check = BRANCH_HALT,
 827	.clkr = {
 828		.enable_reg = 0x8060,
 829		.enable_mask = BIT(0),
 830		.hw.init = &(const struct clk_init_data) {
 831			.name = "mdss_0_disp_cc_mdss_dptx0_pixel0_clk",
 832			.parent_hws = (const struct clk_hw*[]) {
 833				&mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
 834			},
 835			.num_parents = 1,
 836			.flags = CLK_SET_RATE_PARENT,
 837			.ops = &clk_branch2_ops,
 838		},
 839	},
 840};
 841
 842static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel1_clk = {
 843	.halt_reg = 0x8064,
 844	.halt_check = BRANCH_HALT,
 845	.clkr = {
 846		.enable_reg = 0x8064,
 847		.enable_mask = BIT(0),
 848		.hw.init = &(const struct clk_init_data) {
 849			.name = "mdss_0_disp_cc_mdss_dptx0_pixel1_clk",
 850			.parent_hws = (const struct clk_hw*[]) {
 851				&mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
 852			},
 853			.num_parents = 1,
 854			.flags = CLK_SET_RATE_PARENT,
 855			.ops = &clk_branch2_ops,
 856		},
 857	},
 858};
 859
 860static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel2_clk = {
 861	.halt_reg = 0x8264,
 862	.halt_check = BRANCH_HALT,
 863	.clkr = {
 864		.enable_reg = 0x8264,
 865		.enable_mask = BIT(0),
 866		.hw.init = &(const struct clk_init_data) {
 867			.name = "mdss_0_disp_cc_mdss_dptx0_pixel2_clk",
 868			.parent_hws = (const struct clk_hw*[]) {
 869				&mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src.clkr.hw,
 870			},
 871			.num_parents = 1,
 872			.flags = CLK_SET_RATE_PARENT,
 873			.ops = &clk_branch2_ops,
 874		},
 875	},
 876};
 877
 878static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel3_clk = {
 879	.halt_reg = 0x8268,
 880	.halt_check = BRANCH_HALT,
 881	.clkr = {
 882		.enable_reg = 0x8268,
 883		.enable_mask = BIT(0),
 884		.hw.init = &(const struct clk_init_data) {
 885			.name = "mdss_0_disp_cc_mdss_dptx0_pixel3_clk",
 886			.parent_hws = (const struct clk_hw*[]) {
 887				&mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src.clkr.hw,
 888			},
 889			.num_parents = 1,
 890			.flags = CLK_SET_RATE_PARENT,
 891			.ops = &clk_branch2_ops,
 892		},
 893	},
 894};
 895
 896static struct clk_branch mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
 897	.halt_reg = 0x8054,
 898	.halt_check = BRANCH_HALT,
 899	.clkr = {
 900		.enable_reg = 0x8054,
 901		.enable_mask = BIT(0),
 902		.hw.init = &(const struct clk_init_data) {
 903			.name = "mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_clk",
 904			.parent_hws = (const struct clk_hw*[]) {
 905				&mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
 906			},
 907			.num_parents = 1,
 908			.flags = CLK_SET_RATE_PARENT,
 909			.ops = &clk_branch2_ops,
 910		},
 911	},
 912};
 913
 914static struct clk_branch mdss_0_disp_cc_mdss_dptx1_aux_clk = {
 915	.halt_reg = 0x8080,
 916	.halt_check = BRANCH_HALT,
 917	.clkr = {
 918		.enable_reg = 0x8080,
 919		.enable_mask = BIT(0),
 920		.hw.init = &(const struct clk_init_data) {
 921			.name = "mdss_0_disp_cc_mdss_dptx1_aux_clk",
 922			.parent_hws = (const struct clk_hw*[]) {
 923				&mdss_0_disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
 924			},
 925			.num_parents = 1,
 926			.flags = CLK_SET_RATE_PARENT,
 927			.ops = &clk_branch2_ops,
 928		},
 929	},
 930};
 931
 932static struct clk_branch mdss_0_disp_cc_mdss_dptx1_crypto_clk = {
 933	.halt_reg = 0x807c,
 934	.halt_check = BRANCH_HALT,
 935	.clkr = {
 936		.enable_reg = 0x807c,
 937		.enable_mask = BIT(0),
 938		.hw.init = &(const struct clk_init_data) {
 939			.name = "mdss_0_disp_cc_mdss_dptx1_crypto_clk",
 940			.parent_hws = (const struct clk_hw*[]) {
 941				&mdss_0_disp_cc_mdss_dptx1_crypto_clk_src.clkr.hw,
 942			},
 943			.num_parents = 1,
 944			.flags = CLK_SET_RATE_PARENT,
 945			.ops = &clk_branch2_ops,
 946		},
 947	},
 948};
 949
 950static struct clk_branch mdss_0_disp_cc_mdss_dptx1_link_clk = {
 951	.halt_reg = 0x8070,
 952	.halt_check = BRANCH_HALT,
 953	.clkr = {
 954		.enable_reg = 0x8070,
 955		.enable_mask = BIT(0),
 956		.hw.init = &(const struct clk_init_data) {
 957			.name = "mdss_0_disp_cc_mdss_dptx1_link_clk",
 958			.parent_hws = (const struct clk_hw*[]) {
 959				&mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
 960			},
 961			.num_parents = 1,
 962			.flags = CLK_SET_RATE_PARENT,
 963			.ops = &clk_branch2_ops,
 964		},
 965	},
 966};
 967
 968static struct clk_branch mdss_0_disp_cc_mdss_dptx1_link_intf_clk = {
 969	.halt_reg = 0x8074,
 970	.halt_check = BRANCH_HALT,
 971	.clkr = {
 972		.enable_reg = 0x8074,
 973		.enable_mask = BIT(0),
 974		.hw.init = &(const struct clk_init_data) {
 975			.name = "mdss_0_disp_cc_mdss_dptx1_link_intf_clk",
 976			.parent_hws = (const struct clk_hw*[]) {
 977				&mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
 978			},
 979			.num_parents = 1,
 980			.flags = CLK_SET_RATE_PARENT,
 981			.ops = &clk_branch2_ops,
 982		},
 983	},
 984};
 985
 986static struct clk_branch mdss_0_disp_cc_mdss_dptx1_pixel0_clk = {
 987	.halt_reg = 0x8068,
 988	.halt_check = BRANCH_HALT,
 989	.clkr = {
 990		.enable_reg = 0x8068,
 991		.enable_mask = BIT(0),
 992		.hw.init = &(const struct clk_init_data) {
 993			.name = "mdss_0_disp_cc_mdss_dptx1_pixel0_clk",
 994			.parent_hws = (const struct clk_hw*[]) {
 995				&mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
 996			},
 997			.num_parents = 1,
 998			.flags = CLK_SET_RATE_PARENT,
 999			.ops = &clk_branch2_ops,
1000		},
1001	},
1002};
1003
1004static struct clk_branch mdss_0_disp_cc_mdss_dptx1_pixel1_clk = {
1005	.halt_reg = 0x806c,
1006	.halt_check = BRANCH_HALT,
1007	.clkr = {
1008		.enable_reg = 0x806c,
1009		.enable_mask = BIT(0),
1010		.hw.init = &(const struct clk_init_data) {
1011			.name = "mdss_0_disp_cc_mdss_dptx1_pixel1_clk",
1012			.parent_hws = (const struct clk_hw*[]) {
1013				&mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
1014			},
1015			.num_parents = 1,
1016			.flags = CLK_SET_RATE_PARENT,
1017			.ops = &clk_branch2_ops,
1018		},
1019	},
1020};
1021
1022static struct clk_branch mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
1023	.halt_reg = 0x8078,
1024	.halt_check = BRANCH_HALT,
1025	.clkr = {
1026		.enable_reg = 0x8078,
1027		.enable_mask = BIT(0),
1028		.hw.init = &(const struct clk_init_data) {
1029			.name = "mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_clk",
1030			.parent_hws = (const struct clk_hw*[]) {
1031				&mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1032			},
1033			.num_parents = 1,
1034			.flags = CLK_SET_RATE_PARENT,
1035			.ops = &clk_branch2_ops,
1036		},
1037	},
1038};
1039
1040static struct clk_branch mdss_0_disp_cc_mdss_esc0_clk = {
1041	.halt_reg = 0x8044,
1042	.halt_check = BRANCH_HALT,
1043	.clkr = {
1044		.enable_reg = 0x8044,
1045		.enable_mask = BIT(0),
1046		.hw.init = &(const struct clk_init_data) {
1047			.name = "mdss_0_disp_cc_mdss_esc0_clk",
1048			.parent_hws = (const struct clk_hw*[]) {
1049				&mdss_0_disp_cc_mdss_esc0_clk_src.clkr.hw,
1050			},
1051			.num_parents = 1,
1052			.flags = CLK_SET_RATE_PARENT,
1053			.ops = &clk_branch2_ops,
1054		},
1055	},
1056};
1057
1058static struct clk_branch mdss_0_disp_cc_mdss_esc1_clk = {
1059	.halt_reg = 0x8048,
1060	.halt_check = BRANCH_HALT,
1061	.clkr = {
1062		.enable_reg = 0x8048,
1063		.enable_mask = BIT(0),
1064		.hw.init = &(const struct clk_init_data) {
1065			.name = "mdss_0_disp_cc_mdss_esc1_clk",
1066			.parent_hws = (const struct clk_hw*[]) {
1067				&mdss_0_disp_cc_mdss_esc1_clk_src.clkr.hw,
1068			},
1069			.num_parents = 1,
1070			.flags = CLK_SET_RATE_PARENT,
1071			.ops = &clk_branch2_ops,
1072		},
1073	},
1074};
1075
1076static struct clk_branch mdss_0_disp_cc_mdss_mdp1_clk = {
1077	.halt_reg = 0x8014,
1078	.halt_check = BRANCH_HALT,
1079	.clkr = {
1080		.enable_reg = 0x8014,
1081		.enable_mask = BIT(0),
1082		.hw.init = &(const struct clk_init_data) {
1083			.name = "mdss_0_disp_cc_mdss_mdp1_clk",
1084			.parent_hws = (const struct clk_hw*[]) {
1085				&mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw,
1086			},
1087			.num_parents = 1,
1088			.flags = CLK_SET_RATE_PARENT,
1089			.ops = &clk_branch2_ops,
1090		},
1091	},
1092};
1093
1094static struct clk_branch mdss_0_disp_cc_mdss_mdp_clk = {
1095	.halt_reg = 0x800c,
1096	.halt_check = BRANCH_HALT,
1097	.clkr = {
1098		.enable_reg = 0x800c,
1099		.enable_mask = BIT(0),
1100		.hw.init = &(const struct clk_init_data) {
1101			.name = "mdss_0_disp_cc_mdss_mdp_clk",
1102			.parent_hws = (const struct clk_hw*[]) {
1103				&mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw,
1104			},
1105			.num_parents = 1,
1106			.flags = CLK_SET_RATE_PARENT,
1107			.ops = &clk_branch2_ops,
1108		},
1109	},
1110};
1111
1112static struct clk_branch mdss_0_disp_cc_mdss_mdp_lut1_clk = {
1113	.halt_reg = 0x8024,
1114	.halt_check = BRANCH_HALT_VOTED,
1115	.clkr = {
1116		.enable_reg = 0x8024,
1117		.enable_mask = BIT(0),
1118		.hw.init = &(const struct clk_init_data) {
1119			.name = "mdss_0_disp_cc_mdss_mdp_lut1_clk",
1120			.parent_hws = (const struct clk_hw*[]) {
1121				&mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw,
1122			},
1123			.num_parents = 1,
1124			.flags = CLK_SET_RATE_PARENT,
1125			.ops = &clk_branch2_ops,
1126		},
1127	},
1128};
1129
1130static struct clk_branch mdss_0_disp_cc_mdss_mdp_lut_clk = {
1131	.halt_reg = 0x801c,
1132	.halt_check = BRANCH_HALT_VOTED,
1133	.clkr = {
1134		.enable_reg = 0x801c,
1135		.enable_mask = BIT(0),
1136		.hw.init = &(const struct clk_init_data) {
1137			.name = "mdss_0_disp_cc_mdss_mdp_lut_clk",
1138			.parent_hws = (const struct clk_hw*[]) {
1139				&mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw,
1140			},
1141			.num_parents = 1,
1142			.flags = CLK_SET_RATE_PARENT,
1143			.ops = &clk_branch2_ops,
1144		},
1145	},
1146};
1147
1148static struct clk_branch mdss_0_disp_cc_mdss_non_gdsc_ahb_clk = {
1149	.halt_reg = 0xa004,
1150	.halt_check = BRANCH_HALT_VOTED,
1151	.clkr = {
1152		.enable_reg = 0xa004,
1153		.enable_mask = BIT(0),
1154		.hw.init = &(const struct clk_init_data) {
1155			.name = "mdss_0_disp_cc_mdss_non_gdsc_ahb_clk",
1156			.parent_hws = (const struct clk_hw*[]) {
1157				&mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw,
1158			},
1159			.num_parents = 1,
1160			.flags = CLK_SET_RATE_PARENT,
1161			.ops = &clk_branch2_ops,
1162		},
1163	},
1164};
1165
1166static struct clk_branch mdss_0_disp_cc_mdss_pclk0_clk = {
1167	.halt_reg = 0x8004,
1168	.halt_check = BRANCH_HALT,
1169	.clkr = {
1170		.enable_reg = 0x8004,
1171		.enable_mask = BIT(0),
1172		.hw.init = &(const struct clk_init_data) {
1173			.name = "mdss_0_disp_cc_mdss_pclk0_clk",
1174			.parent_hws = (const struct clk_hw*[]) {
1175				&mdss_0_disp_cc_mdss_pclk0_clk_src.clkr.hw,
1176			},
1177			.num_parents = 1,
1178			.flags = CLK_SET_RATE_PARENT,
1179			.ops = &clk_branch2_ops,
1180		},
1181	},
1182};
1183
1184static struct clk_branch mdss_0_disp_cc_mdss_pclk1_clk = {
1185	.halt_reg = 0x8008,
1186	.halt_check = BRANCH_HALT,
1187	.clkr = {
1188		.enable_reg = 0x8008,
1189		.enable_mask = BIT(0),
1190		.hw.init = &(const struct clk_init_data) {
1191			.name = "mdss_0_disp_cc_mdss_pclk1_clk",
1192			.parent_hws = (const struct clk_hw*[]) {
1193				&mdss_0_disp_cc_mdss_pclk1_clk_src.clkr.hw,
1194			},
1195			.num_parents = 1,
1196			.flags = CLK_SET_RATE_PARENT,
1197			.ops = &clk_branch2_ops,
1198		},
1199	},
1200};
1201
1202static struct clk_branch mdss_0_disp_cc_mdss_pll_lock_monitor_clk = {
1203	.halt_reg = 0xe000,
1204	.halt_check = BRANCH_HALT,
1205	.clkr = {
1206		.enable_reg = 0xe000,
1207		.enable_mask = BIT(0),
1208		.hw.init = &(const struct clk_init_data) {
1209			.name = "mdss_0_disp_cc_mdss_pll_lock_monitor_clk",
1210			.parent_hws = (const struct clk_hw*[]) {
1211				&mdss_0_disp_cc_xo_clk_src.clkr.hw,
1212			},
1213			.num_parents = 1,
1214			.flags = CLK_SET_RATE_PARENT,
1215			.ops = &clk_branch2_ops,
1216		},
1217	},
1218};
1219
1220static struct clk_branch mdss_0_disp_cc_mdss_rscc_ahb_clk = {
1221	.halt_reg = 0xa00c,
1222	.halt_check = BRANCH_HALT,
1223	.clkr = {
1224		.enable_reg = 0xa00c,
1225		.enable_mask = BIT(0),
1226		.hw.init = &(const struct clk_init_data) {
1227			.name = "mdss_0_disp_cc_mdss_rscc_ahb_clk",
1228			.parent_hws = (const struct clk_hw*[]) {
1229				&mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw,
1230			},
1231			.num_parents = 1,
1232			.flags = CLK_SET_RATE_PARENT,
1233			.ops = &clk_branch2_ops,
1234		},
1235	},
1236};
1237
1238static struct clk_branch mdss_0_disp_cc_mdss_rscc_vsync_clk = {
1239	.halt_reg = 0xa008,
1240	.halt_check = BRANCH_HALT,
1241	.clkr = {
1242		.enable_reg = 0xa008,
1243		.enable_mask = BIT(0),
1244		.hw.init = &(const struct clk_init_data) {
1245			.name = "mdss_0_disp_cc_mdss_rscc_vsync_clk",
1246			.parent_hws = (const struct clk_hw*[]) {
1247				&mdss_0_disp_cc_mdss_vsync_clk_src.clkr.hw,
1248			},
1249			.num_parents = 1,
1250			.flags = CLK_SET_RATE_PARENT,
1251			.ops = &clk_branch2_ops,
1252		},
1253	},
1254};
1255
1256static struct clk_branch mdss_0_disp_cc_mdss_vsync1_clk = {
1257	.halt_reg = 0x8030,
1258	.halt_check = BRANCH_HALT,
1259	.clkr = {
1260		.enable_reg = 0x8030,
1261		.enable_mask = BIT(0),
1262		.hw.init = &(const struct clk_init_data) {
1263			.name = "mdss_0_disp_cc_mdss_vsync1_clk",
1264			.parent_hws = (const struct clk_hw*[]) {
1265				&mdss_0_disp_cc_mdss_vsync_clk_src.clkr.hw,
1266			},
1267			.num_parents = 1,
1268			.flags = CLK_SET_RATE_PARENT,
1269			.ops = &clk_branch2_ops,
1270		},
1271	},
1272};
1273
1274static struct clk_branch mdss_0_disp_cc_mdss_vsync_clk = {
1275	.halt_reg = 0x802c,
1276	.halt_check = BRANCH_HALT,
1277	.clkr = {
1278		.enable_reg = 0x802c,
1279		.enable_mask = BIT(0),
1280		.hw.init = &(const struct clk_init_data) {
1281			.name = "mdss_0_disp_cc_mdss_vsync_clk",
1282			.parent_hws = (const struct clk_hw*[]) {
1283				&mdss_0_disp_cc_mdss_vsync_clk_src.clkr.hw,
1284			},
1285			.num_parents = 1,
1286			.flags = CLK_SET_RATE_PARENT,
1287			.ops = &clk_branch2_ops,
1288		},
1289	},
1290};
1291
1292static struct clk_branch mdss_0_disp_cc_sm_obs_clk = {
1293	.halt_reg = 0x11014,
1294	.halt_check = BRANCH_HALT_SKIP,
1295	.clkr = {
1296		.enable_reg = 0x11014,
1297		.enable_mask = BIT(0),
1298		.hw.init = &(const struct clk_init_data) {
1299			.name = "mdss_0_disp_cc_sm_obs_clk",
1300			.ops = &clk_branch2_ops,
1301		},
1302	},
1303};
1304
1305static struct gdsc mdss_0_disp_cc_mdss_core_gdsc = {
1306	.gdscr = 0x9000,
1307	.en_rest_wait_val = 0x2,
1308	.en_few_wait_val = 0x2,
1309	.clk_dis_wait_val = 0xf,
1310	.pd = {
1311		.name = "mdss_0_disp_cc_mdss_core_gdsc",
1312	},
1313	.pwrsts = PWRSTS_OFF_ON,
1314	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
1315};
1316
1317static struct gdsc mdss_0_disp_cc_mdss_core_int2_gdsc = {
1318	.gdscr = 0xd000,
1319	.en_rest_wait_val = 0x2,
1320	.en_few_wait_val = 0x2,
1321	.clk_dis_wait_val = 0xf,
1322	.pd = {
1323		.name = "mdss_0_disp_cc_mdss_core_int2_gdsc",
1324	},
1325	.pwrsts = PWRSTS_OFF_ON,
1326	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
1327};
1328
1329static struct clk_regmap *disp_cc_0_sa8775p_clocks[] = {
1330	[MDSS_DISP_CC_MDSS_AHB1_CLK] = &mdss_0_disp_cc_mdss_ahb1_clk.clkr,
1331	[MDSS_DISP_CC_MDSS_AHB_CLK] = &mdss_0_disp_cc_mdss_ahb_clk.clkr,
1332	[MDSS_DISP_CC_MDSS_AHB_CLK_SRC] = &mdss_0_disp_cc_mdss_ahb_clk_src.clkr,
1333	[MDSS_DISP_CC_MDSS_BYTE0_CLK] = &mdss_0_disp_cc_mdss_byte0_clk.clkr,
1334	[MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC] = &mdss_0_disp_cc_mdss_byte0_clk_src.clkr,
1335	[MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &mdss_0_disp_cc_mdss_byte0_div_clk_src.clkr,
1336	[MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK] = &mdss_0_disp_cc_mdss_byte0_intf_clk.clkr,
1337	[MDSS_DISP_CC_MDSS_BYTE1_CLK] = &mdss_0_disp_cc_mdss_byte1_clk.clkr,
1338	[MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC] = &mdss_0_disp_cc_mdss_byte1_clk_src.clkr,
1339	[MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &mdss_0_disp_cc_mdss_byte1_div_clk_src.clkr,
1340	[MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK] = &mdss_0_disp_cc_mdss_byte1_intf_clk.clkr,
1341	[MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK] = &mdss_0_disp_cc_mdss_dptx0_aux_clk.clkr,
1342	[MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_aux_clk_src.clkr,
1343	[MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &mdss_0_disp_cc_mdss_dptx0_crypto_clk.clkr,
1344	[MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_crypto_clk_src.clkr,
1345	[MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK] = &mdss_0_disp_cc_mdss_dptx0_link_clk.clkr,
1346	[MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr,
1347	[MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] =
1348	      &mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr,
1349	[MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &mdss_0_disp_cc_mdss_dptx0_link_intf_clk.clkr,
1350	[MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &mdss_0_disp_cc_mdss_dptx0_pixel0_clk.clkr,
1351	[MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
1352	[MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &mdss_0_disp_cc_mdss_dptx0_pixel1_clk.clkr,
1353	[MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
1354	[MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK] = &mdss_0_disp_cc_mdss_dptx0_pixel2_clk.clkr,
1355	[MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src.clkr,
1356	[MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK] = &mdss_0_disp_cc_mdss_dptx0_pixel3_clk.clkr,
1357	[MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src.clkr,
1358	[MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
1359	      &mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
1360	[MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK] = &mdss_0_disp_cc_mdss_dptx1_aux_clk.clkr,
1361	[MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_aux_clk_src.clkr,
1362	[MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &mdss_0_disp_cc_mdss_dptx1_crypto_clk.clkr,
1363	[MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_crypto_clk_src.clkr,
1364	[MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK] = &mdss_0_disp_cc_mdss_dptx1_link_clk.clkr,
1365	[MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr,
1366	[MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] =
1367	      &mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr,
1368	[MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &mdss_0_disp_cc_mdss_dptx1_link_intf_clk.clkr,
1369	[MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &mdss_0_disp_cc_mdss_dptx1_pixel0_clk.clkr,
1370	[MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
1371	[MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &mdss_0_disp_cc_mdss_dptx1_pixel1_clk.clkr,
1372	[MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
1373	[MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
1374	      &mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
1375	[MDSS_DISP_CC_MDSS_ESC0_CLK] = &mdss_0_disp_cc_mdss_esc0_clk.clkr,
1376	[MDSS_DISP_CC_MDSS_ESC0_CLK_SRC] = &mdss_0_disp_cc_mdss_esc0_clk_src.clkr,
1377	[MDSS_DISP_CC_MDSS_ESC1_CLK] = &mdss_0_disp_cc_mdss_esc1_clk.clkr,
1378	[MDSS_DISP_CC_MDSS_ESC1_CLK_SRC] = &mdss_0_disp_cc_mdss_esc1_clk_src.clkr,
1379	[MDSS_DISP_CC_MDSS_MDP1_CLK] = &mdss_0_disp_cc_mdss_mdp1_clk.clkr,
1380	[MDSS_DISP_CC_MDSS_MDP_CLK] = &mdss_0_disp_cc_mdss_mdp_clk.clkr,
1381	[MDSS_DISP_CC_MDSS_MDP_CLK_SRC] = &mdss_0_disp_cc_mdss_mdp_clk_src.clkr,
1382	[MDSS_DISP_CC_MDSS_MDP_LUT1_CLK] = &mdss_0_disp_cc_mdss_mdp_lut1_clk.clkr,
1383	[MDSS_DISP_CC_MDSS_MDP_LUT_CLK] = &mdss_0_disp_cc_mdss_mdp_lut_clk.clkr,
1384	[MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &mdss_0_disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1385	[MDSS_DISP_CC_MDSS_PCLK0_CLK] = &mdss_0_disp_cc_mdss_pclk0_clk.clkr,
1386	[MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC] = &mdss_0_disp_cc_mdss_pclk0_clk_src.clkr,
1387	[MDSS_DISP_CC_MDSS_PCLK1_CLK] = &mdss_0_disp_cc_mdss_pclk1_clk.clkr,
1388	[MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC] = &mdss_0_disp_cc_mdss_pclk1_clk_src.clkr,
1389	[MDSS_DISP_CC_MDSS_PLL_LOCK_MONITOR_CLK] = &mdss_0_disp_cc_mdss_pll_lock_monitor_clk.clkr,
1390	[MDSS_DISP_CC_MDSS_RSCC_AHB_CLK] = &mdss_0_disp_cc_mdss_rscc_ahb_clk.clkr,
1391	[MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK] = &mdss_0_disp_cc_mdss_rscc_vsync_clk.clkr,
1392	[MDSS_DISP_CC_MDSS_VSYNC1_CLK] = &mdss_0_disp_cc_mdss_vsync1_clk.clkr,
1393	[MDSS_DISP_CC_MDSS_VSYNC_CLK] = &mdss_0_disp_cc_mdss_vsync_clk.clkr,
1394	[MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC] = &mdss_0_disp_cc_mdss_vsync_clk_src.clkr,
1395	[MDSS_DISP_CC_PLL0] = &mdss_0_disp_cc_pll0.clkr,
1396	[MDSS_DISP_CC_PLL1] = &mdss_0_disp_cc_pll1.clkr,
1397	[MDSS_DISP_CC_SLEEP_CLK_SRC] = &mdss_0_disp_cc_sleep_clk_src.clkr,
1398	[MDSS_DISP_CC_SM_OBS_CLK] = &mdss_0_disp_cc_sm_obs_clk.clkr,
1399	[MDSS_DISP_CC_XO_CLK_SRC] = &mdss_0_disp_cc_xo_clk_src.clkr,
1400};
1401
1402static struct gdsc *disp_cc_0_sa8775p_gdscs[] = {
1403	[MDSS_DISP_CC_MDSS_CORE_GDSC] = &mdss_0_disp_cc_mdss_core_gdsc,
1404	[MDSS_DISP_CC_MDSS_CORE_INT2_GDSC] = &mdss_0_disp_cc_mdss_core_int2_gdsc,
1405};
1406
1407static const struct qcom_reset_map disp_cc_0_sa8775p_resets[] = {
1408	[MDSS_DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1409	[MDSS_DISP_CC_MDSS_RSCC_BCR] = { 0xa000 },
1410};
1411
1412static const struct regmap_config disp_cc_0_sa8775p_regmap_config = {
1413	.reg_bits = 32,
1414	.reg_stride = 4,
1415	.val_bits = 32,
1416	.max_register = 0x12414,
1417	.fast_io = true,
1418};
1419
1420static const struct qcom_cc_desc disp_cc_0_sa8775p_desc = {
1421	.config = &disp_cc_0_sa8775p_regmap_config,
1422	.clks = disp_cc_0_sa8775p_clocks,
1423	.num_clks = ARRAY_SIZE(disp_cc_0_sa8775p_clocks),
1424	.resets = disp_cc_0_sa8775p_resets,
1425	.num_resets = ARRAY_SIZE(disp_cc_0_sa8775p_resets),
1426	.gdscs = disp_cc_0_sa8775p_gdscs,
1427	.num_gdscs = ARRAY_SIZE(disp_cc_0_sa8775p_gdscs),
1428};
1429
1430static const struct of_device_id disp_cc_0_sa8775p_match_table[] = {
1431	{ .compatible = "qcom,sa8775p-dispcc0" },
1432	{ }
1433};
1434MODULE_DEVICE_TABLE(of, disp_cc_0_sa8775p_match_table);
1435
1436static int disp_cc_0_sa8775p_probe(struct platform_device *pdev)
1437{
1438	struct regmap *regmap;
1439	int ret;
1440
1441	ret = devm_pm_runtime_enable(&pdev->dev);
1442	if (ret)
1443		return ret;
1444
1445	ret = pm_runtime_resume_and_get(&pdev->dev);
1446	if (ret)
1447		return ret;
1448
1449	regmap = qcom_cc_map(pdev, &disp_cc_0_sa8775p_desc);
1450	if (IS_ERR(regmap)) {
1451		pm_runtime_put(&pdev->dev);
1452		return PTR_ERR(regmap);
1453	}
1454
1455	clk_lucid_evo_pll_configure(&mdss_0_disp_cc_pll0, regmap, &mdss_0_disp_cc_pll0_config);
1456	clk_lucid_evo_pll_configure(&mdss_0_disp_cc_pll1, regmap, &mdss_0_disp_cc_pll1_config);
1457
1458	/* Keep some clocks always enabled */
1459	qcom_branch_set_clk_en(regmap, 0xc070); /* MDSS_0_DISP_CC_SLEEP_CLK */
1460	qcom_branch_set_clk_en(regmap, 0xc054); /* MDSS_0_DISP_CC_XO_CLK */
1461
1462	ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_0_sa8775p_desc, regmap);
1463
1464	pm_runtime_put(&pdev->dev);
1465
1466	return ret;
1467}
1468
1469static struct platform_driver disp_cc_0_sa8775p_driver = {
1470	.probe = disp_cc_0_sa8775p_probe,
1471	.driver = {
1472		.name = "dispcc0-sa8775p",
1473		.of_match_table = disp_cc_0_sa8775p_match_table,
1474	},
1475};
1476
1477module_platform_driver(disp_cc_0_sa8775p_driver);
1478
1479MODULE_DESCRIPTION("QTI DISPCC0 SA8775P Driver");
1480MODULE_LICENSE("GPL");