dispcc-sm8750.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2023-2024, Linaro Ltd.
   5 */
   6
   7#include <linux/clk-provider.h>
   8#include <linux/err.h>
   9#include <linux/kernel.h>
  10#include <linux/mod_devicetable.h>
  11#include <linux/module.h>
  12#include <linux/platform_device.h>
  13#include <linux/regmap.h>
  14#include <linux/pm_runtime.h>
  15
  16#include <dt-bindings/clock/qcom,sm8750-dispcc.h>
  17
  18#include "common.h"
  19#include "clk-alpha-pll.h"
  20#include "clk-branch.h"
  21#include "clk-pll.h"
  22#include "clk-rcg.h"
  23#include "clk-regmap.h"
  24#include "clk-regmap-divider.h"
  25#include "clk-regmap-mux.h"
  26#include "reset.h"
  27#include "gdsc.h"
  28
  29/* Need to match the order of clocks in DT binding */
  30enum {
  31	DT_BI_TCXO,
  32	DT_BI_TCXO_AO,
  33	DT_AHB_CLK,
  34	DT_SLEEP_CLK,
  35
  36	DT_DSI0_PHY_PLL_OUT_BYTECLK,
  37	DT_DSI0_PHY_PLL_OUT_DSICLK,
  38	DT_DSI1_PHY_PLL_OUT_BYTECLK,
  39	DT_DSI1_PHY_PLL_OUT_DSICLK,
  40
  41	DT_DP0_PHY_PLL_LINK_CLK,
  42	DT_DP0_PHY_PLL_VCO_DIV_CLK,
  43	DT_DP1_PHY_PLL_LINK_CLK,
  44	DT_DP1_PHY_PLL_VCO_DIV_CLK,
  45	DT_DP2_PHY_PLL_LINK_CLK,
  46	DT_DP2_PHY_PLL_VCO_DIV_CLK,
  47	DT_DP3_PHY_PLL_LINK_CLK,
  48	DT_DP3_PHY_PLL_VCO_DIV_CLK,
  49};
  50
  51#define DISP_CC_MISC_CMD	0xF000
  52
  53enum {
  54	P_BI_TCXO,
  55	P_DISP_CC_PLL0_OUT_MAIN,
  56	P_DISP_CC_PLL1_OUT_EVEN,
  57	P_DISP_CC_PLL1_OUT_MAIN,
  58	P_DISP_CC_PLL2_OUT_MAIN,
  59	P_DP0_PHY_PLL_LINK_CLK,
  60	P_DP0_PHY_PLL_VCO_DIV_CLK,
  61	P_DP1_PHY_PLL_LINK_CLK,
  62	P_DP1_PHY_PLL_VCO_DIV_CLK,
  63	P_DP2_PHY_PLL_LINK_CLK,
  64	P_DP2_PHY_PLL_VCO_DIV_CLK,
  65	P_DP3_PHY_PLL_LINK_CLK,
  66	P_DP3_PHY_PLL_VCO_DIV_CLK,
  67	P_DSI0_PHY_PLL_OUT_BYTECLK,
  68	P_DSI0_PHY_PLL_OUT_DSICLK,
  69	P_DSI1_PHY_PLL_OUT_BYTECLK,
  70	P_DSI1_PHY_PLL_OUT_DSICLK,
  71	P_SLEEP_CLK,
  72};
  73
  74static const struct pll_vco pongo_elu_vco[] = {
  75	{ 38400000, 38400000, 0 },
  76};
  77
  78static const struct pll_vco taycan_elu_vco[] = {
  79	{ 249600000, 2500000000, 0 },
  80};
  81
  82static struct alpha_pll_config disp_cc_pll0_config = {
  83	.l = 0xd,
  84	.alpha = 0x6492,
  85	.config_ctl_val = 0x19660387,
  86	.config_ctl_hi_val = 0x098060a0,
  87	.config_ctl_hi1_val = 0xb416cb20,
  88	.user_ctl_val = 0x00000000,
  89	.user_ctl_hi_val = 0x00000002,
  90};
  91
  92static struct clk_alpha_pll disp_cc_pll0 = {
  93	.offset = 0x0,
  94	.vco_table = taycan_elu_vco,
  95	.num_vco = ARRAY_SIZE(taycan_elu_vco),
  96	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
  97	.clkr = {
  98		.hw.init = &(const struct clk_init_data) {
  99			.name = "disp_cc_pll0",
 100			.parent_data = &(const struct clk_parent_data) {
 101				.index = DT_BI_TCXO,
 102			},
 103			.num_parents = 1,
 104			.ops = &clk_alpha_pll_taycan_elu_ops,
 105		},
 106	},
 107};
 108
 109static struct alpha_pll_config disp_cc_pll1_config = {
 110	.l = 0x1f,
 111	.alpha = 0x4000,
 112	.config_ctl_val = 0x19660387,
 113	.config_ctl_hi_val = 0x098060a0,
 114	.config_ctl_hi1_val = 0xb416cb20,
 115	.user_ctl_val = 0x00000000,
 116	.user_ctl_hi_val = 0x00000002,
 117};
 118
 119static struct clk_alpha_pll disp_cc_pll1 = {
 120	.offset = 0x1000,
 121	.vco_table = taycan_elu_vco,
 122	.num_vco = ARRAY_SIZE(taycan_elu_vco),
 123	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
 124	.clkr = {
 125		.hw.init = &(const struct clk_init_data) {
 126			.name = "disp_cc_pll1",
 127			.parent_data = &(const struct clk_parent_data) {
 128				.index = DT_BI_TCXO,
 129			},
 130			.num_parents = 1,
 131			.ops = &clk_alpha_pll_taycan_elu_ops,
 132		},
 133	},
 134};
 135
 136static const struct alpha_pll_config disp_cc_pll2_config = {
 137	.l = 0x493,
 138	.alpha = 0x0,
 139	.config_ctl_val = 0x60000f68,
 140	.config_ctl_hi_val = 0x0001c808,
 141	.config_ctl_hi1_val = 0x00000000,
 142	.config_ctl_hi2_val = 0x040082f4,
 143	.test_ctl_val = 0x00008000,
 144	.test_ctl_hi_val = 0x0080c496,
 145	.test_ctl_hi1_val = 0x40100180,
 146	.test_ctl_hi2_val = 0x441001bc,
 147	.test_ctl_hi3_val = 0x002003d8,
 148	.user_ctl_val = 0x00000400,
 149	.user_ctl_hi_val = 0x00e50302,
 150};
 151
 152static struct clk_alpha_pll disp_cc_pll2 = {
 153	.offset = 0x2000,
 154	.vco_table = pongo_elu_vco,
 155	.num_vco = ARRAY_SIZE(pongo_elu_vco),
 156	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_PONGO_ELU],
 157	.clkr = {
 158		.hw.init = &(const struct clk_init_data) {
 159			.name = "disp_cc_pll2",
 160			.parent_data = &(const struct clk_parent_data) {
 161				.index = DT_SLEEP_CLK,
 162			},
 163			.num_parents = 1,
 164			.ops = &clk_alpha_pll_pongo_elu_ops,
 165		},
 166	},
 167};
 168
 169static const struct parent_map disp_cc_parent_map_0[] = {
 170	{ P_BI_TCXO, 0 },
 171};
 172
 173static const struct clk_parent_data disp_cc_parent_data_0[] = {
 174	{ .index = DT_BI_TCXO },
 175};
 176
 177static const struct clk_parent_data disp_cc_parent_data_0_ao[] = {
 178	{ .index = DT_BI_TCXO_AO },
 179};
 180
 181static const struct parent_map disp_cc_parent_map_1[] = {
 182	{ P_BI_TCXO, 0 },
 183	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
 184	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
 185	{ P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
 186	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
 187};
 188
 189static const struct clk_parent_data disp_cc_parent_data_1[] = {
 190	{ .index = DT_BI_TCXO },
 191	{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
 192	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
 193	{ .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
 194	{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
 195};
 196
 197static const struct parent_map disp_cc_parent_map_2[] = {
 198	{ P_BI_TCXO, 0 },
 199	{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
 200	{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
 201	{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
 202};
 203
 204static const struct clk_parent_data disp_cc_parent_data_2[] = {
 205	{ .index = DT_BI_TCXO },
 206	{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
 207	{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
 208	{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
 209};
 210
 211static const struct parent_map disp_cc_parent_map_3[] = {
 212	{ P_BI_TCXO, 0 },
 213	{ P_DP1_PHY_PLL_LINK_CLK, 2 },
 214	{ P_DP2_PHY_PLL_LINK_CLK, 3 },
 215	{ P_DP3_PHY_PLL_LINK_CLK, 4 },
 216};
 217
 218static const struct clk_parent_data disp_cc_parent_data_3[] = {
 219	{ .index = DT_BI_TCXO },
 220	{ .index = DT_DP1_PHY_PLL_LINK_CLK },
 221	{ .index = DT_DP2_PHY_PLL_LINK_CLK },
 222	{ .index = DT_DP3_PHY_PLL_LINK_CLK },
 223};
 224
 225static const struct parent_map disp_cc_parent_map_4[] = {
 226	{ P_BI_TCXO, 0 },
 227	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
 228	{ P_DISP_CC_PLL2_OUT_MAIN, 2 },
 229	{ P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
 230};
 231
 232static const struct clk_parent_data disp_cc_parent_data_4[] = {
 233	{ .index = DT_BI_TCXO },
 234	{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
 235	{ .hw = &disp_cc_pll2.clkr.hw },
 236	{ .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
 237};
 238
 239static const struct parent_map disp_cc_parent_map_5[] = {
 240	{ P_BI_TCXO, 0 },
 241	{ P_DP0_PHY_PLL_LINK_CLK, 1 },
 242	{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
 243	{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
 244	{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
 245	{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
 246};
 247
 248static const struct clk_parent_data disp_cc_parent_data_5[] = {
 249	{ .index = DT_BI_TCXO },
 250	{ .index = DT_DP0_PHY_PLL_LINK_CLK },
 251	{ .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
 252	{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
 253	{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
 254	{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
 255};
 256
 257static const struct parent_map disp_cc_parent_map_6[] = {
 258	{ P_BI_TCXO, 0 },
 259	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
 260	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
 261};
 262
 263static const struct clk_parent_data disp_cc_parent_data_6[] = {
 264	{ .index = DT_BI_TCXO },
 265	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
 266	{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
 267};
 268
 269static const struct parent_map disp_cc_parent_map_7[] = {
 270	{ P_BI_TCXO, 0 },
 271	{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
 272	{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
 273};
 274
 275static const struct clk_parent_data disp_cc_parent_data_7[] = {
 276	{ .index = DT_BI_TCXO },
 277	{ .hw = &disp_cc_pll1.clkr.hw },
 278	{ .hw = &disp_cc_pll1.clkr.hw },
 279};
 280
 281static const struct parent_map disp_cc_parent_map_8[] = {
 282	{ P_BI_TCXO, 0 },
 283	{ P_DP0_PHY_PLL_LINK_CLK, 1 },
 284	{ P_DP1_PHY_PLL_LINK_CLK, 2 },
 285	{ P_DP2_PHY_PLL_LINK_CLK, 3 },
 286	{ P_DP3_PHY_PLL_LINK_CLK, 4 },
 287};
 288
 289static const struct clk_parent_data disp_cc_parent_data_8[] = {
 290	{ .index = DT_BI_TCXO },
 291	{ .index = DT_DP0_PHY_PLL_LINK_CLK },
 292	{ .index = DT_DP1_PHY_PLL_LINK_CLK },
 293	{ .index = DT_DP2_PHY_PLL_LINK_CLK },
 294	{ .index = DT_DP3_PHY_PLL_LINK_CLK },
 295};
 296
 297static const struct parent_map disp_cc_parent_map_9[] = {
 298	{ P_BI_TCXO, 0 },
 299	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
 300	{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
 301	{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
 302};
 303
 304static const struct clk_parent_data disp_cc_parent_data_9[] = {
 305	{ .index = DT_BI_TCXO },
 306	{ .hw = &disp_cc_pll0.clkr.hw },
 307	{ .hw = &disp_cc_pll1.clkr.hw },
 308	{ .hw = &disp_cc_pll1.clkr.hw },
 309};
 310
 311static const struct parent_map disp_cc_parent_map_10[] = {
 312	{ P_BI_TCXO, 0 },
 313	{ P_DISP_CC_PLL2_OUT_MAIN, 2 },
 314};
 315
 316static const struct clk_parent_data disp_cc_parent_data_10[] = {
 317	{ .index = DT_BI_TCXO },
 318	{ .hw = &disp_cc_pll2.clkr.hw },
 319};
 320
 321static const struct parent_map disp_cc_parent_map_11[] = {
 322	{ P_SLEEP_CLK, 0 },
 323};
 324
 325static const struct clk_parent_data disp_cc_parent_data_11[] = {
 326	{ .index = DT_SLEEP_CLK },
 327};
 328
 329static const struct freq_tbl ftbl_disp_cc_esync0_clk_src[] = {
 330	F(19200000, P_BI_TCXO, 1, 0, 0),
 331	{ }
 332};
 333
 334static struct clk_rcg2 disp_cc_esync0_clk_src = {
 335	.cmd_rcgr = 0x80c0,
 336	.mnd_width = 16,
 337	.hid_width = 5,
 338	.parent_map = disp_cc_parent_map_4,
 339	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 340	.clkr.hw.init = &(const struct clk_init_data) {
 341		.name = "disp_cc_esync0_clk_src",
 342		.parent_data = disp_cc_parent_data_4,
 343		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
 344		.flags = CLK_SET_RATE_PARENT,
 345		.ops = &clk_byte2_ops,
 346	},
 347};
 348
 349static struct clk_rcg2 disp_cc_esync1_clk_src = {
 350	.cmd_rcgr = 0x80d8,
 351	.mnd_width = 16,
 352	.hid_width = 5,
 353	.parent_map = disp_cc_parent_map_4,
 354	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 355	.clkr.hw.init = &(const struct clk_init_data) {
 356		.name = "disp_cc_esync1_clk_src",
 357		.parent_data = disp_cc_parent_data_4,
 358		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
 359		.flags = CLK_SET_RATE_PARENT,
 360		.ops = &clk_byte2_ops,
 361	},
 362};
 363
 364static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
 365	F(19200000, P_BI_TCXO, 1, 0, 0),
 366	F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
 367	F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
 368	{ }
 369};
 370
 371static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
 372	.cmd_rcgr = 0x8360,
 373	.mnd_width = 0,
 374	.hid_width = 5,
 375	.parent_map = disp_cc_parent_map_7,
 376	.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
 377	.clkr.hw.init = &(const struct clk_init_data) {
 378		.name = "disp_cc_mdss_ahb_clk_src",
 379		.parent_data = disp_cc_parent_data_7,
 380		.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
 381		.flags = CLK_SET_RATE_PARENT,
 382		.ops = &clk_rcg2_shared_ops,
 383	},
 384};
 385
 386static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
 387	.cmd_rcgr = 0x8180,
 388	.mnd_width = 0,
 389	.hid_width = 5,
 390	.parent_map = disp_cc_parent_map_1,
 391	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 392	.clkr.hw.init = &(const struct clk_init_data) {
 393		.name = "disp_cc_mdss_byte0_clk_src",
 394		.parent_data = disp_cc_parent_data_1,
 395		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 396		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 397		.ops = &clk_byte2_ops,
 398	},
 399};
 400
 401static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
 402	.cmd_rcgr = 0x819c,
 403	.mnd_width = 0,
 404	.hid_width = 5,
 405	.parent_map = disp_cc_parent_map_1,
 406	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 407	.clkr.hw.init = &(const struct clk_init_data) {
 408		.name = "disp_cc_mdss_byte1_clk_src",
 409		.parent_data = disp_cc_parent_data_1,
 410		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 411		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 412		.ops = &clk_byte2_ops,
 413	},
 414};
 415
 416static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
 417	.cmd_rcgr = 0x8234,
 418	.mnd_width = 0,
 419	.hid_width = 5,
 420	.parent_map = disp_cc_parent_map_0,
 421	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 422	.clkr.hw.init = &(const struct clk_init_data) {
 423		.name = "disp_cc_mdss_dptx0_aux_clk_src",
 424		.parent_data = disp_cc_parent_data_0,
 425		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 426		.flags = CLK_SET_RATE_PARENT,
 427		.ops = &clk_rcg2_ops,
 428	},
 429};
 430
 431static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
 432	.cmd_rcgr = 0x81e8,
 433	.mnd_width = 0,
 434	.hid_width = 5,
 435	.parent_map = disp_cc_parent_map_8,
 436	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 437	.clkr.hw.init = &(const struct clk_init_data) {
 438		.name = "disp_cc_mdss_dptx0_link_clk_src",
 439		.parent_data = disp_cc_parent_data_8,
 440		.num_parents = ARRAY_SIZE(disp_cc_parent_data_8),
 441		.flags = CLK_SET_RATE_PARENT,
 442		.ops = &clk_byte2_ops,
 443	},
 444};
 445
 446static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
 447	.cmd_rcgr = 0x8204,
 448	.mnd_width = 16,
 449	.hid_width = 5,
 450	.parent_map = disp_cc_parent_map_5,
 451	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 452	.clkr.hw.init = &(const struct clk_init_data) {
 453		.name = "disp_cc_mdss_dptx0_pixel0_clk_src",
 454		.parent_data = disp_cc_parent_data_5,
 455		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
 456		.flags = CLK_SET_RATE_PARENT,
 457		.ops = &clk_dp_ops,
 458	},
 459};
 460
 461static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
 462	.cmd_rcgr = 0x821c,
 463	.mnd_width = 16,
 464	.hid_width = 5,
 465	.parent_map = disp_cc_parent_map_5,
 466	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 467	.clkr.hw.init = &(const struct clk_init_data) {
 468		.name = "disp_cc_mdss_dptx0_pixel1_clk_src",
 469		.parent_data = disp_cc_parent_data_5,
 470		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
 471		.flags = CLK_SET_RATE_PARENT,
 472		.ops = &clk_dp_ops,
 473	},
 474};
 475
 476static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
 477	.cmd_rcgr = 0x8298,
 478	.mnd_width = 0,
 479	.hid_width = 5,
 480	.parent_map = disp_cc_parent_map_0,
 481	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 482	.clkr.hw.init = &(const struct clk_init_data) {
 483		.name = "disp_cc_mdss_dptx1_aux_clk_src",
 484		.parent_data = disp_cc_parent_data_0,
 485		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 486		.flags = CLK_SET_RATE_PARENT,
 487		.ops = &clk_rcg2_ops,
 488	},
 489};
 490
 491static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
 492	.cmd_rcgr = 0x827c,
 493	.mnd_width = 0,
 494	.hid_width = 5,
 495	.parent_map = disp_cc_parent_map_3,
 496	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 497	.clkr.hw.init = &(const struct clk_init_data) {
 498		.name = "disp_cc_mdss_dptx1_link_clk_src",
 499		.parent_data = disp_cc_parent_data_3,
 500		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 501		.flags = CLK_SET_RATE_PARENT,
 502		.ops = &clk_byte2_ops,
 503	},
 504};
 505
 506static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
 507	.cmd_rcgr = 0x824c,
 508	.mnd_width = 16,
 509	.hid_width = 5,
 510	.parent_map = disp_cc_parent_map_2,
 511	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 512	.clkr.hw.init = &(const struct clk_init_data) {
 513		.name = "disp_cc_mdss_dptx1_pixel0_clk_src",
 514		.parent_data = disp_cc_parent_data_2,
 515		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 516		.flags = CLK_SET_RATE_PARENT,
 517		.ops = &clk_dp_ops,
 518	},
 519};
 520
 521static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
 522	.cmd_rcgr = 0x8264,
 523	.mnd_width = 16,
 524	.hid_width = 5,
 525	.parent_map = disp_cc_parent_map_2,
 526	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 527	.clkr.hw.init = &(const struct clk_init_data) {
 528		.name = "disp_cc_mdss_dptx1_pixel1_clk_src",
 529		.parent_data = disp_cc_parent_data_2,
 530		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 531		.flags = CLK_SET_RATE_PARENT,
 532		.ops = &clk_dp_ops,
 533	},
 534};
 535
 536static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
 537	.cmd_rcgr = 0x82fc,
 538	.mnd_width = 0,
 539	.hid_width = 5,
 540	.parent_map = disp_cc_parent_map_0,
 541	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 542	.clkr.hw.init = &(const struct clk_init_data) {
 543		.name = "disp_cc_mdss_dptx2_aux_clk_src",
 544		.parent_data = disp_cc_parent_data_0,
 545		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 546		.flags = CLK_SET_RATE_PARENT,
 547		.ops = &clk_rcg2_ops,
 548	},
 549};
 550
 551static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
 552	.cmd_rcgr = 0x82b0,
 553	.mnd_width = 0,
 554	.hid_width = 5,
 555	.parent_map = disp_cc_parent_map_3,
 556	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 557	.clkr.hw.init = &(const struct clk_init_data) {
 558		.name = "disp_cc_mdss_dptx2_link_clk_src",
 559		.parent_data = disp_cc_parent_data_3,
 560		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 561		.flags = CLK_SET_RATE_PARENT,
 562		.ops = &clk_byte2_ops,
 563	},
 564};
 565
 566static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
 567	.cmd_rcgr = 0x82cc,
 568	.mnd_width = 16,
 569	.hid_width = 5,
 570	.parent_map = disp_cc_parent_map_2,
 571	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 572	.clkr.hw.init = &(const struct clk_init_data) {
 573		.name = "disp_cc_mdss_dptx2_pixel0_clk_src",
 574		.parent_data = disp_cc_parent_data_2,
 575		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 576		.flags = CLK_SET_RATE_PARENT,
 577		.ops = &clk_dp_ops,
 578	},
 579};
 580
 581static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
 582	.cmd_rcgr = 0x82e4,
 583	.mnd_width = 16,
 584	.hid_width = 5,
 585	.parent_map = disp_cc_parent_map_2,
 586	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 587	.clkr.hw.init = &(const struct clk_init_data) {
 588		.name = "disp_cc_mdss_dptx2_pixel1_clk_src",
 589		.parent_data = disp_cc_parent_data_2,
 590		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 591		.flags = CLK_SET_RATE_PARENT,
 592		.ops = &clk_dp_ops,
 593	},
 594};
 595
 596static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
 597	.cmd_rcgr = 0x8348,
 598	.mnd_width = 0,
 599	.hid_width = 5,
 600	.parent_map = disp_cc_parent_map_0,
 601	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 602	.clkr.hw.init = &(const struct clk_init_data) {
 603		.name = "disp_cc_mdss_dptx3_aux_clk_src",
 604		.parent_data = disp_cc_parent_data_0,
 605		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 606		.flags = CLK_SET_RATE_PARENT,
 607		.ops = &clk_rcg2_ops,
 608	},
 609};
 610
 611static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
 612	.cmd_rcgr = 0x832c,
 613	.mnd_width = 0,
 614	.hid_width = 5,
 615	.parent_map = disp_cc_parent_map_3,
 616	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 617	.clkr.hw.init = &(const struct clk_init_data) {
 618		.name = "disp_cc_mdss_dptx3_link_clk_src",
 619		.parent_data = disp_cc_parent_data_3,
 620		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 621		.flags = CLK_SET_RATE_PARENT,
 622		.ops = &clk_byte2_ops,
 623	},
 624};
 625
 626static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
 627	.cmd_rcgr = 0x8314,
 628	.mnd_width = 16,
 629	.hid_width = 5,
 630	.parent_map = disp_cc_parent_map_2,
 631	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 632	.clkr.hw.init = &(const struct clk_init_data) {
 633		.name = "disp_cc_mdss_dptx3_pixel0_clk_src",
 634		.parent_data = disp_cc_parent_data_2,
 635		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 636		.flags = CLK_SET_RATE_PARENT,
 637		.ops = &clk_dp_ops,
 638	},
 639};
 640
 641static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
 642	.cmd_rcgr = 0x81b8,
 643	.mnd_width = 0,
 644	.hid_width = 5,
 645	.parent_map = disp_cc_parent_map_6,
 646	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 647	.clkr.hw.init = &(const struct clk_init_data) {
 648		.name = "disp_cc_mdss_esc0_clk_src",
 649		.parent_data = disp_cc_parent_data_6,
 650		.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
 651		.flags = CLK_SET_RATE_PARENT,
 652		.ops = &clk_rcg2_shared_ops,
 653	},
 654};
 655
 656static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
 657	.cmd_rcgr = 0x81d0,
 658	.mnd_width = 0,
 659	.hid_width = 5,
 660	.parent_map = disp_cc_parent_map_6,
 661	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 662	.clkr.hw.init = &(const struct clk_init_data) {
 663		.name = "disp_cc_mdss_esc1_clk_src",
 664		.parent_data = disp_cc_parent_data_6,
 665		.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
 666		.flags = CLK_SET_RATE_PARENT,
 667		.ops = &clk_rcg2_shared_ops,
 668	},
 669};
 670
 671static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
 672	F(19200000, P_BI_TCXO, 1, 0, 0),
 673	F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 674	F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 675	F(156000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 676	F(207000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 677	F(337000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 678	F(417000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 679	F(532000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 680	F(575000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 681	{ }
 682};
 683
 684static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
 685	.cmd_rcgr = 0x8150,
 686	.mnd_width = 0,
 687	.hid_width = 5,
 688	.parent_map = disp_cc_parent_map_9,
 689	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
 690	.clkr.hw.init = &(const struct clk_init_data) {
 691		.name = "disp_cc_mdss_mdp_clk_src",
 692		.parent_data = disp_cc_parent_data_9,
 693		.num_parents = ARRAY_SIZE(disp_cc_parent_data_9),
 694		.flags = CLK_SET_RATE_PARENT,
 695		/*
 696		 * TODO: Downstream does not manage the clock directly, but
 697		 * places votes via new hardware block called "cesta".
 698		 * It is not clear whether such approach should be taken instead
 699		 * of manual control.
 700		 */
 701		.ops = &clk_rcg2_shared_ops,
 702	},
 703};
 704
 705static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
 706	.cmd_rcgr = 0x8108,
 707	.mnd_width = 8,
 708	.hid_width = 5,
 709	.parent_map = disp_cc_parent_map_1,
 710	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 711	.clkr.hw.init = &(const struct clk_init_data) {
 712		.name = "disp_cc_mdss_pclk0_clk_src",
 713		.parent_data = disp_cc_parent_data_1,
 714		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 715		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 716		.ops = &clk_pixel_ops,
 717	},
 718};
 719
 720static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
 721	.cmd_rcgr = 0x8120,
 722	.mnd_width = 8,
 723	.hid_width = 5,
 724	.parent_map = disp_cc_parent_map_1,
 725	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 726	.clkr.hw.init = &(const struct clk_init_data) {
 727		.name = "disp_cc_mdss_pclk1_clk_src",
 728		.parent_data = disp_cc_parent_data_1,
 729		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 730		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 731		.ops = &clk_pixel_ops,
 732	},
 733};
 734
 735static struct clk_rcg2 disp_cc_mdss_pclk2_clk_src = {
 736	.cmd_rcgr = 0x8138,
 737	.mnd_width = 8,
 738	.hid_width = 5,
 739	.parent_map = disp_cc_parent_map_1,
 740	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 741	.clkr.hw.init = &(const struct clk_init_data) {
 742		.name = "disp_cc_mdss_pclk2_clk_src",
 743		.parent_data = disp_cc_parent_data_1,
 744		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 745		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 746		.ops = &clk_pixel_ops,
 747	},
 748};
 749
 750static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
 751	.cmd_rcgr = 0x8168,
 752	.mnd_width = 0,
 753	.hid_width = 5,
 754	.parent_map = disp_cc_parent_map_0,
 755	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 756	.clkr.hw.init = &(const struct clk_init_data) {
 757		.name = "disp_cc_mdss_vsync_clk_src",
 758		.parent_data = disp_cc_parent_data_0,
 759		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 760		.flags = CLK_SET_RATE_PARENT,
 761		.ops = &clk_rcg2_ops,
 762	},
 763};
 764
 765static const struct freq_tbl ftbl_disp_cc_osc_clk_src[] = {
 766	F(38400000, P_DISP_CC_PLL2_OUT_MAIN, 1, 0, 0),
 767	{ }
 768};
 769
 770static struct clk_rcg2 disp_cc_osc_clk_src = {
 771	.cmd_rcgr = 0x80f0,
 772	.mnd_width = 0,
 773	.hid_width = 5,
 774	.parent_map = disp_cc_parent_map_10,
 775	.freq_tbl = ftbl_disp_cc_osc_clk_src,
 776	.clkr.hw.init = &(const struct clk_init_data) {
 777		.name = "disp_cc_osc_clk_src",
 778		.parent_data = disp_cc_parent_data_10,
 779		.num_parents = ARRAY_SIZE(disp_cc_parent_data_10),
 780		.flags = CLK_SET_RATE_PARENT,
 781		.ops = &clk_rcg2_ops,
 782	},
 783};
 784
 785static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
 786	F(32000, P_SLEEP_CLK, 1, 0, 0),
 787	{ }
 788};
 789
 790static struct clk_rcg2 disp_cc_sleep_clk_src = {
 791	.cmd_rcgr = 0xe064,
 792	.mnd_width = 0,
 793	.hid_width = 5,
 794	.parent_map = disp_cc_parent_map_11,
 795	.freq_tbl = ftbl_disp_cc_sleep_clk_src,
 796	.clkr.hw.init = &(const struct clk_init_data) {
 797		.name = "disp_cc_sleep_clk_src",
 798		.parent_data = disp_cc_parent_data_11,
 799		.num_parents = ARRAY_SIZE(disp_cc_parent_data_11),
 800		.flags = CLK_SET_RATE_PARENT,
 801		.ops = &clk_rcg2_ops,
 802	},
 803};
 804
 805static struct clk_rcg2 disp_cc_xo_clk_src = {
 806	.cmd_rcgr = 0xe044,
 807	.mnd_width = 0,
 808	.hid_width = 5,
 809	.parent_map = disp_cc_parent_map_0,
 810	.freq_tbl = ftbl_disp_cc_esync0_clk_src,
 811	.clkr.hw.init = &(const struct clk_init_data) {
 812		.name = "disp_cc_xo_clk_src",
 813		.parent_data = disp_cc_parent_data_0_ao,
 814		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao),
 815		.flags = CLK_SET_RATE_PARENT,
 816		.ops = &clk_rcg2_ops,
 817	},
 818};
 819
 820static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
 821	.reg = 0x8198,
 822	.shift = 0,
 823	.width = 4,
 824	.clkr.hw.init = &(const struct clk_init_data) {
 825		.name = "disp_cc_mdss_byte0_div_clk_src",
 826		.parent_hws = (const struct clk_hw*[]) {
 827			&disp_cc_mdss_byte0_clk_src.clkr.hw,
 828		},
 829		.num_parents = 1,
 830		.ops = &clk_regmap_div_ops,
 831	},
 832};
 833
 834static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
 835	.reg = 0x81b4,
 836	.shift = 0,
 837	.width = 4,
 838	.clkr.hw.init = &(const struct clk_init_data) {
 839		.name = "disp_cc_mdss_byte1_div_clk_src",
 840		.parent_hws = (const struct clk_hw*[]) {
 841			&disp_cc_mdss_byte1_clk_src.clkr.hw,
 842		},
 843		.num_parents = 1,
 844		.ops = &clk_regmap_div_ops,
 845	},
 846};
 847
 848static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
 849	.reg = 0x8200,
 850	.shift = 0,
 851	.width = 4,
 852	.clkr.hw.init = &(const struct clk_init_data) {
 853		.name = "disp_cc_mdss_dptx0_link_div_clk_src",
 854		.parent_hws = (const struct clk_hw*[]) {
 855			&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
 856		},
 857		.num_parents = 1,
 858		.flags = CLK_SET_RATE_PARENT,
 859		.ops = &clk_regmap_div_ro_ops,
 860	},
 861};
 862
 863static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
 864	.reg = 0x8294,
 865	.shift = 0,
 866	.width = 4,
 867	.clkr.hw.init = &(const struct clk_init_data) {
 868		.name = "disp_cc_mdss_dptx1_link_div_clk_src",
 869		.parent_hws = (const struct clk_hw*[]) {
 870			&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
 871		},
 872		.num_parents = 1,
 873		.flags = CLK_SET_RATE_PARENT,
 874		.ops = &clk_regmap_div_ro_ops,
 875	},
 876};
 877
 878static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
 879	.reg = 0x82c8,
 880	.shift = 0,
 881	.width = 4,
 882	.clkr.hw.init = &(const struct clk_init_data) {
 883		.name = "disp_cc_mdss_dptx2_link_div_clk_src",
 884		.parent_hws = (const struct clk_hw*[]) {
 885			&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
 886		},
 887		.num_parents = 1,
 888		.flags = CLK_SET_RATE_PARENT,
 889		.ops = &clk_regmap_div_ro_ops,
 890	},
 891};
 892
 893static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
 894	.reg = 0x8344,
 895	.shift = 0,
 896	.width = 4,
 897	.clkr.hw.init = &(const struct clk_init_data) {
 898		.name = "disp_cc_mdss_dptx3_link_div_clk_src",
 899		.parent_hws = (const struct clk_hw*[]) {
 900			&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
 901		},
 902		.num_parents = 1,
 903		.flags = CLK_SET_RATE_PARENT,
 904		.ops = &clk_regmap_div_ro_ops,
 905	},
 906};
 907
 908static struct clk_branch disp_cc_esync0_clk = {
 909	.halt_reg = 0x80b8,
 910	.halt_check = BRANCH_HALT,
 911	.clkr = {
 912		.enable_reg = 0x80b8,
 913		.enable_mask = BIT(0),
 914		.hw.init = &(const struct clk_init_data) {
 915			.name = "disp_cc_esync0_clk",
 916			.parent_hws = (const struct clk_hw*[]) {
 917				&disp_cc_esync0_clk_src.clkr.hw,
 918			},
 919			.num_parents = 1,
 920			.flags = CLK_SET_RATE_PARENT,
 921			.ops = &clk_branch2_ops,
 922		},
 923	},
 924};
 925
 926static struct clk_branch disp_cc_esync1_clk = {
 927	.halt_reg = 0x80bc,
 928	.halt_check = BRANCH_HALT,
 929	.clkr = {
 930		.enable_reg = 0x80bc,
 931		.enable_mask = BIT(0),
 932		.hw.init = &(const struct clk_init_data) {
 933			.name = "disp_cc_esync1_clk",
 934			.parent_hws = (const struct clk_hw*[]) {
 935				&disp_cc_esync1_clk_src.clkr.hw,
 936			},
 937			.num_parents = 1,
 938			.flags = CLK_SET_RATE_PARENT,
 939			.ops = &clk_branch2_ops,
 940		},
 941	},
 942};
 943
 944static struct clk_branch disp_cc_mdss_accu_shift_clk = {
 945	.halt_reg = 0xe060,
 946	.halt_check = BRANCH_HALT_VOTED,
 947	.clkr = {
 948		.enable_reg = 0xe060,
 949		.enable_mask = BIT(0),
 950		.hw.init = &(const struct clk_init_data) {
 951			.name = "disp_cc_mdss_accu_shift_clk",
 952			.parent_hws = (const struct clk_hw*[]) {
 953				&disp_cc_xo_clk_src.clkr.hw,
 954			},
 955			.num_parents = 1,
 956			.flags = CLK_SET_RATE_PARENT,
 957			.ops = &clk_branch2_ops,
 958		},
 959	},
 960};
 961
 962static struct clk_branch disp_cc_mdss_ahb1_clk = {
 963	.halt_reg = 0xa028,
 964	.halt_check = BRANCH_HALT,
 965	.clkr = {
 966		.enable_reg = 0xa028,
 967		.enable_mask = BIT(0),
 968		.hw.init = &(const struct clk_init_data) {
 969			.name = "disp_cc_mdss_ahb1_clk",
 970			.parent_hws = (const struct clk_hw*[]) {
 971				&disp_cc_mdss_ahb_clk_src.clkr.hw,
 972			},
 973			.num_parents = 1,
 974			.flags = CLK_SET_RATE_PARENT,
 975			.ops = &clk_branch2_ops,
 976		},
 977	},
 978};
 979
 980static struct clk_branch disp_cc_mdss_ahb_clk = {
 981	.halt_reg = 0x80b0,
 982	.halt_check = BRANCH_HALT,
 983	.clkr = {
 984		.enable_reg = 0x80b0,
 985		.enable_mask = BIT(0),
 986		.hw.init = &(const struct clk_init_data) {
 987			.name = "disp_cc_mdss_ahb_clk",
 988			.parent_hws = (const struct clk_hw*[]) {
 989				&disp_cc_mdss_ahb_clk_src.clkr.hw,
 990			},
 991			.num_parents = 1,
 992			.flags = CLK_SET_RATE_PARENT,
 993			.ops = &clk_branch2_ops,
 994		},
 995	},
 996};
 997
 998static struct clk_branch disp_cc_mdss_byte0_clk = {
 999	.halt_reg = 0x8034,
1000	.halt_check = BRANCH_HALT,
1001	.clkr = {
1002		.enable_reg = 0x8034,
1003		.enable_mask = BIT(0),
1004		.hw.init = &(const struct clk_init_data) {
1005			.name = "disp_cc_mdss_byte0_clk",
1006			.parent_hws = (const struct clk_hw*[]) {
1007				&disp_cc_mdss_byte0_clk_src.clkr.hw,
1008			},
1009			.num_parents = 1,
1010			.flags = CLK_SET_RATE_PARENT,
1011			.ops = &clk_branch2_ops,
1012		},
1013	},
1014};
1015
1016static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
1017	.halt_reg = 0x8038,
1018	.halt_check = BRANCH_HALT,
1019	.clkr = {
1020		.enable_reg = 0x8038,
1021		.enable_mask = BIT(0),
1022		.hw.init = &(const struct clk_init_data) {
1023			.name = "disp_cc_mdss_byte0_intf_clk",
1024			.parent_hws = (const struct clk_hw*[]) {
1025				&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
1026			},
1027			.num_parents = 1,
1028			.flags = CLK_SET_RATE_PARENT,
1029			.ops = &clk_branch2_ops,
1030		},
1031	},
1032};
1033
1034static struct clk_branch disp_cc_mdss_byte1_clk = {
1035	.halt_reg = 0x803c,
1036	.halt_check = BRANCH_HALT,
1037	.clkr = {
1038		.enable_reg = 0x803c,
1039		.enable_mask = BIT(0),
1040		.hw.init = &(const struct clk_init_data) {
1041			.name = "disp_cc_mdss_byte1_clk",
1042			.parent_hws = (const struct clk_hw*[]) {
1043				&disp_cc_mdss_byte1_clk_src.clkr.hw,
1044			},
1045			.num_parents = 1,
1046			.flags = CLK_SET_RATE_PARENT,
1047			.ops = &clk_branch2_ops,
1048		},
1049	},
1050};
1051
1052static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
1053	.halt_reg = 0x8040,
1054	.halt_check = BRANCH_HALT,
1055	.clkr = {
1056		.enable_reg = 0x8040,
1057		.enable_mask = BIT(0),
1058		.hw.init = &(const struct clk_init_data) {
1059			.name = "disp_cc_mdss_byte1_intf_clk",
1060			.parent_hws = (const struct clk_hw*[]) {
1061				&disp_cc_mdss_byte1_div_clk_src.clkr.hw,
1062			},
1063			.num_parents = 1,
1064			.flags = CLK_SET_RATE_PARENT,
1065			.ops = &clk_branch2_ops,
1066		},
1067	},
1068};
1069
1070static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
1071	.halt_reg = 0x8064,
1072	.halt_check = BRANCH_HALT,
1073	.clkr = {
1074		.enable_reg = 0x8064,
1075		.enable_mask = BIT(0),
1076		.hw.init = &(const struct clk_init_data) {
1077			.name = "disp_cc_mdss_dptx0_aux_clk",
1078			.parent_hws = (const struct clk_hw*[]) {
1079				&disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
1080			},
1081			.num_parents = 1,
1082			.flags = CLK_SET_RATE_PARENT,
1083			.ops = &clk_branch2_ops,
1084		},
1085	},
1086};
1087
1088static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {
1089	.halt_reg = 0x8058,
1090	.halt_check = BRANCH_HALT,
1091	.clkr = {
1092		.enable_reg = 0x8058,
1093		.enable_mask = BIT(0),
1094		.hw.init = &(const struct clk_init_data) {
1095			.name = "disp_cc_mdss_dptx0_crypto_clk",
1096			.parent_hws = (const struct clk_hw*[]) {
1097				&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
1098			},
1099			.num_parents = 1,
1100			.flags = CLK_SET_RATE_PARENT,
1101			.ops = &clk_branch2_ops,
1102		},
1103	},
1104};
1105
1106static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
1107	.halt_reg = 0x804c,
1108	.halt_check = BRANCH_HALT,
1109	.clkr = {
1110		.enable_reg = 0x804c,
1111		.enable_mask = BIT(0),
1112		.hw.init = &(const struct clk_init_data) {
1113			.name = "disp_cc_mdss_dptx0_link_clk",
1114			.parent_hws = (const struct clk_hw*[]) {
1115				&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
1116			},
1117			.num_parents = 1,
1118			.flags = CLK_SET_RATE_PARENT,
1119			.ops = &clk_branch2_ops,
1120		},
1121	},
1122};
1123
1124static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
1125	.halt_reg = 0x8054,
1126	.halt_check = BRANCH_HALT,
1127	.clkr = {
1128		.enable_reg = 0x8054,
1129		.enable_mask = BIT(0),
1130		.hw.init = &(const struct clk_init_data) {
1131			.name = "disp_cc_mdss_dptx0_link_intf_clk",
1132			.parent_hws = (const struct clk_hw*[]) {
1133				&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1134			},
1135			.num_parents = 1,
1136			.flags = CLK_SET_RATE_PARENT,
1137			.ops = &clk_branch2_ops,
1138		},
1139	},
1140};
1141
1142static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
1143	.halt_reg = 0x805c,
1144	.halt_check = BRANCH_HALT,
1145	.clkr = {
1146		.enable_reg = 0x805c,
1147		.enable_mask = BIT(0),
1148		.hw.init = &(const struct clk_init_data) {
1149			.name = "disp_cc_mdss_dptx0_pixel0_clk",
1150			.parent_hws = (const struct clk_hw*[]) {
1151				&disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
1152			},
1153			.num_parents = 1,
1154			.flags = CLK_SET_RATE_PARENT,
1155			.ops = &clk_branch2_ops,
1156		},
1157	},
1158};
1159
1160static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
1161	.halt_reg = 0x8060,
1162	.halt_check = BRANCH_HALT,
1163	.clkr = {
1164		.enable_reg = 0x8060,
1165		.enable_mask = BIT(0),
1166		.hw.init = &(const struct clk_init_data) {
1167			.name = "disp_cc_mdss_dptx0_pixel1_clk",
1168			.parent_hws = (const struct clk_hw*[]) {
1169				&disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
1170			},
1171			.num_parents = 1,
1172			.flags = CLK_SET_RATE_PARENT,
1173			.ops = &clk_branch2_ops,
1174		},
1175	},
1176};
1177
1178static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
1179	.halt_reg = 0x8050,
1180	.halt_check = BRANCH_HALT,
1181	.clkr = {
1182		.enable_reg = 0x8050,
1183		.enable_mask = BIT(0),
1184		.hw.init = &(const struct clk_init_data) {
1185			.name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
1186			.parent_hws = (const struct clk_hw*[]) {
1187				&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1188			},
1189			.num_parents = 1,
1190			.flags = CLK_SET_RATE_PARENT,
1191			.ops = &clk_branch2_ops,
1192		},
1193	},
1194};
1195
1196static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
1197	.halt_reg = 0x8080,
1198	.halt_check = BRANCH_HALT,
1199	.clkr = {
1200		.enable_reg = 0x8080,
1201		.enable_mask = BIT(0),
1202		.hw.init = &(const struct clk_init_data) {
1203			.name = "disp_cc_mdss_dptx1_aux_clk",
1204			.parent_hws = (const struct clk_hw*[]) {
1205				&disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
1206			},
1207			.num_parents = 1,
1208			.flags = CLK_SET_RATE_PARENT,
1209			.ops = &clk_branch2_ops,
1210		},
1211	},
1212};
1213
1214static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {
1215	.halt_reg = 0x807c,
1216	.halt_check = BRANCH_HALT,
1217	.clkr = {
1218		.enable_reg = 0x807c,
1219		.enable_mask = BIT(0),
1220		.hw.init = &(const struct clk_init_data) {
1221			.name = "disp_cc_mdss_dptx1_crypto_clk",
1222			.parent_hws = (const struct clk_hw*[]) {
1223				&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1224			},
1225			.num_parents = 1,
1226			.flags = CLK_SET_RATE_PARENT,
1227			.ops = &clk_branch2_ops,
1228		},
1229	},
1230};
1231
1232static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
1233	.halt_reg = 0x8070,
1234	.halt_check = BRANCH_HALT,
1235	.clkr = {
1236		.enable_reg = 0x8070,
1237		.enable_mask = BIT(0),
1238		.hw.init = &(const struct clk_init_data) {
1239			.name = "disp_cc_mdss_dptx1_link_clk",
1240			.parent_hws = (const struct clk_hw*[]) {
1241				&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1242			},
1243			.num_parents = 1,
1244			.flags = CLK_SET_RATE_PARENT,
1245			.ops = &clk_branch2_ops,
1246		},
1247	},
1248};
1249
1250static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
1251	.halt_reg = 0x8078,
1252	.halt_check = BRANCH_HALT,
1253	.clkr = {
1254		.enable_reg = 0x8078,
1255		.enable_mask = BIT(0),
1256		.hw.init = &(const struct clk_init_data) {
1257			.name = "disp_cc_mdss_dptx1_link_intf_clk",
1258			.parent_hws = (const struct clk_hw*[]) {
1259				&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1260			},
1261			.num_parents = 1,
1262			.flags = CLK_SET_RATE_PARENT,
1263			.ops = &clk_branch2_ops,
1264		},
1265	},
1266};
1267
1268static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
1269	.halt_reg = 0x8068,
1270	.halt_check = BRANCH_HALT,
1271	.clkr = {
1272		.enable_reg = 0x8068,
1273		.enable_mask = BIT(0),
1274		.hw.init = &(const struct clk_init_data) {
1275			.name = "disp_cc_mdss_dptx1_pixel0_clk",
1276			.parent_hws = (const struct clk_hw*[]) {
1277				&disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
1278			},
1279			.num_parents = 1,
1280			.flags = CLK_SET_RATE_PARENT,
1281			.ops = &clk_branch2_ops,
1282		},
1283	},
1284};
1285
1286static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
1287	.halt_reg = 0x806c,
1288	.halt_check = BRANCH_HALT,
1289	.clkr = {
1290		.enable_reg = 0x806c,
1291		.enable_mask = BIT(0),
1292		.hw.init = &(const struct clk_init_data) {
1293			.name = "disp_cc_mdss_dptx1_pixel1_clk",
1294			.parent_hws = (const struct clk_hw*[]) {
1295				&disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
1296			},
1297			.num_parents = 1,
1298			.flags = CLK_SET_RATE_PARENT,
1299			.ops = &clk_branch2_ops,
1300		},
1301	},
1302};
1303
1304static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
1305	.halt_reg = 0x8074,
1306	.halt_check = BRANCH_HALT,
1307	.clkr = {
1308		.enable_reg = 0x8074,
1309		.enable_mask = BIT(0),
1310		.hw.init = &(const struct clk_init_data) {
1311			.name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
1312			.parent_hws = (const struct clk_hw*[]) {
1313				&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1314			},
1315			.num_parents = 1,
1316			.flags = CLK_SET_RATE_PARENT,
1317			.ops = &clk_branch2_ops,
1318		},
1319	},
1320};
1321
1322static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
1323	.halt_reg = 0x8098,
1324	.halt_check = BRANCH_HALT,
1325	.clkr = {
1326		.enable_reg = 0x8098,
1327		.enable_mask = BIT(0),
1328		.hw.init = &(const struct clk_init_data) {
1329			.name = "disp_cc_mdss_dptx2_aux_clk",
1330			.parent_hws = (const struct clk_hw*[]) {
1331				&disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
1332			},
1333			.num_parents = 1,
1334			.flags = CLK_SET_RATE_PARENT,
1335			.ops = &clk_branch2_ops,
1336		},
1337	},
1338};
1339
1340static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {
1341	.halt_reg = 0x8094,
1342	.halt_check = BRANCH_HALT,
1343	.clkr = {
1344		.enable_reg = 0x8094,
1345		.enable_mask = BIT(0),
1346		.hw.init = &(const struct clk_init_data) {
1347			.name = "disp_cc_mdss_dptx2_crypto_clk",
1348			.parent_hws = (const struct clk_hw*[]) {
1349				&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1350			},
1351			.num_parents = 1,
1352			.flags = CLK_SET_RATE_PARENT,
1353			.ops = &clk_branch2_ops,
1354		},
1355	},
1356};
1357
1358static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
1359	.halt_reg = 0x808c,
1360	.halt_check = BRANCH_HALT,
1361	.clkr = {
1362		.enable_reg = 0x808c,
1363		.enable_mask = BIT(0),
1364		.hw.init = &(const struct clk_init_data) {
1365			.name = "disp_cc_mdss_dptx2_link_clk",
1366			.parent_hws = (const struct clk_hw*[]) {
1367				&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1368			},
1369			.num_parents = 1,
1370			.flags = CLK_SET_RATE_PARENT,
1371			.ops = &clk_branch2_ops,
1372		},
1373	},
1374};
1375
1376static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
1377	.halt_reg = 0x8090,
1378	.halt_check = BRANCH_HALT,
1379	.clkr = {
1380		.enable_reg = 0x8090,
1381		.enable_mask = BIT(0),
1382		.hw.init = &(const struct clk_init_data) {
1383			.name = "disp_cc_mdss_dptx2_link_intf_clk",
1384			.parent_hws = (const struct clk_hw*[]) {
1385				&disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
1386			},
1387			.num_parents = 1,
1388			.flags = CLK_SET_RATE_PARENT,
1389			.ops = &clk_branch2_ops,
1390		},
1391	},
1392};
1393
1394static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
1395	.halt_reg = 0x8084,
1396	.halt_check = BRANCH_HALT,
1397	.clkr = {
1398		.enable_reg = 0x8084,
1399		.enable_mask = BIT(0),
1400		.hw.init = &(const struct clk_init_data) {
1401			.name = "disp_cc_mdss_dptx2_pixel0_clk",
1402			.parent_hws = (const struct clk_hw*[]) {
1403				&disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
1404			},
1405			.num_parents = 1,
1406			.flags = CLK_SET_RATE_PARENT,
1407			.ops = &clk_branch2_ops,
1408		},
1409	},
1410};
1411
1412static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
1413	.halt_reg = 0x8088,
1414	.halt_check = BRANCH_HALT,
1415	.clkr = {
1416		.enable_reg = 0x8088,
1417		.enable_mask = BIT(0),
1418		.hw.init = &(const struct clk_init_data) {
1419			.name = "disp_cc_mdss_dptx2_pixel1_clk",
1420			.parent_hws = (const struct clk_hw*[]) {
1421				&disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
1422			},
1423			.num_parents = 1,
1424			.flags = CLK_SET_RATE_PARENT,
1425			.ops = &clk_branch2_ops,
1426		},
1427	},
1428};
1429
1430static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
1431	.halt_reg = 0x80a8,
1432	.halt_check = BRANCH_HALT,
1433	.clkr = {
1434		.enable_reg = 0x80a8,
1435		.enable_mask = BIT(0),
1436		.hw.init = &(const struct clk_init_data) {
1437			.name = "disp_cc_mdss_dptx3_aux_clk",
1438			.parent_hws = (const struct clk_hw*[]) {
1439				&disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
1440			},
1441			.num_parents = 1,
1442			.flags = CLK_SET_RATE_PARENT,
1443			.ops = &clk_branch2_ops,
1444		},
1445	},
1446};
1447
1448static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {
1449	.halt_reg = 0x80ac,
1450	.halt_check = BRANCH_HALT,
1451	.clkr = {
1452		.enable_reg = 0x80ac,
1453		.enable_mask = BIT(0),
1454		.hw.init = &(const struct clk_init_data) {
1455			.name = "disp_cc_mdss_dptx3_crypto_clk",
1456			.parent_hws = (const struct clk_hw*[]) {
1457				&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1458			},
1459			.num_parents = 1,
1460			.flags = CLK_SET_RATE_PARENT,
1461			.ops = &clk_branch2_ops,
1462		},
1463	},
1464};
1465
1466static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
1467	.halt_reg = 0x80a0,
1468	.halt_check = BRANCH_HALT,
1469	.clkr = {
1470		.enable_reg = 0x80a0,
1471		.enable_mask = BIT(0),
1472		.hw.init = &(const struct clk_init_data) {
1473			.name = "disp_cc_mdss_dptx3_link_clk",
1474			.parent_hws = (const struct clk_hw*[]) {
1475				&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1476			},
1477			.num_parents = 1,
1478			.flags = CLK_SET_RATE_PARENT,
1479			.ops = &clk_branch2_ops,
1480		},
1481	},
1482};
1483
1484static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
1485	.halt_reg = 0x80a4,
1486	.halt_check = BRANCH_HALT,
1487	.clkr = {
1488		.enable_reg = 0x80a4,
1489		.enable_mask = BIT(0),
1490		.hw.init = &(const struct clk_init_data) {
1491			.name = "disp_cc_mdss_dptx3_link_intf_clk",
1492			.parent_hws = (const struct clk_hw*[]) {
1493				&disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
1494			},
1495			.num_parents = 1,
1496			.flags = CLK_SET_RATE_PARENT,
1497			.ops = &clk_branch2_ops,
1498		},
1499	},
1500};
1501
1502static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
1503	.halt_reg = 0x809c,
1504	.halt_check = BRANCH_HALT,
1505	.clkr = {
1506		.enable_reg = 0x809c,
1507		.enable_mask = BIT(0),
1508		.hw.init = &(const struct clk_init_data) {
1509			.name = "disp_cc_mdss_dptx3_pixel0_clk",
1510			.parent_hws = (const struct clk_hw*[]) {
1511				&disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
1512			},
1513			.num_parents = 1,
1514			.flags = CLK_SET_RATE_PARENT,
1515			.ops = &clk_branch2_ops,
1516		},
1517	},
1518};
1519
1520static struct clk_branch disp_cc_mdss_esc0_clk = {
1521	.halt_reg = 0x8044,
1522	.halt_check = BRANCH_HALT,
1523	.clkr = {
1524		.enable_reg = 0x8044,
1525		.enable_mask = BIT(0),
1526		.hw.init = &(const struct clk_init_data) {
1527			.name = "disp_cc_mdss_esc0_clk",
1528			.parent_hws = (const struct clk_hw*[]) {
1529				&disp_cc_mdss_esc0_clk_src.clkr.hw,
1530			},
1531			.num_parents = 1,
1532			.flags = CLK_SET_RATE_PARENT,
1533			.ops = &clk_branch2_ops,
1534		},
1535	},
1536};
1537
1538static struct clk_branch disp_cc_mdss_esc1_clk = {
1539	.halt_reg = 0x8048,
1540	.halt_check = BRANCH_HALT,
1541	.clkr = {
1542		.enable_reg = 0x8048,
1543		.enable_mask = BIT(0),
1544		.hw.init = &(const struct clk_init_data) {
1545			.name = "disp_cc_mdss_esc1_clk",
1546			.parent_hws = (const struct clk_hw*[]) {
1547				&disp_cc_mdss_esc1_clk_src.clkr.hw,
1548			},
1549			.num_parents = 1,
1550			.flags = CLK_SET_RATE_PARENT,
1551			.ops = &clk_branch2_ops,
1552		},
1553	},
1554};
1555
1556static struct clk_branch disp_cc_mdss_mdp1_clk = {
1557	.halt_reg = 0xa004,
1558	.halt_check = BRANCH_HALT,
1559	.clkr = {
1560		.enable_reg = 0xa004,
1561		.enable_mask = BIT(0),
1562		.hw.init = &(const struct clk_init_data) {
1563			.name = "disp_cc_mdss_mdp1_clk",
1564			.parent_hws = (const struct clk_hw*[]) {
1565				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1566			},
1567			.num_parents = 1,
1568			.flags = CLK_SET_RATE_PARENT,
1569			.ops = &clk_branch2_ops,
1570		},
1571	},
1572};
1573
1574static struct clk_branch disp_cc_mdss_mdp_clk = {
1575	.halt_reg = 0x8010,
1576	.halt_check = BRANCH_HALT,
1577	.clkr = {
1578		.enable_reg = 0x8010,
1579		.enable_mask = BIT(0),
1580		.hw.init = &(const struct clk_init_data) {
1581			.name = "disp_cc_mdss_mdp_clk",
1582			.parent_hws = (const struct clk_hw*[]) {
1583				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1584			},
1585			.num_parents = 1,
1586			.flags = CLK_SET_RATE_PARENT,
1587			.ops = &clk_branch2_aon_ops,
1588		},
1589	},
1590};
1591
1592static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
1593	.halt_reg = 0xa014,
1594	.halt_check = BRANCH_HALT,
1595	.clkr = {
1596		.enable_reg = 0xa014,
1597		.enable_mask = BIT(0),
1598		.hw.init = &(const struct clk_init_data) {
1599			.name = "disp_cc_mdss_mdp_lut1_clk",
1600			.parent_hws = (const struct clk_hw*[]) {
1601				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1602			},
1603			.num_parents = 1,
1604			.flags = CLK_SET_RATE_PARENT,
1605			.ops = &clk_branch2_ops,
1606		},
1607	},
1608};
1609
1610static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
1611	.halt_reg = 0x8020,
1612	.halt_check = BRANCH_HALT_VOTED,
1613	.clkr = {
1614		.enable_reg = 0x8020,
1615		.enable_mask = BIT(0),
1616		.hw.init = &(const struct clk_init_data) {
1617			.name = "disp_cc_mdss_mdp_lut_clk",
1618			.parent_hws = (const struct clk_hw*[]) {
1619				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1620			},
1621			.num_parents = 1,
1622			.flags = CLK_SET_RATE_PARENT,
1623			.ops = &clk_branch2_ops,
1624		},
1625	},
1626};
1627
1628static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
1629	.halt_reg = 0xc004,
1630	.halt_check = BRANCH_HALT_VOTED,
1631	.clkr = {
1632		.enable_reg = 0xc004,
1633		.enable_mask = BIT(0),
1634		.hw.init = &(const struct clk_init_data) {
1635			.name = "disp_cc_mdss_non_gdsc_ahb_clk",
1636			.parent_hws = (const struct clk_hw*[]) {
1637				&disp_cc_mdss_ahb_clk_src.clkr.hw,
1638			},
1639			.num_parents = 1,
1640			.flags = CLK_SET_RATE_PARENT,
1641			.ops = &clk_branch2_ops,
1642		},
1643	},
1644};
1645
1646static struct clk_branch disp_cc_mdss_pclk0_clk = {
1647	.halt_reg = 0x8004,
1648	.halt_check = BRANCH_HALT,
1649	.clkr = {
1650		.enable_reg = 0x8004,
1651		.enable_mask = BIT(0),
1652		.hw.init = &(const struct clk_init_data) {
1653			.name = "disp_cc_mdss_pclk0_clk",
1654			.parent_hws = (const struct clk_hw*[]) {
1655				&disp_cc_mdss_pclk0_clk_src.clkr.hw,
1656			},
1657			.num_parents = 1,
1658			.flags = CLK_SET_RATE_PARENT,
1659			.ops = &clk_branch2_ops,
1660		},
1661	},
1662};
1663
1664static struct clk_branch disp_cc_mdss_pclk1_clk = {
1665	.halt_reg = 0x8008,
1666	.halt_check = BRANCH_HALT,
1667	.clkr = {
1668		.enable_reg = 0x8008,
1669		.enable_mask = BIT(0),
1670		.hw.init = &(const struct clk_init_data) {
1671			.name = "disp_cc_mdss_pclk1_clk",
1672			.parent_hws = (const struct clk_hw*[]) {
1673				&disp_cc_mdss_pclk1_clk_src.clkr.hw,
1674			},
1675			.num_parents = 1,
1676			.flags = CLK_SET_RATE_PARENT,
1677			.ops = &clk_branch2_ops,
1678		},
1679	},
1680};
1681
1682static struct clk_branch disp_cc_mdss_pclk2_clk = {
1683	.halt_reg = 0x800c,
1684	.halt_check = BRANCH_HALT,
1685	.clkr = {
1686		.enable_reg = 0x800c,
1687		.enable_mask = BIT(0),
1688		.hw.init = &(const struct clk_init_data) {
1689			.name = "disp_cc_mdss_pclk2_clk",
1690			.parent_hws = (const struct clk_hw*[]) {
1691				&disp_cc_mdss_pclk2_clk_src.clkr.hw,
1692			},
1693			.num_parents = 1,
1694			.flags = CLK_SET_RATE_PARENT,
1695			.ops = &clk_branch2_ops,
1696		},
1697	},
1698};
1699
1700static struct clk_branch disp_cc_mdss_vsync1_clk = {
1701	.halt_reg = 0xa024,
1702	.halt_check = BRANCH_HALT,
1703	.clkr = {
1704		.enable_reg = 0xa024,
1705		.enable_mask = BIT(0),
1706		.hw.init = &(const struct clk_init_data) {
1707			.name = "disp_cc_mdss_vsync1_clk",
1708			.parent_hws = (const struct clk_hw*[]) {
1709				&disp_cc_mdss_vsync_clk_src.clkr.hw,
1710			},
1711			.num_parents = 1,
1712			.flags = CLK_SET_RATE_PARENT,
1713			.ops = &clk_branch2_ops,
1714		},
1715	},
1716};
1717
1718static struct clk_branch disp_cc_mdss_vsync_clk = {
1719	.halt_reg = 0x8030,
1720	.halt_check = BRANCH_HALT,
1721	.clkr = {
1722		.enable_reg = 0x8030,
1723		.enable_mask = BIT(0),
1724		.hw.init = &(const struct clk_init_data) {
1725			.name = "disp_cc_mdss_vsync_clk",
1726			.parent_hws = (const struct clk_hw*[]) {
1727				&disp_cc_mdss_vsync_clk_src.clkr.hw,
1728			},
1729			.num_parents = 1,
1730			.flags = CLK_SET_RATE_PARENT,
1731			.ops = &clk_branch2_ops,
1732		},
1733	},
1734};
1735
1736static struct clk_branch disp_cc_osc_clk = {
1737	.halt_reg = 0x80b4,
1738	.halt_check = BRANCH_HALT,
1739	.clkr = {
1740		.enable_reg = 0x80b4,
1741		.enable_mask = BIT(0),
1742		.hw.init = &(const struct clk_init_data) {
1743			.name = "disp_cc_osc_clk",
1744			.parent_hws = (const struct clk_hw*[]) {
1745				&disp_cc_osc_clk_src.clkr.hw,
1746			},
1747			.num_parents = 1,
1748			.flags = CLK_SET_RATE_PARENT,
1749			.ops = &clk_branch2_ops,
1750		},
1751	},
1752};
1753
1754static struct gdsc mdss_gdsc = {
1755	.gdscr = 0x9000,
1756	.en_rest_wait_val = 0x2,
1757	.en_few_wait_val = 0x2,
1758	.clk_dis_wait_val = 0xf,
1759	.pd = {
1760		.name = "mdss_gdsc",
1761	},
1762	.pwrsts = PWRSTS_OFF_ON,
1763	.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
1764};
1765
1766static struct gdsc mdss_int2_gdsc = {
1767	.gdscr = 0xb000,
1768	.en_rest_wait_val = 0x2,
1769	.en_few_wait_val = 0x2,
1770	.clk_dis_wait_val = 0xf,
1771	.pd = {
1772		.name = "mdss_int2_gdsc",
1773	},
1774	.pwrsts = PWRSTS_OFF_ON,
1775	.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
1776};
1777
1778static struct clk_regmap *disp_cc_sm8750_clocks[] = {
1779	[DISP_CC_ESYNC0_CLK] = &disp_cc_esync0_clk.clkr,
1780	[DISP_CC_ESYNC0_CLK_SRC] = &disp_cc_esync0_clk_src.clkr,
1781	[DISP_CC_ESYNC1_CLK] = &disp_cc_esync1_clk.clkr,
1782	[DISP_CC_ESYNC1_CLK_SRC] = &disp_cc_esync1_clk_src.clkr,
1783	[DISP_CC_MDSS_ACCU_SHIFT_CLK] = &disp_cc_mdss_accu_shift_clk.clkr,
1784	[DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
1785	[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
1786	[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
1787	[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
1788	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
1789	[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
1790	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
1791	[DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
1792	[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1793	[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
1794	[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
1795	[DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,
1796	[DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,
1797	[DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr,
1798	[DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,
1799	[DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,
1800	[DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,
1801	[DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,
1802	[DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,
1803	[DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
1804	[DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
1805	[DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
1806	[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
1807		&disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
1808	[DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,
1809	[DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,
1810	[DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr,
1811	[DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,
1812	[DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,
1813	[DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,
1814	[DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,
1815	[DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,
1816	[DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
1817	[DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
1818	[DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
1819	[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
1820		&disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
1821	[DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,
1822	[DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,
1823	[DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr,
1824	[DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,
1825	[DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,
1826	[DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,
1827	[DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,
1828	[DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,
1829	[DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,
1830	[DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
1831	[DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
1832	[DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,
1833	[DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,
1834	[DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr,
1835	[DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,
1836	[DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,
1837	[DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,
1838	[DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,
1839	[DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,
1840	[DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,
1841	[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
1842	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
1843	[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1844	[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1845	[DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
1846	[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1847	[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1848	[DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
1849	[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1850	[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1851	[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1852	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1853	[DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1854	[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1855	[DISP_CC_MDSS_PCLK2_CLK] = &disp_cc_mdss_pclk2_clk.clkr,
1856	[DISP_CC_MDSS_PCLK2_CLK_SRC] = &disp_cc_mdss_pclk2_clk_src.clkr,
1857	[DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
1858	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1859	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1860	[DISP_CC_OSC_CLK] = &disp_cc_osc_clk.clkr,
1861	[DISP_CC_OSC_CLK_SRC] = &disp_cc_osc_clk_src.clkr,
1862	[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1863	[DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1864	[DISP_CC_PLL2] = &disp_cc_pll2.clkr,
1865	[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
1866	[DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
1867};
1868
1869static const struct qcom_reset_map disp_cc_sm8750_resets[] = {
1870	[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1871	[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
1872	[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
1873};
1874
1875static struct gdsc *disp_cc_sm8750_gdscs[] = {
1876	[MDSS_GDSC] = &mdss_gdsc,
1877	[MDSS_INT2_GDSC] = &mdss_int2_gdsc,
1878};
1879
1880static const struct regmap_config disp_cc_sm8750_regmap_config = {
1881	.reg_bits = 32,
1882	.reg_stride = 4,
1883	.val_bits = 32,
1884	.max_register = 0xf004, /* 0x10000, 0x10004 and maybe others are for TZ */
1885	.fast_io = true,
1886};
1887
1888static const struct qcom_cc_desc disp_cc_sm8750_desc = {
1889	.config = &disp_cc_sm8750_regmap_config,
1890	.clks = disp_cc_sm8750_clocks,
1891	.num_clks = ARRAY_SIZE(disp_cc_sm8750_clocks),
1892	.resets = disp_cc_sm8750_resets,
1893	.num_resets = ARRAY_SIZE(disp_cc_sm8750_resets),
1894	.gdscs = disp_cc_sm8750_gdscs,
1895	.num_gdscs = ARRAY_SIZE(disp_cc_sm8750_gdscs),
1896};
1897
1898static const struct of_device_id disp_cc_sm8750_match_table[] = {
1899	{ .compatible = "qcom,sm8750-dispcc" },
1900	{ }
1901};
1902MODULE_DEVICE_TABLE(of, disp_cc_sm8750_match_table);
1903
1904static int disp_cc_sm8750_probe(struct platform_device *pdev)
1905{
1906	struct regmap *regmap;
1907	int ret;
1908
1909	ret = devm_pm_runtime_enable(&pdev->dev);
1910	if (ret)
1911		return ret;
1912
1913	ret = pm_runtime_resume_and_get(&pdev->dev);
1914	if (ret)
1915		return ret;
1916
1917	regmap = qcom_cc_map(pdev, &disp_cc_sm8750_desc);
1918	if (IS_ERR(regmap)) {
1919		ret = PTR_ERR(regmap);
1920		goto err_put_rpm;
1921	}
1922
1923	clk_taycan_elu_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1924	clk_taycan_elu_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1925	clk_pongo_elu_pll_configure(&disp_cc_pll2, regmap, &disp_cc_pll2_config);
1926
1927	/* Enable clock gating for MDP clocks */
1928	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
1929
1930	/* Keep some clocks always-on */
1931	qcom_branch_set_clk_en(regmap, 0xe07c); /* DISP_CC_SLEEP_CLK */
1932	qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */
1933	qcom_branch_set_clk_en(regmap, 0xc00c); /* DISP_CC_MDSS_RSCC_AHB_CLK */
1934	qcom_branch_set_clk_en(regmap, 0xc008); /* DISP_CC_MDSS_RSCC_VSYNC_CLK */
1935
1936	ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8750_desc, regmap);
1937	if (ret)
1938		goto err_put_rpm;
1939
1940	pm_runtime_put(&pdev->dev);
1941
1942	return 0;
1943
1944err_put_rpm:
1945	pm_runtime_put_sync(&pdev->dev);
1946
1947	return ret;
1948}
1949
1950static struct platform_driver disp_cc_sm8750_driver = {
1951	.probe = disp_cc_sm8750_probe,
1952	.driver = {
1953		.name = "disp_cc-sm8750",
1954		.of_match_table = disp_cc_sm8750_match_table,
1955	},
1956};
1957
1958module_platform_driver(disp_cc_sm8750_driver);
1959
1960MODULE_DESCRIPTION("QTI DISPCC SM8750 Driver");
1961MODULE_LICENSE("GPL");