dispcc-sm8550.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2023, Linaro Ltd.
   5 */
   6
   7#include <linux/clk-provider.h>
   8#include <linux/err.h>
   9#include <linux/kernel.h>
  10#include <linux/mod_devicetable.h>
  11#include <linux/module.h>
  12#include <linux/platform_device.h>
  13#include <linux/regmap.h>
  14#include <linux/pm_runtime.h>
  15
  16#include <dt-bindings/clock/qcom,sm8550-dispcc.h>
  17
  18#include "common.h"
  19#include "clk-alpha-pll.h"
  20#include "clk-branch.h"
  21#include "clk-pll.h"
  22#include "clk-rcg.h"
  23#include "clk-regmap.h"
  24#include "clk-regmap-divider.h"
  25#include "clk-regmap-mux.h"
  26#include "reset.h"
  27#include "gdsc.h"
  28
  29/* Need to match the order of clocks in DT binding */
  30enum {
  31	DT_BI_TCXO,
  32	DT_BI_TCXO_AO,
  33	DT_AHB_CLK,
  34	DT_SLEEP_CLK,
  35
  36	DT_DSI0_PHY_PLL_OUT_BYTECLK,
  37	DT_DSI0_PHY_PLL_OUT_DSICLK,
  38	DT_DSI1_PHY_PLL_OUT_BYTECLK,
  39	DT_DSI1_PHY_PLL_OUT_DSICLK,
  40
  41	DT_DP0_PHY_PLL_LINK_CLK,
  42	DT_DP0_PHY_PLL_VCO_DIV_CLK,
  43	DT_DP1_PHY_PLL_LINK_CLK,
  44	DT_DP1_PHY_PLL_VCO_DIV_CLK,
  45	DT_DP2_PHY_PLL_LINK_CLK,
  46	DT_DP2_PHY_PLL_VCO_DIV_CLK,
  47	DT_DP3_PHY_PLL_LINK_CLK,
  48	DT_DP3_PHY_PLL_VCO_DIV_CLK,
  49};
  50
  51#define DISP_CC_MISC_CMD	0xF000
  52
  53enum {
  54	P_BI_TCXO,
  55	P_DISP_CC_PLL0_OUT_MAIN,
  56	P_DISP_CC_PLL1_OUT_EVEN,
  57	P_DISP_CC_PLL1_OUT_MAIN,
  58	P_DP0_PHY_PLL_LINK_CLK,
  59	P_DP0_PHY_PLL_VCO_DIV_CLK,
  60	P_DP1_PHY_PLL_LINK_CLK,
  61	P_DP1_PHY_PLL_VCO_DIV_CLK,
  62	P_DP2_PHY_PLL_LINK_CLK,
  63	P_DP2_PHY_PLL_VCO_DIV_CLK,
  64	P_DP3_PHY_PLL_LINK_CLK,
  65	P_DP3_PHY_PLL_VCO_DIV_CLK,
  66	P_DSI0_PHY_PLL_OUT_BYTECLK,
  67	P_DSI0_PHY_PLL_OUT_DSICLK,
  68	P_DSI1_PHY_PLL_OUT_BYTECLK,
  69	P_DSI1_PHY_PLL_OUT_DSICLK,
  70	P_SLEEP_CLK,
  71};
  72
  73static struct pll_vco lucid_ole_vco[] = {
  74	{ 249600000, 2000000000, 0 },
  75};
  76
  77static struct alpha_pll_config disp_cc_pll0_config = {
  78	.l = 0xd,
  79	.alpha = 0x6492,
  80	.config_ctl_val = 0x20485699,
  81	.config_ctl_hi_val = 0x00182261,
  82	.config_ctl_hi1_val = 0x82aa299c,
  83	.test_ctl_val = 0x00000000,
  84	.test_ctl_hi_val = 0x00000003,
  85	.test_ctl_hi1_val = 0x00009000,
  86	.test_ctl_hi2_val = 0x00000034,
  87	.user_ctl_val = 0x00000000,
  88	.user_ctl_hi_val = 0x00000005,
  89};
  90
  91static struct clk_alpha_pll disp_cc_pll0 = {
  92	.offset = 0x0,
  93	.vco_table = lucid_ole_vco,
  94	.num_vco = ARRAY_SIZE(lucid_ole_vco),
  95	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
  96	.clkr = {
  97		.hw.init = &(const struct clk_init_data) {
  98			.name = "disp_cc_pll0",
  99			.parent_data = &(const struct clk_parent_data) {
 100				.index = DT_BI_TCXO,
 101			},
 102			.num_parents = 1,
 103			.ops = &clk_alpha_pll_reset_lucid_ole_ops,
 104		},
 105	},
 106};
 107
 108static struct alpha_pll_config disp_cc_pll1_config = {
 109	.l = 0x1f,
 110	.alpha = 0x4000,
 111	.config_ctl_val = 0x20485699,
 112	.config_ctl_hi_val = 0x00182261,
 113	.config_ctl_hi1_val = 0x82aa299c,
 114	.test_ctl_val = 0x00000000,
 115	.test_ctl_hi_val = 0x00000003,
 116	.test_ctl_hi1_val = 0x00009000,
 117	.test_ctl_hi2_val = 0x00000034,
 118	.user_ctl_val = 0x00000000,
 119	.user_ctl_hi_val = 0x00000005,
 120};
 121
 122static struct clk_alpha_pll disp_cc_pll1 = {
 123	.offset = 0x1000,
 124	.vco_table = lucid_ole_vco,
 125	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 126	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 127	.clkr = {
 128		.hw.init = &(const struct clk_init_data) {
 129			.name = "disp_cc_pll1",
 130			.parent_data = &(const struct clk_parent_data) {
 131				.index = DT_BI_TCXO,
 132			},
 133			.num_parents = 1,
 134			.ops = &clk_alpha_pll_reset_lucid_ole_ops,
 135		},
 136	},
 137};
 138
 139static const struct parent_map disp_cc_parent_map_0[] = {
 140	{ P_BI_TCXO, 0 },
 141};
 142
 143static const struct clk_parent_data disp_cc_parent_data_0[] = {
 144	{ .index = DT_BI_TCXO },
 145};
 146
 147static const struct clk_parent_data disp_cc_parent_data_0_ao[] = {
 148	{ .index = DT_BI_TCXO_AO },
 149};
 150
 151static const struct parent_map disp_cc_parent_map_1[] = {
 152	{ P_BI_TCXO, 0 },
 153	{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
 154	{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
 155	{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
 156};
 157
 158static const struct clk_parent_data disp_cc_parent_data_1[] = {
 159	{ .index = DT_BI_TCXO },
 160	{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
 161	{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
 162	{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
 163};
 164
 165static const struct parent_map disp_cc_parent_map_2[] = {
 166	{ P_BI_TCXO, 0 },
 167	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
 168	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
 169	{ P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
 170	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
 171};
 172
 173static const struct clk_parent_data disp_cc_parent_data_2[] = {
 174	{ .index = DT_BI_TCXO },
 175	{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
 176	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
 177	{ .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
 178	{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
 179};
 180
 181static const struct parent_map disp_cc_parent_map_3[] = {
 182	{ P_BI_TCXO, 0 },
 183	{ P_DP1_PHY_PLL_LINK_CLK, 2 },
 184	{ P_DP2_PHY_PLL_LINK_CLK, 3 },
 185	{ P_DP3_PHY_PLL_LINK_CLK, 4 },
 186};
 187
 188static const struct clk_parent_data disp_cc_parent_data_3[] = {
 189	{ .index = DT_BI_TCXO },
 190	{ .index = DT_DP1_PHY_PLL_LINK_CLK },
 191	{ .index = DT_DP2_PHY_PLL_LINK_CLK },
 192	{ .index = DT_DP3_PHY_PLL_LINK_CLK },
 193};
 194
 195static const struct parent_map disp_cc_parent_map_4[] = {
 196	{ P_BI_TCXO, 0 },
 197	{ P_DP0_PHY_PLL_LINK_CLK, 1 },
 198	{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
 199	{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
 200	{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
 201	{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
 202};
 203
 204static const struct clk_parent_data disp_cc_parent_data_4[] = {
 205	{ .index = DT_BI_TCXO },
 206	{ .index = DT_DP0_PHY_PLL_LINK_CLK },
 207	{ .index = DT_DP0_PHY_PLL_VCO_DIV_CLK },
 208	{ .index = DT_DP3_PHY_PLL_VCO_DIV_CLK },
 209	{ .index = DT_DP1_PHY_PLL_VCO_DIV_CLK },
 210	{ .index = DT_DP2_PHY_PLL_VCO_DIV_CLK },
 211};
 212
 213static const struct parent_map disp_cc_parent_map_5[] = {
 214	{ P_BI_TCXO, 0 },
 215	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
 216	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
 217};
 218
 219static const struct clk_parent_data disp_cc_parent_data_5[] = {
 220	{ .index = DT_BI_TCXO },
 221	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
 222	{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
 223};
 224
 225static const struct parent_map disp_cc_parent_map_6[] = {
 226	{ P_BI_TCXO, 0 },
 227	{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
 228	{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
 229};
 230
 231static const struct clk_parent_data disp_cc_parent_data_6[] = {
 232	{ .index = DT_BI_TCXO },
 233	{ .hw = &disp_cc_pll1.clkr.hw },
 234	{ .hw = &disp_cc_pll1.clkr.hw },
 235};
 236
 237static const struct parent_map disp_cc_parent_map_7[] = {
 238	{ P_BI_TCXO, 0 },
 239	{ P_DP0_PHY_PLL_LINK_CLK, 1 },
 240	{ P_DP1_PHY_PLL_LINK_CLK, 2 },
 241	{ P_DP2_PHY_PLL_LINK_CLK, 3 },
 242	{ P_DP3_PHY_PLL_LINK_CLK, 4 },
 243};
 244
 245static const struct clk_parent_data disp_cc_parent_data_7[] = {
 246	{ .index = DT_BI_TCXO },
 247	{ .index = DT_DP0_PHY_PLL_LINK_CLK },
 248	{ .index = DT_DP1_PHY_PLL_LINK_CLK },
 249	{ .index = DT_DP2_PHY_PLL_LINK_CLK },
 250	{ .index = DT_DP3_PHY_PLL_LINK_CLK },
 251};
 252
 253static const struct parent_map disp_cc_parent_map_8[] = {
 254	{ P_BI_TCXO, 0 },
 255	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
 256	{ P_DISP_CC_PLL1_OUT_MAIN, 4 },
 257	{ P_DISP_CC_PLL1_OUT_EVEN, 6 },
 258};
 259
 260static const struct clk_parent_data disp_cc_parent_data_8[] = {
 261	{ .index = DT_BI_TCXO },
 262	{ .hw = &disp_cc_pll0.clkr.hw },
 263	{ .hw = &disp_cc_pll1.clkr.hw },
 264	{ .hw = &disp_cc_pll1.clkr.hw },
 265};
 266
 267static const struct parent_map disp_cc_parent_map_9[] = {
 268	{ P_SLEEP_CLK, 0 },
 269};
 270
 271static const struct clk_parent_data disp_cc_parent_data_9[] = {
 272	{ .index = DT_SLEEP_CLK },
 273};
 274
 275static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
 276	F(19200000, P_BI_TCXO, 1, 0, 0),
 277	F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
 278	F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
 279	{ }
 280};
 281
 282static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
 283	.cmd_rcgr = 0x82e8,
 284	.mnd_width = 0,
 285	.hid_width = 5,
 286	.parent_map = disp_cc_parent_map_6,
 287	.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
 288	.clkr.hw.init = &(const struct clk_init_data) {
 289		.name = "disp_cc_mdss_ahb_clk_src",
 290		.parent_data = disp_cc_parent_data_6,
 291		.num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
 292		.flags = CLK_SET_RATE_PARENT,
 293		.ops = &clk_rcg2_shared_ops,
 294	},
 295};
 296
 297static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
 298	F(19200000, P_BI_TCXO, 1, 0, 0),
 299	{ }
 300};
 301
 302static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
 303	.cmd_rcgr = 0x8108,
 304	.mnd_width = 0,
 305	.hid_width = 5,
 306	.parent_map = disp_cc_parent_map_2,
 307	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 308	.clkr.hw.init = &(const struct clk_init_data) {
 309		.name = "disp_cc_mdss_byte0_clk_src",
 310		.parent_data = disp_cc_parent_data_2,
 311		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 312		.flags = CLK_SET_RATE_PARENT,
 313		.ops = &clk_byte2_ops,
 314	},
 315};
 316
 317static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
 318	.cmd_rcgr = 0x8124,
 319	.mnd_width = 0,
 320	.hid_width = 5,
 321	.parent_map = disp_cc_parent_map_2,
 322	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 323	.clkr.hw.init = &(const struct clk_init_data) {
 324		.name = "disp_cc_mdss_byte1_clk_src",
 325		.parent_data = disp_cc_parent_data_2,
 326		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 327		.flags = CLK_SET_RATE_PARENT,
 328		.ops = &clk_byte2_ops,
 329	},
 330};
 331
 332static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = {
 333	.cmd_rcgr = 0x81bc,
 334	.mnd_width = 0,
 335	.hid_width = 5,
 336	.parent_map = disp_cc_parent_map_0,
 337	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 338	.clkr.hw.init = &(const struct clk_init_data) {
 339		.name = "disp_cc_mdss_dptx0_aux_clk_src",
 340		.parent_data = disp_cc_parent_data_0,
 341		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 342		.flags = CLK_SET_RATE_PARENT,
 343		.ops = &clk_rcg2_ops,
 344	},
 345};
 346
 347static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = {
 348	.cmd_rcgr = 0x8170,
 349	.mnd_width = 0,
 350	.hid_width = 5,
 351	.parent_map = disp_cc_parent_map_7,
 352	.clkr.hw.init = &(const struct clk_init_data) {
 353		.name = "disp_cc_mdss_dptx0_link_clk_src",
 354		.parent_data = disp_cc_parent_data_7,
 355		.num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
 356		.flags = CLK_SET_RATE_PARENT,
 357		.ops = &clk_byte2_ops,
 358	},
 359};
 360
 361static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = {
 362	.cmd_rcgr = 0x818c,
 363	.mnd_width = 16,
 364	.hid_width = 5,
 365	.parent_map = disp_cc_parent_map_4,
 366	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 367	.clkr.hw.init = &(const struct clk_init_data) {
 368		.name = "disp_cc_mdss_dptx0_pixel0_clk_src",
 369		.parent_data = disp_cc_parent_data_4,
 370		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
 371		.flags = CLK_SET_RATE_PARENT,
 372		.ops = &clk_dp_ops,
 373	},
 374};
 375
 376static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = {
 377	.cmd_rcgr = 0x81a4,
 378	.mnd_width = 16,
 379	.hid_width = 5,
 380	.parent_map = disp_cc_parent_map_4,
 381	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 382	.clkr.hw.init = &(const struct clk_init_data) {
 383		.name = "disp_cc_mdss_dptx0_pixel1_clk_src",
 384		.parent_data = disp_cc_parent_data_4,
 385		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
 386		.flags = CLK_SET_RATE_PARENT,
 387		.ops = &clk_dp_ops,
 388	},
 389};
 390
 391static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = {
 392	.cmd_rcgr = 0x8220,
 393	.mnd_width = 0,
 394	.hid_width = 5,
 395	.parent_map = disp_cc_parent_map_0,
 396	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 397	.clkr.hw.init = &(const struct clk_init_data) {
 398		.name = "disp_cc_mdss_dptx1_aux_clk_src",
 399		.parent_data = disp_cc_parent_data_0,
 400		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 401		.flags = CLK_SET_RATE_PARENT,
 402		.ops = &clk_rcg2_ops,
 403	},
 404};
 405
 406static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = {
 407	.cmd_rcgr = 0x8204,
 408	.mnd_width = 0,
 409	.hid_width = 5,
 410	.parent_map = disp_cc_parent_map_3,
 411	.clkr.hw.init = &(const struct clk_init_data) {
 412		.name = "disp_cc_mdss_dptx1_link_clk_src",
 413		.parent_data = disp_cc_parent_data_3,
 414		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 415		.flags = CLK_SET_RATE_PARENT,
 416		.ops = &clk_byte2_ops,
 417	},
 418};
 419
 420static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = {
 421	.cmd_rcgr = 0x81d4,
 422	.mnd_width = 16,
 423	.hid_width = 5,
 424	.parent_map = disp_cc_parent_map_1,
 425	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 426	.clkr.hw.init = &(const struct clk_init_data) {
 427		.name = "disp_cc_mdss_dptx1_pixel0_clk_src",
 428		.parent_data = disp_cc_parent_data_1,
 429		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 430		.flags = CLK_SET_RATE_PARENT,
 431		.ops = &clk_dp_ops,
 432	},
 433};
 434
 435static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = {
 436	.cmd_rcgr = 0x81ec,
 437	.mnd_width = 16,
 438	.hid_width = 5,
 439	.parent_map = disp_cc_parent_map_1,
 440	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 441	.clkr.hw.init = &(const struct clk_init_data) {
 442		.name = "disp_cc_mdss_dptx1_pixel1_clk_src",
 443		.parent_data = disp_cc_parent_data_1,
 444		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 445		.flags = CLK_SET_RATE_PARENT,
 446		.ops = &clk_dp_ops,
 447	},
 448};
 449
 450static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = {
 451	.cmd_rcgr = 0x8284,
 452	.mnd_width = 0,
 453	.hid_width = 5,
 454	.parent_map = disp_cc_parent_map_0,
 455	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 456	.clkr.hw.init = &(const struct clk_init_data) {
 457		.name = "disp_cc_mdss_dptx2_aux_clk_src",
 458		.parent_data = disp_cc_parent_data_0,
 459		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 460		.flags = CLK_SET_RATE_PARENT,
 461		.ops = &clk_rcg2_ops,
 462	},
 463};
 464
 465static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = {
 466	.cmd_rcgr = 0x8238,
 467	.mnd_width = 0,
 468	.hid_width = 5,
 469	.parent_map = disp_cc_parent_map_3,
 470	.clkr.hw.init = &(const struct clk_init_data) {
 471		.name = "disp_cc_mdss_dptx2_link_clk_src",
 472		.parent_data = disp_cc_parent_data_3,
 473		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 474		.flags = CLK_SET_RATE_PARENT,
 475		.ops = &clk_byte2_ops,
 476	},
 477};
 478
 479static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = {
 480	.cmd_rcgr = 0x8254,
 481	.mnd_width = 16,
 482	.hid_width = 5,
 483	.parent_map = disp_cc_parent_map_1,
 484	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 485	.clkr.hw.init = &(const struct clk_init_data) {
 486		.name = "disp_cc_mdss_dptx2_pixel0_clk_src",
 487		.parent_data = disp_cc_parent_data_1,
 488		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 489		.flags = CLK_SET_RATE_PARENT,
 490		.ops = &clk_dp_ops,
 491	},
 492};
 493
 494static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = {
 495	.cmd_rcgr = 0x826c,
 496	.mnd_width = 16,
 497	.hid_width = 5,
 498	.parent_map = disp_cc_parent_map_1,
 499	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 500	.clkr.hw.init = &(const struct clk_init_data) {
 501		.name = "disp_cc_mdss_dptx2_pixel1_clk_src",
 502		.parent_data = disp_cc_parent_data_1,
 503		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 504		.flags = CLK_SET_RATE_PARENT,
 505		.ops = &clk_dp_ops,
 506	},
 507};
 508
 509static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = {
 510	.cmd_rcgr = 0x82d0,
 511	.mnd_width = 0,
 512	.hid_width = 5,
 513	.parent_map = disp_cc_parent_map_0,
 514	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 515	.clkr.hw.init = &(const struct clk_init_data) {
 516		.name = "disp_cc_mdss_dptx3_aux_clk_src",
 517		.parent_data = disp_cc_parent_data_0,
 518		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 519		.flags = CLK_SET_RATE_PARENT,
 520		.ops = &clk_rcg2_ops,
 521	},
 522};
 523
 524static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = {
 525	.cmd_rcgr = 0x82b4,
 526	.mnd_width = 0,
 527	.hid_width = 5,
 528	.parent_map = disp_cc_parent_map_3,
 529	.clkr.hw.init = &(const struct clk_init_data) {
 530		.name = "disp_cc_mdss_dptx3_link_clk_src",
 531		.parent_data = disp_cc_parent_data_3,
 532		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 533		.flags = CLK_SET_RATE_PARENT,
 534		.ops = &clk_byte2_ops,
 535	},
 536};
 537
 538static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = {
 539	.cmd_rcgr = 0x829c,
 540	.mnd_width = 16,
 541	.hid_width = 5,
 542	.parent_map = disp_cc_parent_map_1,
 543	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 544	.clkr.hw.init = &(const struct clk_init_data) {
 545		.name = "disp_cc_mdss_dptx3_pixel0_clk_src",
 546		.parent_data = disp_cc_parent_data_1,
 547		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 548		.flags = CLK_SET_RATE_PARENT,
 549		.ops = &clk_dp_ops,
 550	},
 551};
 552
 553static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
 554	.cmd_rcgr = 0x8140,
 555	.mnd_width = 0,
 556	.hid_width = 5,
 557	.parent_map = disp_cc_parent_map_5,
 558	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 559	.clkr.hw.init = &(const struct clk_init_data) {
 560		.name = "disp_cc_mdss_esc0_clk_src",
 561		.parent_data = disp_cc_parent_data_5,
 562		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
 563		.flags = CLK_SET_RATE_PARENT,
 564		.ops = &clk_rcg2_shared_ops,
 565	},
 566};
 567
 568static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
 569	.cmd_rcgr = 0x8158,
 570	.mnd_width = 0,
 571	.hid_width = 5,
 572	.parent_map = disp_cc_parent_map_5,
 573	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 574	.clkr.hw.init = &(const struct clk_init_data) {
 575		.name = "disp_cc_mdss_esc1_clk_src",
 576		.parent_data = disp_cc_parent_data_5,
 577		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
 578		.flags = CLK_SET_RATE_PARENT,
 579		.ops = &clk_rcg2_shared_ops,
 580	},
 581};
 582
 583static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
 584	F(19200000, P_BI_TCXO, 1, 0, 0),
 585	F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 586	F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 587	F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 588	F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 589	F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 590	F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 591	F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 592	F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 593	{ }
 594};
 595
 596static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sar2130p[] = {
 597	F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 598	F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 599	F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 600	{ }
 601};
 602
 603static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sm8650[] = {
 604	F(19200000, P_BI_TCXO, 1, 0, 0),
 605	F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 606	F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 607	F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 608	F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 609	F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 610	F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 611	F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 612	{ }
 613};
 614
 615static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
 616	.cmd_rcgr = 0x80d8,
 617	.mnd_width = 0,
 618	.hid_width = 5,
 619	.parent_map = disp_cc_parent_map_8,
 620	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
 621	.clkr.hw.init = &(const struct clk_init_data) {
 622		.name = "disp_cc_mdss_mdp_clk_src",
 623		.parent_data = disp_cc_parent_data_8,
 624		.num_parents = ARRAY_SIZE(disp_cc_parent_data_8),
 625		.flags = CLK_SET_RATE_PARENT,
 626		.ops = &clk_rcg2_shared_ops,
 627	},
 628};
 629
 630static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
 631	.cmd_rcgr = 0x80a8,
 632	.mnd_width = 8,
 633	.hid_width = 5,
 634	.parent_map = disp_cc_parent_map_2,
 635	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 636	.clkr.hw.init = &(const struct clk_init_data) {
 637		.name = "disp_cc_mdss_pclk0_clk_src",
 638		.parent_data = disp_cc_parent_data_2,
 639		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 640		.flags = CLK_SET_RATE_PARENT,
 641		.ops = &clk_pixel_ops,
 642	},
 643};
 644
 645static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
 646	.cmd_rcgr = 0x80c0,
 647	.mnd_width = 8,
 648	.hid_width = 5,
 649	.parent_map = disp_cc_parent_map_2,
 650	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 651	.clkr.hw.init = &(const struct clk_init_data) {
 652		.name = "disp_cc_mdss_pclk1_clk_src",
 653		.parent_data = disp_cc_parent_data_2,
 654		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 655		.flags = CLK_SET_RATE_PARENT,
 656		.ops = &clk_pixel_ops,
 657	},
 658};
 659
 660static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
 661	.cmd_rcgr = 0x80f0,
 662	.mnd_width = 0,
 663	.hid_width = 5,
 664	.parent_map = disp_cc_parent_map_0,
 665	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 666	.clkr.hw.init = &(const struct clk_init_data) {
 667		.name = "disp_cc_mdss_vsync_clk_src",
 668		.parent_data = disp_cc_parent_data_0,
 669		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 670		.flags = CLK_SET_RATE_PARENT,
 671		.ops = &clk_rcg2_ops,
 672	},
 673};
 674
 675static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
 676	F(32000, P_SLEEP_CLK, 1, 0, 0),
 677	{ }
 678};
 679
 680static struct clk_rcg2 disp_cc_sleep_clk_src = {
 681	.cmd_rcgr = 0xe05c,
 682	.mnd_width = 0,
 683	.hid_width = 5,
 684	.parent_map = disp_cc_parent_map_9,
 685	.freq_tbl = ftbl_disp_cc_sleep_clk_src,
 686	.clkr.hw.init = &(const struct clk_init_data) {
 687		.name = "disp_cc_sleep_clk_src",
 688		.parent_data = disp_cc_parent_data_9,
 689		.num_parents = ARRAY_SIZE(disp_cc_parent_data_9),
 690		.flags = CLK_SET_RATE_PARENT,
 691		.ops = &clk_rcg2_ops,
 692	},
 693};
 694
 695static struct clk_rcg2 disp_cc_xo_clk_src = {
 696	.cmd_rcgr = 0xe03c,
 697	.mnd_width = 0,
 698	.hid_width = 5,
 699	.parent_map = disp_cc_parent_map_0,
 700	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 701	.clkr.hw.init = &(const struct clk_init_data) {
 702		.name = "disp_cc_xo_clk_src",
 703		.parent_data = disp_cc_parent_data_0_ao,
 704		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao),
 705		.flags = CLK_SET_RATE_PARENT,
 706		.ops = &clk_rcg2_ops,
 707	},
 708};
 709
 710static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
 711	.reg = 0x8120,
 712	.shift = 0,
 713	.width = 4,
 714	.clkr.hw.init = &(const struct clk_init_data) {
 715		.name = "disp_cc_mdss_byte0_div_clk_src",
 716		.parent_hws = (const struct clk_hw*[]) {
 717			&disp_cc_mdss_byte0_clk_src.clkr.hw,
 718		},
 719		.num_parents = 1,
 720		.ops = &clk_regmap_div_ops,
 721	},
 722};
 723
 724static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
 725	.reg = 0x813c,
 726	.shift = 0,
 727	.width = 4,
 728	.clkr.hw.init = &(const struct clk_init_data) {
 729		.name = "disp_cc_mdss_byte1_div_clk_src",
 730		.parent_hws = (const struct clk_hw*[]) {
 731			&disp_cc_mdss_byte1_clk_src.clkr.hw,
 732		},
 733		.num_parents = 1,
 734		.ops = &clk_regmap_div_ops,
 735	},
 736};
 737
 738static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = {
 739	.reg = 0x8188,
 740	.shift = 0,
 741	.width = 4,
 742	.clkr.hw.init = &(const struct clk_init_data) {
 743		.name = "disp_cc_mdss_dptx0_link_div_clk_src",
 744		.parent_hws = (const struct clk_hw*[]) {
 745			&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
 746		},
 747		.num_parents = 1,
 748		.flags = CLK_SET_RATE_PARENT,
 749		.ops = &clk_regmap_div_ro_ops,
 750	},
 751};
 752
 753static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = {
 754	.reg = 0x821c,
 755	.shift = 0,
 756	.width = 4,
 757	.clkr.hw.init = &(const struct clk_init_data) {
 758		.name = "disp_cc_mdss_dptx1_link_div_clk_src",
 759		.parent_hws = (const struct clk_hw*[]) {
 760			&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
 761		},
 762		.num_parents = 1,
 763		.flags = CLK_SET_RATE_PARENT,
 764		.ops = &clk_regmap_div_ro_ops,
 765	},
 766};
 767
 768static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = {
 769	.reg = 0x8250,
 770	.shift = 0,
 771	.width = 4,
 772	.clkr.hw.init = &(const struct clk_init_data) {
 773		.name = "disp_cc_mdss_dptx2_link_div_clk_src",
 774		.parent_hws = (const struct clk_hw*[]) {
 775			&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
 776		},
 777		.num_parents = 1,
 778		.flags = CLK_SET_RATE_PARENT,
 779		.ops = &clk_regmap_div_ro_ops,
 780	},
 781};
 782
 783static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = {
 784	.reg = 0x82cc,
 785	.shift = 0,
 786	.width = 4,
 787	.clkr.hw.init = &(const struct clk_init_data) {
 788		.name = "disp_cc_mdss_dptx3_link_div_clk_src",
 789		.parent_hws = (const struct clk_hw*[]) {
 790			&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
 791		},
 792		.num_parents = 1,
 793		.flags = CLK_SET_RATE_PARENT,
 794		.ops = &clk_regmap_div_ro_ops,
 795	},
 796};
 797
 798static struct clk_branch disp_cc_mdss_accu_clk = {
 799	.halt_reg = 0xe058,
 800	.halt_check = BRANCH_HALT_VOTED,
 801	.clkr = {
 802		.enable_reg = 0xe058,
 803		.enable_mask = BIT(0),
 804		.hw.init = &(const struct clk_init_data) {
 805			.name = "disp_cc_mdss_accu_clk",
 806			.parent_hws = (const struct clk_hw*[]) {
 807				&disp_cc_xo_clk_src.clkr.hw,
 808			},
 809			.num_parents = 1,
 810			.flags = CLK_SET_RATE_PARENT,
 811			.ops = &clk_branch2_ops,
 812		},
 813	},
 814};
 815
 816static struct clk_branch disp_cc_mdss_ahb1_clk = {
 817	.halt_reg = 0xa020,
 818	.halt_check = BRANCH_HALT,
 819	.clkr = {
 820		.enable_reg = 0xa020,
 821		.enable_mask = BIT(0),
 822		.hw.init = &(const struct clk_init_data) {
 823			.name = "disp_cc_mdss_ahb1_clk",
 824			.parent_hws = (const struct clk_hw*[]) {
 825				&disp_cc_mdss_ahb_clk_src.clkr.hw,
 826			},
 827			.num_parents = 1,
 828			.flags = CLK_SET_RATE_PARENT,
 829			.ops = &clk_branch2_ops,
 830		},
 831	},
 832};
 833
 834static struct clk_branch disp_cc_mdss_ahb_clk = {
 835	.halt_reg = 0x80a4,
 836	.halt_check = BRANCH_HALT,
 837	.clkr = {
 838		.enable_reg = 0x80a4,
 839		.enable_mask = BIT(0),
 840		.hw.init = &(const struct clk_init_data) {
 841			.name = "disp_cc_mdss_ahb_clk",
 842			.parent_hws = (const struct clk_hw*[]) {
 843				&disp_cc_mdss_ahb_clk_src.clkr.hw,
 844			},
 845			.num_parents = 1,
 846			.flags = CLK_SET_RATE_PARENT,
 847			.ops = &clk_branch2_ops,
 848		},
 849	},
 850};
 851
 852static struct clk_branch disp_cc_mdss_byte0_clk = {
 853	.halt_reg = 0x8028,
 854	.halt_check = BRANCH_HALT,
 855	.clkr = {
 856		.enable_reg = 0x8028,
 857		.enable_mask = BIT(0),
 858		.hw.init = &(const struct clk_init_data) {
 859			.name = "disp_cc_mdss_byte0_clk",
 860			.parent_hws = (const struct clk_hw*[]) {
 861				&disp_cc_mdss_byte0_clk_src.clkr.hw,
 862			},
 863			.num_parents = 1,
 864			.flags = CLK_SET_RATE_PARENT,
 865			.ops = &clk_branch2_ops,
 866		},
 867	},
 868};
 869
 870static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
 871	.halt_reg = 0x802c,
 872	.halt_check = BRANCH_HALT,
 873	.clkr = {
 874		.enable_reg = 0x802c,
 875		.enable_mask = BIT(0),
 876		.hw.init = &(const struct clk_init_data) {
 877			.name = "disp_cc_mdss_byte0_intf_clk",
 878			.parent_hws = (const struct clk_hw*[]) {
 879				&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
 880			},
 881			.num_parents = 1,
 882			.flags = CLK_SET_RATE_PARENT,
 883			.ops = &clk_branch2_ops,
 884		},
 885	},
 886};
 887
 888static struct clk_branch disp_cc_mdss_byte1_clk = {
 889	.halt_reg = 0x8030,
 890	.halt_check = BRANCH_HALT,
 891	.clkr = {
 892		.enable_reg = 0x8030,
 893		.enable_mask = BIT(0),
 894		.hw.init = &(const struct clk_init_data) {
 895			.name = "disp_cc_mdss_byte1_clk",
 896			.parent_hws = (const struct clk_hw*[]) {
 897				&disp_cc_mdss_byte1_clk_src.clkr.hw,
 898			},
 899			.num_parents = 1,
 900			.flags = CLK_SET_RATE_PARENT,
 901			.ops = &clk_branch2_ops,
 902		},
 903	},
 904};
 905
 906static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
 907	.halt_reg = 0x8034,
 908	.halt_check = BRANCH_HALT,
 909	.clkr = {
 910		.enable_reg = 0x8034,
 911		.enable_mask = BIT(0),
 912		.hw.init = &(const struct clk_init_data) {
 913			.name = "disp_cc_mdss_byte1_intf_clk",
 914			.parent_hws = (const struct clk_hw*[]) {
 915				&disp_cc_mdss_byte1_div_clk_src.clkr.hw,
 916			},
 917			.num_parents = 1,
 918			.flags = CLK_SET_RATE_PARENT,
 919			.ops = &clk_branch2_ops,
 920		},
 921	},
 922};
 923
 924static struct clk_branch disp_cc_mdss_dptx0_aux_clk = {
 925	.halt_reg = 0x8058,
 926	.halt_check = BRANCH_HALT,
 927	.clkr = {
 928		.enable_reg = 0x8058,
 929		.enable_mask = BIT(0),
 930		.hw.init = &(const struct clk_init_data) {
 931			.name = "disp_cc_mdss_dptx0_aux_clk",
 932			.parent_hws = (const struct clk_hw*[]) {
 933				&disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
 934			},
 935			.num_parents = 1,
 936			.flags = CLK_SET_RATE_PARENT,
 937			.ops = &clk_branch2_ops,
 938		},
 939	},
 940};
 941
 942static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = {
 943	.halt_reg = 0x804c,
 944	.halt_check = BRANCH_HALT,
 945	.clkr = {
 946		.enable_reg = 0x804c,
 947		.enable_mask = BIT(0),
 948		.hw.init = &(const struct clk_init_data) {
 949			.name = "disp_cc_mdss_dptx0_crypto_clk",
 950			.parent_hws = (const struct clk_hw*[]) {
 951				&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
 952			},
 953			.num_parents = 1,
 954			.flags = CLK_SET_RATE_PARENT,
 955			.ops = &clk_branch2_ops,
 956		},
 957	},
 958};
 959
 960static struct clk_branch disp_cc_mdss_dptx0_link_clk = {
 961	.halt_reg = 0x8040,
 962	.halt_check = BRANCH_HALT,
 963	.clkr = {
 964		.enable_reg = 0x8040,
 965		.enable_mask = BIT(0),
 966		.hw.init = &(const struct clk_init_data) {
 967			.name = "disp_cc_mdss_dptx0_link_clk",
 968			.parent_hws = (const struct clk_hw*[]) {
 969				&disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
 970			},
 971			.num_parents = 1,
 972			.flags = CLK_SET_RATE_PARENT,
 973			.ops = &clk_branch2_ops,
 974		},
 975	},
 976};
 977
 978static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = {
 979	.halt_reg = 0x8048,
 980	.halt_check = BRANCH_HALT,
 981	.clkr = {
 982		.enable_reg = 0x8048,
 983		.enable_mask = BIT(0),
 984		.hw.init = &(const struct clk_init_data) {
 985			.name = "disp_cc_mdss_dptx0_link_intf_clk",
 986			.parent_hws = (const struct clk_hw*[]) {
 987				&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
 988			},
 989			.num_parents = 1,
 990			.flags = CLK_SET_RATE_PARENT,
 991			.ops = &clk_branch2_ops,
 992		},
 993	},
 994};
 995
 996static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = {
 997	.halt_reg = 0x8050,
 998	.halt_check = BRANCH_HALT,
 999	.clkr = {
1000		.enable_reg = 0x8050,
1001		.enable_mask = BIT(0),
1002		.hw.init = &(const struct clk_init_data) {
1003			.name = "disp_cc_mdss_dptx0_pixel0_clk",
1004			.parent_hws = (const struct clk_hw*[]) {
1005				&disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
1006			},
1007			.num_parents = 1,
1008			.flags = CLK_SET_RATE_PARENT,
1009			.ops = &clk_branch2_ops,
1010		},
1011	},
1012};
1013
1014static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = {
1015	.halt_reg = 0x8054,
1016	.halt_check = BRANCH_HALT,
1017	.clkr = {
1018		.enable_reg = 0x8054,
1019		.enable_mask = BIT(0),
1020		.hw.init = &(const struct clk_init_data) {
1021			.name = "disp_cc_mdss_dptx0_pixel1_clk",
1022			.parent_hws = (const struct clk_hw*[]) {
1023				&disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
1024			},
1025			.num_parents = 1,
1026			.flags = CLK_SET_RATE_PARENT,
1027			.ops = &clk_branch2_ops,
1028		},
1029	},
1030};
1031
1032static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
1033	.halt_reg = 0x8044,
1034	.halt_check = BRANCH_HALT,
1035	.clkr = {
1036		.enable_reg = 0x8044,
1037		.enable_mask = BIT(0),
1038		.hw.init = &(const struct clk_init_data) {
1039			.name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk",
1040			.parent_hws = (const struct clk_hw*[]) {
1041				&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1042			},
1043			.num_parents = 1,
1044			.flags = CLK_SET_RATE_PARENT,
1045			.ops = &clk_branch2_ops,
1046		},
1047	},
1048};
1049
1050static struct clk_branch disp_cc_mdss_dptx1_aux_clk = {
1051	.halt_reg = 0x8074,
1052	.halt_check = BRANCH_HALT,
1053	.clkr = {
1054		.enable_reg = 0x8074,
1055		.enable_mask = BIT(0),
1056		.hw.init = &(const struct clk_init_data) {
1057			.name = "disp_cc_mdss_dptx1_aux_clk",
1058			.parent_hws = (const struct clk_hw*[]) {
1059				&disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
1060			},
1061			.num_parents = 1,
1062			.flags = CLK_SET_RATE_PARENT,
1063			.ops = &clk_branch2_ops,
1064		},
1065	},
1066};
1067
1068static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = {
1069	.halt_reg = 0x8070,
1070	.halt_check = BRANCH_HALT,
1071	.clkr = {
1072		.enable_reg = 0x8070,
1073		.enable_mask = BIT(0),
1074		.hw.init = &(const struct clk_init_data) {
1075			.name = "disp_cc_mdss_dptx1_crypto_clk",
1076			.parent_hws = (const struct clk_hw*[]) {
1077				&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1078			},
1079			.num_parents = 1,
1080			.flags = CLK_SET_RATE_PARENT,
1081			.ops = &clk_branch2_ops,
1082		},
1083	},
1084};
1085
1086static struct clk_branch disp_cc_mdss_dptx1_link_clk = {
1087	.halt_reg = 0x8064,
1088	.halt_check = BRANCH_HALT,
1089	.clkr = {
1090		.enable_reg = 0x8064,
1091		.enable_mask = BIT(0),
1092		.hw.init = &(const struct clk_init_data) {
1093			.name = "disp_cc_mdss_dptx1_link_clk",
1094			.parent_hws = (const struct clk_hw*[]) {
1095				&disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
1096			},
1097			.num_parents = 1,
1098			.flags = CLK_SET_RATE_PARENT,
1099			.ops = &clk_branch2_ops,
1100		},
1101	},
1102};
1103
1104static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = {
1105	.halt_reg = 0x806c,
1106	.halt_check = BRANCH_HALT,
1107	.clkr = {
1108		.enable_reg = 0x806c,
1109		.enable_mask = BIT(0),
1110		.hw.init = &(const struct clk_init_data) {
1111			.name = "disp_cc_mdss_dptx1_link_intf_clk",
1112			.parent_hws = (const struct clk_hw*[]) {
1113				&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
1114			},
1115			.num_parents = 1,
1116			.flags = CLK_SET_RATE_PARENT,
1117			.ops = &clk_branch2_ops,
1118		},
1119	},
1120};
1121
1122static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = {
1123	.halt_reg = 0x805c,
1124	.halt_check = BRANCH_HALT,
1125	.clkr = {
1126		.enable_reg = 0x805c,
1127		.enable_mask = BIT(0),
1128		.hw.init = &(const struct clk_init_data) {
1129			.name = "disp_cc_mdss_dptx1_pixel0_clk",
1130			.parent_hws = (const struct clk_hw*[]) {
1131				&disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
1132			},
1133			.num_parents = 1,
1134			.flags = CLK_SET_RATE_PARENT,
1135			.ops = &clk_branch2_ops,
1136		},
1137	},
1138};
1139
1140static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = {
1141	.halt_reg = 0x8060,
1142	.halt_check = BRANCH_HALT,
1143	.clkr = {
1144		.enable_reg = 0x8060,
1145		.enable_mask = BIT(0),
1146		.hw.init = &(const struct clk_init_data) {
1147			.name = "disp_cc_mdss_dptx1_pixel1_clk",
1148			.parent_hws = (const struct clk_hw*[]) {
1149				&disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
1150			},
1151			.num_parents = 1,
1152			.flags = CLK_SET_RATE_PARENT,
1153			.ops = &clk_branch2_ops,
1154		},
1155	},
1156};
1157
1158static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
1159	.halt_reg = 0x8068,
1160	.halt_check = BRANCH_HALT,
1161	.clkr = {
1162		.enable_reg = 0x8068,
1163		.enable_mask = BIT(0),
1164		.hw.init = &(const struct clk_init_data) {
1165			.name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk",
1166			.parent_hws = (const struct clk_hw*[]) {
1167				&disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
1168			},
1169			.num_parents = 1,
1170			.flags = CLK_SET_RATE_PARENT,
1171			.ops = &clk_branch2_ops,
1172		},
1173	},
1174};
1175
1176static struct clk_branch disp_cc_mdss_dptx2_aux_clk = {
1177	.halt_reg = 0x808c,
1178	.halt_check = BRANCH_HALT,
1179	.clkr = {
1180		.enable_reg = 0x808c,
1181		.enable_mask = BIT(0),
1182		.hw.init = &(const struct clk_init_data) {
1183			.name = "disp_cc_mdss_dptx2_aux_clk",
1184			.parent_hws = (const struct clk_hw*[]) {
1185				&disp_cc_mdss_dptx2_aux_clk_src.clkr.hw,
1186			},
1187			.num_parents = 1,
1188			.flags = CLK_SET_RATE_PARENT,
1189			.ops = &clk_branch2_ops,
1190		},
1191	},
1192};
1193
1194static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = {
1195	.halt_reg = 0x8088,
1196	.halt_check = BRANCH_HALT,
1197	.clkr = {
1198		.enable_reg = 0x8088,
1199		.enable_mask = BIT(0),
1200		.hw.init = &(const struct clk_init_data) {
1201			.name = "disp_cc_mdss_dptx2_crypto_clk",
1202			.parent_hws = (const struct clk_hw*[]) {
1203				&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1204			},
1205			.num_parents = 1,
1206			.flags = CLK_SET_RATE_PARENT,
1207			.ops = &clk_branch2_ops,
1208		},
1209	},
1210};
1211
1212static struct clk_branch disp_cc_mdss_dptx2_link_clk = {
1213	.halt_reg = 0x8080,
1214	.halt_check = BRANCH_HALT,
1215	.clkr = {
1216		.enable_reg = 0x8080,
1217		.enable_mask = BIT(0),
1218		.hw.init = &(const struct clk_init_data) {
1219			.name = "disp_cc_mdss_dptx2_link_clk",
1220			.parent_hws = (const struct clk_hw*[]) {
1221				&disp_cc_mdss_dptx2_link_clk_src.clkr.hw,
1222			},
1223			.num_parents = 1,
1224			.flags = CLK_SET_RATE_PARENT,
1225			.ops = &clk_branch2_ops,
1226		},
1227	},
1228};
1229
1230static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = {
1231	.halt_reg = 0x8084,
1232	.halt_check = BRANCH_HALT,
1233	.clkr = {
1234		.enable_reg = 0x8084,
1235		.enable_mask = BIT(0),
1236		.hw.init = &(const struct clk_init_data) {
1237			.name = "disp_cc_mdss_dptx2_link_intf_clk",
1238			.parent_hws = (const struct clk_hw*[]) {
1239				&disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw,
1240			},
1241			.num_parents = 1,
1242			.flags = CLK_SET_RATE_PARENT,
1243			.ops = &clk_branch2_ops,
1244		},
1245	},
1246};
1247
1248static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = {
1249	.halt_reg = 0x8078,
1250	.halt_check = BRANCH_HALT,
1251	.clkr = {
1252		.enable_reg = 0x8078,
1253		.enable_mask = BIT(0),
1254		.hw.init = &(const struct clk_init_data) {
1255			.name = "disp_cc_mdss_dptx2_pixel0_clk",
1256			.parent_hws = (const struct clk_hw*[]) {
1257				&disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw,
1258			},
1259			.num_parents = 1,
1260			.flags = CLK_SET_RATE_PARENT,
1261			.ops = &clk_branch2_ops,
1262		},
1263	},
1264};
1265
1266static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = {
1267	.halt_reg = 0x807c,
1268	.halt_check = BRANCH_HALT,
1269	.clkr = {
1270		.enable_reg = 0x807c,
1271		.enable_mask = BIT(0),
1272		.hw.init = &(const struct clk_init_data) {
1273			.name = "disp_cc_mdss_dptx2_pixel1_clk",
1274			.parent_hws = (const struct clk_hw*[]) {
1275				&disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw,
1276			},
1277			.num_parents = 1,
1278			.flags = CLK_SET_RATE_PARENT,
1279			.ops = &clk_branch2_ops,
1280		},
1281	},
1282};
1283
1284static struct clk_branch disp_cc_mdss_dptx3_aux_clk = {
1285	.halt_reg = 0x809c,
1286	.halt_check = BRANCH_HALT,
1287	.clkr = {
1288		.enable_reg = 0x809c,
1289		.enable_mask = BIT(0),
1290		.hw.init = &(const struct clk_init_data) {
1291			.name = "disp_cc_mdss_dptx3_aux_clk",
1292			.parent_hws = (const struct clk_hw*[]) {
1293				&disp_cc_mdss_dptx3_aux_clk_src.clkr.hw,
1294			},
1295			.num_parents = 1,
1296			.flags = CLK_SET_RATE_PARENT,
1297			.ops = &clk_branch2_ops,
1298		},
1299	},
1300};
1301
1302static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = {
1303	.halt_reg = 0x80a0,
1304	.halt_check = BRANCH_HALT,
1305	.clkr = {
1306		.enable_reg = 0x80a0,
1307		.enable_mask = BIT(0),
1308		.hw.init = &(const struct clk_init_data) {
1309			.name = "disp_cc_mdss_dptx3_crypto_clk",
1310			.parent_hws = (const struct clk_hw*[]) {
1311				&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1312			},
1313			.num_parents = 1,
1314			.flags = CLK_SET_RATE_PARENT,
1315			.ops = &clk_branch2_ops,
1316		},
1317	},
1318};
1319
1320static struct clk_branch disp_cc_mdss_dptx3_link_clk = {
1321	.halt_reg = 0x8094,
1322	.halt_check = BRANCH_HALT,
1323	.clkr = {
1324		.enable_reg = 0x8094,
1325		.enable_mask = BIT(0),
1326		.hw.init = &(const struct clk_init_data) {
1327			.name = "disp_cc_mdss_dptx3_link_clk",
1328			.parent_hws = (const struct clk_hw*[]) {
1329				&disp_cc_mdss_dptx3_link_clk_src.clkr.hw,
1330			},
1331			.num_parents = 1,
1332			.flags = CLK_SET_RATE_PARENT,
1333			.ops = &clk_branch2_ops,
1334		},
1335	},
1336};
1337
1338static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = {
1339	.halt_reg = 0x8098,
1340	.halt_check = BRANCH_HALT,
1341	.clkr = {
1342		.enable_reg = 0x8098,
1343		.enable_mask = BIT(0),
1344		.hw.init = &(const struct clk_init_data) {
1345			.name = "disp_cc_mdss_dptx3_link_intf_clk",
1346			.parent_hws = (const struct clk_hw*[]) {
1347				&disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw,
1348			},
1349			.num_parents = 1,
1350			.flags = CLK_SET_RATE_PARENT,
1351			.ops = &clk_branch2_ops,
1352		},
1353	},
1354};
1355
1356static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = {
1357	.halt_reg = 0x8090,
1358	.halt_check = BRANCH_HALT,
1359	.clkr = {
1360		.enable_reg = 0x8090,
1361		.enable_mask = BIT(0),
1362		.hw.init = &(const struct clk_init_data) {
1363			.name = "disp_cc_mdss_dptx3_pixel0_clk",
1364			.parent_hws = (const struct clk_hw*[]) {
1365				&disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw,
1366			},
1367			.num_parents = 1,
1368			.flags = CLK_SET_RATE_PARENT,
1369			.ops = &clk_branch2_ops,
1370		},
1371	},
1372};
1373
1374static struct clk_branch disp_cc_mdss_esc0_clk = {
1375	.halt_reg = 0x8038,
1376	.halt_check = BRANCH_HALT,
1377	.clkr = {
1378		.enable_reg = 0x8038,
1379		.enable_mask = BIT(0),
1380		.hw.init = &(const struct clk_init_data) {
1381			.name = "disp_cc_mdss_esc0_clk",
1382			.parent_hws = (const struct clk_hw*[]) {
1383				&disp_cc_mdss_esc0_clk_src.clkr.hw,
1384			},
1385			.num_parents = 1,
1386			.flags = CLK_SET_RATE_PARENT,
1387			.ops = &clk_branch2_ops,
1388		},
1389	},
1390};
1391
1392static struct clk_branch disp_cc_mdss_esc1_clk = {
1393	.halt_reg = 0x803c,
1394	.halt_check = BRANCH_HALT,
1395	.clkr = {
1396		.enable_reg = 0x803c,
1397		.enable_mask = BIT(0),
1398		.hw.init = &(const struct clk_init_data) {
1399			.name = "disp_cc_mdss_esc1_clk",
1400			.parent_hws = (const struct clk_hw*[]) {
1401				&disp_cc_mdss_esc1_clk_src.clkr.hw,
1402			},
1403			.num_parents = 1,
1404			.flags = CLK_SET_RATE_PARENT,
1405			.ops = &clk_branch2_ops,
1406		},
1407	},
1408};
1409
1410static struct clk_branch disp_cc_mdss_mdp1_clk = {
1411	.halt_reg = 0xa004,
1412	.halt_check = BRANCH_HALT,
1413	.clkr = {
1414		.enable_reg = 0xa004,
1415		.enable_mask = BIT(0),
1416		.hw.init = &(const struct clk_init_data) {
1417			.name = "disp_cc_mdss_mdp1_clk",
1418			.parent_hws = (const struct clk_hw*[]) {
1419				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1420			},
1421			.num_parents = 1,
1422			.flags = CLK_SET_RATE_PARENT,
1423			.ops = &clk_branch2_ops,
1424		},
1425	},
1426};
1427
1428static struct clk_branch disp_cc_mdss_mdp_clk = {
1429	.halt_reg = 0x800c,
1430	.halt_check = BRANCH_HALT,
1431	.clkr = {
1432		.enable_reg = 0x800c,
1433		.enable_mask = BIT(0),
1434		.hw.init = &(const struct clk_init_data) {
1435			.name = "disp_cc_mdss_mdp_clk",
1436			.parent_hws = (const struct clk_hw*[]) {
1437				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1438			},
1439			.num_parents = 1,
1440			.flags = CLK_SET_RATE_PARENT,
1441			.ops = &clk_branch2_ops,
1442		},
1443	},
1444};
1445
1446static struct clk_branch disp_cc_mdss_mdp_lut1_clk = {
1447	.halt_reg = 0xa010,
1448	.halt_check = BRANCH_HALT,
1449	.clkr = {
1450		.enable_reg = 0xa010,
1451		.enable_mask = BIT(0),
1452		.hw.init = &(const struct clk_init_data) {
1453			.name = "disp_cc_mdss_mdp_lut1_clk",
1454			.parent_hws = (const struct clk_hw*[]) {
1455				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1456			},
1457			.num_parents = 1,
1458			.flags = CLK_SET_RATE_PARENT,
1459			.ops = &clk_branch2_ops,
1460		},
1461	},
1462};
1463
1464static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
1465	.halt_reg = 0x8018,
1466	.halt_check = BRANCH_HALT_VOTED,
1467	.clkr = {
1468		.enable_reg = 0x8018,
1469		.enable_mask = BIT(0),
1470		.hw.init = &(const struct clk_init_data) {
1471			.name = "disp_cc_mdss_mdp_lut_clk",
1472			.parent_hws = (const struct clk_hw*[]) {
1473				&disp_cc_mdss_mdp_clk_src.clkr.hw,
1474			},
1475			.num_parents = 1,
1476			.flags = CLK_SET_RATE_PARENT,
1477			.ops = &clk_branch2_ops,
1478		},
1479	},
1480};
1481
1482static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
1483	.halt_reg = 0xc004,
1484	.halt_check = BRANCH_HALT_VOTED,
1485	.clkr = {
1486		.enable_reg = 0xc004,
1487		.enable_mask = BIT(0),
1488		.hw.init = &(const struct clk_init_data) {
1489			.name = "disp_cc_mdss_non_gdsc_ahb_clk",
1490			.parent_hws = (const struct clk_hw*[]) {
1491				&disp_cc_mdss_ahb_clk_src.clkr.hw,
1492			},
1493			.num_parents = 1,
1494			.flags = CLK_SET_RATE_PARENT,
1495			.ops = &clk_branch2_ops,
1496		},
1497	},
1498};
1499
1500static struct clk_branch disp_cc_mdss_pclk0_clk = {
1501	.halt_reg = 0x8004,
1502	.halt_check = BRANCH_HALT,
1503	.clkr = {
1504		.enable_reg = 0x8004,
1505		.enable_mask = BIT(0),
1506		.hw.init = &(const struct clk_init_data) {
1507			.name = "disp_cc_mdss_pclk0_clk",
1508			.parent_hws = (const struct clk_hw*[]) {
1509				&disp_cc_mdss_pclk0_clk_src.clkr.hw,
1510			},
1511			.num_parents = 1,
1512			.flags = CLK_SET_RATE_PARENT,
1513			.ops = &clk_branch2_ops,
1514		},
1515	},
1516};
1517
1518static struct clk_branch disp_cc_mdss_pclk1_clk = {
1519	.halt_reg = 0x8008,
1520	.halt_check = BRANCH_HALT,
1521	.clkr = {
1522		.enable_reg = 0x8008,
1523		.enable_mask = BIT(0),
1524		.hw.init = &(const struct clk_init_data) {
1525			.name = "disp_cc_mdss_pclk1_clk",
1526			.parent_hws = (const struct clk_hw*[]) {
1527				&disp_cc_mdss_pclk1_clk_src.clkr.hw,
1528			},
1529			.num_parents = 1,
1530			.flags = CLK_SET_RATE_PARENT,
1531			.ops = &clk_branch2_ops,
1532		},
1533	},
1534};
1535
1536static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
1537	.halt_reg = 0xc00c,
1538	.halt_check = BRANCH_HALT,
1539	.clkr = {
1540		.enable_reg = 0xc00c,
1541		.enable_mask = BIT(0),
1542		.hw.init = &(const struct clk_init_data) {
1543			.name = "disp_cc_mdss_rscc_ahb_clk",
1544			.parent_hws = (const struct clk_hw*[]) {
1545				&disp_cc_mdss_ahb_clk_src.clkr.hw,
1546			},
1547			.num_parents = 1,
1548			.flags = CLK_SET_RATE_PARENT,
1549			.ops = &clk_branch2_ops,
1550		},
1551	},
1552};
1553
1554static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
1555	.halt_reg = 0xc008,
1556	.halt_check = BRANCH_HALT,
1557	.clkr = {
1558		.enable_reg = 0xc008,
1559		.enable_mask = BIT(0),
1560		.hw.init = &(const struct clk_init_data) {
1561			.name = "disp_cc_mdss_rscc_vsync_clk",
1562			.parent_hws = (const struct clk_hw*[]) {
1563				&disp_cc_mdss_vsync_clk_src.clkr.hw,
1564			},
1565			.num_parents = 1,
1566			.flags = CLK_SET_RATE_PARENT,
1567			.ops = &clk_branch2_ops,
1568		},
1569	},
1570};
1571
1572static struct clk_branch disp_cc_mdss_vsync1_clk = {
1573	.halt_reg = 0xa01c,
1574	.halt_check = BRANCH_HALT,
1575	.clkr = {
1576		.enable_reg = 0xa01c,
1577		.enable_mask = BIT(0),
1578		.hw.init = &(const struct clk_init_data) {
1579			.name = "disp_cc_mdss_vsync1_clk",
1580			.parent_hws = (const struct clk_hw*[]) {
1581				&disp_cc_mdss_vsync_clk_src.clkr.hw,
1582			},
1583			.num_parents = 1,
1584			.flags = CLK_SET_RATE_PARENT,
1585			.ops = &clk_branch2_ops,
1586		},
1587	},
1588};
1589
1590static struct clk_branch disp_cc_mdss_vsync_clk = {
1591	.halt_reg = 0x8024,
1592	.halt_check = BRANCH_HALT,
1593	.clkr = {
1594		.enable_reg = 0x8024,
1595		.enable_mask = BIT(0),
1596		.hw.init = &(const struct clk_init_data) {
1597			.name = "disp_cc_mdss_vsync_clk",
1598			.parent_hws = (const struct clk_hw*[]) {
1599				&disp_cc_mdss_vsync_clk_src.clkr.hw,
1600			},
1601			.num_parents = 1,
1602			.flags = CLK_SET_RATE_PARENT,
1603			.ops = &clk_branch2_ops,
1604		},
1605	},
1606};
1607
1608static struct clk_branch disp_cc_sleep_clk = {
1609	.halt_reg = 0xe074,
1610	.halt_check = BRANCH_HALT,
1611	.clkr = {
1612		.enable_reg = 0xe074,
1613		.enable_mask = BIT(0),
1614		.hw.init = &(const struct clk_init_data) {
1615			.name = "disp_cc_sleep_clk",
1616			.parent_hws = (const struct clk_hw*[]) {
1617				&disp_cc_sleep_clk_src.clkr.hw,
1618			},
1619			.num_parents = 1,
1620			.flags = CLK_SET_RATE_PARENT,
1621			.ops = &clk_branch2_ops,
1622		},
1623	},
1624};
1625
1626static struct gdsc mdss_gdsc = {
1627	.gdscr = 0x9000,
1628	.pd = {
1629		.name = "mdss_gdsc",
1630	},
1631	.pwrsts = PWRSTS_OFF_ON,
1632	.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
1633};
1634
1635static struct gdsc mdss_int2_gdsc = {
1636	.gdscr = 0xb000,
1637	.pd = {
1638		.name = "mdss_int2_gdsc",
1639	},
1640	.pwrsts = PWRSTS_OFF_ON,
1641	.flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
1642};
1643
1644static struct clk_regmap *disp_cc_sm8550_clocks[] = {
1645	[DISP_CC_MDSS_ACCU_CLK] = &disp_cc_mdss_accu_clk.clkr,
1646	[DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr,
1647	[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
1648	[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
1649	[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
1650	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
1651	[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
1652	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
1653	[DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
1654	[DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1655	[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
1656	[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
1657	[DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr,
1658	[DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr,
1659	[DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr,
1660	[DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr,
1661	[DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr,
1662	[DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr,
1663	[DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr,
1664	[DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr,
1665	[DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
1666	[DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr,
1667	[DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
1668	[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
1669		&disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
1670	[DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr,
1671	[DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr,
1672	[DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr,
1673	[DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr,
1674	[DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr,
1675	[DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr,
1676	[DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr,
1677	[DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr,
1678	[DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
1679	[DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr,
1680	[DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
1681	[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
1682		&disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
1683	[DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr,
1684	[DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr,
1685	[DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr,
1686	[DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr,
1687	[DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr,
1688	[DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr,
1689	[DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr,
1690	[DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr,
1691	[DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr,
1692	[DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr,
1693	[DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr,
1694	[DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr,
1695	[DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr,
1696	[DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr,
1697	[DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr,
1698	[DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr,
1699	[DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr,
1700	[DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr,
1701	[DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr,
1702	[DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr,
1703	[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
1704	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
1705	[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1706	[DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1707	[DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr,
1708	[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1709	[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1710	[DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr,
1711	[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1712	[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1713	[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1714	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1715	[DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1716	[DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1717	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
1718	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
1719	[DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr,
1720	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1721	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1722	[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1723	[DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1724	[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
1725	[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
1726	[DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
1727};
1728
1729static const struct qcom_reset_map disp_cc_sm8550_resets[] = {
1730	[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1731	[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
1732	[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
1733};
1734
1735static struct gdsc *disp_cc_sm8550_gdscs[] = {
1736	[MDSS_GDSC] = &mdss_gdsc,
1737	[MDSS_INT2_GDSC] = &mdss_int2_gdsc,
1738};
1739
1740static const struct regmap_config disp_cc_sm8550_regmap_config = {
1741	.reg_bits = 32,
1742	.reg_stride = 4,
1743	.val_bits = 32,
1744	.max_register = 0x11008,
1745	.fast_io = true,
1746};
1747
1748static const struct qcom_cc_desc disp_cc_sm8550_desc = {
1749	.config = &disp_cc_sm8550_regmap_config,
1750	.clks = disp_cc_sm8550_clocks,
1751	.num_clks = ARRAY_SIZE(disp_cc_sm8550_clocks),
1752	.resets = disp_cc_sm8550_resets,
1753	.num_resets = ARRAY_SIZE(disp_cc_sm8550_resets),
1754	.gdscs = disp_cc_sm8550_gdscs,
1755	.num_gdscs = ARRAY_SIZE(disp_cc_sm8550_gdscs),
1756};
1757
1758static const struct of_device_id disp_cc_sm8550_match_table[] = {
1759	{ .compatible = "qcom,sar2130p-dispcc" },
1760	{ .compatible = "qcom,sm8550-dispcc" },
1761	{ .compatible = "qcom,sm8650-dispcc" },
1762	{ }
1763};
1764MODULE_DEVICE_TABLE(of, disp_cc_sm8550_match_table);
1765
1766static int disp_cc_sm8550_probe(struct platform_device *pdev)
1767{
1768	struct regmap *regmap;
1769	int ret;
1770
1771	ret = devm_pm_runtime_enable(&pdev->dev);
1772	if (ret)
1773		return ret;
1774
1775	ret = pm_runtime_resume_and_get(&pdev->dev);
1776	if (ret)
1777		return ret;
1778
1779	regmap = qcom_cc_map(pdev, &disp_cc_sm8550_desc);
1780	if (IS_ERR(regmap)) {
1781		ret = PTR_ERR(regmap);
1782		goto err_put_rpm;
1783	}
1784
1785	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-dispcc")) {
1786		lucid_ole_vco[0].max_freq = 2100000000;
1787		disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sm8650;
1788		disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr.hw.init->parent_hws[0] =
1789			&disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw;
1790	} else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sar2130p-dispcc")) {
1791		disp_cc_pll0_config.l = 0x1f;
1792		disp_cc_pll0_config.alpha = 0x4000;
1793		disp_cc_pll0_config.user_ctl_val = 0x1;
1794		disp_cc_pll1_config.user_ctl_val = 0x1;
1795		disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sar2130p;
1796	}
1797
1798	clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1799	clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1800
1801	/* Enable clock gating for MDP clocks */
1802	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);
1803
1804	/* Keep some clocks always-on */
1805	qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */
1806
1807	ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8550_desc, regmap);
1808	if (ret)
1809		goto err_put_rpm;
1810
1811	pm_runtime_put(&pdev->dev);
1812
1813	return 0;
1814
1815err_put_rpm:
1816	pm_runtime_put_sync(&pdev->dev);
1817
1818	return ret;
1819}
1820
1821static struct platform_driver disp_cc_sm8550_driver = {
1822	.probe = disp_cc_sm8550_probe,
1823	.driver = {
1824		.name = "disp_cc-sm8550",
1825		.of_match_table = disp_cc_sm8550_match_table,
1826	},
1827};
1828
1829module_platform_driver(disp_cc_sm8550_driver);
1830
1831MODULE_DESCRIPTION("QTI DISPCC SM8550 / SM8650  Driver");
1832MODULE_LICENSE("GPL");