dispcc-sm6375.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
  4 * Copyright (c) 2022, Linaro Limited
  5 */
  6
  7#include <linux/clk-provider.h>
  8#include <linux/mod_devicetable.h>
  9#include <linux/module.h>
 10#include <linux/platform_device.h>
 11#include <linux/regmap.h>
 12
 13#include <dt-bindings/clock/qcom,sm6375-dispcc.h>
 14
 15#include "clk-alpha-pll.h"
 16#include "clk-branch.h"
 17#include "clk-rcg.h"
 18#include "clk-regmap-divider.h"
 19#include "common.h"
 20#include "gdsc.h"
 21#include "reset.h"
 22
 23enum {
 24	DT_BI_TCXO,
 25	DT_GCC_DISP_GPLL0_CLK,
 26	DT_DSI0_PHY_PLL_OUT_BYTECLK,
 27	DT_DSI0_PHY_PLL_OUT_DSICLK,
 28};
 29
 30enum {
 31	P_BI_TCXO,
 32	P_DISP_CC_PLL0_OUT_EVEN,
 33	P_DISP_CC_PLL0_OUT_MAIN,
 34	P_DSI0_PHY_PLL_OUT_BYTECLK,
 35	P_DSI0_PHY_PLL_OUT_DSICLK,
 36	P_GCC_DISP_GPLL0_CLK,
 37};
 38
 39static const struct pll_vco lucid_vco[] = {
 40	{ 249600000, 2000000000, 0 },
 41};
 42
 43/* 615MHz */
 44static const struct alpha_pll_config disp_cc_pll0_config = {
 45	.l = 0x20,
 46	.alpha = 0x800,
 47	.config_ctl_val = 0x20485699,
 48	.config_ctl_hi_val = 0x00002261,
 49	.config_ctl_hi1_val = 0x329a299c,
 50	.user_ctl_val = 0x00000001,
 51	.user_ctl_hi_val = 0x00000805,
 52	.user_ctl_hi1_val = 0x00000000,
 53};
 54
 55static struct clk_alpha_pll disp_cc_pll0 = {
 56	.offset = 0x0,
 57	.vco_table = lucid_vco,
 58	.num_vco = ARRAY_SIZE(lucid_vco),
 59	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 60	.clkr = {
 61		.hw.init = &(struct clk_init_data){
 62			.name = "disp_cc_pll0",
 63			.parent_data = &(const struct clk_parent_data){
 64				.index = DT_BI_TCXO,
 65			},
 66			.num_parents = 1,
 67			.ops = &clk_alpha_pll_lucid_ops,
 68		},
 69	},
 70};
 71
 72static const struct parent_map disp_cc_parent_map_0[] = {
 73	{ P_BI_TCXO, 0 },
 74	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
 75};
 76
 77static const struct clk_parent_data disp_cc_parent_data_0[] = {
 78	{ .index = DT_BI_TCXO },
 79	{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
 80};
 81
 82static const struct parent_map disp_cc_parent_map_1[] = {
 83	{ P_BI_TCXO, 0 },
 84	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
 85	{ P_GCC_DISP_GPLL0_CLK, 4 },
 86	{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
 87};
 88
 89static const struct clk_parent_data disp_cc_parent_data_1[] = {
 90	{ .index = DT_BI_TCXO },
 91	{ .hw = &disp_cc_pll0.clkr.hw },
 92	{ .index = DT_GCC_DISP_GPLL0_CLK },
 93	{ .hw = &disp_cc_pll0.clkr.hw },
 94};
 95
 96static const struct parent_map disp_cc_parent_map_2[] = {
 97	{ P_BI_TCXO, 0 },
 98	{ P_GCC_DISP_GPLL0_CLK, 4 },
 99};
100
101static const struct clk_parent_data disp_cc_parent_data_2[] = {
102	{ .index = DT_BI_TCXO },
103	{ .index = DT_GCC_DISP_GPLL0_CLK },
104};
105
106static const struct parent_map disp_cc_parent_map_3[] = {
107	{ P_BI_TCXO, 0 },
108	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
109};
110
111static const struct clk_parent_data disp_cc_parent_data_3[] = {
112	{ .index = DT_BI_TCXO },
113	{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
114};
115
116static const struct parent_map disp_cc_parent_map_4[] = {
117	{ P_BI_TCXO, 0 },
118};
119
120static const struct clk_parent_data disp_cc_parent_data_4[] = {
121	{ .index = DT_BI_TCXO },
122};
123
124static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
125	F(19200000, P_BI_TCXO, 1, 0, 0),
126	F(37500000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
127	F(75000000, P_GCC_DISP_GPLL0_CLK, 4, 0, 0),
128	{ }
129};
130
131static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
132	.cmd_rcgr = 0x115c,
133	.mnd_width = 0,
134	.hid_width = 5,
135	.parent_map = disp_cc_parent_map_2,
136	.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
137	.clkr.hw.init = &(struct clk_init_data){
138		.name = "disp_cc_mdss_ahb_clk_src",
139		.parent_data = disp_cc_parent_data_2,
140		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
141		.ops = &clk_rcg2_shared_ops,
142	},
143};
144
145static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
146	.cmd_rcgr = 0x10c4,
147	.mnd_width = 0,
148	.hid_width = 5,
149	.parent_map = disp_cc_parent_map_0,
150	.clkr.hw.init = &(struct clk_init_data){
151		.name = "disp_cc_mdss_byte0_clk_src",
152		.parent_data = disp_cc_parent_data_0,
153		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
154		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
155		.ops = &clk_byte2_ops,
156	},
157};
158
159static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
160	F(19200000, P_BI_TCXO, 1, 0, 0),
161	{ }
162};
163
164static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
165	.cmd_rcgr = 0x10e0,
166	.mnd_width = 0,
167	.hid_width = 5,
168	.parent_map = disp_cc_parent_map_0,
169	.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
170	.clkr.hw.init = &(struct clk_init_data){
171		.name = "disp_cc_mdss_esc0_clk_src",
172		.parent_data = disp_cc_parent_data_0,
173		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
174		.ops = &clk_rcg2_shared_ops,
175	},
176};
177
178static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
179	F(200000000, P_GCC_DISP_GPLL0_CLK, 1.5, 0, 0),
180	F(300000000, P_GCC_DISP_GPLL0_CLK, 1, 0, 0),
181	F(373500000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
182	F(470000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
183	F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
184	{ }
185};
186
187static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
188	.cmd_rcgr = 0x107c,
189	.mnd_width = 0,
190	.hid_width = 5,
191	.parent_map = disp_cc_parent_map_1,
192	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
193	.clkr.hw.init = &(struct clk_init_data){
194		.name = "disp_cc_mdss_mdp_clk_src",
195		.parent_data = disp_cc_parent_data_1,
196		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
197		.flags = CLK_SET_RATE_PARENT,
198		.ops = &clk_rcg2_shared_ops,
199	},
200};
201
202static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
203	.cmd_rcgr = 0x1064,
204	.mnd_width = 8,
205	.hid_width = 5,
206	.parent_map = disp_cc_parent_map_3,
207	.clkr.hw.init = &(struct clk_init_data){
208		.name = "disp_cc_mdss_pclk0_clk_src",
209		.parent_data = disp_cc_parent_data_3,
210		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
211		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
212		.ops = &clk_pixel_ops,
213	},
214};
215
216static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
217	F(200000000, P_GCC_DISP_GPLL0_CLK, 1.5, 0, 0),
218	F(300000000, P_GCC_DISP_GPLL0_CLK, 1, 0, 0),
219	{ }
220};
221
222static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
223	.cmd_rcgr = 0x1094,
224	.mnd_width = 0,
225	.hid_width = 5,
226	.parent_map = disp_cc_parent_map_1,
227	.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
228	.clkr.hw.init = &(struct clk_init_data){
229		.name = "disp_cc_mdss_rot_clk_src",
230		.parent_data = disp_cc_parent_data_1,
231		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
232		.ops = &clk_rcg2_shared_ops,
233	},
234};
235
236static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
237	.cmd_rcgr = 0x10ac,
238	.mnd_width = 0,
239	.hid_width = 5,
240	.parent_map = disp_cc_parent_map_4,
241	.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
242	.clkr.hw.init = &(struct clk_init_data){
243		.name = "disp_cc_mdss_vsync_clk_src",
244		.parent_data = disp_cc_parent_data_4,
245		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
246		.ops = &clk_rcg2_ops,
247	},
248};
249
250static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
251	.reg = 0x10dc,
252	.shift = 0,
253	.width = 4,
254	.clkr.hw.init = &(struct clk_init_data) {
255		.name = "disp_cc_mdss_byte0_div_clk_src",
256		.parent_hws = (const struct clk_hw*[]) {
257			&disp_cc_mdss_byte0_clk_src.clkr.hw,
258		},
259		.num_parents = 1,
260		.ops = &clk_regmap_div_ops,
261	},
262};
263
264static struct clk_branch disp_cc_mdss_ahb_clk = {
265	.halt_reg = 0x104c,
266	.halt_check = BRANCH_HALT,
267	.clkr = {
268		.enable_reg = 0x104c,
269		.enable_mask = BIT(0),
270		.hw.init = &(struct clk_init_data){
271			.name = "disp_cc_mdss_ahb_clk",
272			.parent_hws = (const struct clk_hw*[]){
273				&disp_cc_mdss_ahb_clk_src.clkr.hw,
274			},
275			.num_parents = 1,
276			.flags = CLK_SET_RATE_PARENT,
277			.ops = &clk_branch2_ops,
278		},
279	},
280};
281
282static struct clk_branch disp_cc_mdss_byte0_clk = {
283	.halt_reg = 0x102c,
284	.halt_check = BRANCH_HALT,
285	.clkr = {
286		.enable_reg = 0x102c,
287		.enable_mask = BIT(0),
288		.hw.init = &(struct clk_init_data){
289			.name = "disp_cc_mdss_byte0_clk",
290			.parent_hws = (const struct clk_hw*[]){
291				&disp_cc_mdss_byte0_clk_src.clkr.hw,
292			},
293			.num_parents = 1,
294			.flags = CLK_SET_RATE_PARENT,
295			.ops = &clk_branch2_ops,
296		},
297	},
298};
299
300static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
301	.halt_reg = 0x1030,
302	.halt_check = BRANCH_HALT,
303	.clkr = {
304		.enable_reg = 0x1030,
305		.enable_mask = BIT(0),
306		.hw.init = &(struct clk_init_data){
307			.name = "disp_cc_mdss_byte0_intf_clk",
308			.parent_hws = (const struct clk_hw*[]){
309				&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
310			},
311			.num_parents = 1,
312			.flags = CLK_SET_RATE_PARENT,
313			.ops = &clk_branch2_ops,
314		},
315	},
316};
317
318static struct clk_branch disp_cc_mdss_esc0_clk = {
319	.halt_reg = 0x1034,
320	.halt_check = BRANCH_HALT,
321	.clkr = {
322		.enable_reg = 0x1034,
323		.enable_mask = BIT(0),
324		.hw.init = &(struct clk_init_data){
325			.name = "disp_cc_mdss_esc0_clk",
326			.parent_hws = (const struct clk_hw*[]){
327				&disp_cc_mdss_esc0_clk_src.clkr.hw,
328			},
329			.num_parents = 1,
330			.flags = CLK_SET_RATE_PARENT,
331			.ops = &clk_branch2_ops,
332		},
333	},
334};
335
336static struct clk_branch disp_cc_mdss_mdp_clk = {
337	.halt_reg = 0x1010,
338	.halt_check = BRANCH_HALT,
339	.clkr = {
340		.enable_reg = 0x1010,
341		.enable_mask = BIT(0),
342		.hw.init = &(struct clk_init_data){
343			.name = "disp_cc_mdss_mdp_clk",
344			.parent_hws = (const struct clk_hw*[]){
345				&disp_cc_mdss_mdp_clk_src.clkr.hw,
346			},
347			.num_parents = 1,
348			.flags = CLK_SET_RATE_PARENT,
349			.ops = &clk_branch2_ops,
350		},
351	},
352};
353
354static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
355	.halt_reg = 0x1020,
356	.halt_check = BRANCH_HALT_VOTED,
357	.clkr = {
358		.enable_reg = 0x1020,
359		.enable_mask = BIT(0),
360		.hw.init = &(struct clk_init_data){
361			.name = "disp_cc_mdss_mdp_lut_clk",
362			.parent_hws = (const struct clk_hw*[]){
363				&disp_cc_mdss_mdp_clk_src.clkr.hw,
364			},
365			.num_parents = 1,
366			.flags = CLK_SET_RATE_PARENT,
367			.ops = &clk_branch2_ops,
368		},
369	},
370};
371
372static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
373	.halt_reg = 0x2004,
374	.halt_check = BRANCH_HALT_VOTED,
375	.clkr = {
376		.enable_reg = 0x2004,
377		.enable_mask = BIT(0),
378		.hw.init = &(struct clk_init_data){
379			.name = "disp_cc_mdss_non_gdsc_ahb_clk",
380			.parent_hws = (const struct clk_hw*[]){
381				&disp_cc_mdss_ahb_clk_src.clkr.hw,
382			},
383			.num_parents = 1,
384			.flags = CLK_SET_RATE_PARENT,
385			.ops = &clk_branch2_ops,
386		},
387	},
388};
389
390static struct clk_branch disp_cc_mdss_pclk0_clk = {
391	.halt_reg = 0x1168,
392	.halt_check = BRANCH_HALT,
393	.clkr = {
394		.enable_reg = 0x1168,
395		.enable_mask = BIT(0),
396		.hw.init = &(struct clk_init_data){
397			.name = "disp_cc_mdss_pclk0_clk",
398			.parent_hws = (const struct clk_hw*[]){
399				&disp_cc_mdss_pclk0_clk_src.clkr.hw,
400			},
401			.num_parents = 1,
402			.flags = CLK_SET_RATE_PARENT,
403			.ops = &clk_branch2_ops,
404		},
405	},
406};
407
408static struct clk_branch disp_cc_mdss_rot_clk = {
409	.halt_reg = 0x1018,
410	.halt_check = BRANCH_HALT,
411	.clkr = {
412		.enable_reg = 0x1018,
413		.enable_mask = BIT(0),
414		.hw.init = &(struct clk_init_data){
415			.name = "disp_cc_mdss_rot_clk",
416			.parent_hws = (const struct clk_hw*[]){
417				&disp_cc_mdss_rot_clk_src.clkr.hw,
418			},
419			.num_parents = 1,
420			.flags = CLK_SET_RATE_PARENT,
421			.ops = &clk_branch2_ops,
422		},
423	},
424};
425
426static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
427	.halt_reg = 0x200c,
428	.halt_check = BRANCH_HALT,
429	.clkr = {
430		.enable_reg = 0x200c,
431		.enable_mask = BIT(0),
432		.hw.init = &(struct clk_init_data){
433			.name = "disp_cc_mdss_rscc_ahb_clk",
434			.parent_hws = (const struct clk_hw*[]){
435				&disp_cc_mdss_ahb_clk_src.clkr.hw,
436			},
437			.num_parents = 1,
438			.flags = CLK_SET_RATE_PARENT,
439			.ops = &clk_branch2_ops,
440		},
441	},
442};
443
444static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
445	.halt_reg = 0x2008,
446	.halt_check = BRANCH_HALT,
447	.clkr = {
448		.enable_reg = 0x2008,
449		.enable_mask = BIT(0),
450		.hw.init = &(struct clk_init_data){
451			.name = "disp_cc_mdss_rscc_vsync_clk",
452			.parent_hws = (const struct clk_hw*[]){
453				&disp_cc_mdss_vsync_clk_src.clkr.hw,
454			},
455			.num_parents = 1,
456			.flags = CLK_SET_RATE_PARENT,
457			.ops = &clk_branch2_ops,
458		},
459	},
460};
461
462static struct clk_branch disp_cc_mdss_vsync_clk = {
463	.halt_reg = 0x1028,
464	.halt_check = BRANCH_HALT,
465	.clkr = {
466		.enable_reg = 0x1028,
467		.enable_mask = BIT(0),
468		.hw.init = &(struct clk_init_data){
469			.name = "disp_cc_mdss_vsync_clk",
470			.parent_hws = (const struct clk_hw*[]){
471				&disp_cc_mdss_vsync_clk_src.clkr.hw,
472			},
473			.num_parents = 1,
474			.flags = CLK_SET_RATE_PARENT,
475			.ops = &clk_branch2_ops,
476		},
477	},
478};
479
480static struct clk_branch disp_cc_sleep_clk = {
481	.halt_check = BRANCH_HALT,
482	.clkr = {
483		.enable_reg = 0x5004,
484		.enable_mask = BIT(0),
485		.hw.init = &(struct clk_init_data){
486			.name = "disp_cc_sleep_clk",
487			.flags = CLK_IS_CRITICAL,
488			.ops = &clk_branch2_ops,
489		},
490	},
491};
492
493static struct clk_branch disp_cc_xo_clk = {
494	.halt_check = BRANCH_HALT,
495	.clkr = {
496		.enable_reg = 0x5008,
497		.enable_mask = BIT(0),
498		.hw.init = &(struct clk_init_data){
499			.name = "disp_cc_xo_clk",
500			.flags = CLK_IS_CRITICAL,
501			.ops = &clk_branch2_ops,
502		},
503	},
504};
505
506static struct gdsc mdss_gdsc = {
507	.gdscr = 0x1004,
508	.en_rest_wait_val = 0x2,
509	.en_few_wait_val = 0x2,
510	.clk_dis_wait_val = 0xf,
511	.pd = {
512		.name = "mdss_gdsc",
513	},
514	.pwrsts = PWRSTS_OFF_ON,
515	.flags = HW_CTRL,
516};
517
518static struct clk_regmap *disp_cc_sm6375_clocks[] = {
519	[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
520	[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
521	[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
522	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
523	[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
524	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
525	[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
526	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
527	[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
528	[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
529	[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
530	[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
531	[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
532	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
533	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
534	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
535	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
536	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
537	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
538	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
539	[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
540	[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
541	[DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr,
542};
543
544static const struct qcom_reset_map disp_cc_sm6375_resets[] = {
545	[DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
546	[DISP_CC_MDSS_RSCC_BCR] = { 0x2000 },
547};
548
549static struct gdsc *disp_cc_sm6375_gdscs[] = {
550	[MDSS_GDSC] = &mdss_gdsc,
551};
552
553static const struct regmap_config disp_cc_sm6375_regmap_config = {
554	.reg_bits = 32,
555	.reg_stride = 4,
556	.val_bits = 32,
557	.max_register = 0x10000,
558	.fast_io = true,
559};
560
561static const struct qcom_cc_desc disp_cc_sm6375_desc = {
562	.config = &disp_cc_sm6375_regmap_config,
563	.clks = disp_cc_sm6375_clocks,
564	.num_clks = ARRAY_SIZE(disp_cc_sm6375_clocks),
565	.resets = disp_cc_sm6375_resets,
566	.num_resets = ARRAY_SIZE(disp_cc_sm6375_resets),
567	.gdscs = disp_cc_sm6375_gdscs,
568	.num_gdscs = ARRAY_SIZE(disp_cc_sm6375_gdscs),
569};
570
571static const struct of_device_id disp_cc_sm6375_match_table[] = {
572	{ .compatible = "qcom,sm6375-dispcc" },
573	{ }
574};
575MODULE_DEVICE_TABLE(of, disp_cc_sm6375_match_table);
576
577static int disp_cc_sm6375_probe(struct platform_device *pdev)
578{
579	struct regmap *regmap;
580
581	regmap = qcom_cc_map(pdev, &disp_cc_sm6375_desc);
582	if (IS_ERR(regmap))
583		return PTR_ERR(regmap);
584
585	clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
586
587	return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6375_desc, regmap);
588}
589
590static struct platform_driver disp_cc_sm6375_driver = {
591	.probe = disp_cc_sm6375_probe,
592	.driver = {
593		.name = "disp_cc-sm6375",
594		.of_match_table = disp_cc_sm6375_match_table,
595	},
596};
597
598module_platform_driver(disp_cc_sm6375_driver);
599
600MODULE_DESCRIPTION("QTI DISPCC SM6375 Driver");
601MODULE_LICENSE("GPL");