dispcc-sm6125.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
  4 */
  5
  6#include <linux/clk-provider.h>
  7#include <linux/mod_devicetable.h>
  8#include <linux/module.h>
  9#include <linux/platform_device.h>
 10#include <linux/regmap.h>
 11
 12#include <dt-bindings/clock/qcom,dispcc-sm6125.h>
 13
 14#include "clk-alpha-pll.h"
 15#include "clk-branch.h"
 16#include "clk-rcg.h"
 17#include "clk-regmap.h"
 18#include "common.h"
 19#include "gdsc.h"
 20
 21enum {
 22	P_BI_TCXO,
 23	P_DISP_CC_PLL0_OUT_MAIN,
 24	P_DP_PHY_PLL_LINK_CLK,
 25	P_DP_PHY_PLL_VCO_DIV_CLK,
 26	P_DSI0_PHY_PLL_OUT_BYTECLK,
 27	P_DSI0_PHY_PLL_OUT_DSICLK,
 28	P_DSI1_PHY_PLL_OUT_DSICLK,
 29	P_GPLL0_OUT_MAIN,
 30};
 31
 32static const struct pll_vco disp_cc_pll_vco[] = {
 33	{ 500000000, 1000000000, 2 },
 34};
 35
 36static struct clk_alpha_pll disp_cc_pll0 = {
 37	.offset = 0x0,
 38	.vco_table = disp_cc_pll_vco,
 39	.num_vco = ARRAY_SIZE(disp_cc_pll_vco),
 40	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 41	.flags = SUPPORTS_DYNAMIC_UPDATE,
 42	.clkr = {
 43		.hw.init = &(struct clk_init_data){
 44			.name = "disp_cc_pll0",
 45			.parent_data = &(const struct clk_parent_data){
 46				.fw_name = "bi_tcxo",
 47			},
 48			.num_parents = 1,
 49			.ops = &clk_alpha_pll_ops,
 50		},
 51	},
 52};
 53
 54/* 768MHz configuration */
 55static const struct alpha_pll_config disp_cc_pll0_config = {
 56	.l = 0x28,
 57	.vco_val = 0x2 << 20,
 58	.vco_mask = 0x3 << 20,
 59	.main_output_mask = BIT(0),
 60	.config_ctl_val = 0x4001055b,
 61};
 62
 63static const struct parent_map disp_cc_parent_map_0[] = {
 64	{ P_BI_TCXO, 0 },
 65};
 66
 67static const struct clk_parent_data disp_cc_parent_data_0[] = {
 68	{ .fw_name = "bi_tcxo" },
 69};
 70
 71static const struct parent_map disp_cc_parent_map_1[] = {
 72	{ P_BI_TCXO, 0 },
 73	{ P_DP_PHY_PLL_LINK_CLK, 1 },
 74	{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
 75};
 76
 77static const struct clk_parent_data disp_cc_parent_data_1[] = {
 78	{ .fw_name = "bi_tcxo" },
 79	{ .fw_name = "dp_phy_pll_link_clk" },
 80	{ .fw_name = "dp_phy_pll_vco_div_clk" },
 81};
 82
 83static const struct parent_map disp_cc_parent_map_2[] = {
 84	{ P_BI_TCXO, 0 },
 85	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
 86};
 87
 88static const struct clk_parent_data disp_cc_parent_data_2[] = {
 89	{ .fw_name = "bi_tcxo" },
 90	{ .fw_name = "dsi0_phy_pll_out_byteclk" },
 91};
 92
 93static const struct parent_map disp_cc_parent_map_3[] = {
 94	{ P_BI_TCXO, 0 },
 95	{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
 96	{ P_GPLL0_OUT_MAIN, 4 },
 97};
 98
 99static const struct clk_parent_data disp_cc_parent_data_3[] = {
100	{ .fw_name = "bi_tcxo" },
101	{ .hw = &disp_cc_pll0.clkr.hw },
102	{ .fw_name = "gcc_disp_gpll0_div_clk_src" },
103};
104
105static const struct parent_map disp_cc_parent_map_4[] = {
106	{ P_BI_TCXO, 0 },
107	{ P_GPLL0_OUT_MAIN, 4 },
108};
109
110static const struct clk_parent_data disp_cc_parent_data_4[] = {
111	{ .fw_name = "bi_tcxo" },
112	{ .fw_name = "gcc_disp_gpll0_div_clk_src" },
113};
114
115static const struct parent_map disp_cc_parent_map_5[] = {
116	{ P_BI_TCXO, 0 },
117	{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
118	{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
119};
120
121static const struct clk_parent_data disp_cc_parent_data_5[] = {
122	{ .fw_name = "bi_tcxo" },
123	{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
124	{ .fw_name = "dsi1_phy_pll_out_dsiclk" },
125};
126
127static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
128	F(19200000, P_BI_TCXO, 1, 0, 0),
129	F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
130	F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
131	{ }
132};
133
134static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
135	.cmd_rcgr = 0x2154,
136	.mnd_width = 0,
137	.hid_width = 5,
138	.parent_map = disp_cc_parent_map_4,
139	.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
140	.clkr.hw.init = &(struct clk_init_data){
141		.name = "disp_cc_mdss_ahb_clk_src",
142		.parent_data = disp_cc_parent_data_4,
143		.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
144		.ops = &clk_rcg2_shared_ops,
145	},
146};
147
148static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
149	.cmd_rcgr = 0x20bc,
150	.mnd_width = 0,
151	.hid_width = 5,
152	.parent_map = disp_cc_parent_map_2,
153	.clkr.hw.init = &(struct clk_init_data){
154		.name = "disp_cc_mdss_byte0_clk_src",
155		.parent_data = disp_cc_parent_data_2,
156		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
157		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
158		.ops = &clk_byte2_ops,
159	},
160};
161
162static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux1_clk_src[] = {
163	F(19200000, P_BI_TCXO, 1, 0, 0),
164	{ }
165};
166
167static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
168	.cmd_rcgr = 0x213c,
169	.mnd_width = 0,
170	.hid_width = 5,
171	.parent_map = disp_cc_parent_map_0,
172	.freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
173	.clkr.hw.init = &(struct clk_init_data){
174		.name = "disp_cc_mdss_dp_aux_clk_src",
175		.parent_data = disp_cc_parent_data_0,
176		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
177		.ops = &clk_rcg2_ops,
178	},
179};
180
181static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = {
182	F( 180000, P_DP_PHY_PLL_LINK_CLK,   1.5,   0,   0),
183	F( 360000, P_DP_PHY_PLL_LINK_CLK,   1.5,   0,   0),
184	{ }
185};
186
187static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
188	.cmd_rcgr = 0x210c,
189	.mnd_width = 0,
190	.hid_width = 5,
191	.parent_map = disp_cc_parent_map_1,
192	.freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src,
193	.clkr.hw.init = &(struct clk_init_data){
194		.name = "disp_cc_mdss_dp_crypto_clk_src",
195		.parent_data = disp_cc_parent_data_1,
196		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
197		.flags = CLK_GET_RATE_NOCACHE,
198		.ops = &clk_rcg2_ops,
199	},
200};
201
202static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {
203	F( 162000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),
204	F( 270000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),
205	F( 540000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),
206	{ }
207};
208
209static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
210	.cmd_rcgr = 0x20f0,
211	.mnd_width = 0,
212	.hid_width = 5,
213	.parent_map = disp_cc_parent_map_1,
214	.freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src,
215	.clkr.hw.init = &(struct clk_init_data){
216		.name = "disp_cc_mdss_dp_link_clk_src",
217		.parent_data = disp_cc_parent_data_1,
218		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
219		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
220		.ops = &clk_rcg2_ops,
221	},
222};
223
224static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
225	.cmd_rcgr = 0x2124,
226	.mnd_width = 16,
227	.hid_width = 5,
228	.parent_map = disp_cc_parent_map_1,
229	.clkr.hw.init = &(struct clk_init_data){
230		.name = "disp_cc_mdss_dp_pixel_clk_src",
231		.parent_data = disp_cc_parent_data_1,
232		.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
233		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
234		.ops = &clk_dp_ops,
235	},
236};
237
238static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
239	.cmd_rcgr = 0x20d8,
240	.mnd_width = 0,
241	.hid_width = 5,
242	.parent_map = disp_cc_parent_map_2,
243	.freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
244	.clkr.hw.init = &(struct clk_init_data){
245		.name = "disp_cc_mdss_esc0_clk_src",
246		.parent_data = disp_cc_parent_data_2,
247		.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
248		.ops = &clk_rcg2_ops,
249	},
250};
251
252static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
253	F(19200000, P_BI_TCXO, 1, 0, 0),
254	F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
255	F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
256	F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
257	F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
258	F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
259	{ }
260};
261
262static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
263	.cmd_rcgr = 0x2074,
264	.mnd_width = 0,
265	.hid_width = 5,
266	.parent_map = disp_cc_parent_map_3,
267	.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
268	.clkr.hw.init = &(struct clk_init_data){
269		.name = "disp_cc_mdss_mdp_clk_src",
270		.parent_data = disp_cc_parent_data_3,
271		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
272		.ops = &clk_rcg2_shared_ops,
273	},
274};
275
276static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
277	.cmd_rcgr = 0x205c,
278	.mnd_width = 8,
279	.hid_width = 5,
280	.parent_map = disp_cc_parent_map_5,
281	.clkr.hw.init = &(struct clk_init_data){
282		.name = "disp_cc_mdss_pclk0_clk_src",
283		.parent_data = disp_cc_parent_data_5,
284		.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
285		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
286		.ops = &clk_pixel_ops,
287	},
288};
289
290static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
291	F(19200000, P_BI_TCXO, 1, 0, 0),
292	F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
293	F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
294	F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
295	{ }
296};
297
298static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
299	.cmd_rcgr = 0x208c,
300	.mnd_width = 0,
301	.hid_width = 5,
302	.parent_map = disp_cc_parent_map_3,
303	.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
304	.clkr.hw.init = &(struct clk_init_data){
305		.name = "disp_cc_mdss_rot_clk_src",
306		.parent_data = disp_cc_parent_data_3,
307		.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
308		.flags = CLK_SET_RATE_PARENT,
309		.ops = &clk_rcg2_shared_ops,
310	},
311};
312
313static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
314	.cmd_rcgr = 0x20a4,
315	.mnd_width = 0,
316	.hid_width = 5,
317	.parent_map = disp_cc_parent_map_0,
318	.freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src,
319	.clkr.hw.init = &(struct clk_init_data){
320		.name = "disp_cc_mdss_vsync_clk_src",
321		.parent_data = disp_cc_parent_data_0,
322		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
323		.ops = &clk_rcg2_ops,
324	},
325};
326
327static struct clk_branch disp_cc_mdss_ahb_clk = {
328	.halt_reg = 0x2044,
329	.halt_check = BRANCH_HALT,
330	.clkr = {
331		.enable_reg = 0x2044,
332		.enable_mask = BIT(0),
333		.hw.init = &(struct clk_init_data){
334			.name = "disp_cc_mdss_ahb_clk",
335			.parent_hws = (const struct clk_hw*[]){
336				&disp_cc_mdss_ahb_clk_src.clkr.hw,
337			},
338			.num_parents = 1,
339			.flags = CLK_SET_RATE_PARENT,
340			.ops = &clk_branch2_ops,
341		},
342	},
343};
344
345static struct clk_branch disp_cc_mdss_byte0_clk = {
346	.halt_reg = 0x2024,
347	.halt_check = BRANCH_HALT,
348	.clkr = {
349		.enable_reg = 0x2024,
350		.enable_mask = BIT(0),
351		.hw.init = &(struct clk_init_data){
352			.name = "disp_cc_mdss_byte0_clk",
353			.parent_hws = (const struct clk_hw*[]){
354				&disp_cc_mdss_byte0_clk_src.clkr.hw,
355			},
356			.num_parents = 1,
357			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
358			.ops = &clk_branch2_ops,
359		},
360	},
361};
362
363static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
364	.halt_reg = 0x2028,
365	.halt_check = BRANCH_HALT,
366	.clkr = {
367		.enable_reg = 0x2028,
368		.enable_mask = BIT(0),
369		.hw.init = &(struct clk_init_data){
370			.name = "disp_cc_mdss_byte0_intf_clk",
371			.parent_hws = (const struct clk_hw*[]){
372				&disp_cc_mdss_byte0_clk_src.clkr.hw,
373			},
374			.num_parents = 1,
375			.flags = CLK_GET_RATE_NOCACHE,
376			.ops = &clk_branch2_ops,
377		},
378	},
379};
380
381static struct clk_branch disp_cc_mdss_dp_aux_clk = {
382	.halt_reg = 0x2040,
383	.halt_check = BRANCH_HALT,
384	.clkr = {
385		.enable_reg = 0x2040,
386		.enable_mask = BIT(0),
387		.hw.init = &(struct clk_init_data){
388			.name = "disp_cc_mdss_dp_aux_clk",
389			.parent_hws = (const struct clk_hw*[]){
390				&disp_cc_mdss_dp_aux_clk_src.clkr.hw,
391			},
392			.num_parents = 1,
393			.flags = CLK_SET_RATE_PARENT,
394			.ops = &clk_branch2_ops,
395		},
396	},
397};
398
399static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
400	.halt_reg = 0x2038,
401	.halt_check = BRANCH_HALT,
402	.clkr = {
403		.enable_reg = 0x2038,
404		.enable_mask = BIT(0),
405		.hw.init = &(struct clk_init_data){
406			.name = "disp_cc_mdss_dp_crypto_clk",
407			.parent_hws = (const struct clk_hw*[]){
408				&disp_cc_mdss_dp_crypto_clk_src.clkr.hw,
409			},
410			.num_parents = 1,
411			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
412			.ops = &clk_branch2_ops,
413		},
414	},
415};
416
417static struct clk_branch disp_cc_mdss_dp_link_clk = {
418	.halt_reg = 0x2030,
419	.halt_check = BRANCH_HALT,
420	.clkr = {
421		.enable_reg = 0x2030,
422		.enable_mask = BIT(0),
423		.hw.init = &(struct clk_init_data){
424			.name = "disp_cc_mdss_dp_link_clk",
425			.parent_hws = (const struct clk_hw*[]){
426				&disp_cc_mdss_dp_link_clk_src.clkr.hw,
427			},
428			.num_parents = 1,
429			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
430			.ops = &clk_branch2_ops,
431		},
432	},
433};
434
435static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
436	.halt_reg = 0x2034,
437	.halt_check = BRANCH_HALT,
438	.clkr = {
439		.enable_reg = 0x2034,
440		.enable_mask = BIT(0),
441		.hw.init = &(struct clk_init_data){
442			.name = "disp_cc_mdss_dp_link_intf_clk",
443			.parent_hws = (const struct clk_hw*[]){
444				&disp_cc_mdss_dp_link_clk_src.clkr.hw,
445			},
446			.num_parents = 1,
447			.flags = CLK_GET_RATE_NOCACHE,
448			.ops = &clk_branch2_ops,
449		},
450	},
451};
452
453static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
454	.halt_reg = 0x203c,
455	.halt_check = BRANCH_HALT,
456	.clkr = {
457		.enable_reg = 0x203c,
458		.enable_mask = BIT(0),
459		.hw.init = &(struct clk_init_data){
460			.name = "disp_cc_mdss_dp_pixel_clk",
461			.parent_hws = (const struct clk_hw*[]){
462				&disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
463			},
464			.num_parents = 1,
465			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
466			.ops = &clk_branch2_ops,
467		},
468	},
469};
470
471static struct clk_branch disp_cc_mdss_esc0_clk = {
472	.halt_reg = 0x202c,
473	.halt_check = BRANCH_HALT,
474	.clkr = {
475		.enable_reg = 0x202c,
476		.enable_mask = BIT(0),
477		.hw.init = &(struct clk_init_data){
478			.name = "disp_cc_mdss_esc0_clk",
479			.parent_hws = (const struct clk_hw*[]){
480				&disp_cc_mdss_esc0_clk_src.clkr.hw,
481			},
482			.num_parents = 1,
483			.flags = CLK_SET_RATE_PARENT,
484			.ops = &clk_branch2_ops,
485		},
486	},
487};
488
489static struct clk_branch disp_cc_mdss_mdp_clk = {
490	.halt_reg = 0x2008,
491	.halt_check = BRANCH_HALT,
492	.clkr = {
493		.enable_reg = 0x2008,
494		.enable_mask = BIT(0),
495		.hw.init = &(struct clk_init_data){
496			.name = "disp_cc_mdss_mdp_clk",
497			.parent_hws = (const struct clk_hw*[]){
498				&disp_cc_mdss_mdp_clk_src.clkr.hw,
499			},
500			.num_parents = 1,
501			.flags = CLK_SET_RATE_PARENT,
502			.ops = &clk_branch2_ops,
503		},
504	},
505};
506
507static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
508	.halt_reg = 0x2018,
509	.halt_check = BRANCH_VOTED,
510	.clkr = {
511		.enable_reg = 0x2018,
512		.enable_mask = BIT(0),
513		.hw.init = &(struct clk_init_data){
514			.name = "disp_cc_mdss_mdp_lut_clk",
515			.parent_hws = (const struct clk_hw*[]){
516				&disp_cc_mdss_mdp_clk_src.clkr.hw,
517			},
518			.num_parents = 1,
519			.ops = &clk_branch2_ops,
520		},
521	},
522};
523
524static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
525	.halt_reg = 0x4004,
526	.halt_check = BRANCH_VOTED,
527	.clkr = {
528		.enable_reg = 0x4004,
529		.enable_mask = BIT(0),
530		.hw.init = &(struct clk_init_data){
531			.name = "disp_cc_mdss_non_gdsc_ahb_clk",
532			.parent_hws = (const struct clk_hw*[]){
533				&disp_cc_mdss_ahb_clk_src.clkr.hw,
534			},
535			.num_parents = 1,
536			.flags = CLK_SET_RATE_PARENT,
537			.ops = &clk_branch2_ops,
538		},
539	},
540};
541
542static struct clk_branch disp_cc_mdss_pclk0_clk = {
543	.halt_reg = 0x2004,
544	.halt_check = BRANCH_HALT,
545	.clkr = {
546		.enable_reg = 0x2004,
547		.enable_mask = BIT(0),
548		.hw.init = &(struct clk_init_data){
549			.name = "disp_cc_mdss_pclk0_clk",
550			.parent_hws = (const struct clk_hw*[]){
551				&disp_cc_mdss_pclk0_clk_src.clkr.hw,
552			},
553			.num_parents = 1,
554			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
555			.ops = &clk_branch2_ops,
556		},
557	},
558};
559
560static struct clk_branch disp_cc_mdss_rot_clk = {
561	.halt_reg = 0x2010,
562	.halt_check = BRANCH_HALT,
563	.clkr = {
564		.enable_reg = 0x2010,
565		.enable_mask = BIT(0),
566		.hw.init = &(struct clk_init_data){
567			.name = "disp_cc_mdss_rot_clk",
568			.parent_hws = (const struct clk_hw*[]){
569				&disp_cc_mdss_rot_clk_src.clkr.hw,
570			},
571			.num_parents = 1,
572			.flags = CLK_SET_RATE_PARENT,
573			.ops = &clk_branch2_ops,
574		},
575	},
576};
577
578static struct clk_branch disp_cc_mdss_vsync_clk = {
579	.halt_reg = 0x2020,
580	.halt_check = BRANCH_HALT,
581	.clkr = {
582		.enable_reg = 0x2020,
583		.enable_mask = BIT(0),
584		.hw.init = &(struct clk_init_data){
585			.name = "disp_cc_mdss_vsync_clk",
586			.parent_hws = (const struct clk_hw*[]){
587				&disp_cc_mdss_vsync_clk_src.clkr.hw,
588			},
589			.num_parents = 1,
590			.flags = CLK_SET_RATE_PARENT,
591			.ops = &clk_branch2_ops,
592		},
593	},
594};
595
596static struct clk_branch disp_cc_xo_clk = {
597	.halt_reg = 0x604c,
598	.halt_check = BRANCH_HALT,
599	.clkr = {
600		.enable_reg = 0x604c,
601		.enable_mask = BIT(0),
602		.hw.init = &(struct clk_init_data){
603			.name = "disp_cc_xo_clk",
604			.flags = CLK_IS_CRITICAL,
605			.ops = &clk_branch2_ops,
606		},
607	},
608};
609
610static struct gdsc mdss_gdsc = {
611	.gdscr = 0x3000,
612	.pd = {
613		.name = "mdss_gdsc",
614	},
615	.pwrsts = PWRSTS_OFF_ON,
616	.flags = HW_CTRL,
617};
618
619static struct clk_regmap *disp_cc_sm6125_clocks[] = {
620	[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
621	[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
622	[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
623	[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
624	[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
625	[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
626	[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
627	[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
628	[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr,
629	[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
630	[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
631	[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
632	[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
633	[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
634	[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
635	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
636	[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
637	[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
638	[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
639	[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
640	[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
641	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
642	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
643	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
644	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
645	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
646	[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
647	[DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr,
648};
649
650static struct gdsc *disp_cc_sm6125_gdscs[] = {
651	[MDSS_GDSC] = &mdss_gdsc,
652};
653
654static const struct regmap_config disp_cc_sm6125_regmap_config = {
655	.reg_bits = 32,
656	.reg_stride = 4,
657	.val_bits = 32,
658	.max_register = 0x10000,
659	.fast_io = true,
660};
661
662static const struct qcom_cc_desc disp_cc_sm6125_desc = {
663	.config = &disp_cc_sm6125_regmap_config,
664	.clks = disp_cc_sm6125_clocks,
665	.num_clks = ARRAY_SIZE(disp_cc_sm6125_clocks),
666	.gdscs = disp_cc_sm6125_gdscs,
667	.num_gdscs = ARRAY_SIZE(disp_cc_sm6125_gdscs),
668};
669
670static const struct of_device_id disp_cc_sm6125_match_table[] = {
671	{ .compatible = "qcom,sm6125-dispcc" },
672	{ }
673};
674MODULE_DEVICE_TABLE(of, disp_cc_sm6125_match_table);
675
676static int disp_cc_sm6125_probe(struct platform_device *pdev)
677{
678	struct regmap *regmap;
679
680	regmap = qcom_cc_map(pdev, &disp_cc_sm6125_desc);
681	if (IS_ERR(regmap))
682		return PTR_ERR(regmap);
683
684	clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
685
686	return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6125_desc, regmap);
687}
688
689static struct platform_driver disp_cc_sm6125_driver = {
690	.probe = disp_cc_sm6125_probe,
691	.driver = {
692		.name = "disp_cc-sm6125",
693		.of_match_table = disp_cc_sm6125_match_table,
694	},
695};
696
697module_platform_driver(disp_cc_sm6125_driver);
698
699MODULE_DESCRIPTION("QTI DISPCC SM6125 Driver");
700MODULE_LICENSE("GPL v2");