clk-spmi-pmic-div.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
  3 */
  4
  5#include <linux/bitops.h>
  6#include <linux/cleanup.h>
  7#include <linux/clk.h>
  8#include <linux/clk-provider.h>
  9#include <linux/delay.h>
 10#include <linux/err.h>
 11#include <linux/log2.h>
 12#include <linux/module.h>
 13#include <linux/of.h>
 14#include <linux/platform_device.h>
 15#include <linux/regmap.h>
 16#include <linux/slab.h>
 17#include <linux/types.h>
 18
 19#define REG_DIV_CTL1			0x43
 20#define DIV_CTL1_DIV_FACTOR_MASK	GENMASK(2, 0)
 21
 22#define REG_EN_CTL			0x46
 23#define REG_EN_MASK			BIT(7)
 24
 25struct clkdiv {
 26	struct regmap		*regmap;
 27	u16			base;
 28	spinlock_t		lock;
 29
 30	struct clk_hw		hw;
 31	unsigned int		cxo_period_ns;
 32};
 33
 34static inline struct clkdiv *to_clkdiv(struct clk_hw *hw)
 35{
 36	return container_of(hw, struct clkdiv, hw);
 37}
 38
 39static inline unsigned int div_factor_to_div(unsigned int div_factor)
 40{
 41	if (!div_factor)
 42		div_factor = 1;
 43
 44	return 1 << (div_factor - 1);
 45}
 46
 47static inline unsigned int div_to_div_factor(unsigned int div)
 48{
 49	return min(ilog2(div) + 1, 7);
 50}
 51
 52static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv)
 53{
 54	unsigned int val = 0;
 55
 56	regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val);
 57
 58	return val & REG_EN_MASK;
 59}
 60
 61static int
 62__spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable,
 63				    unsigned int div_factor)
 64{
 65	int ret;
 66	unsigned int ns = clkdiv->cxo_period_ns;
 67	unsigned int div = div_factor_to_div(div_factor);
 68
 69	ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL,
 70				 REG_EN_MASK, enable ? REG_EN_MASK : 0);
 71	if (ret)
 72		return ret;
 73
 74	if (enable)
 75		ndelay((2 + 3 * div) * ns);
 76	else
 77		ndelay(3 * div * ns);
 78
 79	return 0;
 80}
 81
 82static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable)
 83{
 84	unsigned int div_factor;
 85
 86	regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
 87	div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
 88
 89	return __spmi_pmic_clkdiv_set_enable_state(clkdiv, enable, div_factor);
 90}
 91
 92static int clk_spmi_pmic_div_enable(struct clk_hw *hw)
 93{
 94	struct clkdiv *clkdiv = to_clkdiv(hw);
 95	unsigned long flags;
 96	int ret;
 97
 98	spin_lock_irqsave(&clkdiv->lock, flags);
 99	ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, true);
100	spin_unlock_irqrestore(&clkdiv->lock, flags);
101
102	return ret;
103}
104
105static void clk_spmi_pmic_div_disable(struct clk_hw *hw)
106{
107	struct clkdiv *clkdiv = to_clkdiv(hw);
108	unsigned long flags;
109
110	spin_lock_irqsave(&clkdiv->lock, flags);
111	spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
112	spin_unlock_irqrestore(&clkdiv->lock, flags);
113}
114
115static int clk_spmi_pmic_div_determine_rate(struct clk_hw *hw,
116					    struct clk_rate_request *req)
117{
118	unsigned int div, div_factor;
119
120	div = DIV_ROUND_UP(req->best_parent_rate, req->rate);
121	div_factor = div_to_div_factor(div);
122	div = div_factor_to_div(div_factor);
123
124	req->rate = req->best_parent_rate / div;
125
126	return 0;
127}
128
129static unsigned long
130clk_spmi_pmic_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
131{
132	struct clkdiv *clkdiv = to_clkdiv(hw);
133	unsigned int div_factor;
134
135	regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
136	div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
137
138	return parent_rate / div_factor_to_div(div_factor);
139}
140
141static int clk_spmi_pmic_div_set_rate(struct clk_hw *hw, unsigned long rate,
142				      unsigned long parent_rate)
143{
144	struct clkdiv *clkdiv = to_clkdiv(hw);
145	unsigned int div_factor = div_to_div_factor(parent_rate / rate);
146	bool enabled;
147	int ret;
148
149	guard(spinlock_irqsave)(&clkdiv->lock);
150
151	enabled = is_spmi_pmic_clkdiv_enabled(clkdiv);
152	if (enabled) {
153		ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
154		if (ret)
155			return ret;
156	}
157
158	ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1,
159				 DIV_CTL1_DIV_FACTOR_MASK, div_factor);
160	if (ret)
161		return ret;
162
163	if (enabled)
164		ret = __spmi_pmic_clkdiv_set_enable_state(clkdiv, true,
165							  div_factor);
166	return ret;
167}
168
169static const struct clk_ops clk_spmi_pmic_div_ops = {
170	.enable = clk_spmi_pmic_div_enable,
171	.disable = clk_spmi_pmic_div_disable,
172	.set_rate = clk_spmi_pmic_div_set_rate,
173	.recalc_rate = clk_spmi_pmic_div_recalc_rate,
174	.determine_rate = clk_spmi_pmic_div_determine_rate,
175};
176
177struct spmi_pmic_div_clk_cc {
178	int		nclks;
179	struct clkdiv	clks[] __counted_by(nclks);
180};
181
182static struct clk_hw *
183spmi_pmic_div_clk_hw_get(struct of_phandle_args *clkspec, void *data)
184{
185	struct spmi_pmic_div_clk_cc *cc = data;
186	int idx = clkspec->args[0] - 1; /* Start at 1 instead of 0 */
187
188	if (idx < 0 || idx >= cc->nclks) {
189		pr_err("%s: index value %u is invalid; allowed range [1, %d]\n",
190		       __func__, clkspec->args[0], cc->nclks);
191		return ERR_PTR(-EINVAL);
192	}
193
194	return &cc->clks[idx].hw;
195}
196
197static int spmi_pmic_clkdiv_probe(struct platform_device *pdev)
198{
199	struct spmi_pmic_div_clk_cc *cc;
200	struct clk_init_data init = {};
201	struct clkdiv *clkdiv;
202	struct clk *cxo;
203	struct regmap *regmap;
204	struct device *dev = &pdev->dev;
205	struct device_node *of_node = dev->of_node;
206	struct clk_parent_data parent_data = { .index = 0, };
207	int nclks, i, ret, cxo_hz;
208	char name[20];
209	u32 start;
210
211	ret = of_property_read_u32(of_node, "reg", &start);
212	if (ret < 0) {
213		dev_err(dev, "reg property reading failed\n");
214		return ret;
215	}
216
217	regmap = dev_get_regmap(dev->parent, NULL);
218	if (!regmap) {
219		dev_err(dev, "Couldn't get parent's regmap\n");
220		return -EINVAL;
221	}
222
223	ret = of_property_read_u32(of_node, "qcom,num-clkdivs", &nclks);
224	if (ret < 0) {
225		dev_err(dev, "qcom,num-clkdivs property reading failed, ret=%d\n",
226			ret);
227		return ret;
228	}
229
230	if (!nclks)
231		return -EINVAL;
232
233	cc = devm_kzalloc(dev, struct_size(cc, clks, nclks), GFP_KERNEL);
234	if (!cc)
235		return -ENOMEM;
236	cc->nclks = nclks;
237
238	cxo = clk_get(dev, "xo");
239	if (IS_ERR(cxo)) {
240		ret = PTR_ERR(cxo);
241		if (ret != -EPROBE_DEFER)
242			dev_err(dev, "failed to get xo clock\n");
243		return ret;
244	}
245	cxo_hz = clk_get_rate(cxo);
246	clk_put(cxo);
247
248	init.name = name;
249	init.parent_data = &parent_data;
250	init.num_parents = 1;
251	init.ops = &clk_spmi_pmic_div_ops;
252
253	for (i = 0, clkdiv = cc->clks; i < nclks; i++) {
254		snprintf(name, sizeof(name), "div_clk%d", i + 1);
255
256		spin_lock_init(&clkdiv[i].lock);
257		clkdiv[i].base = start + i * 0x100;
258		clkdiv[i].regmap = regmap;
259		clkdiv[i].cxo_period_ns = NSEC_PER_SEC / cxo_hz;
260		clkdiv[i].hw.init = &init;
261
262		ret = devm_clk_hw_register(dev, &clkdiv[i].hw);
263		if (ret)
264			return ret;
265	}
266
267	return devm_of_clk_add_hw_provider(dev, spmi_pmic_div_clk_hw_get, cc);
268}
269
270static const struct of_device_id spmi_pmic_clkdiv_match_table[] = {
271	{ .compatible = "qcom,spmi-clkdiv" },
272	{ /* sentinel */ }
273};
274MODULE_DEVICE_TABLE(of, spmi_pmic_clkdiv_match_table);
275
276static struct platform_driver spmi_pmic_clkdiv_driver = {
277	.driver		= {
278		.name	= "qcom,spmi-pmic-clkdiv",
279		.of_match_table = spmi_pmic_clkdiv_match_table,
280	},
281	.probe		= spmi_pmic_clkdiv_probe,
282};
283module_platform_driver(spmi_pmic_clkdiv_driver);
284
285MODULE_DESCRIPTION("QCOM SPMI PMIC clkdiv driver");
286MODULE_LICENSE("GPL v2");