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clk-smd-rpm.c
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linux-6.19.14/drivers/clk/qcom/clk-smd-rpm.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 5 */ 6 7#include <linux/cleanup.h> 8#include <linux/clk-provider.h> 9#include <linux/err.h> 10#include <linux/export.h> 11#include <linux/init.h> 12#include <linux/kernel.h> 13#include <linux/module.h> 14#include <linux/mutex.h> 15#include <linux/of.h> 16#include <linux/platform_device.h> 17#include <linux/soc/qcom/smd-rpm.h> 18 19#include <dt-bindings/clock/qcom,rpmcc.h> 20 21#define __DEFINE_CLK_SMD_RPM_PREFIX(_prefix, _name, _active, \ 22 type, r_id, key, ao_rate, ao_flags) \ 23 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ 24 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \ 25 .rpm_res_type = (type), \ 26 .rpm_clk_id = (r_id), \ 27 .rpm_key = (key), \ 28 .peer = &clk_smd_rpm_##_prefix##_active, \ 29 .rate = INT_MAX, \ 30 .hw.init = &(struct clk_init_data){ \ 31 .ops = &clk_smd_rpm_ops, \ 32 .name = #_name, \ 33 .parent_data = &(const struct clk_parent_data){ \ 34 .fw_name = "xo", \ 35 .name = "xo_board", \ 36 }, \ 37 .num_parents = 1, \ 38 }, \ 39 }; \ 40 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \ 41 .rpm_res_type = (type), \ 42 .rpm_clk_id = (r_id), \ 43 .active_only = true, \ 44 .rpm_key = (key), \ 45 .peer = &clk_smd_rpm_##_prefix##_name, \ 46 .rate = (ao_rate), \ 47 .hw.init = &(struct clk_init_data){ \ 48 .ops = &clk_smd_rpm_ops, \ 49 .name = #_active, \ 50 .parent_data = &(const struct clk_parent_data){ \ 51 .fw_name = "xo", \ 52 .name = "xo_board", \ 53 }, \ 54 .num_parents = 1, \ 55 .flags = (ao_flags), \ 56 }, \ 57 } 58 59#define __DEFINE_CLK_SMD_RPM(_name, _active, type, r_id, key,\ 60 ao_rate, ao_flags) \ 61 __DEFINE_CLK_SMD_RPM_PREFIX(/* empty */, _name, _active, \ 62 type, r_id, key, ao_rate, ao_flags) 63 64#define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, _name, _active,\ 65 type, r_id, r, key, ao_flags) \ 66 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ 67 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \ 68 .rpm_res_type = (type), \ 69 .rpm_clk_id = (r_id), \ 70 .rpm_key = (key), \ 71 .branch = true, \ 72 .peer = &clk_smd_rpm_##_prefix##_active, \ 73 .rate = (r), \ 74 .hw.init = &(struct clk_init_data){ \ 75 .ops = &clk_smd_rpm_branch_ops, \ 76 .name = #_name, \ 77 .parent_data = &(const struct clk_parent_data){ \ 78 .fw_name = "xo", \ 79 .name = "xo_board", \ 80 }, \ 81 .num_parents = 1, \ 82 }, \ 83 }; \ 84 static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \ 85 .rpm_res_type = (type), \ 86 .rpm_clk_id = (r_id), \ 87 .active_only = true, \ 88 .rpm_key = (key), \ 89 .branch = true, \ 90 .peer = &clk_smd_rpm_##_prefix##_name, \ 91 .rate = (r), \ 92 .hw.init = &(struct clk_init_data){ \ 93 .ops = &clk_smd_rpm_branch_ops, \ 94 .name = #_active, \ 95 .parent_data = &(const struct clk_parent_data){ \ 96 .fw_name = "xo", \ 97 .name = "xo_board", \ 98 }, \ 99 .num_parents = 1, \ 100 .flags = (ao_flags), \ 101 }, \ 102 } 103 104#define __DEFINE_CLK_SMD_RPM_BRANCH(_name, _active, type, r_id, r, key) \ 105 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(/* empty */, \ 106 _name, _active, type, r_id, r, key, 0) 107 108#define DEFINE_CLK_SMD_RPM(_name, type, r_id) \ 109 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ 110 type, r_id, QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0) 111 112#define DEFINE_CLK_SMD_RPM_BUS(_name, r_id) \ 113 __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \ 114 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \ 115 QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0) 116 117#define DEFINE_CLK_SMD_RPM_BUS_A(_name, r_id, ao_rate, ao_flags) \ 118 __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \ 119 _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \ 120 QCOM_RPM_SMD_KEY_RATE, ao_rate, ao_flags) 121 122#define DEFINE_CLK_SMD_RPM_CLK_SRC(_name, type, r_id) \ 123 __DEFINE_CLK_SMD_RPM( \ 124 _name##_clk_src, _name##_a_clk_src, \ 125 type, r_id, QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0) 126 127#define DEFINE_CLK_SMD_RPM_BRANCH(_name, type, r_id, r) \ 128 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ 129 _name##_clk, _name##_a_clk, \ 130 type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE, 0) 131 132#define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r, ao_flags) \ 133 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ 134 _name, _name##_a, type, \ 135 r_id, r, QCOM_RPM_SMD_KEY_ENABLE, ao_flags) 136 137#define DEFINE_CLK_SMD_RPM_QDSS(_name, type, r_id) \ 138 __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ 139 type, r_id, QCOM_RPM_SMD_KEY_STATE, INT_MAX, 0) 140 141#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r) \ 142 __DEFINE_CLK_SMD_RPM_BRANCH(_name, _name##_a, \ 143 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ 144 QCOM_RPM_KEY_SOFTWARE_ENABLE) 145 146#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(_prefix, _name, r_id, r) \ 147 __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, \ 148 _name, _name##_a, \ 149 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ 150 QCOM_RPM_KEY_SOFTWARE_ENABLE, 0) 151 152#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_name, r_id, r) \ 153 DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r); \ 154 __DEFINE_CLK_SMD_RPM_BRANCH(_name##_pin, _name##_a##_pin, \ 155 QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ 156 QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY) 157 158#define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw) 159 160static struct qcom_smd_rpm *rpmcc_smd_rpm; 161 162struct clk_smd_rpm { 163 const int rpm_res_type; 164 const int rpm_key; 165 const int rpm_clk_id; 166 const bool active_only; 167 bool enabled; 168 bool branch; 169 struct clk_smd_rpm *peer; 170 struct clk_hw hw; 171 unsigned long rate; 172}; 173 174struct rpm_smd_clk_desc { 175 struct clk_smd_rpm **clks; 176 size_t num_clks; 177 178 /* 179 * Interconnect clocks are managed by the icc framework, this driver 180 * only kickstarts them so that they don't get gated between 181 * clk_smd_rpm_enable_scaling() and interconnect driver initialization. 182 */ 183 const struct clk_smd_rpm ** const icc_clks; 184 size_t num_icc_clks; 185 bool scaling_before_handover; 186}; 187 188static DEFINE_MUTEX(rpm_smd_clk_lock); 189 190static int clk_smd_rpm_handoff(const struct clk_smd_rpm *r) 191{ 192 int ret; 193 struct clk_smd_rpm_req req = { 194 .key = cpu_to_le32(r->rpm_key), 195 .nbytes = cpu_to_le32(sizeof(u32)), 196 .value = cpu_to_le32(r->branch ? 1 : INT_MAX), 197 }; 198 199 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, 200 r->rpm_res_type, r->rpm_clk_id, &req, 201 sizeof(req)); 202 if (ret) 203 return ret; 204 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, 205 r->rpm_res_type, r->rpm_clk_id, &req, 206 sizeof(req)); 207 if (ret) 208 return ret; 209 210 return 0; 211} 212 213static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r, 214 unsigned long rate) 215{ 216 struct clk_smd_rpm_req req = { 217 .key = cpu_to_le32(r->rpm_key), 218 .nbytes = cpu_to_le32(sizeof(u32)), 219 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ 220 }; 221 222 return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, 223 r->rpm_res_type, r->rpm_clk_id, &req, 224 sizeof(req)); 225} 226 227static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r, 228 unsigned long rate) 229{ 230 struct clk_smd_rpm_req req = { 231 .key = cpu_to_le32(r->rpm_key), 232 .nbytes = cpu_to_le32(sizeof(u32)), 233 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ 234 }; 235 236 return qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, 237 r->rpm_res_type, r->rpm_clk_id, &req, 238 sizeof(req)); 239} 240 241static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate, 242 unsigned long *active, unsigned long *sleep) 243{ 244 *active = rate; 245 246 /* 247 * Active-only clocks don't care what the rate is during sleep. So, 248 * they vote for zero. 249 */ 250 if (r->active_only) 251 *sleep = 0; 252 else 253 *sleep = *active; 254} 255 256static int clk_smd_rpm_prepare(struct clk_hw *hw) 257{ 258 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 259 struct clk_smd_rpm *peer = r->peer; 260 unsigned long this_rate = 0, this_sleep_rate = 0; 261 unsigned long peer_rate = 0, peer_sleep_rate = 0; 262 unsigned long active_rate, sleep_rate; 263 int ret = 0; 264 265 mutex_lock(&rpm_smd_clk_lock); 266 267 /* Don't send requests to the RPM if the rate has not been set. */ 268 if (!r->rate) 269 goto out; 270 271 to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate); 272 273 /* Take peer clock's rate into account only if it's enabled. */ 274 if (peer->enabled) 275 to_active_sleep(peer, peer->rate, 276 &peer_rate, &peer_sleep_rate); 277 278 active_rate = max(this_rate, peer_rate); 279 280 if (r->branch) 281 active_rate = !!active_rate; 282 283 ret = clk_smd_rpm_set_rate_active(r, active_rate); 284 if (ret) 285 goto out; 286 287 sleep_rate = max(this_sleep_rate, peer_sleep_rate); 288 if (r->branch) 289 sleep_rate = !!sleep_rate; 290 291 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 292 if (ret) 293 /* Undo the active set vote and restore it */ 294 ret = clk_smd_rpm_set_rate_active(r, peer_rate); 295 296out: 297 if (!ret) 298 r->enabled = true; 299 300 mutex_unlock(&rpm_smd_clk_lock); 301 302 return ret; 303} 304 305static void clk_smd_rpm_unprepare(struct clk_hw *hw) 306{ 307 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 308 struct clk_smd_rpm *peer = r->peer; 309 unsigned long peer_rate = 0, peer_sleep_rate = 0; 310 unsigned long active_rate, sleep_rate; 311 int ret; 312 313 guard(mutex)(&rpm_smd_clk_lock); 314 315 if (!r->rate) 316 return; 317 318 /* Take peer clock's rate into account only if it's enabled. */ 319 if (peer->enabled) 320 to_active_sleep(peer, peer->rate, &peer_rate, 321 &peer_sleep_rate); 322 323 active_rate = r->branch ? !!peer_rate : peer_rate; 324 ret = clk_smd_rpm_set_rate_active(r, active_rate); 325 if (ret) 326 return; 327 328 sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate; 329 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 330 if (ret) 331 return; 332 333 r->enabled = false; 334} 335 336static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate, 337 unsigned long parent_rate) 338{ 339 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 340 struct clk_smd_rpm *peer = r->peer; 341 unsigned long active_rate, sleep_rate; 342 unsigned long this_rate = 0, this_sleep_rate = 0; 343 unsigned long peer_rate = 0, peer_sleep_rate = 0; 344 int ret = 0; 345 346 guard(mutex)(&rpm_smd_clk_lock); 347 348 if (!r->enabled) 349 return 0; 350 351 to_active_sleep(r, rate, &this_rate, &this_sleep_rate); 352 353 /* Take peer clock's rate into account only if it's enabled. */ 354 if (peer->enabled) 355 to_active_sleep(peer, peer->rate, 356 &peer_rate, &peer_sleep_rate); 357 358 active_rate = max(this_rate, peer_rate); 359 ret = clk_smd_rpm_set_rate_active(r, active_rate); 360 if (ret) 361 return ret; 362 363 sleep_rate = max(this_sleep_rate, peer_sleep_rate); 364 ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate); 365 if (ret) 366 return ret; 367 368 r->rate = rate; 369 370 return 0; 371} 372 373static int clk_smd_rpm_determine_rate(struct clk_hw *hw, 374 struct clk_rate_request *req) 375{ 376 /* 377 * RPM handles rate rounding and we don't have a way to 378 * know what the rate will be, so just return whatever 379 * rate is requested. 380 */ 381 return 0; 382} 383 384static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw, 385 unsigned long parent_rate) 386{ 387 struct clk_smd_rpm *r = to_clk_smd_rpm(hw); 388 389 /* 390 * RPM handles rate rounding and we don't have a way to 391 * know what the rate will be, so just return whatever 392 * rate was set. 393 */ 394 return r->rate; 395} 396 397static int clk_smd_rpm_enable_scaling(void) 398{ 399 int ret; 400 struct clk_smd_rpm_req req = { 401 .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE), 402 .nbytes = cpu_to_le32(sizeof(u32)), 403 .value = cpu_to_le32(1), 404 }; 405 406 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, 407 QCOM_SMD_RPM_MISC_CLK, 408 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); 409 if (ret) { 410 pr_err("RPM clock scaling (sleep set) not enabled!\n"); 411 return ret; 412 } 413 414 ret = qcom_rpm_smd_write(rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, 415 QCOM_SMD_RPM_MISC_CLK, 416 QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); 417 if (ret) { 418 pr_err("RPM clock scaling (active set) not enabled!\n"); 419 return ret; 420 } 421 422 pr_debug("%s: RPM clock scaling is enabled\n", __func__); 423 return 0; 424} 425 426static const struct clk_ops clk_smd_rpm_ops = { 427 .prepare = clk_smd_rpm_prepare, 428 .unprepare = clk_smd_rpm_unprepare, 429 .set_rate = clk_smd_rpm_set_rate, 430 .determine_rate = clk_smd_rpm_determine_rate, 431 .recalc_rate = clk_smd_rpm_recalc_rate, 432}; 433 434static const struct clk_ops clk_smd_rpm_branch_ops = { 435 .prepare = clk_smd_rpm_prepare, 436 .unprepare = clk_smd_rpm_unprepare, 437 .recalc_rate = clk_smd_rpm_recalc_rate, 438}; 439 440/* Disabling BI_TCXO_AO could gate the root clock source of the entire system. */ 441DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000, CLK_IS_CRITICAL); 442DEFINE_CLK_SMD_RPM_BRANCH(qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000); 443DEFINE_CLK_SMD_RPM_QDSS(qdss, QCOM_SMD_RPM_MISC_CLK, 1); 444DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1, 0); 445 446DEFINE_CLK_SMD_RPM_BRANCH(mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); 447 448DEFINE_CLK_SMD_RPM_BRANCH(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1, 1000); 449DEFINE_CLK_SMD_RPM_BRANCH(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); 450DEFINE_CLK_SMD_RPM(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); 451DEFINE_CLK_SMD_RPM(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); 452 453DEFINE_CLK_SMD_RPM_BUS_A(pcnoc, 0, 19200000, CLK_IS_CRITICAL); 454DEFINE_CLK_SMD_RPM_BUS(snoc, 1); 455DEFINE_CLK_SMD_RPM_BUS(sysmmnoc, 2); 456DEFINE_CLK_SMD_RPM_BUS(cnoc, 2); 457DEFINE_CLK_SMD_RPM_BUS(mmssnoc_ahb, 3); 458DEFINE_CLK_SMD_RPM_BUS(snoc_periph, 0); 459DEFINE_CLK_SMD_RPM_BUS(cnoc, 1); 460DEFINE_CLK_SMD_RPM_BUS(snoc, 2); 461DEFINE_CLK_SMD_RPM_BUS(snoc_lpass, 5); 462 463DEFINE_CLK_SMD_RPM(bimc, QCOM_SMD_RPM_MEM_CLK, 0); 464DEFINE_CLK_SMD_RPM(cpuss_gnoc, QCOM_SMD_RPM_MEM_CLK, 1); 465DEFINE_CLK_SMD_RPM_CLK_SRC(gfx3d, QCOM_SMD_RPM_MEM_CLK, 1); 466DEFINE_CLK_SMD_RPM(ocmemgx, QCOM_SMD_RPM_MEM_CLK, 2); 467DEFINE_CLK_SMD_RPM(bimc_gpu, QCOM_SMD_RPM_MEM_CLK, 2); 468 469DEFINE_CLK_SMD_RPM(ce1, QCOM_SMD_RPM_CE_CLK, 0); 470DEFINE_CLK_SMD_RPM(ce2, QCOM_SMD_RPM_CE_CLK, 1); 471DEFINE_CLK_SMD_RPM(ce3, QCOM_SMD_RPM_CE_CLK, 2); 472 473DEFINE_CLK_SMD_RPM(ipa, QCOM_SMD_RPM_IPA_CLK, 0); 474 475DEFINE_CLK_SMD_RPM(hwkm, QCOM_SMD_RPM_HWKM_CLK, 0); 476 477DEFINE_CLK_SMD_RPM(mmssnoc_axi_rpm, QCOM_SMD_RPM_MMAXI_CLK, 0); 478DEFINE_CLK_SMD_RPM(mmnrt, QCOM_SMD_RPM_MMAXI_CLK, 0); 479DEFINE_CLK_SMD_RPM(mmrt, QCOM_SMD_RPM_MMAXI_CLK, 1); 480 481DEFINE_CLK_SMD_RPM(pka, QCOM_SMD_RPM_PKA_CLK, 0); 482 483DEFINE_CLK_SMD_RPM(qpic, QCOM_SMD_RPM_QPIC_CLK, 0); 484 485DEFINE_CLK_SMD_RPM(qup, QCOM_SMD_RPM_QUP_CLK, 0); 486 487DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk1, 1, 19200000); 488DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk2, 2, 19200000); 489DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk3, 3, 19200000); 490DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk1, 1, 19200000); 491DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk2, 2, 19200000); 492DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk3, 3, 19200000); 493DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk1, 4, 19200000); 494DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk2, 5, 19200000); 495DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk3, 6, 19200000); 496DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk, 8, 19200000); 497 498DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(38m4_, rf_clk3, 6, 38400000); 499 500DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d0, 1, 19200000); 501DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d1, 2, 19200000); 502DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a0, 4, 19200000); 503DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a1, 5, 19200000); 504DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a2, 6, 19200000); 505 506DEFINE_CLK_SMD_RPM_XO_BUFFER(diff_clk, 7, 19200000); 507DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000); 508DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000); 509DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000); 510 511static const struct clk_smd_rpm *bimc_pcnoc_icc_clks[] = { 512 &clk_smd_rpm_bimc_clk, 513 &clk_smd_rpm_bus_0_pcnoc_clk, 514}; 515 516static const struct clk_smd_rpm *bimc_pcnoc_snoc_icc_clks[] = { 517 &clk_smd_rpm_bimc_clk, 518 &clk_smd_rpm_bus_0_pcnoc_clk, 519 &clk_smd_rpm_bus_1_snoc_clk, 520}; 521 522static const struct clk_smd_rpm *bimc_pcnoc_snoc_smmnoc_icc_clks[] = { 523 &clk_smd_rpm_bimc_clk, 524 &clk_smd_rpm_bus_0_pcnoc_clk, 525 &clk_smd_rpm_bus_1_snoc_clk, 526 &clk_smd_rpm_bus_2_sysmmnoc_clk, 527}; 528 529static const struct clk_smd_rpm *bimc_pcnoc_snoc_cnoc_ocmem_icc_clks[] = { 530 &clk_smd_rpm_bimc_clk, 531 &clk_smd_rpm_bus_0_pcnoc_clk, 532 &clk_smd_rpm_bus_1_snoc_clk, 533 &clk_smd_rpm_bus_2_cnoc_clk, 534 &clk_smd_rpm_ocmemgx_clk, 535}; 536 537static const struct clk_smd_rpm *msm8996_icc_clks[] = { 538 &clk_smd_rpm_bimc_clk, 539 &clk_smd_rpm_branch_aggre1_noc_clk, 540 &clk_smd_rpm_branch_aggre2_noc_clk, 541 &clk_smd_rpm_bus_0_pcnoc_clk, 542 &clk_smd_rpm_bus_1_snoc_clk, 543 &clk_smd_rpm_bus_2_cnoc_clk, 544 &clk_smd_rpm_mmssnoc_axi_rpm_clk, 545}; 546 547static const struct clk_smd_rpm *msm8998_icc_clks[] = { 548 &clk_smd_rpm_aggre1_noc_clk, 549 &clk_smd_rpm_aggre2_noc_clk, 550 &clk_smd_rpm_bimc_clk, 551 &clk_smd_rpm_bus_1_snoc_clk, 552 &clk_smd_rpm_bus_2_cnoc_clk, 553 &clk_smd_rpm_mmssnoc_axi_rpm_clk, 554}; 555 556static const struct clk_smd_rpm *sdm660_icc_clks[] = { 557 &clk_smd_rpm_aggre2_noc_clk, 558 &clk_smd_rpm_bimc_clk, 559 &clk_smd_rpm_bus_1_snoc_clk, 560 &clk_smd_rpm_bus_2_cnoc_clk, 561 &clk_smd_rpm_mmssnoc_axi_rpm_clk, 562}; 563 564static const struct clk_smd_rpm *sm_qnoc_icc_clks[] = { 565 &clk_smd_rpm_bimc_clk, 566 &clk_smd_rpm_bus_1_cnoc_clk, 567 &clk_smd_rpm_mmnrt_clk, 568 &clk_smd_rpm_mmrt_clk, 569 &clk_smd_rpm_qup_clk, 570 &clk_smd_rpm_bus_2_snoc_clk, 571}; 572 573static const struct clk_smd_rpm *qcm2290_icc_clks[] = { 574 &clk_smd_rpm_bimc_clk, 575 &clk_smd_rpm_bus_1_cnoc_clk, 576 &clk_smd_rpm_mmnrt_clk, 577 &clk_smd_rpm_mmrt_clk, 578 &clk_smd_rpm_qup_clk, 579 &clk_smd_rpm_bus_2_snoc_clk, 580 &clk_smd_rpm_cpuss_gnoc_clk, 581}; 582 583static struct clk_smd_rpm *msm8909_clks[] = { 584 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 585 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 586 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 587 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 588 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 589 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 590 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 591 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 592 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 593 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 594 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 595 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 596 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 597 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 598 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 599 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 600 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 601 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 602 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 603 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 604}; 605 606static const struct rpm_smd_clk_desc rpm_clk_msm8909 = { 607 .clks = msm8909_clks, 608 .num_clks = ARRAY_SIZE(msm8909_clks), 609 .icc_clks = bimc_pcnoc_snoc_icc_clks, 610 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks), 611}; 612 613static struct clk_smd_rpm *msm8916_clks[] = { 614 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 615 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 616 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 617 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 618 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 619 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 620 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 621 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 622 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 623 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 624 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 625 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 626 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 627 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 628 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 629 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 630 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 631 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 632}; 633 634static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { 635 .clks = msm8916_clks, 636 .num_clks = ARRAY_SIZE(msm8916_clks), 637 .icc_clks = bimc_pcnoc_snoc_icc_clks, 638 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks), 639}; 640 641static struct clk_smd_rpm *msm8917_clks[] = { 642 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 643 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 644 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, 645 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, 646 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 647 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 648 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 649 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 650 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 651 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 652 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 653 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 654 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 655 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 656 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 657 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 658 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 659 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 660}; 661 662static const struct rpm_smd_clk_desc rpm_clk_msm8917 = { 663 .clks = msm8917_clks, 664 .num_clks = ARRAY_SIZE(msm8917_clks), 665 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, 666 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), 667}; 668 669static struct clk_smd_rpm *msm8936_clks[] = { 670 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 671 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 672 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 673 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 674 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 675 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 676 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 677 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 678 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 679 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 680 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 681 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 682 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 683 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 684 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 685 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 686 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 687 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 688 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 689 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 690}; 691 692static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { 693 .clks = msm8936_clks, 694 .num_clks = ARRAY_SIZE(msm8936_clks), 695 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, 696 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), 697}; 698 699static struct clk_smd_rpm *msm8937_clks[] = { 700 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 701 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 702 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 703 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 704 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 705 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 706 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 707 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 708 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 709 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 710 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 711 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 712 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 713 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 714 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 715 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 716}; 717 718static const struct rpm_smd_clk_desc rpm_clk_msm8937 = { 719 .clks = msm8937_clks, 720 .num_clks = ARRAY_SIZE(msm8937_clks), 721 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, 722 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), 723}; 724 725static struct clk_smd_rpm *msm8940_clks[] = { 726 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 727 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 728 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 729 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 730 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 731 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 732 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 733 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 734 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 735 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 736 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 737 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 738 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 739 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 740 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 741 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 742 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 743 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 744}; 745 746static const struct rpm_smd_clk_desc rpm_clk_msm8940 = { 747 .clks = msm8940_clks, 748 .num_clks = ARRAY_SIZE(msm8940_clks), 749 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, 750 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), 751}; 752 753static struct clk_smd_rpm *msm8974_clks[] = { 754 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 755 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 756 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, 757 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, 758 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, 759 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, 760 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 761 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 762 [RPM_SMD_CXO_D0] = &clk_smd_rpm_cxo_d0, 763 [RPM_SMD_CXO_D0_A] = &clk_smd_rpm_cxo_d0_a, 764 [RPM_SMD_CXO_D1] = &clk_smd_rpm_cxo_d1, 765 [RPM_SMD_CXO_D1_A] = &clk_smd_rpm_cxo_d1_a, 766 [RPM_SMD_CXO_A0] = &clk_smd_rpm_cxo_a0, 767 [RPM_SMD_CXO_A0_A] = &clk_smd_rpm_cxo_a0_a, 768 [RPM_SMD_CXO_A1] = &clk_smd_rpm_cxo_a1, 769 [RPM_SMD_CXO_A1_A] = &clk_smd_rpm_cxo_a1_a, 770 [RPM_SMD_CXO_A2] = &clk_smd_rpm_cxo_a2, 771 [RPM_SMD_CXO_A2_A] = &clk_smd_rpm_cxo_a2_a, 772 [RPM_SMD_DIFF_CLK] = &clk_smd_rpm_diff_clk, 773 [RPM_SMD_DIFF_A_CLK] = &clk_smd_rpm_diff_clk_a, 774 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 775 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 776 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 777 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 778 [RPM_SMD_CXO_D0_PIN] = &clk_smd_rpm_cxo_d0_pin, 779 [RPM_SMD_CXO_D0_A_PIN] = &clk_smd_rpm_cxo_d0_a_pin, 780 [RPM_SMD_CXO_D1_PIN] = &clk_smd_rpm_cxo_d1_pin, 781 [RPM_SMD_CXO_D1_A_PIN] = &clk_smd_rpm_cxo_d1_a_pin, 782 [RPM_SMD_CXO_A0_PIN] = &clk_smd_rpm_cxo_a0_pin, 783 [RPM_SMD_CXO_A0_A_PIN] = &clk_smd_rpm_cxo_a0_a_pin, 784 [RPM_SMD_CXO_A1_PIN] = &clk_smd_rpm_cxo_a1_pin, 785 [RPM_SMD_CXO_A1_A_PIN] = &clk_smd_rpm_cxo_a1_a_pin, 786 [RPM_SMD_CXO_A2_PIN] = &clk_smd_rpm_cxo_a2_pin, 787 [RPM_SMD_CXO_A2_A_PIN] = &clk_smd_rpm_cxo_a2_a_pin, 788}; 789 790static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { 791 .clks = msm8974_clks, 792 .num_clks = ARRAY_SIZE(msm8974_clks), 793 .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks, 794 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks), 795 .scaling_before_handover = true, 796}; 797 798static struct clk_smd_rpm *msm8976_clks[] = { 799 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 800 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 801 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 802 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 803 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 804 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 805 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 806 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 807 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 808 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 809 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 810 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 811 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 812 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 813 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 814 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 815 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 816 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 817}; 818 819static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { 820 .clks = msm8976_clks, 821 .num_clks = ARRAY_SIZE(msm8976_clks), 822 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, 823 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), 824}; 825 826static struct clk_smd_rpm *msm8992_clks[] = { 827 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 828 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 829 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, 830 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, 831 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 832 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 833 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 834 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 835 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 836 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 837 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 838 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 839 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 840 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 841 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 842 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 843 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 844 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 845 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 846 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 847 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 848 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 849 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, 850 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, 851 [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk, 852 [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk, 853 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 854 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 855 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 856 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 857 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 858 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 859 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 860 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 861 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 862 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 863 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 864 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 865 [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk, 866 [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk, 867}; 868 869static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { 870 .clks = msm8992_clks, 871 .num_clks = ARRAY_SIZE(msm8992_clks), 872 .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks, 873 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks), 874}; 875 876static struct clk_smd_rpm *msm8994_clks[] = { 877 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 878 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 879 [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, 880 [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, 881 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 882 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 883 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 884 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 885 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 886 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 887 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 888 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 889 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 890 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 891 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 892 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 893 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 894 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 895 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 896 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 897 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 898 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 899 [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, 900 [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, 901 [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk, 902 [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk, 903 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 904 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 905 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 906 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 907 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 908 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 909 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 910 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 911 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 912 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 913 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 914 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 915 [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk, 916 [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk, 917 [RPM_SMD_CE3_CLK] = &clk_smd_rpm_ce3_clk, 918 [RPM_SMD_CE3_A_CLK] = &clk_smd_rpm_ce3_a_clk, 919}; 920 921static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { 922 .clks = msm8994_clks, 923 .num_clks = ARRAY_SIZE(msm8994_clks), 924 .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks, 925 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks), 926}; 927 928static struct clk_smd_rpm *msm8996_clks[] = { 929 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 930 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 931 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 932 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 933 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 934 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 935 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 936 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 937 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 938 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 939 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 940 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 941 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 942 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 943 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 944 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 945 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 946 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 947 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 948 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 949 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 950 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 951 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 952 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 953 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 954 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 955 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 956 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 957 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 958 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 959 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 960 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 961}; 962 963static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { 964 .clks = msm8996_clks, 965 .num_clks = ARRAY_SIZE(msm8996_clks), 966 .icc_clks = msm8996_icc_clks, 967 .num_icc_clks = ARRAY_SIZE(msm8996_icc_clks), 968}; 969 970static struct clk_smd_rpm *qcs404_clks[] = { 971 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 972 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 973 [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 974 [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 975 [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, 976 [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, 977 [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, 978 [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, 979 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, 980 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, 981 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 982 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 983 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 984 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 985 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 986 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 987 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, 988 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, 989 [RPM_SMD_LN_BB_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_pin, 990 [RPM_SMD_LN_BB_A_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_a_pin, 991}; 992 993static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { 994 .clks = qcs404_clks, 995 .num_clks = ARRAY_SIZE(qcs404_clks), 996 .icc_clks = bimc_pcnoc_snoc_icc_clks, 997 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks), 998}; 999 1000static struct clk_smd_rpm *msm8998_clks[] = { 1001 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1002 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1003 [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 1004 [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 1005 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1006 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1007 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 1008 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 1009 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 1010 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 1011 [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, 1012 [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, 1013 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1014 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1015 [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1, 1016 [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a, 1017 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 1018 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 1019 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, 1020 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, 1021 [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin, 1022 [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin, 1023 [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin, 1024 [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin, 1025 [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin, 1026 [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin, 1027 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 1028 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 1029 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 1030 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 1031 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 1032 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 1033 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_rf_clk3, 1034 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_rf_clk3_a, 1035 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 1036 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 1037 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 1038 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 1039 [RPM_SMD_RF_CLK3_PIN] = &clk_smd_rpm_rf_clk3_pin, 1040 [RPM_SMD_RF_CLK3_A_PIN] = &clk_smd_rpm_rf_clk3_a_pin, 1041}; 1042 1043static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { 1044 .clks = msm8998_clks, 1045 .num_clks = ARRAY_SIZE(msm8998_clks), 1046 .icc_clks = msm8998_icc_clks, 1047 .num_icc_clks = ARRAY_SIZE(msm8998_icc_clks), 1048}; 1049 1050static struct clk_smd_rpm *sdm429_clks[] = { 1051 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1052 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1053 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 1054 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 1055 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 1056 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 1057 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 1058 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 1059 [RPM_SMD_BB_CLK3] = &clk_smd_rpm_bb_clk3, 1060 [RPM_SMD_BB_CLK3_A] = &clk_smd_rpm_bb_clk3_a, 1061 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 1062 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 1063 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 1064 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 1065 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 1066 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 1067 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 1068 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 1069 [RPM_SMD_BB_CLK3_PIN] = &clk_smd_rpm_bb_clk3_pin, 1070 [RPM_SMD_BB_CLK3_A_PIN] = &clk_smd_rpm_bb_clk3_a_pin, 1071}; 1072 1073static const struct rpm_smd_clk_desc rpm_clk_sdm429 = { 1074 .clks = sdm429_clks, 1075 .num_clks = ARRAY_SIZE(sdm429_clks), 1076 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, 1077 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), 1078}; 1079 1080static struct clk_smd_rpm *sdm660_clks[] = { 1081 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1082 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1083 [RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, 1084 [RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, 1085 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1086 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1087 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1088 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1089 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 1090 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 1091 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 1092 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 1093 [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, 1094 [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, 1095 [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk1, 1096 [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk1_a, 1097 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 1098 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 1099 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, 1100 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, 1101 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 1102 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 1103 [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin, 1104 [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin, 1105 [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin, 1106 [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin, 1107 [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin, 1108 [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin, 1109}; 1110 1111static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { 1112 .clks = sdm660_clks, 1113 .num_clks = ARRAY_SIZE(sdm660_clks), 1114 .icc_clks = sdm660_icc_clks, 1115 .num_icc_clks = ARRAY_SIZE(sdm660_icc_clks), 1116}; 1117 1118static struct clk_smd_rpm *mdm9607_clks[] = { 1119 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1120 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1121 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 1122 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 1123 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 1124 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 1125 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 1126 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 1127 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 1128 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 1129}; 1130 1131static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = { 1132 .clks = mdm9607_clks, 1133 .num_clks = ARRAY_SIZE(mdm9607_clks), 1134 .icc_clks = bimc_pcnoc_icc_clks, 1135 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_icc_clks), 1136}; 1137 1138static struct clk_smd_rpm *msm8953_clks[] = { 1139 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1140 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1141 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1142 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1143 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, 1144 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, 1145 [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, 1146 [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, 1147 [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, 1148 [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, 1149 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 1150 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 1151 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_ln_bb_clk, 1152 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_ln_bb_clk_a, 1153 [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, 1154 [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, 1155 [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, 1156 [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, 1157 [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, 1158 [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, 1159}; 1160 1161static const struct rpm_smd_clk_desc rpm_clk_msm8953 = { 1162 .clks = msm8953_clks, 1163 .num_clks = ARRAY_SIZE(msm8953_clks), 1164 .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, 1165 .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), 1166}; 1167 1168static struct clk_smd_rpm *sm6125_clks[] = { 1169 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1170 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1171 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1172 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1173 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 1174 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 1175 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 1176 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 1177 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1178 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1179 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1180 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1181 [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1, 1182 [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a, 1183 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 1184 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 1185 [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, 1186 [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, 1187 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1188 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1189 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1190 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1191}; 1192 1193static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { 1194 .clks = sm6125_clks, 1195 .num_clks = ARRAY_SIZE(sm6125_clks), 1196 .icc_clks = sm_qnoc_icc_clks, 1197 .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) 1198}; 1199 1200/* SM6115 */ 1201static struct clk_smd_rpm *sm6115_clks[] = { 1202 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1203 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1204 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1205 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1206 [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, 1207 [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, 1208 [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, 1209 [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, 1210 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1211 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1212 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1213 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1214 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1215 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1216 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1217 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1218 [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, 1219 [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, 1220 [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, 1221 [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, 1222}; 1223 1224static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { 1225 .clks = sm6115_clks, 1226 .num_clks = ARRAY_SIZE(sm6115_clks), 1227 .icc_clks = sm_qnoc_icc_clks, 1228 .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) 1229}; 1230 1231static struct clk_smd_rpm *sm6375_clks[] = { 1232 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1233 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1234 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1235 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1236 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1237 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1238 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1239 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1240 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1241 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1242 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1243 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1244 [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk, 1245 [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk, 1246 [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk, 1247 [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, 1248 [RPM_SMD_BIMC_FREQ_LOG] = &clk_smd_rpm_branch_bimc_freq_log, 1249}; 1250 1251static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { 1252 .clks = sm6375_clks, 1253 .num_clks = ARRAY_SIZE(sm6375_clks), 1254 .icc_clks = sm_qnoc_icc_clks, 1255 .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) 1256}; 1257 1258static struct clk_smd_rpm *qcm2290_clks[] = { 1259 [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, 1260 [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, 1261 [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, 1262 [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, 1263 [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, 1264 [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, 1265 [RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3, 1266 [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a, 1267 [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, 1268 [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, 1269 [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, 1270 [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, 1271 [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, 1272 [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, 1273 [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, 1274 [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, 1275 [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, 1276 [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, 1277 [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk, 1278 [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk, 1279 [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk, 1280 [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, 1281 [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, 1282 [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, 1283}; 1284 1285static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = { 1286 .clks = qcm2290_clks, 1287 .num_clks = ARRAY_SIZE(qcm2290_clks), 1288 .icc_clks = qcm2290_icc_clks, 1289 .num_icc_clks = ARRAY_SIZE(qcm2290_icc_clks) 1290}; 1291 1292static const struct of_device_id rpm_smd_clk_match_table[] = { 1293 { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 }, 1294 { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 }, 1295 { .compatible = "qcom,rpmcc-msm8909", .data = &rpm_clk_msm8909 }, 1296 { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, 1297 { .compatible = "qcom,rpmcc-msm8917", .data = &rpm_clk_msm8917 }, 1298 { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 }, 1299 { .compatible = "qcom,rpmcc-msm8937", .data = &rpm_clk_msm8937 }, 1300 { .compatible = "qcom,rpmcc-msm8940", .data = &rpm_clk_msm8940 }, 1301 { .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 }, 1302 { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 }, 1303 { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 }, 1304 { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 }, 1305 { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 }, 1306 { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 }, 1307 { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 }, 1308 { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 }, 1309 { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 }, 1310 { .compatible = "qcom,rpmcc-sdm429", .data = &rpm_clk_sdm429 }, 1311 { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 }, 1312 { .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 }, 1313 { .compatible = "qcom,rpmcc-sm6125", .data = &rpm_clk_sm6125 }, 1314 { .compatible = "qcom,rpmcc-sm6375", .data = &rpm_clk_sm6375 }, 1315 { } 1316}; 1317MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); 1318 1319static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec, 1320 void *data) 1321{ 1322 const struct rpm_smd_clk_desc *desc = data; 1323 unsigned int idx = clkspec->args[0]; 1324 1325 if (idx >= desc->num_clks) { 1326 pr_err("%s: invalid index %u\n", __func__, idx); 1327 return ERR_PTR(-EINVAL); 1328 } 1329 1330 return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT); 1331} 1332 1333static void rpm_smd_unregister_icc(void *data) 1334{ 1335 struct platform_device *icc_pdev = data; 1336 1337 platform_device_unregister(icc_pdev); 1338} 1339 1340static int rpm_smd_clk_probe(struct platform_device *pdev) 1341{ 1342 int ret; 1343 size_t num_clks, i; 1344 struct clk_smd_rpm **rpm_smd_clks; 1345 const struct rpm_smd_clk_desc *desc; 1346 struct platform_device *icc_pdev; 1347 1348 rpmcc_smd_rpm = dev_get_drvdata(pdev->dev.parent); 1349 if (!rpmcc_smd_rpm) { 1350 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n"); 1351 return -ENODEV; 1352 } 1353 1354 desc = of_device_get_match_data(&pdev->dev); 1355 if (!desc) 1356 return -EINVAL; 1357 1358 rpm_smd_clks = desc->clks; 1359 num_clks = desc->num_clks; 1360 1361 if (desc->scaling_before_handover) { 1362 ret = clk_smd_rpm_enable_scaling(); 1363 if (ret) 1364 goto err; 1365 } 1366 1367 for (i = 0; i < num_clks; i++) { 1368 if (!rpm_smd_clks[i]) 1369 continue; 1370 1371 ret = clk_smd_rpm_handoff(rpm_smd_clks[i]); 1372 if (ret) 1373 goto err; 1374 } 1375 1376 for (i = 0; i < desc->num_icc_clks; i++) { 1377 if (!desc->icc_clks[i]) 1378 continue; 1379 1380 ret = clk_smd_rpm_handoff(desc->icc_clks[i]); 1381 if (ret) 1382 goto err; 1383 } 1384 1385 if (!desc->scaling_before_handover) { 1386 ret = clk_smd_rpm_enable_scaling(); 1387 if (ret) 1388 goto err; 1389 } 1390 1391 for (i = 0; i < num_clks; i++) { 1392 if (!rpm_smd_clks[i]) 1393 continue; 1394 1395 ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw); 1396 if (ret) 1397 goto err; 1398 } 1399 1400 ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get, 1401 (void *)desc); 1402 if (ret) 1403 goto err; 1404 1405 icc_pdev = platform_device_register_data(pdev->dev.parent, 1406 "icc_smd_rpm", -1, NULL, 0); 1407 if (IS_ERR(icc_pdev)) { 1408 dev_err(&pdev->dev, "Failed to register icc_smd_rpm device: %pE\n", 1409 icc_pdev); 1410 /* No need to unregister clocks because of this */ 1411 } else { 1412 ret = devm_add_action_or_reset(&pdev->dev, rpm_smd_unregister_icc, 1413 icc_pdev); 1414 if (ret) 1415 goto err; 1416 } 1417 1418 return 0; 1419err: 1420 dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret); 1421 return ret; 1422} 1423 1424static struct platform_driver rpm_smd_clk_driver = { 1425 .driver = { 1426 .name = "qcom-clk-smd-rpm", 1427 .of_match_table = rpm_smd_clk_match_table, 1428 }, 1429 .probe = rpm_smd_clk_probe, 1430}; 1431 1432static int __init rpm_smd_clk_init(void) 1433{ 1434 return platform_driver_register(&rpm_smd_clk_driver); 1435} 1436core_initcall(rpm_smd_clk_init); 1437 1438static void __exit rpm_smd_clk_exit(void) 1439{ 1440 platform_driver_unregister(&rpm_smd_clk_driver); 1441} 1442module_exit(rpm_smd_clk_exit); 1443 1444MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver"); 1445MODULE_LICENSE("GPL v2"); 1446MODULE_ALIAS("platform:qcom-clk-smd-rpm");
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