clk-rcg.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */
  3
  4#ifndef __QCOM_CLK_RCG_H__
  5#define __QCOM_CLK_RCG_H__
  6
  7#include <linux/clk-provider.h>
  8#include "clk-regmap.h"
  9
 10#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 11
 12struct freq_tbl {
 13	unsigned long freq;
 14	u8 src;
 15	u8 pre_div;
 16	u16 m;
 17	u16 n;
 18};
 19
 20#define C(s, h, m, n) { (s), (2 * (h) - 1), (m), (n) }
 21#define FM(f, confs) { (f), ARRAY_SIZE(confs), (confs) }
 22#define FMS(f, s, h, m, n) { (f), 1, (const struct freq_conf []){ C(s, h, m, n) } }
 23
 24struct freq_conf {
 25	u8 src;
 26	u8 pre_div;
 27	u16 m;
 28	u16 n;
 29};
 30
 31struct freq_multi_tbl {
 32	unsigned long freq;
 33	size_t num_confs;
 34	const struct freq_conf *confs;
 35};
 36
 37/**
 38 * struct mn - M/N:D counter
 39 * @mnctr_en_bit: bit to enable mn counter
 40 * @mnctr_reset_bit: bit to assert mn counter reset
 41 * @mnctr_mode_shift: lowest bit of mn counter mode field
 42 * @n_val_shift: lowest bit of n value field
 43 * @m_val_shift: lowest bit of m value field
 44 * @width: number of bits in m/n/d values
 45 * @reset_in_cc: true if the mnctr_reset_bit is in the CC register
 46 */
 47struct mn {
 48	u8		mnctr_en_bit;
 49	u8		mnctr_reset_bit;
 50	u8		mnctr_mode_shift;
 51#define MNCTR_MODE_DUAL 0x2
 52#define MNCTR_MODE_MASK 0x3
 53	u8		n_val_shift;
 54	u8		m_val_shift;
 55	u8		width;
 56	bool		reset_in_cc;
 57};
 58
 59/**
 60 * struct pre_div - pre-divider
 61 * @pre_div_shift: lowest bit of pre divider field
 62 * @pre_div_width: number of bits in predivider
 63 */
 64struct pre_div {
 65	u8		pre_div_shift;
 66	u8		pre_div_width;
 67};
 68
 69/**
 70 * struct src_sel - source selector
 71 * @src_sel_shift: lowest bit of source selection field
 72 * @parent_map: map from software's parent index to hardware's src_sel field
 73 */
 74struct src_sel {
 75	u8		src_sel_shift;
 76#define SRC_SEL_MASK	0x7
 77	const struct parent_map	*parent_map;
 78};
 79
 80/**
 81 * struct clk_rcg - root clock generator
 82 *
 83 * @ns_reg: NS register
 84 * @md_reg: MD register
 85 * @mn: mn counter
 86 * @p: pre divider
 87 * @s: source selector
 88 * @freq_tbl: frequency table
 89 * @clkr: regmap clock handle
 90 * @lock: register lock
 91 */
 92struct clk_rcg {
 93	u32		ns_reg;
 94	u32		md_reg;
 95
 96	struct mn	mn;
 97	struct pre_div	p;
 98	struct src_sel	s;
 99
100	const struct freq_tbl	*freq_tbl;
101
102	struct clk_regmap	clkr;
103};
104
105extern const struct clk_ops clk_rcg_ops;
106extern const struct clk_ops clk_rcg_floor_ops;
107extern const struct clk_ops clk_rcg_bypass_ops;
108extern const struct clk_ops clk_rcg_bypass2_ops;
109extern const struct clk_ops clk_rcg_pixel_ops;
110extern const struct clk_ops clk_rcg_esc_ops;
111extern const struct clk_ops clk_rcg_lcc_ops;
112
113#define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
114
115/**
116 * struct clk_dyn_rcg - root clock generator with glitch free mux
117 *
118 * @mux_sel_bit: bit to switch glitch free mux
119 * @ns_reg: NS0 and NS1 register
120 * @md_reg: MD0 and MD1 register
121 * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
122 * @mn: mn counter (banked)
123 * @s: source selector (banked)
124 * @freq_tbl: frequency table
125 * @clkr: regmap clock handle
126 * @lock: register lock
127 */
128struct clk_dyn_rcg {
129	u32	ns_reg[2];
130	u32	md_reg[2];
131	u32	bank_reg;
132
133	u8	mux_sel_bit;
134
135	struct mn	mn[2];
136	struct pre_div	p[2];
137	struct src_sel	s[2];
138
139	const struct freq_tbl *freq_tbl;
140
141	struct clk_regmap clkr;
142};
143
144extern const struct clk_ops clk_dyn_rcg_ops;
145
146#define to_clk_dyn_rcg(_hw) \
147	container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr)
148
149/**
150 * struct clk_rcg2 - root clock generator
151 *
152 * @cmd_rcgr: corresponds to *_CMD_RCGR
153 * @mnd_width: number of bits in m/n/d values
154 * @hid_width: number of bits in half integer divider
155 * @safe_src_index: safe src index value
156 * @parent_map: map from software's parent index to hardware's src_sel field
157 * @freq_tbl: frequency table
158 * @freq_multi_tbl: frequency table for clocks reachable with multiple RCGs conf
159 * @clkr: regmap clock handle
160 * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
161 * @parked_cfg: cached value of the CFG register for parked RCGs
162 * @hw_clk_ctrl: whether to enable hardware clock control
163 */
164struct clk_rcg2 {
165	u32			cmd_rcgr;
166	u8			mnd_width;
167	u8			hid_width;
168	u8			safe_src_index;
169	const struct parent_map	*parent_map;
170	union {
171		const struct freq_tbl		*freq_tbl;
172		const struct freq_multi_tbl	*freq_multi_tbl;
173	};
174	struct clk_regmap	clkr;
175	u8			cfg_off;
176	u32			parked_cfg;
177	bool			hw_clk_ctrl;
178};
179
180#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
181
182struct clk_rcg2_gfx3d {
183	u8 div;
184	struct clk_rcg2 rcg;
185	struct clk_hw **hws;
186};
187
188#define to_clk_rcg2_gfx3d(_hw) \
189	container_of(to_clk_rcg2(_hw), struct clk_rcg2_gfx3d, rcg)
190
191extern const struct clk_ops clk_rcg2_ops;
192extern const struct clk_ops clk_rcg2_gp_ops;
193extern const struct clk_ops clk_rcg2_floor_ops;
194extern const struct clk_ops clk_rcg2_fm_ops;
195extern const struct clk_ops clk_rcg2_mux_closest_ops;
196extern const struct clk_ops clk_edp_pixel_ops;
197extern const struct clk_ops clk_byte_ops;
198extern const struct clk_ops clk_byte2_ops;
199extern const struct clk_ops clk_pixel_ops;
200extern const struct clk_ops clk_gfx3d_ops;
201extern const struct clk_ops clk_rcg2_shared_ops;
202extern const struct clk_ops clk_rcg2_shared_floor_ops;
203extern const struct clk_ops clk_rcg2_shared_no_init_park_ops;
204extern const struct clk_ops clk_dp_ops;
205
206struct clk_rcg_dfs_data {
207	struct clk_rcg2 *rcg;
208	struct clk_init_data *init;
209};
210
211#define DEFINE_RCG_DFS(r) \
212	{ .rcg = &r, .init = &r##_init }
213
214extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
215				    const struct clk_rcg_dfs_data *rcgs,
216				    size_t len);
217#endif