FILE
clk-alpha-pll.c
File preview with syntax highlighting.
linux-6.19.14/drivers/clk/qcom/clk-alpha-pll.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#include <linux/kernel.h> 8#include <linux/export.h> 9#include <linux/clk-provider.h> 10#include <linux/regmap.h> 11#include <linux/delay.h> 12 13#include "clk-alpha-pll.h" 14#include "common.h" 15 16#define PLL_MODE(p) ((p)->offset + 0x0) 17# define PLL_OUTCTRL BIT(0) 18# define PLL_BYPASSNL BIT(1) 19# define PLL_RESET_N BIT(2) 20# define PLL_OFFLINE_REQ BIT(7) 21# define PLL_LOCK_COUNT_SHIFT 8 22# define PLL_LOCK_COUNT_MASK 0x3f 23# define PLL_BIAS_COUNT_SHIFT 14 24# define PLL_BIAS_COUNT_MASK 0x3f 25# define PLL_VOTE_FSM_ENA BIT(20) 26# define PLL_FSM_ENA BIT(20) 27# define PLL_VOTE_FSM_RESET BIT(21) 28# define PLL_UPDATE BIT(22) 29# define PLL_UPDATE_BYPASS BIT(23) 30# define PLL_FSM_LEGACY_MODE BIT(24) 31# define PLL_OFFLINE_ACK BIT(28) 32# define ALPHA_PLL_ACK_LATCH BIT(29) 33# define PLL_ACTIVE_FLAG BIT(30) 34# define PLL_LOCK_DET BIT(31) 35 36#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 37#define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL]) 38#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 39#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 40 41#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) 42# define PLL_POST_DIV_SHIFT 8 43# define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0) 44# define PLL_ALPHA_MSB BIT(15) 45# define PLL_ALPHA_EN BIT(24) 46# define PLL_ALPHA_MODE BIT(25) 47# define PLL_VCO_SHIFT 20 48# define PLL_VCO_MASK 0x3 49 50#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 51#define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1]) 52 53#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 54#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 55#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1]) 56#define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2]) 57#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 58#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 59#define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1]) 60#define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2]) 61#define PLL_TEST_CTL_U3(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U3]) 62#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 63#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 64#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 65 66#define GET_PLL_TYPE(pll) (((pll)->regs - clk_alpha_pll_regs[0]) / PLL_OFF_MAX_REGS) 67 68const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 69 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 70 [PLL_OFF_L_VAL] = 0x04, 71 [PLL_OFF_ALPHA_VAL] = 0x08, 72 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 73 [PLL_OFF_USER_CTL] = 0x10, 74 [PLL_OFF_USER_CTL_U] = 0x14, 75 [PLL_OFF_CONFIG_CTL] = 0x18, 76 [PLL_OFF_TEST_CTL] = 0x1c, 77 [PLL_OFF_TEST_CTL_U] = 0x20, 78 [PLL_OFF_STATUS] = 0x24, 79 }, 80 [CLK_ALPHA_PLL_TYPE_HUAYRA] = { 81 [PLL_OFF_L_VAL] = 0x04, 82 [PLL_OFF_ALPHA_VAL] = 0x08, 83 [PLL_OFF_USER_CTL] = 0x10, 84 [PLL_OFF_CONFIG_CTL] = 0x14, 85 [PLL_OFF_CONFIG_CTL_U] = 0x18, 86 [PLL_OFF_TEST_CTL] = 0x1c, 87 [PLL_OFF_TEST_CTL_U] = 0x20, 88 [PLL_OFF_STATUS] = 0x24, 89 }, 90 [CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = { 91 [PLL_OFF_L_VAL] = 0x08, 92 [PLL_OFF_ALPHA_VAL] = 0x10, 93 [PLL_OFF_USER_CTL] = 0x18, 94 [PLL_OFF_CONFIG_CTL] = 0x20, 95 [PLL_OFF_CONFIG_CTL_U] = 0x24, 96 [PLL_OFF_STATUS] = 0x28, 97 [PLL_OFF_TEST_CTL] = 0x30, 98 [PLL_OFF_TEST_CTL_U] = 0x34, 99 }, 100 [CLK_ALPHA_PLL_TYPE_HUAYRA_2290] = { 101 [PLL_OFF_L_VAL] = 0x04, 102 [PLL_OFF_ALPHA_VAL] = 0x08, 103 [PLL_OFF_USER_CTL] = 0x0c, 104 [PLL_OFF_CONFIG_CTL] = 0x10, 105 [PLL_OFF_CONFIG_CTL_U] = 0x14, 106 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 107 [PLL_OFF_TEST_CTL] = 0x1c, 108 [PLL_OFF_TEST_CTL_U] = 0x20, 109 [PLL_OFF_TEST_CTL_U1] = 0x24, 110 [PLL_OFF_OPMODE] = 0x28, 111 [PLL_OFF_STATUS] = 0x38, 112 }, 113 [CLK_ALPHA_PLL_TYPE_BRAMMO] = { 114 [PLL_OFF_L_VAL] = 0x04, 115 [PLL_OFF_ALPHA_VAL] = 0x08, 116 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 117 [PLL_OFF_USER_CTL] = 0x10, 118 [PLL_OFF_CONFIG_CTL] = 0x18, 119 [PLL_OFF_TEST_CTL] = 0x1c, 120 [PLL_OFF_STATUS] = 0x24, 121 }, 122 [CLK_ALPHA_PLL_TYPE_FABIA] = { 123 [PLL_OFF_L_VAL] = 0x04, 124 [PLL_OFF_USER_CTL] = 0x0c, 125 [PLL_OFF_USER_CTL_U] = 0x10, 126 [PLL_OFF_CONFIG_CTL] = 0x14, 127 [PLL_OFF_CONFIG_CTL_U] = 0x18, 128 [PLL_OFF_TEST_CTL] = 0x1c, 129 [PLL_OFF_TEST_CTL_U] = 0x20, 130 [PLL_OFF_STATUS] = 0x24, 131 [PLL_OFF_OPMODE] = 0x2c, 132 [PLL_OFF_FRAC] = 0x38, 133 }, 134 [CLK_ALPHA_PLL_TYPE_TRION] = { 135 [PLL_OFF_L_VAL] = 0x04, 136 [PLL_OFF_CAL_L_VAL] = 0x08, 137 [PLL_OFF_USER_CTL] = 0x0c, 138 [PLL_OFF_USER_CTL_U] = 0x10, 139 [PLL_OFF_USER_CTL_U1] = 0x14, 140 [PLL_OFF_CONFIG_CTL] = 0x18, 141 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 142 [PLL_OFF_CONFIG_CTL_U1] = 0x20, 143 [PLL_OFF_TEST_CTL] = 0x24, 144 [PLL_OFF_TEST_CTL_U] = 0x28, 145 [PLL_OFF_TEST_CTL_U1] = 0x2c, 146 [PLL_OFF_STATUS] = 0x30, 147 [PLL_OFF_OPMODE] = 0x38, 148 [PLL_OFF_ALPHA_VAL] = 0x40, 149 }, 150 [CLK_ALPHA_PLL_TYPE_AGERA] = { 151 [PLL_OFF_L_VAL] = 0x04, 152 [PLL_OFF_ALPHA_VAL] = 0x08, 153 [PLL_OFF_USER_CTL] = 0x0c, 154 [PLL_OFF_CONFIG_CTL] = 0x10, 155 [PLL_OFF_CONFIG_CTL_U] = 0x14, 156 [PLL_OFF_TEST_CTL] = 0x18, 157 [PLL_OFF_TEST_CTL_U] = 0x1c, 158 [PLL_OFF_STATUS] = 0x2c, 159 }, 160 [CLK_ALPHA_PLL_TYPE_ZONDA] = { 161 [PLL_OFF_L_VAL] = 0x04, 162 [PLL_OFF_ALPHA_VAL] = 0x08, 163 [PLL_OFF_USER_CTL] = 0x0c, 164 [PLL_OFF_CONFIG_CTL] = 0x10, 165 [PLL_OFF_CONFIG_CTL_U] = 0x14, 166 [PLL_OFF_CONFIG_CTL_U1] = 0x18, 167 [PLL_OFF_TEST_CTL] = 0x1c, 168 [PLL_OFF_TEST_CTL_U] = 0x20, 169 [PLL_OFF_TEST_CTL_U1] = 0x24, 170 [PLL_OFF_OPMODE] = 0x28, 171 [PLL_OFF_STATUS] = 0x38, 172 }, 173 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = { 174 [PLL_OFF_OPMODE] = 0x04, 175 [PLL_OFF_STATUS] = 0x0c, 176 [PLL_OFF_L_VAL] = 0x10, 177 [PLL_OFF_ALPHA_VAL] = 0x14, 178 [PLL_OFF_USER_CTL] = 0x18, 179 [PLL_OFF_USER_CTL_U] = 0x1c, 180 [PLL_OFF_CONFIG_CTL] = 0x20, 181 [PLL_OFF_CONFIG_CTL_U] = 0x24, 182 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 183 [PLL_OFF_TEST_CTL] = 0x2c, 184 [PLL_OFF_TEST_CTL_U] = 0x30, 185 [PLL_OFF_TEST_CTL_U1] = 0x34, 186 }, 187 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = { 188 [PLL_OFF_OPMODE] = 0x04, 189 [PLL_OFF_STATE] = 0x08, 190 [PLL_OFF_STATUS] = 0x0c, 191 [PLL_OFF_L_VAL] = 0x10, 192 [PLL_OFF_ALPHA_VAL] = 0x14, 193 [PLL_OFF_USER_CTL] = 0x18, 194 [PLL_OFF_USER_CTL_U] = 0x1c, 195 [PLL_OFF_CONFIG_CTL] = 0x20, 196 [PLL_OFF_CONFIG_CTL_U] = 0x24, 197 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 198 [PLL_OFF_TEST_CTL] = 0x2c, 199 [PLL_OFF_TEST_CTL_U] = 0x30, 200 [PLL_OFF_TEST_CTL_U1] = 0x34, 201 [PLL_OFF_TEST_CTL_U2] = 0x38, 202 }, 203 [CLK_ALPHA_PLL_TYPE_PONGO_ELU] = { 204 [PLL_OFF_OPMODE] = 0x04, 205 [PLL_OFF_STATE] = 0x08, 206 [PLL_OFF_STATUS] = 0x0c, 207 [PLL_OFF_L_VAL] = 0x10, 208 [PLL_OFF_USER_CTL] = 0x14, 209 [PLL_OFF_USER_CTL_U] = 0x18, 210 [PLL_OFF_CONFIG_CTL] = 0x1c, 211 [PLL_OFF_CONFIG_CTL_U] = 0x20, 212 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 213 [PLL_OFF_CONFIG_CTL_U2] = 0x28, 214 [PLL_OFF_TEST_CTL] = 0x2c, 215 [PLL_OFF_TEST_CTL_U] = 0x30, 216 [PLL_OFF_TEST_CTL_U1] = 0x34, 217 [PLL_OFF_TEST_CTL_U2] = 0x38, 218 [PLL_OFF_TEST_CTL_U3] = 0x3c, 219 }, 220 [CLK_ALPHA_PLL_TYPE_TAYCAN_ELU] = { 221 [PLL_OFF_OPMODE] = 0x04, 222 [PLL_OFF_STATE] = 0x08, 223 [PLL_OFF_STATUS] = 0x0c, 224 [PLL_OFF_L_VAL] = 0x10, 225 [PLL_OFF_ALPHA_VAL] = 0x14, 226 [PLL_OFF_USER_CTL] = 0x18, 227 [PLL_OFF_USER_CTL_U] = 0x1c, 228 [PLL_OFF_CONFIG_CTL] = 0x20, 229 [PLL_OFF_CONFIG_CTL_U] = 0x24, 230 [PLL_OFF_CONFIG_CTL_U1] = 0x28, 231 [PLL_OFF_TEST_CTL] = 0x2c, 232 [PLL_OFF_TEST_CTL_U] = 0x30, 233 }, 234 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = { 235 [PLL_OFF_OPMODE] = 0x04, 236 [PLL_OFF_STATUS] = 0x0c, 237 [PLL_OFF_L_VAL] = 0x10, 238 [PLL_OFF_USER_CTL] = 0x14, 239 [PLL_OFF_USER_CTL_U] = 0x18, 240 [PLL_OFF_CONFIG_CTL] = 0x1c, 241 [PLL_OFF_CONFIG_CTL_U] = 0x20, 242 [PLL_OFF_CONFIG_CTL_U1] = 0x24, 243 [PLL_OFF_TEST_CTL] = 0x28, 244 [PLL_OFF_TEST_CTL_U] = 0x2c, 245 }, 246 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = { 247 [PLL_OFF_L_VAL] = 0x04, 248 [PLL_OFF_ALPHA_VAL] = 0x08, 249 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 250 [PLL_OFF_TEST_CTL] = 0x10, 251 [PLL_OFF_TEST_CTL_U] = 0x14, 252 [PLL_OFF_USER_CTL] = 0x18, 253 [PLL_OFF_USER_CTL_U] = 0x1c, 254 [PLL_OFF_CONFIG_CTL] = 0x20, 255 [PLL_OFF_STATUS] = 0x24, 256 }, 257 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = { 258 [PLL_OFF_L_VAL] = 0x04, 259 [PLL_OFF_ALPHA_VAL] = 0x08, 260 [PLL_OFF_ALPHA_VAL_U] = 0x0c, 261 [PLL_OFF_TEST_CTL] = 0x10, 262 [PLL_OFF_TEST_CTL_U] = 0x14, 263 [PLL_OFF_USER_CTL] = 0x18, 264 [PLL_OFF_CONFIG_CTL] = 0x1C, 265 [PLL_OFF_STATUS] = 0x20, 266 }, 267 [CLK_ALPHA_PLL_TYPE_STROMER] = { 268 [PLL_OFF_L_VAL] = 0x08, 269 [PLL_OFF_ALPHA_VAL] = 0x10, 270 [PLL_OFF_ALPHA_VAL_U] = 0x14, 271 [PLL_OFF_USER_CTL] = 0x18, 272 [PLL_OFF_USER_CTL_U] = 0x1c, 273 [PLL_OFF_CONFIG_CTL] = 0x20, 274 [PLL_OFF_STATUS] = 0x28, 275 [PLL_OFF_TEST_CTL] = 0x30, 276 [PLL_OFF_TEST_CTL_U] = 0x34, 277 }, 278 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { 279 [PLL_OFF_L_VAL] = 0x04, 280 [PLL_OFF_USER_CTL] = 0x08, 281 [PLL_OFF_USER_CTL_U] = 0x0c, 282 [PLL_OFF_CONFIG_CTL] = 0x10, 283 [PLL_OFF_TEST_CTL] = 0x14, 284 [PLL_OFF_TEST_CTL_U] = 0x18, 285 [PLL_OFF_STATUS] = 0x1c, 286 [PLL_OFF_ALPHA_VAL] = 0x24, 287 [PLL_OFF_ALPHA_VAL_U] = 0x28, 288 }, 289 [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = { 290 [PLL_OFF_L_VAL] = 0x04, 291 [PLL_OFF_ALPHA_VAL] = 0x08, 292 [PLL_OFF_USER_CTL] = 0x0c, 293 [PLL_OFF_USER_CTL_U] = 0x10, 294 [PLL_OFF_CONFIG_CTL] = 0x14, 295 [PLL_OFF_CONFIG_CTL_U] = 0x18, 296 [PLL_OFF_CONFIG_CTL_U1] = 0x1c, 297 [PLL_OFF_CONFIG_CTL_U2] = 0x20, 298 [PLL_OFF_TEST_CTL] = 0x24, 299 [PLL_OFF_TEST_CTL_U] = 0x28, 300 [PLL_OFF_TEST_CTL_U1] = 0x2c, 301 [PLL_OFF_OPMODE] = 0x30, 302 [PLL_OFF_STATUS] = 0x3c, 303 }, 304 [CLK_ALPHA_PLL_TYPE_NSS_HUAYRA] = { 305 [PLL_OFF_L_VAL] = 0x04, 306 [PLL_OFF_ALPHA_VAL] = 0x08, 307 [PLL_OFF_TEST_CTL] = 0x0c, 308 [PLL_OFF_TEST_CTL_U] = 0x10, 309 [PLL_OFF_USER_CTL] = 0x14, 310 [PLL_OFF_CONFIG_CTL] = 0x18, 311 [PLL_OFF_CONFIG_CTL_U] = 0x1c, 312 [PLL_OFF_STATUS] = 0x20, 313 }, 314 315}; 316EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 317 318/* 319 * Even though 40 bits are present, use only 32 for ease of calculation. 320 */ 321#define ALPHA_REG_BITWIDTH 40 322#define ALPHA_REG_16BIT_WIDTH 16 323#define ALPHA_BITWIDTH 32U 324#define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) 325 326#define ALPHA_PLL_STATUS_REG_SHIFT 8 327 328#define PLL_HUAYRA_M_WIDTH 8 329#define PLL_HUAYRA_M_SHIFT 8 330#define PLL_HUAYRA_M_MASK 0xff 331#define PLL_HUAYRA_N_SHIFT 0 332#define PLL_HUAYRA_N_MASK 0xff 333#define PLL_HUAYRA_ALPHA_WIDTH 16 334 335#define PLL_STANDBY 0x0 336#define PLL_RUN 0x1 337#define PLL_OUT_MASK 0x7 338#define PLL_RATE_MARGIN 500 339 340/* TRION PLL specific settings and offsets */ 341#define TRION_PLL_CAL_VAL 0x44 342#define TRION_PCAL_DONE BIT(26) 343 344/* LUCID PLL specific settings and offsets */ 345#define LUCID_PCAL_DONE BIT(27) 346 347/* LUCID 5LPE PLL specific settings and offsets */ 348#define LUCID_5LPE_PCAL_DONE BIT(11) 349#define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) 350#define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) 351#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21) 352 353/* LUCID EVO PLL specific settings and offsets */ 354#define LUCID_EVO_PCAL_NOT_DONE BIT(8) 355#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25) 356#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) 357#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16 358#define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24 359 360/* PONGO ELU PLL specific setting and offsets */ 361#define PONGO_PLL_OUT_MASK GENMASK(1, 0) 362#define PONGO_PLL_L_VAL_MASK GENMASK(11, 0) 363#define PONGO_XO_PRESENT BIT(10) 364#define PONGO_CLOCK_SELECT BIT(12) 365 366/* ZONDA PLL specific */ 367#define ZONDA_PLL_OUT_MASK 0xf 368#define ZONDA_STAY_IN_CFA BIT(16) 369#define ZONDA_PLL_FREQ_LOCK_DET BIT(29) 370 371#define pll_alpha_width(p) \ 372 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 373 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 374 375#define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) 376 377#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ 378 struct clk_alpha_pll, clkr) 379 380#define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \ 381 struct clk_alpha_pll_postdiv, clkr) 382 383static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, 384 const char *action) 385{ 386 u32 val; 387 int count; 388 int ret; 389 const char *name = clk_hw_get_name(&pll->clkr.hw); 390 391 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 392 if (ret) 393 return ret; 394 395 /* Pongo PLLs using a 32KHz reference can take upwards of 1500us to lock. */ 396 for (count = 1500; count > 0; count--) { 397 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 398 if (ret) 399 return ret; 400 if (inverse && !(val & mask)) 401 return 0; 402 else if ((val & mask) == mask) 403 return 0; 404 405 udelay(1); 406 } 407 408 WARN(1, "%s failed to %s!\n", name, action); 409 return -ETIMEDOUT; 410} 411 412#define wait_for_pll_enable_active(pll) \ 413 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable") 414 415#define wait_for_pll_enable_lock(pll) \ 416 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable") 417 418#define wait_for_zonda_pll_freq_lock(pll) \ 419 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable") 420 421#define wait_for_pll_disable(pll) \ 422 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable") 423 424#define wait_for_pll_offline(pll) \ 425 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline") 426 427#define wait_for_pll_update(pll) \ 428 wait_for_pll(pll, PLL_UPDATE, 1, "update") 429 430#define wait_for_pll_update_ack_set(pll) \ 431 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set") 432 433#define wait_for_pll_update_ack_clear(pll) \ 434 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear") 435 436static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg, 437 unsigned int val) 438{ 439 if (val) 440 regmap_write(regmap, reg, val); 441} 442 443void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 444 const struct alpha_pll_config *config) 445{ 446 u32 val, mask; 447 448 regmap_write(regmap, PLL_L_VAL(pll), config->l); 449 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 450 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 451 452 if (pll_has_64bit_config(pll)) 453 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 454 config->config_ctl_hi_val); 455 456 if (pll_alpha_width(pll) > 32) 457 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 458 459 val = config->main_output_mask; 460 val |= config->aux_output_mask; 461 val |= config->aux2_output_mask; 462 val |= config->early_output_mask; 463 val |= config->pre_div_val; 464 val |= config->post_div_val; 465 val |= config->vco_val; 466 val |= config->alpha_en_mask; 467 val |= config->alpha_mode_mask; 468 469 mask = config->main_output_mask; 470 mask |= config->aux_output_mask; 471 mask |= config->aux2_output_mask; 472 mask |= config->early_output_mask; 473 mask |= config->pre_div_mask; 474 mask |= config->post_div_mask; 475 mask |= config->vco_mask; 476 mask |= config->alpha_en_mask; 477 mask |= config->alpha_mode_mask; 478 479 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 480 481 if (config->test_ctl_mask) 482 regmap_update_bits(regmap, PLL_TEST_CTL(pll), 483 config->test_ctl_mask, 484 config->test_ctl_val); 485 else 486 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 487 config->test_ctl_val); 488 489 if (config->test_ctl_hi_mask) 490 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll), 491 config->test_ctl_hi_mask, 492 config->test_ctl_hi_val); 493 else 494 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 495 config->test_ctl_hi_val); 496 497 if (pll->flags & SUPPORTS_FSM_MODE) 498 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 499} 500EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); 501 502static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) 503{ 504 int ret; 505 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 506 u32 val; 507 508 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 509 if (ret) 510 return ret; 511 512 val |= PLL_FSM_ENA; 513 514 if (pll->flags & SUPPORTS_OFFLINE_REQ) 515 val &= ~PLL_OFFLINE_REQ; 516 517 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val); 518 if (ret) 519 return ret; 520 521 /* Make sure enable request goes through before waiting for update */ 522 mb(); 523 524 return wait_for_pll_enable_active(pll); 525} 526 527static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) 528{ 529 int ret; 530 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 531 u32 val; 532 533 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 534 if (ret) 535 return; 536 537 if (pll->flags & SUPPORTS_OFFLINE_REQ) { 538 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 539 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ); 540 if (ret) 541 return; 542 543 ret = wait_for_pll_offline(pll); 544 if (ret) 545 return; 546 } 547 548 /* Disable hwfsm */ 549 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 550 PLL_FSM_ENA, 0); 551 if (ret) 552 return; 553 554 wait_for_pll_disable(pll); 555} 556 557static int pll_is_enabled(struct clk_hw *hw, u32 mask) 558{ 559 int ret; 560 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 561 u32 val; 562 563 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 564 if (ret) 565 return ret; 566 567 return !!(val & mask); 568} 569 570static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw) 571{ 572 return pll_is_enabled(hw, PLL_ACTIVE_FLAG); 573} 574 575static int clk_alpha_pll_is_enabled(struct clk_hw *hw) 576{ 577 return pll_is_enabled(hw, PLL_LOCK_DET); 578} 579 580static int clk_alpha_pll_enable(struct clk_hw *hw) 581{ 582 int ret; 583 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 584 u32 val, mask; 585 586 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; 587 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 588 if (ret) 589 return ret; 590 591 /* If in FSM mode, just vote for it */ 592 if (val & PLL_VOTE_FSM_ENA) { 593 ret = clk_enable_regmap(hw); 594 if (ret) 595 return ret; 596 return wait_for_pll_enable_active(pll); 597 } 598 599 /* Skip if already enabled */ 600 if ((val & mask) == mask) 601 return 0; 602 603 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 604 PLL_BYPASSNL, PLL_BYPASSNL); 605 if (ret) 606 return ret; 607 608 /* 609 * H/W requires a 5us delay between disabling the bypass and 610 * de-asserting the reset. 611 */ 612 mb(); 613 udelay(5); 614 615 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 616 PLL_RESET_N, PLL_RESET_N); 617 if (ret) 618 return ret; 619 620 ret = wait_for_pll_enable_lock(pll); 621 if (ret) 622 return ret; 623 624 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), 625 PLL_OUTCTRL, PLL_OUTCTRL); 626 627 /* Ensure that the write above goes through before returning. */ 628 mb(); 629 return ret; 630} 631 632static void clk_alpha_pll_disable(struct clk_hw *hw) 633{ 634 int ret; 635 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 636 u32 val, mask; 637 638 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 639 if (ret) 640 return; 641 642 /* If in FSM mode, just unvote it */ 643 if (val & PLL_VOTE_FSM_ENA) { 644 clk_disable_regmap(hw); 645 return; 646 } 647 648 mask = PLL_OUTCTRL; 649 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 650 651 /* Delay of 2 output clock ticks required until output is disabled */ 652 mb(); 653 udelay(1); 654 655 mask = PLL_RESET_N | PLL_BYPASSNL; 656 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); 657} 658 659static unsigned long 660alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width) 661{ 662 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width)); 663} 664 665static unsigned long 666alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a, 667 u32 alpha_width) 668{ 669 u64 remainder; 670 u64 quotient; 671 672 quotient = rate; 673 remainder = do_div(quotient, prate); 674 *l = quotient; 675 676 if (!remainder) { 677 *a = 0; 678 return rate; 679 } 680 681 /* Upper ALPHA_BITWIDTH bits of Alpha */ 682 quotient = remainder << ALPHA_SHIFT(alpha_width); 683 684 remainder = do_div(quotient, prate); 685 686 if (remainder) 687 quotient++; 688 689 *a = quotient; 690 return alpha_pll_calc_rate(prate, *l, *a, alpha_width); 691} 692 693static const struct pll_vco * 694alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate) 695{ 696 const struct pll_vco *v = pll->vco_table; 697 const struct pll_vco *end = v + pll->num_vco; 698 699 for (; v < end; v++) 700 if (rate >= v->min_freq && rate <= v->max_freq) 701 return v; 702 703 return NULL; 704} 705 706static unsigned long 707clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 708{ 709 u32 l, low, high, ctl; 710 u64 a = 0, prate = parent_rate; 711 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 712 u32 alpha_width = pll_alpha_width(pll); 713 714 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 715 return 0; 716 717 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) 718 return 0; 719 720 if (ctl & PLL_ALPHA_EN) { 721 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low)) 722 return 0; 723 if (alpha_width > 32) { 724 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 725 &high)) 726 return 0; 727 a = (u64)high << 32 | low; 728 } else { 729 a = low & GENMASK(alpha_width - 1, 0); 730 } 731 732 if (alpha_width > ALPHA_BITWIDTH) 733 a >>= alpha_width - ALPHA_BITWIDTH; 734 } 735 736 return alpha_pll_calc_rate(prate, l, a, alpha_width); 737} 738 739 740static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll) 741{ 742 int ret; 743 u32 mode; 744 745 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode); 746 747 /* Latch the input to the PLL */ 748 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 749 PLL_UPDATE); 750 751 /* Wait for 2 reference cycle before checking ACK bit */ 752 udelay(1); 753 754 /* 755 * PLL will latch the new L, Alpha and freq control word. 756 * PLL will respond by raising PLL_ACK_LATCH output when new programming 757 * has been latched in and PLL is being updated. When 758 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared 759 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL. 760 */ 761 if (mode & PLL_UPDATE_BYPASS) { 762 ret = wait_for_pll_update_ack_set(pll); 763 if (ret) 764 return ret; 765 766 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0); 767 } else { 768 ret = wait_for_pll_update(pll); 769 if (ret) 770 return ret; 771 } 772 773 ret = wait_for_pll_update_ack_clear(pll); 774 if (ret) 775 return ret; 776 777 /* Wait for PLL output to stabilize */ 778 udelay(10); 779 780 return 0; 781} 782 783static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll, 784 int (*is_enabled)(struct clk_hw *)) 785{ 786 if (!is_enabled(&pll->clkr.hw) || 787 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE)) 788 return 0; 789 790 return __clk_alpha_pll_update_latch(pll); 791} 792 793static void clk_alpha_pll_update_configs(struct clk_alpha_pll *pll, const struct pll_vco *vco, 794 u32 l, u64 alpha, u32 alpha_width, bool alpha_en) 795{ 796 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 797 798 if (alpha_width > ALPHA_BITWIDTH) 799 alpha <<= alpha_width - ALPHA_BITWIDTH; 800 801 if (alpha_width > 32) 802 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), upper_32_bits(alpha)); 803 804 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), lower_32_bits(alpha)); 805 806 if (vco) { 807 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 808 PLL_VCO_MASK << PLL_VCO_SHIFT, 809 vco->val << PLL_VCO_SHIFT); 810 } 811 812 if (alpha_en) 813 regmap_set_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_ALPHA_EN); 814} 815 816static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 817 unsigned long prate, 818 int (*is_enabled)(struct clk_hw *)) 819{ 820 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 821 const struct pll_vco *vco; 822 u32 l, alpha_width = pll_alpha_width(pll); 823 u64 a; 824 825 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 826 vco = alpha_pll_find_vco(pll, rate); 827 if (pll->vco_table && !vco) { 828 pr_err("%s: alpha pll not in a valid vco range\n", 829 clk_hw_get_name(hw)); 830 return -EINVAL; 831 } 832 833 clk_alpha_pll_update_configs(pll, vco, l, a, alpha_width, true); 834 835 return clk_alpha_pll_update_latch(pll, is_enabled); 836} 837 838static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 839 unsigned long prate) 840{ 841 return __clk_alpha_pll_set_rate(hw, rate, prate, 842 clk_alpha_pll_is_enabled); 843} 844 845static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate, 846 unsigned long prate) 847{ 848 return __clk_alpha_pll_set_rate(hw, rate, prate, 849 clk_alpha_pll_hwfsm_is_enabled); 850} 851 852static int clk_alpha_pll_determine_rate(struct clk_hw *hw, 853 struct clk_rate_request *req) 854{ 855 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 856 u32 l, alpha_width = pll_alpha_width(pll); 857 u64 a; 858 unsigned long min_freq, max_freq; 859 860 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l, 861 &a, alpha_width); 862 if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate)) 863 return 0; 864 865 min_freq = pll->vco_table[0].min_freq; 866 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 867 868 req->rate = clamp(req->rate, min_freq, max_freq); 869 870 return 0; 871} 872 873void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 874 const struct alpha_pll_config *config) 875{ 876 u32 val; 877 878 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 879 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 880 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 881 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 882 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 883 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 884 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 885 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 886 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 887 888 /* Set PLL_BYPASSNL */ 889 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 890 regmap_read(regmap, PLL_MODE(pll), &val); 891 892 /* Wait 5 us between setting BYPASS and deasserting reset */ 893 udelay(5); 894 895 /* Take PLL out from reset state */ 896 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 897 regmap_read(regmap, PLL_MODE(pll), &val); 898 899 /* Wait 50us for PLL_LOCK_DET bit to go high */ 900 usleep_range(50, 55); 901 902 /* Enable PLL output */ 903 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 904} 905EXPORT_SYMBOL_GPL(clk_huayra_2290_pll_configure); 906 907static unsigned long 908alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a) 909{ 910 /* 911 * a contains 16 bit alpha_val in two’s complement number in the range 912 * of [-0.5, 0.5). 913 */ 914 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 915 l -= 1; 916 917 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH); 918} 919 920static unsigned long 921alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate, 922 u32 *l, u32 *a) 923{ 924 u64 remainder; 925 u64 quotient; 926 927 quotient = rate; 928 remainder = do_div(quotient, prate); 929 *l = quotient; 930 931 if (!remainder) { 932 *a = 0; 933 return rate; 934 } 935 936 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH; 937 remainder = do_div(quotient, prate); 938 939 if (remainder) 940 quotient++; 941 942 /* 943 * alpha_val should be in two’s complement number in the range 944 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value 945 * since alpha value will be subtracted in this case. 946 */ 947 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1)) 948 *l += 1; 949 950 *a = quotient; 951 return alpha_huayra_pll_calc_rate(prate, *l, *a); 952} 953 954static unsigned long 955alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 956{ 957 u64 rate = parent_rate, tmp; 958 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 959 u32 l, alpha = 0, ctl, alpha_m, alpha_n; 960 961 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 962 return 0; 963 964 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) 965 return 0; 966 967 if (ctl & PLL_ALPHA_EN) { 968 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha); 969 /* 970 * Depending upon alpha_mode, it can be treated as M/N value or 971 * as a two’s complement number. When alpha_mode=1, 972 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N 973 * 974 * Fout=FIN*(L+(M/N)) 975 * 976 * M is a signed number (-128 to 127) and N is unsigned 977 * (0 to 255). M/N has to be within +/-0.5. 978 * 979 * When alpha_mode=0, it is a two’s complement number in the 980 * range [-0.5, 0.5). 981 * 982 * Fout=FIN*(L+(alpha_val)/2^16) 983 * 984 * where alpha_val is two’s complement number. 985 */ 986 if (!(ctl & PLL_ALPHA_MODE)) 987 return alpha_huayra_pll_calc_rate(rate, l, alpha); 988 989 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK; 990 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK; 991 992 rate *= l; 993 tmp = parent_rate; 994 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) { 995 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m; 996 tmp *= alpha_m; 997 do_div(tmp, alpha_n); 998 rate -= tmp; 999 } else { 1000 tmp *= alpha_m; 1001 do_div(tmp, alpha_n); 1002 rate += tmp; 1003 } 1004 1005 return rate; 1006 } 1007 1008 return alpha_huayra_pll_calc_rate(rate, l, alpha); 1009} 1010 1011static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate, 1012 unsigned long prate) 1013{ 1014 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1015 u32 l, a, ctl, cur_alpha = 0; 1016 1017 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a); 1018 1019 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1020 1021 if (ctl & PLL_ALPHA_EN) 1022 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha); 1023 1024 /* 1025 * Huayra PLL supports PLL dynamic programming. User can change L_VAL, 1026 * without having to go through the power on sequence. 1027 */ 1028 if (clk_alpha_pll_is_enabled(hw)) { 1029 if (cur_alpha != a) { 1030 pr_err("%s: clock needs to be gated\n", 1031 clk_hw_get_name(hw)); 1032 return -EBUSY; 1033 } 1034 1035 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1036 /* Ensure that the write above goes to detect L val change. */ 1037 mb(); 1038 return wait_for_pll_enable_lock(pll); 1039 } 1040 1041 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1042 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1043 1044 if (a == 0) 1045 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1046 PLL_ALPHA_EN, 0x0); 1047 else 1048 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1049 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN); 1050 1051 return 0; 1052} 1053 1054static int alpha_pll_huayra_determine_rate(struct clk_hw *hw, 1055 struct clk_rate_request *req) 1056{ 1057 u32 l, a; 1058 1059 req->rate = alpha_huayra_pll_round_rate(req->rate, 1060 req->best_parent_rate, &l, &a); 1061 1062 return 0; 1063} 1064 1065static int trion_pll_is_enabled(struct clk_alpha_pll *pll, 1066 struct regmap *regmap) 1067{ 1068 u32 mode_val, opmode_val; 1069 int ret; 1070 1071 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val); 1072 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1073 if (ret) 1074 return 0; 1075 1076 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); 1077} 1078 1079static int clk_trion_pll_is_enabled(struct clk_hw *hw) 1080{ 1081 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1082 1083 return trion_pll_is_enabled(pll, pll->clkr.regmap); 1084} 1085 1086static int clk_trion_pll_enable(struct clk_hw *hw) 1087{ 1088 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1089 struct regmap *regmap = pll->clkr.regmap; 1090 u32 val; 1091 int ret; 1092 1093 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1094 if (ret) 1095 return ret; 1096 1097 /* If in FSM mode, just vote for it */ 1098 if (val & PLL_VOTE_FSM_ENA) { 1099 ret = clk_enable_regmap(hw); 1100 if (ret) 1101 return ret; 1102 return wait_for_pll_enable_active(pll); 1103 } 1104 1105 /* Set operation mode to RUN */ 1106 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1107 1108 ret = wait_for_pll_enable_lock(pll); 1109 if (ret) 1110 return ret; 1111 1112 /* Enable the PLL outputs */ 1113 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1114 PLL_OUT_MASK, PLL_OUT_MASK); 1115 if (ret) 1116 return ret; 1117 1118 /* Enable the global PLL outputs */ 1119 return regmap_update_bits(regmap, PLL_MODE(pll), 1120 PLL_OUTCTRL, PLL_OUTCTRL); 1121} 1122 1123static void clk_trion_pll_disable(struct clk_hw *hw) 1124{ 1125 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1126 struct regmap *regmap = pll->clkr.regmap; 1127 u32 val; 1128 int ret; 1129 1130 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1131 if (ret) 1132 return; 1133 1134 /* If in FSM mode, just unvote it */ 1135 if (val & PLL_VOTE_FSM_ENA) { 1136 clk_disable_regmap(hw); 1137 return; 1138 } 1139 1140 /* Disable the global PLL output */ 1141 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1142 if (ret) 1143 return; 1144 1145 /* Disable the PLL outputs */ 1146 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1147 PLL_OUT_MASK, 0); 1148 if (ret) 1149 return; 1150 1151 /* Place the PLL mode in STANDBY */ 1152 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1153 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1154} 1155 1156static unsigned long 1157clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1158{ 1159 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1160 u32 l, frac, alpha_width = pll_alpha_width(pll); 1161 1162 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 1163 return 0; 1164 1165 if (regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac)) 1166 return 0; 1167 1168 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1169} 1170 1171const struct clk_ops clk_alpha_pll_fixed_ops = { 1172 .enable = clk_alpha_pll_enable, 1173 .disable = clk_alpha_pll_disable, 1174 .is_enabled = clk_alpha_pll_is_enabled, 1175 .recalc_rate = clk_alpha_pll_recalc_rate, 1176}; 1177EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); 1178 1179const struct clk_ops clk_alpha_pll_ops = { 1180 .enable = clk_alpha_pll_enable, 1181 .disable = clk_alpha_pll_disable, 1182 .is_enabled = clk_alpha_pll_is_enabled, 1183 .recalc_rate = clk_alpha_pll_recalc_rate, 1184 .determine_rate = clk_alpha_pll_determine_rate, 1185 .set_rate = clk_alpha_pll_set_rate, 1186}; 1187EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); 1188 1189const struct clk_ops clk_alpha_pll_huayra_ops = { 1190 .enable = clk_alpha_pll_enable, 1191 .disable = clk_alpha_pll_disable, 1192 .is_enabled = clk_alpha_pll_is_enabled, 1193 .recalc_rate = alpha_pll_huayra_recalc_rate, 1194 .determine_rate = alpha_pll_huayra_determine_rate, 1195 .set_rate = alpha_pll_huayra_set_rate, 1196}; 1197EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); 1198 1199const struct clk_ops clk_alpha_pll_hwfsm_ops = { 1200 .enable = clk_alpha_pll_hwfsm_enable, 1201 .disable = clk_alpha_pll_hwfsm_disable, 1202 .is_enabled = clk_alpha_pll_hwfsm_is_enabled, 1203 .recalc_rate = clk_alpha_pll_recalc_rate, 1204 .determine_rate = clk_alpha_pll_determine_rate, 1205 .set_rate = clk_alpha_pll_hwfsm_set_rate, 1206}; 1207EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 1208 1209const struct clk_ops clk_alpha_pll_fixed_trion_ops = { 1210 .enable = clk_trion_pll_enable, 1211 .disable = clk_trion_pll_disable, 1212 .is_enabled = clk_trion_pll_is_enabled, 1213 .recalc_rate = clk_trion_pll_recalc_rate, 1214 .determine_rate = clk_alpha_pll_determine_rate, 1215}; 1216EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops); 1217 1218static unsigned long 1219clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1220{ 1221 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1222 u32 ctl; 1223 1224 if (regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl)) 1225 return 0; 1226 1227 ctl >>= PLL_POST_DIV_SHIFT; 1228 ctl &= PLL_POST_DIV_MASK(pll); 1229 1230 return parent_rate >> fls(ctl); 1231} 1232 1233static const struct clk_div_table clk_alpha_div_table[] = { 1234 { 0x0, 1 }, 1235 { 0x1, 2 }, 1236 { 0x3, 4 }, 1237 { 0x7, 8 }, 1238 { 0xf, 16 }, 1239 { } 1240}; 1241 1242static const struct clk_div_table clk_alpha_2bit_div_table[] = { 1243 { 0x0, 1 }, 1244 { 0x1, 2 }, 1245 { 0x3, 4 }, 1246 { } 1247}; 1248 1249static int clk_alpha_pll_postdiv_determine_rate(struct clk_hw *hw, 1250 struct clk_rate_request *req) 1251{ 1252 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1253 const struct clk_div_table *table; 1254 1255 if (pll->width == 2) 1256 table = clk_alpha_2bit_div_table; 1257 else 1258 table = clk_alpha_div_table; 1259 1260 return divider_determine_rate(hw, req, table, pll->width, 1261 CLK_DIVIDER_POWER_OF_TWO); 1262} 1263 1264static int clk_alpha_pll_postdiv_ro_determine_rate(struct clk_hw *hw, 1265 struct clk_rate_request *req) 1266{ 1267 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1268 u32 ctl, div; 1269 1270 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); 1271 1272 ctl >>= PLL_POST_DIV_SHIFT; 1273 ctl &= BIT(pll->width) - 1; 1274 div = 1 << fls(ctl); 1275 1276 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) 1277 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1278 div * req->rate); 1279 1280 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); 1281 1282 return 0; 1283} 1284 1285static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1286 unsigned long parent_rate) 1287{ 1288 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1289 int div; 1290 1291 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 1292 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1; 1293 1294 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1295 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 1296 div << PLL_POST_DIV_SHIFT); 1297} 1298 1299const struct clk_ops clk_alpha_pll_postdiv_ops = { 1300 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1301 .determine_rate = clk_alpha_pll_postdiv_determine_rate, 1302 .set_rate = clk_alpha_pll_postdiv_set_rate, 1303}; 1304EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops); 1305 1306const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 1307 .determine_rate = clk_alpha_pll_postdiv_ro_determine_rate, 1308 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate, 1309}; 1310EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops); 1311 1312void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1313 const struct alpha_pll_config *config) 1314{ 1315 u32 val, mask; 1316 1317 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1318 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha); 1319 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1320 config->config_ctl_val); 1321 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1322 config->config_ctl_hi_val); 1323 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1324 config->user_ctl_val); 1325 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1326 config->user_ctl_hi_val); 1327 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1328 config->test_ctl_val); 1329 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1330 config->test_ctl_hi_val); 1331 1332 if (config->post_div_mask) { 1333 mask = config->post_div_mask; 1334 val = config->post_div_val; 1335 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 1336 } 1337 1338 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) 1339 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, 1340 PLL_FSM_LEGACY_MODE); 1341 1342 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1343 PLL_UPDATE_BYPASS); 1344 1345 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1346} 1347EXPORT_SYMBOL_GPL(clk_fabia_pll_configure); 1348 1349static int alpha_pll_fabia_enable(struct clk_hw *hw) 1350{ 1351 int ret; 1352 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1353 u32 val, opmode_val; 1354 struct regmap *regmap = pll->clkr.regmap; 1355 1356 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1357 if (ret) 1358 return ret; 1359 1360 /* If in FSM mode, just vote for it */ 1361 if (val & PLL_VOTE_FSM_ENA) { 1362 ret = clk_enable_regmap(hw); 1363 if (ret) 1364 return ret; 1365 return wait_for_pll_enable_active(pll); 1366 } 1367 1368 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val); 1369 if (ret) 1370 return ret; 1371 1372 /* Skip If PLL is already running */ 1373 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) 1374 return 0; 1375 1376 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1377 if (ret) 1378 return ret; 1379 1380 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1381 if (ret) 1382 return ret; 1383 1384 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 1385 PLL_RESET_N); 1386 if (ret) 1387 return ret; 1388 1389 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 1390 if (ret) 1391 return ret; 1392 1393 ret = wait_for_pll_enable_lock(pll); 1394 if (ret) 1395 return ret; 1396 1397 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), 1398 PLL_OUT_MASK, PLL_OUT_MASK); 1399 if (ret) 1400 return ret; 1401 1402 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 1403 PLL_OUTCTRL); 1404} 1405 1406static void alpha_pll_fabia_disable(struct clk_hw *hw) 1407{ 1408 int ret; 1409 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1410 u32 val; 1411 struct regmap *regmap = pll->clkr.regmap; 1412 1413 ret = regmap_read(regmap, PLL_MODE(pll), &val); 1414 if (ret) 1415 return; 1416 1417 /* If in FSM mode, just unvote it */ 1418 if (val & PLL_FSM_ENA) { 1419 clk_disable_regmap(hw); 1420 return; 1421 } 1422 1423 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1424 if (ret) 1425 return; 1426 1427 /* Disable main outputs */ 1428 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 1429 if (ret) 1430 return; 1431 1432 /* Place the PLL in STANDBY */ 1433 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1434} 1435 1436static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw, 1437 unsigned long parent_rate) 1438{ 1439 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1440 u32 l, frac, alpha_width = pll_alpha_width(pll); 1441 1442 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 1443 return 0; 1444 1445 if (regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac)) 1446 return 0; 1447 1448 return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width); 1449} 1450 1451/* 1452 * Due to limited number of bits for fractional rate programming, the 1453 * rounded up rate could be marginally higher than the requested rate. 1454 */ 1455static int alpha_pll_check_rate_margin(struct clk_hw *hw, 1456 unsigned long rrate, unsigned long rate) 1457{ 1458 unsigned long rate_margin = rate + PLL_RATE_MARGIN; 1459 1460 if (rrate > rate_margin || rrate < rate) { 1461 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n", 1462 clk_hw_get_name(hw), rrate, rate, rate_margin); 1463 return -EINVAL; 1464 } 1465 1466 return 0; 1467} 1468 1469static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 1470 unsigned long prate) 1471{ 1472 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1473 u32 l, alpha_width = pll_alpha_width(pll); 1474 unsigned long rrate; 1475 int ret; 1476 u64 a; 1477 1478 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1479 1480 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1481 if (ret < 0) 1482 return ret; 1483 1484 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1485 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a); 1486 1487 return __clk_alpha_pll_update_latch(pll); 1488} 1489 1490static int alpha_pll_fabia_prepare(struct clk_hw *hw) 1491{ 1492 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1493 const struct pll_vco *vco; 1494 struct clk_hw *parent_hw; 1495 unsigned long cal_freq, rrate; 1496 u32 cal_l, val, alpha_width = pll_alpha_width(pll); 1497 const char *name = clk_hw_get_name(hw); 1498 u64 a; 1499 int ret; 1500 1501 /* Check if calibration needs to be done i.e. PLL is in reset */ 1502 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1503 if (ret) 1504 return ret; 1505 1506 /* Return early if calibration is not needed. */ 1507 if (val & PLL_RESET_N) 1508 return 0; 1509 1510 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 1511 if (!vco) { 1512 pr_err("%s: alpha pll not in a valid vco range\n", name); 1513 return -EINVAL; 1514 } 1515 1516 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq + 1517 pll->vco_table[0].max_freq) * 54, 100); 1518 1519 parent_hw = clk_hw_get_parent(hw); 1520 if (!parent_hw) 1521 return -EINVAL; 1522 1523 rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw), 1524 &cal_l, &a, alpha_width); 1525 1526 ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq); 1527 if (ret < 0) 1528 return ret; 1529 1530 /* Setup PLL for calibration frequency */ 1531 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l); 1532 1533 /* Bringup the PLL at calibration frequency */ 1534 ret = clk_alpha_pll_enable(hw); 1535 if (ret) { 1536 pr_err("%s: alpha pll calibration failed\n", name); 1537 return ret; 1538 } 1539 1540 clk_alpha_pll_disable(hw); 1541 1542 return 0; 1543} 1544 1545const struct clk_ops clk_alpha_pll_fabia_ops = { 1546 .prepare = alpha_pll_fabia_prepare, 1547 .enable = alpha_pll_fabia_enable, 1548 .disable = alpha_pll_fabia_disable, 1549 .is_enabled = clk_alpha_pll_is_enabled, 1550 .set_rate = alpha_pll_fabia_set_rate, 1551 .recalc_rate = alpha_pll_fabia_recalc_rate, 1552 .determine_rate = clk_alpha_pll_determine_rate, 1553}; 1554EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); 1555 1556const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 1557 .enable = alpha_pll_fabia_enable, 1558 .disable = alpha_pll_fabia_disable, 1559 .is_enabled = clk_alpha_pll_is_enabled, 1560 .recalc_rate = alpha_pll_fabia_recalc_rate, 1561 .determine_rate = clk_alpha_pll_determine_rate, 1562}; 1563EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops); 1564 1565static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw, 1566 unsigned long parent_rate) 1567{ 1568 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1569 u32 i, div = 1, val; 1570 int ret; 1571 1572 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1573 if (ret) 1574 return ret; 1575 1576 val >>= pll->post_div_shift; 1577 val &= BIT(pll->width) - 1; 1578 1579 for (i = 0; i < pll->num_post_div; i++) { 1580 if (pll->post_div_table[i].val == val) { 1581 div = pll->post_div_table[i].div; 1582 break; 1583 } 1584 } 1585 1586 return (parent_rate / div); 1587} 1588 1589static unsigned long 1590clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 1591{ 1592 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1593 struct regmap *regmap = pll->clkr.regmap; 1594 u32 i, div = 1, val; 1595 1596 if (regmap_read(regmap, PLL_USER_CTL(pll), &val)) 1597 return 0; 1598 1599 val >>= pll->post_div_shift; 1600 val &= PLL_POST_DIV_MASK(pll); 1601 1602 for (i = 0; i < pll->num_post_div; i++) { 1603 if (pll->post_div_table[i].val == val) { 1604 div = pll->post_div_table[i].div; 1605 break; 1606 } 1607 } 1608 1609 return (parent_rate / div); 1610} 1611 1612static int clk_trion_pll_postdiv_determine_rate(struct clk_hw *hw, 1613 struct clk_rate_request *req) 1614{ 1615 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1616 1617 return divider_determine_rate(hw, req, pll->post_div_table, pll->width, 1618 CLK_DIVIDER_ROUND_CLOSEST); 1619}; 1620 1621static int 1622clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 1623 unsigned long parent_rate) 1624{ 1625 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1626 struct regmap *regmap = pll->clkr.regmap; 1627 int i, val = 0, div; 1628 1629 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1630 for (i = 0; i < pll->num_post_div; i++) { 1631 if (pll->post_div_table[i].div == div) { 1632 val = pll->post_div_table[i].val; 1633 break; 1634 } 1635 } 1636 1637 return regmap_update_bits(regmap, PLL_USER_CTL(pll), 1638 PLL_POST_DIV_MASK(pll) << pll->post_div_shift, 1639 val << pll->post_div_shift); 1640} 1641 1642const struct clk_ops clk_alpha_pll_postdiv_trion_ops = { 1643 .recalc_rate = clk_trion_pll_postdiv_recalc_rate, 1644 .determine_rate = clk_trion_pll_postdiv_determine_rate, 1645 .set_rate = clk_trion_pll_postdiv_set_rate, 1646}; 1647EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops); 1648 1649static int clk_alpha_pll_postdiv_fabia_determine_rate(struct clk_hw *hw, 1650 struct clk_rate_request *req) 1651{ 1652 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1653 1654 return divider_determine_rate(hw, req, pll->post_div_table, pll->width, 1655 CLK_DIVIDER_ROUND_CLOSEST); 1656} 1657 1658static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw, 1659 unsigned long rate, unsigned long parent_rate) 1660{ 1661 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1662 int i, val = 0, div, ret; 1663 1664 /* 1665 * If the PLL is in FSM mode, then treat set_rate callback as a 1666 * no-operation. 1667 */ 1668 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1669 if (ret) 1670 return ret; 1671 1672 if (val & PLL_VOTE_FSM_ENA) 1673 return 0; 1674 1675 div = DIV_ROUND_UP_ULL(parent_rate, rate); 1676 for (i = 0; i < pll->num_post_div; i++) { 1677 if (pll->post_div_table[i].div == div) { 1678 val = pll->post_div_table[i].val; 1679 break; 1680 } 1681 } 1682 1683 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 1684 (BIT(pll->width) - 1) << pll->post_div_shift, 1685 val << pll->post_div_shift); 1686} 1687 1688const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = { 1689 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1690 .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate, 1691 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1692}; 1693EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops); 1694 1695/** 1696 * clk_trion_pll_configure - configure the trion pll 1697 * 1698 * @pll: clk alpha pll 1699 * @regmap: register map 1700 * @config: configuration to apply for pll 1701 */ 1702void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1703 const struct alpha_pll_config *config) 1704{ 1705 /* 1706 * If the bootloader left the PLL enabled it's likely that there are 1707 * RCGs that will lock up if we disable the PLL below. 1708 */ 1709 if (trion_pll_is_enabled(pll, regmap)) { 1710 pr_debug("Trion PLL is already enabled, skipping configuration\n"); 1711 return; 1712 } 1713 1714 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1715 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1716 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1717 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1718 config->config_ctl_val); 1719 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1720 config->config_ctl_hi_val); 1721 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1722 config->config_ctl_hi1_val); 1723 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1724 config->user_ctl_val); 1725 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1726 config->user_ctl_hi_val); 1727 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1728 config->user_ctl_hi1_val); 1729 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1730 config->test_ctl_val); 1731 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1732 config->test_ctl_hi_val); 1733 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1734 config->test_ctl_hi1_val); 1735 1736 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS, 1737 PLL_UPDATE_BYPASS); 1738 1739 /* Disable PLL output */ 1740 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1741 1742 /* Set operation mode to OFF */ 1743 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1744 1745 /* Place the PLL in STANDBY mode */ 1746 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1747} 1748EXPORT_SYMBOL_GPL(clk_trion_pll_configure); 1749 1750/* 1751 * The TRION PLL requires a power-on self-calibration which happens when the 1752 * PLL comes out of reset. Calibrate in case it is not completed. 1753 */ 1754static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) 1755{ 1756 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1757 u32 val; 1758 int ret; 1759 1760 /* Return early if calibration is not needed. */ 1761 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); 1762 if (val & pcal_done) 1763 return 0; 1764 1765 /* On/off to calibrate */ 1766 ret = clk_trion_pll_enable(hw); 1767 if (!ret) 1768 clk_trion_pll_disable(hw); 1769 1770 return ret; 1771} 1772 1773static int alpha_pll_trion_prepare(struct clk_hw *hw) 1774{ 1775 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE); 1776} 1777 1778static int alpha_pll_lucid_prepare(struct clk_hw *hw) 1779{ 1780 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE); 1781} 1782 1783static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1784 unsigned long prate, u32 latch_bit, u32 latch_ack) 1785{ 1786 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1787 unsigned long rrate; 1788 u32 val, l, alpha_width = pll_alpha_width(pll); 1789 u64 a; 1790 int ret; 1791 1792 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1793 1794 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1795 if (ret < 0) 1796 return ret; 1797 1798 regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l); 1799 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1800 1801 /* Latch the PLL input */ 1802 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit); 1803 if (ret) 1804 return ret; 1805 1806 /* Wait for 2 reference cycles before checking the ACK bit. */ 1807 udelay(1); 1808 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 1809 if (!(val & latch_ack)) { 1810 pr_err("Lucid PLL latch failed. Output may be unstable!\n"); 1811 return -EINVAL; 1812 } 1813 1814 /* Return the latch input to 0 */ 1815 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0); 1816 if (ret) 1817 return ret; 1818 1819 if (clk_hw_is_enabled(hw)) { 1820 ret = wait_for_pll_enable_lock(pll); 1821 if (ret) 1822 return ret; 1823 } 1824 1825 /* Wait for PLL output to stabilize */ 1826 udelay(100); 1827 return 0; 1828} 1829 1830static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 1831 unsigned long prate) 1832{ 1833 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH); 1834} 1835 1836const struct clk_ops clk_alpha_pll_trion_ops = { 1837 .prepare = alpha_pll_trion_prepare, 1838 .enable = clk_trion_pll_enable, 1839 .disable = clk_trion_pll_disable, 1840 .is_enabled = clk_trion_pll_is_enabled, 1841 .recalc_rate = clk_trion_pll_recalc_rate, 1842 .determine_rate = clk_alpha_pll_determine_rate, 1843 .set_rate = alpha_pll_trion_set_rate, 1844}; 1845EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); 1846 1847const struct clk_ops clk_alpha_pll_lucid_ops = { 1848 .prepare = alpha_pll_lucid_prepare, 1849 .enable = clk_trion_pll_enable, 1850 .disable = clk_trion_pll_disable, 1851 .is_enabled = clk_trion_pll_is_enabled, 1852 .recalc_rate = clk_trion_pll_recalc_rate, 1853 .determine_rate = clk_alpha_pll_determine_rate, 1854 .set_rate = alpha_pll_trion_set_rate, 1855}; 1856EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops); 1857 1858const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { 1859 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 1860 .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate, 1861 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, 1862}; 1863EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops); 1864 1865void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1866 const struct alpha_pll_config *config) 1867{ 1868 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1869 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1870 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1871 config->user_ctl_val); 1872 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1873 config->config_ctl_val); 1874 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1875 config->config_ctl_hi_val); 1876 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1877 config->test_ctl_val); 1878 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1879 config->test_ctl_hi_val); 1880} 1881EXPORT_SYMBOL_GPL(clk_agera_pll_configure); 1882 1883static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, 1884 unsigned long prate) 1885{ 1886 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1887 u32 l, alpha_width = pll_alpha_width(pll); 1888 int ret; 1889 unsigned long rrate; 1890 u64 a; 1891 1892 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 1893 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 1894 if (ret < 0) 1895 return ret; 1896 1897 /* change L_VAL without having to go through the power on sequence */ 1898 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 1899 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 1900 1901 if (clk_hw_is_enabled(hw)) 1902 return wait_for_pll_enable_lock(pll); 1903 1904 return 0; 1905} 1906 1907const struct clk_ops clk_alpha_pll_agera_ops = { 1908 .enable = clk_alpha_pll_enable, 1909 .disable = clk_alpha_pll_disable, 1910 .is_enabled = clk_alpha_pll_is_enabled, 1911 .recalc_rate = alpha_pll_fabia_recalc_rate, 1912 .determine_rate = clk_alpha_pll_determine_rate, 1913 .set_rate = clk_alpha_pll_agera_set_rate, 1914}; 1915EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops); 1916 1917/** 1918 * clk_lucid_5lpe_pll_configure - configure the lucid 5lpe pll 1919 * 1920 * @pll: clk alpha pll 1921 * @regmap: register map 1922 * @config: configuration to apply for pll 1923 */ 1924void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 1925 const struct alpha_pll_config *config) 1926{ 1927 /* 1928 * If the bootloader left the PLL enabled it's likely that there are 1929 * RCGs that will lock up if we disable the PLL below. 1930 */ 1931 if (trion_pll_is_enabled(pll, regmap)) { 1932 pr_debug("Lucid 5LPE PLL is already enabled, skipping configuration\n"); 1933 return; 1934 } 1935 1936 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 1937 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL); 1938 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 1939 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), 1940 config->config_ctl_val); 1941 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), 1942 config->config_ctl_hi_val); 1943 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), 1944 config->config_ctl_hi1_val); 1945 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 1946 config->user_ctl_val); 1947 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), 1948 config->user_ctl_hi_val); 1949 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), 1950 config->user_ctl_hi1_val); 1951 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), 1952 config->test_ctl_val); 1953 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), 1954 config->test_ctl_hi_val); 1955 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), 1956 config->test_ctl_hi1_val); 1957 1958 /* Disable PLL output */ 1959 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 1960 1961 /* Set operation mode to OFF */ 1962 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 1963 1964 /* Place the PLL in STANDBY mode */ 1965 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1966} 1967EXPORT_SYMBOL_GPL(clk_lucid_5lpe_pll_configure); 1968 1969static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) 1970{ 1971 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 1972 u32 val; 1973 int ret; 1974 1975 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1976 if (ret) 1977 return ret; 1978 1979 /* If in FSM mode, just vote for it */ 1980 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 1981 ret = clk_enable_regmap(hw); 1982 if (ret) 1983 return ret; 1984 return wait_for_pll_enable_lock(pll); 1985 } 1986 1987 /* Check if PLL is already enabled, return if enabled */ 1988 if (trion_pll_is_enabled(pll, pll->clkr.regmap)) 1989 return 0; 1990 1991 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 1992 if (ret) 1993 return ret; 1994 1995 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN); 1996 1997 ret = wait_for_pll_enable_lock(pll); 1998 if (ret) 1999 return ret; 2000 2001 /* Enable the PLL outputs */ 2002 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2003 if (ret) 2004 return ret; 2005 2006 /* Enable the global PLL outputs */ 2007 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2008} 2009 2010static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) 2011{ 2012 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2013 u32 val; 2014 int ret; 2015 2016 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 2017 if (ret) 2018 return; 2019 2020 /* If in FSM mode, just unvote it */ 2021 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) { 2022 clk_disable_regmap(hw); 2023 return; 2024 } 2025 2026 /* Disable the global PLL output */ 2027 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2028 if (ret) 2029 return; 2030 2031 /* Disable the PLL outputs */ 2032 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2033 if (ret) 2034 return; 2035 2036 /* Place the PLL mode in STANDBY */ 2037 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY); 2038} 2039 2040/* 2041 * The Lucid 5LPE PLL requires a power-on self-calibration which happens 2042 * when the PLL comes out of reset. Calibrate in case it is not completed. 2043 */ 2044static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) 2045{ 2046 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2047 struct clk_hw *p; 2048 u32 val = 0; 2049 int ret; 2050 2051 /* Return early if calibration is not needed. */ 2052 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2053 if (val & LUCID_5LPE_PCAL_DONE) 2054 return 0; 2055 2056 p = clk_hw_get_parent(hw); 2057 if (!p) 2058 return -EINVAL; 2059 2060 ret = alpha_pll_lucid_5lpe_enable(hw); 2061 if (ret) 2062 return ret; 2063 2064 alpha_pll_lucid_5lpe_disable(hw); 2065 2066 return 0; 2067} 2068 2069static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, 2070 unsigned long prate) 2071{ 2072 return __alpha_pll_trion_set_rate(hw, rate, prate, 2073 LUCID_5LPE_PLL_LATCH_INPUT, 2074 LUCID_5LPE_ALPHA_PLL_ACK_LATCH); 2075} 2076 2077static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2078 unsigned long parent_rate, 2079 unsigned long enable_vote_run) 2080{ 2081 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 2082 struct regmap *regmap = pll->clkr.regmap; 2083 int i, val, div, ret; 2084 u32 mask; 2085 2086 /* 2087 * If the PLL is in FSM mode, then treat set_rate callback as a 2088 * no-operation. 2089 */ 2090 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2091 if (ret) 2092 return ret; 2093 2094 if (val & enable_vote_run) 2095 return 0; 2096 2097 if (!pll->post_div_table) { 2098 pr_err("Missing the post_div_table for the %s PLL\n", 2099 clk_hw_get_name(&pll->clkr.hw)); 2100 return -EINVAL; 2101 } 2102 2103 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 2104 for (i = 0; i < pll->num_post_div; i++) { 2105 if (pll->post_div_table[i].div == div) { 2106 val = pll->post_div_table[i].val; 2107 break; 2108 } 2109 } 2110 2111 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift); 2112 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2113 mask, val << pll->post_div_shift); 2114} 2115 2116static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2117 unsigned long parent_rate) 2118{ 2119 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN); 2120} 2121 2122const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { 2123 .prepare = alpha_pll_lucid_5lpe_prepare, 2124 .enable = alpha_pll_lucid_5lpe_enable, 2125 .disable = alpha_pll_lucid_5lpe_disable, 2126 .is_enabled = clk_trion_pll_is_enabled, 2127 .recalc_rate = clk_trion_pll_recalc_rate, 2128 .determine_rate = clk_alpha_pll_determine_rate, 2129 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2130}; 2131EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops); 2132 2133const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { 2134 .enable = alpha_pll_lucid_5lpe_enable, 2135 .disable = alpha_pll_lucid_5lpe_disable, 2136 .is_enabled = clk_trion_pll_is_enabled, 2137 .recalc_rate = clk_trion_pll_recalc_rate, 2138 .determine_rate = clk_alpha_pll_determine_rate, 2139}; 2140EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops); 2141 2142const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = { 2143 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2144 .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate, 2145 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate, 2146}; 2147EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops); 2148 2149void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2150 const struct alpha_pll_config *config) 2151{ 2152 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2153 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2154 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2155 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2156 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2157 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2158 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2159 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 2160 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2161 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2162 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2163 2164 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0); 2165 2166 /* Disable PLL output */ 2167 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2168 2169 /* Set operation mode to OFF */ 2170 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2171 2172 /* Place the PLL in STANDBY mode */ 2173 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2174} 2175EXPORT_SYMBOL_GPL(clk_zonda_pll_configure); 2176 2177static int clk_zonda_pll_enable(struct clk_hw *hw) 2178{ 2179 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2180 struct regmap *regmap = pll->clkr.regmap; 2181 u32 val; 2182 int ret; 2183 2184 regmap_read(regmap, PLL_MODE(pll), &val); 2185 2186 /* If in FSM mode, just vote for it */ 2187 if (val & PLL_VOTE_FSM_ENA) { 2188 ret = clk_enable_regmap(hw); 2189 if (ret) 2190 return ret; 2191 return wait_for_pll_enable_active(pll); 2192 } 2193 2194 /* Get the PLL out of bypass mode */ 2195 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL); 2196 2197 /* 2198 * H/W requires a 1us delay between disabling the bypass and 2199 * de-asserting the reset. 2200 */ 2201 udelay(1); 2202 2203 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2204 2205 /* Set operation mode to RUN */ 2206 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2207 2208 regmap_read(regmap, PLL_TEST_CTL(pll), &val); 2209 2210 /* If cfa mode then poll for freq lock */ 2211 if (val & ZONDA_STAY_IN_CFA) 2212 ret = wait_for_zonda_pll_freq_lock(pll); 2213 else 2214 ret = wait_for_pll_enable_lock(pll); 2215 if (ret) 2216 return ret; 2217 2218 /* Enable the PLL outputs */ 2219 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK); 2220 2221 /* Enable the global PLL outputs */ 2222 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2223 2224 return 0; 2225} 2226 2227static void clk_zonda_pll_disable(struct clk_hw *hw) 2228{ 2229 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2230 struct regmap *regmap = pll->clkr.regmap; 2231 u32 val; 2232 2233 regmap_read(regmap, PLL_MODE(pll), &val); 2234 2235 /* If in FSM mode, just unvote it */ 2236 if (val & PLL_VOTE_FSM_ENA) { 2237 clk_disable_regmap(hw); 2238 return; 2239 } 2240 2241 /* Disable the global PLL output */ 2242 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2243 2244 /* Disable the PLL outputs */ 2245 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0); 2246 2247 /* Put the PLL in bypass and reset */ 2248 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0); 2249 2250 /* Place the PLL mode in OFF state */ 2251 regmap_write(regmap, PLL_OPMODE(pll), 0x0); 2252} 2253 2254static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l) 2255{ 2256 u64 remainder, quotient; 2257 2258 quotient = rate; 2259 remainder = do_div(quotient, prate); 2260 2261 *l = rate + (u32)(remainder * 2 >= prate); 2262} 2263 2264static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, 2265 unsigned long prate) 2266{ 2267 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2268 unsigned long rrate; 2269 u32 test_ctl_val; 2270 u32 l, alpha_width = pll_alpha_width(pll); 2271 u64 a; 2272 int ret; 2273 2274 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2275 2276 ret = alpha_pll_check_rate_margin(hw, rrate, rate); 2277 if (ret < 0) 2278 return ret; 2279 2280 if (a & PLL_ALPHA_MSB) 2281 zonda_pll_adjust_l_val(rate, prate, &l); 2282 2283 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2284 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2285 2286 if (!clk_hw_is_enabled(hw)) 2287 return 0; 2288 2289 /* Wait before polling for the frequency latch */ 2290 udelay(5); 2291 2292 /* Read stay in cfa mode */ 2293 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val); 2294 2295 /* If cfa mode then poll for freq lock */ 2296 if (test_ctl_val & ZONDA_STAY_IN_CFA) 2297 ret = wait_for_zonda_pll_freq_lock(pll); 2298 else 2299 ret = wait_for_pll_enable_lock(pll); 2300 if (ret) 2301 return ret; 2302 2303 /* Wait for PLL output to stabilize */ 2304 udelay(100); 2305 return 0; 2306} 2307 2308const struct clk_ops clk_alpha_pll_zonda_ops = { 2309 .enable = clk_zonda_pll_enable, 2310 .disable = clk_zonda_pll_disable, 2311 .is_enabled = clk_trion_pll_is_enabled, 2312 .recalc_rate = clk_trion_pll_recalc_rate, 2313 .determine_rate = clk_alpha_pll_determine_rate, 2314 .set_rate = clk_zonda_pll_set_rate, 2315}; 2316EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); 2317 2318void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2319 const struct alpha_pll_config *config) 2320{ 2321 u32 lval = config->l; 2322 2323 /* 2324 * If the bootloader left the PLL enabled it's likely that there are 2325 * RCGs that will lock up if we disable the PLL below. 2326 */ 2327 if (trion_pll_is_enabled(pll, regmap)) { 2328 pr_debug("Lucid Evo PLL is already enabled, skipping configuration\n"); 2329 return; 2330 } 2331 2332 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2333 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2334 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2335 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2336 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2337 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2338 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2339 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2340 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2341 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2342 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2343 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2344 2345 /* Disable PLL output */ 2346 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2347 2348 /* Set operation mode to STANDBY and de-assert the reset */ 2349 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2350 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2351} 2352EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure); 2353 2354void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2355 const struct alpha_pll_config *config) 2356{ 2357 u32 lval = config->l; 2358 2359 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT; 2360 lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT; 2361 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval); 2362 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2363 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2364 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2365 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2366 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2367 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2368 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2369 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2370 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2371 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2372 2373 /* Disable PLL output */ 2374 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2375 2376 /* Set operation mode to STANDBY and de-assert the reset */ 2377 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2378 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2379} 2380EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure); 2381 2382static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) 2383{ 2384 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2385 struct regmap *regmap = pll->clkr.regmap; 2386 u32 val; 2387 int ret; 2388 2389 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2390 if (ret) 2391 return ret; 2392 2393 /* If in FSM mode, just vote for it */ 2394 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2395 ret = clk_enable_regmap(hw); 2396 if (ret) 2397 return ret; 2398 return wait_for_pll_enable_lock(pll); 2399 } 2400 2401 /* Check if PLL is already enabled */ 2402 if (trion_pll_is_enabled(pll, regmap)) 2403 return 0; 2404 2405 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2406 if (ret) 2407 return ret; 2408 2409 /* Set operation mode to RUN */ 2410 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2411 2412 ret = wait_for_pll_enable_lock(pll); 2413 if (ret) 2414 return ret; 2415 2416 /* Enable the PLL outputs */ 2417 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK); 2418 if (ret) 2419 return ret; 2420 2421 /* Enable the global PLL outputs */ 2422 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2423 if (ret) 2424 return ret; 2425 2426 /* Ensure that the write above goes through before returning. */ 2427 mb(); 2428 return ret; 2429} 2430 2431static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) 2432{ 2433 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2434 struct regmap *regmap = pll->clkr.regmap; 2435 u32 val; 2436 int ret; 2437 2438 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val); 2439 if (ret) 2440 return; 2441 2442 /* If in FSM mode, just unvote it */ 2443 if (val & LUCID_EVO_ENABLE_VOTE_RUN) { 2444 clk_disable_regmap(hw); 2445 return; 2446 } 2447 2448 /* Disable the global PLL output */ 2449 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2450 if (ret) 2451 return; 2452 2453 /* Disable the PLL outputs */ 2454 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0); 2455 if (ret) 2456 return; 2457 2458 /* Place the PLL mode in STANDBY */ 2459 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2460 2461 if (reset) 2462 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); 2463} 2464 2465static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) 2466{ 2467 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2468 struct clk_hw *p; 2469 u32 val = 0; 2470 int ret; 2471 2472 /* Return early if calibration is not needed. */ 2473 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 2474 if (!(val & LUCID_EVO_PCAL_NOT_DONE)) 2475 return 0; 2476 2477 p = clk_hw_get_parent(hw); 2478 if (!p) 2479 return -EINVAL; 2480 2481 ret = alpha_pll_lucid_evo_enable(hw); 2482 if (ret) 2483 return ret; 2484 2485 _alpha_pll_lucid_evo_disable(hw, reset); 2486 2487 return 0; 2488} 2489 2490static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) 2491{ 2492 _alpha_pll_lucid_evo_disable(hw, false); 2493} 2494 2495static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) 2496{ 2497 return _alpha_pll_lucid_evo_prepare(hw, false); 2498} 2499 2500static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw) 2501{ 2502 _alpha_pll_lucid_evo_disable(hw, true); 2503} 2504 2505static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw) 2506{ 2507 return _alpha_pll_lucid_evo_prepare(hw, true); 2508} 2509 2510static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, 2511 unsigned long parent_rate) 2512{ 2513 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2514 struct regmap *regmap = pll->clkr.regmap; 2515 u32 l, frac; 2516 2517 if (regmap_read(regmap, PLL_L_VAL(pll), &l)) 2518 return 0; 2519 l &= LUCID_EVO_PLL_L_VAL_MASK; 2520 2521 if (regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac)) 2522 return 0; 2523 2524 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll)); 2525} 2526 2527static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 2528 unsigned long parent_rate) 2529{ 2530 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN); 2531} 2532 2533const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = { 2534 .enable = alpha_pll_lucid_evo_enable, 2535 .disable = alpha_pll_lucid_evo_disable, 2536 .is_enabled = clk_trion_pll_is_enabled, 2537 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2538 .determine_rate = clk_alpha_pll_determine_rate, 2539}; 2540EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops); 2541 2542const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = { 2543 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, 2544 .determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate, 2545 .set_rate = clk_lucid_evo_pll_postdiv_set_rate, 2546}; 2547EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops); 2548 2549const struct clk_ops clk_alpha_pll_lucid_evo_ops = { 2550 .prepare = alpha_pll_lucid_evo_prepare, 2551 .enable = alpha_pll_lucid_evo_enable, 2552 .disable = alpha_pll_lucid_evo_disable, 2553 .is_enabled = clk_trion_pll_is_enabled, 2554 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2555 .determine_rate = clk_alpha_pll_determine_rate, 2556 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2557}; 2558EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); 2559 2560const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = { 2561 .prepare = alpha_pll_reset_lucid_evo_prepare, 2562 .enable = alpha_pll_lucid_evo_enable, 2563 .disable = alpha_pll_reset_lucid_evo_disable, 2564 .is_enabled = clk_trion_pll_is_enabled, 2565 .recalc_rate = alpha_pll_lucid_evo_recalc_rate, 2566 .determine_rate = clk_alpha_pll_determine_rate, 2567 .set_rate = alpha_pll_lucid_5lpe_set_rate, 2568}; 2569EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); 2570 2571static int alpha_pll_pongo_elu_prepare(struct clk_hw *hw) 2572{ 2573 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2574 struct regmap *regmap = pll->clkr.regmap; 2575 int ret; 2576 2577 /* Enable PLL intially to one-time calibrate against XO. */ 2578 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2579 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2580 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_XO_PRESENT, PONGO_XO_PRESENT); 2581 2582 /* Set regmap for wait_for_pll() */ 2583 pll->clkr.regmap = regmap; 2584 ret = wait_for_pll_enable_lock(pll); 2585 if (ret) { 2586 /* Reverse calibration - disable PLL output */ 2587 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2588 return ret; 2589 } 2590 2591 /* Disable PLL after one-time calibration. */ 2592 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2593 2594 /* Select internally generated clock. */ 2595 regmap_update_bits(regmap, PLL_MODE(pll), PONGO_CLOCK_SELECT, 2596 PONGO_CLOCK_SELECT); 2597 2598 return 0; 2599} 2600 2601static int alpha_pll_pongo_elu_enable(struct clk_hw *hw) 2602{ 2603 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2604 struct regmap *regmap = pll->clkr.regmap; 2605 int ret; 2606 2607 /* Check if PLL is already enabled */ 2608 if (trion_pll_is_enabled(pll, regmap)) 2609 return 0; 2610 2611 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N); 2612 if (ret) 2613 return ret; 2614 2615 /* Set operation mode to RUN */ 2616 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN); 2617 2618 ret = wait_for_pll_enable_lock(pll); 2619 if (ret) 2620 return ret; 2621 2622 /* Enable the global PLL outputs */ 2623 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL); 2624 if (ret) 2625 return ret; 2626 2627 /* Ensure that the write above goes through before returning. */ 2628 mb(); 2629 2630 return ret; 2631} 2632 2633static void alpha_pll_pongo_elu_disable(struct clk_hw *hw) 2634{ 2635 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2636 struct regmap *regmap = pll->clkr.regmap; 2637 int ret; 2638 2639 /* Disable the global PLL output */ 2640 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2641 if (ret) 2642 return; 2643 2644 /* Place the PLL mode in STANDBY */ 2645 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2646} 2647 2648static unsigned long alpha_pll_pongo_elu_recalc_rate(struct clk_hw *hw, 2649 unsigned long parent_rate) 2650{ 2651 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2652 struct regmap *regmap = pll->clkr.regmap; 2653 u32 l; 2654 2655 if (regmap_read(regmap, PLL_L_VAL(pll), &l)) 2656 return 0; 2657 2658 l &= PONGO_PLL_L_VAL_MASK; 2659 2660 return alpha_pll_calc_rate(parent_rate, l, 0, pll_alpha_width(pll)); 2661} 2662 2663const struct clk_ops clk_alpha_pll_pongo_elu_ops = { 2664 .prepare = alpha_pll_pongo_elu_prepare, 2665 .enable = alpha_pll_pongo_elu_enable, 2666 .disable = alpha_pll_pongo_elu_disable, 2667 .recalc_rate = alpha_pll_pongo_elu_recalc_rate, 2668}; 2669EXPORT_SYMBOL_GPL(clk_alpha_pll_pongo_elu_ops); 2670 2671void clk_pongo_elu_pll_configure(struct clk_alpha_pll *pll, 2672 struct regmap *regmap, 2673 const struct alpha_pll_config *config) 2674{ 2675 u32 val; 2676 2677 regmap_update_bits(regmap, PLL_USER_CTL(pll), PONGO_PLL_OUT_MASK, 2678 PONGO_PLL_OUT_MASK); 2679 2680 if (trion_pll_is_enabled(pll, regmap)) 2681 return; 2682 2683 if (regmap_read(regmap, PLL_L_VAL(pll), &val)) 2684 return; 2685 val &= PONGO_PLL_L_VAL_MASK; 2686 if (val) 2687 return; 2688 2689 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2690 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2691 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2692 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2693 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2694 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U2(pll), config->config_ctl_hi2_val); 2695 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), 2696 config->user_ctl_val | PONGO_PLL_OUT_MASK); 2697 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2698 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2699 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2700 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2701 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val); 2702 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U3(pll), config->test_ctl_hi3_val); 2703 2704 /* Disable PLL output */ 2705 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); 2706} 2707EXPORT_SYMBOL_GPL(clk_pongo_elu_pll_configure); 2708 2709void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2710 const struct alpha_pll_config *config) 2711{ 2712 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2713 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2714 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2715 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2716 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2717 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2718 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2719 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2720 2721 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2722 2723 regmap_update_bits(regmap, PLL_MODE(pll), 2724 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL, 2725 PLL_RESET_N | PLL_BYPASSNL); 2726} 2727EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure); 2728 2729static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw, 2730 unsigned long parent_rate) 2731{ 2732 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2733 u32 l; 2734 2735 if (regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l)) 2736 return 0; 2737 2738 return parent_rate * l; 2739} 2740 2741static int clk_rivian_evo_pll_determine_rate(struct clk_hw *hw, 2742 struct clk_rate_request *req) 2743{ 2744 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2745 unsigned long min_freq, max_freq; 2746 u32 l; 2747 u64 a; 2748 2749 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l, 2750 &a, 0); 2751 if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate)) 2752 return 0; 2753 2754 min_freq = pll->vco_table[0].min_freq; 2755 max_freq = pll->vco_table[pll->num_vco - 1].max_freq; 2756 2757 req->rate = clamp(req->rate, min_freq, max_freq); 2758 2759 return 0; 2760} 2761 2762const struct clk_ops clk_alpha_pll_rivian_evo_ops = { 2763 .enable = alpha_pll_lucid_5lpe_enable, 2764 .disable = alpha_pll_lucid_5lpe_disable, 2765 .is_enabled = clk_trion_pll_is_enabled, 2766 .recalc_rate = clk_rivian_evo_pll_recalc_rate, 2767 .determine_rate = clk_rivian_evo_pll_determine_rate, 2768}; 2769EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); 2770 2771void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2772 const struct alpha_pll_config *config) 2773{ 2774 u32 val, val_u, mask, mask_u; 2775 2776 regmap_write(regmap, PLL_L_VAL(pll), config->l); 2777 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2778 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2779 2780 if (pll_has_64bit_config(pll)) 2781 regmap_write(regmap, PLL_CONFIG_CTL_U(pll), 2782 config->config_ctl_hi_val); 2783 2784 if (pll_alpha_width(pll) > 32) 2785 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); 2786 2787 val = config->main_output_mask; 2788 val |= config->aux_output_mask; 2789 val |= config->aux2_output_mask; 2790 val |= config->early_output_mask; 2791 val |= config->pre_div_val; 2792 val |= config->post_div_val; 2793 val |= config->vco_val; 2794 val |= config->alpha_en_mask; 2795 val |= config->alpha_mode_mask; 2796 2797 mask = config->main_output_mask; 2798 mask |= config->aux_output_mask; 2799 mask |= config->aux2_output_mask; 2800 mask |= config->early_output_mask; 2801 mask |= config->pre_div_mask; 2802 mask |= config->post_div_mask; 2803 mask |= config->vco_mask; 2804 mask |= config->alpha_en_mask; 2805 mask |= config->alpha_mode_mask; 2806 2807 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); 2808 2809 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ 2810 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT; 2811 val_u |= config->lock_det; 2812 2813 mask_u = config->status_mask; 2814 mask_u |= config->lock_det; 2815 2816 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); 2817 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2818 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2819 2820 if (pll->flags & SUPPORTS_FSM_MODE) 2821 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); 2822} 2823EXPORT_SYMBOL_GPL(clk_stromer_pll_configure); 2824 2825static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw, 2826 struct clk_rate_request *req) 2827{ 2828 u32 l; 2829 u64 a; 2830 2831 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, 2832 &l, &a, ALPHA_REG_BITWIDTH); 2833 2834 return 0; 2835} 2836 2837static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, 2838 unsigned long prate) 2839{ 2840 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2841 int ret; 2842 u32 l; 2843 u64 a; 2844 2845 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH); 2846 2847 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2848 2849 a <<= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH; 2850 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2851 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2852 a >> ALPHA_BITWIDTH); 2853 2854 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2855 PLL_ALPHA_EN, PLL_ALPHA_EN); 2856 2857 if (!clk_hw_is_enabled(hw)) 2858 return 0; 2859 2860 /* 2861 * Stromer PLL supports Dynamic programming. 2862 * It allows the PLL frequency to be changed on-the-fly without first 2863 * execution of a shutdown procedure followed by a bring up procedure. 2864 */ 2865 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 2866 PLL_UPDATE); 2867 2868 ret = wait_for_pll_update(pll); 2869 if (ret) 2870 return ret; 2871 2872 return wait_for_pll_enable_lock(pll); 2873} 2874 2875const struct clk_ops clk_alpha_pll_stromer_ops = { 2876 .enable = clk_alpha_pll_enable, 2877 .disable = clk_alpha_pll_disable, 2878 .is_enabled = clk_alpha_pll_is_enabled, 2879 .recalc_rate = clk_alpha_pll_recalc_rate, 2880 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2881 .set_rate = clk_alpha_pll_stromer_set_rate, 2882}; 2883EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops); 2884 2885static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw, 2886 unsigned long rate, 2887 unsigned long prate) 2888{ 2889 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 2890 u32 l, alpha_width = pll_alpha_width(pll); 2891 int ret, pll_mode; 2892 u64 a; 2893 2894 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); 2895 2896 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); 2897 if (ret) 2898 return ret; 2899 2900 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); 2901 2902 /* Delay of 2 output clock ticks required until output is disabled */ 2903 udelay(1); 2904 2905 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); 2906 2907 if (alpha_width > ALPHA_BITWIDTH) 2908 a <<= alpha_width - ALPHA_BITWIDTH; 2909 2910 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); 2911 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), 2912 a >> ALPHA_BITWIDTH); 2913 2914 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 2915 PLL_ALPHA_EN, PLL_ALPHA_EN); 2916 2917 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); 2918 2919 /* Wait five micro seconds or more */ 2920 udelay(5); 2921 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, 2922 PLL_RESET_N); 2923 2924 /* The lock time should be less than 50 micro seconds worst case */ 2925 usleep_range(50, 60); 2926 2927 ret = wait_for_pll_enable_lock(pll); 2928 if (ret) { 2929 pr_err("Wait for PLL enable lock failed [%s] %d\n", 2930 clk_hw_get_name(hw), ret); 2931 return ret; 2932 } 2933 2934 if (pll_mode & PLL_OUTCTRL) 2935 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 2936 PLL_OUTCTRL); 2937 2938 return 0; 2939} 2940 2941const struct clk_ops clk_alpha_pll_stromer_plus_ops = { 2942 .prepare = clk_alpha_pll_enable, 2943 .unprepare = clk_alpha_pll_disable, 2944 .is_enabled = clk_alpha_pll_is_enabled, 2945 .recalc_rate = clk_alpha_pll_recalc_rate, 2946 .determine_rate = clk_alpha_pll_stromer_determine_rate, 2947 .set_rate = clk_alpha_pll_stromer_plus_set_rate, 2948}; 2949EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops); 2950 2951void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 2952 const struct alpha_pll_config *config) 2953{ 2954 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l); 2955 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha); 2956 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); 2957 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val); 2958 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val); 2959 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val); 2960 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val); 2961 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val); 2962 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); 2963 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); 2964 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val); 2965 2966 /* Set operation mode to STANDBY */ 2967 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); 2968} 2969EXPORT_SYMBOL_GPL(clk_regera_pll_configure); 2970 2971const struct clk_ops clk_alpha_pll_regera_ops = { 2972 .enable = clk_zonda_pll_enable, 2973 .disable = clk_zonda_pll_disable, 2974 .is_enabled = clk_alpha_pll_is_enabled, 2975 .recalc_rate = clk_trion_pll_recalc_rate, 2976 .determine_rate = clk_alpha_pll_determine_rate, 2977 .set_rate = clk_zonda_pll_set_rate, 2978}; 2979EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops); 2980 2981void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap) 2982{ 2983 const struct clk_init_data *init = pll->clkr.hw.init; 2984 2985 switch (GET_PLL_TYPE(pll)) { 2986 case CLK_ALPHA_PLL_TYPE_LUCID_OLE: 2987 clk_lucid_ole_pll_configure(pll, regmap, pll->config); 2988 break; 2989 case CLK_ALPHA_PLL_TYPE_LUCID_EVO: 2990 clk_lucid_evo_pll_configure(pll, regmap, pll->config); 2991 break; 2992 case CLK_ALPHA_PLL_TYPE_TAYCAN_ELU: 2993 clk_taycan_elu_pll_configure(pll, regmap, pll->config); 2994 break; 2995 case CLK_ALPHA_PLL_TYPE_RIVIAN_EVO: 2996 clk_rivian_evo_pll_configure(pll, regmap, pll->config); 2997 break; 2998 case CLK_ALPHA_PLL_TYPE_TRION: 2999 clk_trion_pll_configure(pll, regmap, pll->config); 3000 break; 3001 case CLK_ALPHA_PLL_TYPE_HUAYRA_2290: 3002 clk_huayra_2290_pll_configure(pll, regmap, pll->config); 3003 break; 3004 case CLK_ALPHA_PLL_TYPE_FABIA: 3005 clk_fabia_pll_configure(pll, regmap, pll->config); 3006 break; 3007 case CLK_ALPHA_PLL_TYPE_AGERA: 3008 clk_agera_pll_configure(pll, regmap, pll->config); 3009 break; 3010 case CLK_ALPHA_PLL_TYPE_PONGO_ELU: 3011 clk_pongo_elu_pll_configure(pll, regmap, pll->config); 3012 break; 3013 case CLK_ALPHA_PLL_TYPE_ZONDA: 3014 case CLK_ALPHA_PLL_TYPE_ZONDA_OLE: 3015 clk_zonda_pll_configure(pll, regmap, pll->config); 3016 break; 3017 case CLK_ALPHA_PLL_TYPE_STROMER: 3018 case CLK_ALPHA_PLL_TYPE_STROMER_PLUS: 3019 clk_stromer_pll_configure(pll, regmap, pll->config); 3020 break; 3021 case CLK_ALPHA_PLL_TYPE_DEFAULT: 3022 case CLK_ALPHA_PLL_TYPE_DEFAULT_EVO: 3023 case CLK_ALPHA_PLL_TYPE_HUAYRA: 3024 case CLK_ALPHA_PLL_TYPE_HUAYRA_APSS: 3025 case CLK_ALPHA_PLL_TYPE_BRAMMO: 3026 case CLK_ALPHA_PLL_TYPE_BRAMMO_EVO: 3027 clk_alpha_pll_configure(pll, regmap, pll->config); 3028 break; 3029 default: 3030 WARN(1, "%s: invalid pll type\n", init->name); 3031 break; 3032 } 3033} 3034EXPORT_SYMBOL_GPL(qcom_clk_alpha_pll_configure); 3035 3036static int clk_alpha_pll_slew_update(struct clk_alpha_pll *pll) 3037{ 3038 u32 val; 3039 int ret; 3040 3041 regmap_set_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE); 3042 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); 3043 3044 ret = wait_for_pll_update(pll); 3045 if (ret) 3046 return ret; 3047 /* 3048 * Hardware programming mandates a wait of at least 570ns before polling the LOCK 3049 * detect bit. Have a delay of 1us just to be safe. 3050 */ 3051 udelay(1); 3052 3053 return wait_for_pll_enable_lock(pll); 3054} 3055 3056static int clk_alpha_pll_slew_set_rate(struct clk_hw *hw, unsigned long rate, 3057 unsigned long parent_rate) 3058{ 3059 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 3060 const struct pll_vco *curr_vco, *vco; 3061 unsigned long freq_hz; 3062 u64 a; 3063 u32 l; 3064 3065 freq_hz = alpha_pll_round_rate(rate, parent_rate, &l, &a, ALPHA_REG_BITWIDTH); 3066 if (freq_hz != rate) { 3067 pr_err("alpha_pll: Call clk_set_rate with rounded rates!\n"); 3068 return -EINVAL; 3069 } 3070 3071 curr_vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 3072 if (!curr_vco) { 3073 pr_err("alpha pll: not in a valid vco range\n"); 3074 return -EINVAL; 3075 } 3076 3077 vco = alpha_pll_find_vco(pll, freq_hz); 3078 if (!vco) { 3079 pr_err("alpha pll: not in a valid vco range\n"); 3080 return -EINVAL; 3081 } 3082 3083 /* 3084 * Dynamic pll update will not support switching frequencies across 3085 * vco ranges. In those cases fall back to normal alpha set rate. 3086 */ 3087 if (curr_vco->val != vco->val) 3088 return clk_alpha_pll_set_rate(hw, rate, parent_rate); 3089 3090 clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, false); 3091 3092 /* Ensure that the write above goes before slewing the PLL */ 3093 mb(); 3094 3095 if (clk_hw_is_enabled(hw)) 3096 return clk_alpha_pll_slew_update(pll); 3097 3098 return 0; 3099} 3100 3101/* 3102 * Slewing plls should be bought up at frequency which is in the middle of the 3103 * desired VCO range. So after bringing up the pll at calibration freq, set it 3104 * back to desired frequency(that was set by previous clk_set_rate). 3105 */ 3106static int clk_alpha_pll_calibrate(struct clk_hw *hw) 3107{ 3108 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); 3109 struct clk_hw *parent; 3110 const struct pll_vco *vco; 3111 unsigned long calibration_freq, freq_hz; 3112 u64 a; 3113 u32 l; 3114 int rc; 3115 3116 parent = clk_hw_get_parent(hw); 3117 if (!parent) { 3118 pr_err("alpha pll: no valid parent found\n"); 3119 return -EINVAL; 3120 } 3121 3122 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw)); 3123 if (!vco) { 3124 pr_err("alpha pll: not in a valid vco range\n"); 3125 return -EINVAL; 3126 } 3127 3128 /* 3129 * As during slewing plls vco_sel won't be allowed to change, vco table 3130 * should have only one entry table, i.e. index = 0, find the 3131 * calibration frequency. 3132 */ 3133 calibration_freq = (pll->vco_table[0].min_freq + pll->vco_table[0].max_freq) / 2; 3134 3135 freq_hz = alpha_pll_round_rate(calibration_freq, clk_hw_get_rate(parent), 3136 &l, &a, ALPHA_REG_BITWIDTH); 3137 if (freq_hz != calibration_freq) { 3138 pr_err("alpha_pll: call clk_set_rate with rounded rates!\n"); 3139 return -EINVAL; 3140 } 3141 3142 clk_alpha_pll_update_configs(pll, vco, l, a, ALPHA_REG_BITWIDTH, false); 3143 3144 /* Bringup the pll at calibration frequency */ 3145 rc = clk_alpha_pll_enable(hw); 3146 if (rc) { 3147 pr_err("alpha pll calibration failed\n"); 3148 return rc; 3149 } 3150 3151 /* 3152 * PLL is already running at calibration frequency. 3153 * So slew pll to the previously set frequency. 3154 */ 3155 freq_hz = alpha_pll_round_rate(clk_hw_get_rate(hw), 3156 clk_hw_get_rate(parent), &l, &a, ALPHA_REG_BITWIDTH); 3157 3158 pr_debug("pll %s: setting back to required rate %lu, freq_hz %ld\n", 3159 clk_hw_get_name(hw), clk_hw_get_rate(hw), freq_hz); 3160 3161 clk_alpha_pll_update_configs(pll, NULL, l, a, ALPHA_REG_BITWIDTH, true); 3162 3163 return clk_alpha_pll_slew_update(pll); 3164} 3165 3166static int clk_alpha_pll_slew_enable(struct clk_hw *hw) 3167{ 3168 int rc; 3169 3170 rc = clk_alpha_pll_calibrate(hw); 3171 if (rc) 3172 return rc; 3173 3174 return clk_alpha_pll_enable(hw); 3175} 3176 3177const struct clk_ops clk_alpha_pll_slew_ops = { 3178 .enable = clk_alpha_pll_slew_enable, 3179 .disable = clk_alpha_pll_disable, 3180 .recalc_rate = clk_alpha_pll_recalc_rate, 3181 .determine_rate = clk_alpha_pll_determine_rate, 3182 .set_rate = clk_alpha_pll_slew_set_rate, 3183}; 3184EXPORT_SYMBOL(clk_alpha_pll_slew_ops);
~/
Read-only file preview.