camcc-sm8650.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/mod_devicetable.h>
   8#include <linux/module.h>
   9#include <linux/platform_device.h>
  10#include <linux/regmap.h>
  11
  12#include <dt-bindings/clock/qcom,sm8650-camcc.h>
  13
  14#include "clk-alpha-pll.h"
  15#include "clk-branch.h"
  16#include "clk-rcg.h"
  17#include "clk-regmap.h"
  18#include "common.h"
  19#include "gdsc.h"
  20#include "reset.h"
  21
  22enum {
  23	DT_IFACE,
  24	DT_BI_TCXO,
  25	DT_BI_TCXO_AO,
  26	DT_SLEEP_CLK,
  27};
  28
  29enum {
  30	P_BI_TCXO,
  31	P_BI_TCXO_AO,
  32	P_CAM_CC_PLL0_OUT_EVEN,
  33	P_CAM_CC_PLL0_OUT_MAIN,
  34	P_CAM_CC_PLL0_OUT_ODD,
  35	P_CAM_CC_PLL1_OUT_EVEN,
  36	P_CAM_CC_PLL2_OUT_EVEN,
  37	P_CAM_CC_PLL2_OUT_MAIN,
  38	P_CAM_CC_PLL3_OUT_EVEN,
  39	P_CAM_CC_PLL4_OUT_EVEN,
  40	P_CAM_CC_PLL5_OUT_EVEN,
  41	P_CAM_CC_PLL6_OUT_EVEN,
  42	P_CAM_CC_PLL7_OUT_EVEN,
  43	P_CAM_CC_PLL8_OUT_EVEN,
  44	P_CAM_CC_PLL9_OUT_EVEN,
  45	P_CAM_CC_PLL9_OUT_ODD,
  46	P_CAM_CC_PLL10_OUT_EVEN,
  47	P_SLEEP_CLK,
  48};
  49
  50static const struct pll_vco lucid_ole_vco[] = {
  51	{ 249600000, 2300000000, 0 },
  52};
  53
  54static const struct pll_vco rivian_ole_vco[] = {
  55	{ 777000000, 1285000000, 0 },
  56};
  57
  58static const struct alpha_pll_config cam_cc_pll0_config = {
  59	.l = 0x3e,
  60	.alpha = 0x8000,
  61	.config_ctl_val = 0x20485699,
  62	.config_ctl_hi_val = 0x00182261,
  63	.config_ctl_hi1_val = 0x82aa299c,
  64	.test_ctl_val = 0x00000000,
  65	.test_ctl_hi_val = 0x00000003,
  66	.test_ctl_hi1_val = 0x00009000,
  67	.test_ctl_hi2_val = 0x00000034,
  68	.user_ctl_val = 0x00008400,
  69	.user_ctl_hi_val = 0x00000005,
  70};
  71
  72static struct clk_alpha_pll cam_cc_pll0 = {
  73	.offset = 0x0,
  74	.config = &cam_cc_pll0_config,
  75	.vco_table = lucid_ole_vco,
  76	.num_vco = ARRAY_SIZE(lucid_ole_vco),
  77	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
  78	.clkr = {
  79		.hw.init = &(const struct clk_init_data) {
  80			.name = "cam_cc_pll0",
  81			.parent_data = &(const struct clk_parent_data) {
  82				.index = DT_BI_TCXO,
  83			},
  84			.num_parents = 1,
  85			.ops = &clk_alpha_pll_lucid_evo_ops,
  86		},
  87	},
  88};
  89
  90static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
  91	{ 0x1, 2 },
  92	{ }
  93};
  94
  95static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
  96	.offset = 0x0,
  97	.post_div_shift = 10,
  98	.post_div_table = post_div_table_cam_cc_pll0_out_even,
  99	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
 100	.width = 4,
 101	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 102	.clkr.hw.init = &(const struct clk_init_data) {
 103		.name = "cam_cc_pll0_out_even",
 104		.parent_hws = (const struct clk_hw*[]) {
 105			&cam_cc_pll0.clkr.hw,
 106		},
 107		.num_parents = 1,
 108		.flags = CLK_SET_RATE_PARENT,
 109		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 110	},
 111};
 112
 113static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
 114	{ 0x2, 3 },
 115	{ }
 116};
 117
 118static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
 119	.offset = 0x0,
 120	.post_div_shift = 14,
 121	.post_div_table = post_div_table_cam_cc_pll0_out_odd,
 122	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
 123	.width = 4,
 124	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 125	.clkr.hw.init = &(const struct clk_init_data) {
 126		.name = "cam_cc_pll0_out_odd",
 127		.parent_hws = (const struct clk_hw*[]) {
 128			&cam_cc_pll0.clkr.hw,
 129		},
 130		.num_parents = 1,
 131		.flags = CLK_SET_RATE_PARENT,
 132		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 133	},
 134};
 135
 136static const struct alpha_pll_config cam_cc_pll1_config = {
 137	.l = 0x31,
 138	.alpha = 0x7aaa,
 139	.config_ctl_val = 0x20485699,
 140	.config_ctl_hi_val = 0x00182261,
 141	.config_ctl_hi1_val = 0x82aa299c,
 142	.test_ctl_val = 0x00000000,
 143	.test_ctl_hi_val = 0x00000003,
 144	.test_ctl_hi1_val = 0x00009000,
 145	.test_ctl_hi2_val = 0x00000034,
 146	.user_ctl_val = 0x00000400,
 147	.user_ctl_hi_val = 0x00000005,
 148};
 149
 150static struct clk_alpha_pll cam_cc_pll1 = {
 151	.offset = 0x1000,
 152	.config = &cam_cc_pll1_config,
 153	.vco_table = lucid_ole_vco,
 154	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 155	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 156	.clkr = {
 157		.hw.init = &(const struct clk_init_data) {
 158			.name = "cam_cc_pll1",
 159			.parent_data = &(const struct clk_parent_data) {
 160				.index = DT_BI_TCXO,
 161			},
 162			.num_parents = 1,
 163			.ops = &clk_alpha_pll_lucid_evo_ops,
 164		},
 165	},
 166};
 167
 168static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
 169	{ 0x1, 2 },
 170	{ }
 171};
 172
 173static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
 174	.offset = 0x1000,
 175	.post_div_shift = 10,
 176	.post_div_table = post_div_table_cam_cc_pll1_out_even,
 177	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
 178	.width = 4,
 179	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 180	.clkr.hw.init = &(const struct clk_init_data) {
 181		.name = "cam_cc_pll1_out_even",
 182		.parent_hws = (const struct clk_hw*[]) {
 183			&cam_cc_pll1.clkr.hw,
 184		},
 185		.num_parents = 1,
 186		.flags = CLK_SET_RATE_PARENT,
 187		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 188	},
 189};
 190
 191static const struct alpha_pll_config cam_cc_pll2_config = {
 192	.l = 0x32,
 193	.alpha = 0x0,
 194	.config_ctl_val = 0x10000030,
 195	.config_ctl_hi_val = 0x80890263,
 196	.config_ctl_hi1_val = 0x00000217,
 197	.user_ctl_val = 0x00000001,
 198	.user_ctl_hi_val = 0x00000000,
 199};
 200
 201static struct clk_alpha_pll cam_cc_pll2 = {
 202	.offset = 0x2000,
 203	.config = &cam_cc_pll2_config,
 204	.vco_table = rivian_ole_vco,
 205	.num_vco = ARRAY_SIZE(rivian_ole_vco),
 206	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
 207	.clkr = {
 208		.hw.init = &(const struct clk_init_data) {
 209			.name = "cam_cc_pll2",
 210			.parent_data = &(const struct clk_parent_data) {
 211				.index = DT_BI_TCXO,
 212			},
 213			.num_parents = 1,
 214			.ops = &clk_alpha_pll_rivian_evo_ops,
 215		},
 216	},
 217};
 218
 219static const struct alpha_pll_config cam_cc_pll3_config = {
 220	.l = 0x30,
 221	.alpha = 0x8aaa,
 222	.config_ctl_val = 0x20485699,
 223	.config_ctl_hi_val = 0x00182261,
 224	.config_ctl_hi1_val = 0x82aa299c,
 225	.test_ctl_val = 0x00000000,
 226	.test_ctl_hi_val = 0x00000003,
 227	.test_ctl_hi1_val = 0x00009000,
 228	.test_ctl_hi2_val = 0x00000034,
 229	.user_ctl_val = 0x00000400,
 230	.user_ctl_hi_val = 0x00000005,
 231};
 232
 233static struct clk_alpha_pll cam_cc_pll3 = {
 234	.offset = 0x3000,
 235	.config = &cam_cc_pll3_config,
 236	.vco_table = lucid_ole_vco,
 237	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 238	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 239	.clkr = {
 240		.hw.init = &(const struct clk_init_data) {
 241			.name = "cam_cc_pll3",
 242			.parent_data = &(const struct clk_parent_data) {
 243				.index = DT_BI_TCXO,
 244			},
 245			.num_parents = 1,
 246			.ops = &clk_alpha_pll_lucid_evo_ops,
 247		},
 248	},
 249};
 250
 251static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
 252	{ 0x1, 2 },
 253	{ }
 254};
 255
 256static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
 257	.offset = 0x3000,
 258	.post_div_shift = 10,
 259	.post_div_table = post_div_table_cam_cc_pll3_out_even,
 260	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
 261	.width = 4,
 262	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 263	.clkr.hw.init = &(const struct clk_init_data) {
 264		.name = "cam_cc_pll3_out_even",
 265		.parent_hws = (const struct clk_hw*[]) {
 266			&cam_cc_pll3.clkr.hw,
 267		},
 268		.num_parents = 1,
 269		.flags = CLK_SET_RATE_PARENT,
 270		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 271	},
 272};
 273
 274static const struct alpha_pll_config cam_cc_pll4_config = {
 275	.l = 0x30,
 276	.alpha = 0x8aaa,
 277	.config_ctl_val = 0x20485699,
 278	.config_ctl_hi_val = 0x00182261,
 279	.config_ctl_hi1_val = 0x82aa299c,
 280	.test_ctl_val = 0x00000000,
 281	.test_ctl_hi_val = 0x00000003,
 282	.test_ctl_hi1_val = 0x00009000,
 283	.test_ctl_hi2_val = 0x00000034,
 284	.user_ctl_val = 0x00000400,
 285	.user_ctl_hi_val = 0x00000005,
 286};
 287
 288static struct clk_alpha_pll cam_cc_pll4 = {
 289	.offset = 0x4000,
 290	.config = &cam_cc_pll4_config,
 291	.vco_table = lucid_ole_vco,
 292	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 293	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 294	.clkr = {
 295		.hw.init = &(const struct clk_init_data) {
 296			.name = "cam_cc_pll4",
 297			.parent_data = &(const struct clk_parent_data) {
 298				.index = DT_BI_TCXO,
 299			},
 300			.num_parents = 1,
 301			.ops = &clk_alpha_pll_lucid_evo_ops,
 302		},
 303	},
 304};
 305
 306static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
 307	{ 0x1, 2 },
 308	{ }
 309};
 310
 311static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
 312	.offset = 0x4000,
 313	.post_div_shift = 10,
 314	.post_div_table = post_div_table_cam_cc_pll4_out_even,
 315	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
 316	.width = 4,
 317	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 318	.clkr.hw.init = &(const struct clk_init_data) {
 319		.name = "cam_cc_pll4_out_even",
 320		.parent_hws = (const struct clk_hw*[]) {
 321			&cam_cc_pll4.clkr.hw,
 322		},
 323		.num_parents = 1,
 324		.flags = CLK_SET_RATE_PARENT,
 325		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 326	},
 327};
 328
 329static const struct alpha_pll_config cam_cc_pll5_config = {
 330	.l = 0x30,
 331	.alpha = 0x8aaa,
 332	.config_ctl_val = 0x20485699,
 333	.config_ctl_hi_val = 0x00182261,
 334	.config_ctl_hi1_val = 0x82aa299c,
 335	.test_ctl_val = 0x00000000,
 336	.test_ctl_hi_val = 0x00000003,
 337	.test_ctl_hi1_val = 0x00009000,
 338	.test_ctl_hi2_val = 0x00000034,
 339	.user_ctl_val = 0x00000400,
 340	.user_ctl_hi_val = 0x00000005,
 341};
 342
 343static struct clk_alpha_pll cam_cc_pll5 = {
 344	.offset = 0x5000,
 345	.config = &cam_cc_pll5_config,
 346	.vco_table = lucid_ole_vco,
 347	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 348	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 349	.clkr = {
 350		.hw.init = &(const struct clk_init_data) {
 351			.name = "cam_cc_pll5",
 352			.parent_data = &(const struct clk_parent_data) {
 353				.index = DT_BI_TCXO,
 354			},
 355			.num_parents = 1,
 356			.ops = &clk_alpha_pll_lucid_evo_ops,
 357		},
 358	},
 359};
 360
 361static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
 362	{ 0x1, 2 },
 363	{ }
 364};
 365
 366static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
 367	.offset = 0x5000,
 368	.post_div_shift = 10,
 369	.post_div_table = post_div_table_cam_cc_pll5_out_even,
 370	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
 371	.width = 4,
 372	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 373	.clkr.hw.init = &(const struct clk_init_data) {
 374		.name = "cam_cc_pll5_out_even",
 375		.parent_hws = (const struct clk_hw*[]) {
 376			&cam_cc_pll5.clkr.hw,
 377		},
 378		.num_parents = 1,
 379		.flags = CLK_SET_RATE_PARENT,
 380		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 381	},
 382};
 383
 384static const struct alpha_pll_config cam_cc_pll6_config = {
 385	.l = 0x30,
 386	.alpha = 0x8aaa,
 387	.config_ctl_val = 0x20485699,
 388	.config_ctl_hi_val = 0x00182261,
 389	.config_ctl_hi1_val = 0x82aa299c,
 390	.test_ctl_val = 0x00000000,
 391	.test_ctl_hi_val = 0x00000003,
 392	.test_ctl_hi1_val = 0x00009000,
 393	.test_ctl_hi2_val = 0x00000034,
 394	.user_ctl_val = 0x00000400,
 395	.user_ctl_hi_val = 0x00000005,
 396};
 397
 398static struct clk_alpha_pll cam_cc_pll6 = {
 399	.offset = 0x6000,
 400	.config = &cam_cc_pll6_config,
 401	.vco_table = lucid_ole_vco,
 402	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 403	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 404	.clkr = {
 405		.hw.init = &(const struct clk_init_data) {
 406			.name = "cam_cc_pll6",
 407			.parent_data = &(const struct clk_parent_data) {
 408				.index = DT_BI_TCXO,
 409			},
 410			.num_parents = 1,
 411			.ops = &clk_alpha_pll_lucid_evo_ops,
 412		},
 413	},
 414};
 415
 416static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
 417	{ 0x1, 2 },
 418	{ }
 419};
 420
 421static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
 422	.offset = 0x6000,
 423	.post_div_shift = 10,
 424	.post_div_table = post_div_table_cam_cc_pll6_out_even,
 425	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
 426	.width = 4,
 427	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 428	.clkr.hw.init = &(const struct clk_init_data) {
 429		.name = "cam_cc_pll6_out_even",
 430		.parent_hws = (const struct clk_hw*[]) {
 431			&cam_cc_pll6.clkr.hw,
 432		},
 433		.num_parents = 1,
 434		.flags = CLK_SET_RATE_PARENT,
 435		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 436	},
 437};
 438
 439static const struct alpha_pll_config cam_cc_pll7_config = {
 440	.l = 0x30,
 441	.alpha = 0x8aaa,
 442	.config_ctl_val = 0x20485699,
 443	.config_ctl_hi_val = 0x00182261,
 444	.config_ctl_hi1_val = 0x82aa299c,
 445	.test_ctl_val = 0x00000000,
 446	.test_ctl_hi_val = 0x00000003,
 447	.test_ctl_hi1_val = 0x00009000,
 448	.test_ctl_hi2_val = 0x00000034,
 449	.user_ctl_val = 0x00000400,
 450	.user_ctl_hi_val = 0x00000005,
 451};
 452
 453static struct clk_alpha_pll cam_cc_pll7 = {
 454	.offset = 0x7000,
 455	.config = &cam_cc_pll7_config,
 456	.vco_table = lucid_ole_vco,
 457	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 458	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 459	.clkr = {
 460		.hw.init = &(const struct clk_init_data) {
 461			.name = "cam_cc_pll7",
 462			.parent_data = &(const struct clk_parent_data) {
 463				.index = DT_BI_TCXO,
 464			},
 465			.num_parents = 1,
 466			.ops = &clk_alpha_pll_lucid_evo_ops,
 467		},
 468	},
 469};
 470
 471static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
 472	{ 0x1, 2 },
 473	{ }
 474};
 475
 476static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
 477	.offset = 0x7000,
 478	.post_div_shift = 10,
 479	.post_div_table = post_div_table_cam_cc_pll7_out_even,
 480	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even),
 481	.width = 4,
 482	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 483	.clkr.hw.init = &(const struct clk_init_data) {
 484		.name = "cam_cc_pll7_out_even",
 485		.parent_hws = (const struct clk_hw*[]) {
 486			&cam_cc_pll7.clkr.hw,
 487		},
 488		.num_parents = 1,
 489		.flags = CLK_SET_RATE_PARENT,
 490		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 491	},
 492};
 493
 494static const struct alpha_pll_config cam_cc_pll8_config = {
 495	.l = 0x14,
 496	.alpha = 0xd555,
 497	.config_ctl_val = 0x20485699,
 498	.config_ctl_hi_val = 0x00182261,
 499	.config_ctl_hi1_val = 0x82aa299c,
 500	.test_ctl_val = 0x00000000,
 501	.test_ctl_hi_val = 0x00000003,
 502	.test_ctl_hi1_val = 0x00009000,
 503	.test_ctl_hi2_val = 0x00000034,
 504	.user_ctl_val = 0x00000400,
 505	.user_ctl_hi_val = 0x00000005,
 506};
 507
 508static struct clk_alpha_pll cam_cc_pll8 = {
 509	.offset = 0x8000,
 510	.config = &cam_cc_pll8_config,
 511	.vco_table = lucid_ole_vco,
 512	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 513	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 514	.clkr = {
 515		.hw.init = &(const struct clk_init_data) {
 516			.name = "cam_cc_pll8",
 517			.parent_data = &(const struct clk_parent_data) {
 518				.index = DT_BI_TCXO,
 519			},
 520			.num_parents = 1,
 521			.ops = &clk_alpha_pll_lucid_evo_ops,
 522		},
 523	},
 524};
 525
 526static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
 527	{ 0x1, 2 },
 528	{ }
 529};
 530
 531static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
 532	.offset = 0x8000,
 533	.post_div_shift = 10,
 534	.post_div_table = post_div_table_cam_cc_pll8_out_even,
 535	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even),
 536	.width = 4,
 537	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 538	.clkr.hw.init = &(const struct clk_init_data) {
 539		.name = "cam_cc_pll8_out_even",
 540		.parent_hws = (const struct clk_hw*[]) {
 541			&cam_cc_pll8.clkr.hw,
 542		},
 543		.num_parents = 1,
 544		.flags = CLK_SET_RATE_PARENT,
 545		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 546	},
 547};
 548
 549static const struct alpha_pll_config cam_cc_pll9_config = {
 550	.l = 0x32,
 551	.alpha = 0x0,
 552	.config_ctl_val = 0x20485699,
 553	.config_ctl_hi_val = 0x00182261,
 554	.config_ctl_hi1_val = 0x82aa299c,
 555	.test_ctl_val = 0x00000000,
 556	.test_ctl_hi_val = 0x00000003,
 557	.test_ctl_hi1_val = 0x00009000,
 558	.test_ctl_hi2_val = 0x00000034,
 559	.user_ctl_val = 0x00008400,
 560	.user_ctl_hi_val = 0x00000005,
 561};
 562
 563static struct clk_alpha_pll cam_cc_pll9 = {
 564	.offset = 0x9000,
 565	.config = &cam_cc_pll9_config,
 566	.vco_table = lucid_ole_vco,
 567	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 568	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 569	.clkr = {
 570		.hw.init = &(const struct clk_init_data) {
 571			.name = "cam_cc_pll9",
 572			.parent_data = &(const struct clk_parent_data) {
 573				.index = DT_BI_TCXO,
 574			},
 575			.num_parents = 1,
 576			.ops = &clk_alpha_pll_lucid_evo_ops,
 577		},
 578	},
 579};
 580
 581static const struct clk_div_table post_div_table_cam_cc_pll9_out_even[] = {
 582	{ 0x1, 2 },
 583	{ }
 584};
 585
 586static struct clk_alpha_pll_postdiv cam_cc_pll9_out_even = {
 587	.offset = 0x9000,
 588	.post_div_shift = 10,
 589	.post_div_table = post_div_table_cam_cc_pll9_out_even,
 590	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_even),
 591	.width = 4,
 592	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 593	.clkr.hw.init = &(const struct clk_init_data) {
 594		.name = "cam_cc_pll9_out_even",
 595		.parent_hws = (const struct clk_hw*[]) {
 596			&cam_cc_pll9.clkr.hw,
 597		},
 598		.num_parents = 1,
 599		.flags = CLK_SET_RATE_PARENT,
 600		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 601	},
 602};
 603
 604static const struct clk_div_table post_div_table_cam_cc_pll9_out_odd[] = {
 605	{ 0x2, 3 },
 606	{ }
 607};
 608
 609static struct clk_alpha_pll_postdiv cam_cc_pll9_out_odd = {
 610	.offset = 0x9000,
 611	.post_div_shift = 14,
 612	.post_div_table = post_div_table_cam_cc_pll9_out_odd,
 613	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_odd),
 614	.width = 4,
 615	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 616	.clkr.hw.init = &(const struct clk_init_data) {
 617		.name = "cam_cc_pll9_out_odd",
 618		.parent_hws = (const struct clk_hw*[]) {
 619			&cam_cc_pll9.clkr.hw,
 620		},
 621		.num_parents = 1,
 622		.flags = CLK_SET_RATE_PARENT,
 623		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 624	},
 625};
 626
 627static const struct alpha_pll_config cam_cc_pll10_config = {
 628	.l = 0x30,
 629	.alpha = 0x8aaa,
 630	.config_ctl_val = 0x20485699,
 631	.config_ctl_hi_val = 0x00182261,
 632	.config_ctl_hi1_val = 0x82aa299c,
 633	.test_ctl_val = 0x00000000,
 634	.test_ctl_hi_val = 0x00000003,
 635	.test_ctl_hi1_val = 0x00009000,
 636	.test_ctl_hi2_val = 0x00000034,
 637	.user_ctl_val = 0x00000400,
 638	.user_ctl_hi_val = 0x00000005,
 639};
 640
 641static struct clk_alpha_pll cam_cc_pll10 = {
 642	.offset = 0xa000,
 643	.config = &cam_cc_pll10_config,
 644	.vco_table = lucid_ole_vco,
 645	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 646	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 647	.clkr = {
 648		.hw.init = &(const struct clk_init_data) {
 649			.name = "cam_cc_pll10",
 650			.parent_data = &(const struct clk_parent_data) {
 651				.index = DT_BI_TCXO,
 652			},
 653			.num_parents = 1,
 654			.ops = &clk_alpha_pll_lucid_evo_ops,
 655		},
 656	},
 657};
 658
 659static const struct clk_div_table post_div_table_cam_cc_pll10_out_even[] = {
 660	{ 0x1, 2 },
 661	{ }
 662};
 663
 664static struct clk_alpha_pll_postdiv cam_cc_pll10_out_even = {
 665	.offset = 0xa000,
 666	.post_div_shift = 10,
 667	.post_div_table = post_div_table_cam_cc_pll10_out_even,
 668	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll10_out_even),
 669	.width = 4,
 670	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 671	.clkr.hw.init = &(const struct clk_init_data) {
 672		.name = "cam_cc_pll10_out_even",
 673		.parent_hws = (const struct clk_hw*[]) {
 674			&cam_cc_pll10.clkr.hw,
 675		},
 676		.num_parents = 1,
 677		.flags = CLK_SET_RATE_PARENT,
 678		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 679	},
 680};
 681
 682static const struct parent_map cam_cc_parent_map_0[] = {
 683	{ P_BI_TCXO, 0 },
 684	{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
 685	{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
 686	{ P_CAM_CC_PLL0_OUT_ODD, 3 },
 687	{ P_CAM_CC_PLL9_OUT_ODD, 4 },
 688	{ P_CAM_CC_PLL9_OUT_EVEN, 5 },
 689};
 690
 691static const struct clk_parent_data cam_cc_parent_data_0[] = {
 692	{ .index = DT_BI_TCXO },
 693	{ .hw = &cam_cc_pll0.clkr.hw },
 694	{ .hw = &cam_cc_pll0_out_even.clkr.hw },
 695	{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
 696	{ .hw = &cam_cc_pll9_out_odd.clkr.hw },
 697	{ .hw = &cam_cc_pll9_out_even.clkr.hw },
 698};
 699
 700static const struct parent_map cam_cc_parent_map_1[] = {
 701	{ P_BI_TCXO, 0 },
 702	{ P_CAM_CC_PLL2_OUT_EVEN, 3 },
 703	{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
 704};
 705
 706static const struct clk_parent_data cam_cc_parent_data_1[] = {
 707	{ .index = DT_BI_TCXO },
 708	{ .hw = &cam_cc_pll2.clkr.hw },
 709	{ .hw = &cam_cc_pll2.clkr.hw },
 710};
 711
 712static const struct parent_map cam_cc_parent_map_2[] = {
 713	{ P_BI_TCXO, 0 },
 714	{ P_CAM_CC_PLL8_OUT_EVEN, 6 },
 715};
 716
 717static const struct clk_parent_data cam_cc_parent_data_2[] = {
 718	{ .index = DT_BI_TCXO },
 719	{ .hw = &cam_cc_pll8_out_even.clkr.hw },
 720};
 721
 722static const struct parent_map cam_cc_parent_map_3[] = {
 723	{ P_BI_TCXO, 0 },
 724	{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
 725};
 726
 727static const struct clk_parent_data cam_cc_parent_data_3[] = {
 728	{ .index = DT_BI_TCXO },
 729	{ .hw = &cam_cc_pll3_out_even.clkr.hw },
 730};
 731
 732static const struct parent_map cam_cc_parent_map_4[] = {
 733	{ P_BI_TCXO, 0 },
 734	{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
 735};
 736
 737static const struct clk_parent_data cam_cc_parent_data_4[] = {
 738	{ .index = DT_BI_TCXO },
 739	{ .hw = &cam_cc_pll4_out_even.clkr.hw },
 740};
 741
 742static const struct parent_map cam_cc_parent_map_5[] = {
 743	{ P_BI_TCXO, 0 },
 744	{ P_CAM_CC_PLL5_OUT_EVEN, 6 },
 745};
 746
 747static const struct clk_parent_data cam_cc_parent_data_5[] = {
 748	{ .index = DT_BI_TCXO },
 749	{ .hw = &cam_cc_pll5_out_even.clkr.hw },
 750};
 751
 752static const struct parent_map cam_cc_parent_map_6[] = {
 753	{ P_BI_TCXO, 0 },
 754	{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
 755};
 756
 757static const struct clk_parent_data cam_cc_parent_data_6[] = {
 758	{ .index = DT_BI_TCXO },
 759	{ .hw = &cam_cc_pll1_out_even.clkr.hw },
 760};
 761
 762static const struct parent_map cam_cc_parent_map_7[] = {
 763	{ P_BI_TCXO, 0 },
 764	{ P_CAM_CC_PLL6_OUT_EVEN, 6 },
 765};
 766
 767static const struct clk_parent_data cam_cc_parent_data_7[] = {
 768	{ .index = DT_BI_TCXO },
 769	{ .hw = &cam_cc_pll6_out_even.clkr.hw },
 770};
 771
 772static const struct parent_map cam_cc_parent_map_8[] = {
 773	{ P_BI_TCXO, 0 },
 774	{ P_CAM_CC_PLL7_OUT_EVEN, 6 },
 775};
 776
 777static const struct clk_parent_data cam_cc_parent_data_8[] = {
 778	{ .index = DT_BI_TCXO },
 779	{ .hw = &cam_cc_pll7_out_even.clkr.hw },
 780};
 781
 782static const struct parent_map cam_cc_parent_map_9[] = {
 783	{ P_BI_TCXO, 0 },
 784	{ P_CAM_CC_PLL10_OUT_EVEN, 6 },
 785};
 786
 787static const struct clk_parent_data cam_cc_parent_data_9[] = {
 788	{ .index = DT_BI_TCXO },
 789	{ .hw = &cam_cc_pll10_out_even.clkr.hw },
 790};
 791
 792static const struct parent_map cam_cc_parent_map_10[] = {
 793	{ P_SLEEP_CLK, 0 },
 794};
 795
 796static const struct clk_parent_data cam_cc_parent_data_10[] = {
 797	{ .index = DT_SLEEP_CLK },
 798};
 799
 800static const struct parent_map cam_cc_parent_map_11_ao[] = {
 801	{ P_BI_TCXO_AO, 0 },
 802};
 803
 804static const struct clk_parent_data cam_cc_parent_data_11_ao[] = {
 805	{ .index = DT_BI_TCXO_AO },
 806};
 807
 808static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
 809	F(19200000, P_BI_TCXO, 1, 0, 0),
 810	F(200000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
 811	F(400000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
 812	F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
 813	F(785000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
 814	{ }
 815};
 816
 817static struct clk_rcg2 cam_cc_bps_clk_src = {
 818	.cmd_rcgr = 0x10050,
 819	.mnd_width = 0,
 820	.hid_width = 5,
 821	.parent_map = cam_cc_parent_map_2,
 822	.freq_tbl = ftbl_cam_cc_bps_clk_src,
 823	.clkr.hw.init = &(const struct clk_init_data) {
 824		.name = "cam_cc_bps_clk_src",
 825		.parent_data = cam_cc_parent_data_2,
 826		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
 827		.flags = CLK_SET_RATE_PARENT,
 828		.ops = &clk_rcg2_shared_ops,
 829	},
 830};
 831
 832static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = {
 833	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
 834	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 835	{ }
 836};
 837
 838static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = {
 839	.cmd_rcgr = 0x1325c,
 840	.mnd_width = 0,
 841	.hid_width = 5,
 842	.parent_map = cam_cc_parent_map_0,
 843	.freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src,
 844	.clkr.hw.init = &(const struct clk_init_data) {
 845		.name = "cam_cc_camnoc_axi_rt_clk_src",
 846		.parent_data = cam_cc_parent_data_0,
 847		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 848		.flags = CLK_SET_RATE_PARENT,
 849		.ops = &clk_rcg2_shared_ops,
 850	},
 851};
 852
 853static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
 854	F(19200000, P_BI_TCXO, 1, 0, 0),
 855	F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
 856	{ }
 857};
 858
 859static struct clk_rcg2 cam_cc_cci_0_clk_src = {
 860	.cmd_rcgr = 0x131cc,
 861	.mnd_width = 8,
 862	.hid_width = 5,
 863	.parent_map = cam_cc_parent_map_0,
 864	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 865	.clkr.hw.init = &(const struct clk_init_data) {
 866		.name = "cam_cc_cci_0_clk_src",
 867		.parent_data = cam_cc_parent_data_0,
 868		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 869		.flags = CLK_SET_RATE_PARENT,
 870		.ops = &clk_rcg2_shared_ops,
 871	},
 872};
 873
 874static struct clk_rcg2 cam_cc_cci_1_clk_src = {
 875	.cmd_rcgr = 0x131e8,
 876	.mnd_width = 8,
 877	.hid_width = 5,
 878	.parent_map = cam_cc_parent_map_0,
 879	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 880	.clkr.hw.init = &(const struct clk_init_data) {
 881		.name = "cam_cc_cci_1_clk_src",
 882		.parent_data = cam_cc_parent_data_0,
 883		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 884		.flags = CLK_SET_RATE_PARENT,
 885		.ops = &clk_rcg2_shared_ops,
 886	},
 887};
 888
 889static struct clk_rcg2 cam_cc_cci_2_clk_src = {
 890	.cmd_rcgr = 0x13204,
 891	.mnd_width = 8,
 892	.hid_width = 5,
 893	.parent_map = cam_cc_parent_map_0,
 894	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 895	.clkr.hw.init = &(const struct clk_init_data) {
 896		.name = "cam_cc_cci_2_clk_src",
 897		.parent_data = cam_cc_parent_data_0,
 898		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 899		.flags = CLK_SET_RATE_PARENT,
 900		.ops = &clk_rcg2_shared_ops,
 901	},
 902};
 903
 904static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
 905	F(19200000, P_BI_TCXO, 1, 0, 0),
 906	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
 907	F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
 908	{ }
 909};
 910
 911static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
 912	.cmd_rcgr = 0x1104c,
 913	.mnd_width = 0,
 914	.hid_width = 5,
 915	.parent_map = cam_cc_parent_map_0,
 916	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
 917	.clkr.hw.init = &(const struct clk_init_data) {
 918		.name = "cam_cc_cphy_rx_clk_src",
 919		.parent_data = cam_cc_parent_data_0,
 920		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 921		.flags = CLK_SET_RATE_PARENT,
 922		.ops = &clk_rcg2_shared_ops,
 923	},
 924};
 925
 926static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = {
 927	F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
 928	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 929	F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
 930	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
 931	{ }
 932};
 933
 934static struct clk_rcg2 cam_cc_cre_clk_src = {
 935	.cmd_rcgr = 0x13144,
 936	.mnd_width = 0,
 937	.hid_width = 5,
 938	.parent_map = cam_cc_parent_map_0,
 939	.freq_tbl = ftbl_cam_cc_cre_clk_src,
 940	.clkr.hw.init = &(const struct clk_init_data) {
 941		.name = "cam_cc_cre_clk_src",
 942		.parent_data = cam_cc_parent_data_0,
 943		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 944		.flags = CLK_SET_RATE_PARENT,
 945		.ops = &clk_rcg2_shared_ops,
 946	},
 947};
 948
 949static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
 950	F(19200000, P_BI_TCXO, 1, 0, 0),
 951	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
 952	{ }
 953};
 954
 955static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
 956	.cmd_rcgr = 0x150e0,
 957	.mnd_width = 0,
 958	.hid_width = 5,
 959	.parent_map = cam_cc_parent_map_0,
 960	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 961	.clkr.hw.init = &(const struct clk_init_data) {
 962		.name = "cam_cc_csi0phytimer_clk_src",
 963		.parent_data = cam_cc_parent_data_0,
 964		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 965		.flags = CLK_SET_RATE_PARENT,
 966		.ops = &clk_rcg2_shared_ops,
 967	},
 968};
 969
 970static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
 971	.cmd_rcgr = 0x15104,
 972	.mnd_width = 0,
 973	.hid_width = 5,
 974	.parent_map = cam_cc_parent_map_0,
 975	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 976	.clkr.hw.init = &(const struct clk_init_data) {
 977		.name = "cam_cc_csi1phytimer_clk_src",
 978		.parent_data = cam_cc_parent_data_0,
 979		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 980		.flags = CLK_SET_RATE_PARENT,
 981		.ops = &clk_rcg2_shared_ops,
 982	},
 983};
 984
 985static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
 986	.cmd_rcgr = 0x15124,
 987	.mnd_width = 0,
 988	.hid_width = 5,
 989	.parent_map = cam_cc_parent_map_0,
 990	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 991	.clkr.hw.init = &(const struct clk_init_data) {
 992		.name = "cam_cc_csi2phytimer_clk_src",
 993		.parent_data = cam_cc_parent_data_0,
 994		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 995		.flags = CLK_SET_RATE_PARENT,
 996		.ops = &clk_rcg2_shared_ops,
 997	},
 998};
 999
1000static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
1001	.cmd_rcgr = 0x15144,
1002	.mnd_width = 0,
1003	.hid_width = 5,
1004	.parent_map = cam_cc_parent_map_0,
1005	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1006	.clkr.hw.init = &(const struct clk_init_data) {
1007		.name = "cam_cc_csi3phytimer_clk_src",
1008		.parent_data = cam_cc_parent_data_0,
1009		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1010		.flags = CLK_SET_RATE_PARENT,
1011		.ops = &clk_rcg2_shared_ops,
1012	},
1013};
1014
1015static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
1016	.cmd_rcgr = 0x15164,
1017	.mnd_width = 0,
1018	.hid_width = 5,
1019	.parent_map = cam_cc_parent_map_0,
1020	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1021	.clkr.hw.init = &(const struct clk_init_data) {
1022		.name = "cam_cc_csi4phytimer_clk_src",
1023		.parent_data = cam_cc_parent_data_0,
1024		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1025		.flags = CLK_SET_RATE_PARENT,
1026		.ops = &clk_rcg2_shared_ops,
1027	},
1028};
1029
1030static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
1031	.cmd_rcgr = 0x15184,
1032	.mnd_width = 0,
1033	.hid_width = 5,
1034	.parent_map = cam_cc_parent_map_0,
1035	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1036	.clkr.hw.init = &(const struct clk_init_data) {
1037		.name = "cam_cc_csi5phytimer_clk_src",
1038		.parent_data = cam_cc_parent_data_0,
1039		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1040		.flags = CLK_SET_RATE_PARENT,
1041		.ops = &clk_rcg2_shared_ops,
1042	},
1043};
1044
1045static struct clk_rcg2 cam_cc_csi6phytimer_clk_src = {
1046	.cmd_rcgr = 0x151a4,
1047	.mnd_width = 0,
1048	.hid_width = 5,
1049	.parent_map = cam_cc_parent_map_0,
1050	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1051	.clkr.hw.init = &(const struct clk_init_data) {
1052		.name = "cam_cc_csi6phytimer_clk_src",
1053		.parent_data = cam_cc_parent_data_0,
1054		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1055		.flags = CLK_SET_RATE_PARENT,
1056		.ops = &clk_rcg2_shared_ops,
1057	},
1058};
1059
1060static struct clk_rcg2 cam_cc_csi7phytimer_clk_src = {
1061	.cmd_rcgr = 0x151c4,
1062	.mnd_width = 0,
1063	.hid_width = 5,
1064	.parent_map = cam_cc_parent_map_0,
1065	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1066	.clkr.hw.init = &(const struct clk_init_data) {
1067		.name = "cam_cc_csi7phytimer_clk_src",
1068		.parent_data = cam_cc_parent_data_0,
1069		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1070		.flags = CLK_SET_RATE_PARENT,
1071		.ops = &clk_rcg2_shared_ops,
1072	},
1073};
1074
1075static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = {
1076	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1077	F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
1078	{ }
1079};
1080
1081static struct clk_rcg2 cam_cc_csid_clk_src = {
1082	.cmd_rcgr = 0x13238,
1083	.mnd_width = 0,
1084	.hid_width = 5,
1085	.parent_map = cam_cc_parent_map_0,
1086	.freq_tbl = ftbl_cam_cc_csid_clk_src,
1087	.clkr.hw.init = &(const struct clk_init_data) {
1088		.name = "cam_cc_csid_clk_src",
1089		.parent_data = cam_cc_parent_data_0,
1090		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1091		.flags = CLK_SET_RATE_PARENT,
1092		.ops = &clk_rcg2_shared_ops,
1093	},
1094};
1095
1096static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
1097	F(19200000, P_BI_TCXO, 1, 0, 0),
1098	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
1099	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1100	{ }
1101};
1102
1103static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
1104	.cmd_rcgr = 0x10018,
1105	.mnd_width = 0,
1106	.hid_width = 5,
1107	.parent_map = cam_cc_parent_map_0,
1108	.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
1109	.clkr.hw.init = &(const struct clk_init_data) {
1110		.name = "cam_cc_fast_ahb_clk_src",
1111		.parent_data = cam_cc_parent_data_0,
1112		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1113		.flags = CLK_SET_RATE_PARENT,
1114		.ops = &clk_rcg2_shared_ops,
1115	},
1116};
1117
1118static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
1119	F(19200000, P_BI_TCXO, 1, 0, 0),
1120	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1121	F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
1122	F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
1123	{ }
1124};
1125
1126static struct clk_rcg2 cam_cc_icp_clk_src = {
1127	.cmd_rcgr = 0x131a4,
1128	.mnd_width = 0,
1129	.hid_width = 5,
1130	.parent_map = cam_cc_parent_map_0,
1131	.freq_tbl = ftbl_cam_cc_icp_clk_src,
1132	.clkr.hw.init = &(const struct clk_init_data) {
1133		.name = "cam_cc_icp_clk_src",
1134		.parent_data = cam_cc_parent_data_0,
1135		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1136		.flags = CLK_SET_RATE_PARENT,
1137		.ops = &clk_rcg2_shared_ops,
1138	},
1139};
1140
1141static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
1142	F(19200000, P_BI_TCXO, 1, 0, 0),
1143	F(466000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1144	F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1145	F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1146	F(785000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1147	{ }
1148};
1149
1150static struct clk_rcg2 cam_cc_ife_0_clk_src = {
1151	.cmd_rcgr = 0x11018,
1152	.mnd_width = 0,
1153	.hid_width = 5,
1154	.parent_map = cam_cc_parent_map_3,
1155	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
1156	.clkr.hw.init = &(const struct clk_init_data) {
1157		.name = "cam_cc_ife_0_clk_src",
1158		.parent_data = cam_cc_parent_data_3,
1159		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
1160		.flags = CLK_SET_RATE_PARENT,
1161		.ops = &clk_rcg2_shared_ops,
1162	},
1163};
1164
1165static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
1166	F(19200000, P_BI_TCXO, 1, 0, 0),
1167	F(466000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1168	F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1169	F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1170	F(785000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1171	{ }
1172};
1173
1174static struct clk_rcg2 cam_cc_ife_1_clk_src = {
1175	.cmd_rcgr = 0x12018,
1176	.mnd_width = 0,
1177	.hid_width = 5,
1178	.parent_map = cam_cc_parent_map_4,
1179	.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
1180	.clkr.hw.init = &(const struct clk_init_data) {
1181		.name = "cam_cc_ife_1_clk_src",
1182		.parent_data = cam_cc_parent_data_4,
1183		.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
1184		.flags = CLK_SET_RATE_PARENT,
1185		.ops = &clk_rcg2_shared_ops,
1186	},
1187};
1188
1189static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
1190	F(19200000, P_BI_TCXO, 1, 0, 0),
1191	F(466000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1192	F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1193	F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1194	F(785000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1195	{ }
1196};
1197
1198static struct clk_rcg2 cam_cc_ife_2_clk_src = {
1199	.cmd_rcgr = 0x12068,
1200	.mnd_width = 0,
1201	.hid_width = 5,
1202	.parent_map = cam_cc_parent_map_5,
1203	.freq_tbl = ftbl_cam_cc_ife_2_clk_src,
1204	.clkr.hw.init = &(const struct clk_init_data) {
1205		.name = "cam_cc_ife_2_clk_src",
1206		.parent_data = cam_cc_parent_data_5,
1207		.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
1208		.flags = CLK_SET_RATE_PARENT,
1209		.ops = &clk_rcg2_shared_ops,
1210	},
1211};
1212
1213static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
1214	.cmd_rcgr = 0x13000,
1215	.mnd_width = 0,
1216	.hid_width = 5,
1217	.parent_map = cam_cc_parent_map_0,
1218	.freq_tbl = ftbl_cam_cc_csid_clk_src,
1219	.clkr.hw.init = &(const struct clk_init_data) {
1220		.name = "cam_cc_ife_lite_clk_src",
1221		.parent_data = cam_cc_parent_data_0,
1222		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1223		.flags = CLK_SET_RATE_PARENT,
1224		.ops = &clk_rcg2_shared_ops,
1225	},
1226};
1227
1228static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
1229	.cmd_rcgr = 0x13028,
1230	.mnd_width = 0,
1231	.hid_width = 5,
1232	.parent_map = cam_cc_parent_map_0,
1233	.freq_tbl = ftbl_cam_cc_csid_clk_src,
1234	.clkr.hw.init = &(const struct clk_init_data) {
1235		.name = "cam_cc_ife_lite_csid_clk_src",
1236		.parent_data = cam_cc_parent_data_0,
1237		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1238		.flags = CLK_SET_RATE_PARENT,
1239		.ops = &clk_rcg2_shared_ops,
1240	},
1241};
1242
1243static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = {
1244	F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1245	F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1246	F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1247	F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1248	{ }
1249};
1250
1251static struct clk_rcg2 cam_cc_ipe_nps_clk_src = {
1252	.cmd_rcgr = 0x10094,
1253	.mnd_width = 0,
1254	.hid_width = 5,
1255	.parent_map = cam_cc_parent_map_6,
1256	.freq_tbl = ftbl_cam_cc_ipe_nps_clk_src,
1257	.clkr.hw.init = &(const struct clk_init_data) {
1258		.name = "cam_cc_ipe_nps_clk_src",
1259		.parent_data = cam_cc_parent_data_6,
1260		.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
1261		.flags = CLK_SET_RATE_PARENT,
1262		.ops = &clk_rcg2_shared_ops,
1263	},
1264};
1265
1266static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = {
1267	F(19200000, P_BI_TCXO, 1, 0, 0),
1268	F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
1269	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1270	F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
1271	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
1272	{ }
1273};
1274
1275static struct clk_rcg2 cam_cc_jpeg_clk_src = {
1276	.cmd_rcgr = 0x13168,
1277	.mnd_width = 0,
1278	.hid_width = 5,
1279	.parent_map = cam_cc_parent_map_0,
1280	.freq_tbl = ftbl_cam_cc_jpeg_clk_src,
1281	.clkr.hw.init = &(const struct clk_init_data) {
1282		.name = "cam_cc_jpeg_clk_src",
1283		.parent_data = cam_cc_parent_data_0,
1284		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1285		.flags = CLK_SET_RATE_PARENT,
1286		.ops = &clk_rcg2_shared_ops,
1287	},
1288};
1289
1290static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
1291	F(19200000, P_BI_TCXO, 1, 0, 0),
1292	F(24000000, P_CAM_CC_PLL2_OUT_EVEN, 10, 1, 4),
1293	F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0),
1294	{ }
1295};
1296
1297static struct clk_rcg2 cam_cc_mclk0_clk_src = {
1298	.cmd_rcgr = 0x15000,
1299	.mnd_width = 8,
1300	.hid_width = 5,
1301	.parent_map = cam_cc_parent_map_1,
1302	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1303	.clkr.hw.init = &(const struct clk_init_data) {
1304		.name = "cam_cc_mclk0_clk_src",
1305		.parent_data = cam_cc_parent_data_1,
1306		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1307		.flags = CLK_SET_RATE_PARENT,
1308		.ops = &clk_rcg2_shared_ops,
1309	},
1310};
1311
1312static struct clk_rcg2 cam_cc_mclk1_clk_src = {
1313	.cmd_rcgr = 0x1501c,
1314	.mnd_width = 8,
1315	.hid_width = 5,
1316	.parent_map = cam_cc_parent_map_1,
1317	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1318	.clkr.hw.init = &(const struct clk_init_data) {
1319		.name = "cam_cc_mclk1_clk_src",
1320		.parent_data = cam_cc_parent_data_1,
1321		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1322		.flags = CLK_SET_RATE_PARENT,
1323		.ops = &clk_rcg2_shared_ops,
1324	},
1325};
1326
1327static struct clk_rcg2 cam_cc_mclk2_clk_src = {
1328	.cmd_rcgr = 0x15038,
1329	.mnd_width = 8,
1330	.hid_width = 5,
1331	.parent_map = cam_cc_parent_map_1,
1332	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1333	.clkr.hw.init = &(const struct clk_init_data) {
1334		.name = "cam_cc_mclk2_clk_src",
1335		.parent_data = cam_cc_parent_data_1,
1336		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1337		.flags = CLK_SET_RATE_PARENT,
1338		.ops = &clk_rcg2_shared_ops,
1339	},
1340};
1341
1342static struct clk_rcg2 cam_cc_mclk3_clk_src = {
1343	.cmd_rcgr = 0x15054,
1344	.mnd_width = 8,
1345	.hid_width = 5,
1346	.parent_map = cam_cc_parent_map_1,
1347	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1348	.clkr.hw.init = &(const struct clk_init_data) {
1349		.name = "cam_cc_mclk3_clk_src",
1350		.parent_data = cam_cc_parent_data_1,
1351		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1352		.flags = CLK_SET_RATE_PARENT,
1353		.ops = &clk_rcg2_shared_ops,
1354	},
1355};
1356
1357static struct clk_rcg2 cam_cc_mclk4_clk_src = {
1358	.cmd_rcgr = 0x15070,
1359	.mnd_width = 8,
1360	.hid_width = 5,
1361	.parent_map = cam_cc_parent_map_1,
1362	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1363	.clkr.hw.init = &(const struct clk_init_data) {
1364		.name = "cam_cc_mclk4_clk_src",
1365		.parent_data = cam_cc_parent_data_1,
1366		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1367		.flags = CLK_SET_RATE_PARENT,
1368		.ops = &clk_rcg2_shared_ops,
1369	},
1370};
1371
1372static struct clk_rcg2 cam_cc_mclk5_clk_src = {
1373	.cmd_rcgr = 0x1508c,
1374	.mnd_width = 8,
1375	.hid_width = 5,
1376	.parent_map = cam_cc_parent_map_1,
1377	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1378	.clkr.hw.init = &(const struct clk_init_data) {
1379		.name = "cam_cc_mclk5_clk_src",
1380		.parent_data = cam_cc_parent_data_1,
1381		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1382		.flags = CLK_SET_RATE_PARENT,
1383		.ops = &clk_rcg2_shared_ops,
1384	},
1385};
1386
1387static struct clk_rcg2 cam_cc_mclk6_clk_src = {
1388	.cmd_rcgr = 0x150a8,
1389	.mnd_width = 8,
1390	.hid_width = 5,
1391	.parent_map = cam_cc_parent_map_1,
1392	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1393	.clkr.hw.init = &(const struct clk_init_data) {
1394		.name = "cam_cc_mclk6_clk_src",
1395		.parent_data = cam_cc_parent_data_1,
1396		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1397		.flags = CLK_SET_RATE_PARENT,
1398		.ops = &clk_rcg2_shared_ops,
1399	},
1400};
1401
1402static struct clk_rcg2 cam_cc_mclk7_clk_src = {
1403	.cmd_rcgr = 0x150c4,
1404	.mnd_width = 8,
1405	.hid_width = 5,
1406	.parent_map = cam_cc_parent_map_1,
1407	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1408	.clkr.hw.init = &(const struct clk_init_data) {
1409		.name = "cam_cc_mclk7_clk_src",
1410		.parent_data = cam_cc_parent_data_1,
1411		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1412		.flags = CLK_SET_RATE_PARENT,
1413		.ops = &clk_rcg2_shared_ops,
1414	},
1415};
1416
1417static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = {
1418	F(19200000, P_BI_TCXO, 1, 0, 0),
1419	F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
1420	F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
1421	F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
1422	{ }
1423};
1424
1425static struct clk_rcg2 cam_cc_qdss_debug_clk_src = {
1426	.cmd_rcgr = 0x1329c,
1427	.mnd_width = 0,
1428	.hid_width = 5,
1429	.parent_map = cam_cc_parent_map_0,
1430	.freq_tbl = ftbl_cam_cc_qdss_debug_clk_src,
1431	.clkr.hw.init = &(const struct clk_init_data) {
1432		.name = "cam_cc_qdss_debug_clk_src",
1433		.parent_data = cam_cc_parent_data_0,
1434		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1435		.flags = CLK_SET_RATE_PARENT,
1436		.ops = &clk_rcg2_shared_ops,
1437	},
1438};
1439
1440static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
1441	F(466000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1442	F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1443	F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1444	F(785000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1445	{ }
1446};
1447
1448static struct clk_rcg2 cam_cc_sfe_0_clk_src = {
1449	.cmd_rcgr = 0x1306c,
1450	.mnd_width = 0,
1451	.hid_width = 5,
1452	.parent_map = cam_cc_parent_map_7,
1453	.freq_tbl = ftbl_cam_cc_sfe_0_clk_src,
1454	.clkr.hw.init = &(const struct clk_init_data) {
1455		.name = "cam_cc_sfe_0_clk_src",
1456		.parent_data = cam_cc_parent_data_7,
1457		.num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
1458		.flags = CLK_SET_RATE_PARENT,
1459		.ops = &clk_rcg2_shared_ops,
1460	},
1461};
1462
1463static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = {
1464	F(466000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1465	F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1466	F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1467	F(785000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1468	{ }
1469};
1470
1471static struct clk_rcg2 cam_cc_sfe_1_clk_src = {
1472	.cmd_rcgr = 0x130bc,
1473	.mnd_width = 0,
1474	.hid_width = 5,
1475	.parent_map = cam_cc_parent_map_8,
1476	.freq_tbl = ftbl_cam_cc_sfe_1_clk_src,
1477	.clkr.hw.init = &(const struct clk_init_data) {
1478		.name = "cam_cc_sfe_1_clk_src",
1479		.parent_data = cam_cc_parent_data_8,
1480		.num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
1481		.flags = CLK_SET_RATE_PARENT,
1482		.ops = &clk_rcg2_shared_ops,
1483	},
1484};
1485
1486static const struct freq_tbl ftbl_cam_cc_sfe_2_clk_src[] = {
1487	F(466000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1488	F(594000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1489	F(675000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1490	F(785000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1491	{ }
1492};
1493
1494static struct clk_rcg2 cam_cc_sfe_2_clk_src = {
1495	.cmd_rcgr = 0x1310c,
1496	.mnd_width = 0,
1497	.hid_width = 5,
1498	.parent_map = cam_cc_parent_map_9,
1499	.freq_tbl = ftbl_cam_cc_sfe_2_clk_src,
1500	.clkr.hw.init = &(const struct clk_init_data) {
1501		.name = "cam_cc_sfe_2_clk_src",
1502		.parent_data = cam_cc_parent_data_9,
1503		.num_parents = ARRAY_SIZE(cam_cc_parent_data_9),
1504		.flags = CLK_SET_RATE_PARENT,
1505		.ops = &clk_rcg2_shared_ops,
1506	},
1507};
1508
1509static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
1510	F(32000, P_SLEEP_CLK, 1, 0, 0),
1511	{ }
1512};
1513
1514static struct clk_rcg2 cam_cc_sleep_clk_src = {
1515	.cmd_rcgr = 0x132f0,
1516	.mnd_width = 0,
1517	.hid_width = 5,
1518	.parent_map = cam_cc_parent_map_10,
1519	.freq_tbl = ftbl_cam_cc_sleep_clk_src,
1520	.clkr.hw.init = &(const struct clk_init_data) {
1521		.name = "cam_cc_sleep_clk_src",
1522		.parent_data = cam_cc_parent_data_10,
1523		.num_parents = ARRAY_SIZE(cam_cc_parent_data_10),
1524		.flags = CLK_SET_RATE_PARENT,
1525		.ops = &clk_rcg2_shared_ops,
1526	},
1527};
1528
1529static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
1530	F(19200000, P_BI_TCXO, 1, 0, 0),
1531	F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
1532	{ }
1533};
1534
1535static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
1536	.cmd_rcgr = 0x10034,
1537	.mnd_width = 0,
1538	.hid_width = 5,
1539	.parent_map = cam_cc_parent_map_0,
1540	.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
1541	.clkr.hw.init = &(const struct clk_init_data) {
1542		.name = "cam_cc_slow_ahb_clk_src",
1543		.parent_data = cam_cc_parent_data_0,
1544		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1545		.flags = CLK_SET_RATE_PARENT,
1546		.ops = &clk_rcg2_shared_ops,
1547	},
1548};
1549
1550static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
1551	F(19200000, P_BI_TCXO_AO, 1, 0, 0),
1552	{ }
1553};
1554
1555static struct clk_rcg2 cam_cc_xo_clk_src = {
1556	.cmd_rcgr = 0x132d4,
1557	.mnd_width = 0,
1558	.hid_width = 5,
1559	.parent_map = cam_cc_parent_map_11_ao,
1560	.freq_tbl = ftbl_cam_cc_xo_clk_src,
1561	.clkr.hw.init = &(const struct clk_init_data) {
1562		.name = "cam_cc_xo_clk_src",
1563		.parent_data = cam_cc_parent_data_11_ao,
1564		.num_parents = ARRAY_SIZE(cam_cc_parent_data_11_ao),
1565		.flags = CLK_SET_RATE_PARENT,
1566		.ops = &clk_rcg2_shared_ops,
1567	},
1568};
1569
1570static struct clk_branch cam_cc_bps_ahb_clk = {
1571	.halt_reg = 0x1004c,
1572	.halt_check = BRANCH_HALT,
1573	.clkr = {
1574		.enable_reg = 0x1004c,
1575		.enable_mask = BIT(0),
1576		.hw.init = &(const struct clk_init_data) {
1577			.name = "cam_cc_bps_ahb_clk",
1578			.parent_hws = (const struct clk_hw*[]) {
1579				&cam_cc_slow_ahb_clk_src.clkr.hw,
1580			},
1581			.num_parents = 1,
1582			.flags = CLK_SET_RATE_PARENT,
1583			.ops = &clk_branch2_ops,
1584		},
1585	},
1586};
1587
1588static struct clk_branch cam_cc_bps_clk = {
1589	.halt_reg = 0x10068,
1590	.halt_check = BRANCH_HALT,
1591	.clkr = {
1592		.enable_reg = 0x10068,
1593		.enable_mask = BIT(0),
1594		.hw.init = &(const struct clk_init_data) {
1595			.name = "cam_cc_bps_clk",
1596			.parent_hws = (const struct clk_hw*[]) {
1597				&cam_cc_bps_clk_src.clkr.hw,
1598			},
1599			.num_parents = 1,
1600			.flags = CLK_SET_RATE_PARENT,
1601			.ops = &clk_branch2_ops,
1602		},
1603	},
1604};
1605
1606static struct clk_branch cam_cc_bps_fast_ahb_clk = {
1607	.halt_reg = 0x10030,
1608	.halt_check = BRANCH_HALT,
1609	.clkr = {
1610		.enable_reg = 0x10030,
1611		.enable_mask = BIT(0),
1612		.hw.init = &(const struct clk_init_data) {
1613			.name = "cam_cc_bps_fast_ahb_clk",
1614			.parent_hws = (const struct clk_hw*[]) {
1615				&cam_cc_fast_ahb_clk_src.clkr.hw,
1616			},
1617			.num_parents = 1,
1618			.flags = CLK_SET_RATE_PARENT,
1619			.ops = &clk_branch2_ops,
1620		},
1621	},
1622};
1623
1624static struct clk_branch cam_cc_bps_shift_clk = {
1625	.halt_reg = 0x10078,
1626	.halt_check = BRANCH_HALT_VOTED,
1627	.clkr = {
1628		.enable_reg = 0x10078,
1629		.enable_mask = BIT(0),
1630		.hw.init = &(const struct clk_init_data) {
1631			.name = "cam_cc_bps_shift_clk",
1632			.parent_hws = (const struct clk_hw*[]) {
1633				&cam_cc_xo_clk_src.clkr.hw,
1634			},
1635			.num_parents = 1,
1636			.flags = CLK_SET_RATE_PARENT,
1637			.ops = &clk_branch2_ops,
1638		},
1639	},
1640};
1641
1642static struct clk_branch cam_cc_camnoc_axi_nrt_clk = {
1643	.halt_reg = 0x13284,
1644	.halt_check = BRANCH_HALT,
1645	.clkr = {
1646		.enable_reg = 0x13284,
1647		.enable_mask = BIT(0),
1648		.hw.init = &(const struct clk_init_data) {
1649			.name = "cam_cc_camnoc_axi_nrt_clk",
1650			.parent_hws = (const struct clk_hw*[]) {
1651				&cam_cc_camnoc_axi_rt_clk_src.clkr.hw,
1652			},
1653			.num_parents = 1,
1654			.flags = CLK_SET_RATE_PARENT,
1655			.ops = &clk_branch2_ops,
1656		},
1657	},
1658};
1659
1660static struct clk_branch cam_cc_camnoc_axi_rt_clk = {
1661	.halt_reg = 0x13274,
1662	.halt_check = BRANCH_HALT,
1663	.clkr = {
1664		.enable_reg = 0x13274,
1665		.enable_mask = BIT(0),
1666		.hw.init = &(const struct clk_init_data) {
1667			.name = "cam_cc_camnoc_axi_rt_clk",
1668			.parent_hws = (const struct clk_hw*[]) {
1669				&cam_cc_camnoc_axi_rt_clk_src.clkr.hw,
1670			},
1671			.num_parents = 1,
1672			.flags = CLK_SET_RATE_PARENT,
1673			.ops = &clk_branch2_ops,
1674		},
1675	},
1676};
1677
1678static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
1679	.halt_reg = 0x13290,
1680	.halt_check = BRANCH_HALT,
1681	.clkr = {
1682		.enable_reg = 0x13290,
1683		.enable_mask = BIT(0),
1684		.hw.init = &(const struct clk_init_data) {
1685			.name = "cam_cc_camnoc_dcd_xo_clk",
1686			.parent_hws = (const struct clk_hw*[]) {
1687				&cam_cc_xo_clk_src.clkr.hw,
1688			},
1689			.num_parents = 1,
1690			.flags = CLK_SET_RATE_PARENT,
1691			.ops = &clk_branch2_ops,
1692		},
1693	},
1694};
1695
1696static struct clk_branch cam_cc_camnoc_xo_clk = {
1697	.halt_reg = 0x13294,
1698	.halt_check = BRANCH_HALT,
1699	.clkr = {
1700		.enable_reg = 0x13294,
1701		.enable_mask = BIT(0),
1702		.hw.init = &(const struct clk_init_data) {
1703			.name = "cam_cc_camnoc_xo_clk",
1704			.parent_hws = (const struct clk_hw*[]) {
1705				&cam_cc_xo_clk_src.clkr.hw,
1706			},
1707			.num_parents = 1,
1708			.flags = CLK_SET_RATE_PARENT,
1709			.ops = &clk_branch2_ops,
1710		},
1711	},
1712};
1713
1714static struct clk_branch cam_cc_cci_0_clk = {
1715	.halt_reg = 0x131e4,
1716	.halt_check = BRANCH_HALT,
1717	.clkr = {
1718		.enable_reg = 0x131e4,
1719		.enable_mask = BIT(0),
1720		.hw.init = &(const struct clk_init_data) {
1721			.name = "cam_cc_cci_0_clk",
1722			.parent_hws = (const struct clk_hw*[]) {
1723				&cam_cc_cci_0_clk_src.clkr.hw,
1724			},
1725			.num_parents = 1,
1726			.flags = CLK_SET_RATE_PARENT,
1727			.ops = &clk_branch2_ops,
1728		},
1729	},
1730};
1731
1732static struct clk_branch cam_cc_cci_1_clk = {
1733	.halt_reg = 0x13200,
1734	.halt_check = BRANCH_HALT,
1735	.clkr = {
1736		.enable_reg = 0x13200,
1737		.enable_mask = BIT(0),
1738		.hw.init = &(const struct clk_init_data) {
1739			.name = "cam_cc_cci_1_clk",
1740			.parent_hws = (const struct clk_hw*[]) {
1741				&cam_cc_cci_1_clk_src.clkr.hw,
1742			},
1743			.num_parents = 1,
1744			.flags = CLK_SET_RATE_PARENT,
1745			.ops = &clk_branch2_ops,
1746		},
1747	},
1748};
1749
1750static struct clk_branch cam_cc_cci_2_clk = {
1751	.halt_reg = 0x1321c,
1752	.halt_check = BRANCH_HALT,
1753	.clkr = {
1754		.enable_reg = 0x1321c,
1755		.enable_mask = BIT(0),
1756		.hw.init = &(const struct clk_init_data) {
1757			.name = "cam_cc_cci_2_clk",
1758			.parent_hws = (const struct clk_hw*[]) {
1759				&cam_cc_cci_2_clk_src.clkr.hw,
1760			},
1761			.num_parents = 1,
1762			.flags = CLK_SET_RATE_PARENT,
1763			.ops = &clk_branch2_ops,
1764		},
1765	},
1766};
1767
1768static struct clk_branch cam_cc_core_ahb_clk = {
1769	.halt_reg = 0x132d0,
1770	.halt_check = BRANCH_HALT_DELAY,
1771	.clkr = {
1772		.enable_reg = 0x132d0,
1773		.enable_mask = BIT(0),
1774		.hw.init = &(const struct clk_init_data) {
1775			.name = "cam_cc_core_ahb_clk",
1776			.parent_hws = (const struct clk_hw*[]) {
1777				&cam_cc_slow_ahb_clk_src.clkr.hw,
1778			},
1779			.num_parents = 1,
1780			.flags = CLK_SET_RATE_PARENT,
1781			.ops = &clk_branch2_ops,
1782		},
1783	},
1784};
1785
1786static struct clk_branch cam_cc_cpas_ahb_clk = {
1787	.halt_reg = 0x13220,
1788	.halt_check = BRANCH_HALT,
1789	.clkr = {
1790		.enable_reg = 0x13220,
1791		.enable_mask = BIT(0),
1792		.hw.init = &(const struct clk_init_data) {
1793			.name = "cam_cc_cpas_ahb_clk",
1794			.parent_hws = (const struct clk_hw*[]) {
1795				&cam_cc_slow_ahb_clk_src.clkr.hw,
1796			},
1797			.num_parents = 1,
1798			.flags = CLK_SET_RATE_PARENT,
1799			.ops = &clk_branch2_ops,
1800		},
1801	},
1802};
1803
1804static struct clk_branch cam_cc_cpas_bps_clk = {
1805	.halt_reg = 0x10074,
1806	.halt_check = BRANCH_HALT,
1807	.clkr = {
1808		.enable_reg = 0x10074,
1809		.enable_mask = BIT(0),
1810		.hw.init = &(const struct clk_init_data) {
1811			.name = "cam_cc_cpas_bps_clk",
1812			.parent_hws = (const struct clk_hw*[]) {
1813				&cam_cc_bps_clk_src.clkr.hw,
1814			},
1815			.num_parents = 1,
1816			.flags = CLK_SET_RATE_PARENT,
1817			.ops = &clk_branch2_ops,
1818		},
1819	},
1820};
1821
1822static struct clk_branch cam_cc_cpas_cre_clk = {
1823	.halt_reg = 0x13160,
1824	.halt_check = BRANCH_HALT,
1825	.clkr = {
1826		.enable_reg = 0x13160,
1827		.enable_mask = BIT(0),
1828		.hw.init = &(const struct clk_init_data) {
1829			.name = "cam_cc_cpas_cre_clk",
1830			.parent_hws = (const struct clk_hw*[]) {
1831				&cam_cc_cre_clk_src.clkr.hw,
1832			},
1833			.num_parents = 1,
1834			.flags = CLK_SET_RATE_PARENT,
1835			.ops = &clk_branch2_ops,
1836		},
1837	},
1838};
1839
1840static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
1841	.halt_reg = 0x1322c,
1842	.halt_check = BRANCH_HALT,
1843	.clkr = {
1844		.enable_reg = 0x1322c,
1845		.enable_mask = BIT(0),
1846		.hw.init = &(const struct clk_init_data) {
1847			.name = "cam_cc_cpas_fast_ahb_clk",
1848			.parent_hws = (const struct clk_hw*[]) {
1849				&cam_cc_fast_ahb_clk_src.clkr.hw,
1850			},
1851			.num_parents = 1,
1852			.flags = CLK_SET_RATE_PARENT,
1853			.ops = &clk_branch2_ops,
1854		},
1855	},
1856};
1857
1858static struct clk_branch cam_cc_cpas_ife_0_clk = {
1859	.halt_reg = 0x1103c,
1860	.halt_check = BRANCH_HALT,
1861	.clkr = {
1862		.enable_reg = 0x1103c,
1863		.enable_mask = BIT(0),
1864		.hw.init = &(const struct clk_init_data) {
1865			.name = "cam_cc_cpas_ife_0_clk",
1866			.parent_hws = (const struct clk_hw*[]) {
1867				&cam_cc_ife_0_clk_src.clkr.hw,
1868			},
1869			.num_parents = 1,
1870			.flags = CLK_SET_RATE_PARENT,
1871			.ops = &clk_branch2_ops,
1872		},
1873	},
1874};
1875
1876static struct clk_branch cam_cc_cpas_ife_1_clk = {
1877	.halt_reg = 0x1203c,
1878	.halt_check = BRANCH_HALT,
1879	.clkr = {
1880		.enable_reg = 0x1203c,
1881		.enable_mask = BIT(0),
1882		.hw.init = &(const struct clk_init_data) {
1883			.name = "cam_cc_cpas_ife_1_clk",
1884			.parent_hws = (const struct clk_hw*[]) {
1885				&cam_cc_ife_1_clk_src.clkr.hw,
1886			},
1887			.num_parents = 1,
1888			.flags = CLK_SET_RATE_PARENT,
1889			.ops = &clk_branch2_ops,
1890		},
1891	},
1892};
1893
1894static struct clk_branch cam_cc_cpas_ife_2_clk = {
1895	.halt_reg = 0x1208c,
1896	.halt_check = BRANCH_HALT,
1897	.clkr = {
1898		.enable_reg = 0x1208c,
1899		.enable_mask = BIT(0),
1900		.hw.init = &(const struct clk_init_data) {
1901			.name = "cam_cc_cpas_ife_2_clk",
1902			.parent_hws = (const struct clk_hw*[]) {
1903				&cam_cc_ife_2_clk_src.clkr.hw,
1904			},
1905			.num_parents = 1,
1906			.flags = CLK_SET_RATE_PARENT,
1907			.ops = &clk_branch2_ops,
1908		},
1909	},
1910};
1911
1912static struct clk_branch cam_cc_cpas_ife_lite_clk = {
1913	.halt_reg = 0x13024,
1914	.halt_check = BRANCH_HALT,
1915	.clkr = {
1916		.enable_reg = 0x13024,
1917		.enable_mask = BIT(0),
1918		.hw.init = &(const struct clk_init_data) {
1919			.name = "cam_cc_cpas_ife_lite_clk",
1920			.parent_hws = (const struct clk_hw*[]) {
1921				&cam_cc_ife_lite_clk_src.clkr.hw,
1922			},
1923			.num_parents = 1,
1924			.flags = CLK_SET_RATE_PARENT,
1925			.ops = &clk_branch2_ops,
1926		},
1927	},
1928};
1929
1930static struct clk_branch cam_cc_cpas_ipe_nps_clk = {
1931	.halt_reg = 0x100b8,
1932	.halt_check = BRANCH_HALT,
1933	.clkr = {
1934		.enable_reg = 0x100b8,
1935		.enable_mask = BIT(0),
1936		.hw.init = &(const struct clk_init_data) {
1937			.name = "cam_cc_cpas_ipe_nps_clk",
1938			.parent_hws = (const struct clk_hw*[]) {
1939				&cam_cc_ipe_nps_clk_src.clkr.hw,
1940			},
1941			.num_parents = 1,
1942			.flags = CLK_SET_RATE_PARENT,
1943			.ops = &clk_branch2_ops,
1944		},
1945	},
1946};
1947
1948static struct clk_branch cam_cc_cpas_sbi_clk = {
1949	.halt_reg = 0x10104,
1950	.halt_check = BRANCH_HALT,
1951	.clkr = {
1952		.enable_reg = 0x10104,
1953		.enable_mask = BIT(0),
1954		.hw.init = &(const struct clk_init_data) {
1955			.name = "cam_cc_cpas_sbi_clk",
1956			.parent_hws = (const struct clk_hw*[]) {
1957				&cam_cc_ife_0_clk_src.clkr.hw,
1958			},
1959			.num_parents = 1,
1960			.flags = CLK_SET_RATE_PARENT,
1961			.ops = &clk_branch2_ops,
1962		},
1963	},
1964};
1965
1966static struct clk_branch cam_cc_cpas_sfe_0_clk = {
1967	.halt_reg = 0x13090,
1968	.halt_check = BRANCH_HALT,
1969	.clkr = {
1970		.enable_reg = 0x13090,
1971		.enable_mask = BIT(0),
1972		.hw.init = &(const struct clk_init_data) {
1973			.name = "cam_cc_cpas_sfe_0_clk",
1974			.parent_hws = (const struct clk_hw*[]) {
1975				&cam_cc_sfe_0_clk_src.clkr.hw,
1976			},
1977			.num_parents = 1,
1978			.flags = CLK_SET_RATE_PARENT,
1979			.ops = &clk_branch2_ops,
1980		},
1981	},
1982};
1983
1984static struct clk_branch cam_cc_cpas_sfe_1_clk = {
1985	.halt_reg = 0x130e0,
1986	.halt_check = BRANCH_HALT,
1987	.clkr = {
1988		.enable_reg = 0x130e0,
1989		.enable_mask = BIT(0),
1990		.hw.init = &(const struct clk_init_data) {
1991			.name = "cam_cc_cpas_sfe_1_clk",
1992			.parent_hws = (const struct clk_hw*[]) {
1993				&cam_cc_sfe_1_clk_src.clkr.hw,
1994			},
1995			.num_parents = 1,
1996			.flags = CLK_SET_RATE_PARENT,
1997			.ops = &clk_branch2_ops,
1998		},
1999	},
2000};
2001
2002static struct clk_branch cam_cc_cpas_sfe_2_clk = {
2003	.halt_reg = 0x13130,
2004	.halt_check = BRANCH_HALT,
2005	.clkr = {
2006		.enable_reg = 0x13130,
2007		.enable_mask = BIT(0),
2008		.hw.init = &(const struct clk_init_data) {
2009			.name = "cam_cc_cpas_sfe_2_clk",
2010			.parent_hws = (const struct clk_hw*[]) {
2011				&cam_cc_sfe_2_clk_src.clkr.hw,
2012			},
2013			.num_parents = 1,
2014			.flags = CLK_SET_RATE_PARENT,
2015			.ops = &clk_branch2_ops,
2016		},
2017	},
2018};
2019
2020static struct clk_branch cam_cc_cre_ahb_clk = {
2021	.halt_reg = 0x13164,
2022	.halt_check = BRANCH_HALT,
2023	.clkr = {
2024		.enable_reg = 0x13164,
2025		.enable_mask = BIT(0),
2026		.hw.init = &(const struct clk_init_data) {
2027			.name = "cam_cc_cre_ahb_clk",
2028			.parent_hws = (const struct clk_hw*[]) {
2029				&cam_cc_slow_ahb_clk_src.clkr.hw,
2030			},
2031			.num_parents = 1,
2032			.flags = CLK_SET_RATE_PARENT,
2033			.ops = &clk_branch2_ops,
2034		},
2035	},
2036};
2037
2038static struct clk_branch cam_cc_cre_clk = {
2039	.halt_reg = 0x1315c,
2040	.halt_check = BRANCH_HALT,
2041	.clkr = {
2042		.enable_reg = 0x1315c,
2043		.enable_mask = BIT(0),
2044		.hw.init = &(const struct clk_init_data) {
2045			.name = "cam_cc_cre_clk",
2046			.parent_hws = (const struct clk_hw*[]) {
2047				&cam_cc_cre_clk_src.clkr.hw,
2048			},
2049			.num_parents = 1,
2050			.flags = CLK_SET_RATE_PARENT,
2051			.ops = &clk_branch2_ops,
2052		},
2053	},
2054};
2055
2056static struct clk_branch cam_cc_csi0phytimer_clk = {
2057	.halt_reg = 0x150f8,
2058	.halt_check = BRANCH_HALT,
2059	.clkr = {
2060		.enable_reg = 0x150f8,
2061		.enable_mask = BIT(0),
2062		.hw.init = &(const struct clk_init_data) {
2063			.name = "cam_cc_csi0phytimer_clk",
2064			.parent_hws = (const struct clk_hw*[]) {
2065				&cam_cc_csi0phytimer_clk_src.clkr.hw,
2066			},
2067			.num_parents = 1,
2068			.flags = CLK_SET_RATE_PARENT,
2069			.ops = &clk_branch2_ops,
2070		},
2071	},
2072};
2073
2074static struct clk_branch cam_cc_csi1phytimer_clk = {
2075	.halt_reg = 0x1511c,
2076	.halt_check = BRANCH_HALT,
2077	.clkr = {
2078		.enable_reg = 0x1511c,
2079		.enable_mask = BIT(0),
2080		.hw.init = &(const struct clk_init_data) {
2081			.name = "cam_cc_csi1phytimer_clk",
2082			.parent_hws = (const struct clk_hw*[]) {
2083				&cam_cc_csi1phytimer_clk_src.clkr.hw,
2084			},
2085			.num_parents = 1,
2086			.flags = CLK_SET_RATE_PARENT,
2087			.ops = &clk_branch2_ops,
2088		},
2089	},
2090};
2091
2092static struct clk_branch cam_cc_csi2phytimer_clk = {
2093	.halt_reg = 0x1513c,
2094	.halt_check = BRANCH_HALT,
2095	.clkr = {
2096		.enable_reg = 0x1513c,
2097		.enable_mask = BIT(0),
2098		.hw.init = &(const struct clk_init_data) {
2099			.name = "cam_cc_csi2phytimer_clk",
2100			.parent_hws = (const struct clk_hw*[]) {
2101				&cam_cc_csi2phytimer_clk_src.clkr.hw,
2102			},
2103			.num_parents = 1,
2104			.flags = CLK_SET_RATE_PARENT,
2105			.ops = &clk_branch2_ops,
2106		},
2107	},
2108};
2109
2110static struct clk_branch cam_cc_csi3phytimer_clk = {
2111	.halt_reg = 0x1515c,
2112	.halt_check = BRANCH_HALT,
2113	.clkr = {
2114		.enable_reg = 0x1515c,
2115		.enable_mask = BIT(0),
2116		.hw.init = &(const struct clk_init_data) {
2117			.name = "cam_cc_csi3phytimer_clk",
2118			.parent_hws = (const struct clk_hw*[]) {
2119				&cam_cc_csi3phytimer_clk_src.clkr.hw,
2120			},
2121			.num_parents = 1,
2122			.flags = CLK_SET_RATE_PARENT,
2123			.ops = &clk_branch2_ops,
2124		},
2125	},
2126};
2127
2128static struct clk_branch cam_cc_csi4phytimer_clk = {
2129	.halt_reg = 0x1517c,
2130	.halt_check = BRANCH_HALT,
2131	.clkr = {
2132		.enable_reg = 0x1517c,
2133		.enable_mask = BIT(0),
2134		.hw.init = &(const struct clk_init_data) {
2135			.name = "cam_cc_csi4phytimer_clk",
2136			.parent_hws = (const struct clk_hw*[]) {
2137				&cam_cc_csi4phytimer_clk_src.clkr.hw,
2138			},
2139			.num_parents = 1,
2140			.flags = CLK_SET_RATE_PARENT,
2141			.ops = &clk_branch2_ops,
2142		},
2143	},
2144};
2145
2146static struct clk_branch cam_cc_csi5phytimer_clk = {
2147	.halt_reg = 0x1519c,
2148	.halt_check = BRANCH_HALT,
2149	.clkr = {
2150		.enable_reg = 0x1519c,
2151		.enable_mask = BIT(0),
2152		.hw.init = &(const struct clk_init_data) {
2153			.name = "cam_cc_csi5phytimer_clk",
2154			.parent_hws = (const struct clk_hw*[]) {
2155				&cam_cc_csi5phytimer_clk_src.clkr.hw,
2156			},
2157			.num_parents = 1,
2158			.flags = CLK_SET_RATE_PARENT,
2159			.ops = &clk_branch2_ops,
2160		},
2161	},
2162};
2163
2164static struct clk_branch cam_cc_csi6phytimer_clk = {
2165	.halt_reg = 0x151bc,
2166	.halt_check = BRANCH_HALT,
2167	.clkr = {
2168		.enable_reg = 0x151bc,
2169		.enable_mask = BIT(0),
2170		.hw.init = &(const struct clk_init_data) {
2171			.name = "cam_cc_csi6phytimer_clk",
2172			.parent_hws = (const struct clk_hw*[]) {
2173				&cam_cc_csi6phytimer_clk_src.clkr.hw,
2174			},
2175			.num_parents = 1,
2176			.flags = CLK_SET_RATE_PARENT,
2177			.ops = &clk_branch2_ops,
2178		},
2179	},
2180};
2181
2182static struct clk_branch cam_cc_csi7phytimer_clk = {
2183	.halt_reg = 0x151dc,
2184	.halt_check = BRANCH_HALT,
2185	.clkr = {
2186		.enable_reg = 0x151dc,
2187		.enable_mask = BIT(0),
2188		.hw.init = &(const struct clk_init_data) {
2189			.name = "cam_cc_csi7phytimer_clk",
2190			.parent_hws = (const struct clk_hw*[]) {
2191				&cam_cc_csi7phytimer_clk_src.clkr.hw,
2192			},
2193			.num_parents = 1,
2194			.flags = CLK_SET_RATE_PARENT,
2195			.ops = &clk_branch2_ops,
2196		},
2197	},
2198};
2199
2200static struct clk_branch cam_cc_csid_clk = {
2201	.halt_reg = 0x13250,
2202	.halt_check = BRANCH_HALT,
2203	.clkr = {
2204		.enable_reg = 0x13250,
2205		.enable_mask = BIT(0),
2206		.hw.init = &(const struct clk_init_data) {
2207			.name = "cam_cc_csid_clk",
2208			.parent_hws = (const struct clk_hw*[]) {
2209				&cam_cc_csid_clk_src.clkr.hw,
2210			},
2211			.num_parents = 1,
2212			.flags = CLK_SET_RATE_PARENT,
2213			.ops = &clk_branch2_ops,
2214		},
2215	},
2216};
2217
2218static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
2219	.halt_reg = 0x15100,
2220	.halt_check = BRANCH_HALT,
2221	.clkr = {
2222		.enable_reg = 0x15100,
2223		.enable_mask = BIT(0),
2224		.hw.init = &(const struct clk_init_data) {
2225			.name = "cam_cc_csid_csiphy_rx_clk",
2226			.parent_hws = (const struct clk_hw*[]) {
2227				&cam_cc_cphy_rx_clk_src.clkr.hw,
2228			},
2229			.num_parents = 1,
2230			.flags = CLK_SET_RATE_PARENT,
2231			.ops = &clk_branch2_ops,
2232		},
2233	},
2234};
2235
2236static struct clk_branch cam_cc_csiphy0_clk = {
2237	.halt_reg = 0x150fc,
2238	.halt_check = BRANCH_HALT,
2239	.clkr = {
2240		.enable_reg = 0x150fc,
2241		.enable_mask = BIT(0),
2242		.hw.init = &(const struct clk_init_data) {
2243			.name = "cam_cc_csiphy0_clk",
2244			.parent_hws = (const struct clk_hw*[]) {
2245				&cam_cc_cphy_rx_clk_src.clkr.hw,
2246			},
2247			.num_parents = 1,
2248			.flags = CLK_SET_RATE_PARENT,
2249			.ops = &clk_branch2_ops,
2250		},
2251	},
2252};
2253
2254static struct clk_branch cam_cc_csiphy1_clk = {
2255	.halt_reg = 0x15120,
2256	.halt_check = BRANCH_HALT,
2257	.clkr = {
2258		.enable_reg = 0x15120,
2259		.enable_mask = BIT(0),
2260		.hw.init = &(const struct clk_init_data) {
2261			.name = "cam_cc_csiphy1_clk",
2262			.parent_hws = (const struct clk_hw*[]) {
2263				&cam_cc_cphy_rx_clk_src.clkr.hw,
2264			},
2265			.num_parents = 1,
2266			.flags = CLK_SET_RATE_PARENT,
2267			.ops = &clk_branch2_ops,
2268		},
2269	},
2270};
2271
2272static struct clk_branch cam_cc_csiphy2_clk = {
2273	.halt_reg = 0x15140,
2274	.halt_check = BRANCH_HALT,
2275	.clkr = {
2276		.enable_reg = 0x15140,
2277		.enable_mask = BIT(0),
2278		.hw.init = &(const struct clk_init_data) {
2279			.name = "cam_cc_csiphy2_clk",
2280			.parent_hws = (const struct clk_hw*[]) {
2281				&cam_cc_cphy_rx_clk_src.clkr.hw,
2282			},
2283			.num_parents = 1,
2284			.flags = CLK_SET_RATE_PARENT,
2285			.ops = &clk_branch2_ops,
2286		},
2287	},
2288};
2289
2290static struct clk_branch cam_cc_csiphy3_clk = {
2291	.halt_reg = 0x15160,
2292	.halt_check = BRANCH_HALT,
2293	.clkr = {
2294		.enable_reg = 0x15160,
2295		.enable_mask = BIT(0),
2296		.hw.init = &(const struct clk_init_data) {
2297			.name = "cam_cc_csiphy3_clk",
2298			.parent_hws = (const struct clk_hw*[]) {
2299				&cam_cc_cphy_rx_clk_src.clkr.hw,
2300			},
2301			.num_parents = 1,
2302			.flags = CLK_SET_RATE_PARENT,
2303			.ops = &clk_branch2_ops,
2304		},
2305	},
2306};
2307
2308static struct clk_branch cam_cc_csiphy4_clk = {
2309	.halt_reg = 0x15180,
2310	.halt_check = BRANCH_HALT,
2311	.clkr = {
2312		.enable_reg = 0x15180,
2313		.enable_mask = BIT(0),
2314		.hw.init = &(const struct clk_init_data) {
2315			.name = "cam_cc_csiphy4_clk",
2316			.parent_hws = (const struct clk_hw*[]) {
2317				&cam_cc_cphy_rx_clk_src.clkr.hw,
2318			},
2319			.num_parents = 1,
2320			.flags = CLK_SET_RATE_PARENT,
2321			.ops = &clk_branch2_ops,
2322		},
2323	},
2324};
2325
2326static struct clk_branch cam_cc_csiphy5_clk = {
2327	.halt_reg = 0x151a0,
2328	.halt_check = BRANCH_HALT,
2329	.clkr = {
2330		.enable_reg = 0x151a0,
2331		.enable_mask = BIT(0),
2332		.hw.init = &(const struct clk_init_data) {
2333			.name = "cam_cc_csiphy5_clk",
2334			.parent_hws = (const struct clk_hw*[]) {
2335				&cam_cc_cphy_rx_clk_src.clkr.hw,
2336			},
2337			.num_parents = 1,
2338			.flags = CLK_SET_RATE_PARENT,
2339			.ops = &clk_branch2_ops,
2340		},
2341	},
2342};
2343
2344static struct clk_branch cam_cc_csiphy6_clk = {
2345	.halt_reg = 0x151c0,
2346	.halt_check = BRANCH_HALT,
2347	.clkr = {
2348		.enable_reg = 0x151c0,
2349		.enable_mask = BIT(0),
2350		.hw.init = &(const struct clk_init_data) {
2351			.name = "cam_cc_csiphy6_clk",
2352			.parent_hws = (const struct clk_hw*[]) {
2353				&cam_cc_cphy_rx_clk_src.clkr.hw,
2354			},
2355			.num_parents = 1,
2356			.flags = CLK_SET_RATE_PARENT,
2357			.ops = &clk_branch2_ops,
2358		},
2359	},
2360};
2361
2362static struct clk_branch cam_cc_csiphy7_clk = {
2363	.halt_reg = 0x151e0,
2364	.halt_check = BRANCH_HALT,
2365	.clkr = {
2366		.enable_reg = 0x151e0,
2367		.enable_mask = BIT(0),
2368		.hw.init = &(const struct clk_init_data) {
2369			.name = "cam_cc_csiphy7_clk",
2370			.parent_hws = (const struct clk_hw*[]) {
2371				&cam_cc_cphy_rx_clk_src.clkr.hw,
2372			},
2373			.num_parents = 1,
2374			.flags = CLK_SET_RATE_PARENT,
2375			.ops = &clk_branch2_ops,
2376		},
2377	},
2378};
2379
2380static struct clk_branch cam_cc_icp_ahb_clk = {
2381	.halt_reg = 0x131c8,
2382	.halt_check = BRANCH_HALT,
2383	.clkr = {
2384		.enable_reg = 0x131c8,
2385		.enable_mask = BIT(0),
2386		.hw.init = &(const struct clk_init_data) {
2387			.name = "cam_cc_icp_ahb_clk",
2388			.parent_hws = (const struct clk_hw*[]) {
2389				&cam_cc_slow_ahb_clk_src.clkr.hw,
2390			},
2391			.num_parents = 1,
2392			.flags = CLK_SET_RATE_PARENT,
2393			.ops = &clk_branch2_ops,
2394		},
2395	},
2396};
2397
2398static struct clk_branch cam_cc_icp_clk = {
2399	.halt_reg = 0x131bc,
2400	.halt_check = BRANCH_HALT,
2401	.clkr = {
2402		.enable_reg = 0x131bc,
2403		.enable_mask = BIT(0),
2404		.hw.init = &(const struct clk_init_data) {
2405			.name = "cam_cc_icp_clk",
2406			.parent_hws = (const struct clk_hw*[]) {
2407				&cam_cc_icp_clk_src.clkr.hw,
2408			},
2409			.num_parents = 1,
2410			.flags = CLK_SET_RATE_PARENT,
2411			.ops = &clk_branch2_ops,
2412		},
2413	},
2414};
2415
2416static struct clk_branch cam_cc_ife_0_clk = {
2417	.halt_reg = 0x11030,
2418	.halt_check = BRANCH_HALT,
2419	.clkr = {
2420		.enable_reg = 0x11030,
2421		.enable_mask = BIT(0),
2422		.hw.init = &(const struct clk_init_data) {
2423			.name = "cam_cc_ife_0_clk",
2424			.parent_hws = (const struct clk_hw*[]) {
2425				&cam_cc_ife_0_clk_src.clkr.hw,
2426			},
2427			.num_parents = 1,
2428			.flags = CLK_SET_RATE_PARENT,
2429			.ops = &clk_branch2_ops,
2430		},
2431	},
2432};
2433
2434static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
2435	.halt_reg = 0x11048,
2436	.halt_check = BRANCH_HALT,
2437	.clkr = {
2438		.enable_reg = 0x11048,
2439		.enable_mask = BIT(0),
2440		.hw.init = &(const struct clk_init_data) {
2441			.name = "cam_cc_ife_0_fast_ahb_clk",
2442			.parent_hws = (const struct clk_hw*[]) {
2443				&cam_cc_fast_ahb_clk_src.clkr.hw,
2444			},
2445			.num_parents = 1,
2446			.flags = CLK_SET_RATE_PARENT,
2447			.ops = &clk_branch2_ops,
2448		},
2449	},
2450};
2451
2452static struct clk_branch cam_cc_ife_0_shift_clk = {
2453	.halt_reg = 0x11064,
2454	.halt_check = BRANCH_HALT_VOTED,
2455	.clkr = {
2456		.enable_reg = 0x11064,
2457		.enable_mask = BIT(0),
2458		.hw.init = &(const struct clk_init_data) {
2459			.name = "cam_cc_ife_0_shift_clk",
2460			.parent_hws = (const struct clk_hw*[]) {
2461				&cam_cc_xo_clk_src.clkr.hw,
2462			},
2463			.num_parents = 1,
2464			.flags = CLK_SET_RATE_PARENT,
2465			.ops = &clk_branch2_ops,
2466		},
2467	},
2468};
2469
2470static struct clk_branch cam_cc_ife_1_clk = {
2471	.halt_reg = 0x12030,
2472	.halt_check = BRANCH_HALT,
2473	.clkr = {
2474		.enable_reg = 0x12030,
2475		.enable_mask = BIT(0),
2476		.hw.init = &(const struct clk_init_data) {
2477			.name = "cam_cc_ife_1_clk",
2478			.parent_hws = (const struct clk_hw*[]) {
2479				&cam_cc_ife_1_clk_src.clkr.hw,
2480			},
2481			.num_parents = 1,
2482			.flags = CLK_SET_RATE_PARENT,
2483			.ops = &clk_branch2_ops,
2484		},
2485	},
2486};
2487
2488static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
2489	.halt_reg = 0x12048,
2490	.halt_check = BRANCH_HALT,
2491	.clkr = {
2492		.enable_reg = 0x12048,
2493		.enable_mask = BIT(0),
2494		.hw.init = &(const struct clk_init_data) {
2495			.name = "cam_cc_ife_1_fast_ahb_clk",
2496			.parent_hws = (const struct clk_hw*[]) {
2497				&cam_cc_fast_ahb_clk_src.clkr.hw,
2498			},
2499			.num_parents = 1,
2500			.flags = CLK_SET_RATE_PARENT,
2501			.ops = &clk_branch2_ops,
2502		},
2503	},
2504};
2505
2506static struct clk_branch cam_cc_ife_1_shift_clk = {
2507	.halt_reg = 0x1204c,
2508	.halt_check = BRANCH_HALT_VOTED,
2509	.clkr = {
2510		.enable_reg = 0x1204c,
2511		.enable_mask = BIT(0),
2512		.hw.init = &(const struct clk_init_data) {
2513			.name = "cam_cc_ife_1_shift_clk",
2514			.parent_hws = (const struct clk_hw*[]) {
2515				&cam_cc_xo_clk_src.clkr.hw,
2516			},
2517			.num_parents = 1,
2518			.flags = CLK_SET_RATE_PARENT,
2519			.ops = &clk_branch2_ops,
2520		},
2521	},
2522};
2523
2524static struct clk_branch cam_cc_ife_2_clk = {
2525	.halt_reg = 0x12080,
2526	.halt_check = BRANCH_HALT,
2527	.clkr = {
2528		.enable_reg = 0x12080,
2529		.enable_mask = BIT(0),
2530		.hw.init = &(const struct clk_init_data) {
2531			.name = "cam_cc_ife_2_clk",
2532			.parent_hws = (const struct clk_hw*[]) {
2533				&cam_cc_ife_2_clk_src.clkr.hw,
2534			},
2535			.num_parents = 1,
2536			.flags = CLK_SET_RATE_PARENT,
2537			.ops = &clk_branch2_ops,
2538		},
2539	},
2540};
2541
2542static struct clk_branch cam_cc_ife_2_fast_ahb_clk = {
2543	.halt_reg = 0x12098,
2544	.halt_check = BRANCH_HALT,
2545	.clkr = {
2546		.enable_reg = 0x12098,
2547		.enable_mask = BIT(0),
2548		.hw.init = &(const struct clk_init_data) {
2549			.name = "cam_cc_ife_2_fast_ahb_clk",
2550			.parent_hws = (const struct clk_hw*[]) {
2551				&cam_cc_fast_ahb_clk_src.clkr.hw,
2552			},
2553			.num_parents = 1,
2554			.flags = CLK_SET_RATE_PARENT,
2555			.ops = &clk_branch2_ops,
2556		},
2557	},
2558};
2559
2560static struct clk_branch cam_cc_ife_2_shift_clk = {
2561	.halt_reg = 0x1209c,
2562	.halt_check = BRANCH_HALT_VOTED,
2563	.clkr = {
2564		.enable_reg = 0x1209c,
2565		.enable_mask = BIT(0),
2566		.hw.init = &(const struct clk_init_data) {
2567			.name = "cam_cc_ife_2_shift_clk",
2568			.parent_hws = (const struct clk_hw*[]) {
2569				&cam_cc_xo_clk_src.clkr.hw,
2570			},
2571			.num_parents = 1,
2572			.flags = CLK_SET_RATE_PARENT,
2573			.ops = &clk_branch2_ops,
2574		},
2575	},
2576};
2577
2578static struct clk_branch cam_cc_ife_lite_ahb_clk = {
2579	.halt_reg = 0x13050,
2580	.halt_check = BRANCH_HALT,
2581	.clkr = {
2582		.enable_reg = 0x13050,
2583		.enable_mask = BIT(0),
2584		.hw.init = &(const struct clk_init_data) {
2585			.name = "cam_cc_ife_lite_ahb_clk",
2586			.parent_hws = (const struct clk_hw*[]) {
2587				&cam_cc_slow_ahb_clk_src.clkr.hw,
2588			},
2589			.num_parents = 1,
2590			.flags = CLK_SET_RATE_PARENT,
2591			.ops = &clk_branch2_ops,
2592		},
2593	},
2594};
2595
2596static struct clk_branch cam_cc_ife_lite_clk = {
2597	.halt_reg = 0x13018,
2598	.halt_check = BRANCH_HALT,
2599	.clkr = {
2600		.enable_reg = 0x13018,
2601		.enable_mask = BIT(0),
2602		.hw.init = &(const struct clk_init_data) {
2603			.name = "cam_cc_ife_lite_clk",
2604			.parent_hws = (const struct clk_hw*[]) {
2605				&cam_cc_ife_lite_clk_src.clkr.hw,
2606			},
2607			.num_parents = 1,
2608			.flags = CLK_SET_RATE_PARENT,
2609			.ops = &clk_branch2_ops,
2610		},
2611	},
2612};
2613
2614static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
2615	.halt_reg = 0x1304c,
2616	.halt_check = BRANCH_HALT,
2617	.clkr = {
2618		.enable_reg = 0x1304c,
2619		.enable_mask = BIT(0),
2620		.hw.init = &(const struct clk_init_data) {
2621			.name = "cam_cc_ife_lite_cphy_rx_clk",
2622			.parent_hws = (const struct clk_hw*[]) {
2623				&cam_cc_cphy_rx_clk_src.clkr.hw,
2624			},
2625			.num_parents = 1,
2626			.flags = CLK_SET_RATE_PARENT,
2627			.ops = &clk_branch2_ops,
2628		},
2629	},
2630};
2631
2632static struct clk_branch cam_cc_ife_lite_csid_clk = {
2633	.halt_reg = 0x13040,
2634	.halt_check = BRANCH_HALT,
2635	.clkr = {
2636		.enable_reg = 0x13040,
2637		.enable_mask = BIT(0),
2638		.hw.init = &(const struct clk_init_data) {
2639			.name = "cam_cc_ife_lite_csid_clk",
2640			.parent_hws = (const struct clk_hw*[]) {
2641				&cam_cc_ife_lite_csid_clk_src.clkr.hw,
2642			},
2643			.num_parents = 1,
2644			.flags = CLK_SET_RATE_PARENT,
2645			.ops = &clk_branch2_ops,
2646		},
2647	},
2648};
2649
2650static struct clk_branch cam_cc_ipe_nps_ahb_clk = {
2651	.halt_reg = 0x100d0,
2652	.halt_check = BRANCH_HALT,
2653	.clkr = {
2654		.enable_reg = 0x100d0,
2655		.enable_mask = BIT(0),
2656		.hw.init = &(const struct clk_init_data) {
2657			.name = "cam_cc_ipe_nps_ahb_clk",
2658			.parent_hws = (const struct clk_hw*[]) {
2659				&cam_cc_slow_ahb_clk_src.clkr.hw,
2660			},
2661			.num_parents = 1,
2662			.flags = CLK_SET_RATE_PARENT,
2663			.ops = &clk_branch2_ops,
2664		},
2665	},
2666};
2667
2668static struct clk_branch cam_cc_ipe_nps_clk = {
2669	.halt_reg = 0x100ac,
2670	.halt_check = BRANCH_HALT,
2671	.clkr = {
2672		.enable_reg = 0x100ac,
2673		.enable_mask = BIT(0),
2674		.hw.init = &(const struct clk_init_data) {
2675			.name = "cam_cc_ipe_nps_clk",
2676			.parent_hws = (const struct clk_hw*[]) {
2677				&cam_cc_ipe_nps_clk_src.clkr.hw,
2678			},
2679			.num_parents = 1,
2680			.flags = CLK_SET_RATE_PARENT,
2681			.ops = &clk_branch2_ops,
2682		},
2683	},
2684};
2685
2686static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = {
2687	.halt_reg = 0x100d4,
2688	.halt_check = BRANCH_HALT,
2689	.clkr = {
2690		.enable_reg = 0x100d4,
2691		.enable_mask = BIT(0),
2692		.hw.init = &(const struct clk_init_data) {
2693			.name = "cam_cc_ipe_nps_fast_ahb_clk",
2694			.parent_hws = (const struct clk_hw*[]) {
2695				&cam_cc_fast_ahb_clk_src.clkr.hw,
2696			},
2697			.num_parents = 1,
2698			.flags = CLK_SET_RATE_PARENT,
2699			.ops = &clk_branch2_ops,
2700		},
2701	},
2702};
2703
2704static struct clk_branch cam_cc_ipe_pps_clk = {
2705	.halt_reg = 0x100bc,
2706	.halt_check = BRANCH_HALT,
2707	.clkr = {
2708		.enable_reg = 0x100bc,
2709		.enable_mask = BIT(0),
2710		.hw.init = &(const struct clk_init_data) {
2711			.name = "cam_cc_ipe_pps_clk",
2712			.parent_hws = (const struct clk_hw*[]) {
2713				&cam_cc_ipe_nps_clk_src.clkr.hw,
2714			},
2715			.num_parents = 1,
2716			.flags = CLK_SET_RATE_PARENT,
2717			.ops = &clk_branch2_ops,
2718		},
2719	},
2720};
2721
2722static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = {
2723	.halt_reg = 0x100d8,
2724	.halt_check = BRANCH_HALT,
2725	.clkr = {
2726		.enable_reg = 0x100d8,
2727		.enable_mask = BIT(0),
2728		.hw.init = &(const struct clk_init_data) {
2729			.name = "cam_cc_ipe_pps_fast_ahb_clk",
2730			.parent_hws = (const struct clk_hw*[]) {
2731				&cam_cc_fast_ahb_clk_src.clkr.hw,
2732			},
2733			.num_parents = 1,
2734			.flags = CLK_SET_RATE_PARENT,
2735			.ops = &clk_branch2_ops,
2736		},
2737	},
2738};
2739
2740static struct clk_branch cam_cc_ipe_shift_clk = {
2741	.halt_reg = 0x100dc,
2742	.halt_check = BRANCH_HALT_VOTED,
2743	.clkr = {
2744		.enable_reg = 0x100dc,
2745		.enable_mask = BIT(0),
2746		.hw.init = &(const struct clk_init_data) {
2747			.name = "cam_cc_ipe_shift_clk",
2748			.parent_hws = (const struct clk_hw*[]) {
2749				&cam_cc_xo_clk_src.clkr.hw,
2750			},
2751			.num_parents = 1,
2752			.flags = CLK_SET_RATE_PARENT,
2753			.ops = &clk_branch2_ops,
2754		},
2755	},
2756};
2757
2758static struct clk_branch cam_cc_jpeg_1_clk = {
2759	.halt_reg = 0x1318c,
2760	.halt_check = BRANCH_HALT,
2761	.clkr = {
2762		.enable_reg = 0x1318c,
2763		.enable_mask = BIT(0),
2764		.hw.init = &(const struct clk_init_data) {
2765			.name = "cam_cc_jpeg_1_clk",
2766			.parent_hws = (const struct clk_hw*[]) {
2767				&cam_cc_jpeg_clk_src.clkr.hw,
2768			},
2769			.num_parents = 1,
2770			.flags = CLK_SET_RATE_PARENT,
2771			.ops = &clk_branch2_ops,
2772		},
2773	},
2774};
2775
2776static struct clk_branch cam_cc_jpeg_clk = {
2777	.halt_reg = 0x13180,
2778	.halt_check = BRANCH_HALT,
2779	.clkr = {
2780		.enable_reg = 0x13180,
2781		.enable_mask = BIT(0),
2782		.hw.init = &(const struct clk_init_data) {
2783			.name = "cam_cc_jpeg_clk",
2784			.parent_hws = (const struct clk_hw*[]) {
2785				&cam_cc_jpeg_clk_src.clkr.hw,
2786			},
2787			.num_parents = 1,
2788			.flags = CLK_SET_RATE_PARENT,
2789			.ops = &clk_branch2_ops,
2790		},
2791	},
2792};
2793
2794static struct clk_branch cam_cc_mclk0_clk = {
2795	.halt_reg = 0x15018,
2796	.halt_check = BRANCH_HALT,
2797	.clkr = {
2798		.enable_reg = 0x15018,
2799		.enable_mask = BIT(0),
2800		.hw.init = &(const struct clk_init_data) {
2801			.name = "cam_cc_mclk0_clk",
2802			.parent_hws = (const struct clk_hw*[]) {
2803				&cam_cc_mclk0_clk_src.clkr.hw,
2804			},
2805			.num_parents = 1,
2806			.flags = CLK_SET_RATE_PARENT,
2807			.ops = &clk_branch2_ops,
2808		},
2809	},
2810};
2811
2812static struct clk_branch cam_cc_mclk1_clk = {
2813	.halt_reg = 0x15034,
2814	.halt_check = BRANCH_HALT,
2815	.clkr = {
2816		.enable_reg = 0x15034,
2817		.enable_mask = BIT(0),
2818		.hw.init = &(const struct clk_init_data) {
2819			.name = "cam_cc_mclk1_clk",
2820			.parent_hws = (const struct clk_hw*[]) {
2821				&cam_cc_mclk1_clk_src.clkr.hw,
2822			},
2823			.num_parents = 1,
2824			.flags = CLK_SET_RATE_PARENT,
2825			.ops = &clk_branch2_ops,
2826		},
2827	},
2828};
2829
2830static struct clk_branch cam_cc_mclk2_clk = {
2831	.halt_reg = 0x15050,
2832	.halt_check = BRANCH_HALT,
2833	.clkr = {
2834		.enable_reg = 0x15050,
2835		.enable_mask = BIT(0),
2836		.hw.init = &(const struct clk_init_data) {
2837			.name = "cam_cc_mclk2_clk",
2838			.parent_hws = (const struct clk_hw*[]) {
2839				&cam_cc_mclk2_clk_src.clkr.hw,
2840			},
2841			.num_parents = 1,
2842			.flags = CLK_SET_RATE_PARENT,
2843			.ops = &clk_branch2_ops,
2844		},
2845	},
2846};
2847
2848static struct clk_branch cam_cc_mclk3_clk = {
2849	.halt_reg = 0x1506c,
2850	.halt_check = BRANCH_HALT,
2851	.clkr = {
2852		.enable_reg = 0x1506c,
2853		.enable_mask = BIT(0),
2854		.hw.init = &(const struct clk_init_data) {
2855			.name = "cam_cc_mclk3_clk",
2856			.parent_hws = (const struct clk_hw*[]) {
2857				&cam_cc_mclk3_clk_src.clkr.hw,
2858			},
2859			.num_parents = 1,
2860			.flags = CLK_SET_RATE_PARENT,
2861			.ops = &clk_branch2_ops,
2862		},
2863	},
2864};
2865
2866static struct clk_branch cam_cc_mclk4_clk = {
2867	.halt_reg = 0x15088,
2868	.halt_check = BRANCH_HALT,
2869	.clkr = {
2870		.enable_reg = 0x15088,
2871		.enable_mask = BIT(0),
2872		.hw.init = &(const struct clk_init_data) {
2873			.name = "cam_cc_mclk4_clk",
2874			.parent_hws = (const struct clk_hw*[]) {
2875				&cam_cc_mclk4_clk_src.clkr.hw,
2876			},
2877			.num_parents = 1,
2878			.flags = CLK_SET_RATE_PARENT,
2879			.ops = &clk_branch2_ops,
2880		},
2881	},
2882};
2883
2884static struct clk_branch cam_cc_mclk5_clk = {
2885	.halt_reg = 0x150a4,
2886	.halt_check = BRANCH_HALT,
2887	.clkr = {
2888		.enable_reg = 0x150a4,
2889		.enable_mask = BIT(0),
2890		.hw.init = &(const struct clk_init_data) {
2891			.name = "cam_cc_mclk5_clk",
2892			.parent_hws = (const struct clk_hw*[]) {
2893				&cam_cc_mclk5_clk_src.clkr.hw,
2894			},
2895			.num_parents = 1,
2896			.flags = CLK_SET_RATE_PARENT,
2897			.ops = &clk_branch2_ops,
2898		},
2899	},
2900};
2901
2902static struct clk_branch cam_cc_mclk6_clk = {
2903	.halt_reg = 0x150c0,
2904	.halt_check = BRANCH_HALT,
2905	.clkr = {
2906		.enable_reg = 0x150c0,
2907		.enable_mask = BIT(0),
2908		.hw.init = &(const struct clk_init_data) {
2909			.name = "cam_cc_mclk6_clk",
2910			.parent_hws = (const struct clk_hw*[]) {
2911				&cam_cc_mclk6_clk_src.clkr.hw,
2912			},
2913			.num_parents = 1,
2914			.flags = CLK_SET_RATE_PARENT,
2915			.ops = &clk_branch2_ops,
2916		},
2917	},
2918};
2919
2920static struct clk_branch cam_cc_mclk7_clk = {
2921	.halt_reg = 0x150dc,
2922	.halt_check = BRANCH_HALT,
2923	.clkr = {
2924		.enable_reg = 0x150dc,
2925		.enable_mask = BIT(0),
2926		.hw.init = &(const struct clk_init_data) {
2927			.name = "cam_cc_mclk7_clk",
2928			.parent_hws = (const struct clk_hw*[]) {
2929				&cam_cc_mclk7_clk_src.clkr.hw,
2930			},
2931			.num_parents = 1,
2932			.flags = CLK_SET_RATE_PARENT,
2933			.ops = &clk_branch2_ops,
2934		},
2935	},
2936};
2937
2938static struct clk_branch cam_cc_qdss_debug_clk = {
2939	.halt_reg = 0x132b4,
2940	.halt_check = BRANCH_HALT,
2941	.clkr = {
2942		.enable_reg = 0x132b4,
2943		.enable_mask = BIT(0),
2944		.hw.init = &(const struct clk_init_data) {
2945			.name = "cam_cc_qdss_debug_clk",
2946			.parent_hws = (const struct clk_hw*[]) {
2947				&cam_cc_qdss_debug_clk_src.clkr.hw,
2948			},
2949			.num_parents = 1,
2950			.flags = CLK_SET_RATE_PARENT,
2951			.ops = &clk_branch2_ops,
2952		},
2953	},
2954};
2955
2956static struct clk_branch cam_cc_qdss_debug_xo_clk = {
2957	.halt_reg = 0x132b8,
2958	.halt_check = BRANCH_HALT,
2959	.clkr = {
2960		.enable_reg = 0x132b8,
2961		.enable_mask = BIT(0),
2962		.hw.init = &(const struct clk_init_data) {
2963			.name = "cam_cc_qdss_debug_xo_clk",
2964			.parent_hws = (const struct clk_hw*[]) {
2965				&cam_cc_xo_clk_src.clkr.hw,
2966			},
2967			.num_parents = 1,
2968			.flags = CLK_SET_RATE_PARENT,
2969			.ops = &clk_branch2_ops,
2970		},
2971	},
2972};
2973
2974static struct clk_branch cam_cc_sbi_clk = {
2975	.halt_reg = 0x100f8,
2976	.halt_check = BRANCH_HALT,
2977	.clkr = {
2978		.enable_reg = 0x100f8,
2979		.enable_mask = BIT(0),
2980		.hw.init = &(const struct clk_init_data) {
2981			.name = "cam_cc_sbi_clk",
2982			.parent_hws = (const struct clk_hw*[]) {
2983				&cam_cc_ife_0_clk_src.clkr.hw,
2984			},
2985			.num_parents = 1,
2986			.flags = CLK_SET_RATE_PARENT,
2987			.ops = &clk_branch2_ops,
2988		},
2989	},
2990};
2991
2992static struct clk_branch cam_cc_sbi_fast_ahb_clk = {
2993	.halt_reg = 0x10108,
2994	.halt_check = BRANCH_HALT,
2995	.clkr = {
2996		.enable_reg = 0x10108,
2997		.enable_mask = BIT(0),
2998		.hw.init = &(const struct clk_init_data) {
2999			.name = "cam_cc_sbi_fast_ahb_clk",
3000			.parent_hws = (const struct clk_hw*[]) {
3001				&cam_cc_fast_ahb_clk_src.clkr.hw,
3002			},
3003			.num_parents = 1,
3004			.flags = CLK_SET_RATE_PARENT,
3005			.ops = &clk_branch2_ops,
3006		},
3007	},
3008};
3009
3010static struct clk_branch cam_cc_sbi_shift_clk = {
3011	.halt_reg = 0x1010c,
3012	.halt_check = BRANCH_HALT_VOTED,
3013	.clkr = {
3014		.enable_reg = 0x1010c,
3015		.enable_mask = BIT(0),
3016		.hw.init = &(const struct clk_init_data) {
3017			.name = "cam_cc_sbi_shift_clk",
3018			.parent_hws = (const struct clk_hw*[]) {
3019				&cam_cc_xo_clk_src.clkr.hw,
3020			},
3021			.num_parents = 1,
3022			.flags = CLK_SET_RATE_PARENT,
3023			.ops = &clk_branch2_ops,
3024		},
3025	},
3026};
3027
3028static struct clk_branch cam_cc_sfe_0_clk = {
3029	.halt_reg = 0x13084,
3030	.halt_check = BRANCH_HALT,
3031	.clkr = {
3032		.enable_reg = 0x13084,
3033		.enable_mask = BIT(0),
3034		.hw.init = &(const struct clk_init_data) {
3035			.name = "cam_cc_sfe_0_clk",
3036			.parent_hws = (const struct clk_hw*[]) {
3037				&cam_cc_sfe_0_clk_src.clkr.hw,
3038			},
3039			.num_parents = 1,
3040			.flags = CLK_SET_RATE_PARENT,
3041			.ops = &clk_branch2_ops,
3042		},
3043	},
3044};
3045
3046static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = {
3047	.halt_reg = 0x1309c,
3048	.halt_check = BRANCH_HALT,
3049	.clkr = {
3050		.enable_reg = 0x1309c,
3051		.enable_mask = BIT(0),
3052		.hw.init = &(const struct clk_init_data) {
3053			.name = "cam_cc_sfe_0_fast_ahb_clk",
3054			.parent_hws = (const struct clk_hw*[]) {
3055				&cam_cc_fast_ahb_clk_src.clkr.hw,
3056			},
3057			.num_parents = 1,
3058			.flags = CLK_SET_RATE_PARENT,
3059			.ops = &clk_branch2_ops,
3060		},
3061	},
3062};
3063
3064static struct clk_branch cam_cc_sfe_0_shift_clk = {
3065	.halt_reg = 0x130a0,
3066	.halt_check = BRANCH_HALT_VOTED,
3067	.clkr = {
3068		.enable_reg = 0x130a0,
3069		.enable_mask = BIT(0),
3070		.hw.init = &(const struct clk_init_data) {
3071			.name = "cam_cc_sfe_0_shift_clk",
3072			.parent_hws = (const struct clk_hw*[]) {
3073				&cam_cc_xo_clk_src.clkr.hw,
3074			},
3075			.num_parents = 1,
3076			.flags = CLK_SET_RATE_PARENT,
3077			.ops = &clk_branch2_ops,
3078		},
3079	},
3080};
3081
3082static struct clk_branch cam_cc_sfe_1_clk = {
3083	.halt_reg = 0x130d4,
3084	.halt_check = BRANCH_HALT,
3085	.clkr = {
3086		.enable_reg = 0x130d4,
3087		.enable_mask = BIT(0),
3088		.hw.init = &(const struct clk_init_data) {
3089			.name = "cam_cc_sfe_1_clk",
3090			.parent_hws = (const struct clk_hw*[]) {
3091				&cam_cc_sfe_1_clk_src.clkr.hw,
3092			},
3093			.num_parents = 1,
3094			.flags = CLK_SET_RATE_PARENT,
3095			.ops = &clk_branch2_ops,
3096		},
3097	},
3098};
3099
3100static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
3101	.halt_reg = 0x130ec,
3102	.halt_check = BRANCH_HALT,
3103	.clkr = {
3104		.enable_reg = 0x130ec,
3105		.enable_mask = BIT(0),
3106		.hw.init = &(const struct clk_init_data) {
3107			.name = "cam_cc_sfe_1_fast_ahb_clk",
3108			.parent_hws = (const struct clk_hw*[]) {
3109				&cam_cc_fast_ahb_clk_src.clkr.hw,
3110			},
3111			.num_parents = 1,
3112			.flags = CLK_SET_RATE_PARENT,
3113			.ops = &clk_branch2_ops,
3114		},
3115	},
3116};
3117
3118static struct clk_branch cam_cc_sfe_1_shift_clk = {
3119	.halt_reg = 0x130f0,
3120	.halt_check = BRANCH_HALT_VOTED,
3121	.clkr = {
3122		.enable_reg = 0x130f0,
3123		.enable_mask = BIT(0),
3124		.hw.init = &(const struct clk_init_data) {
3125			.name = "cam_cc_sfe_1_shift_clk",
3126			.parent_hws = (const struct clk_hw*[]) {
3127				&cam_cc_xo_clk_src.clkr.hw,
3128			},
3129			.num_parents = 1,
3130			.flags = CLK_SET_RATE_PARENT,
3131			.ops = &clk_branch2_ops,
3132		},
3133	},
3134};
3135
3136static struct clk_branch cam_cc_sfe_2_clk = {
3137	.halt_reg = 0x13124,
3138	.halt_check = BRANCH_HALT,
3139	.clkr = {
3140		.enable_reg = 0x13124,
3141		.enable_mask = BIT(0),
3142		.hw.init = &(const struct clk_init_data) {
3143			.name = "cam_cc_sfe_2_clk",
3144			.parent_hws = (const struct clk_hw*[]) {
3145				&cam_cc_sfe_2_clk_src.clkr.hw,
3146			},
3147			.num_parents = 1,
3148			.flags = CLK_SET_RATE_PARENT,
3149			.ops = &clk_branch2_ops,
3150		},
3151	},
3152};
3153
3154static struct clk_branch cam_cc_sfe_2_fast_ahb_clk = {
3155	.halt_reg = 0x1313c,
3156	.halt_check = BRANCH_HALT,
3157	.clkr = {
3158		.enable_reg = 0x1313c,
3159		.enable_mask = BIT(0),
3160		.hw.init = &(const struct clk_init_data) {
3161			.name = "cam_cc_sfe_2_fast_ahb_clk",
3162			.parent_hws = (const struct clk_hw*[]) {
3163				&cam_cc_fast_ahb_clk_src.clkr.hw,
3164			},
3165			.num_parents = 1,
3166			.flags = CLK_SET_RATE_PARENT,
3167			.ops = &clk_branch2_ops,
3168		},
3169	},
3170};
3171
3172static struct clk_branch cam_cc_sfe_2_shift_clk = {
3173	.halt_reg = 0x13140,
3174	.halt_check = BRANCH_HALT_VOTED,
3175	.clkr = {
3176		.enable_reg = 0x13140,
3177		.enable_mask = BIT(0),
3178		.hw.init = &(const struct clk_init_data) {
3179			.name = "cam_cc_sfe_2_shift_clk",
3180			.parent_hws = (const struct clk_hw*[]) {
3181				&cam_cc_xo_clk_src.clkr.hw,
3182			},
3183			.num_parents = 1,
3184			.flags = CLK_SET_RATE_PARENT,
3185			.ops = &clk_branch2_ops,
3186		},
3187	},
3188};
3189
3190static struct clk_branch cam_cc_titan_top_shift_clk = {
3191	.halt_reg = 0x1330c,
3192	.halt_check = BRANCH_HALT_VOTED,
3193	.clkr = {
3194		.enable_reg = 0x1330c,
3195		.enable_mask = BIT(0),
3196		.hw.init = &(const struct clk_init_data) {
3197			.name = "cam_cc_titan_top_shift_clk",
3198			.parent_hws = (const struct clk_hw*[]) {
3199				&cam_cc_xo_clk_src.clkr.hw,
3200			},
3201			.num_parents = 1,
3202			.flags = CLK_SET_RATE_PARENT,
3203			.ops = &clk_branch2_ops,
3204		},
3205	},
3206};
3207
3208static struct gdsc cam_cc_titan_top_gdsc = {
3209	.gdscr = 0x132bc,
3210	.en_rest_wait_val = 0x2,
3211	.en_few_wait_val = 0x2,
3212	.clk_dis_wait_val = 0xf,
3213	.pd = {
3214		.name = "cam_cc_titan_top_gdsc",
3215	},
3216	.pwrsts = PWRSTS_OFF_ON,
3217	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3218};
3219
3220static struct gdsc cam_cc_bps_gdsc = {
3221	.gdscr = 0x10004,
3222	.en_rest_wait_val = 0x2,
3223	.en_few_wait_val = 0x2,
3224	.clk_dis_wait_val = 0xf,
3225	.pd = {
3226		.name = "cam_cc_bps_gdsc",
3227	},
3228	.pwrsts = PWRSTS_OFF_ON,
3229	.parent = &cam_cc_titan_top_gdsc.pd,
3230	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3231};
3232
3233static struct gdsc cam_cc_ife_0_gdsc = {
3234	.gdscr = 0x11004,
3235	.en_rest_wait_val = 0x2,
3236	.en_few_wait_val = 0x2,
3237	.clk_dis_wait_val = 0xf,
3238	.pd = {
3239		.name = "cam_cc_ife_0_gdsc",
3240	},
3241	.pwrsts = PWRSTS_OFF_ON,
3242	.parent = &cam_cc_titan_top_gdsc.pd,
3243	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3244};
3245
3246static struct gdsc cam_cc_ife_1_gdsc = {
3247	.gdscr = 0x12004,
3248	.en_rest_wait_val = 0x2,
3249	.en_few_wait_val = 0x2,
3250	.clk_dis_wait_val = 0xf,
3251	.pd = {
3252		.name = "cam_cc_ife_1_gdsc",
3253	},
3254	.pwrsts = PWRSTS_OFF_ON,
3255	.parent = &cam_cc_titan_top_gdsc.pd,
3256	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3257};
3258
3259static struct gdsc cam_cc_ife_2_gdsc = {
3260	.gdscr = 0x12054,
3261	.en_rest_wait_val = 0x2,
3262	.en_few_wait_val = 0x2,
3263	.clk_dis_wait_val = 0xf,
3264	.pd = {
3265		.name = "cam_cc_ife_2_gdsc",
3266	},
3267	.pwrsts = PWRSTS_OFF_ON,
3268	.parent = &cam_cc_titan_top_gdsc.pd,
3269	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3270};
3271
3272static struct gdsc cam_cc_ipe_0_gdsc = {
3273	.gdscr = 0x10080,
3274	.en_rest_wait_val = 0x2,
3275	.en_few_wait_val = 0x2,
3276	.clk_dis_wait_val = 0xf,
3277	.pd = {
3278		.name = "cam_cc_ipe_0_gdsc",
3279	},
3280	.pwrsts = PWRSTS_OFF_ON,
3281	.parent = &cam_cc_titan_top_gdsc.pd,
3282	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3283};
3284
3285static struct gdsc cam_cc_sbi_gdsc = {
3286	.gdscr = 0x100e4,
3287	.en_rest_wait_val = 0x2,
3288	.en_few_wait_val = 0x2,
3289	.clk_dis_wait_val = 0xf,
3290	.pd = {
3291		.name = "cam_cc_sbi_gdsc",
3292	},
3293	.pwrsts = PWRSTS_OFF_ON,
3294	.parent = &cam_cc_titan_top_gdsc.pd,
3295	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3296};
3297
3298static struct gdsc cam_cc_sfe_0_gdsc = {
3299	.gdscr = 0x13058,
3300	.en_rest_wait_val = 0x2,
3301	.en_few_wait_val = 0x2,
3302	.clk_dis_wait_val = 0xf,
3303	.pd = {
3304		.name = "cam_cc_sfe_0_gdsc",
3305	},
3306	.pwrsts = PWRSTS_OFF_ON,
3307	.parent = &cam_cc_titan_top_gdsc.pd,
3308	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3309};
3310
3311static struct gdsc cam_cc_sfe_1_gdsc = {
3312	.gdscr = 0x130a8,
3313	.en_rest_wait_val = 0x2,
3314	.en_few_wait_val = 0x2,
3315	.clk_dis_wait_val = 0xf,
3316	.pd = {
3317		.name = "cam_cc_sfe_1_gdsc",
3318	},
3319	.pwrsts = PWRSTS_OFF_ON,
3320	.parent = &cam_cc_titan_top_gdsc.pd,
3321	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3322};
3323
3324static struct gdsc cam_cc_sfe_2_gdsc = {
3325	.gdscr = 0x130f8,
3326	.en_rest_wait_val = 0x2,
3327	.en_few_wait_val = 0x2,
3328	.clk_dis_wait_val = 0xf,
3329	.pd = {
3330		.name = "cam_cc_sfe_2_gdsc",
3331	},
3332	.pwrsts = PWRSTS_OFF_ON,
3333	.parent = &cam_cc_titan_top_gdsc.pd,
3334	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3335};
3336
3337static struct clk_regmap *cam_cc_sm8650_clocks[] = {
3338	[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
3339	[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
3340	[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
3341	[CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr,
3342	[CAM_CC_BPS_SHIFT_CLK] = &cam_cc_bps_shift_clk.clkr,
3343	[CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr,
3344	[CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr,
3345	[CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr,
3346	[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
3347	[CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr,
3348	[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
3349	[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
3350	[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
3351	[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
3352	[CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr,
3353	[CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr,
3354	[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
3355	[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
3356	[CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr,
3357	[CAM_CC_CPAS_CRE_CLK] = &cam_cc_cpas_cre_clk.clkr,
3358	[CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
3359	[CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
3360	[CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
3361	[CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr,
3362	[CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
3363	[CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr,
3364	[CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr,
3365	[CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr,
3366	[CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr,
3367	[CAM_CC_CPAS_SFE_2_CLK] = &cam_cc_cpas_sfe_2_clk.clkr,
3368	[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
3369	[CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr,
3370	[CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr,
3371	[CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr,
3372	[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
3373	[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
3374	[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
3375	[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
3376	[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
3377	[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
3378	[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
3379	[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
3380	[CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
3381	[CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
3382	[CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
3383	[CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
3384	[CAM_CC_CSI6PHYTIMER_CLK] = &cam_cc_csi6phytimer_clk.clkr,
3385	[CAM_CC_CSI6PHYTIMER_CLK_SRC] = &cam_cc_csi6phytimer_clk_src.clkr,
3386	[CAM_CC_CSI7PHYTIMER_CLK] = &cam_cc_csi7phytimer_clk.clkr,
3387	[CAM_CC_CSI7PHYTIMER_CLK_SRC] = &cam_cc_csi7phytimer_clk_src.clkr,
3388	[CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
3389	[CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
3390	[CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
3391	[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
3392	[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
3393	[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
3394	[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
3395	[CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
3396	[CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
3397	[CAM_CC_CSIPHY6_CLK] = &cam_cc_csiphy6_clk.clkr,
3398	[CAM_CC_CSIPHY7_CLK] = &cam_cc_csiphy7_clk.clkr,
3399	[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
3400	[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
3401	[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
3402	[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
3403	[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
3404	[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
3405	[CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
3406	[CAM_CC_IFE_0_SHIFT_CLK] = &cam_cc_ife_0_shift_clk.clkr,
3407	[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
3408	[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
3409	[CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
3410	[CAM_CC_IFE_1_SHIFT_CLK] = &cam_cc_ife_1_shift_clk.clkr,
3411	[CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
3412	[CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
3413	[CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr,
3414	[CAM_CC_IFE_2_SHIFT_CLK] = &cam_cc_ife_2_shift_clk.clkr,
3415	[CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
3416	[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
3417	[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
3418	[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
3419	[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
3420	[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
3421	[CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr,
3422	[CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr,
3423	[CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr,
3424	[CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr,
3425	[CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr,
3426	[CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr,
3427	[CAM_CC_IPE_SHIFT_CLK] = &cam_cc_ipe_shift_clk.clkr,
3428	[CAM_CC_JPEG_1_CLK] = &cam_cc_jpeg_1_clk.clkr,
3429	[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
3430	[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
3431	[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
3432	[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
3433	[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
3434	[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
3435	[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
3436	[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
3437	[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
3438	[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
3439	[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
3440	[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
3441	[CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
3442	[CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
3443	[CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
3444	[CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
3445	[CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr,
3446	[CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr,
3447	[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
3448	[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
3449	[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
3450	[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
3451	[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
3452	[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
3453	[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
3454	[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
3455	[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
3456	[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
3457	[CAM_CC_PLL5] = &cam_cc_pll5.clkr,
3458	[CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
3459	[CAM_CC_PLL6] = &cam_cc_pll6.clkr,
3460	[CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
3461	[CAM_CC_PLL7] = &cam_cc_pll7.clkr,
3462	[CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr,
3463	[CAM_CC_PLL8] = &cam_cc_pll8.clkr,
3464	[CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr,
3465	[CAM_CC_PLL9] = &cam_cc_pll9.clkr,
3466	[CAM_CC_PLL9_OUT_EVEN] = &cam_cc_pll9_out_even.clkr,
3467	[CAM_CC_PLL9_OUT_ODD] = &cam_cc_pll9_out_odd.clkr,
3468	[CAM_CC_PLL10] = &cam_cc_pll10.clkr,
3469	[CAM_CC_PLL10_OUT_EVEN] = &cam_cc_pll10_out_even.clkr,
3470	[CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr,
3471	[CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr,
3472	[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
3473	[CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
3474	[CAM_CC_SBI_FAST_AHB_CLK] = &cam_cc_sbi_fast_ahb_clk.clkr,
3475	[CAM_CC_SBI_SHIFT_CLK] = &cam_cc_sbi_shift_clk.clkr,
3476	[CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
3477	[CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr,
3478	[CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr,
3479	[CAM_CC_SFE_0_SHIFT_CLK] = &cam_cc_sfe_0_shift_clk.clkr,
3480	[CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr,
3481	[CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr,
3482	[CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr,
3483	[CAM_CC_SFE_1_SHIFT_CLK] = &cam_cc_sfe_1_shift_clk.clkr,
3484	[CAM_CC_SFE_2_CLK] = &cam_cc_sfe_2_clk.clkr,
3485	[CAM_CC_SFE_2_CLK_SRC] = &cam_cc_sfe_2_clk_src.clkr,
3486	[CAM_CC_SFE_2_FAST_AHB_CLK] = &cam_cc_sfe_2_fast_ahb_clk.clkr,
3487	[CAM_CC_SFE_2_SHIFT_CLK] = &cam_cc_sfe_2_shift_clk.clkr,
3488	[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
3489	[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
3490	[CAM_CC_TITAN_TOP_SHIFT_CLK] = &cam_cc_titan_top_shift_clk.clkr,
3491	[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
3492};
3493
3494static struct gdsc *cam_cc_sm8650_gdscs[] = {
3495	[CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc,
3496	[CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc,
3497	[CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc,
3498	[CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc,
3499	[CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc,
3500	[CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc,
3501	[CAM_CC_SBI_GDSC] = &cam_cc_sbi_gdsc,
3502	[CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc,
3503	[CAM_CC_SFE_1_GDSC] = &cam_cc_sfe_1_gdsc,
3504	[CAM_CC_SFE_2_GDSC] = &cam_cc_sfe_2_gdsc,
3505};
3506
3507static const struct qcom_reset_map cam_cc_sm8650_resets[] = {
3508	[CAM_CC_BPS_BCR] = { 0x10000 },
3509	[CAM_CC_DRV_BCR] = { 0x13310 },
3510	[CAM_CC_ICP_BCR] = { 0x131a0 },
3511	[CAM_CC_IFE_0_BCR] = { 0x11000 },
3512	[CAM_CC_IFE_1_BCR] = { 0x12000 },
3513	[CAM_CC_IFE_2_BCR] = { 0x12050 },
3514	[CAM_CC_IPE_0_BCR] = { 0x1007c },
3515	[CAM_CC_QDSS_DEBUG_BCR] = { 0x13298 },
3516	[CAM_CC_SBI_BCR] = { 0x100e0 },
3517	[CAM_CC_SFE_0_BCR] = { 0x13054 },
3518	[CAM_CC_SFE_1_BCR] = { 0x130a4 },
3519	[CAM_CC_SFE_2_BCR] = { 0x130f4 },
3520};
3521
3522static struct clk_alpha_pll *cam_cc_sm8650_plls[] = {
3523	&cam_cc_pll0,
3524	&cam_cc_pll1,
3525	&cam_cc_pll2,
3526	&cam_cc_pll3,
3527	&cam_cc_pll4,
3528	&cam_cc_pll5,
3529	&cam_cc_pll6,
3530	&cam_cc_pll7,
3531	&cam_cc_pll8,
3532	&cam_cc_pll9,
3533	&cam_cc_pll10,
3534};
3535
3536static u32 cam_cc_sm8650_critical_cbcrs[] = {
3537	0x132ec, /* CAM_CC_GDSC_CLK */
3538	0x13308, /* CAM_CC_SLEEP_CLK */
3539	0x13314, /* CAM_CC_DRV_XO_CLK */
3540	0x13318, /* CAM_CC_DRV_AHB_CLK */
3541};
3542
3543static const struct regmap_config cam_cc_sm8650_regmap_config = {
3544	.reg_bits = 32,
3545	.reg_stride = 4,
3546	.val_bits = 32,
3547	.max_register = 0x1603c,
3548	.fast_io = true,
3549};
3550
3551static struct qcom_cc_driver_data cam_cc_sm8650_driver_data = {
3552	.alpha_plls = cam_cc_sm8650_plls,
3553	.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8650_plls),
3554	.clk_cbcrs = cam_cc_sm8650_critical_cbcrs,
3555	.num_clk_cbcrs = ARRAY_SIZE(cam_cc_sm8650_critical_cbcrs),
3556};
3557
3558static const struct qcom_cc_desc cam_cc_sm8650_desc = {
3559	.config = &cam_cc_sm8650_regmap_config,
3560	.clks = cam_cc_sm8650_clocks,
3561	.num_clks = ARRAY_SIZE(cam_cc_sm8650_clocks),
3562	.resets = cam_cc_sm8650_resets,
3563	.num_resets = ARRAY_SIZE(cam_cc_sm8650_resets),
3564	.gdscs = cam_cc_sm8650_gdscs,
3565	.num_gdscs = ARRAY_SIZE(cam_cc_sm8650_gdscs),
3566	.use_rpm = true,
3567	.driver_data = &cam_cc_sm8650_driver_data,
3568};
3569
3570static const struct of_device_id cam_cc_sm8650_match_table[] = {
3571	{ .compatible = "qcom,sm8650-camcc" },
3572	{ }
3573};
3574MODULE_DEVICE_TABLE(of, cam_cc_sm8650_match_table);
3575
3576static int cam_cc_sm8650_probe(struct platform_device *pdev)
3577{
3578	return qcom_cc_probe(pdev, &cam_cc_sm8650_desc);
3579}
3580
3581static struct platform_driver cam_cc_sm8650_driver = {
3582	.probe = cam_cc_sm8650_probe,
3583	.driver = {
3584		.name = "camcc-sm8650",
3585		.of_match_table = cam_cc_sm8650_match_table,
3586	},
3587};
3588
3589module_platform_driver(cam_cc_sm8650_driver);
3590
3591MODULE_DESCRIPTION("QTI CAMCC SM8650 Driver");
3592MODULE_LICENSE("GPL");