camcc-sm8550.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/mod_devicetable.h>
   8#include <linux/module.h>
   9#include <linux/platform_device.h>
  10#include <linux/regmap.h>
  11
  12#include <dt-bindings/clock/qcom,sm8550-camcc.h>
  13
  14#include "clk-alpha-pll.h"
  15#include "clk-branch.h"
  16#include "clk-rcg.h"
  17#include "clk-regmap.h"
  18#include "common.h"
  19#include "gdsc.h"
  20#include "reset.h"
  21
  22enum {
  23	DT_IFACE,
  24	DT_BI_TCXO,
  25	DT_BI_TCXO_AO,
  26	DT_SLEEP_CLK,
  27};
  28
  29enum {
  30	P_BI_TCXO,
  31	P_BI_TCXO_AO,
  32	P_CAM_CC_PLL0_OUT_EVEN,
  33	P_CAM_CC_PLL0_OUT_MAIN,
  34	P_CAM_CC_PLL0_OUT_ODD,
  35	P_CAM_CC_PLL1_OUT_EVEN,
  36	P_CAM_CC_PLL2_OUT_EVEN,
  37	P_CAM_CC_PLL2_OUT_MAIN,
  38	P_CAM_CC_PLL3_OUT_EVEN,
  39	P_CAM_CC_PLL4_OUT_EVEN,
  40	P_CAM_CC_PLL5_OUT_EVEN,
  41	P_CAM_CC_PLL6_OUT_EVEN,
  42	P_CAM_CC_PLL7_OUT_EVEN,
  43	P_CAM_CC_PLL8_OUT_EVEN,
  44	P_CAM_CC_PLL9_OUT_EVEN,
  45	P_CAM_CC_PLL9_OUT_ODD,
  46	P_CAM_CC_PLL10_OUT_EVEN,
  47	P_CAM_CC_PLL11_OUT_EVEN,
  48	P_CAM_CC_PLL12_OUT_EVEN,
  49	P_SLEEP_CLK,
  50};
  51
  52static const struct pll_vco lucid_ole_vco[] = {
  53	{ 249600000, 2300000000, 0 },
  54};
  55
  56static const struct pll_vco rivian_ole_vco[] = {
  57	{ 777000000, 1285000000, 0 },
  58};
  59
  60static const struct alpha_pll_config cam_cc_pll0_config = {
  61	.l = 0x3e,
  62	.alpha = 0x8000,
  63	.config_ctl_val = 0x20485699,
  64	.config_ctl_hi_val = 0x00182261,
  65	.config_ctl_hi1_val = 0x82aa299c,
  66	.test_ctl_val = 0x00000000,
  67	.test_ctl_hi_val = 0x00000003,
  68	.test_ctl_hi1_val = 0x00009000,
  69	.test_ctl_hi2_val = 0x00000034,
  70	.user_ctl_val = 0x00008400,
  71	.user_ctl_hi_val = 0x00000005,
  72};
  73
  74static struct clk_alpha_pll cam_cc_pll0 = {
  75	.offset = 0x0,
  76	.config = &cam_cc_pll0_config,
  77	.vco_table = lucid_ole_vco,
  78	.num_vco = ARRAY_SIZE(lucid_ole_vco),
  79	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
  80	.clkr = {
  81		.hw.init = &(const struct clk_init_data) {
  82			.name = "cam_cc_pll0",
  83			.parent_data = &(const struct clk_parent_data) {
  84				.index = DT_BI_TCXO,
  85			},
  86			.num_parents = 1,
  87			.ops = &clk_alpha_pll_lucid_evo_ops,
  88		},
  89	},
  90};
  91
  92static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
  93	{ 0x1, 2 },
  94	{ }
  95};
  96
  97static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
  98	.offset = 0x0,
  99	.post_div_shift = 10,
 100	.post_div_table = post_div_table_cam_cc_pll0_out_even,
 101	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
 102	.width = 4,
 103	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 104	.clkr.hw.init = &(const struct clk_init_data) {
 105		.name = "cam_cc_pll0_out_even",
 106		.parent_hws = (const struct clk_hw*[]) {
 107			&cam_cc_pll0.clkr.hw,
 108		},
 109		.num_parents = 1,
 110		.flags = CLK_SET_RATE_PARENT,
 111		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 112	},
 113};
 114
 115static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
 116	{ 0x2, 3 },
 117	{ }
 118};
 119
 120static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
 121	.offset = 0x0,
 122	.post_div_shift = 14,
 123	.post_div_table = post_div_table_cam_cc_pll0_out_odd,
 124	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
 125	.width = 4,
 126	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 127	.clkr.hw.init = &(const struct clk_init_data) {
 128		.name = "cam_cc_pll0_out_odd",
 129		.parent_hws = (const struct clk_hw*[]) {
 130			&cam_cc_pll0.clkr.hw,
 131		},
 132		.num_parents = 1,
 133		.flags = CLK_SET_RATE_PARENT,
 134		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 135	},
 136};
 137
 138static const struct alpha_pll_config cam_cc_pll1_config = {
 139	.l = 0x2f,
 140	.alpha = 0x6555,
 141	.config_ctl_val = 0x20485699,
 142	.config_ctl_hi_val = 0x00182261,
 143	.config_ctl_hi1_val = 0x82aa299c,
 144	.test_ctl_val = 0x00000000,
 145	.test_ctl_hi_val = 0x00000003,
 146	.test_ctl_hi1_val = 0x00009000,
 147	.test_ctl_hi2_val = 0x00000034,
 148	.user_ctl_val = 0x00000400,
 149	.user_ctl_hi_val = 0x00000005,
 150};
 151
 152static struct clk_alpha_pll cam_cc_pll1 = {
 153	.offset = 0x1000,
 154	.config = &cam_cc_pll1_config,
 155	.vco_table = lucid_ole_vco,
 156	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 157	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 158	.clkr = {
 159		.hw.init = &(const struct clk_init_data) {
 160			.name = "cam_cc_pll1",
 161			.parent_data = &(const struct clk_parent_data) {
 162				.index = DT_BI_TCXO,
 163			},
 164			.num_parents = 1,
 165			.ops = &clk_alpha_pll_lucid_evo_ops,
 166		},
 167	},
 168};
 169
 170static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
 171	{ 0x1, 2 },
 172	{ }
 173};
 174
 175static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
 176	.offset = 0x1000,
 177	.post_div_shift = 10,
 178	.post_div_table = post_div_table_cam_cc_pll1_out_even,
 179	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
 180	.width = 4,
 181	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 182	.clkr.hw.init = &(const struct clk_init_data) {
 183		.name = "cam_cc_pll1_out_even",
 184		.parent_hws = (const struct clk_hw*[]) {
 185			&cam_cc_pll1.clkr.hw,
 186		},
 187		.num_parents = 1,
 188		.flags = CLK_SET_RATE_PARENT,
 189		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 190	},
 191};
 192
 193static const struct alpha_pll_config cam_cc_pll2_config = {
 194	.l = 0x32,
 195	.alpha = 0x0,
 196	.config_ctl_val = 0x10000030,
 197	.config_ctl_hi_val = 0x80890263,
 198	.config_ctl_hi1_val = 0x00000217,
 199	.user_ctl_val = 0x00000000,
 200	.user_ctl_hi_val = 0x00100000,
 201};
 202
 203static struct clk_alpha_pll cam_cc_pll2 = {
 204	.offset = 0x2000,
 205	.config = &cam_cc_pll2_config,
 206	.vco_table = rivian_ole_vco,
 207	.num_vco = ARRAY_SIZE(rivian_ole_vco),
 208	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
 209	.clkr = {
 210		.hw.init = &(const struct clk_init_data) {
 211			.name = "cam_cc_pll2",
 212			.parent_data = &(const struct clk_parent_data) {
 213				.index = DT_BI_TCXO,
 214			},
 215			.num_parents = 1,
 216			.ops = &clk_alpha_pll_rivian_evo_ops,
 217		},
 218	},
 219};
 220
 221static const struct alpha_pll_config cam_cc_pll3_config = {
 222	.l = 0x30,
 223	.alpha = 0x8aaa,
 224	.config_ctl_val = 0x20485699,
 225	.config_ctl_hi_val = 0x00182261,
 226	.config_ctl_hi1_val = 0x82aa299c,
 227	.test_ctl_val = 0x00000000,
 228	.test_ctl_hi_val = 0x00000003,
 229	.test_ctl_hi1_val = 0x00009000,
 230	.test_ctl_hi2_val = 0x00000034,
 231	.user_ctl_val = 0x00000400,
 232	.user_ctl_hi_val = 0x00000005,
 233};
 234
 235static struct clk_alpha_pll cam_cc_pll3 = {
 236	.offset = 0x3000,
 237	.config = &cam_cc_pll3_config,
 238	.vco_table = lucid_ole_vco,
 239	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 240	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 241	.clkr = {
 242		.hw.init = &(const struct clk_init_data) {
 243			.name = "cam_cc_pll3",
 244			.parent_data = &(const struct clk_parent_data) {
 245				.index = DT_BI_TCXO,
 246			},
 247			.num_parents = 1,
 248			.ops = &clk_alpha_pll_lucid_evo_ops,
 249		},
 250	},
 251};
 252
 253static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
 254	{ 0x1, 2 },
 255	{ }
 256};
 257
 258static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
 259	.offset = 0x3000,
 260	.post_div_shift = 10,
 261	.post_div_table = post_div_table_cam_cc_pll3_out_even,
 262	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
 263	.width = 4,
 264	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 265	.clkr.hw.init = &(const struct clk_init_data) {
 266		.name = "cam_cc_pll3_out_even",
 267		.parent_hws = (const struct clk_hw*[]) {
 268			&cam_cc_pll3.clkr.hw,
 269		},
 270		.num_parents = 1,
 271		.flags = CLK_SET_RATE_PARENT,
 272		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 273	},
 274};
 275
 276static const struct alpha_pll_config cam_cc_pll4_config = {
 277	.l = 0x30,
 278	.alpha = 0x8aaa,
 279	.config_ctl_val = 0x20485699,
 280	.config_ctl_hi_val = 0x00182261,
 281	.config_ctl_hi1_val = 0x82aa299c,
 282	.test_ctl_val = 0x00000000,
 283	.test_ctl_hi_val = 0x00000003,
 284	.test_ctl_hi1_val = 0x00009000,
 285	.test_ctl_hi2_val = 0x00000034,
 286	.user_ctl_val = 0x00000400,
 287	.user_ctl_hi_val = 0x00000005,
 288};
 289
 290static struct clk_alpha_pll cam_cc_pll4 = {
 291	.offset = 0x4000,
 292	.config = &cam_cc_pll4_config,
 293	.vco_table = lucid_ole_vco,
 294	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 295	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 296	.clkr = {
 297		.hw.init = &(const struct clk_init_data) {
 298			.name = "cam_cc_pll4",
 299			.parent_data = &(const struct clk_parent_data) {
 300				.index = DT_BI_TCXO,
 301			},
 302			.num_parents = 1,
 303			.ops = &clk_alpha_pll_lucid_evo_ops,
 304		},
 305	},
 306};
 307
 308static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
 309	{ 0x1, 2 },
 310	{ }
 311};
 312
 313static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
 314	.offset = 0x4000,
 315	.post_div_shift = 10,
 316	.post_div_table = post_div_table_cam_cc_pll4_out_even,
 317	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
 318	.width = 4,
 319	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 320	.clkr.hw.init = &(const struct clk_init_data) {
 321		.name = "cam_cc_pll4_out_even",
 322		.parent_hws = (const struct clk_hw*[]) {
 323			&cam_cc_pll4.clkr.hw,
 324		},
 325		.num_parents = 1,
 326		.flags = CLK_SET_RATE_PARENT,
 327		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 328	},
 329};
 330
 331static const struct alpha_pll_config cam_cc_pll5_config = {
 332	.l = 0x30,
 333	.alpha = 0x8aaa,
 334	.config_ctl_val = 0x20485699,
 335	.config_ctl_hi_val = 0x00182261,
 336	.config_ctl_hi1_val = 0x82aa299c,
 337	.test_ctl_val = 0x00000000,
 338	.test_ctl_hi_val = 0x00000003,
 339	.test_ctl_hi1_val = 0x00009000,
 340	.test_ctl_hi2_val = 0x00000034,
 341	.user_ctl_val = 0x00000400,
 342	.user_ctl_hi_val = 0x00000005,
 343};
 344
 345static struct clk_alpha_pll cam_cc_pll5 = {
 346	.offset = 0x5000,
 347	.config = &cam_cc_pll5_config,
 348	.vco_table = lucid_ole_vco,
 349	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 350	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 351	.clkr = {
 352		.hw.init = &(const struct clk_init_data) {
 353			.name = "cam_cc_pll5",
 354			.parent_data = &(const struct clk_parent_data) {
 355				.index = DT_BI_TCXO,
 356			},
 357			.num_parents = 1,
 358			.ops = &clk_alpha_pll_lucid_evo_ops,
 359		},
 360	},
 361};
 362
 363static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
 364	{ 0x1, 2 },
 365	{ }
 366};
 367
 368static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
 369	.offset = 0x5000,
 370	.post_div_shift = 10,
 371	.post_div_table = post_div_table_cam_cc_pll5_out_even,
 372	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
 373	.width = 4,
 374	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 375	.clkr.hw.init = &(const struct clk_init_data) {
 376		.name = "cam_cc_pll5_out_even",
 377		.parent_hws = (const struct clk_hw*[]) {
 378			&cam_cc_pll5.clkr.hw,
 379		},
 380		.num_parents = 1,
 381		.flags = CLK_SET_RATE_PARENT,
 382		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 383	},
 384};
 385
 386static const struct alpha_pll_config cam_cc_pll6_config = {
 387	.l = 0x30,
 388	.alpha = 0x8aaa,
 389	.config_ctl_val = 0x20485699,
 390	.config_ctl_hi_val = 0x00182261,
 391	.config_ctl_hi1_val = 0x82aa299c,
 392	.test_ctl_val = 0x00000000,
 393	.test_ctl_hi_val = 0x00000003,
 394	.test_ctl_hi1_val = 0x00009000,
 395	.test_ctl_hi2_val = 0x00000034,
 396	.user_ctl_val = 0x00000400,
 397	.user_ctl_hi_val = 0x00000005,
 398};
 399
 400static struct clk_alpha_pll cam_cc_pll6 = {
 401	.offset = 0x6000,
 402	.config = &cam_cc_pll6_config,
 403	.vco_table = lucid_ole_vco,
 404	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 405	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 406	.clkr = {
 407		.hw.init = &(const struct clk_init_data) {
 408			.name = "cam_cc_pll6",
 409			.parent_data = &(const struct clk_parent_data) {
 410				.index = DT_BI_TCXO,
 411			},
 412			.num_parents = 1,
 413			.ops = &clk_alpha_pll_lucid_evo_ops,
 414		},
 415	},
 416};
 417
 418static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
 419	{ 0x1, 2 },
 420	{ }
 421};
 422
 423static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
 424	.offset = 0x6000,
 425	.post_div_shift = 10,
 426	.post_div_table = post_div_table_cam_cc_pll6_out_even,
 427	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
 428	.width = 4,
 429	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 430	.clkr.hw.init = &(const struct clk_init_data) {
 431		.name = "cam_cc_pll6_out_even",
 432		.parent_hws = (const struct clk_hw*[]) {
 433			&cam_cc_pll6.clkr.hw,
 434		},
 435		.num_parents = 1,
 436		.flags = CLK_SET_RATE_PARENT,
 437		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 438	},
 439};
 440
 441static const struct alpha_pll_config cam_cc_pll7_config = {
 442	.l = 0x30,
 443	.alpha = 0x8aaa,
 444	.config_ctl_val = 0x20485699,
 445	.config_ctl_hi_val = 0x00182261,
 446	.config_ctl_hi1_val = 0x82aa299c,
 447	.test_ctl_val = 0x00000000,
 448	.test_ctl_hi_val = 0x00000003,
 449	.test_ctl_hi1_val = 0x00009000,
 450	.test_ctl_hi2_val = 0x00000034,
 451	.user_ctl_val = 0x00000400,
 452	.user_ctl_hi_val = 0x00000005,
 453};
 454
 455static struct clk_alpha_pll cam_cc_pll7 = {
 456	.offset = 0x7000,
 457	.config = &cam_cc_pll7_config,
 458	.vco_table = lucid_ole_vco,
 459	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 460	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 461	.clkr = {
 462		.hw.init = &(const struct clk_init_data) {
 463			.name = "cam_cc_pll7",
 464			.parent_data = &(const struct clk_parent_data) {
 465				.index = DT_BI_TCXO,
 466			},
 467			.num_parents = 1,
 468			.ops = &clk_alpha_pll_lucid_evo_ops,
 469		},
 470	},
 471};
 472
 473static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
 474	{ 0x1, 2 },
 475	{ }
 476};
 477
 478static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
 479	.offset = 0x7000,
 480	.post_div_shift = 10,
 481	.post_div_table = post_div_table_cam_cc_pll7_out_even,
 482	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even),
 483	.width = 4,
 484	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 485	.clkr.hw.init = &(const struct clk_init_data) {
 486		.name = "cam_cc_pll7_out_even",
 487		.parent_hws = (const struct clk_hw*[]) {
 488			&cam_cc_pll7.clkr.hw,
 489		},
 490		.num_parents = 1,
 491		.flags = CLK_SET_RATE_PARENT,
 492		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 493	},
 494};
 495
 496static const struct alpha_pll_config cam_cc_pll8_config = {
 497	.l = 0x14,
 498	.alpha = 0xd555,
 499	.config_ctl_val = 0x20485699,
 500	.config_ctl_hi_val = 0x00182261,
 501	.config_ctl_hi1_val = 0x82aa299c,
 502	.test_ctl_val = 0x00000000,
 503	.test_ctl_hi_val = 0x00000003,
 504	.test_ctl_hi1_val = 0x00009000,
 505	.test_ctl_hi2_val = 0x00000034,
 506	.user_ctl_val = 0x00000400,
 507	.user_ctl_hi_val = 0x00000005,
 508};
 509
 510static struct clk_alpha_pll cam_cc_pll8 = {
 511	.offset = 0x8000,
 512	.config = &cam_cc_pll8_config,
 513	.vco_table = lucid_ole_vco,
 514	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 515	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 516	.clkr = {
 517		.hw.init = &(const struct clk_init_data) {
 518			.name = "cam_cc_pll8",
 519			.parent_data = &(const struct clk_parent_data) {
 520				.index = DT_BI_TCXO,
 521			},
 522			.num_parents = 1,
 523			.ops = &clk_alpha_pll_lucid_evo_ops,
 524		},
 525	},
 526};
 527
 528static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
 529	{ 0x1, 2 },
 530	{ }
 531};
 532
 533static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
 534	.offset = 0x8000,
 535	.post_div_shift = 10,
 536	.post_div_table = post_div_table_cam_cc_pll8_out_even,
 537	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even),
 538	.width = 4,
 539	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 540	.clkr.hw.init = &(const struct clk_init_data) {
 541		.name = "cam_cc_pll8_out_even",
 542		.parent_hws = (const struct clk_hw*[]) {
 543			&cam_cc_pll8.clkr.hw,
 544		},
 545		.num_parents = 1,
 546		.flags = CLK_SET_RATE_PARENT,
 547		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 548	},
 549};
 550
 551static const struct alpha_pll_config cam_cc_pll9_config = {
 552	.l = 0x32,
 553	.alpha = 0x0,
 554	.config_ctl_val = 0x20485699,
 555	.config_ctl_hi_val = 0x00182261,
 556	.config_ctl_hi1_val = 0x82aa299c,
 557	.test_ctl_val = 0x00000000,
 558	.test_ctl_hi_val = 0x00000003,
 559	.test_ctl_hi1_val = 0x00009000,
 560	.test_ctl_hi2_val = 0x00000034,
 561	.user_ctl_val = 0x00000400,
 562	.user_ctl_hi_val = 0x00000005,
 563};
 564
 565static struct clk_alpha_pll cam_cc_pll9 = {
 566	.offset = 0x9000,
 567	.config = &cam_cc_pll9_config,
 568	.vco_table = lucid_ole_vco,
 569	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 570	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 571	.clkr = {
 572		.hw.init = &(const struct clk_init_data) {
 573			.name = "cam_cc_pll9",
 574			.parent_data = &(const struct clk_parent_data) {
 575				.index = DT_BI_TCXO,
 576			},
 577			.num_parents = 1,
 578			.ops = &clk_alpha_pll_lucid_evo_ops,
 579		},
 580	},
 581};
 582
 583static const struct clk_div_table post_div_table_cam_cc_pll9_out_even[] = {
 584	{ 0x1, 2 },
 585	{ }
 586};
 587
 588static struct clk_alpha_pll_postdiv cam_cc_pll9_out_even = {
 589	.offset = 0x9000,
 590	.post_div_shift = 10,
 591	.post_div_table = post_div_table_cam_cc_pll9_out_even,
 592	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_even),
 593	.width = 4,
 594	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 595	.clkr.hw.init = &(const struct clk_init_data) {
 596		.name = "cam_cc_pll9_out_even",
 597		.parent_hws = (const struct clk_hw*[]) {
 598			&cam_cc_pll9.clkr.hw,
 599		},
 600		.num_parents = 1,
 601		.flags = CLK_SET_RATE_PARENT,
 602		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 603	},
 604};
 605
 606static const struct alpha_pll_config cam_cc_pll10_config = {
 607	.l = 0x30,
 608	.alpha = 0x8aaa,
 609	.config_ctl_val = 0x20485699,
 610	.config_ctl_hi_val = 0x00182261,
 611	.config_ctl_hi1_val = 0x82aa299c,
 612	.test_ctl_val = 0x00000000,
 613	.test_ctl_hi_val = 0x00000003,
 614	.test_ctl_hi1_val = 0x00009000,
 615	.test_ctl_hi2_val = 0x00000034,
 616	.user_ctl_val = 0x00000400,
 617	.user_ctl_hi_val = 0x00000005,
 618};
 619
 620static struct clk_alpha_pll cam_cc_pll10 = {
 621	.offset = 0xa000,
 622	.config = &cam_cc_pll10_config,
 623	.vco_table = lucid_ole_vco,
 624	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 625	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 626	.clkr = {
 627		.hw.init = &(const struct clk_init_data) {
 628			.name = "cam_cc_pll10",
 629			.parent_data = &(const struct clk_parent_data) {
 630				.index = DT_BI_TCXO,
 631			},
 632			.num_parents = 1,
 633			.ops = &clk_alpha_pll_lucid_evo_ops,
 634		},
 635	},
 636};
 637
 638static const struct clk_div_table post_div_table_cam_cc_pll10_out_even[] = {
 639	{ 0x1, 2 },
 640	{ }
 641};
 642
 643static struct clk_alpha_pll_postdiv cam_cc_pll10_out_even = {
 644	.offset = 0xa000,
 645	.post_div_shift = 10,
 646	.post_div_table = post_div_table_cam_cc_pll10_out_even,
 647	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll10_out_even),
 648	.width = 4,
 649	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 650	.clkr.hw.init = &(const struct clk_init_data) {
 651		.name = "cam_cc_pll10_out_even",
 652		.parent_hws = (const struct clk_hw*[]) {
 653			&cam_cc_pll10.clkr.hw,
 654		},
 655		.num_parents = 1,
 656		.flags = CLK_SET_RATE_PARENT,
 657		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 658	},
 659};
 660
 661static const struct alpha_pll_config cam_cc_pll11_config = {
 662	.l = 0x30,
 663	.alpha = 0x8aaa,
 664	.config_ctl_val = 0x20485699,
 665	.config_ctl_hi_val = 0x00182261,
 666	.config_ctl_hi1_val = 0x82aa299c,
 667	.test_ctl_val = 0x00000000,
 668	.test_ctl_hi_val = 0x00000003,
 669	.test_ctl_hi1_val = 0x00009000,
 670	.test_ctl_hi2_val = 0x00000034,
 671	.user_ctl_val = 0x00000400,
 672	.user_ctl_hi_val = 0x00000005,
 673};
 674
 675static struct clk_alpha_pll cam_cc_pll11 = {
 676	.offset = 0xb000,
 677	.config = &cam_cc_pll11_config,
 678	.vco_table = lucid_ole_vco,
 679	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 680	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 681	.clkr = {
 682		.hw.init = &(const struct clk_init_data) {
 683			.name = "cam_cc_pll11",
 684			.parent_data = &(const struct clk_parent_data) {
 685				.index = DT_BI_TCXO,
 686			},
 687			.num_parents = 1,
 688			.ops = &clk_alpha_pll_lucid_evo_ops,
 689		},
 690	},
 691};
 692
 693static const struct clk_div_table post_div_table_cam_cc_pll11_out_even[] = {
 694	{ 0x1, 2 },
 695	{ }
 696};
 697
 698static struct clk_alpha_pll_postdiv cam_cc_pll11_out_even = {
 699	.offset = 0xb000,
 700	.post_div_shift = 10,
 701	.post_div_table = post_div_table_cam_cc_pll11_out_even,
 702	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll11_out_even),
 703	.width = 4,
 704	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 705	.clkr.hw.init = &(const struct clk_init_data) {
 706		.name = "cam_cc_pll11_out_even",
 707		.parent_hws = (const struct clk_hw*[]) {
 708			&cam_cc_pll11.clkr.hw,
 709		},
 710		.num_parents = 1,
 711		.flags = CLK_SET_RATE_PARENT,
 712		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 713	},
 714};
 715
 716static const struct alpha_pll_config cam_cc_pll12_config = {
 717	.l = 0x30,
 718	.alpha = 0x8aaa,
 719	.config_ctl_val = 0x20485699,
 720	.config_ctl_hi_val = 0x00182261,
 721	.config_ctl_hi1_val = 0x82aa299c,
 722	.test_ctl_val = 0x00000000,
 723	.test_ctl_hi_val = 0x00000003,
 724	.test_ctl_hi1_val = 0x00009000,
 725	.test_ctl_hi2_val = 0x00000034,
 726	.user_ctl_val = 0x00000400,
 727	.user_ctl_hi_val = 0x00000005,
 728};
 729
 730static struct clk_alpha_pll cam_cc_pll12 = {
 731	.offset = 0xc000,
 732	.config = &cam_cc_pll12_config,
 733	.vco_table = lucid_ole_vco,
 734	.num_vco = ARRAY_SIZE(lucid_ole_vco),
 735	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 736	.clkr = {
 737		.hw.init = &(const struct clk_init_data) {
 738			.name = "cam_cc_pll12",
 739			.parent_data = &(const struct clk_parent_data) {
 740				.index = DT_BI_TCXO,
 741			},
 742			.num_parents = 1,
 743			.ops = &clk_alpha_pll_lucid_evo_ops,
 744		},
 745	},
 746};
 747
 748static const struct clk_div_table post_div_table_cam_cc_pll12_out_even[] = {
 749	{ 0x1, 2 },
 750	{ }
 751};
 752
 753static struct clk_alpha_pll_postdiv cam_cc_pll12_out_even = {
 754	.offset = 0xc000,
 755	.post_div_shift = 10,
 756	.post_div_table = post_div_table_cam_cc_pll12_out_even,
 757	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll12_out_even),
 758	.width = 4,
 759	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
 760	.clkr.hw.init = &(const struct clk_init_data) {
 761		.name = "cam_cc_pll12_out_even",
 762		.parent_hws = (const struct clk_hw*[]) {
 763			&cam_cc_pll12.clkr.hw,
 764		},
 765		.num_parents = 1,
 766		.flags = CLK_SET_RATE_PARENT,
 767		.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 768	},
 769};
 770
 771static const struct parent_map cam_cc_parent_map_0[] = {
 772	{ P_BI_TCXO, 0 },
 773	{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
 774	{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
 775	{ P_CAM_CC_PLL0_OUT_ODD, 3 },
 776	{ P_CAM_CC_PLL9_OUT_ODD, 4 },
 777	{ P_CAM_CC_PLL9_OUT_EVEN, 5 },
 778};
 779
 780static const struct clk_parent_data cam_cc_parent_data_0[] = {
 781	{ .index = DT_BI_TCXO },
 782	{ .hw = &cam_cc_pll0.clkr.hw },
 783	{ .hw = &cam_cc_pll0_out_even.clkr.hw },
 784	{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
 785	{ .hw = &cam_cc_pll9.clkr.hw },
 786	{ .hw = &cam_cc_pll9_out_even.clkr.hw },
 787};
 788
 789static const struct parent_map cam_cc_parent_map_1[] = {
 790	{ P_BI_TCXO, 0 },
 791	{ P_CAM_CC_PLL2_OUT_EVEN, 3 },
 792	{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
 793};
 794
 795static const struct clk_parent_data cam_cc_parent_data_1[] = {
 796	{ .index = DT_BI_TCXO },
 797	{ .hw = &cam_cc_pll2.clkr.hw },
 798	{ .hw = &cam_cc_pll2.clkr.hw },
 799};
 800
 801static const struct parent_map cam_cc_parent_map_2[] = {
 802	{ P_BI_TCXO, 0 },
 803	{ P_CAM_CC_PLL8_OUT_EVEN, 6 },
 804};
 805
 806static const struct clk_parent_data cam_cc_parent_data_2[] = {
 807	{ .index = DT_BI_TCXO },
 808	{ .hw = &cam_cc_pll8_out_even.clkr.hw },
 809};
 810
 811static const struct parent_map cam_cc_parent_map_3[] = {
 812	{ P_BI_TCXO, 0 },
 813	{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
 814};
 815
 816static const struct clk_parent_data cam_cc_parent_data_3[] = {
 817	{ .index = DT_BI_TCXO },
 818	{ .hw = &cam_cc_pll3_out_even.clkr.hw },
 819};
 820
 821static const struct parent_map cam_cc_parent_map_4[] = {
 822	{ P_BI_TCXO, 0 },
 823	{ P_CAM_CC_PLL10_OUT_EVEN, 6 },
 824};
 825
 826static const struct clk_parent_data cam_cc_parent_data_4[] = {
 827	{ .index = DT_BI_TCXO },
 828	{ .hw = &cam_cc_pll10_out_even.clkr.hw },
 829};
 830
 831static const struct parent_map cam_cc_parent_map_5[] = {
 832	{ P_BI_TCXO, 0 },
 833	{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
 834};
 835
 836static const struct clk_parent_data cam_cc_parent_data_5[] = {
 837	{ .index = DT_BI_TCXO },
 838	{ .hw = &cam_cc_pll4_out_even.clkr.hw },
 839};
 840
 841static const struct parent_map cam_cc_parent_map_6[] = {
 842	{ P_BI_TCXO, 0 },
 843	{ P_CAM_CC_PLL11_OUT_EVEN, 6 },
 844};
 845
 846static const struct clk_parent_data cam_cc_parent_data_6[] = {
 847	{ .index = DT_BI_TCXO },
 848	{ .hw = &cam_cc_pll11_out_even.clkr.hw },
 849};
 850
 851static const struct parent_map cam_cc_parent_map_7[] = {
 852	{ P_BI_TCXO, 0 },
 853	{ P_CAM_CC_PLL5_OUT_EVEN, 6 },
 854};
 855
 856static const struct clk_parent_data cam_cc_parent_data_7[] = {
 857	{ .index = DT_BI_TCXO },
 858	{ .hw = &cam_cc_pll5_out_even.clkr.hw },
 859};
 860
 861static const struct parent_map cam_cc_parent_map_8[] = {
 862	{ P_BI_TCXO, 0 },
 863	{ P_CAM_CC_PLL12_OUT_EVEN, 6 },
 864};
 865
 866static const struct clk_parent_data cam_cc_parent_data_8[] = {
 867	{ .index = DT_BI_TCXO },
 868	{ .hw = &cam_cc_pll12_out_even.clkr.hw },
 869};
 870
 871static const struct parent_map cam_cc_parent_map_9[] = {
 872	{ P_BI_TCXO, 0 },
 873	{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
 874};
 875
 876static const struct clk_parent_data cam_cc_parent_data_9[] = {
 877	{ .index = DT_BI_TCXO },
 878	{ .hw = &cam_cc_pll1_out_even.clkr.hw },
 879};
 880
 881static const struct parent_map cam_cc_parent_map_10[] = {
 882	{ P_BI_TCXO, 0 },
 883	{ P_CAM_CC_PLL6_OUT_EVEN, 6 },
 884};
 885
 886static const struct clk_parent_data cam_cc_parent_data_10[] = {
 887	{ .index = DT_BI_TCXO },
 888	{ .hw = &cam_cc_pll6_out_even.clkr.hw },
 889};
 890
 891static const struct parent_map cam_cc_parent_map_11[] = {
 892	{ P_BI_TCXO, 0 },
 893	{ P_CAM_CC_PLL7_OUT_EVEN, 6 },
 894};
 895
 896static const struct clk_parent_data cam_cc_parent_data_11[] = {
 897	{ .index = DT_BI_TCXO },
 898	{ .hw = &cam_cc_pll7_out_even.clkr.hw },
 899};
 900
 901static const struct parent_map cam_cc_parent_map_12[] = {
 902	{ P_SLEEP_CLK, 0 },
 903};
 904
 905static const struct clk_parent_data cam_cc_parent_data_12[] = {
 906	{ .index = DT_SLEEP_CLK },
 907};
 908
 909static const struct parent_map cam_cc_parent_map_13_ao[] = {
 910	{ P_BI_TCXO_AO, 0 },
 911};
 912
 913static const struct clk_parent_data cam_cc_parent_data_13_ao[] = {
 914	{ .index = DT_BI_TCXO_AO },
 915};
 916
 917static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
 918	F(19200000, P_BI_TCXO, 1, 0, 0),
 919	F(200000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
 920	F(400000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
 921	F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
 922	F(785000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
 923	{ }
 924};
 925
 926static struct clk_rcg2 cam_cc_bps_clk_src = {
 927	.cmd_rcgr = 0x10278,
 928	.mnd_width = 0,
 929	.hid_width = 5,
 930	.parent_map = cam_cc_parent_map_2,
 931	.freq_tbl = ftbl_cam_cc_bps_clk_src,
 932	.clkr.hw.init = &(const struct clk_init_data) {
 933		.name = "cam_cc_bps_clk_src",
 934		.parent_data = cam_cc_parent_data_2,
 935		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
 936		.flags = CLK_SET_RATE_PARENT,
 937		.ops = &clk_rcg2_shared_ops,
 938	},
 939};
 940
 941static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
 942	F(19200000, P_BI_TCXO, 1, 0, 0),
 943	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
 944	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 945	{ }
 946};
 947
 948static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
 949	.cmd_rcgr = 0x13de0,
 950	.mnd_width = 0,
 951	.hid_width = 5,
 952	.parent_map = cam_cc_parent_map_0,
 953	.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
 954	.clkr.hw.init = &(const struct clk_init_data) {
 955		.name = "cam_cc_camnoc_axi_clk_src",
 956		.parent_data = cam_cc_parent_data_0,
 957		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 958		.flags = CLK_SET_RATE_PARENT,
 959		.ops = &clk_rcg2_shared_ops,
 960	},
 961};
 962
 963static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
 964	F(19200000, P_BI_TCXO, 1, 0, 0),
 965	F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
 966	{ }
 967};
 968
 969static struct clk_rcg2 cam_cc_cci_0_clk_src = {
 970	.cmd_rcgr = 0x13900,
 971	.mnd_width = 8,
 972	.hid_width = 5,
 973	.parent_map = cam_cc_parent_map_0,
 974	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 975	.clkr.hw.init = &(const struct clk_init_data) {
 976		.name = "cam_cc_cci_0_clk_src",
 977		.parent_data = cam_cc_parent_data_0,
 978		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 979		.flags = CLK_SET_RATE_PARENT,
 980		.ops = &clk_rcg2_shared_ops,
 981	},
 982};
 983
 984static struct clk_rcg2 cam_cc_cci_1_clk_src = {
 985	.cmd_rcgr = 0x13a30,
 986	.mnd_width = 8,
 987	.hid_width = 5,
 988	.parent_map = cam_cc_parent_map_0,
 989	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 990	.clkr.hw.init = &(const struct clk_init_data) {
 991		.name = "cam_cc_cci_1_clk_src",
 992		.parent_data = cam_cc_parent_data_0,
 993		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 994		.flags = CLK_SET_RATE_PARENT,
 995		.ops = &clk_rcg2_shared_ops,
 996	},
 997};
 998
 999static struct clk_rcg2 cam_cc_cci_2_clk_src = {
1000	.cmd_rcgr = 0x13b60,
1001	.mnd_width = 8,
1002	.hid_width = 5,
1003	.parent_map = cam_cc_parent_map_0,
1004	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
1005	.clkr.hw.init = &(const struct clk_init_data) {
1006		.name = "cam_cc_cci_2_clk_src",
1007		.parent_data = cam_cc_parent_data_0,
1008		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1009		.flags = CLK_SET_RATE_PARENT,
1010		.ops = &clk_rcg2_shared_ops,
1011	},
1012};
1013
1014static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
1015	F(19200000, P_BI_TCXO, 1, 0, 0),
1016	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1017	F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
1018	{ }
1019};
1020
1021static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
1022	.cmd_rcgr = 0x11290,
1023	.mnd_width = 0,
1024	.hid_width = 5,
1025	.parent_map = cam_cc_parent_map_0,
1026	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
1027	.clkr.hw.init = &(const struct clk_init_data) {
1028		.name = "cam_cc_cphy_rx_clk_src",
1029		.parent_data = cam_cc_parent_data_0,
1030		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1031		.flags = CLK_SET_RATE_PARENT,
1032		.ops = &clk_rcg2_shared_ops,
1033	},
1034};
1035
1036static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = {
1037	F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
1038	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1039	F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
1040	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
1041	{ }
1042};
1043
1044static struct clk_rcg2 cam_cc_cre_clk_src = {
1045	.cmd_rcgr = 0x1353c,
1046	.mnd_width = 0,
1047	.hid_width = 5,
1048	.parent_map = cam_cc_parent_map_0,
1049	.freq_tbl = ftbl_cam_cc_cre_clk_src,
1050	.clkr.hw.init = &(const struct clk_init_data) {
1051		.name = "cam_cc_cre_clk_src",
1052		.parent_data = cam_cc_parent_data_0,
1053		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1054		.flags = CLK_SET_RATE_PARENT,
1055		.ops = &clk_rcg2_shared_ops,
1056	},
1057};
1058
1059static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
1060	F(19200000, P_BI_TCXO, 1, 0, 0),
1061	F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
1062	{ }
1063};
1064
1065static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
1066	.cmd_rcgr = 0x15980,
1067	.mnd_width = 0,
1068	.hid_width = 5,
1069	.parent_map = cam_cc_parent_map_0,
1070	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1071	.clkr.hw.init = &(const struct clk_init_data) {
1072		.name = "cam_cc_csi0phytimer_clk_src",
1073		.parent_data = cam_cc_parent_data_0,
1074		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1075		.flags = CLK_SET_RATE_PARENT,
1076		.ops = &clk_rcg2_shared_ops,
1077	},
1078};
1079
1080static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
1081	.cmd_rcgr = 0x15ab8,
1082	.mnd_width = 0,
1083	.hid_width = 5,
1084	.parent_map = cam_cc_parent_map_0,
1085	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1086	.clkr.hw.init = &(const struct clk_init_data) {
1087		.name = "cam_cc_csi1phytimer_clk_src",
1088		.parent_data = cam_cc_parent_data_0,
1089		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1090		.flags = CLK_SET_RATE_PARENT,
1091		.ops = &clk_rcg2_shared_ops,
1092	},
1093};
1094
1095static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
1096	.cmd_rcgr = 0x15bec,
1097	.mnd_width = 0,
1098	.hid_width = 5,
1099	.parent_map = cam_cc_parent_map_0,
1100	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1101	.clkr.hw.init = &(const struct clk_init_data) {
1102		.name = "cam_cc_csi2phytimer_clk_src",
1103		.parent_data = cam_cc_parent_data_0,
1104		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1105		.flags = CLK_SET_RATE_PARENT,
1106		.ops = &clk_rcg2_shared_ops,
1107	},
1108};
1109
1110static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
1111	.cmd_rcgr = 0x15d20,
1112	.mnd_width = 0,
1113	.hid_width = 5,
1114	.parent_map = cam_cc_parent_map_0,
1115	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1116	.clkr.hw.init = &(const struct clk_init_data) {
1117		.name = "cam_cc_csi3phytimer_clk_src",
1118		.parent_data = cam_cc_parent_data_0,
1119		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1120		.flags = CLK_SET_RATE_PARENT,
1121		.ops = &clk_rcg2_shared_ops,
1122	},
1123};
1124
1125static const struct freq_tbl ftbl_cam_cc_csi4phytimer_clk_src[] = {
1126	F(19200000, P_BI_TCXO, 1, 0, 0),
1127	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1128	{ }
1129};
1130
1131static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
1132	.cmd_rcgr = 0x15e54,
1133	.mnd_width = 0,
1134	.hid_width = 5,
1135	.parent_map = cam_cc_parent_map_0,
1136	.freq_tbl = ftbl_cam_cc_csi4phytimer_clk_src,
1137	.clkr.hw.init = &(const struct clk_init_data) {
1138		.name = "cam_cc_csi4phytimer_clk_src",
1139		.parent_data = cam_cc_parent_data_0,
1140		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1141		.flags = CLK_SET_RATE_PARENT,
1142		.ops = &clk_rcg2_shared_ops,
1143	},
1144};
1145
1146static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
1147	.cmd_rcgr = 0x15f88,
1148	.mnd_width = 0,
1149	.hid_width = 5,
1150	.parent_map = cam_cc_parent_map_0,
1151	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1152	.clkr.hw.init = &(const struct clk_init_data) {
1153		.name = "cam_cc_csi5phytimer_clk_src",
1154		.parent_data = cam_cc_parent_data_0,
1155		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1156		.flags = CLK_SET_RATE_PARENT,
1157		.ops = &clk_rcg2_shared_ops,
1158	},
1159};
1160
1161static struct clk_rcg2 cam_cc_csi6phytimer_clk_src = {
1162	.cmd_rcgr = 0x160bc,
1163	.mnd_width = 0,
1164	.hid_width = 5,
1165	.parent_map = cam_cc_parent_map_0,
1166	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1167	.clkr.hw.init = &(const struct clk_init_data) {
1168		.name = "cam_cc_csi6phytimer_clk_src",
1169		.parent_data = cam_cc_parent_data_0,
1170		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1171		.flags = CLK_SET_RATE_PARENT,
1172		.ops = &clk_rcg2_shared_ops,
1173	},
1174};
1175
1176static struct clk_rcg2 cam_cc_csi7phytimer_clk_src = {
1177	.cmd_rcgr = 0x161f0,
1178	.mnd_width = 0,
1179	.hid_width = 5,
1180	.parent_map = cam_cc_parent_map_0,
1181	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1182	.clkr.hw.init = &(const struct clk_init_data) {
1183		.name = "cam_cc_csi7phytimer_clk_src",
1184		.parent_data = cam_cc_parent_data_0,
1185		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1186		.flags = CLK_SET_RATE_PARENT,
1187		.ops = &clk_rcg2_shared_ops,
1188	},
1189};
1190
1191static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = {
1192	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1193	F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
1194	{ }
1195};
1196
1197static struct clk_rcg2 cam_cc_csid_clk_src = {
1198	.cmd_rcgr = 0x13ca8,
1199	.mnd_width = 0,
1200	.hid_width = 5,
1201	.parent_map = cam_cc_parent_map_0,
1202	.freq_tbl = ftbl_cam_cc_csid_clk_src,
1203	.clkr.hw.init = &(const struct clk_init_data) {
1204		.name = "cam_cc_csid_clk_src",
1205		.parent_data = cam_cc_parent_data_0,
1206		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1207		.flags = CLK_SET_RATE_PARENT,
1208		.ops = &clk_rcg2_shared_ops,
1209	},
1210};
1211
1212static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
1213	F(19200000, P_BI_TCXO, 1, 0, 0),
1214	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
1215	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1216	{ }
1217};
1218
1219static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
1220	.cmd_rcgr = 0x10018,
1221	.mnd_width = 0,
1222	.hid_width = 5,
1223	.parent_map = cam_cc_parent_map_0,
1224	.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
1225	.clkr.hw.init = &(const struct clk_init_data) {
1226		.name = "cam_cc_fast_ahb_clk_src",
1227		.parent_data = cam_cc_parent_data_0,
1228		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1229		.flags = CLK_SET_RATE_PARENT,
1230		.ops = &clk_rcg2_shared_ops,
1231	},
1232};
1233
1234static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
1235	F(19200000, P_BI_TCXO, 1, 0, 0),
1236	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1237	F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
1238	F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
1239	{ }
1240};
1241
1242static struct clk_rcg2 cam_cc_icp_clk_src = {
1243	.cmd_rcgr = 0x137c4,
1244	.mnd_width = 0,
1245	.hid_width = 5,
1246	.parent_map = cam_cc_parent_map_0,
1247	.freq_tbl = ftbl_cam_cc_icp_clk_src,
1248	.clkr.hw.init = &(const struct clk_init_data) {
1249		.name = "cam_cc_icp_clk_src",
1250		.parent_data = cam_cc_parent_data_0,
1251		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1252		.flags = CLK_SET_RATE_PARENT,
1253		.ops = &clk_rcg2_shared_ops,
1254	},
1255};
1256
1257static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
1258	F(19200000, P_BI_TCXO, 1, 0, 0),
1259	F(466000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1260	F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1261	F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1262	F(785000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1263	{ }
1264};
1265
1266static struct clk_rcg2 cam_cc_ife_0_clk_src = {
1267	.cmd_rcgr = 0x11018,
1268	.mnd_width = 0,
1269	.hid_width = 5,
1270	.parent_map = cam_cc_parent_map_3,
1271	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
1272	.clkr.hw.init = &(const struct clk_init_data) {
1273		.name = "cam_cc_ife_0_clk_src",
1274		.parent_data = cam_cc_parent_data_3,
1275		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
1276		.flags = CLK_SET_RATE_PARENT,
1277		.ops = &clk_rcg2_shared_ops,
1278	},
1279};
1280
1281static const struct freq_tbl ftbl_cam_cc_ife_0_dsp_clk_src[] = {
1282	F(466000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1283	F(594000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1284	F(675000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1285	F(785000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1286	{ }
1287};
1288
1289static struct clk_rcg2 cam_cc_ife_0_dsp_clk_src = {
1290	.cmd_rcgr = 0x11154,
1291	.mnd_width = 0,
1292	.hid_width = 5,
1293	.parent_map = cam_cc_parent_map_4,
1294	.freq_tbl = ftbl_cam_cc_ife_0_dsp_clk_src,
1295	.clkr.hw.init = &(const struct clk_init_data) {
1296		.name = "cam_cc_ife_0_dsp_clk_src",
1297		.parent_data = cam_cc_parent_data_4,
1298		.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
1299		.flags = CLK_SET_RATE_PARENT,
1300		.ops = &clk_rcg2_shared_ops,
1301	},
1302};
1303
1304static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
1305	F(19200000, P_BI_TCXO, 1, 0, 0),
1306	F(466000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1307	F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1308	F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1309	F(785000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1310	{ }
1311};
1312
1313static struct clk_rcg2 cam_cc_ife_1_clk_src = {
1314	.cmd_rcgr = 0x12018,
1315	.mnd_width = 0,
1316	.hid_width = 5,
1317	.parent_map = cam_cc_parent_map_5,
1318	.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
1319	.clkr.hw.init = &(const struct clk_init_data) {
1320		.name = "cam_cc_ife_1_clk_src",
1321		.parent_data = cam_cc_parent_data_5,
1322		.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
1323		.flags = CLK_SET_RATE_PARENT,
1324		.ops = &clk_rcg2_shared_ops,
1325	},
1326};
1327
1328static const struct freq_tbl ftbl_cam_cc_ife_1_dsp_clk_src[] = {
1329	F(466000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0),
1330	F(594000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0),
1331	F(675000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0),
1332	F(785000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0),
1333	{ }
1334};
1335
1336static struct clk_rcg2 cam_cc_ife_1_dsp_clk_src = {
1337	.cmd_rcgr = 0x12154,
1338	.mnd_width = 0,
1339	.hid_width = 5,
1340	.parent_map = cam_cc_parent_map_6,
1341	.freq_tbl = ftbl_cam_cc_ife_1_dsp_clk_src,
1342	.clkr.hw.init = &(const struct clk_init_data) {
1343		.name = "cam_cc_ife_1_dsp_clk_src",
1344		.parent_data = cam_cc_parent_data_6,
1345		.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
1346		.flags = CLK_SET_RATE_PARENT,
1347		.ops = &clk_rcg2_shared_ops,
1348	},
1349};
1350
1351static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
1352	F(466000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1353	F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1354	F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1355	F(785000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1356	{ }
1357};
1358
1359static struct clk_rcg2 cam_cc_ife_2_clk_src = {
1360	.cmd_rcgr = 0x122a8,
1361	.mnd_width = 0,
1362	.hid_width = 5,
1363	.parent_map = cam_cc_parent_map_7,
1364	.freq_tbl = ftbl_cam_cc_ife_2_clk_src,
1365	.clkr.hw.init = &(const struct clk_init_data) {
1366		.name = "cam_cc_ife_2_clk_src",
1367		.parent_data = cam_cc_parent_data_7,
1368		.num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
1369		.flags = CLK_SET_RATE_PARENT,
1370		.ops = &clk_rcg2_shared_ops,
1371	},
1372};
1373
1374static const struct freq_tbl ftbl_cam_cc_ife_2_dsp_clk_src[] = {
1375	F(466000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0),
1376	F(594000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0),
1377	F(675000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0),
1378	F(785000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0),
1379	{ }
1380};
1381
1382static struct clk_rcg2 cam_cc_ife_2_dsp_clk_src = {
1383	.cmd_rcgr = 0x123e4,
1384	.mnd_width = 0,
1385	.hid_width = 5,
1386	.parent_map = cam_cc_parent_map_8,
1387	.freq_tbl = ftbl_cam_cc_ife_2_dsp_clk_src,
1388	.clkr.hw.init = &(const struct clk_init_data) {
1389		.name = "cam_cc_ife_2_dsp_clk_src",
1390		.parent_data = cam_cc_parent_data_8,
1391		.num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
1392		.flags = CLK_SET_RATE_PARENT,
1393		.ops = &clk_rcg2_shared_ops,
1394	},
1395};
1396
1397static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
1398	.cmd_rcgr = 0x13000,
1399	.mnd_width = 0,
1400	.hid_width = 5,
1401	.parent_map = cam_cc_parent_map_0,
1402	.freq_tbl = ftbl_cam_cc_csid_clk_src,
1403	.clkr.hw.init = &(const struct clk_init_data) {
1404		.name = "cam_cc_ife_lite_clk_src",
1405		.parent_data = cam_cc_parent_data_0,
1406		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1407		.flags = CLK_SET_RATE_PARENT,
1408		.ops = &clk_rcg2_shared_ops,
1409	},
1410};
1411
1412static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
1413	.cmd_rcgr = 0x1313c,
1414	.mnd_width = 0,
1415	.hid_width = 5,
1416	.parent_map = cam_cc_parent_map_0,
1417	.freq_tbl = ftbl_cam_cc_csid_clk_src,
1418	.clkr.hw.init = &(const struct clk_init_data) {
1419		.name = "cam_cc_ife_lite_csid_clk_src",
1420		.parent_data = cam_cc_parent_data_0,
1421		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1422		.flags = CLK_SET_RATE_PARENT,
1423		.ops = &clk_rcg2_shared_ops,
1424	},
1425};
1426
1427static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = {
1428	F(455000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1429	F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1430	F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1431	F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1432	{ }
1433};
1434
1435static struct clk_rcg2 cam_cc_ipe_nps_clk_src = {
1436	.cmd_rcgr = 0x103cc,
1437	.mnd_width = 0,
1438	.hid_width = 5,
1439	.parent_map = cam_cc_parent_map_9,
1440	.freq_tbl = ftbl_cam_cc_ipe_nps_clk_src,
1441	.clkr.hw.init = &(const struct clk_init_data) {
1442		.name = "cam_cc_ipe_nps_clk_src",
1443		.parent_data = cam_cc_parent_data_9,
1444		.num_parents = ARRAY_SIZE(cam_cc_parent_data_9),
1445		.flags = CLK_SET_RATE_PARENT,
1446		.ops = &clk_rcg2_shared_ops,
1447	},
1448};
1449
1450static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = {
1451	F(19200000, P_BI_TCXO, 1, 0, 0),
1452	F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
1453	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1454	F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
1455	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
1456	{ }
1457};
1458
1459static struct clk_rcg2 cam_cc_jpeg_clk_src = {
1460	.cmd_rcgr = 0x13674,
1461	.mnd_width = 0,
1462	.hid_width = 5,
1463	.parent_map = cam_cc_parent_map_0,
1464	.freq_tbl = ftbl_cam_cc_jpeg_clk_src,
1465	.clkr.hw.init = &(const struct clk_init_data) {
1466		.name = "cam_cc_jpeg_clk_src",
1467		.parent_data = cam_cc_parent_data_0,
1468		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1469		.flags = CLK_SET_RATE_PARENT,
1470		.ops = &clk_rcg2_shared_ops,
1471	},
1472};
1473
1474static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
1475	F(19200000, P_BI_TCXO, 1, 0, 0),
1476	F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4),
1477	F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0),
1478	{ }
1479};
1480
1481static struct clk_rcg2 cam_cc_mclk0_clk_src = {
1482	.cmd_rcgr = 0x15000,
1483	.mnd_width = 8,
1484	.hid_width = 5,
1485	.parent_map = cam_cc_parent_map_1,
1486	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1487	.clkr.hw.init = &(const struct clk_init_data) {
1488		.name = "cam_cc_mclk0_clk_src",
1489		.parent_data = cam_cc_parent_data_1,
1490		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1491		.flags = CLK_SET_RATE_PARENT,
1492		.ops = &clk_rcg2_shared_ops,
1493	},
1494};
1495
1496static struct clk_rcg2 cam_cc_mclk1_clk_src = {
1497	.cmd_rcgr = 0x15130,
1498	.mnd_width = 8,
1499	.hid_width = 5,
1500	.parent_map = cam_cc_parent_map_1,
1501	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1502	.clkr.hw.init = &(const struct clk_init_data) {
1503		.name = "cam_cc_mclk1_clk_src",
1504		.parent_data = cam_cc_parent_data_1,
1505		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1506		.flags = CLK_SET_RATE_PARENT,
1507		.ops = &clk_rcg2_shared_ops,
1508	},
1509};
1510
1511static struct clk_rcg2 cam_cc_mclk2_clk_src = {
1512	.cmd_rcgr = 0x15260,
1513	.mnd_width = 8,
1514	.hid_width = 5,
1515	.parent_map = cam_cc_parent_map_1,
1516	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1517	.clkr.hw.init = &(const struct clk_init_data) {
1518		.name = "cam_cc_mclk2_clk_src",
1519		.parent_data = cam_cc_parent_data_1,
1520		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1521		.flags = CLK_SET_RATE_PARENT,
1522		.ops = &clk_rcg2_shared_ops,
1523	},
1524};
1525
1526static struct clk_rcg2 cam_cc_mclk3_clk_src = {
1527	.cmd_rcgr = 0x15390,
1528	.mnd_width = 8,
1529	.hid_width = 5,
1530	.parent_map = cam_cc_parent_map_1,
1531	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1532	.clkr.hw.init = &(const struct clk_init_data) {
1533		.name = "cam_cc_mclk3_clk_src",
1534		.parent_data = cam_cc_parent_data_1,
1535		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1536		.flags = CLK_SET_RATE_PARENT,
1537		.ops = &clk_rcg2_shared_ops,
1538	},
1539};
1540
1541static struct clk_rcg2 cam_cc_mclk4_clk_src = {
1542	.cmd_rcgr = 0x154c0,
1543	.mnd_width = 8,
1544	.hid_width = 5,
1545	.parent_map = cam_cc_parent_map_1,
1546	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1547	.clkr.hw.init = &(const struct clk_init_data) {
1548		.name = "cam_cc_mclk4_clk_src",
1549		.parent_data = cam_cc_parent_data_1,
1550		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1551		.flags = CLK_SET_RATE_PARENT,
1552		.ops = &clk_rcg2_shared_ops,
1553	},
1554};
1555
1556static struct clk_rcg2 cam_cc_mclk5_clk_src = {
1557	.cmd_rcgr = 0x155f0,
1558	.mnd_width = 8,
1559	.hid_width = 5,
1560	.parent_map = cam_cc_parent_map_1,
1561	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1562	.clkr.hw.init = &(const struct clk_init_data) {
1563		.name = "cam_cc_mclk5_clk_src",
1564		.parent_data = cam_cc_parent_data_1,
1565		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1566		.flags = CLK_SET_RATE_PARENT,
1567		.ops = &clk_rcg2_shared_ops,
1568	},
1569};
1570
1571static struct clk_rcg2 cam_cc_mclk6_clk_src = {
1572	.cmd_rcgr = 0x15720,
1573	.mnd_width = 8,
1574	.hid_width = 5,
1575	.parent_map = cam_cc_parent_map_1,
1576	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1577	.clkr.hw.init = &(const struct clk_init_data) {
1578		.name = "cam_cc_mclk6_clk_src",
1579		.parent_data = cam_cc_parent_data_1,
1580		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1581		.flags = CLK_SET_RATE_PARENT,
1582		.ops = &clk_rcg2_shared_ops,
1583	},
1584};
1585
1586static struct clk_rcg2 cam_cc_mclk7_clk_src = {
1587	.cmd_rcgr = 0x15850,
1588	.mnd_width = 8,
1589	.hid_width = 5,
1590	.parent_map = cam_cc_parent_map_1,
1591	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1592	.clkr.hw.init = &(const struct clk_init_data) {
1593		.name = "cam_cc_mclk7_clk_src",
1594		.parent_data = cam_cc_parent_data_1,
1595		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1596		.flags = CLK_SET_RATE_PARENT,
1597		.ops = &clk_rcg2_shared_ops,
1598	},
1599};
1600
1601static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = {
1602	F(19200000, P_BI_TCXO, 1, 0, 0),
1603	F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
1604	F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
1605	F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
1606	{ }
1607};
1608
1609static struct clk_rcg2 cam_cc_qdss_debug_clk_src = {
1610	.cmd_rcgr = 0x13f24,
1611	.mnd_width = 0,
1612	.hid_width = 5,
1613	.parent_map = cam_cc_parent_map_0,
1614	.freq_tbl = ftbl_cam_cc_qdss_debug_clk_src,
1615	.clkr.hw.init = &(const struct clk_init_data) {
1616		.name = "cam_cc_qdss_debug_clk_src",
1617		.parent_data = cam_cc_parent_data_0,
1618		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1619		.flags = CLK_SET_RATE_PARENT,
1620		.ops = &clk_rcg2_shared_ops,
1621	},
1622};
1623
1624static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
1625	F(466000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1626	F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1627	F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1628	F(785000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1629	{ }
1630};
1631
1632static struct clk_rcg2 cam_cc_sfe_0_clk_src = {
1633	.cmd_rcgr = 0x13294,
1634	.mnd_width = 0,
1635	.hid_width = 5,
1636	.parent_map = cam_cc_parent_map_10,
1637	.freq_tbl = ftbl_cam_cc_sfe_0_clk_src,
1638	.clkr.hw.init = &(const struct clk_init_data) {
1639		.name = "cam_cc_sfe_0_clk_src",
1640		.parent_data = cam_cc_parent_data_10,
1641		.num_parents = ARRAY_SIZE(cam_cc_parent_data_10),
1642		.flags = CLK_SET_RATE_PARENT,
1643		.ops = &clk_rcg2_shared_ops,
1644	},
1645};
1646
1647static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = {
1648	F(466000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1649	F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1650	F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1651	F(785000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1652	{ }
1653};
1654
1655static struct clk_rcg2 cam_cc_sfe_1_clk_src = {
1656	.cmd_rcgr = 0x133f4,
1657	.mnd_width = 0,
1658	.hid_width = 5,
1659	.parent_map = cam_cc_parent_map_11,
1660	.freq_tbl = ftbl_cam_cc_sfe_1_clk_src,
1661	.clkr.hw.init = &(const struct clk_init_data) {
1662		.name = "cam_cc_sfe_1_clk_src",
1663		.parent_data = cam_cc_parent_data_11,
1664		.num_parents = ARRAY_SIZE(cam_cc_parent_data_11),
1665		.flags = CLK_SET_RATE_PARENT,
1666		.ops = &clk_rcg2_shared_ops,
1667	},
1668};
1669
1670static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
1671	F(32000, P_SLEEP_CLK, 1, 0, 0),
1672	{ }
1673};
1674
1675static struct clk_rcg2 cam_cc_sleep_clk_src = {
1676	.cmd_rcgr = 0x141a0,
1677	.mnd_width = 0,
1678	.hid_width = 5,
1679	.parent_map = cam_cc_parent_map_12,
1680	.freq_tbl = ftbl_cam_cc_sleep_clk_src,
1681	.clkr.hw.init = &(const struct clk_init_data) {
1682		.name = "cam_cc_sleep_clk_src",
1683		.parent_data = cam_cc_parent_data_12,
1684		.num_parents = ARRAY_SIZE(cam_cc_parent_data_12),
1685		.flags = CLK_SET_RATE_PARENT,
1686		.ops = &clk_rcg2_shared_ops,
1687	},
1688};
1689
1690static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
1691	F(19200000, P_BI_TCXO, 1, 0, 0),
1692	F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
1693	{ }
1694};
1695
1696static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
1697	.cmd_rcgr = 0x10148,
1698	.mnd_width = 8,
1699	.hid_width = 5,
1700	.parent_map = cam_cc_parent_map_0,
1701	.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
1702	.clkr.hw.init = &(const struct clk_init_data) {
1703		.name = "cam_cc_slow_ahb_clk_src",
1704		.parent_data = cam_cc_parent_data_0,
1705		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1706		.flags = CLK_SET_RATE_PARENT,
1707		.ops = &clk_rcg2_shared_ops,
1708	},
1709};
1710
1711static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
1712	F(19200000, P_BI_TCXO_AO, 1, 0, 0),
1713	{ }
1714};
1715
1716static struct clk_rcg2 cam_cc_xo_clk_src = {
1717	.cmd_rcgr = 0x14070,
1718	.mnd_width = 0,
1719	.hid_width = 5,
1720	.parent_map = cam_cc_parent_map_13_ao,
1721	.freq_tbl = ftbl_cam_cc_xo_clk_src,
1722	.clkr.hw.init = &(const struct clk_init_data) {
1723		.name = "cam_cc_xo_clk_src",
1724		.parent_data = cam_cc_parent_data_13_ao,
1725		.num_parents = ARRAY_SIZE(cam_cc_parent_data_13_ao),
1726		.flags = CLK_SET_RATE_PARENT,
1727		.ops = &clk_rcg2_shared_ops,
1728	},
1729};
1730
1731static struct clk_branch cam_cc_bps_ahb_clk = {
1732	.halt_reg = 0x10274,
1733	.halt_check = BRANCH_HALT,
1734	.clkr = {
1735		.enable_reg = 0x10274,
1736		.enable_mask = BIT(0),
1737		.hw.init = &(const struct clk_init_data) {
1738			.name = "cam_cc_bps_ahb_clk",
1739			.parent_hws = (const struct clk_hw*[]) {
1740				&cam_cc_slow_ahb_clk_src.clkr.hw,
1741			},
1742			.num_parents = 1,
1743			.flags = CLK_SET_RATE_PARENT,
1744			.ops = &clk_branch2_ops,
1745		},
1746	},
1747};
1748
1749static struct clk_branch cam_cc_bps_clk = {
1750	.halt_reg = 0x103a4,
1751	.halt_check = BRANCH_HALT,
1752	.clkr = {
1753		.enable_reg = 0x103a4,
1754		.enable_mask = BIT(0),
1755		.hw.init = &(const struct clk_init_data) {
1756			.name = "cam_cc_bps_clk",
1757			.parent_hws = (const struct clk_hw*[]) {
1758				&cam_cc_bps_clk_src.clkr.hw,
1759			},
1760			.num_parents = 1,
1761			.flags = CLK_SET_RATE_PARENT,
1762			.ops = &clk_branch2_ops,
1763		},
1764	},
1765};
1766
1767static struct clk_branch cam_cc_bps_fast_ahb_clk = {
1768	.halt_reg = 0x10144,
1769	.halt_check = BRANCH_HALT,
1770	.clkr = {
1771		.enable_reg = 0x10144,
1772		.enable_mask = BIT(0),
1773		.hw.init = &(const struct clk_init_data) {
1774			.name = "cam_cc_bps_fast_ahb_clk",
1775			.parent_hws = (const struct clk_hw*[]) {
1776				&cam_cc_fast_ahb_clk_src.clkr.hw,
1777			},
1778			.num_parents = 1,
1779			.flags = CLK_SET_RATE_PARENT,
1780			.ops = &clk_branch2_ops,
1781		},
1782	},
1783};
1784
1785static struct clk_branch cam_cc_camnoc_axi_clk = {
1786	.halt_reg = 0x13f0c,
1787	.halt_check = BRANCH_HALT,
1788	.clkr = {
1789		.enable_reg = 0x13f0c,
1790		.enable_mask = BIT(0),
1791		.hw.init = &(const struct clk_init_data) {
1792			.name = "cam_cc_camnoc_axi_clk",
1793			.parent_hws = (const struct clk_hw*[]) {
1794				&cam_cc_camnoc_axi_clk_src.clkr.hw,
1795			},
1796			.num_parents = 1,
1797			.flags = CLK_SET_RATE_PARENT,
1798			.ops = &clk_branch2_ops,
1799		},
1800	},
1801};
1802
1803static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
1804	.halt_reg = 0x13f18,
1805	.halt_check = BRANCH_HALT,
1806	.clkr = {
1807		.enable_reg = 0x13f18,
1808		.enable_mask = BIT(0),
1809		.hw.init = &(const struct clk_init_data) {
1810			.name = "cam_cc_camnoc_dcd_xo_clk",
1811			.parent_hws = (const struct clk_hw*[]) {
1812				&cam_cc_xo_clk_src.clkr.hw,
1813			},
1814			.num_parents = 1,
1815			.flags = CLK_SET_RATE_PARENT,
1816			.ops = &clk_branch2_ops,
1817		},
1818	},
1819};
1820
1821static struct clk_branch cam_cc_camnoc_xo_clk = {
1822	.halt_reg = 0x13f1c,
1823	.halt_check = BRANCH_HALT,
1824	.clkr = {
1825		.enable_reg = 0x13f1c,
1826		.enable_mask = BIT(0),
1827		.hw.init = &(const struct clk_init_data) {
1828			.name = "cam_cc_camnoc_xo_clk",
1829			.parent_hws = (const struct clk_hw*[]) {
1830				&cam_cc_xo_clk_src.clkr.hw,
1831			},
1832			.num_parents = 1,
1833			.flags = CLK_SET_RATE_PARENT,
1834			.ops = &clk_branch2_ops,
1835		},
1836	},
1837};
1838
1839static struct clk_branch cam_cc_cci_0_clk = {
1840	.halt_reg = 0x13a2c,
1841	.halt_check = BRANCH_HALT,
1842	.clkr = {
1843		.enable_reg = 0x13a2c,
1844		.enable_mask = BIT(0),
1845		.hw.init = &(const struct clk_init_data) {
1846			.name = "cam_cc_cci_0_clk",
1847			.parent_hws = (const struct clk_hw*[]) {
1848				&cam_cc_cci_0_clk_src.clkr.hw,
1849			},
1850			.num_parents = 1,
1851			.flags = CLK_SET_RATE_PARENT,
1852			.ops = &clk_branch2_ops,
1853		},
1854	},
1855};
1856
1857static struct clk_branch cam_cc_cci_1_clk = {
1858	.halt_reg = 0x13b5c,
1859	.halt_check = BRANCH_HALT,
1860	.clkr = {
1861		.enable_reg = 0x13b5c,
1862		.enable_mask = BIT(0),
1863		.hw.init = &(const struct clk_init_data) {
1864			.name = "cam_cc_cci_1_clk",
1865			.parent_hws = (const struct clk_hw*[]) {
1866				&cam_cc_cci_1_clk_src.clkr.hw,
1867			},
1868			.num_parents = 1,
1869			.flags = CLK_SET_RATE_PARENT,
1870			.ops = &clk_branch2_ops,
1871		},
1872	},
1873};
1874
1875static struct clk_branch cam_cc_cci_2_clk = {
1876	.halt_reg = 0x13c8c,
1877	.halt_check = BRANCH_HALT,
1878	.clkr = {
1879		.enable_reg = 0x13c8c,
1880		.enable_mask = BIT(0),
1881		.hw.init = &(const struct clk_init_data) {
1882			.name = "cam_cc_cci_2_clk",
1883			.parent_hws = (const struct clk_hw*[]) {
1884				&cam_cc_cci_2_clk_src.clkr.hw,
1885			},
1886			.num_parents = 1,
1887			.flags = CLK_SET_RATE_PARENT,
1888			.ops = &clk_branch2_ops,
1889		},
1890	},
1891};
1892
1893static struct clk_branch cam_cc_core_ahb_clk = {
1894	.halt_reg = 0x1406c,
1895	.halt_check = BRANCH_HALT_DELAY,
1896	.clkr = {
1897		.enable_reg = 0x1406c,
1898		.enable_mask = BIT(0),
1899		.hw.init = &(const struct clk_init_data) {
1900			.name = "cam_cc_core_ahb_clk",
1901			.parent_hws = (const struct clk_hw*[]) {
1902				&cam_cc_slow_ahb_clk_src.clkr.hw,
1903			},
1904			.num_parents = 1,
1905			.flags = CLK_SET_RATE_PARENT,
1906			.ops = &clk_branch2_ops,
1907		},
1908	},
1909};
1910
1911static struct clk_branch cam_cc_cpas_ahb_clk = {
1912	.halt_reg = 0x13c90,
1913	.halt_check = BRANCH_HALT,
1914	.clkr = {
1915		.enable_reg = 0x13c90,
1916		.enable_mask = BIT(0),
1917		.hw.init = &(const struct clk_init_data) {
1918			.name = "cam_cc_cpas_ahb_clk",
1919			.parent_hws = (const struct clk_hw*[]) {
1920				&cam_cc_slow_ahb_clk_src.clkr.hw,
1921			},
1922			.num_parents = 1,
1923			.flags = CLK_SET_RATE_PARENT,
1924			.ops = &clk_branch2_ops,
1925		},
1926	},
1927};
1928
1929static struct clk_branch cam_cc_cpas_bps_clk = {
1930	.halt_reg = 0x103b0,
1931	.halt_check = BRANCH_HALT,
1932	.clkr = {
1933		.enable_reg = 0x103b0,
1934		.enable_mask = BIT(0),
1935		.hw.init = &(const struct clk_init_data) {
1936			.name = "cam_cc_cpas_bps_clk",
1937			.parent_hws = (const struct clk_hw*[]) {
1938				&cam_cc_bps_clk_src.clkr.hw,
1939			},
1940			.num_parents = 1,
1941			.flags = CLK_SET_RATE_PARENT,
1942			.ops = &clk_branch2_ops,
1943		},
1944	},
1945};
1946
1947static struct clk_branch cam_cc_cpas_cre_clk = {
1948	.halt_reg = 0x1366c,
1949	.halt_check = BRANCH_HALT,
1950	.clkr = {
1951		.enable_reg = 0x1366c,
1952		.enable_mask = BIT(0),
1953		.hw.init = &(const struct clk_init_data) {
1954			.name = "cam_cc_cpas_cre_clk",
1955			.parent_hws = (const struct clk_hw*[]) {
1956				&cam_cc_cre_clk_src.clkr.hw,
1957			},
1958			.num_parents = 1,
1959			.flags = CLK_SET_RATE_PARENT,
1960			.ops = &clk_branch2_ops,
1961		},
1962	},
1963};
1964
1965static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
1966	.halt_reg = 0x13c9c,
1967	.halt_check = BRANCH_HALT,
1968	.clkr = {
1969		.enable_reg = 0x13c9c,
1970		.enable_mask = BIT(0),
1971		.hw.init = &(const struct clk_init_data) {
1972			.name = "cam_cc_cpas_fast_ahb_clk",
1973			.parent_hws = (const struct clk_hw*[]) {
1974				&cam_cc_fast_ahb_clk_src.clkr.hw,
1975			},
1976			.num_parents = 1,
1977			.flags = CLK_SET_RATE_PARENT,
1978			.ops = &clk_branch2_ops,
1979		},
1980	},
1981};
1982
1983static struct clk_branch cam_cc_cpas_ife_0_clk = {
1984	.halt_reg = 0x11150,
1985	.halt_check = BRANCH_HALT,
1986	.clkr = {
1987		.enable_reg = 0x11150,
1988		.enable_mask = BIT(0),
1989		.hw.init = &(const struct clk_init_data) {
1990			.name = "cam_cc_cpas_ife_0_clk",
1991			.parent_hws = (const struct clk_hw*[]) {
1992				&cam_cc_ife_0_clk_src.clkr.hw,
1993			},
1994			.num_parents = 1,
1995			.flags = CLK_SET_RATE_PARENT,
1996			.ops = &clk_branch2_ops,
1997		},
1998	},
1999};
2000
2001static struct clk_branch cam_cc_cpas_ife_1_clk = {
2002	.halt_reg = 0x12150,
2003	.halt_check = BRANCH_HALT,
2004	.clkr = {
2005		.enable_reg = 0x12150,
2006		.enable_mask = BIT(0),
2007		.hw.init = &(const struct clk_init_data) {
2008			.name = "cam_cc_cpas_ife_1_clk",
2009			.parent_hws = (const struct clk_hw*[]) {
2010				&cam_cc_ife_1_clk_src.clkr.hw,
2011			},
2012			.num_parents = 1,
2013			.flags = CLK_SET_RATE_PARENT,
2014			.ops = &clk_branch2_ops,
2015		},
2016	},
2017};
2018
2019static struct clk_branch cam_cc_cpas_ife_2_clk = {
2020	.halt_reg = 0x123e0,
2021	.halt_check = BRANCH_HALT,
2022	.clkr = {
2023		.enable_reg = 0x123e0,
2024		.enable_mask = BIT(0),
2025		.hw.init = &(const struct clk_init_data) {
2026			.name = "cam_cc_cpas_ife_2_clk",
2027			.parent_hws = (const struct clk_hw*[]) {
2028				&cam_cc_ife_2_clk_src.clkr.hw,
2029			},
2030			.num_parents = 1,
2031			.flags = CLK_SET_RATE_PARENT,
2032			.ops = &clk_branch2_ops,
2033		},
2034	},
2035};
2036
2037static struct clk_branch cam_cc_cpas_ife_lite_clk = {
2038	.halt_reg = 0x13138,
2039	.halt_check = BRANCH_HALT,
2040	.clkr = {
2041		.enable_reg = 0x13138,
2042		.enable_mask = BIT(0),
2043		.hw.init = &(const struct clk_init_data) {
2044			.name = "cam_cc_cpas_ife_lite_clk",
2045			.parent_hws = (const struct clk_hw*[]) {
2046				&cam_cc_ife_lite_clk_src.clkr.hw,
2047			},
2048			.num_parents = 1,
2049			.flags = CLK_SET_RATE_PARENT,
2050			.ops = &clk_branch2_ops,
2051		},
2052	},
2053};
2054
2055static struct clk_branch cam_cc_cpas_ipe_nps_clk = {
2056	.halt_reg = 0x10504,
2057	.halt_check = BRANCH_HALT,
2058	.clkr = {
2059		.enable_reg = 0x10504,
2060		.enable_mask = BIT(0),
2061		.hw.init = &(const struct clk_init_data) {
2062			.name = "cam_cc_cpas_ipe_nps_clk",
2063			.parent_hws = (const struct clk_hw*[]) {
2064				&cam_cc_ipe_nps_clk_src.clkr.hw,
2065			},
2066			.num_parents = 1,
2067			.flags = CLK_SET_RATE_PARENT,
2068			.ops = &clk_branch2_ops,
2069		},
2070	},
2071};
2072
2073static struct clk_branch cam_cc_cpas_sbi_clk = {
2074	.halt_reg = 0x1054c,
2075	.halt_check = BRANCH_HALT,
2076	.clkr = {
2077		.enable_reg = 0x1054c,
2078		.enable_mask = BIT(0),
2079		.hw.init = &(const struct clk_init_data) {
2080			.name = "cam_cc_cpas_sbi_clk",
2081			.parent_hws = (const struct clk_hw*[]) {
2082				&cam_cc_ife_0_clk_src.clkr.hw,
2083			},
2084			.num_parents = 1,
2085			.flags = CLK_SET_RATE_PARENT,
2086			.ops = &clk_branch2_ops,
2087		},
2088	},
2089};
2090
2091static struct clk_branch cam_cc_cpas_sfe_0_clk = {
2092	.halt_reg = 0x133cc,
2093	.halt_check = BRANCH_HALT,
2094	.clkr = {
2095		.enable_reg = 0x133cc,
2096		.enable_mask = BIT(0),
2097		.hw.init = &(const struct clk_init_data) {
2098			.name = "cam_cc_cpas_sfe_0_clk",
2099			.parent_hws = (const struct clk_hw*[]) {
2100				&cam_cc_sfe_0_clk_src.clkr.hw,
2101			},
2102			.num_parents = 1,
2103			.flags = CLK_SET_RATE_PARENT,
2104			.ops = &clk_branch2_ops,
2105		},
2106	},
2107};
2108
2109static struct clk_branch cam_cc_cpas_sfe_1_clk = {
2110	.halt_reg = 0x1352c,
2111	.halt_check = BRANCH_HALT,
2112	.clkr = {
2113		.enable_reg = 0x1352c,
2114		.enable_mask = BIT(0),
2115		.hw.init = &(const struct clk_init_data) {
2116			.name = "cam_cc_cpas_sfe_1_clk",
2117			.parent_hws = (const struct clk_hw*[]) {
2118				&cam_cc_sfe_1_clk_src.clkr.hw,
2119			},
2120			.num_parents = 1,
2121			.flags = CLK_SET_RATE_PARENT,
2122			.ops = &clk_branch2_ops,
2123		},
2124	},
2125};
2126
2127static struct clk_branch cam_cc_cre_ahb_clk = {
2128	.halt_reg = 0x13670,
2129	.halt_check = BRANCH_HALT,
2130	.clkr = {
2131		.enable_reg = 0x13670,
2132		.enable_mask = BIT(0),
2133		.hw.init = &(const struct clk_init_data) {
2134			.name = "cam_cc_cre_ahb_clk",
2135			.parent_hws = (const struct clk_hw*[]) {
2136				&cam_cc_slow_ahb_clk_src.clkr.hw,
2137			},
2138			.num_parents = 1,
2139			.flags = CLK_SET_RATE_PARENT,
2140			.ops = &clk_branch2_ops,
2141		},
2142	},
2143};
2144
2145static struct clk_branch cam_cc_cre_clk = {
2146	.halt_reg = 0x13668,
2147	.halt_check = BRANCH_HALT,
2148	.clkr = {
2149		.enable_reg = 0x13668,
2150		.enable_mask = BIT(0),
2151		.hw.init = &(const struct clk_init_data) {
2152			.name = "cam_cc_cre_clk",
2153			.parent_hws = (const struct clk_hw*[]) {
2154				&cam_cc_cre_clk_src.clkr.hw,
2155			},
2156			.num_parents = 1,
2157			.flags = CLK_SET_RATE_PARENT,
2158			.ops = &clk_branch2_ops,
2159		},
2160	},
2161};
2162
2163static struct clk_branch cam_cc_csi0phytimer_clk = {
2164	.halt_reg = 0x15aac,
2165	.halt_check = BRANCH_HALT,
2166	.clkr = {
2167		.enable_reg = 0x15aac,
2168		.enable_mask = BIT(0),
2169		.hw.init = &(const struct clk_init_data) {
2170			.name = "cam_cc_csi0phytimer_clk",
2171			.parent_hws = (const struct clk_hw*[]) {
2172				&cam_cc_csi0phytimer_clk_src.clkr.hw,
2173			},
2174			.num_parents = 1,
2175			.flags = CLK_SET_RATE_PARENT,
2176			.ops = &clk_branch2_ops,
2177		},
2178	},
2179};
2180
2181static struct clk_branch cam_cc_csi1phytimer_clk = {
2182	.halt_reg = 0x15be4,
2183	.halt_check = BRANCH_HALT,
2184	.clkr = {
2185		.enable_reg = 0x15be4,
2186		.enable_mask = BIT(0),
2187		.hw.init = &(const struct clk_init_data) {
2188			.name = "cam_cc_csi1phytimer_clk",
2189			.parent_hws = (const struct clk_hw*[]) {
2190				&cam_cc_csi1phytimer_clk_src.clkr.hw,
2191			},
2192			.num_parents = 1,
2193			.flags = CLK_SET_RATE_PARENT,
2194			.ops = &clk_branch2_ops,
2195		},
2196	},
2197};
2198
2199static struct clk_branch cam_cc_csi2phytimer_clk = {
2200	.halt_reg = 0x15d18,
2201	.halt_check = BRANCH_HALT,
2202	.clkr = {
2203		.enable_reg = 0x15d18,
2204		.enable_mask = BIT(0),
2205		.hw.init = &(const struct clk_init_data) {
2206			.name = "cam_cc_csi2phytimer_clk",
2207			.parent_hws = (const struct clk_hw*[]) {
2208				&cam_cc_csi2phytimer_clk_src.clkr.hw,
2209			},
2210			.num_parents = 1,
2211			.flags = CLK_SET_RATE_PARENT,
2212			.ops = &clk_branch2_ops,
2213		},
2214	},
2215};
2216
2217static struct clk_branch cam_cc_csi3phytimer_clk = {
2218	.halt_reg = 0x15e4c,
2219	.halt_check = BRANCH_HALT,
2220	.clkr = {
2221		.enable_reg = 0x15e4c,
2222		.enable_mask = BIT(0),
2223		.hw.init = &(const struct clk_init_data) {
2224			.name = "cam_cc_csi3phytimer_clk",
2225			.parent_hws = (const struct clk_hw*[]) {
2226				&cam_cc_csi3phytimer_clk_src.clkr.hw,
2227			},
2228			.num_parents = 1,
2229			.flags = CLK_SET_RATE_PARENT,
2230			.ops = &clk_branch2_ops,
2231		},
2232	},
2233};
2234
2235static struct clk_branch cam_cc_csi4phytimer_clk = {
2236	.halt_reg = 0x15f80,
2237	.halt_check = BRANCH_HALT,
2238	.clkr = {
2239		.enable_reg = 0x15f80,
2240		.enable_mask = BIT(0),
2241		.hw.init = &(const struct clk_init_data) {
2242			.name = "cam_cc_csi4phytimer_clk",
2243			.parent_hws = (const struct clk_hw*[]) {
2244				&cam_cc_csi4phytimer_clk_src.clkr.hw,
2245			},
2246			.num_parents = 1,
2247			.flags = CLK_SET_RATE_PARENT,
2248			.ops = &clk_branch2_ops,
2249		},
2250	},
2251};
2252
2253static struct clk_branch cam_cc_csi5phytimer_clk = {
2254	.halt_reg = 0x160b4,
2255	.halt_check = BRANCH_HALT,
2256	.clkr = {
2257		.enable_reg = 0x160b4,
2258		.enable_mask = BIT(0),
2259		.hw.init = &(const struct clk_init_data) {
2260			.name = "cam_cc_csi5phytimer_clk",
2261			.parent_hws = (const struct clk_hw*[]) {
2262				&cam_cc_csi5phytimer_clk_src.clkr.hw,
2263			},
2264			.num_parents = 1,
2265			.flags = CLK_SET_RATE_PARENT,
2266			.ops = &clk_branch2_ops,
2267		},
2268	},
2269};
2270
2271static struct clk_branch cam_cc_csi6phytimer_clk = {
2272	.halt_reg = 0x161e8,
2273	.halt_check = BRANCH_HALT,
2274	.clkr = {
2275		.enable_reg = 0x161e8,
2276		.enable_mask = BIT(0),
2277		.hw.init = &(const struct clk_init_data) {
2278			.name = "cam_cc_csi6phytimer_clk",
2279			.parent_hws = (const struct clk_hw*[]) {
2280				&cam_cc_csi6phytimer_clk_src.clkr.hw,
2281			},
2282			.num_parents = 1,
2283			.flags = CLK_SET_RATE_PARENT,
2284			.ops = &clk_branch2_ops,
2285		},
2286	},
2287};
2288
2289static struct clk_branch cam_cc_csi7phytimer_clk = {
2290	.halt_reg = 0x1631c,
2291	.halt_check = BRANCH_HALT,
2292	.clkr = {
2293		.enable_reg = 0x1631c,
2294		.enable_mask = BIT(0),
2295		.hw.init = &(const struct clk_init_data) {
2296			.name = "cam_cc_csi7phytimer_clk",
2297			.parent_hws = (const struct clk_hw*[]) {
2298				&cam_cc_csi7phytimer_clk_src.clkr.hw,
2299			},
2300			.num_parents = 1,
2301			.flags = CLK_SET_RATE_PARENT,
2302			.ops = &clk_branch2_ops,
2303		},
2304	},
2305};
2306
2307static struct clk_branch cam_cc_csid_clk = {
2308	.halt_reg = 0x13dd4,
2309	.halt_check = BRANCH_HALT,
2310	.clkr = {
2311		.enable_reg = 0x13dd4,
2312		.enable_mask = BIT(0),
2313		.hw.init = &(const struct clk_init_data) {
2314			.name = "cam_cc_csid_clk",
2315			.parent_hws = (const struct clk_hw*[]) {
2316				&cam_cc_csid_clk_src.clkr.hw,
2317			},
2318			.num_parents = 1,
2319			.flags = CLK_SET_RATE_PARENT,
2320			.ops = &clk_branch2_ops,
2321		},
2322	},
2323};
2324
2325static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
2326	.halt_reg = 0x15ab4,
2327	.halt_check = BRANCH_HALT,
2328	.clkr = {
2329		.enable_reg = 0x15ab4,
2330		.enable_mask = BIT(0),
2331		.hw.init = &(const struct clk_init_data) {
2332			.name = "cam_cc_csid_csiphy_rx_clk",
2333			.parent_hws = (const struct clk_hw*[]) {
2334				&cam_cc_cphy_rx_clk_src.clkr.hw,
2335			},
2336			.num_parents = 1,
2337			.flags = CLK_SET_RATE_PARENT,
2338			.ops = &clk_branch2_ops,
2339		},
2340	},
2341};
2342
2343static struct clk_branch cam_cc_csiphy0_clk = {
2344	.halt_reg = 0x15ab0,
2345	.halt_check = BRANCH_HALT,
2346	.clkr = {
2347		.enable_reg = 0x15ab0,
2348		.enable_mask = BIT(0),
2349		.hw.init = &(const struct clk_init_data) {
2350			.name = "cam_cc_csiphy0_clk",
2351			.parent_hws = (const struct clk_hw*[]) {
2352				&cam_cc_cphy_rx_clk_src.clkr.hw,
2353			},
2354			.num_parents = 1,
2355			.flags = CLK_SET_RATE_PARENT,
2356			.ops = &clk_branch2_ops,
2357		},
2358	},
2359};
2360
2361static struct clk_branch cam_cc_csiphy1_clk = {
2362	.halt_reg = 0x15be8,
2363	.halt_check = BRANCH_HALT,
2364	.clkr = {
2365		.enable_reg = 0x15be8,
2366		.enable_mask = BIT(0),
2367		.hw.init = &(const struct clk_init_data) {
2368			.name = "cam_cc_csiphy1_clk",
2369			.parent_hws = (const struct clk_hw*[]) {
2370				&cam_cc_cphy_rx_clk_src.clkr.hw,
2371			},
2372			.num_parents = 1,
2373			.flags = CLK_SET_RATE_PARENT,
2374			.ops = &clk_branch2_ops,
2375		},
2376	},
2377};
2378
2379static struct clk_branch cam_cc_csiphy2_clk = {
2380	.halt_reg = 0x15d1c,
2381	.halt_check = BRANCH_HALT,
2382	.clkr = {
2383		.enable_reg = 0x15d1c,
2384		.enable_mask = BIT(0),
2385		.hw.init = &(const struct clk_init_data) {
2386			.name = "cam_cc_csiphy2_clk",
2387			.parent_hws = (const struct clk_hw*[]) {
2388				&cam_cc_cphy_rx_clk_src.clkr.hw,
2389			},
2390			.num_parents = 1,
2391			.flags = CLK_SET_RATE_PARENT,
2392			.ops = &clk_branch2_ops,
2393		},
2394	},
2395};
2396
2397static struct clk_branch cam_cc_csiphy3_clk = {
2398	.halt_reg = 0x15e50,
2399	.halt_check = BRANCH_HALT,
2400	.clkr = {
2401		.enable_reg = 0x15e50,
2402		.enable_mask = BIT(0),
2403		.hw.init = &(const struct clk_init_data) {
2404			.name = "cam_cc_csiphy3_clk",
2405			.parent_hws = (const struct clk_hw*[]) {
2406				&cam_cc_cphy_rx_clk_src.clkr.hw,
2407			},
2408			.num_parents = 1,
2409			.flags = CLK_SET_RATE_PARENT,
2410			.ops = &clk_branch2_ops,
2411		},
2412	},
2413};
2414
2415static struct clk_branch cam_cc_csiphy4_clk = {
2416	.halt_reg = 0x15f84,
2417	.halt_check = BRANCH_HALT,
2418	.clkr = {
2419		.enable_reg = 0x15f84,
2420		.enable_mask = BIT(0),
2421		.hw.init = &(const struct clk_init_data) {
2422			.name = "cam_cc_csiphy4_clk",
2423			.parent_hws = (const struct clk_hw*[]) {
2424				&cam_cc_cphy_rx_clk_src.clkr.hw,
2425			},
2426			.num_parents = 1,
2427			.flags = CLK_SET_RATE_PARENT,
2428			.ops = &clk_branch2_ops,
2429		},
2430	},
2431};
2432
2433static struct clk_branch cam_cc_csiphy5_clk = {
2434	.halt_reg = 0x160b8,
2435	.halt_check = BRANCH_HALT,
2436	.clkr = {
2437		.enable_reg = 0x160b8,
2438		.enable_mask = BIT(0),
2439		.hw.init = &(const struct clk_init_data) {
2440			.name = "cam_cc_csiphy5_clk",
2441			.parent_hws = (const struct clk_hw*[]) {
2442				&cam_cc_cphy_rx_clk_src.clkr.hw,
2443			},
2444			.num_parents = 1,
2445			.flags = CLK_SET_RATE_PARENT,
2446			.ops = &clk_branch2_ops,
2447		},
2448	},
2449};
2450
2451static struct clk_branch cam_cc_csiphy6_clk = {
2452	.halt_reg = 0x161ec,
2453	.halt_check = BRANCH_HALT,
2454	.clkr = {
2455		.enable_reg = 0x161ec,
2456		.enable_mask = BIT(0),
2457		.hw.init = &(const struct clk_init_data) {
2458			.name = "cam_cc_csiphy6_clk",
2459			.parent_hws = (const struct clk_hw*[]) {
2460				&cam_cc_cphy_rx_clk_src.clkr.hw,
2461			},
2462			.num_parents = 1,
2463			.flags = CLK_SET_RATE_PARENT,
2464			.ops = &clk_branch2_ops,
2465		},
2466	},
2467};
2468
2469static struct clk_branch cam_cc_csiphy7_clk = {
2470	.halt_reg = 0x16320,
2471	.halt_check = BRANCH_HALT,
2472	.clkr = {
2473		.enable_reg = 0x16320,
2474		.enable_mask = BIT(0),
2475		.hw.init = &(const struct clk_init_data) {
2476			.name = "cam_cc_csiphy7_clk",
2477			.parent_hws = (const struct clk_hw*[]) {
2478				&cam_cc_cphy_rx_clk_src.clkr.hw,
2479			},
2480			.num_parents = 1,
2481			.flags = CLK_SET_RATE_PARENT,
2482			.ops = &clk_branch2_ops,
2483		},
2484	},
2485};
2486
2487static struct clk_branch cam_cc_drv_ahb_clk = {
2488	.halt_reg = 0x142d8,
2489	.halt_check = BRANCH_HALT,
2490	.clkr = {
2491		.enable_reg = 0x142d8,
2492		.enable_mask = BIT(0),
2493		.hw.init = &(const struct clk_init_data) {
2494			.name = "cam_cc_drv_ahb_clk",
2495			.parent_hws = (const struct clk_hw*[]) {
2496				&cam_cc_slow_ahb_clk_src.clkr.hw,
2497			},
2498			.num_parents = 1,
2499			.flags = CLK_SET_RATE_PARENT,
2500			.ops = &clk_branch2_ops,
2501		},
2502	},
2503};
2504
2505static struct clk_branch cam_cc_drv_xo_clk = {
2506	.halt_reg = 0x142d4,
2507	.halt_check = BRANCH_HALT,
2508	.clkr = {
2509		.enable_reg = 0x142d4,
2510		.enable_mask = BIT(0),
2511		.hw.init = &(const struct clk_init_data) {
2512			.name = "cam_cc_drv_xo_clk",
2513			.parent_hws = (const struct clk_hw*[]) {
2514				&cam_cc_xo_clk_src.clkr.hw,
2515			},
2516			.num_parents = 1,
2517			.flags = CLK_SET_RATE_PARENT,
2518			.ops = &clk_branch2_ops,
2519		},
2520	},
2521};
2522
2523static struct clk_branch cam_cc_icp_ahb_clk = {
2524	.halt_reg = 0x138fc,
2525	.halt_check = BRANCH_HALT,
2526	.clkr = {
2527		.enable_reg = 0x138fc,
2528		.enable_mask = BIT(0),
2529		.hw.init = &(const struct clk_init_data) {
2530			.name = "cam_cc_icp_ahb_clk",
2531			.parent_hws = (const struct clk_hw*[]) {
2532				&cam_cc_slow_ahb_clk_src.clkr.hw,
2533			},
2534			.num_parents = 1,
2535			.flags = CLK_SET_RATE_PARENT,
2536			.ops = &clk_branch2_ops,
2537		},
2538	},
2539};
2540
2541static struct clk_branch cam_cc_icp_clk = {
2542	.halt_reg = 0x138f0,
2543	.halt_check = BRANCH_HALT,
2544	.clkr = {
2545		.enable_reg = 0x138f0,
2546		.enable_mask = BIT(0),
2547		.hw.init = &(const struct clk_init_data) {
2548			.name = "cam_cc_icp_clk",
2549			.parent_hws = (const struct clk_hw*[]) {
2550				&cam_cc_icp_clk_src.clkr.hw,
2551			},
2552			.num_parents = 1,
2553			.flags = CLK_SET_RATE_PARENT,
2554			.ops = &clk_branch2_ops,
2555		},
2556	},
2557};
2558
2559static struct clk_branch cam_cc_ife_0_clk = {
2560	.halt_reg = 0x11144,
2561	.halt_check = BRANCH_HALT,
2562	.clkr = {
2563		.enable_reg = 0x11144,
2564		.enable_mask = BIT(0),
2565		.hw.init = &(const struct clk_init_data) {
2566			.name = "cam_cc_ife_0_clk",
2567			.parent_hws = (const struct clk_hw*[]) {
2568				&cam_cc_ife_0_clk_src.clkr.hw,
2569			},
2570			.num_parents = 1,
2571			.flags = CLK_SET_RATE_PARENT,
2572			.ops = &clk_branch2_ops,
2573		},
2574	},
2575};
2576
2577static struct clk_branch cam_cc_ife_0_dsp_clk = {
2578	.halt_reg = 0x11280,
2579	.halt_check = BRANCH_HALT,
2580	.clkr = {
2581		.enable_reg = 0x11280,
2582		.enable_mask = BIT(0),
2583		.hw.init = &(const struct clk_init_data) {
2584			.name = "cam_cc_ife_0_dsp_clk",
2585			.parent_hws = (const struct clk_hw*[]) {
2586				&cam_cc_ife_0_dsp_clk_src.clkr.hw,
2587			},
2588			.num_parents = 1,
2589			.flags = CLK_SET_RATE_PARENT,
2590			.ops = &clk_branch2_ops,
2591		},
2592	},
2593};
2594
2595static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
2596	.halt_reg = 0x1128c,
2597	.halt_check = BRANCH_HALT,
2598	.clkr = {
2599		.enable_reg = 0x1128c,
2600		.enable_mask = BIT(0),
2601		.hw.init = &(const struct clk_init_data) {
2602			.name = "cam_cc_ife_0_fast_ahb_clk",
2603			.parent_hws = (const struct clk_hw*[]) {
2604				&cam_cc_fast_ahb_clk_src.clkr.hw,
2605			},
2606			.num_parents = 1,
2607			.flags = CLK_SET_RATE_PARENT,
2608			.ops = &clk_branch2_ops,
2609		},
2610	},
2611};
2612
2613static struct clk_branch cam_cc_ife_1_clk = {
2614	.halt_reg = 0x12144,
2615	.halt_check = BRANCH_HALT,
2616	.clkr = {
2617		.enable_reg = 0x12144,
2618		.enable_mask = BIT(0),
2619		.hw.init = &(const struct clk_init_data) {
2620			.name = "cam_cc_ife_1_clk",
2621			.parent_hws = (const struct clk_hw*[]) {
2622				&cam_cc_ife_1_clk_src.clkr.hw,
2623			},
2624			.num_parents = 1,
2625			.flags = CLK_SET_RATE_PARENT,
2626			.ops = &clk_branch2_ops,
2627		},
2628	},
2629};
2630
2631static struct clk_branch cam_cc_ife_1_dsp_clk = {
2632	.halt_reg = 0x12280,
2633	.halt_check = BRANCH_HALT,
2634	.clkr = {
2635		.enable_reg = 0x12280,
2636		.enable_mask = BIT(0),
2637		.hw.init = &(const struct clk_init_data) {
2638			.name = "cam_cc_ife_1_dsp_clk",
2639			.parent_hws = (const struct clk_hw*[]) {
2640				&cam_cc_ife_1_dsp_clk_src.clkr.hw,
2641			},
2642			.num_parents = 1,
2643			.flags = CLK_SET_RATE_PARENT,
2644			.ops = &clk_branch2_ops,
2645		},
2646	},
2647};
2648
2649static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
2650	.halt_reg = 0x1228c,
2651	.halt_check = BRANCH_HALT,
2652	.clkr = {
2653		.enable_reg = 0x1228c,
2654		.enable_mask = BIT(0),
2655		.hw.init = &(const struct clk_init_data) {
2656			.name = "cam_cc_ife_1_fast_ahb_clk",
2657			.parent_hws = (const struct clk_hw*[]) {
2658				&cam_cc_fast_ahb_clk_src.clkr.hw,
2659			},
2660			.num_parents = 1,
2661			.flags = CLK_SET_RATE_PARENT,
2662			.ops = &clk_branch2_ops,
2663		},
2664	},
2665};
2666
2667static struct clk_branch cam_cc_ife_2_clk = {
2668	.halt_reg = 0x123d4,
2669	.halt_check = BRANCH_HALT,
2670	.clkr = {
2671		.enable_reg = 0x123d4,
2672		.enable_mask = BIT(0),
2673		.hw.init = &(const struct clk_init_data) {
2674			.name = "cam_cc_ife_2_clk",
2675			.parent_hws = (const struct clk_hw*[]) {
2676				&cam_cc_ife_2_clk_src.clkr.hw,
2677			},
2678			.num_parents = 1,
2679			.flags = CLK_SET_RATE_PARENT,
2680			.ops = &clk_branch2_ops,
2681		},
2682	},
2683};
2684
2685static struct clk_branch cam_cc_ife_2_dsp_clk = {
2686	.halt_reg = 0x12510,
2687	.halt_check = BRANCH_HALT,
2688	.clkr = {
2689		.enable_reg = 0x12510,
2690		.enable_mask = BIT(0),
2691		.hw.init = &(const struct clk_init_data) {
2692			.name = "cam_cc_ife_2_dsp_clk",
2693			.parent_hws = (const struct clk_hw*[]) {
2694				&cam_cc_ife_2_dsp_clk_src.clkr.hw,
2695			},
2696			.num_parents = 1,
2697			.flags = CLK_SET_RATE_PARENT,
2698			.ops = &clk_branch2_ops,
2699		},
2700	},
2701};
2702
2703static struct clk_branch cam_cc_ife_2_fast_ahb_clk = {
2704	.halt_reg = 0x1251c,
2705	.halt_check = BRANCH_HALT,
2706	.clkr = {
2707		.enable_reg = 0x1251c,
2708		.enable_mask = BIT(0),
2709		.hw.init = &(const struct clk_init_data) {
2710			.name = "cam_cc_ife_2_fast_ahb_clk",
2711			.parent_hws = (const struct clk_hw*[]) {
2712				&cam_cc_fast_ahb_clk_src.clkr.hw,
2713			},
2714			.num_parents = 1,
2715			.flags = CLK_SET_RATE_PARENT,
2716			.ops = &clk_branch2_ops,
2717		},
2718	},
2719};
2720
2721static struct clk_branch cam_cc_ife_lite_ahb_clk = {
2722	.halt_reg = 0x13278,
2723	.halt_check = BRANCH_HALT,
2724	.clkr = {
2725		.enable_reg = 0x13278,
2726		.enable_mask = BIT(0),
2727		.hw.init = &(const struct clk_init_data) {
2728			.name = "cam_cc_ife_lite_ahb_clk",
2729			.parent_hws = (const struct clk_hw*[]) {
2730				&cam_cc_slow_ahb_clk_src.clkr.hw,
2731			},
2732			.num_parents = 1,
2733			.flags = CLK_SET_RATE_PARENT,
2734			.ops = &clk_branch2_ops,
2735		},
2736	},
2737};
2738
2739static struct clk_branch cam_cc_ife_lite_clk = {
2740	.halt_reg = 0x1312c,
2741	.halt_check = BRANCH_HALT,
2742	.clkr = {
2743		.enable_reg = 0x1312c,
2744		.enable_mask = BIT(0),
2745		.hw.init = &(const struct clk_init_data) {
2746			.name = "cam_cc_ife_lite_clk",
2747			.parent_hws = (const struct clk_hw*[]) {
2748				&cam_cc_ife_lite_clk_src.clkr.hw,
2749			},
2750			.num_parents = 1,
2751			.flags = CLK_SET_RATE_PARENT,
2752			.ops = &clk_branch2_ops,
2753		},
2754	},
2755};
2756
2757static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
2758	.halt_reg = 0x13274,
2759	.halt_check = BRANCH_HALT,
2760	.clkr = {
2761		.enable_reg = 0x13274,
2762		.enable_mask = BIT(0),
2763		.hw.init = &(const struct clk_init_data) {
2764			.name = "cam_cc_ife_lite_cphy_rx_clk",
2765			.parent_hws = (const struct clk_hw*[]) {
2766				&cam_cc_cphy_rx_clk_src.clkr.hw,
2767			},
2768			.num_parents = 1,
2769			.flags = CLK_SET_RATE_PARENT,
2770			.ops = &clk_branch2_ops,
2771		},
2772	},
2773};
2774
2775static struct clk_branch cam_cc_ife_lite_csid_clk = {
2776	.halt_reg = 0x13268,
2777	.halt_check = BRANCH_HALT,
2778	.clkr = {
2779		.enable_reg = 0x13268,
2780		.enable_mask = BIT(0),
2781		.hw.init = &(const struct clk_init_data) {
2782			.name = "cam_cc_ife_lite_csid_clk",
2783			.parent_hws = (const struct clk_hw*[]) {
2784				&cam_cc_ife_lite_csid_clk_src.clkr.hw,
2785			},
2786			.num_parents = 1,
2787			.flags = CLK_SET_RATE_PARENT,
2788			.ops = &clk_branch2_ops,
2789		},
2790	},
2791};
2792
2793static struct clk_branch cam_cc_ipe_nps_ahb_clk = {
2794	.halt_reg = 0x1051c,
2795	.halt_check = BRANCH_HALT,
2796	.clkr = {
2797		.enable_reg = 0x1051c,
2798		.enable_mask = BIT(0),
2799		.hw.init = &(const struct clk_init_data) {
2800			.name = "cam_cc_ipe_nps_ahb_clk",
2801			.parent_hws = (const struct clk_hw*[]) {
2802				&cam_cc_slow_ahb_clk_src.clkr.hw,
2803			},
2804			.num_parents = 1,
2805			.flags = CLK_SET_RATE_PARENT,
2806			.ops = &clk_branch2_ops,
2807		},
2808	},
2809};
2810
2811static struct clk_branch cam_cc_ipe_nps_clk = {
2812	.halt_reg = 0x104f8,
2813	.halt_check = BRANCH_HALT,
2814	.clkr = {
2815		.enable_reg = 0x104f8,
2816		.enable_mask = BIT(0),
2817		.hw.init = &(const struct clk_init_data) {
2818			.name = "cam_cc_ipe_nps_clk",
2819			.parent_hws = (const struct clk_hw*[]) {
2820				&cam_cc_ipe_nps_clk_src.clkr.hw,
2821			},
2822			.num_parents = 1,
2823			.flags = CLK_SET_RATE_PARENT,
2824			.ops = &clk_branch2_ops,
2825		},
2826	},
2827};
2828
2829static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = {
2830	.halt_reg = 0x10520,
2831	.halt_check = BRANCH_HALT,
2832	.clkr = {
2833		.enable_reg = 0x10520,
2834		.enable_mask = BIT(0),
2835		.hw.init = &(const struct clk_init_data) {
2836			.name = "cam_cc_ipe_nps_fast_ahb_clk",
2837			.parent_hws = (const struct clk_hw*[]) {
2838				&cam_cc_fast_ahb_clk_src.clkr.hw,
2839			},
2840			.num_parents = 1,
2841			.flags = CLK_SET_RATE_PARENT,
2842			.ops = &clk_branch2_ops,
2843		},
2844	},
2845};
2846
2847static struct clk_branch cam_cc_ipe_pps_clk = {
2848	.halt_reg = 0x10508,
2849	.halt_check = BRANCH_HALT,
2850	.clkr = {
2851		.enable_reg = 0x10508,
2852		.enable_mask = BIT(0),
2853		.hw.init = &(const struct clk_init_data) {
2854			.name = "cam_cc_ipe_pps_clk",
2855			.parent_hws = (const struct clk_hw*[]) {
2856				&cam_cc_ipe_nps_clk_src.clkr.hw,
2857			},
2858			.num_parents = 1,
2859			.flags = CLK_SET_RATE_PARENT,
2860			.ops = &clk_branch2_ops,
2861		},
2862	},
2863};
2864
2865static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = {
2866	.halt_reg = 0x10524,
2867	.halt_check = BRANCH_HALT,
2868	.clkr = {
2869		.enable_reg = 0x10524,
2870		.enable_mask = BIT(0),
2871		.hw.init = &(const struct clk_init_data) {
2872			.name = "cam_cc_ipe_pps_fast_ahb_clk",
2873			.parent_hws = (const struct clk_hw*[]) {
2874				&cam_cc_fast_ahb_clk_src.clkr.hw,
2875			},
2876			.num_parents = 1,
2877			.flags = CLK_SET_RATE_PARENT,
2878			.ops = &clk_branch2_ops,
2879		},
2880	},
2881};
2882
2883static struct clk_branch cam_cc_jpeg_1_clk = {
2884	.halt_reg = 0x137ac,
2885	.halt_check = BRANCH_HALT,
2886	.clkr = {
2887		.enable_reg = 0x137ac,
2888		.enable_mask = BIT(0),
2889		.hw.init = &(const struct clk_init_data) {
2890			.name = "cam_cc_jpeg_1_clk",
2891			.parent_hws = (const struct clk_hw*[]) {
2892				&cam_cc_jpeg_clk_src.clkr.hw,
2893			},
2894			.num_parents = 1,
2895			.flags = CLK_SET_RATE_PARENT,
2896			.ops = &clk_branch2_ops,
2897		},
2898	},
2899};
2900
2901static struct clk_branch cam_cc_jpeg_clk = {
2902	.halt_reg = 0x137a0,
2903	.halt_check = BRANCH_HALT,
2904	.clkr = {
2905		.enable_reg = 0x137a0,
2906		.enable_mask = BIT(0),
2907		.hw.init = &(const struct clk_init_data) {
2908			.name = "cam_cc_jpeg_clk",
2909			.parent_hws = (const struct clk_hw*[]) {
2910				&cam_cc_jpeg_clk_src.clkr.hw,
2911			},
2912			.num_parents = 1,
2913			.flags = CLK_SET_RATE_PARENT,
2914			.ops = &clk_branch2_ops,
2915		},
2916	},
2917};
2918
2919static struct clk_branch cam_cc_mclk0_clk = {
2920	.halt_reg = 0x1512c,
2921	.halt_check = BRANCH_HALT,
2922	.clkr = {
2923		.enable_reg = 0x1512c,
2924		.enable_mask = BIT(0),
2925		.hw.init = &(const struct clk_init_data) {
2926			.name = "cam_cc_mclk0_clk",
2927			.parent_hws = (const struct clk_hw*[]) {
2928				&cam_cc_mclk0_clk_src.clkr.hw,
2929			},
2930			.num_parents = 1,
2931			.flags = CLK_SET_RATE_PARENT,
2932			.ops = &clk_branch2_ops,
2933		},
2934	},
2935};
2936
2937static struct clk_branch cam_cc_mclk1_clk = {
2938	.halt_reg = 0x1525c,
2939	.halt_check = BRANCH_HALT,
2940	.clkr = {
2941		.enable_reg = 0x1525c,
2942		.enable_mask = BIT(0),
2943		.hw.init = &(const struct clk_init_data) {
2944			.name = "cam_cc_mclk1_clk",
2945			.parent_hws = (const struct clk_hw*[]) {
2946				&cam_cc_mclk1_clk_src.clkr.hw,
2947			},
2948			.num_parents = 1,
2949			.flags = CLK_SET_RATE_PARENT,
2950			.ops = &clk_branch2_ops,
2951		},
2952	},
2953};
2954
2955static struct clk_branch cam_cc_mclk2_clk = {
2956	.halt_reg = 0x1538c,
2957	.halt_check = BRANCH_HALT,
2958	.clkr = {
2959		.enable_reg = 0x1538c,
2960		.enable_mask = BIT(0),
2961		.hw.init = &(const struct clk_init_data) {
2962			.name = "cam_cc_mclk2_clk",
2963			.parent_hws = (const struct clk_hw*[]) {
2964				&cam_cc_mclk2_clk_src.clkr.hw,
2965			},
2966			.num_parents = 1,
2967			.flags = CLK_SET_RATE_PARENT,
2968			.ops = &clk_branch2_ops,
2969		},
2970	},
2971};
2972
2973static struct clk_branch cam_cc_mclk3_clk = {
2974	.halt_reg = 0x154bc,
2975	.halt_check = BRANCH_HALT,
2976	.clkr = {
2977		.enable_reg = 0x154bc,
2978		.enable_mask = BIT(0),
2979		.hw.init = &(const struct clk_init_data) {
2980			.name = "cam_cc_mclk3_clk",
2981			.parent_hws = (const struct clk_hw*[]) {
2982				&cam_cc_mclk3_clk_src.clkr.hw,
2983			},
2984			.num_parents = 1,
2985			.flags = CLK_SET_RATE_PARENT,
2986			.ops = &clk_branch2_ops,
2987		},
2988	},
2989};
2990
2991static struct clk_branch cam_cc_mclk4_clk = {
2992	.halt_reg = 0x155ec,
2993	.halt_check = BRANCH_HALT,
2994	.clkr = {
2995		.enable_reg = 0x155ec,
2996		.enable_mask = BIT(0),
2997		.hw.init = &(const struct clk_init_data) {
2998			.name = "cam_cc_mclk4_clk",
2999			.parent_hws = (const struct clk_hw*[]) {
3000				&cam_cc_mclk4_clk_src.clkr.hw,
3001			},
3002			.num_parents = 1,
3003			.flags = CLK_SET_RATE_PARENT,
3004			.ops = &clk_branch2_ops,
3005		},
3006	},
3007};
3008
3009static struct clk_branch cam_cc_mclk5_clk = {
3010	.halt_reg = 0x1571c,
3011	.halt_check = BRANCH_HALT,
3012	.clkr = {
3013		.enable_reg = 0x1571c,
3014		.enable_mask = BIT(0),
3015		.hw.init = &(const struct clk_init_data) {
3016			.name = "cam_cc_mclk5_clk",
3017			.parent_hws = (const struct clk_hw*[]) {
3018				&cam_cc_mclk5_clk_src.clkr.hw,
3019			},
3020			.num_parents = 1,
3021			.flags = CLK_SET_RATE_PARENT,
3022			.ops = &clk_branch2_ops,
3023		},
3024	},
3025};
3026
3027static struct clk_branch cam_cc_mclk6_clk = {
3028	.halt_reg = 0x1584c,
3029	.halt_check = BRANCH_HALT,
3030	.clkr = {
3031		.enable_reg = 0x1584c,
3032		.enable_mask = BIT(0),
3033		.hw.init = &(const struct clk_init_data) {
3034			.name = "cam_cc_mclk6_clk",
3035			.parent_hws = (const struct clk_hw*[]) {
3036				&cam_cc_mclk6_clk_src.clkr.hw,
3037			},
3038			.num_parents = 1,
3039			.flags = CLK_SET_RATE_PARENT,
3040			.ops = &clk_branch2_ops,
3041		},
3042	},
3043};
3044
3045static struct clk_branch cam_cc_mclk7_clk = {
3046	.halt_reg = 0x1597c,
3047	.halt_check = BRANCH_HALT,
3048	.clkr = {
3049		.enable_reg = 0x1597c,
3050		.enable_mask = BIT(0),
3051		.hw.init = &(const struct clk_init_data) {
3052			.name = "cam_cc_mclk7_clk",
3053			.parent_hws = (const struct clk_hw*[]) {
3054				&cam_cc_mclk7_clk_src.clkr.hw,
3055			},
3056			.num_parents = 1,
3057			.flags = CLK_SET_RATE_PARENT,
3058			.ops = &clk_branch2_ops,
3059		},
3060	},
3061};
3062
3063static struct clk_branch cam_cc_qdss_debug_clk = {
3064	.halt_reg = 0x14050,
3065	.halt_check = BRANCH_HALT,
3066	.clkr = {
3067		.enable_reg = 0x14050,
3068		.enable_mask = BIT(0),
3069		.hw.init = &(const struct clk_init_data) {
3070			.name = "cam_cc_qdss_debug_clk",
3071			.parent_hws = (const struct clk_hw*[]) {
3072				&cam_cc_qdss_debug_clk_src.clkr.hw,
3073			},
3074			.num_parents = 1,
3075			.flags = CLK_SET_RATE_PARENT,
3076			.ops = &clk_branch2_ops,
3077		},
3078	},
3079};
3080
3081static struct clk_branch cam_cc_qdss_debug_xo_clk = {
3082	.halt_reg = 0x14054,
3083	.halt_check = BRANCH_HALT,
3084	.clkr = {
3085		.enable_reg = 0x14054,
3086		.enable_mask = BIT(0),
3087		.hw.init = &(const struct clk_init_data) {
3088			.name = "cam_cc_qdss_debug_xo_clk",
3089			.parent_hws = (const struct clk_hw*[]) {
3090				&cam_cc_xo_clk_src.clkr.hw,
3091			},
3092			.num_parents = 1,
3093			.flags = CLK_SET_RATE_PARENT,
3094			.ops = &clk_branch2_ops,
3095		},
3096	},
3097};
3098
3099static struct clk_branch cam_cc_sbi_clk = {
3100	.halt_reg = 0x10540,
3101	.halt_check = BRANCH_HALT,
3102	.clkr = {
3103		.enable_reg = 0x10540,
3104		.enable_mask = BIT(0),
3105		.hw.init = &(const struct clk_init_data) {
3106			.name = "cam_cc_sbi_clk",
3107			.parent_hws = (const struct clk_hw*[]) {
3108				&cam_cc_ife_0_clk_src.clkr.hw,
3109			},
3110			.num_parents = 1,
3111			.flags = CLK_SET_RATE_PARENT,
3112			.ops = &clk_branch2_ops,
3113		},
3114	},
3115};
3116
3117static struct clk_branch cam_cc_sbi_fast_ahb_clk = {
3118	.halt_reg = 0x10550,
3119	.halt_check = BRANCH_HALT,
3120	.clkr = {
3121		.enable_reg = 0x10550,
3122		.enable_mask = BIT(0),
3123		.hw.init = &(const struct clk_init_data) {
3124			.name = "cam_cc_sbi_fast_ahb_clk",
3125			.parent_hws = (const struct clk_hw*[]) {
3126				&cam_cc_fast_ahb_clk_src.clkr.hw,
3127			},
3128			.num_parents = 1,
3129			.flags = CLK_SET_RATE_PARENT,
3130			.ops = &clk_branch2_ops,
3131		},
3132	},
3133};
3134
3135static struct clk_branch cam_cc_sfe_0_clk = {
3136	.halt_reg = 0x133c0,
3137	.halt_check = BRANCH_HALT,
3138	.clkr = {
3139		.enable_reg = 0x133c0,
3140		.enable_mask = BIT(0),
3141		.hw.init = &(const struct clk_init_data) {
3142			.name = "cam_cc_sfe_0_clk",
3143			.parent_hws = (const struct clk_hw*[]) {
3144				&cam_cc_sfe_0_clk_src.clkr.hw,
3145			},
3146			.num_parents = 1,
3147			.flags = CLK_SET_RATE_PARENT,
3148			.ops = &clk_branch2_ops,
3149		},
3150	},
3151};
3152
3153static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = {
3154	.halt_reg = 0x133d8,
3155	.halt_check = BRANCH_HALT,
3156	.clkr = {
3157		.enable_reg = 0x133d8,
3158		.enable_mask = BIT(0),
3159		.hw.init = &(const struct clk_init_data) {
3160			.name = "cam_cc_sfe_0_fast_ahb_clk",
3161			.parent_hws = (const struct clk_hw*[]) {
3162				&cam_cc_fast_ahb_clk_src.clkr.hw,
3163			},
3164			.num_parents = 1,
3165			.flags = CLK_SET_RATE_PARENT,
3166			.ops = &clk_branch2_ops,
3167		},
3168	},
3169};
3170
3171static struct clk_branch cam_cc_sfe_1_clk = {
3172	.halt_reg = 0x13520,
3173	.halt_check = BRANCH_HALT,
3174	.clkr = {
3175		.enable_reg = 0x13520,
3176		.enable_mask = BIT(0),
3177		.hw.init = &(const struct clk_init_data) {
3178			.name = "cam_cc_sfe_1_clk",
3179			.parent_hws = (const struct clk_hw*[]) {
3180				&cam_cc_sfe_1_clk_src.clkr.hw,
3181			},
3182			.num_parents = 1,
3183			.flags = CLK_SET_RATE_PARENT,
3184			.ops = &clk_branch2_ops,
3185		},
3186	},
3187};
3188
3189static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
3190	.halt_reg = 0x13538,
3191	.halt_check = BRANCH_HALT,
3192	.clkr = {
3193		.enable_reg = 0x13538,
3194		.enable_mask = BIT(0),
3195		.hw.init = &(const struct clk_init_data) {
3196			.name = "cam_cc_sfe_1_fast_ahb_clk",
3197			.parent_hws = (const struct clk_hw*[]) {
3198				&cam_cc_fast_ahb_clk_src.clkr.hw,
3199			},
3200			.num_parents = 1,
3201			.flags = CLK_SET_RATE_PARENT,
3202			.ops = &clk_branch2_ops,
3203		},
3204	},
3205};
3206
3207static struct gdsc cam_cc_titan_top_gdsc;
3208
3209static struct gdsc cam_cc_bps_gdsc = {
3210	.gdscr = 0x10004,
3211	.en_rest_wait_val = 0x2,
3212	.en_few_wait_val = 0x2,
3213	.clk_dis_wait_val = 0xf,
3214	.pd = {
3215		.name = "cam_cc_bps_gdsc",
3216	},
3217	.pwrsts = PWRSTS_OFF_ON,
3218	.parent = &cam_cc_titan_top_gdsc.pd,
3219	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3220};
3221
3222static struct gdsc cam_cc_ife_0_gdsc = {
3223	.gdscr = 0x11004,
3224	.en_rest_wait_val = 0x2,
3225	.en_few_wait_val = 0x2,
3226	.clk_dis_wait_val = 0xf,
3227	.pd = {
3228		.name = "cam_cc_ife_0_gdsc",
3229	},
3230	.pwrsts = PWRSTS_OFF_ON,
3231	.parent = &cam_cc_titan_top_gdsc.pd,
3232	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3233};
3234
3235static struct gdsc cam_cc_ife_1_gdsc = {
3236	.gdscr = 0x12004,
3237	.en_rest_wait_val = 0x2,
3238	.en_few_wait_val = 0x2,
3239	.clk_dis_wait_val = 0xf,
3240	.pd = {
3241		.name = "cam_cc_ife_1_gdsc",
3242	},
3243	.pwrsts = PWRSTS_OFF_ON,
3244	.parent = &cam_cc_titan_top_gdsc.pd,
3245	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3246};
3247
3248static struct gdsc cam_cc_ife_2_gdsc = {
3249	.gdscr = 0x12294,
3250	.en_rest_wait_val = 0x2,
3251	.en_few_wait_val = 0x2,
3252	.clk_dis_wait_val = 0xf,
3253	.pd = {
3254		.name = "cam_cc_ife_2_gdsc",
3255	},
3256	.pwrsts = PWRSTS_OFF_ON,
3257	.parent = &cam_cc_titan_top_gdsc.pd,
3258	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3259};
3260
3261static struct gdsc cam_cc_ipe_0_gdsc = {
3262	.gdscr = 0x103b8,
3263	.en_rest_wait_val = 0x2,
3264	.en_few_wait_val = 0x2,
3265	.clk_dis_wait_val = 0xf,
3266	.pd = {
3267		.name = "cam_cc_ipe_0_gdsc",
3268	},
3269	.pwrsts = PWRSTS_OFF_ON,
3270	.parent = &cam_cc_titan_top_gdsc.pd,
3271	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3272};
3273
3274static struct gdsc cam_cc_sbi_gdsc = {
3275	.gdscr = 0x1052c,
3276	.en_rest_wait_val = 0x2,
3277	.en_few_wait_val = 0x2,
3278	.clk_dis_wait_val = 0xf,
3279	.pd = {
3280		.name = "cam_cc_sbi_gdsc",
3281	},
3282	.pwrsts = PWRSTS_OFF_ON,
3283	.parent = &cam_cc_titan_top_gdsc.pd,
3284	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3285};
3286
3287static struct gdsc cam_cc_sfe_0_gdsc = {
3288	.gdscr = 0x13280,
3289	.en_rest_wait_val = 0x2,
3290	.en_few_wait_val = 0x2,
3291	.clk_dis_wait_val = 0xf,
3292	.pd = {
3293		.name = "cam_cc_sfe_0_gdsc",
3294	},
3295	.pwrsts = PWRSTS_OFF_ON,
3296	.parent = &cam_cc_titan_top_gdsc.pd,
3297	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3298};
3299
3300static struct gdsc cam_cc_sfe_1_gdsc = {
3301	.gdscr = 0x133e0,
3302	.en_rest_wait_val = 0x2,
3303	.en_few_wait_val = 0x2,
3304	.clk_dis_wait_val = 0xf,
3305	.pd = {
3306		.name = "cam_cc_sfe_1_gdsc",
3307	},
3308	.pwrsts = PWRSTS_OFF_ON,
3309	.parent = &cam_cc_titan_top_gdsc.pd,
3310	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3311};
3312
3313static struct gdsc cam_cc_titan_top_gdsc = {
3314	.gdscr = 0x14058,
3315	.en_rest_wait_val = 0x2,
3316	.en_few_wait_val = 0x2,
3317	.clk_dis_wait_val = 0xf,
3318	.pd = {
3319		.name = "cam_cc_titan_top_gdsc",
3320	},
3321	.pwrsts = PWRSTS_OFF_ON,
3322	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3323};
3324
3325static struct clk_regmap *cam_cc_sm8550_clocks[] = {
3326	[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
3327	[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
3328	[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
3329	[CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr,
3330	[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
3331	[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
3332	[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
3333	[CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr,
3334	[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
3335	[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
3336	[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
3337	[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
3338	[CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr,
3339	[CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr,
3340	[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
3341	[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
3342	[CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr,
3343	[CAM_CC_CPAS_CRE_CLK] = &cam_cc_cpas_cre_clk.clkr,
3344	[CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
3345	[CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
3346	[CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
3347	[CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr,
3348	[CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
3349	[CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr,
3350	[CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr,
3351	[CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr,
3352	[CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr,
3353	[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
3354	[CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr,
3355	[CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr,
3356	[CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr,
3357	[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
3358	[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
3359	[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
3360	[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
3361	[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
3362	[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
3363	[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
3364	[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
3365	[CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
3366	[CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
3367	[CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
3368	[CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
3369	[CAM_CC_CSI6PHYTIMER_CLK] = &cam_cc_csi6phytimer_clk.clkr,
3370	[CAM_CC_CSI6PHYTIMER_CLK_SRC] = &cam_cc_csi6phytimer_clk_src.clkr,
3371	[CAM_CC_CSI7PHYTIMER_CLK] = &cam_cc_csi7phytimer_clk.clkr,
3372	[CAM_CC_CSI7PHYTIMER_CLK_SRC] = &cam_cc_csi7phytimer_clk_src.clkr,
3373	[CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
3374	[CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
3375	[CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
3376	[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
3377	[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
3378	[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
3379	[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
3380	[CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
3381	[CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
3382	[CAM_CC_CSIPHY6_CLK] = &cam_cc_csiphy6_clk.clkr,
3383	[CAM_CC_CSIPHY7_CLK] = &cam_cc_csiphy7_clk.clkr,
3384	[CAM_CC_DRV_AHB_CLK] = &cam_cc_drv_ahb_clk.clkr,
3385	[CAM_CC_DRV_XO_CLK] = &cam_cc_drv_xo_clk.clkr,
3386	[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
3387	[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
3388	[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
3389	[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
3390	[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
3391	[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
3392	[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
3393	[CAM_CC_IFE_0_DSP_CLK_SRC] = &cam_cc_ife_0_dsp_clk_src.clkr,
3394	[CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
3395	[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
3396	[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
3397	[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
3398	[CAM_CC_IFE_1_DSP_CLK_SRC] = &cam_cc_ife_1_dsp_clk_src.clkr,
3399	[CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
3400	[CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
3401	[CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
3402	[CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr,
3403	[CAM_CC_IFE_2_DSP_CLK_SRC] = &cam_cc_ife_2_dsp_clk_src.clkr,
3404	[CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr,
3405	[CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
3406	[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
3407	[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
3408	[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
3409	[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
3410	[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
3411	[CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr,
3412	[CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr,
3413	[CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr,
3414	[CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr,
3415	[CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr,
3416	[CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr,
3417	[CAM_CC_JPEG_1_CLK] = &cam_cc_jpeg_1_clk.clkr,
3418	[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
3419	[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
3420	[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
3421	[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
3422	[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
3423	[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
3424	[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
3425	[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
3426	[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
3427	[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
3428	[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
3429	[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
3430	[CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
3431	[CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
3432	[CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
3433	[CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
3434	[CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr,
3435	[CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr,
3436	[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
3437	[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
3438	[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
3439	[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
3440	[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
3441	[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
3442	[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
3443	[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
3444	[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
3445	[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
3446	[CAM_CC_PLL5] = &cam_cc_pll5.clkr,
3447	[CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
3448	[CAM_CC_PLL6] = &cam_cc_pll6.clkr,
3449	[CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
3450	[CAM_CC_PLL7] = &cam_cc_pll7.clkr,
3451	[CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr,
3452	[CAM_CC_PLL8] = &cam_cc_pll8.clkr,
3453	[CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr,
3454	[CAM_CC_PLL9] = &cam_cc_pll9.clkr,
3455	[CAM_CC_PLL9_OUT_EVEN] = &cam_cc_pll9_out_even.clkr,
3456	[CAM_CC_PLL10] = &cam_cc_pll10.clkr,
3457	[CAM_CC_PLL10_OUT_EVEN] = &cam_cc_pll10_out_even.clkr,
3458	[CAM_CC_PLL11] = &cam_cc_pll11.clkr,
3459	[CAM_CC_PLL11_OUT_EVEN] = &cam_cc_pll11_out_even.clkr,
3460	[CAM_CC_PLL12] = &cam_cc_pll12.clkr,
3461	[CAM_CC_PLL12_OUT_EVEN] = &cam_cc_pll12_out_even.clkr,
3462	[CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr,
3463	[CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr,
3464	[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
3465	[CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
3466	[CAM_CC_SBI_FAST_AHB_CLK] = &cam_cc_sbi_fast_ahb_clk.clkr,
3467	[CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
3468	[CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr,
3469	[CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr,
3470	[CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr,
3471	[CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr,
3472	[CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr,
3473	[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
3474	[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
3475	[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
3476};
3477
3478static struct gdsc *cam_cc_sm8550_gdscs[] = {
3479	[CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc,
3480	[CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc,
3481	[CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc,
3482	[CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc,
3483	[CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc,
3484	[CAM_CC_SBI_GDSC] = &cam_cc_sbi_gdsc,
3485	[CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc,
3486	[CAM_CC_SFE_1_GDSC] = &cam_cc_sfe_1_gdsc,
3487	[CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc,
3488};
3489
3490static const struct qcom_reset_map cam_cc_sm8550_resets[] = {
3491	[CAM_CC_BPS_BCR] = { 0x10000 },
3492	[CAM_CC_DRV_BCR] = { 0x142d0 },
3493	[CAM_CC_ICP_BCR] = { 0x137c0 },
3494	[CAM_CC_IFE_0_BCR] = { 0x11000 },
3495	[CAM_CC_IFE_1_BCR] = { 0x12000 },
3496	[CAM_CC_IFE_2_BCR] = { 0x12290 },
3497	[CAM_CC_IPE_0_BCR] = { 0x103b4 },
3498	[CAM_CC_QDSS_DEBUG_BCR] = { 0x13f20 },
3499	[CAM_CC_SBI_BCR] = { 0x10528 },
3500	[CAM_CC_SFE_0_BCR] = { 0x1327c },
3501	[CAM_CC_SFE_1_BCR] = { 0x133dc },
3502};
3503
3504static struct clk_alpha_pll *cam_cc_sm8550_plls[] = {
3505	&cam_cc_pll0,
3506	&cam_cc_pll1,
3507	&cam_cc_pll2,
3508	&cam_cc_pll3,
3509	&cam_cc_pll4,
3510	&cam_cc_pll5,
3511	&cam_cc_pll6,
3512	&cam_cc_pll7,
3513	&cam_cc_pll8,
3514	&cam_cc_pll9,
3515	&cam_cc_pll10,
3516	&cam_cc_pll11,
3517	&cam_cc_pll12,
3518};
3519
3520static u32 cam_cc_sm8550_critical_cbcrs[] = {
3521	0x1419c, /* CAM_CC_GDSC_CLK */
3522	0x142cc, /* CAM_CC_SLEEP_CLK */
3523};
3524
3525static const struct regmap_config cam_cc_sm8550_regmap_config = {
3526	.reg_bits = 32,
3527	.reg_stride = 4,
3528	.val_bits = 32,
3529	.max_register = 0x16320,
3530	.fast_io = true,
3531};
3532
3533static struct qcom_cc_driver_data cam_cc_sm8550_driver_data = {
3534	.alpha_plls = cam_cc_sm8550_plls,
3535	.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8550_plls),
3536	.clk_cbcrs = cam_cc_sm8550_critical_cbcrs,
3537	.num_clk_cbcrs = ARRAY_SIZE(cam_cc_sm8550_critical_cbcrs),
3538};
3539
3540static const struct qcom_cc_desc cam_cc_sm8550_desc = {
3541	.config = &cam_cc_sm8550_regmap_config,
3542	.clks = cam_cc_sm8550_clocks,
3543	.num_clks = ARRAY_SIZE(cam_cc_sm8550_clocks),
3544	.resets = cam_cc_sm8550_resets,
3545	.num_resets = ARRAY_SIZE(cam_cc_sm8550_resets),
3546	.gdscs = cam_cc_sm8550_gdscs,
3547	.num_gdscs = ARRAY_SIZE(cam_cc_sm8550_gdscs),
3548	.use_rpm = true,
3549	.driver_data = &cam_cc_sm8550_driver_data,
3550};
3551
3552static const struct of_device_id cam_cc_sm8550_match_table[] = {
3553	{ .compatible = "qcom,sm8550-camcc" },
3554	{ }
3555};
3556MODULE_DEVICE_TABLE(of, cam_cc_sm8550_match_table);
3557
3558static int cam_cc_sm8550_probe(struct platform_device *pdev)
3559{
3560	return qcom_cc_probe(pdev, &cam_cc_sm8550_desc);
3561}
3562
3563static struct platform_driver cam_cc_sm8550_driver = {
3564	.probe = cam_cc_sm8550_probe,
3565	.driver = {
3566		.name = "cam_cc-sm8550",
3567		.of_match_table = cam_cc_sm8550_match_table,
3568	},
3569};
3570
3571module_platform_driver(cam_cc_sm8550_driver);
3572
3573MODULE_DESCRIPTION("QTI CAMCC SM8550 Driver");
3574MODULE_LICENSE("GPL");