camcc-sm8450.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/mod_devicetable.h>
   8#include <linux/module.h>
   9#include <linux/platform_device.h>
  10#include <linux/regmap.h>
  11
  12#include <dt-bindings/clock/qcom,sm8450-camcc.h>
  13
  14#include "clk-alpha-pll.h"
  15#include "clk-branch.h"
  16#include "clk-pll.h"
  17#include "clk-rcg.h"
  18#include "clk-regmap-divider.h"
  19#include "clk-regmap-mux.h"
  20#include "clk-regmap.h"
  21#include "common.h"
  22#include "gdsc.h"
  23#include "reset.h"
  24
  25enum {
  26	DT_IFACE,
  27	DT_BI_TCXO,
  28	DT_BI_TCXO_AO,
  29	DT_SLEEP_CLK
  30};
  31
  32enum {
  33	P_BI_TCXO,
  34	P_CAM_CC_PLL0_OUT_EVEN,
  35	P_CAM_CC_PLL0_OUT_MAIN,
  36	P_CAM_CC_PLL0_OUT_ODD,
  37	P_CAM_CC_PLL1_OUT_EVEN,
  38	P_CAM_CC_PLL2_OUT_EVEN,
  39	P_CAM_CC_PLL2_OUT_MAIN,
  40	P_CAM_CC_PLL3_OUT_EVEN,
  41	P_CAM_CC_PLL4_OUT_EVEN,
  42	P_CAM_CC_PLL5_OUT_EVEN,
  43	P_CAM_CC_PLL6_OUT_EVEN,
  44	P_CAM_CC_PLL7_OUT_EVEN,
  45	P_CAM_CC_PLL8_OUT_EVEN,
  46	P_SLEEP_CLK,
  47};
  48
  49static const struct pll_vco lucid_evo_vco[] = {
  50	{ 249600000, 2000000000, 0 },
  51};
  52
  53static const struct pll_vco rivian_evo_vco[] = {
  54	{ 864000000, 1056000000, 0 },
  55};
  56
  57static const struct pll_vco rivian_ole_vco[] = {
  58	{ 864000000, 1075000000, 0 },
  59};
  60
  61static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO };
  62
  63static const struct alpha_pll_config cam_cc_pll0_config = {
  64	.l = 0x3e,
  65	.alpha = 0x8000,
  66	.config_ctl_val = 0x20485699,
  67	.config_ctl_hi_val = 0x00182261,
  68	.config_ctl_hi1_val = 0x32aa299c,
  69	.user_ctl_val = 0x00008400,
  70	.user_ctl_hi_val = 0x00000805,
  71};
  72
  73static const struct alpha_pll_config sm8475_cam_cc_pll0_config = {
  74	.l = 0x3e,
  75	.alpha = 0x8000,
  76	.config_ctl_val = 0x20485699,
  77	.config_ctl_hi_val = 0x00182261,
  78	.config_ctl_hi1_val = 0x82aa299c,
  79	.test_ctl_val = 0x00000000,
  80	.test_ctl_hi_val = 0x00000003,
  81	.test_ctl_hi1_val = 0x00009000,
  82	.test_ctl_hi2_val = 0x00000034,
  83	.user_ctl_val = 0x00008400,
  84	.user_ctl_hi_val = 0x00000005,
  85};
  86
  87static struct clk_alpha_pll cam_cc_pll0 = {
  88	.offset = 0x0,
  89	.config = &cam_cc_pll0_config,
  90	.vco_table = lucid_evo_vco,
  91	.num_vco = ARRAY_SIZE(lucid_evo_vco),
  92	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  93	.clkr = {
  94		.hw.init = &(const struct clk_init_data) {
  95			.name = "cam_cc_pll0",
  96			.parent_data = &pll_parent_data_tcxo,
  97			.num_parents = 1,
  98			.ops = &clk_alpha_pll_lucid_evo_ops,
  99		},
 100	},
 101};
 102
 103static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
 104	{ 0x1, 2 },
 105	{ }
 106};
 107
 108static struct clk_init_data sm8475_cam_cc_pll0_out_even_init = {
 109	.name = "cam_cc_pll0_out_even",
 110	.parent_hws = (const struct clk_hw*[]) {
 111		&cam_cc_pll0.clkr.hw,
 112	},
 113	.num_parents = 1,
 114	.flags = CLK_SET_RATE_PARENT,
 115	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 116};
 117
 118static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
 119	.offset = 0x0,
 120	.post_div_shift = 10,
 121	.post_div_table = post_div_table_cam_cc_pll0_out_even,
 122	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
 123	.width = 4,
 124	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 125	.clkr.hw.init = &(const struct clk_init_data) {
 126		.name = "cam_cc_pll0_out_even",
 127		.parent_hws = (const struct clk_hw*[]) {
 128			&cam_cc_pll0.clkr.hw,
 129		},
 130		.num_parents = 1,
 131		.flags = CLK_SET_RATE_PARENT,
 132		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 133	},
 134};
 135
 136static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
 137	{ 0x2, 3 },
 138	{ }
 139};
 140
 141static struct clk_init_data sm8475_cam_cc_pll0_out_odd_init = {
 142	.name = "cam_cc_pll0_out_odd",
 143	.parent_hws = (const struct clk_hw*[]) {
 144		&cam_cc_pll0.clkr.hw,
 145	},
 146	.num_parents = 1,
 147	.flags = CLK_SET_RATE_PARENT,
 148	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 149};
 150
 151static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
 152	.offset = 0x0,
 153	.post_div_shift = 14,
 154	.post_div_table = post_div_table_cam_cc_pll0_out_odd,
 155	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
 156	.width = 4,
 157	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 158	.clkr.hw.init = &(const struct clk_init_data) {
 159		.name = "cam_cc_pll0_out_odd",
 160		.parent_hws = (const struct clk_hw*[]) {
 161			&cam_cc_pll0.clkr.hw,
 162		},
 163		.num_parents = 1,
 164		.flags = CLK_SET_RATE_PARENT,
 165		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 166	},
 167};
 168
 169static const struct alpha_pll_config cam_cc_pll1_config = {
 170	.l = 0x25,
 171	.alpha = 0xeaaa,
 172	.config_ctl_val = 0x20485699,
 173	.config_ctl_hi_val = 0x00182261,
 174	.config_ctl_hi1_val = 0x32aa299c,
 175	.user_ctl_val = 0x00000400,
 176	.user_ctl_hi_val = 0x00000805,
 177};
 178
 179static const struct alpha_pll_config sm8475_cam_cc_pll1_config = {
 180	.l = 0x25,
 181	.alpha = 0xeaaa,
 182	.config_ctl_val = 0x20485699,
 183	.config_ctl_hi_val = 0x00182261,
 184	.config_ctl_hi1_val = 0x82aa299c,
 185	.test_ctl_val = 0x00000000,
 186	.test_ctl_hi_val = 0x00000003,
 187	.test_ctl_hi1_val = 0x00009000,
 188	.test_ctl_hi2_val = 0x00000034,
 189	.user_ctl_val = 0x00000400,
 190	.user_ctl_hi_val = 0x00000005,
 191};
 192
 193static struct clk_alpha_pll cam_cc_pll1 = {
 194	.offset = 0x1000,
 195	.config = &cam_cc_pll1_config,
 196	.vco_table = lucid_evo_vco,
 197	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 198	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 199	.clkr = {
 200		.hw.init = &(const struct clk_init_data) {
 201			.name = "cam_cc_pll1",
 202			.parent_data = &pll_parent_data_tcxo,
 203			.num_parents = 1,
 204			.ops = &clk_alpha_pll_lucid_evo_ops,
 205		},
 206	},
 207};
 208
 209static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
 210	{ 0x1, 2 },
 211	{ }
 212};
 213
 214static struct clk_init_data sm8475_cam_cc_pll1_out_even_init = {
 215	.name = "cam_cc_pll1_out_even",
 216	.parent_hws = (const struct clk_hw*[]) {
 217		&cam_cc_pll1.clkr.hw,
 218	},
 219	.num_parents = 1,
 220	.flags = CLK_SET_RATE_PARENT,
 221	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 222};
 223
 224static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
 225	.offset = 0x1000,
 226	.post_div_shift = 10,
 227	.post_div_table = post_div_table_cam_cc_pll1_out_even,
 228	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
 229	.width = 4,
 230	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 231	.clkr.hw.init = &(const struct clk_init_data) {
 232		.name = "cam_cc_pll1_out_even",
 233		.parent_hws = (const struct clk_hw*[]) {
 234			&cam_cc_pll1.clkr.hw,
 235		},
 236		.num_parents = 1,
 237		.flags = CLK_SET_RATE_PARENT,
 238		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 239	},
 240};
 241
 242static const struct alpha_pll_config cam_cc_pll2_config = {
 243	.l = 0x32,
 244	.alpha = 0x0,
 245	.config_ctl_val = 0x90008820,
 246	.config_ctl_hi_val = 0x00890263,
 247	.config_ctl_hi1_val = 0x00000217,
 248};
 249
 250static const struct alpha_pll_config sm8475_cam_cc_pll2_config = {
 251	.l = 0x32,
 252	.alpha = 0x0,
 253	.config_ctl_val = 0x10000030,
 254	.config_ctl_hi_val = 0x80890263,
 255	.config_ctl_hi1_val = 0x00000217,
 256	.user_ctl_val = 0x00000001,
 257	.user_ctl_hi_val = 0x00000000,
 258};
 259
 260static struct clk_alpha_pll cam_cc_pll2 = {
 261	.offset = 0x2000,
 262	.config = &cam_cc_pll2_config,
 263	.vco_table = rivian_evo_vco,
 264	.num_vco = ARRAY_SIZE(rivian_evo_vco),
 265	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
 266	.clkr = {
 267		.hw.init = &(const struct clk_init_data) {
 268			.name = "cam_cc_pll2",
 269			.parent_data = &pll_parent_data_tcxo,
 270			.num_parents = 1,
 271			.ops = &clk_alpha_pll_rivian_evo_ops,
 272		},
 273	},
 274};
 275
 276static const struct alpha_pll_config cam_cc_pll3_config = {
 277	.l = 0x2d,
 278	.alpha = 0x0,
 279	.config_ctl_val = 0x20485699,
 280	.config_ctl_hi_val = 0x00182261,
 281	.config_ctl_hi1_val = 0x32aa299c,
 282	.user_ctl_val = 0x00000400,
 283	.user_ctl_hi_val = 0x00000805,
 284};
 285
 286static const struct alpha_pll_config sm8475_cam_cc_pll3_config = {
 287	.l = 0x2d,
 288	.alpha = 0x0,
 289	.config_ctl_val = 0x20485699,
 290	.config_ctl_hi_val = 0x00182261,
 291	.config_ctl_hi1_val = 0x82aa299c,
 292	.test_ctl_val = 0x00000000,
 293	.test_ctl_hi_val = 0x00000003,
 294	.test_ctl_hi1_val = 0x00009000,
 295	.test_ctl_hi2_val = 0x00000034,
 296	.user_ctl_val = 0x00000400,
 297	.user_ctl_hi_val = 0x00000005,
 298};
 299
 300static struct clk_alpha_pll cam_cc_pll3 = {
 301	.offset = 0x3000,
 302	.config = &cam_cc_pll3_config,
 303	.vco_table = lucid_evo_vco,
 304	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 305	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 306	.clkr = {
 307		.hw.init = &(const struct clk_init_data) {
 308			.name = "cam_cc_pll3",
 309			.parent_data = &pll_parent_data_tcxo,
 310			.num_parents = 1,
 311			.ops = &clk_alpha_pll_lucid_evo_ops,
 312		},
 313	},
 314};
 315
 316static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
 317	{ 0x1, 2 },
 318	{ }
 319};
 320
 321static struct clk_init_data sm8475_cam_cc_pll3_out_even_init = {
 322	.name = "cam_cc_pll3_out_even",
 323	.parent_hws = (const struct clk_hw*[]) {
 324		&cam_cc_pll3.clkr.hw,
 325	},
 326	.num_parents = 1,
 327	.flags = CLK_SET_RATE_PARENT,
 328	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 329};
 330
 331static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
 332	.offset = 0x3000,
 333	.post_div_shift = 10,
 334	.post_div_table = post_div_table_cam_cc_pll3_out_even,
 335	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
 336	.width = 4,
 337	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 338	.clkr.hw.init = &(const struct clk_init_data) {
 339		.name = "cam_cc_pll3_out_even",
 340		.parent_hws = (const struct clk_hw*[]) {
 341			&cam_cc_pll3.clkr.hw,
 342		},
 343		.num_parents = 1,
 344		.flags = CLK_SET_RATE_PARENT,
 345		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 346	},
 347};
 348
 349static const struct alpha_pll_config cam_cc_pll4_config = {
 350	.l = 0x2d,
 351	.alpha = 0x0,
 352	.config_ctl_val = 0x20485699,
 353	.config_ctl_hi_val = 0x00182261,
 354	.config_ctl_hi1_val = 0x32aa299c,
 355	.user_ctl_val = 0x00000400,
 356	.user_ctl_hi_val = 0x00000805,
 357};
 358
 359static const struct alpha_pll_config sm8475_cam_cc_pll4_config = {
 360	.l = 0x2d,
 361	.alpha = 0x0,
 362	.config_ctl_val = 0x20485699,
 363	.config_ctl_hi_val = 0x00182261,
 364	.config_ctl_hi1_val = 0x82aa299c,
 365	.test_ctl_val = 0x00000000,
 366	.test_ctl_hi_val = 0x00000003,
 367	.test_ctl_hi1_val = 0x00009000,
 368	.test_ctl_hi2_val = 0x00000034,
 369	.user_ctl_val = 0x00000400,
 370	.user_ctl_hi_val = 0x00000005,
 371};
 372
 373static struct clk_alpha_pll cam_cc_pll4 = {
 374	.offset = 0x4000,
 375	.config = &cam_cc_pll4_config,
 376	.vco_table = lucid_evo_vco,
 377	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 378	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 379	.clkr = {
 380		.hw.init = &(const struct clk_init_data) {
 381			.name = "cam_cc_pll4",
 382			.parent_data = &pll_parent_data_tcxo,
 383			.num_parents = 1,
 384			.ops = &clk_alpha_pll_lucid_evo_ops,
 385		},
 386	},
 387};
 388
 389static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
 390	{ 0x1, 2 },
 391	{ }
 392};
 393
 394static struct clk_init_data sm8475_cam_cc_pll4_out_even_init = {
 395	.name = "cam_cc_pll4_out_even",
 396	.parent_hws = (const struct clk_hw*[]) {
 397		&cam_cc_pll4.clkr.hw,
 398	},
 399	.num_parents = 1,
 400	.flags = CLK_SET_RATE_PARENT,
 401	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 402};
 403
 404static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
 405	.offset = 0x4000,
 406	.post_div_shift = 10,
 407	.post_div_table = post_div_table_cam_cc_pll4_out_even,
 408	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
 409	.width = 4,
 410	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 411	.clkr.hw.init = &(const struct clk_init_data) {
 412		.name = "cam_cc_pll4_out_even",
 413		.parent_hws = (const struct clk_hw*[]) {
 414			&cam_cc_pll4.clkr.hw,
 415		},
 416		.num_parents = 1,
 417		.flags = CLK_SET_RATE_PARENT,
 418		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 419	},
 420};
 421
 422static const struct alpha_pll_config cam_cc_pll5_config = {
 423	.l = 0x2d,
 424	.alpha = 0x0,
 425	.config_ctl_val = 0x20485699,
 426	.config_ctl_hi_val = 0x00182261,
 427	.config_ctl_hi1_val = 0x32aa299c,
 428	.user_ctl_val = 0x00000400,
 429	.user_ctl_hi_val = 0x00000805,
 430};
 431
 432static const struct alpha_pll_config sm8475_cam_cc_pll5_config = {
 433	.l = 0x2d,
 434	.alpha = 0x0,
 435	.config_ctl_val = 0x20485699,
 436	.config_ctl_hi_val = 0x00182261,
 437	.config_ctl_hi1_val = 0x82aa299c,
 438	.test_ctl_val = 0x00000000,
 439	.test_ctl_hi_val = 0x00000003,
 440	.test_ctl_hi1_val = 0x00009000,
 441	.test_ctl_hi2_val = 0x00000034,
 442	.user_ctl_val = 0x00000400,
 443	.user_ctl_hi_val = 0x00000005,
 444};
 445
 446static struct clk_alpha_pll cam_cc_pll5 = {
 447	.offset = 0x5000,
 448	.config = &cam_cc_pll5_config,
 449	.vco_table = lucid_evo_vco,
 450	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 451	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 452	.clkr = {
 453		.hw.init = &(const struct clk_init_data) {
 454			.name = "cam_cc_pll5",
 455			.parent_data = &pll_parent_data_tcxo,
 456			.num_parents = 1,
 457			.ops = &clk_alpha_pll_lucid_evo_ops,
 458		},
 459	},
 460};
 461
 462static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
 463	{ 0x1, 2 },
 464	{ }
 465};
 466
 467static struct clk_init_data sm8475_cam_cc_pll5_out_even_init = {
 468	.name = "cam_cc_pll5_out_even",
 469	.parent_hws = (const struct clk_hw*[]) {
 470		&cam_cc_pll5.clkr.hw,
 471	},
 472	.num_parents = 1,
 473	.flags = CLK_SET_RATE_PARENT,
 474	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 475};
 476
 477static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
 478	.offset = 0x5000,
 479	.post_div_shift = 10,
 480	.post_div_table = post_div_table_cam_cc_pll5_out_even,
 481	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
 482	.width = 4,
 483	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 484	.clkr.hw.init = &(const struct clk_init_data) {
 485		.name = "cam_cc_pll5_out_even",
 486		.parent_hws = (const struct clk_hw*[]) {
 487			&cam_cc_pll5.clkr.hw,
 488		},
 489		.num_parents = 1,
 490		.flags = CLK_SET_RATE_PARENT,
 491		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 492	},
 493};
 494
 495static const struct alpha_pll_config cam_cc_pll6_config = {
 496	.l = 0x2d,
 497	.alpha = 0x0,
 498	.config_ctl_val = 0x20485699,
 499	.config_ctl_hi_val = 0x00182261,
 500	.config_ctl_hi1_val = 0x32aa299c,
 501	.user_ctl_val = 0x00000400,
 502	.user_ctl_hi_val = 0x00000805,
 503};
 504
 505static const struct alpha_pll_config sm8475_cam_cc_pll6_config = {
 506	.l = 0x2d,
 507	.alpha = 0x0,
 508	.config_ctl_val = 0x20485699,
 509	.config_ctl_hi_val = 0x00182261,
 510	.config_ctl_hi1_val = 0x82aa299c,
 511	.test_ctl_val = 0x00000000,
 512	.test_ctl_hi_val = 0x00000003,
 513	.test_ctl_hi1_val = 0x00009000,
 514	.test_ctl_hi2_val = 0x00000034,
 515	.user_ctl_val = 0x00000400,
 516	.user_ctl_hi_val = 0x00000005,
 517};
 518
 519static struct clk_alpha_pll cam_cc_pll6 = {
 520	.offset = 0x6000,
 521	.config = &cam_cc_pll6_config,
 522	.vco_table = lucid_evo_vco,
 523	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 524	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 525	.clkr = {
 526		.hw.init = &(const struct clk_init_data) {
 527			.name = "cam_cc_pll6",
 528			.parent_data = &pll_parent_data_tcxo,
 529			.num_parents = 1,
 530			.ops = &clk_alpha_pll_lucid_evo_ops,
 531		},
 532	},
 533};
 534
 535static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
 536	{ 0x1, 2 },
 537	{ }
 538};
 539
 540static struct clk_init_data sm8475_cam_cc_pll6_out_even_init = {
 541	.name = "cam_cc_pll6_out_even",
 542	.parent_hws = (const struct clk_hw*[]) {
 543		&cam_cc_pll6.clkr.hw,
 544	},
 545	.num_parents = 1,
 546	.flags = CLK_SET_RATE_PARENT,
 547	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 548};
 549
 550static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
 551	.offset = 0x6000,
 552	.post_div_shift = 10,
 553	.post_div_table = post_div_table_cam_cc_pll6_out_even,
 554	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
 555	.width = 4,
 556	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 557	.clkr.hw.init = &(const struct clk_init_data) {
 558		.name = "cam_cc_pll6_out_even",
 559		.parent_hws = (const struct clk_hw*[]) {
 560			&cam_cc_pll6.clkr.hw,
 561		},
 562		.num_parents = 1,
 563		.flags = CLK_SET_RATE_PARENT,
 564		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 565	},
 566};
 567
 568static const struct alpha_pll_config cam_cc_pll7_config = {
 569	.l = 0x2d,
 570	.alpha = 0x0,
 571	.config_ctl_val = 0x20485699,
 572	.config_ctl_hi_val = 0x00182261,
 573	.config_ctl_hi1_val = 0x32aa299c,
 574	.user_ctl_val = 0x00000400,
 575	.user_ctl_hi_val = 0x00000805,
 576};
 577
 578static const struct alpha_pll_config sm8475_cam_cc_pll7_config = {
 579	.l = 0x2d,
 580	.alpha = 0x0,
 581	.config_ctl_val = 0x20485699,
 582	.config_ctl_hi_val = 0x00182261,
 583	.config_ctl_hi1_val = 0x82aa299c,
 584	.test_ctl_val = 0x00000000,
 585	.test_ctl_hi_val = 0x00000003,
 586	.test_ctl_hi1_val = 0x00009000,
 587	.test_ctl_hi2_val = 0x00000034,
 588	.user_ctl_val = 0x00000400,
 589	.user_ctl_hi_val = 0x00000005,
 590};
 591
 592static struct clk_alpha_pll cam_cc_pll7 = {
 593	.offset = 0x7000,
 594	.config = &cam_cc_pll7_config,
 595	.vco_table = lucid_evo_vco,
 596	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 597	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 598	.clkr = {
 599		.hw.init = &(const struct clk_init_data) {
 600			.name = "cam_cc_pll7",
 601			.parent_data = &pll_parent_data_tcxo,
 602			.num_parents = 1,
 603			.ops = &clk_alpha_pll_lucid_evo_ops,
 604		},
 605	},
 606};
 607
 608static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
 609	{ 0x1, 2 },
 610	{ }
 611};
 612
 613static struct clk_init_data sm8475_cam_cc_pll7_out_even_init = {
 614	.name = "cam_cc_pll7_out_even",
 615	.parent_hws = (const struct clk_hw*[]) {
 616		&cam_cc_pll7.clkr.hw,
 617	},
 618	.num_parents = 1,
 619	.flags = CLK_SET_RATE_PARENT,
 620	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 621};
 622
 623static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
 624	.offset = 0x7000,
 625	.post_div_shift = 10,
 626	.post_div_table = post_div_table_cam_cc_pll7_out_even,
 627	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even),
 628	.width = 4,
 629	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 630	.clkr.hw.init = &(const struct clk_init_data) {
 631		.name = "cam_cc_pll7_out_even",
 632		.parent_hws = (const struct clk_hw*[]) {
 633			&cam_cc_pll7.clkr.hw,
 634		},
 635		.num_parents = 1,
 636		.flags = CLK_SET_RATE_PARENT,
 637		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 638	},
 639};
 640
 641static const struct alpha_pll_config cam_cc_pll8_config = {
 642	.l = 0x32,
 643	.alpha = 0x0,
 644	.config_ctl_val = 0x20485699,
 645	.config_ctl_hi_val = 0x00182261,
 646	.config_ctl_hi1_val = 0x32aa299c,
 647	.user_ctl_val = 0x00000400,
 648	.user_ctl_hi_val = 0x00000805,
 649};
 650
 651static const struct alpha_pll_config sm8475_cam_cc_pll8_config = {
 652	.l = 0x32,
 653	.alpha = 0x0,
 654	.config_ctl_val = 0x20485699,
 655	.config_ctl_hi_val = 0x00182261,
 656	.config_ctl_hi1_val = 0x82aa299c,
 657	.test_ctl_val = 0x00000000,
 658	.test_ctl_hi_val = 0x00000003,
 659	.test_ctl_hi1_val = 0x00009000,
 660	.test_ctl_hi2_val = 0x00000034,
 661	.user_ctl_val = 0x00000400,
 662	.user_ctl_hi_val = 0x00000005,
 663};
 664
 665static struct clk_alpha_pll cam_cc_pll8 = {
 666	.offset = 0x8000,
 667	.config = &cam_cc_pll8_config,
 668	.vco_table = lucid_evo_vco,
 669	.num_vco = ARRAY_SIZE(lucid_evo_vco),
 670	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 671	.clkr = {
 672		.hw.init = &(const struct clk_init_data) {
 673			.name = "cam_cc_pll8",
 674			.parent_data = &pll_parent_data_tcxo,
 675			.num_parents = 1,
 676			.ops = &clk_alpha_pll_lucid_evo_ops,
 677		},
 678	},
 679};
 680
 681static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
 682	{ 0x1, 2 },
 683	{ }
 684};
 685
 686static struct clk_init_data sm8475_cam_cc_pll8_out_even_init = {
 687	.name = "cam_cc_pll8_out_even",
 688	.parent_hws = (const struct clk_hw*[]) {
 689		&cam_cc_pll8.clkr.hw,
 690	},
 691	.num_parents = 1,
 692	.flags = CLK_SET_RATE_PARENT,
 693	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
 694};
 695
 696static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
 697	.offset = 0x8000,
 698	.post_div_shift = 10,
 699	.post_div_table = post_div_table_cam_cc_pll8_out_even,
 700	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even),
 701	.width = 4,
 702	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 703	.clkr.hw.init = &(const struct clk_init_data) {
 704		.name = "cam_cc_pll8_out_even",
 705		.parent_hws = (const struct clk_hw*[]) {
 706			&cam_cc_pll8.clkr.hw,
 707		},
 708		.num_parents = 1,
 709		.flags = CLK_SET_RATE_PARENT,
 710		.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 711	},
 712};
 713
 714static const struct parent_map cam_cc_parent_map_0[] = {
 715	{ P_BI_TCXO, 0 },
 716	{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
 717	{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
 718	{ P_CAM_CC_PLL0_OUT_ODD, 3 },
 719	{ P_CAM_CC_PLL8_OUT_EVEN, 5 },
 720};
 721
 722static const struct clk_parent_data cam_cc_parent_data_0[] = {
 723	{ .index = DT_BI_TCXO },
 724	{ .hw = &cam_cc_pll0.clkr.hw },
 725	{ .hw = &cam_cc_pll0_out_even.clkr.hw },
 726	{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
 727	{ .hw = &cam_cc_pll8_out_even.clkr.hw },
 728};
 729
 730static const struct parent_map cam_cc_parent_map_1[] = {
 731	{ P_BI_TCXO, 0 },
 732	{ P_CAM_CC_PLL2_OUT_EVEN, 3 },
 733	{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
 734};
 735
 736static const struct clk_parent_data cam_cc_parent_data_1[] = {
 737	{ .index = DT_BI_TCXO },
 738	{ .hw = &cam_cc_pll2.clkr.hw },
 739	{ .hw = &cam_cc_pll2.clkr.hw },
 740};
 741
 742static const struct parent_map cam_cc_parent_map_2[] = {
 743	{ P_BI_TCXO, 0 },
 744	{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
 745};
 746
 747static const struct clk_parent_data cam_cc_parent_data_2[] = {
 748	{ .index = DT_BI_TCXO },
 749	{ .hw = &cam_cc_pll3_out_even.clkr.hw },
 750};
 751
 752static const struct parent_map cam_cc_parent_map_3[] = {
 753	{ P_BI_TCXO, 0 },
 754	{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
 755};
 756
 757static const struct clk_parent_data cam_cc_parent_data_3[] = {
 758	{ .index = DT_BI_TCXO },
 759	{ .hw = &cam_cc_pll4_out_even.clkr.hw },
 760};
 761
 762static const struct parent_map cam_cc_parent_map_4[] = {
 763	{ P_BI_TCXO, 0 },
 764	{ P_CAM_CC_PLL5_OUT_EVEN, 6 },
 765};
 766
 767static const struct clk_parent_data cam_cc_parent_data_4[] = {
 768	{ .index = DT_BI_TCXO },
 769	{ .hw = &cam_cc_pll5_out_even.clkr.hw },
 770};
 771
 772static const struct parent_map cam_cc_parent_map_5[] = {
 773	{ P_BI_TCXO, 0 },
 774	{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
 775};
 776
 777static const struct clk_parent_data cam_cc_parent_data_5[] = {
 778	{ .index = DT_BI_TCXO },
 779	{ .hw = &cam_cc_pll1_out_even.clkr.hw },
 780};
 781
 782static const struct parent_map cam_cc_parent_map_6[] = {
 783	{ P_BI_TCXO, 0 },
 784	{ P_CAM_CC_PLL6_OUT_EVEN, 6 },
 785};
 786
 787static const struct clk_parent_data cam_cc_parent_data_6[] = {
 788	{ .index = DT_BI_TCXO },
 789	{ .hw = &cam_cc_pll6_out_even.clkr.hw },
 790};
 791
 792static const struct parent_map cam_cc_parent_map_7[] = {
 793	{ P_BI_TCXO, 0 },
 794	{ P_CAM_CC_PLL7_OUT_EVEN, 6 },
 795};
 796
 797static const struct clk_parent_data cam_cc_parent_data_7[] = {
 798	{ .index = DT_BI_TCXO },
 799	{ .hw = &cam_cc_pll7_out_even.clkr.hw },
 800};
 801
 802static const struct parent_map cam_cc_parent_map_8[] = {
 803	{ P_SLEEP_CLK, 0 },
 804};
 805
 806static const struct clk_parent_data cam_cc_parent_data_8[] = {
 807	{ .index = DT_SLEEP_CLK },
 808};
 809
 810static const struct parent_map cam_cc_parent_map_9[] = {
 811	{ P_BI_TCXO, 0 },
 812};
 813
 814static const struct clk_parent_data cam_cc_parent_data_9_ao[] = {
 815	{ .index = DT_BI_TCXO_AO, .name = "bi_tcxo_ao" },
 816};
 817
 818static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
 819	F(19200000, P_BI_TCXO, 1, 0, 0),
 820	F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
 821	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 822	F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
 823	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
 824	{ }
 825};
 826
 827static struct clk_rcg2 cam_cc_bps_clk_src = {
 828	.cmd_rcgr = 0x10050,
 829	.mnd_width = 0,
 830	.hid_width = 5,
 831	.parent_map = cam_cc_parent_map_0,
 832	.freq_tbl = ftbl_cam_cc_bps_clk_src,
 833	.clkr.hw.init = &(const struct clk_init_data) {
 834		.name = "cam_cc_bps_clk_src",
 835		.parent_data = cam_cc_parent_data_0,
 836		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 837		.flags = CLK_SET_RATE_PARENT,
 838		.ops = &clk_rcg2_ops,
 839	},
 840};
 841
 842static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
 843	F(19200000, P_BI_TCXO, 1, 0, 0),
 844	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
 845	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 846	{ }
 847};
 848
 849static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
 850	.cmd_rcgr = 0x13194,
 851	.mnd_width = 0,
 852	.hid_width = 5,
 853	.parent_map = cam_cc_parent_map_0,
 854	.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
 855	.clkr.hw.init = &(const struct clk_init_data) {
 856		.name = "cam_cc_camnoc_axi_clk_src",
 857		.parent_data = cam_cc_parent_data_0,
 858		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 859		.flags = CLK_SET_RATE_PARENT,
 860		.ops = &clk_rcg2_ops,
 861	},
 862};
 863
 864static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
 865	F(19200000, P_BI_TCXO, 1, 0, 0),
 866	F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
 867	{ }
 868};
 869
 870static struct clk_rcg2 cam_cc_cci_0_clk_src = {
 871	.cmd_rcgr = 0x1312c,
 872	.mnd_width = 8,
 873	.hid_width = 5,
 874	.parent_map = cam_cc_parent_map_0,
 875	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 876	.clkr.hw.init = &(const struct clk_init_data) {
 877		.name = "cam_cc_cci_0_clk_src",
 878		.parent_data = cam_cc_parent_data_0,
 879		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 880		.flags = CLK_SET_RATE_PARENT,
 881		.ops = &clk_rcg2_ops,
 882	},
 883};
 884
 885static struct clk_rcg2 cam_cc_cci_1_clk_src = {
 886	.cmd_rcgr = 0x13148,
 887	.mnd_width = 8,
 888	.hid_width = 5,
 889	.parent_map = cam_cc_parent_map_0,
 890	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 891	.clkr.hw.init = &(const struct clk_init_data) {
 892		.name = "cam_cc_cci_1_clk_src",
 893		.parent_data = cam_cc_parent_data_0,
 894		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 895		.flags = CLK_SET_RATE_PARENT,
 896		.ops = &clk_rcg2_ops,
 897	},
 898};
 899
 900static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
 901	F(19200000, P_BI_TCXO, 1, 0, 0),
 902	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
 903	F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
 904	{ }
 905};
 906
 907static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
 908	.cmd_rcgr = 0x1104c,
 909	.mnd_width = 0,
 910	.hid_width = 5,
 911	.parent_map = cam_cc_parent_map_0,
 912	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
 913	.clkr.hw.init = &(const struct clk_init_data) {
 914		.name = "cam_cc_cphy_rx_clk_src",
 915		.parent_data = cam_cc_parent_data_0,
 916		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 917		.flags = CLK_SET_RATE_PARENT,
 918		.ops = &clk_rcg2_ops,
 919	},
 920};
 921
 922static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
 923	F(19200000, P_BI_TCXO, 1, 0, 0),
 924	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 925	{ }
 926};
 927
 928static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
 929	.cmd_rcgr = 0x150e0,
 930	.mnd_width = 0,
 931	.hid_width = 5,
 932	.parent_map = cam_cc_parent_map_0,
 933	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 934	.clkr.hw.init = &(const struct clk_init_data) {
 935		.name = "cam_cc_csi0phytimer_clk_src",
 936		.parent_data = cam_cc_parent_data_0,
 937		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 938		.flags = CLK_SET_RATE_PARENT,
 939		.ops = &clk_rcg2_ops,
 940	},
 941};
 942
 943static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
 944	.cmd_rcgr = 0x15104,
 945	.mnd_width = 0,
 946	.hid_width = 5,
 947	.parent_map = cam_cc_parent_map_0,
 948	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 949	.clkr.hw.init = &(const struct clk_init_data) {
 950		.name = "cam_cc_csi1phytimer_clk_src",
 951		.parent_data = cam_cc_parent_data_0,
 952		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 953		.flags = CLK_SET_RATE_PARENT,
 954		.ops = &clk_rcg2_ops,
 955	},
 956};
 957
 958static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
 959	.cmd_rcgr = 0x15124,
 960	.mnd_width = 0,
 961	.hid_width = 5,
 962	.parent_map = cam_cc_parent_map_0,
 963	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 964	.clkr.hw.init = &(const struct clk_init_data) {
 965		.name = "cam_cc_csi2phytimer_clk_src",
 966		.parent_data = cam_cc_parent_data_0,
 967		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 968		.flags = CLK_SET_RATE_PARENT,
 969		.ops = &clk_rcg2_ops,
 970	},
 971};
 972
 973static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
 974	.cmd_rcgr = 0x1514c,
 975	.mnd_width = 0,
 976	.hid_width = 5,
 977	.parent_map = cam_cc_parent_map_0,
 978	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 979	.clkr.hw.init = &(const struct clk_init_data) {
 980		.name = "cam_cc_csi3phytimer_clk_src",
 981		.parent_data = cam_cc_parent_data_0,
 982		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 983		.flags = CLK_SET_RATE_PARENT,
 984		.ops = &clk_rcg2_ops,
 985	},
 986};
 987
 988static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
 989	.cmd_rcgr = 0x1516c,
 990	.mnd_width = 0,
 991	.hid_width = 5,
 992	.parent_map = cam_cc_parent_map_0,
 993	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 994	.clkr.hw.init = &(const struct clk_init_data) {
 995		.name = "cam_cc_csi4phytimer_clk_src",
 996		.parent_data = cam_cc_parent_data_0,
 997		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 998		.flags = CLK_SET_RATE_PARENT,
 999		.ops = &clk_rcg2_ops,
1000	},
1001};
1002
1003static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
1004	.cmd_rcgr = 0x1518c,
1005	.mnd_width = 0,
1006	.hid_width = 5,
1007	.parent_map = cam_cc_parent_map_0,
1008	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1009	.clkr.hw.init = &(const struct clk_init_data) {
1010		.name = "cam_cc_csi5phytimer_clk_src",
1011		.parent_data = cam_cc_parent_data_0,
1012		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1013		.flags = CLK_SET_RATE_PARENT,
1014		.ops = &clk_rcg2_ops,
1015	},
1016};
1017
1018static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = {
1019	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1020	F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
1021	{ }
1022};
1023
1024static struct clk_rcg2 cam_cc_csid_clk_src = {
1025	.cmd_rcgr = 0x13174,
1026	.mnd_width = 0,
1027	.hid_width = 5,
1028	.parent_map = cam_cc_parent_map_0,
1029	.freq_tbl = ftbl_cam_cc_csid_clk_src,
1030	.clkr.hw.init = &(const struct clk_init_data) {
1031		.name = "cam_cc_csid_clk_src",
1032		.parent_data = cam_cc_parent_data_0,
1033		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1034		.flags = CLK_SET_RATE_PARENT,
1035		.ops = &clk_rcg2_ops,
1036	},
1037};
1038
1039static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
1040	F(19200000, P_BI_TCXO, 1, 0, 0),
1041	F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
1042	F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
1043	F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
1044	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1045	{ }
1046};
1047
1048static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
1049	.cmd_rcgr = 0x10018,
1050	.mnd_width = 0,
1051	.hid_width = 5,
1052	.parent_map = cam_cc_parent_map_0,
1053	.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
1054	.clkr.hw.init = &(const struct clk_init_data) {
1055		.name = "cam_cc_fast_ahb_clk_src",
1056		.parent_data = cam_cc_parent_data_0,
1057		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1058		.flags = CLK_SET_RATE_PARENT,
1059		.ops = &clk_rcg2_ops,
1060	},
1061};
1062
1063static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
1064	F(19200000, P_BI_TCXO, 1, 0, 0),
1065	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1066	F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
1067	F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
1068	{ }
1069};
1070
1071static struct clk_rcg2 cam_cc_icp_clk_src = {
1072	.cmd_rcgr = 0x13108,
1073	.mnd_width = 0,
1074	.hid_width = 5,
1075	.parent_map = cam_cc_parent_map_0,
1076	.freq_tbl = ftbl_cam_cc_icp_clk_src,
1077	.clkr.hw.init = &(const struct clk_init_data) {
1078		.name = "cam_cc_icp_clk_src",
1079		.parent_data = cam_cc_parent_data_0,
1080		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1081		.flags = CLK_SET_RATE_PARENT,
1082		.ops = &clk_rcg2_ops,
1083	},
1084};
1085
1086static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
1087	F(19200000, P_BI_TCXO, 1, 0, 0),
1088	F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1089	F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1090	F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1091	F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1092	{ }
1093};
1094
1095static struct clk_rcg2 cam_cc_ife_0_clk_src = {
1096	.cmd_rcgr = 0x11018,
1097	.mnd_width = 0,
1098	.hid_width = 5,
1099	.parent_map = cam_cc_parent_map_2,
1100	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
1101	.clkr.hw.init = &(const struct clk_init_data) {
1102		.name = "cam_cc_ife_0_clk_src",
1103		.parent_data = cam_cc_parent_data_2,
1104		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
1105		.flags = CLK_SET_RATE_PARENT,
1106		.ops = &clk_rcg2_ops,
1107	},
1108};
1109
1110static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
1111	F(19200000, P_BI_TCXO, 1, 0, 0),
1112	F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1113	F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1114	F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1115	F(727000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1116	{ }
1117};
1118
1119static struct clk_rcg2 cam_cc_ife_1_clk_src = {
1120	.cmd_rcgr = 0x12018,
1121	.mnd_width = 0,
1122	.hid_width = 5,
1123	.parent_map = cam_cc_parent_map_3,
1124	.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
1125	.clkr.hw.init = &(const struct clk_init_data) {
1126		.name = "cam_cc_ife_1_clk_src",
1127		.parent_data = cam_cc_parent_data_3,
1128		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
1129		.flags = CLK_SET_RATE_PARENT,
1130		.ops = &clk_rcg2_ops,
1131	},
1132};
1133
1134static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
1135	F(432000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1136	F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1137	F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1138	F(727000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1139	{ }
1140};
1141
1142static struct clk_rcg2 cam_cc_ife_2_clk_src = {
1143	.cmd_rcgr = 0x12064,
1144	.mnd_width = 0,
1145	.hid_width = 5,
1146	.parent_map = cam_cc_parent_map_4,
1147	.freq_tbl = ftbl_cam_cc_ife_2_clk_src,
1148	.clkr.hw.init = &(const struct clk_init_data) {
1149		.name = "cam_cc_ife_2_clk_src",
1150		.parent_data = cam_cc_parent_data_4,
1151		.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
1152		.flags = CLK_SET_RATE_PARENT,
1153		.ops = &clk_rcg2_ops,
1154	},
1155};
1156
1157static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = {
1158	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1159	F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
1160	{ }
1161};
1162
1163static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
1164	.cmd_rcgr = 0x13000,
1165	.mnd_width = 0,
1166	.hid_width = 5,
1167	.parent_map = cam_cc_parent_map_0,
1168	.freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
1169	.clkr.hw.init = &(const struct clk_init_data) {
1170		.name = "cam_cc_ife_lite_clk_src",
1171		.parent_data = cam_cc_parent_data_0,
1172		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1173		.flags = CLK_SET_RATE_PARENT,
1174		.ops = &clk_rcg2_ops,
1175	},
1176};
1177
1178static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
1179	.cmd_rcgr = 0x13024,
1180	.mnd_width = 0,
1181	.hid_width = 5,
1182	.parent_map = cam_cc_parent_map_0,
1183	.freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
1184	.clkr.hw.init = &(const struct clk_init_data) {
1185		.name = "cam_cc_ife_lite_csid_clk_src",
1186		.parent_data = cam_cc_parent_data_0,
1187		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1188		.flags = CLK_SET_RATE_PARENT,
1189		.ops = &clk_rcg2_ops,
1190	},
1191};
1192
1193static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = {
1194	F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1195	F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1196	F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1197	F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1198	{ }
1199};
1200
1201static struct clk_rcg2 cam_cc_ipe_nps_clk_src = {
1202	.cmd_rcgr = 0x1008c,
1203	.mnd_width = 0,
1204	.hid_width = 5,
1205	.parent_map = cam_cc_parent_map_5,
1206	.freq_tbl = ftbl_cam_cc_ipe_nps_clk_src,
1207	.clkr.hw.init = &(const struct clk_init_data) {
1208		.name = "cam_cc_ipe_nps_clk_src",
1209		.parent_data = cam_cc_parent_data_5,
1210		.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
1211		.flags = CLK_SET_RATE_PARENT,
1212		.ops = &clk_rcg2_ops,
1213	},
1214};
1215
1216static struct clk_rcg2 cam_cc_jpeg_clk_src = {
1217	.cmd_rcgr = 0x130dc,
1218	.mnd_width = 0,
1219	.hid_width = 5,
1220	.parent_map = cam_cc_parent_map_0,
1221	.freq_tbl = ftbl_cam_cc_bps_clk_src,
1222	.clkr.hw.init = &(const struct clk_init_data) {
1223		.name = "cam_cc_jpeg_clk_src",
1224		.parent_data = cam_cc_parent_data_0,
1225		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1226		.flags = CLK_SET_RATE_PARENT,
1227		.ops = &clk_rcg2_ops,
1228	},
1229};
1230
1231static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
1232	F(19200000, P_BI_TCXO, 1, 0, 0),
1233	F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4),
1234	F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0),
1235	{ }
1236};
1237
1238static struct clk_rcg2 cam_cc_mclk0_clk_src = {
1239	.cmd_rcgr = 0x15000,
1240	.mnd_width = 8,
1241	.hid_width = 5,
1242	.parent_map = cam_cc_parent_map_1,
1243	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1244	.clkr.hw.init = &(const struct clk_init_data) {
1245		.name = "cam_cc_mclk0_clk_src",
1246		.parent_data = cam_cc_parent_data_1,
1247		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1248		.flags = CLK_SET_RATE_PARENT,
1249		.ops = &clk_rcg2_ops,
1250	},
1251};
1252
1253static struct clk_rcg2 cam_cc_mclk1_clk_src = {
1254	.cmd_rcgr = 0x1501c,
1255	.mnd_width = 8,
1256	.hid_width = 5,
1257	.parent_map = cam_cc_parent_map_1,
1258	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1259	.clkr.hw.init = &(const struct clk_init_data) {
1260		.name = "cam_cc_mclk1_clk_src",
1261		.parent_data = cam_cc_parent_data_1,
1262		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1263		.flags = CLK_SET_RATE_PARENT,
1264		.ops = &clk_rcg2_ops,
1265	},
1266};
1267
1268static struct clk_rcg2 cam_cc_mclk2_clk_src = {
1269	.cmd_rcgr = 0x15038,
1270	.mnd_width = 8,
1271	.hid_width = 5,
1272	.parent_map = cam_cc_parent_map_1,
1273	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1274	.clkr.hw.init = &(const struct clk_init_data) {
1275		.name = "cam_cc_mclk2_clk_src",
1276		.parent_data = cam_cc_parent_data_1,
1277		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1278		.flags = CLK_SET_RATE_PARENT,
1279		.ops = &clk_rcg2_ops,
1280	},
1281};
1282
1283static struct clk_rcg2 cam_cc_mclk3_clk_src = {
1284	.cmd_rcgr = 0x15054,
1285	.mnd_width = 8,
1286	.hid_width = 5,
1287	.parent_map = cam_cc_parent_map_1,
1288	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1289	.clkr.hw.init = &(const struct clk_init_data) {
1290		.name = "cam_cc_mclk3_clk_src",
1291		.parent_data = cam_cc_parent_data_1,
1292		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1293		.flags = CLK_SET_RATE_PARENT,
1294		.ops = &clk_rcg2_ops,
1295	},
1296};
1297
1298static struct clk_rcg2 cam_cc_mclk4_clk_src = {
1299	.cmd_rcgr = 0x15070,
1300	.mnd_width = 8,
1301	.hid_width = 5,
1302	.parent_map = cam_cc_parent_map_1,
1303	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1304	.clkr.hw.init = &(const struct clk_init_data) {
1305		.name = "cam_cc_mclk4_clk_src",
1306		.parent_data = cam_cc_parent_data_1,
1307		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1308		.flags = CLK_SET_RATE_PARENT,
1309		.ops = &clk_rcg2_ops,
1310	},
1311};
1312
1313static struct clk_rcg2 cam_cc_mclk5_clk_src = {
1314	.cmd_rcgr = 0x1508c,
1315	.mnd_width = 8,
1316	.hid_width = 5,
1317	.parent_map = cam_cc_parent_map_1,
1318	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1319	.clkr.hw.init = &(const struct clk_init_data) {
1320		.name = "cam_cc_mclk5_clk_src",
1321		.parent_data = cam_cc_parent_data_1,
1322		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1323		.flags = CLK_SET_RATE_PARENT,
1324		.ops = &clk_rcg2_ops,
1325	},
1326};
1327
1328static struct clk_rcg2 cam_cc_mclk6_clk_src = {
1329	.cmd_rcgr = 0x150a8,
1330	.mnd_width = 8,
1331	.hid_width = 5,
1332	.parent_map = cam_cc_parent_map_1,
1333	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1334	.clkr.hw.init = &(const struct clk_init_data) {
1335		.name = "cam_cc_mclk6_clk_src",
1336		.parent_data = cam_cc_parent_data_1,
1337		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1338		.flags = CLK_SET_RATE_PARENT,
1339		.ops = &clk_rcg2_ops,
1340	},
1341};
1342
1343static struct clk_rcg2 cam_cc_mclk7_clk_src = {
1344	.cmd_rcgr = 0x150c4,
1345	.mnd_width = 8,
1346	.hid_width = 5,
1347	.parent_map = cam_cc_parent_map_1,
1348	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1349	.clkr.hw.init = &(const struct clk_init_data) {
1350		.name = "cam_cc_mclk7_clk_src",
1351		.parent_data = cam_cc_parent_data_1,
1352		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1353		.flags = CLK_SET_RATE_PARENT,
1354		.ops = &clk_rcg2_ops,
1355	},
1356};
1357
1358static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = {
1359	F(19200000, P_BI_TCXO, 1, 0, 0),
1360	F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
1361	F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
1362	F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
1363	{ }
1364};
1365
1366static struct clk_rcg2 cam_cc_qdss_debug_clk_src = {
1367	.cmd_rcgr = 0x131bc,
1368	.mnd_width = 0,
1369	.hid_width = 5,
1370	.parent_map = cam_cc_parent_map_0,
1371	.freq_tbl = ftbl_cam_cc_qdss_debug_clk_src,
1372	.clkr.hw.init = &(const struct clk_init_data) {
1373		.name = "cam_cc_qdss_debug_clk_src",
1374		.parent_data = cam_cc_parent_data_0,
1375		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1376		.flags = CLK_SET_RATE_PARENT,
1377		.ops = &clk_rcg2_ops,
1378	},
1379};
1380
1381static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
1382	F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1383	F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1384	F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1385	F(727000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1386	{ }
1387};
1388
1389static struct clk_rcg2 cam_cc_sfe_0_clk_src = {
1390	.cmd_rcgr = 0x13064,
1391	.mnd_width = 0,
1392	.hid_width = 5,
1393	.parent_map = cam_cc_parent_map_6,
1394	.freq_tbl = ftbl_cam_cc_sfe_0_clk_src,
1395	.clkr.hw.init = &(const struct clk_init_data) {
1396		.name = "cam_cc_sfe_0_clk_src",
1397		.parent_data = cam_cc_parent_data_6,
1398		.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
1399		.flags = CLK_SET_RATE_PARENT,
1400		.ops = &clk_rcg2_ops,
1401	},
1402};
1403
1404static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = {
1405	F(432000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1406	F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1407	F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1408	F(727000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1409	{ }
1410};
1411
1412static struct clk_rcg2 cam_cc_sfe_1_clk_src = {
1413	.cmd_rcgr = 0x130ac,
1414	.mnd_width = 0,
1415	.hid_width = 5,
1416	.parent_map = cam_cc_parent_map_7,
1417	.freq_tbl = ftbl_cam_cc_sfe_1_clk_src,
1418	.clkr.hw.init = &(const struct clk_init_data) {
1419		.name = "cam_cc_sfe_1_clk_src",
1420		.parent_data = cam_cc_parent_data_7,
1421		.num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
1422		.flags = CLK_SET_RATE_PARENT,
1423		.ops = &clk_rcg2_ops,
1424	},
1425};
1426
1427static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
1428	F(32000, P_SLEEP_CLK, 1, 0, 0),
1429	{ }
1430};
1431
1432static struct clk_rcg2 cam_cc_sleep_clk_src = {
1433	.cmd_rcgr = 0x13210,
1434	.mnd_width = 0,
1435	.hid_width = 5,
1436	.parent_map = cam_cc_parent_map_8,
1437	.freq_tbl = ftbl_cam_cc_sleep_clk_src,
1438	.clkr.hw.init = &(const struct clk_init_data) {
1439		.name = "cam_cc_sleep_clk_src",
1440		.parent_data = cam_cc_parent_data_8,
1441		.num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
1442		.flags = CLK_SET_RATE_PARENT,
1443		.ops = &clk_rcg2_ops,
1444	},
1445};
1446
1447static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
1448	F(19200000, P_BI_TCXO, 1, 0, 0),
1449	F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
1450	{ }
1451};
1452
1453static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
1454	.cmd_rcgr = 0x10034,
1455	.mnd_width = 8,
1456	.hid_width = 5,
1457	.parent_map = cam_cc_parent_map_0,
1458	.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
1459	.clkr.hw.init = &(const struct clk_init_data) {
1460		.name = "cam_cc_slow_ahb_clk_src",
1461		.parent_data = cam_cc_parent_data_0,
1462		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1463		.flags = CLK_SET_RATE_PARENT,
1464		.ops = &clk_rcg2_ops,
1465	},
1466};
1467
1468static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
1469	F(19200000, P_BI_TCXO, 1, 0, 0),
1470	{ }
1471};
1472
1473static struct clk_rcg2 cam_cc_xo_clk_src = {
1474	.cmd_rcgr = 0x131f4,
1475	.mnd_width = 0,
1476	.hid_width = 5,
1477	.parent_map = cam_cc_parent_map_9,
1478	.freq_tbl = ftbl_cam_cc_xo_clk_src,
1479	.clkr.hw.init = &(const struct clk_init_data) {
1480		.name = "cam_cc_xo_clk_src",
1481		.parent_data = cam_cc_parent_data_9_ao,
1482		.num_parents = ARRAY_SIZE(cam_cc_parent_data_9_ao),
1483		.flags = CLK_SET_RATE_PARENT,
1484		.ops = &clk_rcg2_ops,
1485	},
1486};
1487
1488static struct clk_branch cam_cc_bps_ahb_clk = {
1489	.halt_reg = 0x1004c,
1490	.halt_check = BRANCH_HALT,
1491	.clkr = {
1492		.enable_reg = 0x1004c,
1493		.enable_mask = BIT(0),
1494		.hw.init = &(const struct clk_init_data) {
1495			.name = "cam_cc_bps_ahb_clk",
1496			.parent_hws = (const struct clk_hw*[]) {
1497				&cam_cc_slow_ahb_clk_src.clkr.hw,
1498			},
1499			.num_parents = 1,
1500			.flags = CLK_SET_RATE_PARENT,
1501			.ops = &clk_branch2_ops,
1502		},
1503	},
1504};
1505
1506static struct clk_branch cam_cc_bps_clk = {
1507	.halt_reg = 0x10068,
1508	.halt_check = BRANCH_HALT,
1509	.clkr = {
1510		.enable_reg = 0x10068,
1511		.enable_mask = BIT(0),
1512		.hw.init = &(const struct clk_init_data) {
1513			.name = "cam_cc_bps_clk",
1514			.parent_hws = (const struct clk_hw*[]) {
1515				&cam_cc_bps_clk_src.clkr.hw,
1516			},
1517			.num_parents = 1,
1518			.flags = CLK_SET_RATE_PARENT,
1519			.ops = &clk_branch2_ops,
1520		},
1521	},
1522};
1523
1524static struct clk_branch cam_cc_bps_fast_ahb_clk = {
1525	.halt_reg = 0x10030,
1526	.halt_check = BRANCH_HALT,
1527	.clkr = {
1528		.enable_reg = 0x10030,
1529		.enable_mask = BIT(0),
1530		.hw.init = &(const struct clk_init_data) {
1531			.name = "cam_cc_bps_fast_ahb_clk",
1532			.parent_hws = (const struct clk_hw*[]) {
1533				&cam_cc_fast_ahb_clk_src.clkr.hw,
1534			},
1535			.num_parents = 1,
1536			.flags = CLK_SET_RATE_PARENT,
1537			.ops = &clk_branch2_ops,
1538		},
1539	},
1540};
1541
1542static struct clk_branch cam_cc_camnoc_axi_clk = {
1543	.halt_reg = 0x131ac,
1544	.halt_check = BRANCH_HALT,
1545	.clkr = {
1546		.enable_reg = 0x131ac,
1547		.enable_mask = BIT(0),
1548		.hw.init = &(const struct clk_init_data) {
1549			.name = "cam_cc_camnoc_axi_clk",
1550			.parent_hws = (const struct clk_hw*[]) {
1551				&cam_cc_camnoc_axi_clk_src.clkr.hw,
1552			},
1553			.num_parents = 1,
1554			.flags = CLK_SET_RATE_PARENT,
1555			.ops = &clk_branch2_ops,
1556		},
1557	},
1558};
1559
1560static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
1561	.halt_reg = 0x131b4,
1562	.halt_check = BRANCH_HALT,
1563	.clkr = {
1564		.enable_reg = 0x131b4,
1565		.enable_mask = BIT(0),
1566		.hw.init = &(const struct clk_init_data) {
1567			.name = "cam_cc_camnoc_dcd_xo_clk",
1568			.parent_hws = (const struct clk_hw*[]) {
1569				&cam_cc_xo_clk_src.clkr.hw,
1570			},
1571			.num_parents = 1,
1572			.flags = CLK_SET_RATE_PARENT,
1573			.ops = &clk_branch2_ops,
1574		},
1575	},
1576};
1577
1578static struct clk_branch cam_cc_cci_0_clk = {
1579	.halt_reg = 0x13144,
1580	.halt_check = BRANCH_HALT,
1581	.clkr = {
1582		.enable_reg = 0x13144,
1583		.enable_mask = BIT(0),
1584		.hw.init = &(const struct clk_init_data) {
1585			.name = "cam_cc_cci_0_clk",
1586			.parent_hws = (const struct clk_hw*[]) {
1587				&cam_cc_cci_0_clk_src.clkr.hw,
1588			},
1589			.num_parents = 1,
1590			.flags = CLK_SET_RATE_PARENT,
1591			.ops = &clk_branch2_ops,
1592		},
1593	},
1594};
1595
1596static struct clk_branch cam_cc_cci_1_clk = {
1597	.halt_reg = 0x13160,
1598	.halt_check = BRANCH_HALT,
1599	.clkr = {
1600		.enable_reg = 0x13160,
1601		.enable_mask = BIT(0),
1602		.hw.init = &(const struct clk_init_data) {
1603			.name = "cam_cc_cci_1_clk",
1604			.parent_hws = (const struct clk_hw*[]) {
1605				&cam_cc_cci_1_clk_src.clkr.hw,
1606			},
1607			.num_parents = 1,
1608			.flags = CLK_SET_RATE_PARENT,
1609			.ops = &clk_branch2_ops,
1610		},
1611	},
1612};
1613
1614static struct clk_branch cam_cc_core_ahb_clk = {
1615	.halt_reg = 0x131f0,
1616	.halt_check = BRANCH_HALT_DELAY,
1617	.clkr = {
1618		.enable_reg = 0x131f0,
1619		.enable_mask = BIT(0),
1620		.hw.init = &(const struct clk_init_data) {
1621			.name = "cam_cc_core_ahb_clk",
1622			.parent_hws = (const struct clk_hw*[]) {
1623				&cam_cc_slow_ahb_clk_src.clkr.hw,
1624			},
1625			.num_parents = 1,
1626			.flags = CLK_SET_RATE_PARENT,
1627			.ops = &clk_branch2_ops,
1628		},
1629	},
1630};
1631
1632static struct clk_branch cam_cc_cpas_ahb_clk = {
1633	.halt_reg = 0x13164,
1634	.halt_check = BRANCH_HALT,
1635	.clkr = {
1636		.enable_reg = 0x13164,
1637		.enable_mask = BIT(0),
1638		.hw.init = &(const struct clk_init_data) {
1639			.name = "cam_cc_cpas_ahb_clk",
1640			.parent_hws = (const struct clk_hw*[]) {
1641				&cam_cc_slow_ahb_clk_src.clkr.hw,
1642			},
1643			.num_parents = 1,
1644			.flags = CLK_SET_RATE_PARENT,
1645			.ops = &clk_branch2_ops,
1646		},
1647	},
1648};
1649
1650static struct clk_branch cam_cc_cpas_bps_clk = {
1651	.halt_reg = 0x10070,
1652	.halt_check = BRANCH_HALT,
1653	.clkr = {
1654		.enable_reg = 0x10070,
1655		.enable_mask = BIT(0),
1656		.hw.init = &(const struct clk_init_data) {
1657			.name = "cam_cc_cpas_bps_clk",
1658			.parent_hws = (const struct clk_hw*[]) {
1659				&cam_cc_bps_clk_src.clkr.hw,
1660			},
1661			.num_parents = 1,
1662			.flags = CLK_SET_RATE_PARENT,
1663			.ops = &clk_branch2_ops,
1664		},
1665	},
1666};
1667
1668static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
1669	.halt_reg = 0x1316c,
1670	.halt_check = BRANCH_HALT,
1671	.clkr = {
1672		.enable_reg = 0x1316c,
1673		.enable_mask = BIT(0),
1674		.hw.init = &(const struct clk_init_data) {
1675			.name = "cam_cc_cpas_fast_ahb_clk",
1676			.parent_hws = (const struct clk_hw*[]) {
1677				&cam_cc_fast_ahb_clk_src.clkr.hw,
1678			},
1679			.num_parents = 1,
1680			.flags = CLK_SET_RATE_PARENT,
1681			.ops = &clk_branch2_ops,
1682		},
1683	},
1684};
1685
1686static struct clk_branch cam_cc_cpas_ife_0_clk = {
1687	.halt_reg = 0x11038,
1688	.halt_check = BRANCH_HALT,
1689	.clkr = {
1690		.enable_reg = 0x11038,
1691		.enable_mask = BIT(0),
1692		.hw.init = &(const struct clk_init_data) {
1693			.name = "cam_cc_cpas_ife_0_clk",
1694			.parent_hws = (const struct clk_hw*[]) {
1695				&cam_cc_ife_0_clk_src.clkr.hw,
1696			},
1697			.num_parents = 1,
1698			.flags = CLK_SET_RATE_PARENT,
1699			.ops = &clk_branch2_ops,
1700		},
1701	},
1702};
1703
1704static struct clk_branch cam_cc_cpas_ife_1_clk = {
1705	.halt_reg = 0x12038,
1706	.halt_check = BRANCH_HALT,
1707	.clkr = {
1708		.enable_reg = 0x12038,
1709		.enable_mask = BIT(0),
1710		.hw.init = &(const struct clk_init_data) {
1711			.name = "cam_cc_cpas_ife_1_clk",
1712			.parent_hws = (const struct clk_hw*[]) {
1713				&cam_cc_ife_1_clk_src.clkr.hw,
1714			},
1715			.num_parents = 1,
1716			.flags = CLK_SET_RATE_PARENT,
1717			.ops = &clk_branch2_ops,
1718		},
1719	},
1720};
1721
1722static struct clk_branch cam_cc_cpas_ife_2_clk = {
1723	.halt_reg = 0x12084,
1724	.halt_check = BRANCH_HALT,
1725	.clkr = {
1726		.enable_reg = 0x12084,
1727		.enable_mask = BIT(0),
1728		.hw.init = &(const struct clk_init_data) {
1729			.name = "cam_cc_cpas_ife_2_clk",
1730			.parent_hws = (const struct clk_hw*[]) {
1731				&cam_cc_ife_2_clk_src.clkr.hw,
1732			},
1733			.num_parents = 1,
1734			.flags = CLK_SET_RATE_PARENT,
1735			.ops = &clk_branch2_ops,
1736		},
1737	},
1738};
1739
1740static struct clk_branch cam_cc_cpas_ife_lite_clk = {
1741	.halt_reg = 0x13020,
1742	.halt_check = BRANCH_HALT,
1743	.clkr = {
1744		.enable_reg = 0x13020,
1745		.enable_mask = BIT(0),
1746		.hw.init = &(const struct clk_init_data) {
1747			.name = "cam_cc_cpas_ife_lite_clk",
1748			.parent_hws = (const struct clk_hw*[]) {
1749				&cam_cc_ife_lite_clk_src.clkr.hw,
1750			},
1751			.num_parents = 1,
1752			.flags = CLK_SET_RATE_PARENT,
1753			.ops = &clk_branch2_ops,
1754		},
1755	},
1756};
1757
1758static struct clk_branch cam_cc_cpas_ipe_nps_clk = {
1759	.halt_reg = 0x100ac,
1760	.halt_check = BRANCH_HALT,
1761	.clkr = {
1762		.enable_reg = 0x100ac,
1763		.enable_mask = BIT(0),
1764		.hw.init = &(const struct clk_init_data) {
1765			.name = "cam_cc_cpas_ipe_nps_clk",
1766			.parent_hws = (const struct clk_hw*[]) {
1767				&cam_cc_ipe_nps_clk_src.clkr.hw,
1768			},
1769			.num_parents = 1,
1770			.flags = CLK_SET_RATE_PARENT,
1771			.ops = &clk_branch2_ops,
1772		},
1773	},
1774};
1775
1776static struct clk_branch cam_cc_cpas_sbi_clk = {
1777	.halt_reg = 0x100ec,
1778	.halt_check = BRANCH_HALT,
1779	.clkr = {
1780		.enable_reg = 0x100ec,
1781		.enable_mask = BIT(0),
1782		.hw.init = &(const struct clk_init_data) {
1783			.name = "cam_cc_cpas_sbi_clk",
1784			.parent_hws = (const struct clk_hw*[]) {
1785				&cam_cc_ife_0_clk_src.clkr.hw,
1786			},
1787			.num_parents = 1,
1788			.flags = CLK_SET_RATE_PARENT,
1789			.ops = &clk_branch2_ops,
1790		},
1791	},
1792};
1793
1794static struct clk_branch cam_cc_cpas_sfe_0_clk = {
1795	.halt_reg = 0x13084,
1796	.halt_check = BRANCH_HALT,
1797	.clkr = {
1798		.enable_reg = 0x13084,
1799		.enable_mask = BIT(0),
1800		.hw.init = &(const struct clk_init_data) {
1801			.name = "cam_cc_cpas_sfe_0_clk",
1802			.parent_hws = (const struct clk_hw*[]) {
1803				&cam_cc_sfe_0_clk_src.clkr.hw,
1804			},
1805			.num_parents = 1,
1806			.flags = CLK_SET_RATE_PARENT,
1807			.ops = &clk_branch2_ops,
1808		},
1809	},
1810};
1811
1812static struct clk_branch cam_cc_cpas_sfe_1_clk = {
1813	.halt_reg = 0x130cc,
1814	.halt_check = BRANCH_HALT,
1815	.clkr = {
1816		.enable_reg = 0x130cc,
1817		.enable_mask = BIT(0),
1818		.hw.init = &(const struct clk_init_data) {
1819			.name = "cam_cc_cpas_sfe_1_clk",
1820			.parent_hws = (const struct clk_hw*[]) {
1821				&cam_cc_sfe_1_clk_src.clkr.hw,
1822			},
1823			.num_parents = 1,
1824			.flags = CLK_SET_RATE_PARENT,
1825			.ops = &clk_branch2_ops,
1826		},
1827	},
1828};
1829
1830static struct clk_branch cam_cc_csi0phytimer_clk = {
1831	.halt_reg = 0x150f8,
1832	.halt_check = BRANCH_HALT,
1833	.clkr = {
1834		.enable_reg = 0x150f8,
1835		.enable_mask = BIT(0),
1836		.hw.init = &(const struct clk_init_data) {
1837			.name = "cam_cc_csi0phytimer_clk",
1838			.parent_hws = (const struct clk_hw*[]) {
1839				&cam_cc_csi0phytimer_clk_src.clkr.hw,
1840			},
1841			.num_parents = 1,
1842			.flags = CLK_SET_RATE_PARENT,
1843			.ops = &clk_branch2_ops,
1844		},
1845	},
1846};
1847
1848static struct clk_branch cam_cc_csi1phytimer_clk = {
1849	.halt_reg = 0x1511c,
1850	.halt_check = BRANCH_HALT,
1851	.clkr = {
1852		.enable_reg = 0x1511c,
1853		.enable_mask = BIT(0),
1854		.hw.init = &(const struct clk_init_data) {
1855			.name = "cam_cc_csi1phytimer_clk",
1856			.parent_hws = (const struct clk_hw*[]) {
1857				&cam_cc_csi1phytimer_clk_src.clkr.hw,
1858			},
1859			.num_parents = 1,
1860			.flags = CLK_SET_RATE_PARENT,
1861			.ops = &clk_branch2_ops,
1862		},
1863	},
1864};
1865
1866static struct clk_branch cam_cc_csi2phytimer_clk = {
1867	.halt_reg = 0x1513c,
1868	.halt_check = BRANCH_HALT,
1869	.clkr = {
1870		.enable_reg = 0x1513c,
1871		.enable_mask = BIT(0),
1872		.hw.init = &(const struct clk_init_data) {
1873			.name = "cam_cc_csi2phytimer_clk",
1874			.parent_hws = (const struct clk_hw*[]) {
1875				&cam_cc_csi2phytimer_clk_src.clkr.hw,
1876			},
1877			.num_parents = 1,
1878			.flags = CLK_SET_RATE_PARENT,
1879			.ops = &clk_branch2_ops,
1880		},
1881	},
1882};
1883
1884static struct clk_branch cam_cc_csi3phytimer_clk = {
1885	.halt_reg = 0x15164,
1886	.halt_check = BRANCH_HALT,
1887	.clkr = {
1888		.enable_reg = 0x15164,
1889		.enable_mask = BIT(0),
1890		.hw.init = &(const struct clk_init_data) {
1891			.name = "cam_cc_csi3phytimer_clk",
1892			.parent_hws = (const struct clk_hw*[]) {
1893				&cam_cc_csi3phytimer_clk_src.clkr.hw,
1894			},
1895			.num_parents = 1,
1896			.flags = CLK_SET_RATE_PARENT,
1897			.ops = &clk_branch2_ops,
1898		},
1899	},
1900};
1901
1902static struct clk_branch cam_cc_csi4phytimer_clk = {
1903	.halt_reg = 0x15184,
1904	.halt_check = BRANCH_HALT,
1905	.clkr = {
1906		.enable_reg = 0x15184,
1907		.enable_mask = BIT(0),
1908		.hw.init = &(const struct clk_init_data) {
1909			.name = "cam_cc_csi4phytimer_clk",
1910			.parent_hws = (const struct clk_hw*[]) {
1911				&cam_cc_csi4phytimer_clk_src.clkr.hw,
1912			},
1913			.num_parents = 1,
1914			.flags = CLK_SET_RATE_PARENT,
1915			.ops = &clk_branch2_ops,
1916		},
1917	},
1918};
1919
1920static struct clk_branch cam_cc_csi5phytimer_clk = {
1921	.halt_reg = 0x151a4,
1922	.halt_check = BRANCH_HALT,
1923	.clkr = {
1924		.enable_reg = 0x151a4,
1925		.enable_mask = BIT(0),
1926		.hw.init = &(const struct clk_init_data) {
1927			.name = "cam_cc_csi5phytimer_clk",
1928			.parent_hws = (const struct clk_hw*[]) {
1929				&cam_cc_csi5phytimer_clk_src.clkr.hw,
1930			},
1931			.num_parents = 1,
1932			.flags = CLK_SET_RATE_PARENT,
1933			.ops = &clk_branch2_ops,
1934		},
1935	},
1936};
1937
1938static struct clk_branch cam_cc_csid_clk = {
1939	.halt_reg = 0x1318c,
1940	.halt_check = BRANCH_HALT,
1941	.clkr = {
1942		.enable_reg = 0x1318c,
1943		.enable_mask = BIT(0),
1944		.hw.init = &(const struct clk_init_data) {
1945			.name = "cam_cc_csid_clk",
1946			.parent_hws = (const struct clk_hw*[]) {
1947				&cam_cc_csid_clk_src.clkr.hw,
1948			},
1949			.num_parents = 1,
1950			.flags = CLK_SET_RATE_PARENT,
1951			.ops = &clk_branch2_ops,
1952		},
1953	},
1954};
1955
1956static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
1957	.halt_reg = 0x15100,
1958	.halt_check = BRANCH_HALT,
1959	.clkr = {
1960		.enable_reg = 0x15100,
1961		.enable_mask = BIT(0),
1962		.hw.init = &(const struct clk_init_data) {
1963			.name = "cam_cc_csid_csiphy_rx_clk",
1964			.parent_hws = (const struct clk_hw*[]) {
1965				&cam_cc_cphy_rx_clk_src.clkr.hw,
1966			},
1967			.num_parents = 1,
1968			.flags = CLK_SET_RATE_PARENT,
1969			.ops = &clk_branch2_ops,
1970		},
1971	},
1972};
1973
1974static struct clk_branch cam_cc_csiphy0_clk = {
1975	.halt_reg = 0x150fc,
1976	.halt_check = BRANCH_HALT,
1977	.clkr = {
1978		.enable_reg = 0x150fc,
1979		.enable_mask = BIT(0),
1980		.hw.init = &(const struct clk_init_data) {
1981			.name = "cam_cc_csiphy0_clk",
1982			.parent_hws = (const struct clk_hw*[]) {
1983				&cam_cc_cphy_rx_clk_src.clkr.hw,
1984			},
1985			.num_parents = 1,
1986			.flags = CLK_SET_RATE_PARENT,
1987			.ops = &clk_branch2_ops,
1988		},
1989	},
1990};
1991
1992static struct clk_branch cam_cc_csiphy1_clk = {
1993	.halt_reg = 0x15120,
1994	.halt_check = BRANCH_HALT,
1995	.clkr = {
1996		.enable_reg = 0x15120,
1997		.enable_mask = BIT(0),
1998		.hw.init = &(const struct clk_init_data) {
1999			.name = "cam_cc_csiphy1_clk",
2000			.parent_hws = (const struct clk_hw*[]) {
2001				&cam_cc_cphy_rx_clk_src.clkr.hw,
2002			},
2003			.num_parents = 1,
2004			.flags = CLK_SET_RATE_PARENT,
2005			.ops = &clk_branch2_ops,
2006		},
2007	},
2008};
2009
2010static struct clk_branch cam_cc_csiphy2_clk = {
2011	.halt_reg = 0x15140,
2012	.halt_check = BRANCH_HALT,
2013	.clkr = {
2014		.enable_reg = 0x15140,
2015		.enable_mask = BIT(0),
2016		.hw.init = &(const struct clk_init_data) {
2017			.name = "cam_cc_csiphy2_clk",
2018			.parent_hws = (const struct clk_hw*[]) {
2019				&cam_cc_cphy_rx_clk_src.clkr.hw,
2020			},
2021			.num_parents = 1,
2022			.flags = CLK_SET_RATE_PARENT,
2023			.ops = &clk_branch2_ops,
2024		},
2025	},
2026};
2027
2028static struct clk_branch cam_cc_csiphy3_clk = {
2029	.halt_reg = 0x15168,
2030	.halt_check = BRANCH_HALT,
2031	.clkr = {
2032		.enable_reg = 0x15168,
2033		.enable_mask = BIT(0),
2034		.hw.init = &(const struct clk_init_data) {
2035			.name = "cam_cc_csiphy3_clk",
2036			.parent_hws = (const struct clk_hw*[]) {
2037				&cam_cc_cphy_rx_clk_src.clkr.hw,
2038			},
2039			.num_parents = 1,
2040			.flags = CLK_SET_RATE_PARENT,
2041			.ops = &clk_branch2_ops,
2042		},
2043	},
2044};
2045
2046static struct clk_branch cam_cc_csiphy4_clk = {
2047	.halt_reg = 0x15188,
2048	.halt_check = BRANCH_HALT,
2049	.clkr = {
2050		.enable_reg = 0x15188,
2051		.enable_mask = BIT(0),
2052		.hw.init = &(const struct clk_init_data) {
2053			.name = "cam_cc_csiphy4_clk",
2054			.parent_hws = (const struct clk_hw*[]) {
2055				&cam_cc_cphy_rx_clk_src.clkr.hw,
2056			},
2057			.num_parents = 1,
2058			.flags = CLK_SET_RATE_PARENT,
2059			.ops = &clk_branch2_ops,
2060		},
2061	},
2062};
2063
2064static struct clk_branch cam_cc_csiphy5_clk = {
2065	.halt_reg = 0x151a8,
2066	.halt_check = BRANCH_HALT,
2067	.clkr = {
2068		.enable_reg = 0x151a8,
2069		.enable_mask = BIT(0),
2070		.hw.init = &(const struct clk_init_data) {
2071			.name = "cam_cc_csiphy5_clk",
2072			.parent_hws = (const struct clk_hw*[]) {
2073				&cam_cc_cphy_rx_clk_src.clkr.hw,
2074			},
2075			.num_parents = 1,
2076			.flags = CLK_SET_RATE_PARENT,
2077			.ops = &clk_branch2_ops,
2078		},
2079	},
2080};
2081
2082static struct clk_branch cam_cc_icp_ahb_clk = {
2083	.halt_reg = 0x13128,
2084	.halt_check = BRANCH_HALT,
2085	.clkr = {
2086		.enable_reg = 0x13128,
2087		.enable_mask = BIT(0),
2088		.hw.init = &(const struct clk_init_data) {
2089			.name = "cam_cc_icp_ahb_clk",
2090			.parent_hws = (const struct clk_hw*[]) {
2091				&cam_cc_slow_ahb_clk_src.clkr.hw,
2092			},
2093			.num_parents = 1,
2094			.flags = CLK_SET_RATE_PARENT,
2095			.ops = &clk_branch2_ops,
2096		},
2097	},
2098};
2099
2100static struct clk_branch cam_cc_icp_clk = {
2101	.halt_reg = 0x13120,
2102	.halt_check = BRANCH_HALT,
2103	.clkr = {
2104		.enable_reg = 0x13120,
2105		.enable_mask = BIT(0),
2106		.hw.init = &(const struct clk_init_data) {
2107			.name = "cam_cc_icp_clk",
2108			.parent_hws = (const struct clk_hw*[]) {
2109				&cam_cc_icp_clk_src.clkr.hw,
2110			},
2111			.num_parents = 1,
2112			.flags = CLK_SET_RATE_PARENT,
2113			.ops = &clk_branch2_ops,
2114		},
2115	},
2116};
2117
2118static struct clk_branch cam_cc_ife_0_clk = {
2119	.halt_reg = 0x11030,
2120	.halt_check = BRANCH_HALT,
2121	.clkr = {
2122		.enable_reg = 0x11030,
2123		.enable_mask = BIT(0),
2124		.hw.init = &(const struct clk_init_data) {
2125			.name = "cam_cc_ife_0_clk",
2126			.parent_hws = (const struct clk_hw*[]) {
2127				&cam_cc_ife_0_clk_src.clkr.hw,
2128			},
2129			.num_parents = 1,
2130			.flags = CLK_SET_RATE_PARENT,
2131			.ops = &clk_branch2_ops,
2132		},
2133	},
2134};
2135
2136static struct clk_branch cam_cc_ife_0_dsp_clk = {
2137	.halt_reg = 0x1103c,
2138	.halt_check = BRANCH_HALT,
2139	.clkr = {
2140		.enable_reg = 0x1103c,
2141		.enable_mask = BIT(0),
2142		.hw.init = &(const struct clk_init_data) {
2143			.name = "cam_cc_ife_0_dsp_clk",
2144			.parent_hws = (const struct clk_hw*[]) {
2145				&cam_cc_ife_0_clk_src.clkr.hw,
2146			},
2147			.num_parents = 1,
2148			.flags = CLK_SET_RATE_PARENT,
2149			.ops = &clk_branch2_ops,
2150		},
2151	},
2152};
2153
2154static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
2155	.halt_reg = 0x11048,
2156	.halt_check = BRANCH_HALT,
2157	.clkr = {
2158		.enable_reg = 0x11048,
2159		.enable_mask = BIT(0),
2160		.hw.init = &(const struct clk_init_data) {
2161			.name = "cam_cc_ife_0_fast_ahb_clk",
2162			.parent_hws = (const struct clk_hw*[]) {
2163				&cam_cc_fast_ahb_clk_src.clkr.hw,
2164			},
2165			.num_parents = 1,
2166			.flags = CLK_SET_RATE_PARENT,
2167			.ops = &clk_branch2_ops,
2168		},
2169	},
2170};
2171
2172static struct clk_branch cam_cc_ife_1_clk = {
2173	.halt_reg = 0x12030,
2174	.halt_check = BRANCH_HALT,
2175	.clkr = {
2176		.enable_reg = 0x12030,
2177		.enable_mask = BIT(0),
2178		.hw.init = &(const struct clk_init_data) {
2179			.name = "cam_cc_ife_1_clk",
2180			.parent_hws = (const struct clk_hw*[]) {
2181				&cam_cc_ife_1_clk_src.clkr.hw,
2182			},
2183			.num_parents = 1,
2184			.flags = CLK_SET_RATE_PARENT,
2185			.ops = &clk_branch2_ops,
2186		},
2187	},
2188};
2189
2190static struct clk_branch cam_cc_ife_1_dsp_clk = {
2191	.halt_reg = 0x1203c,
2192	.halt_check = BRANCH_HALT,
2193	.clkr = {
2194		.enable_reg = 0x1203c,
2195		.enable_mask = BIT(0),
2196		.hw.init = &(const struct clk_init_data) {
2197			.name = "cam_cc_ife_1_dsp_clk",
2198			.parent_hws = (const struct clk_hw*[]) {
2199				&cam_cc_ife_1_clk_src.clkr.hw,
2200			},
2201			.num_parents = 1,
2202			.flags = CLK_SET_RATE_PARENT,
2203			.ops = &clk_branch2_ops,
2204		},
2205	},
2206};
2207
2208static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
2209	.halt_reg = 0x12048,
2210	.halt_check = BRANCH_HALT,
2211	.clkr = {
2212		.enable_reg = 0x12048,
2213		.enable_mask = BIT(0),
2214		.hw.init = &(const struct clk_init_data) {
2215			.name = "cam_cc_ife_1_fast_ahb_clk",
2216			.parent_hws = (const struct clk_hw*[]) {
2217				&cam_cc_fast_ahb_clk_src.clkr.hw,
2218			},
2219			.num_parents = 1,
2220			.flags = CLK_SET_RATE_PARENT,
2221			.ops = &clk_branch2_ops,
2222		},
2223	},
2224};
2225
2226static struct clk_branch cam_cc_ife_2_clk = {
2227	.halt_reg = 0x1207c,
2228	.halt_check = BRANCH_HALT,
2229	.clkr = {
2230		.enable_reg = 0x1207c,
2231		.enable_mask = BIT(0),
2232		.hw.init = &(const struct clk_init_data) {
2233			.name = "cam_cc_ife_2_clk",
2234			.parent_hws = (const struct clk_hw*[]) {
2235				&cam_cc_ife_2_clk_src.clkr.hw,
2236			},
2237			.num_parents = 1,
2238			.flags = CLK_SET_RATE_PARENT,
2239			.ops = &clk_branch2_ops,
2240		},
2241	},
2242};
2243
2244static struct clk_branch cam_cc_ife_2_dsp_clk = {
2245	.halt_reg = 0x12088,
2246	.halt_check = BRANCH_HALT,
2247	.clkr = {
2248		.enable_reg = 0x12088,
2249		.enable_mask = BIT(0),
2250		.hw.init = &(const struct clk_init_data) {
2251			.name = "cam_cc_ife_2_dsp_clk",
2252			.parent_hws = (const struct clk_hw*[]) {
2253				&cam_cc_ife_2_clk_src.clkr.hw,
2254			},
2255			.num_parents = 1,
2256			.flags = CLK_SET_RATE_PARENT,
2257			.ops = &clk_branch2_ops,
2258		},
2259	},
2260};
2261
2262static struct clk_branch cam_cc_ife_2_fast_ahb_clk = {
2263	.halt_reg = 0x12094,
2264	.halt_check = BRANCH_HALT,
2265	.clkr = {
2266		.enable_reg = 0x12094,
2267		.enable_mask = BIT(0),
2268		.hw.init = &(const struct clk_init_data) {
2269			.name = "cam_cc_ife_2_fast_ahb_clk",
2270			.parent_hws = (const struct clk_hw*[]) {
2271				&cam_cc_fast_ahb_clk_src.clkr.hw,
2272			},
2273			.num_parents = 1,
2274			.flags = CLK_SET_RATE_PARENT,
2275			.ops = &clk_branch2_ops,
2276		},
2277	},
2278};
2279
2280static struct clk_branch cam_cc_ife_lite_ahb_clk = {
2281	.halt_reg = 0x13048,
2282	.halt_check = BRANCH_HALT,
2283	.clkr = {
2284		.enable_reg = 0x13048,
2285		.enable_mask = BIT(0),
2286		.hw.init = &(const struct clk_init_data) {
2287			.name = "cam_cc_ife_lite_ahb_clk",
2288			.parent_hws = (const struct clk_hw*[]) {
2289				&cam_cc_slow_ahb_clk_src.clkr.hw,
2290			},
2291			.num_parents = 1,
2292			.flags = CLK_SET_RATE_PARENT,
2293			.ops = &clk_branch2_ops,
2294		},
2295	},
2296};
2297
2298static struct clk_branch cam_cc_ife_lite_clk = {
2299	.halt_reg = 0x13018,
2300	.halt_check = BRANCH_HALT,
2301	.clkr = {
2302		.enable_reg = 0x13018,
2303		.enable_mask = BIT(0),
2304		.hw.init = &(const struct clk_init_data) {
2305			.name = "cam_cc_ife_lite_clk",
2306			.parent_hws = (const struct clk_hw*[]) {
2307				&cam_cc_ife_lite_clk_src.clkr.hw,
2308			},
2309			.num_parents = 1,
2310			.flags = CLK_SET_RATE_PARENT,
2311			.ops = &clk_branch2_ops,
2312		},
2313	},
2314};
2315
2316static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
2317	.halt_reg = 0x13044,
2318	.halt_check = BRANCH_HALT,
2319	.clkr = {
2320		.enable_reg = 0x13044,
2321		.enable_mask = BIT(0),
2322		.hw.init = &(const struct clk_init_data) {
2323			.name = "cam_cc_ife_lite_cphy_rx_clk",
2324			.parent_hws = (const struct clk_hw*[]) {
2325				&cam_cc_cphy_rx_clk_src.clkr.hw,
2326			},
2327			.num_parents = 1,
2328			.flags = CLK_SET_RATE_PARENT,
2329			.ops = &clk_branch2_ops,
2330		},
2331	},
2332};
2333
2334static struct clk_branch cam_cc_ife_lite_csid_clk = {
2335	.halt_reg = 0x1303c,
2336	.halt_check = BRANCH_HALT,
2337	.clkr = {
2338		.enable_reg = 0x1303c,
2339		.enable_mask = BIT(0),
2340		.hw.init = &(const struct clk_init_data) {
2341			.name = "cam_cc_ife_lite_csid_clk",
2342			.parent_hws = (const struct clk_hw*[]) {
2343				&cam_cc_ife_lite_csid_clk_src.clkr.hw,
2344			},
2345			.num_parents = 1,
2346			.flags = CLK_SET_RATE_PARENT,
2347			.ops = &clk_branch2_ops,
2348		},
2349	},
2350};
2351
2352static struct clk_branch cam_cc_ipe_nps_ahb_clk = {
2353	.halt_reg = 0x100c0,
2354	.halt_check = BRANCH_HALT,
2355	.clkr = {
2356		.enable_reg = 0x100c0,
2357		.enable_mask = BIT(0),
2358		.hw.init = &(const struct clk_init_data) {
2359			.name = "cam_cc_ipe_nps_ahb_clk",
2360			.parent_hws = (const struct clk_hw*[]) {
2361				&cam_cc_slow_ahb_clk_src.clkr.hw,
2362			},
2363			.num_parents = 1,
2364			.flags = CLK_SET_RATE_PARENT,
2365			.ops = &clk_branch2_ops,
2366		},
2367	},
2368};
2369
2370static struct clk_branch cam_cc_ipe_nps_clk = {
2371	.halt_reg = 0x100a4,
2372	.halt_check = BRANCH_HALT,
2373	.clkr = {
2374		.enable_reg = 0x100a4,
2375		.enable_mask = BIT(0),
2376		.hw.init = &(const struct clk_init_data) {
2377			.name = "cam_cc_ipe_nps_clk",
2378			.parent_hws = (const struct clk_hw*[]) {
2379				&cam_cc_ipe_nps_clk_src.clkr.hw,
2380			},
2381			.num_parents = 1,
2382			.flags = CLK_SET_RATE_PARENT,
2383			.ops = &clk_branch2_ops,
2384		},
2385	},
2386};
2387
2388static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = {
2389	.halt_reg = 0x100c4,
2390	.halt_check = BRANCH_HALT,
2391	.clkr = {
2392		.enable_reg = 0x100c4,
2393		.enable_mask = BIT(0),
2394		.hw.init = &(const struct clk_init_data) {
2395			.name = "cam_cc_ipe_nps_fast_ahb_clk",
2396			.parent_hws = (const struct clk_hw*[]) {
2397				&cam_cc_fast_ahb_clk_src.clkr.hw,
2398			},
2399			.num_parents = 1,
2400			.flags = CLK_SET_RATE_PARENT,
2401			.ops = &clk_branch2_ops,
2402		},
2403	},
2404};
2405
2406static struct clk_branch cam_cc_ipe_pps_clk = {
2407	.halt_reg = 0x100b0,
2408	.halt_check = BRANCH_HALT,
2409	.clkr = {
2410		.enable_reg = 0x100b0,
2411		.enable_mask = BIT(0),
2412		.hw.init = &(const struct clk_init_data) {
2413			.name = "cam_cc_ipe_pps_clk",
2414			.parent_hws = (const struct clk_hw*[]) {
2415				&cam_cc_ipe_nps_clk_src.clkr.hw,
2416			},
2417			.num_parents = 1,
2418			.flags = CLK_SET_RATE_PARENT,
2419			.ops = &clk_branch2_ops,
2420		},
2421	},
2422};
2423
2424static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = {
2425	.halt_reg = 0x100c8,
2426	.halt_check = BRANCH_HALT,
2427	.clkr = {
2428		.enable_reg = 0x100c8,
2429		.enable_mask = BIT(0),
2430		.hw.init = &(const struct clk_init_data) {
2431			.name = "cam_cc_ipe_pps_fast_ahb_clk",
2432			.parent_hws = (const struct clk_hw*[]) {
2433				&cam_cc_fast_ahb_clk_src.clkr.hw,
2434			},
2435			.num_parents = 1,
2436			.flags = CLK_SET_RATE_PARENT,
2437			.ops = &clk_branch2_ops,
2438		},
2439	},
2440};
2441
2442static struct clk_branch cam_cc_jpeg_clk = {
2443	.halt_reg = 0x130f4,
2444	.halt_check = BRANCH_HALT,
2445	.clkr = {
2446		.enable_reg = 0x130f4,
2447		.enable_mask = BIT(0),
2448		.hw.init = &(const struct clk_init_data) {
2449			.name = "cam_cc_jpeg_clk",
2450			.parent_hws = (const struct clk_hw*[]) {
2451				&cam_cc_jpeg_clk_src.clkr.hw,
2452			},
2453			.num_parents = 1,
2454			.flags = CLK_SET_RATE_PARENT,
2455			.ops = &clk_branch2_ops,
2456		},
2457	},
2458};
2459
2460static struct clk_branch cam_cc_mclk0_clk = {
2461	.halt_reg = 0x15018,
2462	.halt_check = BRANCH_HALT,
2463	.clkr = {
2464		.enable_reg = 0x15018,
2465		.enable_mask = BIT(0),
2466		.hw.init = &(const struct clk_init_data) {
2467			.name = "cam_cc_mclk0_clk",
2468			.parent_hws = (const struct clk_hw*[]) {
2469				&cam_cc_mclk0_clk_src.clkr.hw,
2470			},
2471			.num_parents = 1,
2472			.flags = CLK_SET_RATE_PARENT,
2473			.ops = &clk_branch2_ops,
2474		},
2475	},
2476};
2477
2478static struct clk_branch cam_cc_mclk1_clk = {
2479	.halt_reg = 0x15034,
2480	.halt_check = BRANCH_HALT,
2481	.clkr = {
2482		.enable_reg = 0x15034,
2483		.enable_mask = BIT(0),
2484		.hw.init = &(const struct clk_init_data) {
2485			.name = "cam_cc_mclk1_clk",
2486			.parent_hws = (const struct clk_hw*[]) {
2487				&cam_cc_mclk1_clk_src.clkr.hw,
2488			},
2489			.num_parents = 1,
2490			.flags = CLK_SET_RATE_PARENT,
2491			.ops = &clk_branch2_ops,
2492		},
2493	},
2494};
2495
2496static struct clk_branch cam_cc_mclk2_clk = {
2497	.halt_reg = 0x15050,
2498	.halt_check = BRANCH_HALT,
2499	.clkr = {
2500		.enable_reg = 0x15050,
2501		.enable_mask = BIT(0),
2502		.hw.init = &(const struct clk_init_data) {
2503			.name = "cam_cc_mclk2_clk",
2504			.parent_hws = (const struct clk_hw*[]) {
2505				&cam_cc_mclk2_clk_src.clkr.hw,
2506			},
2507			.num_parents = 1,
2508			.flags = CLK_SET_RATE_PARENT,
2509			.ops = &clk_branch2_ops,
2510		},
2511	},
2512};
2513
2514static struct clk_branch cam_cc_mclk3_clk = {
2515	.halt_reg = 0x1506c,
2516	.halt_check = BRANCH_HALT,
2517	.clkr = {
2518		.enable_reg = 0x1506c,
2519		.enable_mask = BIT(0),
2520		.hw.init = &(const struct clk_init_data) {
2521			.name = "cam_cc_mclk3_clk",
2522			.parent_hws = (const struct clk_hw*[]) {
2523				&cam_cc_mclk3_clk_src.clkr.hw,
2524			},
2525			.num_parents = 1,
2526			.flags = CLK_SET_RATE_PARENT,
2527			.ops = &clk_branch2_ops,
2528		},
2529	},
2530};
2531
2532static struct clk_branch cam_cc_mclk4_clk = {
2533	.halt_reg = 0x15088,
2534	.halt_check = BRANCH_HALT,
2535	.clkr = {
2536		.enable_reg = 0x15088,
2537		.enable_mask = BIT(0),
2538		.hw.init = &(const struct clk_init_data) {
2539			.name = "cam_cc_mclk4_clk",
2540			.parent_hws = (const struct clk_hw*[]) {
2541				&cam_cc_mclk4_clk_src.clkr.hw,
2542			},
2543			.num_parents = 1,
2544			.flags = CLK_SET_RATE_PARENT,
2545			.ops = &clk_branch2_ops,
2546		},
2547	},
2548};
2549
2550static struct clk_branch cam_cc_mclk5_clk = {
2551	.halt_reg = 0x150a4,
2552	.halt_check = BRANCH_HALT,
2553	.clkr = {
2554		.enable_reg = 0x150a4,
2555		.enable_mask = BIT(0),
2556		.hw.init = &(const struct clk_init_data) {
2557			.name = "cam_cc_mclk5_clk",
2558			.parent_hws = (const struct clk_hw*[]) {
2559				&cam_cc_mclk5_clk_src.clkr.hw,
2560			},
2561			.num_parents = 1,
2562			.flags = CLK_SET_RATE_PARENT,
2563			.ops = &clk_branch2_ops,
2564		},
2565	},
2566};
2567
2568static struct clk_branch cam_cc_mclk6_clk = {
2569	.halt_reg = 0x150c0,
2570	.halt_check = BRANCH_HALT,
2571	.clkr = {
2572		.enable_reg = 0x150c0,
2573		.enable_mask = BIT(0),
2574		.hw.init = &(const struct clk_init_data) {
2575			.name = "cam_cc_mclk6_clk",
2576			.parent_hws = (const struct clk_hw*[]) {
2577				&cam_cc_mclk6_clk_src.clkr.hw,
2578			},
2579			.num_parents = 1,
2580			.flags = CLK_SET_RATE_PARENT,
2581			.ops = &clk_branch2_ops,
2582		},
2583	},
2584};
2585
2586static struct clk_branch cam_cc_mclk7_clk = {
2587	.halt_reg = 0x150dc,
2588	.halt_check = BRANCH_HALT,
2589	.clkr = {
2590		.enable_reg = 0x150dc,
2591		.enable_mask = BIT(0),
2592		.hw.init = &(const struct clk_init_data) {
2593			.name = "cam_cc_mclk7_clk",
2594			.parent_hws = (const struct clk_hw*[]) {
2595				&cam_cc_mclk7_clk_src.clkr.hw,
2596			},
2597			.num_parents = 1,
2598			.flags = CLK_SET_RATE_PARENT,
2599			.ops = &clk_branch2_ops,
2600		},
2601	},
2602};
2603
2604static struct clk_branch cam_cc_qdss_debug_clk = {
2605	.halt_reg = 0x131d4,
2606	.halt_check = BRANCH_HALT,
2607	.clkr = {
2608		.enable_reg = 0x131d4,
2609		.enable_mask = BIT(0),
2610		.hw.init = &(const struct clk_init_data) {
2611			.name = "cam_cc_qdss_debug_clk",
2612			.parent_hws = (const struct clk_hw*[]) {
2613				&cam_cc_qdss_debug_clk_src.clkr.hw,
2614			},
2615			.num_parents = 1,
2616			.flags = CLK_SET_RATE_PARENT,
2617			.ops = &clk_branch2_ops,
2618		},
2619	},
2620};
2621
2622static struct clk_branch cam_cc_qdss_debug_xo_clk = {
2623	.halt_reg = 0x131d8,
2624	.halt_check = BRANCH_HALT,
2625	.clkr = {
2626		.enable_reg = 0x131d8,
2627		.enable_mask = BIT(0),
2628		.hw.init = &(const struct clk_init_data) {
2629			.name = "cam_cc_qdss_debug_xo_clk",
2630			.parent_hws = (const struct clk_hw*[]) {
2631				&cam_cc_xo_clk_src.clkr.hw,
2632			},
2633			.num_parents = 1,
2634			.flags = CLK_SET_RATE_PARENT,
2635			.ops = &clk_branch2_ops,
2636		},
2637	},
2638};
2639
2640static struct clk_branch cam_cc_sbi_ahb_clk = {
2641	.halt_reg = 0x100f0,
2642	.halt_check = BRANCH_HALT,
2643	.clkr = {
2644		.enable_reg = 0x100f0,
2645		.enable_mask = BIT(0),
2646		.hw.init = &(const struct clk_init_data) {
2647			.name = "cam_cc_sbi_ahb_clk",
2648			.parent_hws = (const struct clk_hw*[]) {
2649				&cam_cc_slow_ahb_clk_src.clkr.hw,
2650			},
2651			.num_parents = 1,
2652			.flags = CLK_SET_RATE_PARENT,
2653			.ops = &clk_branch2_ops,
2654		},
2655	},
2656};
2657
2658static struct clk_branch cam_cc_sbi_clk = {
2659	.halt_reg = 0x100e4,
2660	.halt_check = BRANCH_HALT,
2661	.clkr = {
2662		.enable_reg = 0x100e4,
2663		.enable_mask = BIT(0),
2664		.hw.init = &(const struct clk_init_data) {
2665			.name = "cam_cc_sbi_clk",
2666			.parent_hws = (const struct clk_hw*[]) {
2667				&cam_cc_ife_0_clk_src.clkr.hw,
2668			},
2669			.num_parents = 1,
2670			.flags = CLK_SET_RATE_PARENT,
2671			.ops = &clk_branch2_ops,
2672		},
2673	},
2674};
2675
2676static struct clk_branch cam_cc_sfe_0_clk = {
2677	.halt_reg = 0x1307c,
2678	.halt_check = BRANCH_HALT,
2679	.clkr = {
2680		.enable_reg = 0x1307c,
2681		.enable_mask = BIT(0),
2682		.hw.init = &(const struct clk_init_data) {
2683			.name = "cam_cc_sfe_0_clk",
2684			.parent_hws = (const struct clk_hw*[]) {
2685				&cam_cc_sfe_0_clk_src.clkr.hw,
2686			},
2687			.num_parents = 1,
2688			.flags = CLK_SET_RATE_PARENT,
2689			.ops = &clk_branch2_ops,
2690		},
2691	},
2692};
2693
2694static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = {
2695	.halt_reg = 0x13090,
2696	.halt_check = BRANCH_HALT,
2697	.clkr = {
2698		.enable_reg = 0x13090,
2699		.enable_mask = BIT(0),
2700		.hw.init = &(const struct clk_init_data) {
2701			.name = "cam_cc_sfe_0_fast_ahb_clk",
2702			.parent_hws = (const struct clk_hw*[]) {
2703				&cam_cc_fast_ahb_clk_src.clkr.hw,
2704			},
2705			.num_parents = 1,
2706			.flags = CLK_SET_RATE_PARENT,
2707			.ops = &clk_branch2_ops,
2708		},
2709	},
2710};
2711
2712static struct clk_branch cam_cc_sfe_1_clk = {
2713	.halt_reg = 0x130c4,
2714	.halt_check = BRANCH_HALT,
2715	.clkr = {
2716		.enable_reg = 0x130c4,
2717		.enable_mask = BIT(0),
2718		.hw.init = &(const struct clk_init_data) {
2719			.name = "cam_cc_sfe_1_clk",
2720			.parent_hws = (const struct clk_hw*[]) {
2721				&cam_cc_sfe_1_clk_src.clkr.hw,
2722			},
2723			.num_parents = 1,
2724			.flags = CLK_SET_RATE_PARENT,
2725			.ops = &clk_branch2_ops,
2726		},
2727	},
2728};
2729
2730static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
2731	.halt_reg = 0x130d8,
2732	.halt_check = BRANCH_HALT,
2733	.clkr = {
2734		.enable_reg = 0x130d8,
2735		.enable_mask = BIT(0),
2736		.hw.init = &(const struct clk_init_data) {
2737			.name = "cam_cc_sfe_1_fast_ahb_clk",
2738			.parent_hws = (const struct clk_hw*[]) {
2739				&cam_cc_fast_ahb_clk_src.clkr.hw,
2740			},
2741			.num_parents = 1,
2742			.flags = CLK_SET_RATE_PARENT,
2743			.ops = &clk_branch2_ops,
2744		},
2745	},
2746};
2747
2748static struct clk_branch cam_cc_sleep_clk = {
2749	.halt_reg = 0x13228,
2750	.halt_check = BRANCH_HALT,
2751	.clkr = {
2752		.enable_reg = 0x13228,
2753		.enable_mask = BIT(0),
2754		.hw.init = &(const struct clk_init_data) {
2755			.name = "cam_cc_sleep_clk",
2756			.parent_hws = (const struct clk_hw*[]) {
2757				&cam_cc_sleep_clk_src.clkr.hw,
2758			},
2759			.num_parents = 1,
2760			.flags = CLK_SET_RATE_PARENT,
2761			.ops = &clk_branch2_ops,
2762		},
2763	},
2764};
2765
2766static struct clk_regmap *cam_cc_sm8450_clocks[] = {
2767	[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
2768	[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
2769	[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
2770	[CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr,
2771	[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
2772	[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
2773	[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
2774	[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
2775	[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
2776	[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
2777	[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
2778	[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
2779	[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
2780	[CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr,
2781	[CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
2782	[CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
2783	[CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
2784	[CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr,
2785	[CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
2786	[CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr,
2787	[CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr,
2788	[CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr,
2789	[CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr,
2790	[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
2791	[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
2792	[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
2793	[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
2794	[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
2795	[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
2796	[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
2797	[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
2798	[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
2799	[CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
2800	[CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
2801	[CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
2802	[CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
2803	[CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
2804	[CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
2805	[CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
2806	[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
2807	[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
2808	[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
2809	[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
2810	[CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
2811	[CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
2812	[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
2813	[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
2814	[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
2815	[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
2816	[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
2817	[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
2818	[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
2819	[CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
2820	[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
2821	[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
2822	[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
2823	[CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
2824	[CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
2825	[CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
2826	[CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr,
2827	[CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr,
2828	[CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
2829	[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
2830	[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
2831	[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
2832	[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
2833	[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
2834	[CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr,
2835	[CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr,
2836	[CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr,
2837	[CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr,
2838	[CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr,
2839	[CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr,
2840	[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
2841	[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
2842	[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
2843	[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
2844	[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
2845	[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
2846	[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
2847	[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
2848	[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
2849	[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
2850	[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
2851	[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
2852	[CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
2853	[CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
2854	[CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
2855	[CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
2856	[CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr,
2857	[CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr,
2858	[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
2859	[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
2860	[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
2861	[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
2862	[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
2863	[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
2864	[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
2865	[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
2866	[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
2867	[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
2868	[CAM_CC_PLL5] = &cam_cc_pll5.clkr,
2869	[CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
2870	[CAM_CC_PLL6] = &cam_cc_pll6.clkr,
2871	[CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
2872	[CAM_CC_PLL7] = &cam_cc_pll7.clkr,
2873	[CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr,
2874	[CAM_CC_PLL8] = &cam_cc_pll8.clkr,
2875	[CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr,
2876	[CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr,
2877	[CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr,
2878	[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
2879	[CAM_CC_SBI_AHB_CLK] = &cam_cc_sbi_ahb_clk.clkr,
2880	[CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
2881	[CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
2882	[CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr,
2883	[CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr,
2884	[CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr,
2885	[CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr,
2886	[CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr,
2887	[CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,
2888	[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
2889	[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
2890	[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
2891};
2892
2893static const struct qcom_reset_map cam_cc_sm8450_resets[] = {
2894	[CAM_CC_BPS_BCR] = { 0x10000 },
2895	[CAM_CC_ICP_BCR] = { 0x13104 },
2896	[CAM_CC_IFE_0_BCR] = { 0x11000 },
2897	[CAM_CC_IFE_1_BCR] = { 0x12000 },
2898	[CAM_CC_IFE_2_BCR] = { 0x1204c },
2899	[CAM_CC_IPE_0_BCR] = { 0x10074 },
2900	[CAM_CC_QDSS_DEBUG_BCR] = { 0x131b8 },
2901	[CAM_CC_SBI_BCR] = { 0x100cc },
2902	[CAM_CC_SFE_0_BCR] = { 0x1304c },
2903	[CAM_CC_SFE_1_BCR] = { 0x13094 },
2904};
2905
2906static struct clk_alpha_pll *cam_cc_sm8450_plls[] = {
2907	&cam_cc_pll0,
2908	&cam_cc_pll1,
2909	&cam_cc_pll2,
2910	&cam_cc_pll3,
2911	&cam_cc_pll4,
2912	&cam_cc_pll5,
2913	&cam_cc_pll6,
2914	&cam_cc_pll7,
2915	&cam_cc_pll8,
2916};
2917
2918static u32 cam_cc_sm8450_critical_cbcrs[] = {
2919	0x1320c, /* CAM_CC_GDSC_CLK */
2920};
2921
2922static const struct regmap_config cam_cc_sm8450_regmap_config = {
2923	.reg_bits = 32,
2924	.reg_stride = 4,
2925	.val_bits = 32,
2926	.max_register = 0x1601c,
2927	.fast_io = true,
2928};
2929
2930static struct gdsc titan_top_gdsc;
2931
2932static struct gdsc bps_gdsc = {
2933	.gdscr = 0x10004,
2934	.pd = {
2935		.name = "bps_gdsc",
2936	},
2937	.flags = HW_CTRL | POLL_CFG_GDSCR,
2938	.parent = &titan_top_gdsc.pd,
2939	.pwrsts = PWRSTS_OFF_ON,
2940};
2941
2942static struct gdsc ipe_0_gdsc = {
2943	.gdscr = 0x10078,
2944	.pd = {
2945		.name = "ipe_0_gdsc",
2946	},
2947	.flags = HW_CTRL | POLL_CFG_GDSCR,
2948	.parent = &titan_top_gdsc.pd,
2949	.pwrsts = PWRSTS_OFF_ON,
2950};
2951
2952static struct gdsc sbi_gdsc = {
2953	.gdscr = 0x100d0,
2954	.pd = {
2955		.name = "sbi_gdsc",
2956	},
2957	.flags = POLL_CFG_GDSCR,
2958	.parent = &titan_top_gdsc.pd,
2959	.pwrsts = PWRSTS_OFF_ON,
2960};
2961
2962static struct gdsc ife_0_gdsc = {
2963	.gdscr = 0x11004,
2964	.pd = {
2965		.name = "ife_0_gdsc",
2966	},
2967	.flags = POLL_CFG_GDSCR,
2968	.parent = &titan_top_gdsc.pd,
2969	.pwrsts = PWRSTS_OFF_ON,
2970};
2971
2972static struct gdsc ife_1_gdsc = {
2973	.gdscr = 0x12004,
2974	.pd = {
2975		.name = "ife_1_gdsc",
2976	},
2977	.flags = POLL_CFG_GDSCR,
2978	.parent = &titan_top_gdsc.pd,
2979	.pwrsts = PWRSTS_OFF_ON,
2980};
2981
2982static struct gdsc ife_2_gdsc = {
2983	.gdscr = 0x12050,
2984	.pd = {
2985		.name = "ife_2_gdsc",
2986	},
2987	.flags = POLL_CFG_GDSCR,
2988	.parent = &titan_top_gdsc.pd,
2989	.pwrsts = PWRSTS_OFF_ON,
2990};
2991
2992static struct gdsc sfe_0_gdsc = {
2993	.gdscr = 0x13050,
2994	.pd = {
2995		.name = "sfe_0_gdsc",
2996	},
2997	.flags = POLL_CFG_GDSCR,
2998	.parent = &titan_top_gdsc.pd,
2999	.pwrsts = PWRSTS_OFF_ON,
3000};
3001
3002static struct gdsc sfe_1_gdsc = {
3003	.gdscr = 0x13098,
3004	.pd = {
3005		.name = "sfe_1_gdsc",
3006	},
3007	.flags = POLL_CFG_GDSCR,
3008	.parent = &titan_top_gdsc.pd,
3009	.pwrsts = PWRSTS_OFF_ON,
3010};
3011
3012static struct gdsc titan_top_gdsc = {
3013	.gdscr = 0x131dc,
3014	.pd = {
3015		.name = "titan_top_gdsc",
3016	},
3017	.flags = POLL_CFG_GDSCR,
3018	.pwrsts = PWRSTS_OFF_ON,
3019};
3020
3021static struct gdsc *cam_cc_sm8450_gdscs[] = {
3022	[BPS_GDSC] = &bps_gdsc,
3023	[IPE_0_GDSC] = &ipe_0_gdsc,
3024	[SBI_GDSC] = &sbi_gdsc,
3025	[IFE_0_GDSC] = &ife_0_gdsc,
3026	[IFE_1_GDSC] = &ife_1_gdsc,
3027	[IFE_2_GDSC] = &ife_2_gdsc,
3028	[SFE_0_GDSC] = &sfe_0_gdsc,
3029	[SFE_1_GDSC] = &sfe_1_gdsc,
3030	[TITAN_TOP_GDSC] = &titan_top_gdsc,
3031};
3032
3033static struct qcom_cc_driver_data cam_cc_sm8450_driver_data = {
3034	.alpha_plls = cam_cc_sm8450_plls,
3035	.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8450_plls),
3036	.clk_cbcrs = cam_cc_sm8450_critical_cbcrs,
3037	.num_clk_cbcrs = ARRAY_SIZE(cam_cc_sm8450_critical_cbcrs),
3038};
3039
3040static const struct qcom_cc_desc cam_cc_sm8450_desc = {
3041	.config = &cam_cc_sm8450_regmap_config,
3042	.clks = cam_cc_sm8450_clocks,
3043	.num_clks = ARRAY_SIZE(cam_cc_sm8450_clocks),
3044	.resets = cam_cc_sm8450_resets,
3045	.num_resets = ARRAY_SIZE(cam_cc_sm8450_resets),
3046	.gdscs = cam_cc_sm8450_gdscs,
3047	.num_gdscs = ARRAY_SIZE(cam_cc_sm8450_gdscs),
3048	.use_rpm = true,
3049	.driver_data = &cam_cc_sm8450_driver_data,
3050};
3051
3052static const struct of_device_id cam_cc_sm8450_match_table[] = {
3053	{ .compatible = "qcom,sm8450-camcc" },
3054	{ .compatible = "qcom,sm8475-camcc" },
3055	{ }
3056};
3057MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table);
3058
3059static int cam_cc_sm8450_probe(struct platform_device *pdev)
3060{
3061	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-camcc")) {
3062		/* Update CAMCC PLL0 */
3063		cam_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3064		cam_cc_pll0_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3065		cam_cc_pll0_out_even.clkr.hw.init = &sm8475_cam_cc_pll0_out_even_init;
3066		cam_cc_pll0_out_odd.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3067		cam_cc_pll0_out_odd.clkr.hw.init = &sm8475_cam_cc_pll0_out_odd_init;
3068
3069		/* Update CAMCC PLL1 */
3070		cam_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3071		cam_cc_pll1_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3072		cam_cc_pll1_out_even.clkr.hw.init = &sm8475_cam_cc_pll1_out_even_init;
3073
3074		/* Update CAMCC PLL2 */
3075		cam_cc_pll2.vco_table = rivian_ole_vco;
3076
3077		/* Update CAMCC PLL3 */
3078		cam_cc_pll3.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3079		cam_cc_pll3_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3080		cam_cc_pll3_out_even.clkr.hw.init = &sm8475_cam_cc_pll3_out_even_init;
3081
3082		/* Update CAMCC PLL4 */
3083		cam_cc_pll4.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3084		cam_cc_pll4_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3085		cam_cc_pll4_out_even.clkr.hw.init = &sm8475_cam_cc_pll4_out_even_init;
3086
3087		/* Update CAMCC PLL5 */
3088		cam_cc_pll5.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3089		cam_cc_pll5_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3090		cam_cc_pll5_out_even.clkr.hw.init = &sm8475_cam_cc_pll5_out_even_init;
3091
3092		/* Update CAMCC PLL6 */
3093		cam_cc_pll6.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3094		cam_cc_pll6_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3095		cam_cc_pll6_out_even.clkr.hw.init = &sm8475_cam_cc_pll6_out_even_init;
3096
3097		/* Update CAMCC PLL7 */
3098		cam_cc_pll7.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3099		cam_cc_pll7_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3100		cam_cc_pll7_out_even.clkr.hw.init = &sm8475_cam_cc_pll7_out_even_init;
3101
3102		/* Update CAMCC PLL8 */
3103		cam_cc_pll8.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3104		cam_cc_pll8_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
3105		cam_cc_pll8_out_even.clkr.hw.init = &sm8475_cam_cc_pll8_out_even_init;
3106
3107		cam_cc_pll0.config = &sm8475_cam_cc_pll0_config;
3108		cam_cc_pll1.config = &sm8475_cam_cc_pll1_config;
3109		cam_cc_pll2.config = &sm8475_cam_cc_pll2_config;
3110		cam_cc_pll3.config = &sm8475_cam_cc_pll3_config;
3111		cam_cc_pll4.config = &sm8475_cam_cc_pll4_config;
3112		cam_cc_pll5.config = &sm8475_cam_cc_pll5_config;
3113		cam_cc_pll6.config = &sm8475_cam_cc_pll6_config;
3114		cam_cc_pll7.config = &sm8475_cam_cc_pll7_config;
3115		cam_cc_pll8.config = &sm8475_cam_cc_pll8_config;
3116	}
3117
3118	return qcom_cc_probe(pdev, &cam_cc_sm8450_desc);
3119}
3120
3121static struct platform_driver cam_cc_sm8450_driver = {
3122	.probe = cam_cc_sm8450_probe,
3123	.driver = {
3124		.name = "camcc-sm8450",
3125		.of_match_table = cam_cc_sm8450_match_table,
3126	},
3127};
3128
3129module_platform_driver(cam_cc_sm8450_driver);
3130
3131MODULE_DESCRIPTION("QCOM CAMCC SM8450 / SM8475 Driver");
3132MODULE_LICENSE("GPL");