camcc-sm8150.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
   4 */
   5
   6#include <linux/clk-provider.h>
   7#include <linux/err.h>
   8#include <linux/kernel.h>
   9#include <linux/mod_devicetable.h>
  10#include <linux/module.h>
  11#include <linux/platform_device.h>
  12#include <linux/regmap.h>
  13#include <linux/pm_runtime.h>
  14
  15#include <dt-bindings/clock/qcom,sm8150-camcc.h>
  16
  17#include "clk-alpha-pll.h"
  18#include "clk-branch.h"
  19#include "clk-rcg.h"
  20#include "clk-regmap.h"
  21#include "common.h"
  22#include "gdsc.h"
  23#include "reset.h"
  24
  25enum {
  26	DT_BI_TCXO,
  27	DT_IFACE,
  28};
  29
  30enum {
  31	P_BI_TCXO,
  32	P_CAM_CC_PLL0_OUT_EVEN,
  33	P_CAM_CC_PLL0_OUT_MAIN,
  34	P_CAM_CC_PLL0_OUT_ODD,
  35	P_CAM_CC_PLL1_OUT_EVEN,
  36	P_CAM_CC_PLL2_OUT_EARLY,
  37	P_CAM_CC_PLL2_OUT_MAIN,
  38	P_CAM_CC_PLL3_OUT_EVEN,
  39	P_CAM_CC_PLL4_OUT_EVEN,
  40};
  41
  42static const struct pll_vco regera_vco[] = {
  43	{ 600000000, 3300000000, 0 },
  44};
  45
  46static const struct pll_vco trion_vco[] = {
  47	{ 249600000, 2000000000, 0 },
  48};
  49
  50static const struct alpha_pll_config cam_cc_pll0_config = {
  51	.l = 0x3e,
  52	.alpha = 0x8000,
  53	.config_ctl_val = 0x20485699,
  54	.config_ctl_hi_val = 0x00002267,
  55	.config_ctl_hi1_val = 0x00000024,
  56	.test_ctl_val = 0x00000000,
  57	.test_ctl_hi_val = 0x00000000,
  58	.test_ctl_hi1_val = 0x00000020,
  59	.user_ctl_val = 0x00003100,
  60	.user_ctl_hi_val = 0x00000805,
  61	.user_ctl_hi1_val = 0x000000D0,
  62};
  63
  64static struct clk_alpha_pll cam_cc_pll0 = {
  65	.offset = 0x0,
  66	.vco_table = trion_vco,
  67	.num_vco = ARRAY_SIZE(trion_vco),
  68	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  69	.clkr = {
  70		.hw.init = &(const struct clk_init_data) {
  71			.name = "cam_cc_pll0",
  72			.parent_data = &(const struct clk_parent_data) {
  73				.index = DT_BI_TCXO,
  74			},
  75			.num_parents = 1,
  76			.ops = &clk_alpha_pll_trion_ops,
  77		},
  78	},
  79};
  80
  81static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
  82	{ 0x1, 2 },
  83	{ }
  84};
  85
  86static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
  87	.offset = 0x0,
  88	.post_div_shift = 8,
  89	.post_div_table = post_div_table_cam_cc_pll0_out_even,
  90	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
  91	.width = 4,
  92	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  93	.clkr.hw.init = &(const struct clk_init_data) {
  94		.name = "cam_cc_pll0_out_even",
  95		.parent_hws = (const struct clk_hw*[]) {
  96			&cam_cc_pll0.clkr.hw,
  97		},
  98		.num_parents = 1,
  99		.flags = CLK_SET_RATE_PARENT,
 100		.ops = &clk_alpha_pll_postdiv_trion_ops,
 101	},
 102};
 103
 104static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
 105	{ 0x3, 3 },
 106	{ }
 107};
 108
 109static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
 110	.offset = 0x0,
 111	.post_div_shift = 12,
 112	.post_div_table = post_div_table_cam_cc_pll0_out_odd,
 113	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
 114	.width = 4,
 115	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
 116	.clkr.hw.init = &(const struct clk_init_data) {
 117		.name = "cam_cc_pll0_out_odd",
 118		.parent_hws = (const struct clk_hw*[]) {
 119			&cam_cc_pll0.clkr.hw,
 120		},
 121		.num_parents = 1,
 122		.flags = CLK_SET_RATE_PARENT,
 123		.ops = &clk_alpha_pll_postdiv_trion_ops,
 124	},
 125};
 126
 127static const struct alpha_pll_config cam_cc_pll1_config = {
 128	.l = 0x1f,
 129	.alpha = 0x4000,
 130	.config_ctl_val = 0x20485699,
 131	.config_ctl_hi_val = 0x00002267,
 132	.config_ctl_hi1_val = 0x00000024,
 133	.test_ctl_val = 0x00000000,
 134	.test_ctl_hi_val = 0x00000000,
 135	.test_ctl_hi1_val = 0x00000020,
 136	.user_ctl_val = 0x00000100,
 137	.user_ctl_hi_val = 0x00000805,
 138	.user_ctl_hi1_val = 0x000000D0,
 139};
 140
 141static struct clk_alpha_pll cam_cc_pll1 = {
 142	.offset = 0x1000,
 143	.vco_table = trion_vco,
 144	.num_vco = ARRAY_SIZE(trion_vco),
 145	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
 146	.clkr = {
 147		.hw.init = &(const struct clk_init_data) {
 148			.name = "cam_cc_pll1",
 149			.parent_data = &(const struct clk_parent_data) {
 150				.index = DT_BI_TCXO,
 151			},
 152			.num_parents = 1,
 153			.ops = &clk_alpha_pll_trion_ops,
 154		},
 155	},
 156};
 157
 158static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
 159	{ 0x1, 2 },
 160	{ }
 161};
 162
 163static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
 164	.offset = 0x1000,
 165	.post_div_shift = 8,
 166	.post_div_table = post_div_table_cam_cc_pll1_out_even,
 167	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
 168	.width = 4,
 169	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
 170	.clkr.hw.init = &(const struct clk_init_data) {
 171		.name = "cam_cc_pll1_out_even",
 172		.parent_hws = (const struct clk_hw*[]) {
 173			&cam_cc_pll1.clkr.hw,
 174		},
 175		.num_parents = 1,
 176		.flags = CLK_SET_RATE_PARENT,
 177		.ops = &clk_alpha_pll_postdiv_trion_ops,
 178	},
 179};
 180
 181static const struct alpha_pll_config cam_cc_pll2_config = {
 182	.l = 0x32,
 183	.alpha = 0x0,
 184	.config_ctl_val = 0x10000807,
 185	.config_ctl_hi_val = 0x00000011,
 186	.config_ctl_hi1_val = 0x04300142,
 187	.test_ctl_val = 0x04000400,
 188	.test_ctl_hi_val = 0x00004000,
 189	.test_ctl_hi1_val = 0x00000000,
 190	.user_ctl_val = 0x00000100,
 191	.user_ctl_hi_val = 0x00000000,
 192	.user_ctl_hi1_val = 0x00000000,
 193};
 194
 195static struct clk_alpha_pll cam_cc_pll2 = {
 196	.offset = 0x2000,
 197	.vco_table = regera_vco,
 198	.num_vco = ARRAY_SIZE(regera_vco),
 199	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_REGERA],
 200	.clkr = {
 201		.hw.init = &(const struct clk_init_data) {
 202			.name = "cam_cc_pll2",
 203			.parent_data = &(const struct clk_parent_data) {
 204				.index = DT_BI_TCXO,
 205			},
 206			.num_parents = 1,
 207			.ops = &clk_alpha_pll_regera_ops,
 208		},
 209	},
 210};
 211
 212static const struct clk_div_table post_div_table_cam_cc_pll2_out_main[] = {
 213	{ 0x1, 2 },
 214	{ }
 215};
 216
 217static struct clk_alpha_pll_postdiv cam_cc_pll2_out_main = {
 218	.offset = 0x2000,
 219	.post_div_shift = 8,
 220	.post_div_table = post_div_table_cam_cc_pll2_out_main,
 221	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_main),
 222	.width = 2,
 223	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_REGERA],
 224	.clkr.hw.init = &(const struct clk_init_data) {
 225		.name = "cam_cc_pll2_out_main",
 226		.parent_hws = (const struct clk_hw*[]) {
 227			&cam_cc_pll2.clkr.hw,
 228		},
 229		.num_parents = 1,
 230		.flags = CLK_SET_RATE_PARENT,
 231		.ops = &clk_alpha_pll_postdiv_trion_ops,
 232	},
 233};
 234
 235static const struct alpha_pll_config cam_cc_pll3_config = {
 236	.l = 0x29,
 237	.alpha = 0xaaaa,
 238	.config_ctl_val = 0x20485699,
 239	.config_ctl_hi_val = 0x00002267,
 240	.config_ctl_hi1_val = 0x00000024,
 241	.test_ctl_val = 0x00000000,
 242	.test_ctl_hi_val = 0x00000000,
 243	.test_ctl_hi1_val = 0x00000020,
 244	.user_ctl_val = 0x00000100,
 245	.user_ctl_hi_val = 0x00000805,
 246	.user_ctl_hi1_val = 0x000000D0,
 247};
 248
 249static struct clk_alpha_pll cam_cc_pll3 = {
 250	.offset = 0x3000,
 251	.vco_table = trion_vco,
 252	.num_vco = ARRAY_SIZE(trion_vco),
 253	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
 254	.clkr = {
 255		.hw.init = &(const struct clk_init_data) {
 256			.name = "cam_cc_pll3",
 257			.parent_data = &(const struct clk_parent_data) {
 258				.index = DT_BI_TCXO,
 259			},
 260			.num_parents = 1,
 261			.ops = &clk_alpha_pll_trion_ops,
 262		},
 263	},
 264};
 265
 266static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
 267	{ 0x1, 2 },
 268	{ }
 269};
 270
 271static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
 272	.offset = 0x3000,
 273	.post_div_shift = 8,
 274	.post_div_table = post_div_table_cam_cc_pll3_out_even,
 275	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
 276	.width = 4,
 277	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
 278	.clkr.hw.init = &(const struct clk_init_data) {
 279		.name = "cam_cc_pll3_out_even",
 280		.parent_hws = (const struct clk_hw*[]) {
 281			&cam_cc_pll3.clkr.hw,
 282		},
 283		.num_parents = 1,
 284		.flags = CLK_SET_RATE_PARENT,
 285		.ops = &clk_alpha_pll_postdiv_trion_ops,
 286	},
 287};
 288
 289static const struct alpha_pll_config cam_cc_pll4_config = {
 290	.l = 0x29,
 291	.alpha = 0xaaaa,
 292	.config_ctl_val = 0x20485699,
 293	.config_ctl_hi_val = 0x00002267,
 294	.config_ctl_hi1_val = 0x00000024,
 295	.test_ctl_val = 0x00000000,
 296	.test_ctl_hi_val = 0x00000000,
 297	.test_ctl_hi1_val = 0x00000020,
 298	.user_ctl_val = 0x00000100,
 299	.user_ctl_hi_val = 0x00000805,
 300	.user_ctl_hi1_val = 0x000000D0,
 301};
 302
 303static struct clk_alpha_pll cam_cc_pll4 = {
 304	.offset = 0x4000,
 305	.vco_table = trion_vco,
 306	.num_vco = ARRAY_SIZE(trion_vco),
 307	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
 308	.clkr = {
 309		.hw.init = &(const struct clk_init_data) {
 310			.name = "cam_cc_pll4",
 311			.parent_data = &(const struct clk_parent_data) {
 312				.index = DT_BI_TCXO,
 313			},
 314			.num_parents = 1,
 315			.ops = &clk_alpha_pll_trion_ops,
 316		},
 317	},
 318};
 319
 320static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
 321	{ 0x1, 2 },
 322	{ }
 323};
 324
 325static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
 326	.offset = 0x4000,
 327	.post_div_shift = 8,
 328	.post_div_table = post_div_table_cam_cc_pll4_out_even,
 329	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
 330	.width = 4,
 331	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
 332	.clkr.hw.init = &(const struct clk_init_data) {
 333		.name = "cam_cc_pll4_out_even",
 334		.parent_hws = (const struct clk_hw*[]) {
 335			&cam_cc_pll4.clkr.hw,
 336		},
 337		.num_parents = 1,
 338		.flags = CLK_SET_RATE_PARENT,
 339		.ops = &clk_alpha_pll_postdiv_trion_ops,
 340	},
 341};
 342
 343static const struct parent_map cam_cc_parent_map_0[] = {
 344	{ P_BI_TCXO, 0 },
 345	{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
 346	{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
 347	{ P_CAM_CC_PLL0_OUT_ODD, 3 },
 348	{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
 349};
 350
 351static const struct clk_parent_data cam_cc_parent_data_0[] = {
 352	{ .index = DT_BI_TCXO },
 353	{ .hw = &cam_cc_pll0.clkr.hw },
 354	{ .hw = &cam_cc_pll0_out_even.clkr.hw },
 355	{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
 356	{ .hw = &cam_cc_pll2_out_main.clkr.hw },
 357};
 358
 359static const struct parent_map cam_cc_parent_map_1[] = {
 360	{ P_BI_TCXO, 0 },
 361	{ P_CAM_CC_PLL2_OUT_EARLY, 5 },
 362};
 363
 364static const struct clk_parent_data cam_cc_parent_data_1[] = {
 365	{ .index = DT_BI_TCXO },
 366	{ .hw = &cam_cc_pll2.clkr.hw },
 367};
 368
 369static const struct parent_map cam_cc_parent_map_2[] = {
 370	{ P_BI_TCXO, 0 },
 371	{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
 372};
 373
 374static const struct clk_parent_data cam_cc_parent_data_2[] = {
 375	{ .index = DT_BI_TCXO },
 376	{ .hw = &cam_cc_pll3_out_even.clkr.hw },
 377};
 378
 379static const struct parent_map cam_cc_parent_map_3[] = {
 380	{ P_BI_TCXO, 0 },
 381	{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
 382};
 383
 384static const struct clk_parent_data cam_cc_parent_data_3[] = {
 385	{ .index = DT_BI_TCXO },
 386	{ .hw = &cam_cc_pll4_out_even.clkr.hw },
 387};
 388
 389static const struct parent_map cam_cc_parent_map_4[] = {
 390	{ P_BI_TCXO, 0 },
 391	{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
 392};
 393
 394static const struct clk_parent_data cam_cc_parent_data_4[] = {
 395	{ .index = DT_BI_TCXO },
 396	{ .hw = &cam_cc_pll1_out_even.clkr.hw },
 397};
 398
 399static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
 400	F(19200000, P_BI_TCXO, 1, 0, 0),
 401	F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
 402	F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
 403	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 404	F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
 405	F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
 406	{ }
 407};
 408
 409static struct clk_rcg2 cam_cc_bps_clk_src = {
 410	.cmd_rcgr = 0x7010,
 411	.mnd_width = 0,
 412	.hid_width = 5,
 413	.parent_map = cam_cc_parent_map_0,
 414	.freq_tbl = ftbl_cam_cc_bps_clk_src,
 415	.clkr.hw.init = &(const struct clk_init_data) {
 416		.name = "cam_cc_bps_clk_src",
 417		.parent_data = cam_cc_parent_data_0,
 418		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 419		.flags = CLK_SET_RATE_PARENT,
 420		.ops = &clk_rcg2_shared_ops,
 421	},
 422};
 423
 424static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
 425	F(19200000, P_BI_TCXO, 1, 0, 0),
 426	F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
 427	F(266666667, P_CAM_CC_PLL0_OUT_ODD, 1.5, 0, 0),
 428	F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
 429	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
 430	F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
 431	{ }
 432};
 433
 434static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
 435	.cmd_rcgr = 0xc170,
 436	.mnd_width = 0,
 437	.hid_width = 5,
 438	.parent_map = cam_cc_parent_map_0,
 439	.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
 440	.clkr.hw.init = &(const struct clk_init_data) {
 441		.name = "cam_cc_camnoc_axi_clk_src",
 442		.parent_data = cam_cc_parent_data_0,
 443		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 444		.flags = CLK_SET_RATE_PARENT,
 445		.ops = &clk_rcg2_shared_ops,
 446	},
 447};
 448
 449static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
 450	F(19200000, P_BI_TCXO, 1, 0, 0),
 451	F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
 452	{ }
 453};
 454
 455static struct clk_rcg2 cam_cc_cci_0_clk_src = {
 456	.cmd_rcgr = 0xc108,
 457	.mnd_width = 8,
 458	.hid_width = 5,
 459	.parent_map = cam_cc_parent_map_0,
 460	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 461	.clkr.hw.init = &(const struct clk_init_data) {
 462		.name = "cam_cc_cci_0_clk_src",
 463		.parent_data = cam_cc_parent_data_0,
 464		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 465		.flags = CLK_SET_RATE_PARENT,
 466		.ops = &clk_rcg2_shared_ops,
 467	},
 468};
 469
 470static struct clk_rcg2 cam_cc_cci_1_clk_src = {
 471	.cmd_rcgr = 0xc124,
 472	.mnd_width = 8,
 473	.hid_width = 5,
 474	.parent_map = cam_cc_parent_map_0,
 475	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
 476	.clkr.hw.init = &(const struct clk_init_data) {
 477		.name = "cam_cc_cci_1_clk_src",
 478		.parent_data = cam_cc_parent_data_0,
 479		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 480		.flags = CLK_SET_RATE_PARENT,
 481		.ops = &clk_rcg2_shared_ops,
 482	},
 483};
 484
 485static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
 486	F(19200000, P_BI_TCXO, 1, 0, 0),
 487	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 488	{ }
 489};
 490
 491static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
 492	.cmd_rcgr = 0xa064,
 493	.mnd_width = 0,
 494	.hid_width = 5,
 495	.parent_map = cam_cc_parent_map_0,
 496	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
 497	.clkr.hw.init = &(const struct clk_init_data) {
 498		.name = "cam_cc_cphy_rx_clk_src",
 499		.parent_data = cam_cc_parent_data_0,
 500		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 501		.flags = CLK_SET_RATE_PARENT,
 502		.ops = &clk_rcg2_shared_ops,
 503	},
 504};
 505
 506static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
 507	F(19200000, P_BI_TCXO, 1, 0, 0),
 508	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
 509	{ }
 510};
 511
 512static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
 513	.cmd_rcgr = 0x6004,
 514	.mnd_width = 0,
 515	.hid_width = 5,
 516	.parent_map = cam_cc_parent_map_0,
 517	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 518	.clkr.hw.init = &(const struct clk_init_data) {
 519		.name = "cam_cc_csi0phytimer_clk_src",
 520		.parent_data = cam_cc_parent_data_0,
 521		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 522		.flags = CLK_SET_RATE_PARENT,
 523		.ops = &clk_rcg2_shared_ops,
 524	},
 525};
 526
 527static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
 528	.cmd_rcgr = 0x6028,
 529	.mnd_width = 0,
 530	.hid_width = 5,
 531	.parent_map = cam_cc_parent_map_0,
 532	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 533	.clkr.hw.init = &(const struct clk_init_data) {
 534		.name = "cam_cc_csi1phytimer_clk_src",
 535		.parent_data = cam_cc_parent_data_0,
 536		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 537		.flags = CLK_SET_RATE_PARENT,
 538		.ops = &clk_rcg2_shared_ops,
 539	},
 540};
 541
 542static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
 543	.cmd_rcgr = 0x604c,
 544	.mnd_width = 0,
 545	.hid_width = 5,
 546	.parent_map = cam_cc_parent_map_0,
 547	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 548	.clkr.hw.init = &(const struct clk_init_data) {
 549		.name = "cam_cc_csi2phytimer_clk_src",
 550		.parent_data = cam_cc_parent_data_0,
 551		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 552		.flags = CLK_SET_RATE_PARENT,
 553		.ops = &clk_rcg2_shared_ops,
 554	},
 555};
 556
 557static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
 558	.cmd_rcgr = 0x6070,
 559	.mnd_width = 0,
 560	.hid_width = 5,
 561	.parent_map = cam_cc_parent_map_0,
 562	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 563	.clkr.hw.init = &(const struct clk_init_data) {
 564		.name = "cam_cc_csi3phytimer_clk_src",
 565		.parent_data = cam_cc_parent_data_0,
 566		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 567		.flags = CLK_SET_RATE_PARENT,
 568		.ops = &clk_rcg2_shared_ops,
 569	},
 570};
 571
 572static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
 573	F(19200000, P_BI_TCXO, 1, 0, 0),
 574	F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
 575	F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
 576	F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
 577	F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
 578	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
 579	{ }
 580};
 581
 582static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
 583	.cmd_rcgr = 0x703c,
 584	.mnd_width = 0,
 585	.hid_width = 5,
 586	.parent_map = cam_cc_parent_map_0,
 587	.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
 588	.clkr.hw.init = &(const struct clk_init_data) {
 589		.name = "cam_cc_fast_ahb_clk_src",
 590		.parent_data = cam_cc_parent_data_0,
 591		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 592		.flags = CLK_SET_RATE_PARENT,
 593		.ops = &clk_rcg2_shared_ops,
 594	},
 595};
 596
 597static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = {
 598	F(19200000, P_BI_TCXO, 1, 0, 0),
 599	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 600	F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
 601	F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
 602	{ }
 603};
 604
 605static struct clk_rcg2 cam_cc_fd_core_clk_src = {
 606	.cmd_rcgr = 0xc0e0,
 607	.mnd_width = 0,
 608	.hid_width = 5,
 609	.parent_map = cam_cc_parent_map_0,
 610	.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
 611	.clkr.hw.init = &(const struct clk_init_data) {
 612		.name = "cam_cc_fd_core_clk_src",
 613		.parent_data = cam_cc_parent_data_0,
 614		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 615		.flags = CLK_SET_RATE_PARENT,
 616		.ops = &clk_rcg2_shared_ops,
 617	},
 618};
 619
 620static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
 621	F(19200000, P_BI_TCXO, 1, 0, 0),
 622	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 623	F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
 624	{ }
 625};
 626
 627static struct clk_rcg2 cam_cc_icp_clk_src = {
 628	.cmd_rcgr = 0xc0b8,
 629	.mnd_width = 0,
 630	.hid_width = 5,
 631	.parent_map = cam_cc_parent_map_0,
 632	.freq_tbl = ftbl_cam_cc_icp_clk_src,
 633	.clkr.hw.init = &(const struct clk_init_data) {
 634		.name = "cam_cc_icp_clk_src",
 635		.parent_data = cam_cc_parent_data_0,
 636		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 637		.flags = CLK_SET_RATE_PARENT,
 638		.ops = &clk_rcg2_shared_ops,
 639	},
 640};
 641
 642static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
 643	F(19200000, P_BI_TCXO, 1, 0, 0),
 644	F(400000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
 645	F(558000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
 646	F(637000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
 647	F(847000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
 648	F(950000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
 649	{ }
 650};
 651
 652static struct clk_rcg2 cam_cc_ife_0_clk_src = {
 653	.cmd_rcgr = 0xa010,
 654	.mnd_width = 0,
 655	.hid_width = 5,
 656	.parent_map = cam_cc_parent_map_2,
 657	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
 658	.clkr.hw.init = &(const struct clk_init_data) {
 659		.name = "cam_cc_ife_0_clk_src",
 660		.parent_data = cam_cc_parent_data_2,
 661		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
 662		.flags = CLK_SET_RATE_PARENT,
 663		.ops = &clk_rcg2_shared_ops,
 664	},
 665};
 666
 667static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
 668	F(19200000, P_BI_TCXO, 1, 0, 0),
 669	F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
 670	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 671	F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
 672	F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
 673	{ }
 674};
 675
 676static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
 677	.cmd_rcgr = 0xa03c,
 678	.mnd_width = 0,
 679	.hid_width = 5,
 680	.parent_map = cam_cc_parent_map_0,
 681	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
 682	.clkr.hw.init = &(const struct clk_init_data) {
 683		.name = "cam_cc_ife_0_csid_clk_src",
 684		.parent_data = cam_cc_parent_data_0,
 685		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 686		.flags = CLK_SET_RATE_PARENT,
 687		.ops = &clk_rcg2_shared_ops,
 688	},
 689};
 690
 691static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
 692	F(19200000, P_BI_TCXO, 1, 0, 0),
 693	F(400000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
 694	F(558000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
 695	F(637000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
 696	F(847000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
 697	F(950000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
 698	{ }
 699};
 700
 701static struct clk_rcg2 cam_cc_ife_1_clk_src = {
 702	.cmd_rcgr = 0xb010,
 703	.mnd_width = 0,
 704	.hid_width = 5,
 705	.parent_map = cam_cc_parent_map_3,
 706	.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
 707	.clkr.hw.init = &(const struct clk_init_data) {
 708		.name = "cam_cc_ife_1_clk_src",
 709		.parent_data = cam_cc_parent_data_3,
 710		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
 711		.flags = CLK_SET_RATE_PARENT,
 712		.ops = &clk_rcg2_shared_ops,
 713	},
 714};
 715
 716static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
 717	.cmd_rcgr = 0xb034,
 718	.mnd_width = 0,
 719	.hid_width = 5,
 720	.parent_map = cam_cc_parent_map_0,
 721	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
 722	.clkr.hw.init = &(const struct clk_init_data) {
 723		.name = "cam_cc_ife_1_csid_clk_src",
 724		.parent_data = cam_cc_parent_data_0,
 725		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 726		.flags = CLK_SET_RATE_PARENT,
 727		.ops = &clk_rcg2_shared_ops,
 728	},
 729};
 730
 731static const struct freq_tbl ftbl_cam_cc_ife_lite_0_clk_src[] = {
 732	F(19200000, P_BI_TCXO, 1, 0, 0),
 733	F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
 734	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
 735	F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1, 0, 0),
 736	F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
 737	{ }
 738};
 739
 740static struct clk_rcg2 cam_cc_ife_lite_0_clk_src = {
 741	.cmd_rcgr = 0xc004,
 742	.mnd_width = 0,
 743	.hid_width = 5,
 744	.parent_map = cam_cc_parent_map_0,
 745	.freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src,
 746	.clkr.hw.init = &(const struct clk_init_data) {
 747		.name = "cam_cc_ife_lite_0_clk_src",
 748		.parent_data = cam_cc_parent_data_0,
 749		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 750		.flags = CLK_SET_RATE_PARENT,
 751		.ops = &clk_rcg2_shared_ops,
 752	},
 753};
 754
 755static struct clk_rcg2 cam_cc_ife_lite_0_csid_clk_src = {
 756	.cmd_rcgr = 0xc020,
 757	.mnd_width = 0,
 758	.hid_width = 5,
 759	.parent_map = cam_cc_parent_map_0,
 760	.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
 761	.clkr.hw.init = &(const struct clk_init_data) {
 762		.name = "cam_cc_ife_lite_0_csid_clk_src",
 763		.parent_data = cam_cc_parent_data_0,
 764		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 765		.flags = CLK_SET_RATE_PARENT,
 766		.ops = &clk_rcg2_shared_ops,
 767	},
 768};
 769
 770static struct clk_rcg2 cam_cc_ife_lite_1_clk_src = {
 771	.cmd_rcgr = 0xc048,
 772	.mnd_width = 0,
 773	.hid_width = 5,
 774	.parent_map = cam_cc_parent_map_0,
 775	.freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src,
 776	.clkr.hw.init = &(const struct clk_init_data) {
 777		.name = "cam_cc_ife_lite_1_clk_src",
 778		.parent_data = cam_cc_parent_data_0,
 779		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 780		.flags = CLK_SET_RATE_PARENT,
 781		.ops = &clk_rcg2_shared_ops,
 782	},
 783};
 784
 785static struct clk_rcg2 cam_cc_ife_lite_1_csid_clk_src = {
 786	.cmd_rcgr = 0xc064,
 787	.mnd_width = 0,
 788	.hid_width = 5,
 789	.parent_map = cam_cc_parent_map_0,
 790	.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
 791	.clkr.hw.init = &(const struct clk_init_data) {
 792		.name = "cam_cc_ife_lite_1_csid_clk_src",
 793		.parent_data = cam_cc_parent_data_0,
 794		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 795		.flags = CLK_SET_RATE_PARENT,
 796		.ops = &clk_rcg2_shared_ops,
 797	},
 798};
 799
 800static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
 801	F(19200000, P_BI_TCXO, 1, 0, 0),
 802	F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
 803	F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
 804	F(520000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
 805	F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
 806	{ }
 807};
 808
 809static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
 810	.cmd_rcgr = 0x8010,
 811	.mnd_width = 0,
 812	.hid_width = 5,
 813	.parent_map = cam_cc_parent_map_4,
 814	.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
 815	.clkr.hw.init = &(const struct clk_init_data) {
 816		.name = "cam_cc_ipe_0_clk_src",
 817		.parent_data = cam_cc_parent_data_4,
 818		.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
 819		.flags = CLK_SET_RATE_PARENT,
 820		.ops = &clk_rcg2_shared_ops,
 821	},
 822};
 823
 824static struct clk_rcg2 cam_cc_jpeg_clk_src = {
 825	.cmd_rcgr = 0xc08c,
 826	.mnd_width = 0,
 827	.hid_width = 5,
 828	.parent_map = cam_cc_parent_map_0,
 829	.freq_tbl = ftbl_cam_cc_bps_clk_src,
 830	.clkr.hw.init = &(const struct clk_init_data) {
 831		.name = "cam_cc_jpeg_clk_src",
 832		.parent_data = cam_cc_parent_data_0,
 833		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 834		.flags = CLK_SET_RATE_PARENT,
 835		.ops = &clk_rcg2_shared_ops,
 836	},
 837};
 838
 839static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = {
 840	F(19200000, P_BI_TCXO, 1, 0, 0),
 841	F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
 842	F(240000000, P_CAM_CC_PLL2_OUT_MAIN, 2, 0, 0),
 843	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
 844	F(320000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
 845	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
 846	{ }
 847};
 848
 849static struct clk_rcg2 cam_cc_lrme_clk_src = {
 850	.cmd_rcgr = 0xc144,
 851	.mnd_width = 0,
 852	.hid_width = 5,
 853	.parent_map = cam_cc_parent_map_0,
 854	.freq_tbl = ftbl_cam_cc_lrme_clk_src,
 855	.clkr.hw.init = &(const struct clk_init_data) {
 856		.name = "cam_cc_lrme_clk_src",
 857		.parent_data = cam_cc_parent_data_0,
 858		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 859		.flags = CLK_SET_RATE_PARENT,
 860		.ops = &clk_rcg2_shared_ops,
 861	},
 862};
 863
 864static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
 865	F(12000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 8),
 866	F(19200000, P_BI_TCXO, 1, 0, 0),
 867	F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 4),
 868	F(68571429, P_CAM_CC_PLL2_OUT_EARLY, 14, 0, 0),
 869	{ }
 870};
 871
 872static struct clk_rcg2 cam_cc_mclk0_clk_src = {
 873	.cmd_rcgr = 0x5004,
 874	.mnd_width = 8,
 875	.hid_width = 5,
 876	.parent_map = cam_cc_parent_map_1,
 877	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
 878	.clkr.hw.init = &(const struct clk_init_data) {
 879		.name = "cam_cc_mclk0_clk_src",
 880		.parent_data = cam_cc_parent_data_1,
 881		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
 882		.flags = CLK_SET_RATE_PARENT,
 883		.ops = &clk_rcg2_shared_ops,
 884	},
 885};
 886
 887static struct clk_rcg2 cam_cc_mclk1_clk_src = {
 888	.cmd_rcgr = 0x5024,
 889	.mnd_width = 8,
 890	.hid_width = 5,
 891	.parent_map = cam_cc_parent_map_1,
 892	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
 893	.clkr.hw.init = &(const struct clk_init_data) {
 894		.name = "cam_cc_mclk1_clk_src",
 895		.parent_data = cam_cc_parent_data_1,
 896		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
 897		.flags = CLK_SET_RATE_PARENT,
 898		.ops = &clk_rcg2_shared_ops,
 899	},
 900};
 901
 902static struct clk_rcg2 cam_cc_mclk2_clk_src = {
 903	.cmd_rcgr = 0x5044,
 904	.mnd_width = 8,
 905	.hid_width = 5,
 906	.parent_map = cam_cc_parent_map_1,
 907	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
 908	.clkr.hw.init = &(const struct clk_init_data) {
 909		.name = "cam_cc_mclk2_clk_src",
 910		.parent_data = cam_cc_parent_data_1,
 911		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
 912		.flags = CLK_SET_RATE_PARENT,
 913		.ops = &clk_rcg2_shared_ops,
 914	},
 915};
 916
 917static struct clk_rcg2 cam_cc_mclk3_clk_src = {
 918	.cmd_rcgr = 0x5064,
 919	.mnd_width = 8,
 920	.hid_width = 5,
 921	.parent_map = cam_cc_parent_map_1,
 922	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
 923	.clkr.hw.init = &(const struct clk_init_data) {
 924		.name = "cam_cc_mclk3_clk_src",
 925		.parent_data = cam_cc_parent_data_1,
 926		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
 927		.flags = CLK_SET_RATE_PARENT,
 928		.ops = &clk_rcg2_shared_ops,
 929	},
 930};
 931
 932static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
 933	F(19200000, P_BI_TCXO, 1, 0, 0),
 934	F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
 935	{ }
 936};
 937
 938static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
 939	.cmd_rcgr = 0x7058,
 940	.mnd_width = 8,
 941	.hid_width = 5,
 942	.parent_map = cam_cc_parent_map_0,
 943	.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
 944	.clkr.hw.init = &(const struct clk_init_data) {
 945		.name = "cam_cc_slow_ahb_clk_src",
 946		.parent_data = cam_cc_parent_data_0,
 947		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 948		.flags = CLK_SET_RATE_PARENT,
 949		.ops = &clk_rcg2_shared_ops,
 950	},
 951};
 952
 953static struct clk_branch cam_cc_bps_ahb_clk = {
 954	.halt_reg = 0x7070,
 955	.halt_check = BRANCH_HALT,
 956	.clkr = {
 957		.enable_reg = 0x7070,
 958		.enable_mask = BIT(0),
 959		.hw.init = &(const struct clk_init_data) {
 960			.name = "cam_cc_bps_ahb_clk",
 961			.parent_hws = (const struct clk_hw*[]) {
 962				&cam_cc_slow_ahb_clk_src.clkr.hw,
 963			},
 964			.num_parents = 1,
 965			.flags = CLK_SET_RATE_PARENT,
 966			.ops = &clk_branch2_ops,
 967		},
 968	},
 969};
 970
 971static struct clk_branch cam_cc_bps_areg_clk = {
 972	.halt_reg = 0x7054,
 973	.halt_check = BRANCH_HALT,
 974	.clkr = {
 975		.enable_reg = 0x7054,
 976		.enable_mask = BIT(0),
 977		.hw.init = &(const struct clk_init_data) {
 978			.name = "cam_cc_bps_areg_clk",
 979			.parent_hws = (const struct clk_hw*[]) {
 980				&cam_cc_fast_ahb_clk_src.clkr.hw,
 981			},
 982			.num_parents = 1,
 983			.flags = CLK_SET_RATE_PARENT,
 984			.ops = &clk_branch2_ops,
 985		},
 986	},
 987};
 988
 989static struct clk_branch cam_cc_bps_axi_clk = {
 990	.halt_reg = 0x7038,
 991	.halt_check = BRANCH_HALT,
 992	.clkr = {
 993		.enable_reg = 0x7038,
 994		.enable_mask = BIT(0),
 995		.hw.init = &(const struct clk_init_data) {
 996			.name = "cam_cc_bps_axi_clk",
 997			.parent_hws = (const struct clk_hw*[]) {
 998				&cam_cc_camnoc_axi_clk_src.clkr.hw,
 999			},
1000			.num_parents = 1,
1001			.flags = CLK_SET_RATE_PARENT,
1002			.ops = &clk_branch2_ops,
1003		},
1004	},
1005};
1006
1007static struct clk_branch cam_cc_bps_clk = {
1008	.halt_reg = 0x7028,
1009	.halt_check = BRANCH_HALT,
1010	.clkr = {
1011		.enable_reg = 0x7028,
1012		.enable_mask = BIT(0),
1013		.hw.init = &(const struct clk_init_data) {
1014			.name = "cam_cc_bps_clk",
1015			.parent_hws = (const struct clk_hw*[]) {
1016				&cam_cc_bps_clk_src.clkr.hw,
1017			},
1018			.num_parents = 1,
1019			.flags = CLK_SET_RATE_PARENT,
1020			.ops = &clk_branch2_ops,
1021		},
1022	},
1023};
1024
1025static struct clk_branch cam_cc_camnoc_axi_clk = {
1026	.halt_reg = 0xc18c,
1027	.halt_check = BRANCH_HALT,
1028	.clkr = {
1029		.enable_reg = 0xc18c,
1030		.enable_mask = BIT(0),
1031		.hw.init = &(const struct clk_init_data) {
1032			.name = "cam_cc_camnoc_axi_clk",
1033			.parent_hws = (const struct clk_hw*[]) {
1034				&cam_cc_camnoc_axi_clk_src.clkr.hw,
1035			},
1036			.num_parents = 1,
1037			.flags = CLK_SET_RATE_PARENT,
1038			.ops = &clk_branch2_ops,
1039		},
1040	},
1041};
1042
1043static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
1044	.halt_reg = 0xc194,
1045	.halt_check = BRANCH_HALT,
1046	.clkr = {
1047		.enable_reg = 0xc194,
1048		.enable_mask = BIT(0),
1049		.hw.init = &(const struct clk_init_data) {
1050			.name = "cam_cc_camnoc_dcd_xo_clk",
1051			.ops = &clk_branch2_ops,
1052		},
1053	},
1054};
1055
1056static struct clk_branch cam_cc_cci_0_clk = {
1057	.halt_reg = 0xc120,
1058	.halt_check = BRANCH_HALT,
1059	.clkr = {
1060		.enable_reg = 0xc120,
1061		.enable_mask = BIT(0),
1062		.hw.init = &(const struct clk_init_data) {
1063			.name = "cam_cc_cci_0_clk",
1064			.parent_hws = (const struct clk_hw*[]) {
1065				&cam_cc_cci_0_clk_src.clkr.hw,
1066			},
1067			.num_parents = 1,
1068			.flags = CLK_SET_RATE_PARENT,
1069			.ops = &clk_branch2_ops,
1070		},
1071	},
1072};
1073
1074static struct clk_branch cam_cc_cci_1_clk = {
1075	.halt_reg = 0xc13c,
1076	.halt_check = BRANCH_HALT,
1077	.clkr = {
1078		.enable_reg = 0xc13c,
1079		.enable_mask = BIT(0),
1080		.hw.init = &(const struct clk_init_data) {
1081			.name = "cam_cc_cci_1_clk",
1082			.parent_hws = (const struct clk_hw*[]) {
1083				&cam_cc_cci_1_clk_src.clkr.hw,
1084			},
1085			.num_parents = 1,
1086			.flags = CLK_SET_RATE_PARENT,
1087			.ops = &clk_branch2_ops,
1088		},
1089	},
1090};
1091
1092static struct clk_branch cam_cc_core_ahb_clk = {
1093	.halt_reg = 0xc1c8,
1094	.halt_check = BRANCH_HALT_DELAY,
1095	.clkr = {
1096		.enable_reg = 0xc1c8,
1097		.enable_mask = BIT(0),
1098		.hw.init = &(const struct clk_init_data) {
1099			.name = "cam_cc_core_ahb_clk",
1100			.parent_hws = (const struct clk_hw*[]) {
1101				&cam_cc_slow_ahb_clk_src.clkr.hw,
1102			},
1103			.num_parents = 1,
1104			.flags = CLK_SET_RATE_PARENT,
1105			.ops = &clk_branch2_ops,
1106		},
1107	},
1108};
1109
1110static struct clk_branch cam_cc_cpas_ahb_clk = {
1111	.halt_reg = 0xc168,
1112	.halt_check = BRANCH_HALT,
1113	.clkr = {
1114		.enable_reg = 0xc168,
1115		.enable_mask = BIT(0),
1116		.hw.init = &(const struct clk_init_data) {
1117			.name = "cam_cc_cpas_ahb_clk",
1118			.parent_hws = (const struct clk_hw*[]) {
1119				&cam_cc_slow_ahb_clk_src.clkr.hw,
1120			},
1121			.num_parents = 1,
1122			.flags = CLK_SET_RATE_PARENT,
1123			.ops = &clk_branch2_ops,
1124		},
1125	},
1126};
1127
1128static struct clk_branch cam_cc_csi0phytimer_clk = {
1129	.halt_reg = 0x601c,
1130	.halt_check = BRANCH_HALT,
1131	.clkr = {
1132		.enable_reg = 0x601c,
1133		.enable_mask = BIT(0),
1134		.hw.init = &(const struct clk_init_data) {
1135			.name = "cam_cc_csi0phytimer_clk",
1136			.parent_hws = (const struct clk_hw*[]) {
1137				&cam_cc_csi0phytimer_clk_src.clkr.hw,
1138			},
1139			.num_parents = 1,
1140			.flags = CLK_SET_RATE_PARENT,
1141			.ops = &clk_branch2_ops,
1142		},
1143	},
1144};
1145
1146static struct clk_branch cam_cc_csi1phytimer_clk = {
1147	.halt_reg = 0x6040,
1148	.halt_check = BRANCH_HALT,
1149	.clkr = {
1150		.enable_reg = 0x6040,
1151		.enable_mask = BIT(0),
1152		.hw.init = &(const struct clk_init_data) {
1153			.name = "cam_cc_csi1phytimer_clk",
1154			.parent_hws = (const struct clk_hw*[]) {
1155				&cam_cc_csi1phytimer_clk_src.clkr.hw,
1156			},
1157			.num_parents = 1,
1158			.flags = CLK_SET_RATE_PARENT,
1159			.ops = &clk_branch2_ops,
1160		},
1161	},
1162};
1163
1164static struct clk_branch cam_cc_csi2phytimer_clk = {
1165	.halt_reg = 0x6064,
1166	.halt_check = BRANCH_HALT,
1167	.clkr = {
1168		.enable_reg = 0x6064,
1169		.enable_mask = BIT(0),
1170		.hw.init = &(const struct clk_init_data) {
1171			.name = "cam_cc_csi2phytimer_clk",
1172			.parent_hws = (const struct clk_hw*[]) {
1173				&cam_cc_csi2phytimer_clk_src.clkr.hw,
1174			},
1175			.num_parents = 1,
1176			.flags = CLK_SET_RATE_PARENT,
1177			.ops = &clk_branch2_ops,
1178		},
1179	},
1180};
1181
1182static struct clk_branch cam_cc_csi3phytimer_clk = {
1183	.halt_reg = 0x6088,
1184	.halt_check = BRANCH_HALT,
1185	.clkr = {
1186		.enable_reg = 0x6088,
1187		.enable_mask = BIT(0),
1188		.hw.init = &(const struct clk_init_data) {
1189			.name = "cam_cc_csi3phytimer_clk",
1190			.parent_hws = (const struct clk_hw*[]) {
1191				&cam_cc_csi3phytimer_clk_src.clkr.hw,
1192			},
1193			.num_parents = 1,
1194			.flags = CLK_SET_RATE_PARENT,
1195			.ops = &clk_branch2_ops,
1196		},
1197	},
1198};
1199
1200static struct clk_branch cam_cc_csiphy0_clk = {
1201	.halt_reg = 0x6020,
1202	.halt_check = BRANCH_HALT,
1203	.clkr = {
1204		.enable_reg = 0x6020,
1205		.enable_mask = BIT(0),
1206		.hw.init = &(const struct clk_init_data) {
1207			.name = "cam_cc_csiphy0_clk",
1208			.parent_hws = (const struct clk_hw*[]) {
1209				&cam_cc_cphy_rx_clk_src.clkr.hw,
1210			},
1211			.num_parents = 1,
1212			.flags = CLK_SET_RATE_PARENT,
1213			.ops = &clk_branch2_ops,
1214		},
1215	},
1216};
1217
1218static struct clk_branch cam_cc_csiphy1_clk = {
1219	.halt_reg = 0x6044,
1220	.halt_check = BRANCH_HALT,
1221	.clkr = {
1222		.enable_reg = 0x6044,
1223		.enable_mask = BIT(0),
1224		.hw.init = &(const struct clk_init_data) {
1225			.name = "cam_cc_csiphy1_clk",
1226			.parent_hws = (const struct clk_hw*[]) {
1227				&cam_cc_cphy_rx_clk_src.clkr.hw,
1228			},
1229			.num_parents = 1,
1230			.flags = CLK_SET_RATE_PARENT,
1231			.ops = &clk_branch2_ops,
1232		},
1233	},
1234};
1235
1236static struct clk_branch cam_cc_csiphy2_clk = {
1237	.halt_reg = 0x6068,
1238	.halt_check = BRANCH_HALT,
1239	.clkr = {
1240		.enable_reg = 0x6068,
1241		.enable_mask = BIT(0),
1242		.hw.init = &(const struct clk_init_data) {
1243			.name = "cam_cc_csiphy2_clk",
1244			.parent_hws = (const struct clk_hw*[]) {
1245				&cam_cc_cphy_rx_clk_src.clkr.hw,
1246			},
1247			.num_parents = 1,
1248			.flags = CLK_SET_RATE_PARENT,
1249			.ops = &clk_branch2_ops,
1250		},
1251	},
1252};
1253
1254static struct clk_branch cam_cc_csiphy3_clk = {
1255	.halt_reg = 0x608c,
1256	.halt_check = BRANCH_HALT,
1257	.clkr = {
1258		.enable_reg = 0x608c,
1259		.enable_mask = BIT(0),
1260		.hw.init = &(const struct clk_init_data) {
1261			.name = "cam_cc_csiphy3_clk",
1262			.parent_hws = (const struct clk_hw*[]) {
1263				&cam_cc_cphy_rx_clk_src.clkr.hw,
1264			},
1265			.num_parents = 1,
1266			.flags = CLK_SET_RATE_PARENT,
1267			.ops = &clk_branch2_ops,
1268		},
1269	},
1270};
1271
1272static struct clk_branch cam_cc_fd_core_clk = {
1273	.halt_reg = 0xc0f8,
1274	.halt_check = BRANCH_HALT,
1275	.clkr = {
1276		.enable_reg = 0xc0f8,
1277		.enable_mask = BIT(0),
1278		.hw.init = &(const struct clk_init_data) {
1279			.name = "cam_cc_fd_core_clk",
1280			.parent_hws = (const struct clk_hw*[]) {
1281				&cam_cc_fd_core_clk_src.clkr.hw,
1282			},
1283			.num_parents = 1,
1284			.flags = CLK_SET_RATE_PARENT,
1285			.ops = &clk_branch2_ops,
1286		},
1287	},
1288};
1289
1290static struct clk_branch cam_cc_fd_core_uar_clk = {
1291	.halt_reg = 0xc100,
1292	.halt_check = BRANCH_HALT,
1293	.clkr = {
1294		.enable_reg = 0xc100,
1295		.enable_mask = BIT(0),
1296		.hw.init = &(const struct clk_init_data) {
1297			.name = "cam_cc_fd_core_uar_clk",
1298			.parent_hws = (const struct clk_hw*[]) {
1299				&cam_cc_fd_core_clk_src.clkr.hw,
1300			},
1301			.num_parents = 1,
1302			.flags = CLK_SET_RATE_PARENT,
1303			.ops = &clk_branch2_ops,
1304		},
1305	},
1306};
1307
1308static struct clk_branch cam_cc_icp_ahb_clk = {
1309	.halt_reg = 0xc0d8,
1310	.halt_check = BRANCH_HALT,
1311	.clkr = {
1312		.enable_reg = 0xc0d8,
1313		.enable_mask = BIT(0),
1314		.hw.init = &(const struct clk_init_data) {
1315			.name = "cam_cc_icp_ahb_clk",
1316			.parent_hws = (const struct clk_hw*[]) {
1317				&cam_cc_slow_ahb_clk_src.clkr.hw,
1318			},
1319			.num_parents = 1,
1320			.flags = CLK_SET_RATE_PARENT,
1321			.ops = &clk_branch2_ops,
1322		},
1323	},
1324};
1325
1326static struct clk_branch cam_cc_icp_clk = {
1327	.halt_reg = 0xc0d0,
1328	.halt_check = BRANCH_HALT,
1329	.clkr = {
1330		.enable_reg = 0xc0d0,
1331		.enable_mask = BIT(0),
1332		.hw.init = &(const struct clk_init_data) {
1333			.name = "cam_cc_icp_clk",
1334			.parent_hws = (const struct clk_hw*[]) {
1335				&cam_cc_icp_clk_src.clkr.hw,
1336			},
1337			.num_parents = 1,
1338			.flags = CLK_SET_RATE_PARENT,
1339			.ops = &clk_branch2_ops,
1340		},
1341	},
1342};
1343
1344static struct clk_branch cam_cc_ife_0_axi_clk = {
1345	.halt_reg = 0xa080,
1346	.halt_check = BRANCH_HALT,
1347	.clkr = {
1348		.enable_reg = 0xa080,
1349		.enable_mask = BIT(0),
1350		.hw.init = &(const struct clk_init_data) {
1351			.name = "cam_cc_ife_0_axi_clk",
1352			.parent_hws = (const struct clk_hw*[]) {
1353				&cam_cc_camnoc_axi_clk_src.clkr.hw,
1354			},
1355			.num_parents = 1,
1356			.flags = CLK_SET_RATE_PARENT,
1357			.ops = &clk_branch2_ops,
1358		},
1359	},
1360};
1361
1362static struct clk_branch cam_cc_ife_0_clk = {
1363	.halt_reg = 0xa028,
1364	.halt_check = BRANCH_HALT,
1365	.clkr = {
1366		.enable_reg = 0xa028,
1367		.enable_mask = BIT(0),
1368		.hw.init = &(const struct clk_init_data) {
1369			.name = "cam_cc_ife_0_clk",
1370			.parent_hws = (const struct clk_hw*[]) {
1371				&cam_cc_ife_0_clk_src.clkr.hw,
1372			},
1373			.num_parents = 1,
1374			.flags = CLK_SET_RATE_PARENT,
1375			.ops = &clk_branch2_ops,
1376		},
1377	},
1378};
1379
1380static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
1381	.halt_reg = 0xa07c,
1382	.halt_check = BRANCH_HALT,
1383	.clkr = {
1384		.enable_reg = 0xa07c,
1385		.enable_mask = BIT(0),
1386		.hw.init = &(const struct clk_init_data) {
1387			.name = "cam_cc_ife_0_cphy_rx_clk",
1388			.parent_hws = (const struct clk_hw*[]) {
1389				&cam_cc_cphy_rx_clk_src.clkr.hw,
1390			},
1391			.num_parents = 1,
1392			.flags = CLK_SET_RATE_PARENT,
1393			.ops = &clk_branch2_ops,
1394		},
1395	},
1396};
1397
1398static struct clk_branch cam_cc_ife_0_csid_clk = {
1399	.halt_reg = 0xa054,
1400	.halt_check = BRANCH_HALT,
1401	.clkr = {
1402		.enable_reg = 0xa054,
1403		.enable_mask = BIT(0),
1404		.hw.init = &(const struct clk_init_data) {
1405			.name = "cam_cc_ife_0_csid_clk",
1406			.parent_hws = (const struct clk_hw*[]) {
1407				&cam_cc_ife_0_csid_clk_src.clkr.hw,
1408			},
1409			.num_parents = 1,
1410			.flags = CLK_SET_RATE_PARENT,
1411			.ops = &clk_branch2_ops,
1412		},
1413	},
1414};
1415
1416static struct clk_branch cam_cc_ife_0_dsp_clk = {
1417	.halt_reg = 0xa038,
1418	.halt_check = BRANCH_HALT,
1419	.clkr = {
1420		.enable_reg = 0xa038,
1421		.enable_mask = BIT(0),
1422		.hw.init = &(const struct clk_init_data) {
1423			.name = "cam_cc_ife_0_dsp_clk",
1424			.parent_hws = (const struct clk_hw*[]) {
1425				&cam_cc_ife_0_clk_src.clkr.hw,
1426			},
1427			.num_parents = 1,
1428			.flags = CLK_SET_RATE_PARENT,
1429			.ops = &clk_branch2_ops,
1430		},
1431	},
1432};
1433
1434static struct clk_branch cam_cc_ife_1_axi_clk = {
1435	.halt_reg = 0xb058,
1436	.halt_check = BRANCH_HALT,
1437	.clkr = {
1438		.enable_reg = 0xb058,
1439		.enable_mask = BIT(0),
1440		.hw.init = &(const struct clk_init_data) {
1441			.name = "cam_cc_ife_1_axi_clk",
1442			.parent_hws = (const struct clk_hw*[]) {
1443				&cam_cc_camnoc_axi_clk_src.clkr.hw,
1444			},
1445			.num_parents = 1,
1446			.flags = CLK_SET_RATE_PARENT,
1447			.ops = &clk_branch2_ops,
1448		},
1449	},
1450};
1451
1452static struct clk_branch cam_cc_ife_1_clk = {
1453	.halt_reg = 0xb028,
1454	.halt_check = BRANCH_HALT,
1455	.clkr = {
1456		.enable_reg = 0xb028,
1457		.enable_mask = BIT(0),
1458		.hw.init = &(const struct clk_init_data) {
1459			.name = "cam_cc_ife_1_clk",
1460			.parent_hws = (const struct clk_hw*[]) {
1461				&cam_cc_ife_1_clk_src.clkr.hw,
1462			},
1463			.num_parents = 1,
1464			.flags = CLK_SET_RATE_PARENT,
1465			.ops = &clk_branch2_ops,
1466		},
1467	},
1468};
1469
1470static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
1471	.halt_reg = 0xb054,
1472	.halt_check = BRANCH_HALT,
1473	.clkr = {
1474		.enable_reg = 0xb054,
1475		.enable_mask = BIT(0),
1476		.hw.init = &(const struct clk_init_data) {
1477			.name = "cam_cc_ife_1_cphy_rx_clk",
1478			.parent_hws = (const struct clk_hw*[]) {
1479				&cam_cc_cphy_rx_clk_src.clkr.hw,
1480			},
1481			.num_parents = 1,
1482			.flags = CLK_SET_RATE_PARENT,
1483			.ops = &clk_branch2_ops,
1484		},
1485	},
1486};
1487
1488static struct clk_branch cam_cc_ife_1_csid_clk = {
1489	.halt_reg = 0xb04c,
1490	.halt_check = BRANCH_HALT,
1491	.clkr = {
1492		.enable_reg = 0xb04c,
1493		.enable_mask = BIT(0),
1494		.hw.init = &(const struct clk_init_data) {
1495			.name = "cam_cc_ife_1_csid_clk",
1496			.parent_hws = (const struct clk_hw*[]) {
1497				&cam_cc_ife_1_csid_clk_src.clkr.hw,
1498			},
1499			.num_parents = 1,
1500			.flags = CLK_SET_RATE_PARENT,
1501			.ops = &clk_branch2_ops,
1502		},
1503	},
1504};
1505
1506static struct clk_branch cam_cc_ife_1_dsp_clk = {
1507	.halt_reg = 0xb030,
1508	.halt_check = BRANCH_HALT,
1509	.clkr = {
1510		.enable_reg = 0xb030,
1511		.enable_mask = BIT(0),
1512		.hw.init = &(const struct clk_init_data) {
1513			.name = "cam_cc_ife_1_dsp_clk",
1514			.parent_hws = (const struct clk_hw*[]) {
1515				&cam_cc_ife_1_clk_src.clkr.hw,
1516			},
1517			.num_parents = 1,
1518			.flags = CLK_SET_RATE_PARENT,
1519			.ops = &clk_branch2_ops,
1520		},
1521	},
1522};
1523
1524static struct clk_branch cam_cc_ife_lite_0_clk = {
1525	.halt_reg = 0xc01c,
1526	.halt_check = BRANCH_HALT,
1527	.clkr = {
1528		.enable_reg = 0xc01c,
1529		.enable_mask = BIT(0),
1530		.hw.init = &(const struct clk_init_data) {
1531			.name = "cam_cc_ife_lite_0_clk",
1532			.parent_hws = (const struct clk_hw*[]) {
1533				&cam_cc_ife_lite_0_clk_src.clkr.hw,
1534			},
1535			.num_parents = 1,
1536			.flags = CLK_SET_RATE_PARENT,
1537			.ops = &clk_branch2_ops,
1538		},
1539	},
1540};
1541
1542static struct clk_branch cam_cc_ife_lite_0_cphy_rx_clk = {
1543	.halt_reg = 0xc040,
1544	.halt_check = BRANCH_HALT,
1545	.clkr = {
1546		.enable_reg = 0xc040,
1547		.enable_mask = BIT(0),
1548		.hw.init = &(const struct clk_init_data) {
1549			.name = "cam_cc_ife_lite_0_cphy_rx_clk",
1550			.parent_hws = (const struct clk_hw*[]) {
1551				&cam_cc_cphy_rx_clk_src.clkr.hw,
1552			},
1553			.num_parents = 1,
1554			.flags = CLK_SET_RATE_PARENT,
1555			.ops = &clk_branch2_ops,
1556		},
1557	},
1558};
1559
1560static struct clk_branch cam_cc_ife_lite_0_csid_clk = {
1561	.halt_reg = 0xc038,
1562	.halt_check = BRANCH_HALT,
1563	.clkr = {
1564		.enable_reg = 0xc038,
1565		.enable_mask = BIT(0),
1566		.hw.init = &(const struct clk_init_data) {
1567			.name = "cam_cc_ife_lite_0_csid_clk",
1568			.parent_hws = (const struct clk_hw*[]) {
1569				&cam_cc_ife_lite_0_csid_clk_src.clkr.hw,
1570			},
1571			.num_parents = 1,
1572			.flags = CLK_SET_RATE_PARENT,
1573			.ops = &clk_branch2_ops,
1574		},
1575	},
1576};
1577
1578static struct clk_branch cam_cc_ife_lite_1_clk = {
1579	.halt_reg = 0xc060,
1580	.halt_check = BRANCH_HALT,
1581	.clkr = {
1582		.enable_reg = 0xc060,
1583		.enable_mask = BIT(0),
1584		.hw.init = &(const struct clk_init_data) {
1585			.name = "cam_cc_ife_lite_1_clk",
1586			.parent_hws = (const struct clk_hw*[]) {
1587				&cam_cc_ife_lite_1_clk_src.clkr.hw,
1588			},
1589			.num_parents = 1,
1590			.flags = CLK_SET_RATE_PARENT,
1591			.ops = &clk_branch2_ops,
1592		},
1593	},
1594};
1595
1596static struct clk_branch cam_cc_ife_lite_1_cphy_rx_clk = {
1597	.halt_reg = 0xc084,
1598	.halt_check = BRANCH_HALT,
1599	.clkr = {
1600		.enable_reg = 0xc084,
1601		.enable_mask = BIT(0),
1602		.hw.init = &(const struct clk_init_data) {
1603			.name = "cam_cc_ife_lite_1_cphy_rx_clk",
1604			.parent_hws = (const struct clk_hw*[]) {
1605				&cam_cc_cphy_rx_clk_src.clkr.hw,
1606			},
1607			.num_parents = 1,
1608			.flags = CLK_SET_RATE_PARENT,
1609			.ops = &clk_branch2_ops,
1610		},
1611	},
1612};
1613
1614static struct clk_branch cam_cc_ife_lite_1_csid_clk = {
1615	.halt_reg = 0xc07c,
1616	.halt_check = BRANCH_HALT,
1617	.clkr = {
1618		.enable_reg = 0xc07c,
1619		.enable_mask = BIT(0),
1620		.hw.init = &(const struct clk_init_data) {
1621			.name = "cam_cc_ife_lite_1_csid_clk",
1622			.parent_hws = (const struct clk_hw*[]) {
1623				&cam_cc_ife_lite_1_csid_clk_src.clkr.hw,
1624			},
1625			.num_parents = 1,
1626			.flags = CLK_SET_RATE_PARENT,
1627			.ops = &clk_branch2_ops,
1628		},
1629	},
1630};
1631
1632static struct clk_branch cam_cc_ipe_0_ahb_clk = {
1633	.halt_reg = 0x8040,
1634	.halt_check = BRANCH_HALT,
1635	.clkr = {
1636		.enable_reg = 0x8040,
1637		.enable_mask = BIT(0),
1638		.hw.init = &(const struct clk_init_data) {
1639			.name = "cam_cc_ipe_0_ahb_clk",
1640			.parent_hws = (const struct clk_hw*[]) {
1641				&cam_cc_slow_ahb_clk_src.clkr.hw,
1642			},
1643			.num_parents = 1,
1644			.flags = CLK_SET_RATE_PARENT,
1645			.ops = &clk_branch2_ops,
1646		},
1647	},
1648};
1649
1650static struct clk_branch cam_cc_ipe_0_areg_clk = {
1651	.halt_reg = 0x803c,
1652	.halt_check = BRANCH_HALT,
1653	.clkr = {
1654		.enable_reg = 0x803c,
1655		.enable_mask = BIT(0),
1656		.hw.init = &(const struct clk_init_data) {
1657			.name = "cam_cc_ipe_0_areg_clk",
1658			.parent_hws = (const struct clk_hw*[]) {
1659				&cam_cc_fast_ahb_clk_src.clkr.hw,
1660			},
1661			.num_parents = 1,
1662			.flags = CLK_SET_RATE_PARENT,
1663			.ops = &clk_branch2_ops,
1664		},
1665	},
1666};
1667
1668static struct clk_branch cam_cc_ipe_0_axi_clk = {
1669	.halt_reg = 0x8038,
1670	.halt_check = BRANCH_HALT,
1671	.clkr = {
1672		.enable_reg = 0x8038,
1673		.enable_mask = BIT(0),
1674		.hw.init = &(const struct clk_init_data) {
1675			.name = "cam_cc_ipe_0_axi_clk",
1676			.parent_hws = (const struct clk_hw*[]) {
1677				&cam_cc_camnoc_axi_clk_src.clkr.hw,
1678			},
1679			.num_parents = 1,
1680			.flags = CLK_SET_RATE_PARENT,
1681			.ops = &clk_branch2_ops,
1682		},
1683	},
1684};
1685
1686static struct clk_branch cam_cc_ipe_0_clk = {
1687	.halt_reg = 0x8028,
1688	.halt_check = BRANCH_HALT,
1689	.clkr = {
1690		.enable_reg = 0x8028,
1691		.enable_mask = BIT(0),
1692		.hw.init = &(const struct clk_init_data) {
1693			.name = "cam_cc_ipe_0_clk",
1694			.parent_hws = (const struct clk_hw*[]) {
1695				&cam_cc_ipe_0_clk_src.clkr.hw,
1696			},
1697			.num_parents = 1,
1698			.flags = CLK_SET_RATE_PARENT,
1699			.ops = &clk_branch2_ops,
1700		},
1701	},
1702};
1703
1704static struct clk_branch cam_cc_ipe_1_ahb_clk = {
1705	.halt_reg = 0x9028,
1706	.halt_check = BRANCH_HALT,
1707	.clkr = {
1708		.enable_reg = 0x9028,
1709		.enable_mask = BIT(0),
1710		.hw.init = &(const struct clk_init_data) {
1711			.name = "cam_cc_ipe_1_ahb_clk",
1712			.parent_hws = (const struct clk_hw*[]) {
1713				&cam_cc_slow_ahb_clk_src.clkr.hw,
1714			},
1715			.num_parents = 1,
1716			.flags = CLK_SET_RATE_PARENT,
1717			.ops = &clk_branch2_ops,
1718		},
1719	},
1720};
1721
1722static struct clk_branch cam_cc_ipe_1_areg_clk = {
1723	.halt_reg = 0x9024,
1724	.halt_check = BRANCH_HALT,
1725	.clkr = {
1726		.enable_reg = 0x9024,
1727		.enable_mask = BIT(0),
1728		.hw.init = &(const struct clk_init_data) {
1729			.name = "cam_cc_ipe_1_areg_clk",
1730			.parent_hws = (const struct clk_hw*[]) {
1731				&cam_cc_fast_ahb_clk_src.clkr.hw,
1732			},
1733			.num_parents = 1,
1734			.flags = CLK_SET_RATE_PARENT,
1735			.ops = &clk_branch2_ops,
1736		},
1737	},
1738};
1739
1740static struct clk_branch cam_cc_ipe_1_axi_clk = {
1741	.halt_reg = 0x9020,
1742	.halt_check = BRANCH_HALT,
1743	.clkr = {
1744		.enable_reg = 0x9020,
1745		.enable_mask = BIT(0),
1746		.hw.init = &(const struct clk_init_data) {
1747			.name = "cam_cc_ipe_1_axi_clk",
1748			.parent_hws = (const struct clk_hw*[]) {
1749				&cam_cc_camnoc_axi_clk_src.clkr.hw,
1750			},
1751			.num_parents = 1,
1752			.flags = CLK_SET_RATE_PARENT,
1753			.ops = &clk_branch2_ops,
1754		},
1755	},
1756};
1757
1758static struct clk_branch cam_cc_ipe_1_clk = {
1759	.halt_reg = 0x9010,
1760	.halt_check = BRANCH_HALT,
1761	.clkr = {
1762		.enable_reg = 0x9010,
1763		.enable_mask = BIT(0),
1764		.hw.init = &(const struct clk_init_data) {
1765			.name = "cam_cc_ipe_1_clk",
1766			.parent_hws = (const struct clk_hw*[]) {
1767				&cam_cc_ipe_0_clk_src.clkr.hw,
1768			},
1769			.num_parents = 1,
1770			.flags = CLK_SET_RATE_PARENT,
1771			.ops = &clk_branch2_ops,
1772		},
1773	},
1774};
1775
1776static struct clk_branch cam_cc_jpeg_clk = {
1777	.halt_reg = 0xc0a4,
1778	.halt_check = BRANCH_HALT,
1779	.clkr = {
1780		.enable_reg = 0xc0a4,
1781		.enable_mask = BIT(0),
1782		.hw.init = &(const struct clk_init_data) {
1783			.name = "cam_cc_jpeg_clk",
1784			.parent_hws = (const struct clk_hw*[]) {
1785				&cam_cc_jpeg_clk_src.clkr.hw,
1786			},
1787			.num_parents = 1,
1788			.flags = CLK_SET_RATE_PARENT,
1789			.ops = &clk_branch2_ops,
1790		},
1791	},
1792};
1793
1794static struct clk_branch cam_cc_lrme_clk = {
1795	.halt_reg = 0xc15c,
1796	.halt_check = BRANCH_HALT,
1797	.clkr = {
1798		.enable_reg = 0xc15c,
1799		.enable_mask = BIT(0),
1800		.hw.init = &(const struct clk_init_data) {
1801			.name = "cam_cc_lrme_clk",
1802			.parent_hws = (const struct clk_hw*[]) {
1803				&cam_cc_lrme_clk_src.clkr.hw,
1804			},
1805			.num_parents = 1,
1806			.flags = CLK_SET_RATE_PARENT,
1807			.ops = &clk_branch2_ops,
1808		},
1809	},
1810};
1811
1812static struct clk_branch cam_cc_mclk0_clk = {
1813	.halt_reg = 0x501c,
1814	.halt_check = BRANCH_HALT,
1815	.clkr = {
1816		.enable_reg = 0x501c,
1817		.enable_mask = BIT(0),
1818		.hw.init = &(const struct clk_init_data) {
1819			.name = "cam_cc_mclk0_clk",
1820			.parent_hws = (const struct clk_hw*[]) {
1821				&cam_cc_mclk0_clk_src.clkr.hw,
1822			},
1823			.num_parents = 1,
1824			.flags = CLK_SET_RATE_PARENT,
1825			.ops = &clk_branch2_ops,
1826		},
1827	},
1828};
1829
1830static struct clk_branch cam_cc_mclk1_clk = {
1831	.halt_reg = 0x503c,
1832	.halt_check = BRANCH_HALT,
1833	.clkr = {
1834		.enable_reg = 0x503c,
1835		.enable_mask = BIT(0),
1836		.hw.init = &(const struct clk_init_data) {
1837			.name = "cam_cc_mclk1_clk",
1838			.parent_hws = (const struct clk_hw*[]) {
1839				&cam_cc_mclk1_clk_src.clkr.hw,
1840			},
1841			.num_parents = 1,
1842			.flags = CLK_SET_RATE_PARENT,
1843			.ops = &clk_branch2_ops,
1844		},
1845	},
1846};
1847
1848static struct clk_branch cam_cc_mclk2_clk = {
1849	.halt_reg = 0x505c,
1850	.halt_check = BRANCH_HALT,
1851	.clkr = {
1852		.enable_reg = 0x505c,
1853		.enable_mask = BIT(0),
1854		.hw.init = &(const struct clk_init_data) {
1855			.name = "cam_cc_mclk2_clk",
1856			.parent_hws = (const struct clk_hw*[]) {
1857				&cam_cc_mclk2_clk_src.clkr.hw,
1858			},
1859			.num_parents = 1,
1860			.flags = CLK_SET_RATE_PARENT,
1861			.ops = &clk_branch2_ops,
1862		},
1863	},
1864};
1865
1866static struct clk_branch cam_cc_mclk3_clk = {
1867	.halt_reg = 0x507c,
1868	.halt_check = BRANCH_HALT,
1869	.clkr = {
1870		.enable_reg = 0x507c,
1871		.enable_mask = BIT(0),
1872		.hw.init = &(const struct clk_init_data) {
1873			.name = "cam_cc_mclk3_clk",
1874			.parent_hws = (const struct clk_hw*[]) {
1875				&cam_cc_mclk3_clk_src.clkr.hw,
1876			},
1877			.num_parents = 1,
1878			.flags = CLK_SET_RATE_PARENT,
1879			.ops = &clk_branch2_ops,
1880		},
1881	},
1882};
1883
1884static struct gdsc titan_top_gdsc = {
1885	.gdscr = 0xc1bc,
1886	.en_rest_wait_val = 0x2,
1887	.en_few_wait_val = 0x2,
1888	.clk_dis_wait_val = 0xf,
1889	.pd = {
1890		.name = "titan_top_gdsc",
1891	},
1892	.pwrsts = PWRSTS_OFF_ON,
1893	.flags = POLL_CFG_GDSCR,
1894};
1895
1896static struct gdsc bps_gdsc = {
1897	.gdscr = 0x7004,
1898	.en_rest_wait_val = 0x2,
1899	.en_few_wait_val = 0x2,
1900	.clk_dis_wait_val = 0xf,
1901	.pd = {
1902		.name = "bps_gdsc",
1903	},
1904	.pwrsts = PWRSTS_OFF_ON,
1905	.parent = &titan_top_gdsc.pd,
1906	.flags = POLL_CFG_GDSCR,
1907};
1908
1909static struct gdsc ife_0_gdsc = {
1910	.gdscr = 0xa004,
1911	.en_rest_wait_val = 0x2,
1912	.en_few_wait_val = 0x2,
1913	.clk_dis_wait_val = 0xf,
1914	.pd = {
1915		.name = "ife_0_gdsc",
1916	},
1917	.pwrsts = PWRSTS_OFF_ON,
1918	.parent = &titan_top_gdsc.pd,
1919	.flags = POLL_CFG_GDSCR,
1920};
1921
1922static struct gdsc ife_1_gdsc = {
1923	.gdscr = 0xb004,
1924	.en_rest_wait_val = 0x2,
1925	.en_few_wait_val = 0x2,
1926	.clk_dis_wait_val = 0xf,
1927	.pd = {
1928		.name = "ife_1_gdsc",
1929	},
1930	.pwrsts = PWRSTS_OFF_ON,
1931	.parent = &titan_top_gdsc.pd,
1932	.flags = POLL_CFG_GDSCR,
1933};
1934
1935static struct gdsc ipe_0_gdsc = {
1936	.gdscr = 0x8004,
1937	.en_rest_wait_val = 0x2,
1938	.en_few_wait_val = 0x2,
1939	.clk_dis_wait_val = 0xf,
1940	.pd = {
1941		.name = "ipe_0_gdsc",
1942	},
1943	.pwrsts = PWRSTS_OFF_ON,
1944	.parent = &titan_top_gdsc.pd,
1945	.flags = POLL_CFG_GDSCR,
1946};
1947
1948static struct gdsc ipe_1_gdsc = {
1949	.gdscr = 0x9004,
1950	.en_rest_wait_val = 0x2,
1951	.en_few_wait_val = 0x2,
1952	.clk_dis_wait_val = 0xf,
1953	.pd = {
1954		.name = "ipe_1_gdsc",
1955	},
1956	.pwrsts = PWRSTS_OFF_ON,
1957	.parent = &titan_top_gdsc.pd,
1958	.flags = POLL_CFG_GDSCR,
1959};
1960
1961static struct clk_regmap *cam_cc_sm8150_clocks[] = {
1962	[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
1963	[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
1964	[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
1965	[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
1966	[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
1967	[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
1968	[CAM_CC_PLL2_OUT_MAIN] = &cam_cc_pll2_out_main.clkr,
1969	[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
1970	[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
1971	[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
1972	[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
1973	[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
1974	[CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
1975	[CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
1976	[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
1977	[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
1978	[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
1979	[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
1980	[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
1981	[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
1982	[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
1983	[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
1984	[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
1985	[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
1986	[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
1987	[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
1988	[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
1989	[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
1990	[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
1991	[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
1992	[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
1993	[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
1994	[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
1995	[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
1996	[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
1997	[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
1998	[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
1999	[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
2000	[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
2001	[CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr,
2002	[CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr,
2003	[CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr,
2004	[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
2005	[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
2006	[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
2007	[CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
2008	[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
2009	[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
2010	[CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
2011	[CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
2012	[CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
2013	[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
2014	[CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
2015	[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
2016	[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
2017	[CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
2018	[CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
2019	[CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
2020	[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
2021	[CAM_CC_IFE_LITE_0_CLK] = &cam_cc_ife_lite_0_clk.clkr,
2022	[CAM_CC_IFE_LITE_0_CLK_SRC] = &cam_cc_ife_lite_0_clk_src.clkr,
2023	[CAM_CC_IFE_LITE_0_CPHY_RX_CLK] = &cam_cc_ife_lite_0_cphy_rx_clk.clkr,
2024	[CAM_CC_IFE_LITE_0_CSID_CLK] = &cam_cc_ife_lite_0_csid_clk.clkr,
2025	[CAM_CC_IFE_LITE_0_CSID_CLK_SRC] = &cam_cc_ife_lite_0_csid_clk_src.clkr,
2026	[CAM_CC_IFE_LITE_1_CLK] = &cam_cc_ife_lite_1_clk.clkr,
2027	[CAM_CC_IFE_LITE_1_CLK_SRC] = &cam_cc_ife_lite_1_clk_src.clkr,
2028	[CAM_CC_IFE_LITE_1_CPHY_RX_CLK] = &cam_cc_ife_lite_1_cphy_rx_clk.clkr,
2029	[CAM_CC_IFE_LITE_1_CSID_CLK] = &cam_cc_ife_lite_1_csid_clk.clkr,
2030	[CAM_CC_IFE_LITE_1_CSID_CLK_SRC] = &cam_cc_ife_lite_1_csid_clk_src.clkr,
2031	[CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
2032	[CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
2033	[CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
2034	[CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
2035	[CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
2036	[CAM_CC_IPE_1_AHB_CLK] = &cam_cc_ipe_1_ahb_clk.clkr,
2037	[CAM_CC_IPE_1_AREG_CLK] = &cam_cc_ipe_1_areg_clk.clkr,
2038	[CAM_CC_IPE_1_AXI_CLK] = &cam_cc_ipe_1_axi_clk.clkr,
2039	[CAM_CC_IPE_1_CLK] = &cam_cc_ipe_1_clk.clkr,
2040	[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
2041	[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
2042	[CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr,
2043	[CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr,
2044	[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
2045	[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
2046	[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
2047	[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
2048	[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
2049	[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
2050	[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
2051	[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
2052	[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
2053};
2054
2055static struct gdsc *cam_cc_sm8150_gdscs[] = {
2056	[TITAN_TOP_GDSC] = &titan_top_gdsc,
2057	[BPS_GDSC] = &bps_gdsc,
2058	[IFE_0_GDSC] = &ife_0_gdsc,
2059	[IFE_1_GDSC] = &ife_1_gdsc,
2060	[IPE_0_GDSC] = &ipe_0_gdsc,
2061	[IPE_1_GDSC] = &ipe_1_gdsc,
2062};
2063
2064static const struct qcom_reset_map cam_cc_sm8150_resets[] = {
2065	[CAM_CC_BPS_BCR] = { 0x7000 },
2066	[CAM_CC_CAMNOC_BCR] = { 0xc16c },
2067	[CAM_CC_CCI_BCR] = { 0xc104 },
2068	[CAM_CC_CPAS_BCR] = { 0xc164 },
2069	[CAM_CC_CSI0PHY_BCR] = { 0x6000 },
2070	[CAM_CC_CSI1PHY_BCR] = { 0x6024 },
2071	[CAM_CC_CSI2PHY_BCR] = { 0x6048 },
2072	[CAM_CC_CSI3PHY_BCR] = { 0x606c },
2073	[CAM_CC_FD_BCR] = { 0xc0dc },
2074	[CAM_CC_ICP_BCR] = { 0xc0b4 },
2075	[CAM_CC_IFE_0_BCR] = { 0xa000 },
2076	[CAM_CC_IFE_1_BCR] = { 0xb000 },
2077	[CAM_CC_IFE_LITE_0_BCR] = { 0xc000 },
2078	[CAM_CC_IFE_LITE_1_BCR] = { 0xc044 },
2079	[CAM_CC_IPE_0_BCR] = { 0x8000 },
2080	[CAM_CC_IPE_1_BCR] = { 0x9000 },
2081	[CAM_CC_JPEG_BCR] = { 0xc088 },
2082	[CAM_CC_LRME_BCR] = { 0xc140 },
2083	[CAM_CC_MCLK0_BCR] = { 0x5000 },
2084	[CAM_CC_MCLK1_BCR] = { 0x5020 },
2085	[CAM_CC_MCLK2_BCR] = { 0x5040 },
2086	[CAM_CC_MCLK3_BCR] = { 0x5060 },
2087};
2088
2089static const struct regmap_config cam_cc_sm8150_regmap_config = {
2090	.reg_bits = 32,
2091	.reg_stride = 4,
2092	.val_bits = 32,
2093	.max_register = 0xe004,
2094	.fast_io = true,
2095};
2096
2097static const struct qcom_cc_desc cam_cc_sm8150_desc = {
2098	.config = &cam_cc_sm8150_regmap_config,
2099	.clks = cam_cc_sm8150_clocks,
2100	.num_clks = ARRAY_SIZE(cam_cc_sm8150_clocks),
2101	.resets = cam_cc_sm8150_resets,
2102	.num_resets = ARRAY_SIZE(cam_cc_sm8150_resets),
2103	.gdscs = cam_cc_sm8150_gdscs,
2104	.num_gdscs = ARRAY_SIZE(cam_cc_sm8150_gdscs),
2105};
2106
2107static const struct of_device_id cam_cc_sm8150_match_table[] = {
2108	{ .compatible = "qcom,sm8150-camcc" },
2109	{ }
2110};
2111MODULE_DEVICE_TABLE(of, cam_cc_sm8150_match_table);
2112
2113static int cam_cc_sm8150_probe(struct platform_device *pdev)
2114{
2115	struct regmap *regmap;
2116	int ret;
2117
2118	ret = devm_pm_runtime_enable(&pdev->dev);
2119	if (ret)
2120		return ret;
2121
2122	ret = pm_runtime_resume_and_get(&pdev->dev);
2123	if (ret)
2124		return ret;
2125
2126	regmap = qcom_cc_map(pdev, &cam_cc_sm8150_desc);
2127	if (IS_ERR(regmap)) {
2128		pm_runtime_put(&pdev->dev);
2129		return PTR_ERR(regmap);
2130	}
2131
2132	clk_trion_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
2133	clk_trion_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
2134	clk_regera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
2135	clk_trion_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
2136	clk_trion_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
2137
2138	/* Keep the critical clock always-on */
2139	qcom_branch_set_clk_en(regmap, 0xc1e4); /* cam_cc_gdsc_clk */
2140
2141	ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8150_desc, regmap);
2142
2143	pm_runtime_put(&pdev->dev);
2144
2145	return ret;
2146}
2147
2148static struct platform_driver cam_cc_sm8150_driver = {
2149	.probe = cam_cc_sm8150_probe,
2150	.driver = {
2151		.name = "camcc-sm8150",
2152		.of_match_table = cam_cc_sm8150_match_table,
2153	},
2154};
2155
2156module_platform_driver(cam_cc_sm8150_driver);
2157
2158MODULE_DESCRIPTION("QTI CAM_CC SM8150 Driver");
2159MODULE_LICENSE("GPL");