camcc-sm7150.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
   5 */
   6
   7#include <linux/clk-provider.h>
   8#include <linux/mod_devicetable.h>
   9#include <linux/module.h>
  10#include <linux/platform_device.h>
  11#include <linux/regmap.h>
  12
  13#include <dt-bindings/clock/qcom,sm7150-camcc.h>
  14
  15#include "clk-alpha-pll.h"
  16#include "clk-branch.h"
  17#include "clk-rcg.h"
  18#include "clk-regmap.h"
  19#include "common.h"
  20#include "gdsc.h"
  21
  22enum {
  23	DT_BI_TCXO,
  24	DT_BI_TCXO_AO,
  25	DT_CHIP_SLEEP_CLK,
  26};
  27
  28enum {
  29	P_BI_TCXO,
  30	P_BI_TCXO_MX,
  31	P_CAMCC_PLL0_OUT_EVEN,
  32	P_CAMCC_PLL0_OUT_MAIN,
  33	P_CAMCC_PLL0_OUT_ODD,
  34	P_CAMCC_PLL1_OUT_EVEN,
  35	P_CAMCC_PLL2_OUT_AUX,
  36	P_CAMCC_PLL2_OUT_EARLY,
  37	P_CAMCC_PLL2_OUT_MAIN,
  38	P_CAMCC_PLL3_OUT_EVEN,
  39	P_CAMCC_PLL4_OUT_EVEN,
  40	P_CHIP_SLEEP_CLK,
  41};
  42
  43static const struct pll_vco fabia_vco[] = {
  44	{ 249600000, 2000000000, 0 },
  45};
  46
  47/* 1200MHz configuration */
  48static const struct alpha_pll_config camcc_pll0_config = {
  49	.l = 0x3e,
  50	.alpha = 0x8000,
  51	.post_div_mask = 0xff << 8,
  52	.post_div_val = 0x31 << 8,
  53	.test_ctl_val = 0x40000000,
  54};
  55
  56static struct clk_alpha_pll camcc_pll0 = {
  57	.offset = 0x0,
  58	.vco_table = fabia_vco,
  59	.num_vco = ARRAY_SIZE(fabia_vco),
  60	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  61	.clkr = {
  62		.hw.init = &(const struct clk_init_data) {
  63			.name = "camcc_pll0",
  64			.parent_data = &(const struct clk_parent_data) {
  65				.index = DT_BI_TCXO,
  66			},
  67			.num_parents = 1,
  68			.ops = &clk_alpha_pll_fabia_ops,
  69		},
  70	},
  71};
  72
  73static struct clk_fixed_factor camcc_pll0_out_even = {
  74	.mult = 1,
  75	.div = 2,
  76	.hw.init = &(const struct clk_init_data) {
  77		.name = "camcc_pll0_out_even",
  78		.parent_hws = (const struct clk_hw*[]) {
  79			&camcc_pll0.clkr.hw,
  80		},
  81		.num_parents = 1,
  82		.ops = &clk_fixed_factor_ops,
  83	},
  84};
  85
  86static struct clk_fixed_factor camcc_pll0_out_odd = {
  87	.mult = 1,
  88	.div = 3,
  89	.hw.init = &(const struct clk_init_data) {
  90		.name = "camcc_pll0_out_odd",
  91		.parent_hws = (const struct clk_hw*[]) {
  92			&camcc_pll0.clkr.hw,
  93		},
  94		.num_parents = 1,
  95		.ops = &clk_fixed_factor_ops,
  96	},
  97};
  98
  99/* 680MHz configuration */
 100static const struct alpha_pll_config camcc_pll1_config = {
 101	.l = 0x23,
 102	.alpha = 0x6aaa,
 103	.post_div_mask = 0xf << 8,
 104	.post_div_val = 0x1 << 8,
 105	.test_ctl_val = 0x40000000,
 106};
 107
 108static struct clk_alpha_pll camcc_pll1 = {
 109	.offset = 0x1000,
 110	.vco_table = fabia_vco,
 111	.num_vco = ARRAY_SIZE(fabia_vco),
 112	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 113	.clkr = {
 114		.hw.init = &(const struct clk_init_data) {
 115			.name = "camcc_pll1",
 116			.parent_data = &(const struct clk_parent_data) {
 117				.index = DT_BI_TCXO,
 118			},
 119			.num_parents = 1,
 120			.ops = &clk_alpha_pll_fabia_ops,
 121		},
 122	},
 123};
 124
 125static struct clk_fixed_factor camcc_pll1_out_even = {
 126	.mult = 1,
 127	.div = 2,
 128	.hw.init = &(const struct clk_init_data) {
 129		.name = "camcc_pll1_out_even",
 130		.parent_hws = (const struct clk_hw*[]) {
 131			&camcc_pll1.clkr.hw,
 132		},
 133		.num_parents = 1,
 134		.flags = CLK_SET_RATE_PARENT,
 135		.ops = &clk_fixed_factor_ops,
 136	},
 137};
 138
 139/* 1920MHz configuration */
 140static const struct alpha_pll_config camcc_pll2_config = {
 141	.l = 0x64,
 142	.config_ctl_hi_val = 0x400003d6,
 143	.config_ctl_val = 0x20000954,
 144	.user_ctl_val = 0x0000030b,
 145};
 146
 147static struct clk_alpha_pll camcc_pll2 = {
 148	.offset = 0x2000,
 149	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 150	.clkr = {
 151		.hw.init = &(const struct clk_init_data) {
 152			.name = "camcc_pll2",
 153			.parent_data = &(const struct clk_parent_data) {
 154				.index = DT_BI_TCXO,
 155			},
 156			.num_parents = 1,
 157			.ops = &clk_alpha_pll_agera_ops,
 158		},
 159	},
 160};
 161
 162static struct clk_fixed_factor camcc_pll2_out_early = {
 163	.mult = 1,
 164	.div = 2,
 165	.hw.init = &(const struct clk_init_data) {
 166		.name = "camcc_pll2_out_early",
 167		.parent_hws = (const struct clk_hw*[]) {
 168			&camcc_pll2.clkr.hw,
 169		},
 170		.num_parents = 1,
 171		.ops = &clk_fixed_factor_ops,
 172	},
 173};
 174
 175static struct clk_alpha_pll_postdiv camcc_pll2_out_aux = {
 176	.offset = 0x2000,
 177	.post_div_shift = 8,
 178	.width = 2,
 179	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 180	.clkr.hw.init = &(const struct clk_init_data) {
 181		.name = "camcc_pll2_out_aux",
 182		.parent_hws = (const struct clk_hw*[]) {
 183			&camcc_pll2.clkr.hw,
 184		},
 185		.num_parents = 1,
 186		.flags = CLK_SET_RATE_PARENT,
 187		.ops = &clk_alpha_pll_postdiv_ops,
 188	},
 189};
 190
 191static struct clk_alpha_pll_postdiv camcc_pll2_out_main = {
 192	.offset = 0x2000,
 193	.post_div_shift = 8,
 194	.width = 2,
 195	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 196	.clkr.hw.init = &(const struct clk_init_data) {
 197		.name = "camcc_pll2_out_main",
 198		.parent_hws = (const struct clk_hw*[]) {
 199			&camcc_pll2.clkr.hw,
 200		},
 201		.num_parents = 1,
 202		.flags = CLK_SET_RATE_PARENT,
 203		.ops = &clk_alpha_pll_postdiv_ops,
 204	},
 205};
 206
 207/* 760MHz configuration */
 208static const struct alpha_pll_config camcc_pll3_config = {
 209	.l = 0x27,
 210	.alpha = 0x9555,
 211	.post_div_mask = 0xf << 8,
 212	.post_div_val = 0x1 << 8,
 213	.test_ctl_val = 0x40000000,
 214};
 215
 216static struct clk_alpha_pll camcc_pll3 = {
 217	.offset = 0x3000,
 218	.vco_table = fabia_vco,
 219	.num_vco = ARRAY_SIZE(fabia_vco),
 220	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 221	.clkr = {
 222		.hw.init = &(const struct clk_init_data) {
 223			.name = "camcc_pll3",
 224			.parent_data = &(const struct clk_parent_data) {
 225				.index = DT_BI_TCXO,
 226			},
 227			.num_parents = 1,
 228			.ops = &clk_alpha_pll_fabia_ops,
 229		},
 230	},
 231};
 232
 233static struct clk_fixed_factor camcc_pll3_out_even = {
 234	.mult = 1,
 235	.div = 2,
 236	.hw.init = &(const struct clk_init_data) {
 237		.name = "camcc_pll3_out_even",
 238		.parent_hws = (const struct clk_hw*[]) {
 239			&camcc_pll3.clkr.hw,
 240		},
 241		.num_parents = 1,
 242		.flags = CLK_SET_RATE_PARENT,
 243		.ops = &clk_fixed_factor_ops,
 244	},
 245};
 246
 247static struct clk_alpha_pll camcc_pll4 = {
 248	.offset = 0x4000,
 249	.vco_table = fabia_vco,
 250	.num_vco = ARRAY_SIZE(fabia_vco),
 251	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 252	.clkr = {
 253		.hw.init = &(const struct clk_init_data) {
 254			.name = "camcc_pll4",
 255			.parent_data = &(const struct clk_parent_data) {
 256				.index = DT_BI_TCXO,
 257			},
 258			.num_parents = 1,
 259			.ops = &clk_alpha_pll_fabia_ops,
 260		},
 261	},
 262};
 263
 264static struct clk_fixed_factor camcc_pll4_out_even = {
 265	.mult = 1,
 266	.div = 2,
 267	.hw.init = &(const struct clk_init_data) {
 268		.name = "camcc_pll4_out_even",
 269		.parent_hws = (const struct clk_hw*[]) {
 270			&camcc_pll4.clkr.hw,
 271		},
 272		.num_parents = 1,
 273		.flags = CLK_SET_RATE_PARENT,
 274		.ops = &clk_fixed_factor_ops,
 275	},
 276};
 277
 278static const struct parent_map camcc_parent_map_0[] = {
 279	{ P_BI_TCXO, 0 },
 280	{ P_CAMCC_PLL0_OUT_MAIN, 1 },
 281	{ P_CAMCC_PLL0_OUT_EVEN, 2 },
 282	{ P_CAMCC_PLL0_OUT_ODD, 3 },
 283	{ P_CAMCC_PLL2_OUT_MAIN, 5 },
 284};
 285
 286static const struct clk_parent_data camcc_parent_data_0[] = {
 287	{ .index = DT_BI_TCXO },
 288	{ .hw = &camcc_pll0.clkr.hw },
 289	{ .hw = &camcc_pll0_out_even.hw },
 290	{ .hw = &camcc_pll0_out_odd.hw },
 291	{ .hw = &camcc_pll2_out_main.clkr.hw },
 292};
 293
 294static const struct parent_map camcc_parent_map_1[] = {
 295	{ P_BI_TCXO, 0 },
 296	{ P_CAMCC_PLL0_OUT_MAIN, 1 },
 297	{ P_CAMCC_PLL0_OUT_EVEN, 2 },
 298	{ P_CAMCC_PLL0_OUT_ODD, 3 },
 299	{ P_CAMCC_PLL1_OUT_EVEN, 4 },
 300	{ P_CAMCC_PLL2_OUT_EARLY, 5 },
 301};
 302
 303static const struct clk_parent_data camcc_parent_data_1[] = {
 304	{ .index = DT_BI_TCXO },
 305	{ .hw = &camcc_pll0.clkr.hw },
 306	{ .hw = &camcc_pll0_out_even.hw },
 307	{ .hw = &camcc_pll0_out_odd.hw },
 308	{ .hw = &camcc_pll1_out_even.hw },
 309	{ .hw = &camcc_pll2_out_early.hw },
 310};
 311
 312static const struct parent_map camcc_parent_map_2[] = {
 313	{ P_BI_TCXO_MX, 0 },
 314	{ P_CAMCC_PLL2_OUT_AUX, 5 },
 315};
 316
 317static const struct clk_parent_data camcc_parent_data_2[] = {
 318	{ .index = DT_BI_TCXO },
 319	{ .hw = &camcc_pll2_out_aux.clkr.hw },
 320};
 321
 322static const struct parent_map camcc_parent_map_3[] = {
 323	{ P_BI_TCXO, 0 },
 324	{ P_CAMCC_PLL0_OUT_MAIN, 1 },
 325	{ P_CAMCC_PLL0_OUT_EVEN, 2 },
 326	{ P_CAMCC_PLL0_OUT_ODD, 3 },
 327	{ P_CAMCC_PLL2_OUT_EARLY, 5 },
 328	{ P_CAMCC_PLL4_OUT_EVEN, 6 },
 329};
 330
 331static const struct clk_parent_data camcc_parent_data_3[] = {
 332	{ .index = DT_BI_TCXO },
 333	{ .hw = &camcc_pll0.clkr.hw },
 334	{ .hw = &camcc_pll0_out_even.hw },
 335	{ .hw = &camcc_pll0_out_odd.hw },
 336	{ .hw = &camcc_pll2_out_early.hw },
 337	{ .hw = &camcc_pll4_out_even.hw },
 338};
 339
 340static const struct parent_map camcc_parent_map_4[] = {
 341	{ P_BI_TCXO, 0 },
 342	{ P_CAMCC_PLL3_OUT_EVEN, 6 },
 343};
 344
 345static const struct clk_parent_data camcc_parent_data_4[] = {
 346	{ .index = DT_BI_TCXO },
 347	{ .hw = &camcc_pll3_out_even.hw },
 348};
 349
 350static const struct parent_map camcc_parent_map_5[] = {
 351	{ P_BI_TCXO, 0 },
 352	{ P_CAMCC_PLL4_OUT_EVEN, 6 },
 353};
 354
 355static const struct clk_parent_data camcc_parent_data_5[] = {
 356	{ .index = DT_BI_TCXO },
 357	{ .hw = &camcc_pll4_out_even.hw },
 358};
 359
 360static const struct parent_map camcc_parent_map_6[] = {
 361	{ P_BI_TCXO, 0 },
 362	{ P_CAMCC_PLL1_OUT_EVEN, 4 },
 363};
 364
 365static const struct clk_parent_data camcc_parent_data_6[] = {
 366	{ .index = DT_BI_TCXO },
 367	{ .hw = &camcc_pll1_out_even.hw },
 368};
 369
 370static const struct parent_map camcc_parent_map_7[] = {
 371	{ P_CHIP_SLEEP_CLK, 0 },
 372};
 373
 374static const struct clk_parent_data camcc_parent_data_7[] = {
 375	{ .index = DT_CHIP_SLEEP_CLK },
 376};
 377
 378static const struct parent_map camcc_parent_map_8[] = {
 379	{ P_BI_TCXO, 0 },
 380	{ P_CAMCC_PLL0_OUT_ODD, 3 },
 381};
 382
 383static const struct clk_parent_data camcc_parent_data_8[] = {
 384	{ .index = DT_BI_TCXO },
 385	{ .hw = &camcc_pll0_out_odd.hw },
 386};
 387
 388static const struct parent_map camcc_parent_map_9[] = {
 389	{ P_BI_TCXO, 0 },
 390};
 391
 392static const struct clk_parent_data camcc_parent_data_9[] = {
 393	{ .index = DT_BI_TCXO_AO },
 394};
 395
 396static const struct freq_tbl ftbl_camcc_bps_clk_src[] = {
 397	F(19200000, P_BI_TCXO, 1, 0, 0),
 398	F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
 399	F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0),
 400	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
 401	F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
 402	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
 403	{ }
 404};
 405
 406static struct clk_rcg2 camcc_bps_clk_src = {
 407	.cmd_rcgr = 0x7010,
 408	.mnd_width = 0,
 409	.hid_width = 5,
 410	.parent_map = camcc_parent_map_0,
 411	.freq_tbl = ftbl_camcc_bps_clk_src,
 412	.clkr.hw.init = &(const struct clk_init_data) {
 413		.name = "camcc_bps_clk_src",
 414		.parent_data = camcc_parent_data_0,
 415		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 416		.ops = &clk_rcg2_shared_ops,
 417	},
 418};
 419
 420static const struct freq_tbl ftbl_camcc_camnoc_axi_clk_src[] = {
 421	F(19200000, P_BI_TCXO, 1, 0, 0),
 422	F(150000000, P_CAMCC_PLL0_OUT_EVEN, 4, 0, 0),
 423	F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
 424	F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
 425	F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
 426	F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
 427	{ }
 428};
 429
 430static struct clk_rcg2 camcc_camnoc_axi_clk_src = {
 431	.cmd_rcgr = 0xc12c,
 432	.mnd_width = 0,
 433	.hid_width = 5,
 434	.parent_map = camcc_parent_map_0,
 435	.freq_tbl = ftbl_camcc_camnoc_axi_clk_src,
 436	.clkr.hw.init = &(const struct clk_init_data) {
 437		.name = "camcc_camnoc_axi_clk_src",
 438		.parent_data = camcc_parent_data_0,
 439		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 440		.ops = &clk_rcg2_shared_ops,
 441	},
 442};
 443
 444static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = {
 445	F(19200000, P_BI_TCXO, 1, 0, 0),
 446	F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0),
 447	{ }
 448};
 449
 450static struct clk_rcg2 camcc_cci_0_clk_src = {
 451	.cmd_rcgr = 0xc0c4,
 452	.mnd_width = 8,
 453	.hid_width = 5,
 454	.parent_map = camcc_parent_map_0,
 455	.freq_tbl = ftbl_camcc_cci_0_clk_src,
 456	.clkr.hw.init = &(const struct clk_init_data) {
 457		.name = "camcc_cci_0_clk_src",
 458		.parent_data = camcc_parent_data_0,
 459		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 460		.ops = &clk_rcg2_ops,
 461	},
 462};
 463
 464static struct clk_rcg2 camcc_cci_1_clk_src = {
 465	.cmd_rcgr = 0xc0e0,
 466	.mnd_width = 8,
 467	.hid_width = 5,
 468	.parent_map = camcc_parent_map_0,
 469	.freq_tbl = ftbl_camcc_cci_0_clk_src,
 470	.clkr.hw.init = &(const struct clk_init_data) {
 471		.name = "camcc_cci_1_clk_src",
 472		.parent_data = camcc_parent_data_0,
 473		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 474		.ops = &clk_rcg2_ops,
 475	},
 476};
 477
 478static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = {
 479	F(19200000, P_BI_TCXO, 1, 0, 0),
 480	F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
 481	F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
 482	F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
 483	{ }
 484};
 485
 486static struct clk_rcg2 camcc_cphy_rx_clk_src = {
 487	.cmd_rcgr = 0xa064,
 488	.mnd_width = 0,
 489	.hid_width = 5,
 490	.parent_map = camcc_parent_map_1,
 491	.freq_tbl = ftbl_camcc_cphy_rx_clk_src,
 492	.clkr.hw.init = &(const struct clk_init_data) {
 493		.name = "camcc_cphy_rx_clk_src",
 494		.parent_data = camcc_parent_data_1,
 495		.num_parents = ARRAY_SIZE(camcc_parent_data_1),
 496		.ops = &clk_rcg2_ops,
 497	},
 498};
 499
 500static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = {
 501	F(19200000, P_BI_TCXO, 1, 0, 0),
 502	F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
 503	{ }
 504};
 505
 506static struct clk_rcg2 camcc_csi0phytimer_clk_src = {
 507	.cmd_rcgr = 0x6004,
 508	.mnd_width = 0,
 509	.hid_width = 5,
 510	.parent_map = camcc_parent_map_0,
 511	.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
 512	.clkr.hw.init = &(const struct clk_init_data) {
 513		.name = "camcc_csi0phytimer_clk_src",
 514		.parent_data = camcc_parent_data_0,
 515		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 516		.ops = &clk_rcg2_ops,
 517	},
 518};
 519
 520static struct clk_rcg2 camcc_csi1phytimer_clk_src = {
 521	.cmd_rcgr = 0x6028,
 522	.mnd_width = 0,
 523	.hid_width = 5,
 524	.parent_map = camcc_parent_map_0,
 525	.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
 526	.clkr.hw.init = &(const struct clk_init_data) {
 527		.name = "camcc_csi1phytimer_clk_src",
 528		.parent_data = camcc_parent_data_0,
 529		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 530		.ops = &clk_rcg2_ops,
 531	},
 532};
 533
 534static struct clk_rcg2 camcc_csi2phytimer_clk_src = {
 535	.cmd_rcgr = 0x604c,
 536	.mnd_width = 0,
 537	.hid_width = 5,
 538	.parent_map = camcc_parent_map_0,
 539	.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
 540	.clkr.hw.init = &(const struct clk_init_data) {
 541		.name = "camcc_csi2phytimer_clk_src",
 542		.parent_data = camcc_parent_data_0,
 543		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 544		.ops = &clk_rcg2_ops,
 545	},
 546};
 547
 548static struct clk_rcg2 camcc_csi3phytimer_clk_src = {
 549	.cmd_rcgr = 0x6070,
 550	.mnd_width = 0,
 551	.hid_width = 5,
 552	.parent_map = camcc_parent_map_0,
 553	.freq_tbl = ftbl_camcc_csi0phytimer_clk_src,
 554	.clkr.hw.init = &(const struct clk_init_data) {
 555		.name = "camcc_csi3phytimer_clk_src",
 556		.parent_data = camcc_parent_data_0,
 557		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 558		.ops = &clk_rcg2_ops,
 559	},
 560};
 561
 562static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = {
 563	F(19200000, P_BI_TCXO, 1, 0, 0),
 564	F(50000000, P_CAMCC_PLL0_OUT_EVEN, 12, 0, 0),
 565	F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
 566	F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),
 567	F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),
 568	F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
 569	{ }
 570};
 571
 572static struct clk_rcg2 camcc_fast_ahb_clk_src = {
 573	.cmd_rcgr = 0x703c,
 574	.mnd_width = 0,
 575	.hid_width = 5,
 576	.parent_map = camcc_parent_map_0,
 577	.freq_tbl = ftbl_camcc_fast_ahb_clk_src,
 578	.clkr.hw.init = &(const struct clk_init_data) {
 579		.name = "camcc_fast_ahb_clk_src",
 580		.parent_data = camcc_parent_data_0,
 581		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 582		.ops = &clk_rcg2_ops,
 583	},
 584};
 585
 586static const struct freq_tbl ftbl_camcc_fd_core_clk_src[] = {
 587	F(19200000, P_BI_TCXO, 1, 0, 0),
 588	F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
 589	F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
 590	F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
 591	F(480000000, P_CAMCC_PLL2_OUT_EARLY, 2, 0, 0),
 592	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
 593	{ }
 594};
 595
 596static struct clk_rcg2 camcc_fd_core_clk_src = {
 597	.cmd_rcgr = 0xc09c,
 598	.mnd_width = 0,
 599	.hid_width = 5,
 600	.parent_map = camcc_parent_map_3,
 601	.freq_tbl = ftbl_camcc_fd_core_clk_src,
 602	.clkr.hw.init = &(const struct clk_init_data) {
 603		.name = "camcc_fd_core_clk_src",
 604		.parent_data = camcc_parent_data_3,
 605		.num_parents = ARRAY_SIZE(camcc_parent_data_3),
 606		.flags = CLK_SET_RATE_PARENT,
 607		.ops = &clk_rcg2_shared_ops,
 608	},
 609};
 610
 611static const struct freq_tbl ftbl_camcc_icp_clk_src[] = {
 612	F(19200000, P_BI_TCXO, 1, 0, 0),
 613	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
 614	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
 615	{ }
 616};
 617
 618static struct clk_rcg2 camcc_icp_clk_src = {
 619	.cmd_rcgr = 0xc074,
 620	.mnd_width = 0,
 621	.hid_width = 5,
 622	.parent_map = camcc_parent_map_0,
 623	.freq_tbl = ftbl_camcc_icp_clk_src,
 624	.clkr.hw.init = &(const struct clk_init_data) {
 625		.name = "camcc_icp_clk_src",
 626		.parent_data = camcc_parent_data_0,
 627		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 628		.ops = &clk_rcg2_shared_ops,
 629	},
 630};
 631
 632static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = {
 633	F(19200000, P_BI_TCXO, 1, 0, 0),
 634	F(380000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
 635	F(510000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
 636	F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
 637	F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
 638	{ }
 639};
 640
 641static struct clk_rcg2 camcc_ife_0_clk_src = {
 642	.cmd_rcgr = 0xa010,
 643	.mnd_width = 0,
 644	.hid_width = 5,
 645	.parent_map = camcc_parent_map_4,
 646	.freq_tbl = ftbl_camcc_ife_0_clk_src,
 647	.clkr.hw.init = &(const struct clk_init_data) {
 648		.name = "camcc_ife_0_clk_src",
 649		.parent_data = camcc_parent_data_4,
 650		.num_parents = ARRAY_SIZE(camcc_parent_data_4),
 651		.flags = CLK_SET_RATE_PARENT,
 652		.ops = &clk_rcg2_shared_ops,
 653	},
 654};
 655
 656static const struct freq_tbl ftbl_camcc_ife_0_csid_clk_src[] = {
 657	F(19200000, P_BI_TCXO, 1, 0, 0),
 658	F(75000000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0),
 659	F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
 660	F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
 661	F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
 662	{ }
 663};
 664
 665static struct clk_rcg2 camcc_ife_0_csid_clk_src = {
 666	.cmd_rcgr = 0xa03c,
 667	.mnd_width = 0,
 668	.hid_width = 5,
 669	.parent_map = camcc_parent_map_1,
 670	.freq_tbl = ftbl_camcc_ife_0_csid_clk_src,
 671	.clkr.hw.init = &(const struct clk_init_data) {
 672		.name = "camcc_ife_0_csid_clk_src",
 673		.parent_data = camcc_parent_data_1,
 674		.num_parents = ARRAY_SIZE(camcc_parent_data_1),
 675		.ops = &clk_rcg2_shared_ops,
 676	},
 677};
 678
 679static const struct freq_tbl ftbl_camcc_ife_1_clk_src[] = {
 680	F(19200000, P_BI_TCXO, 1, 0, 0),
 681	F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
 682	F(510000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
 683	F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
 684	F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
 685	{ }
 686};
 687
 688static struct clk_rcg2 camcc_ife_1_clk_src = {
 689	.cmd_rcgr = 0xb010,
 690	.mnd_width = 0,
 691	.hid_width = 5,
 692	.parent_map = camcc_parent_map_5,
 693	.freq_tbl = ftbl_camcc_ife_1_clk_src,
 694	.clkr.hw.init = &(const struct clk_init_data) {
 695		.name = "camcc_ife_1_clk_src",
 696		.parent_data = camcc_parent_data_5,
 697		.num_parents = ARRAY_SIZE(camcc_parent_data_5),
 698		.flags = CLK_SET_RATE_PARENT,
 699		.ops = &clk_rcg2_shared_ops,
 700	},
 701};
 702
 703static struct clk_rcg2 camcc_ife_1_csid_clk_src = {
 704	.cmd_rcgr = 0xb034,
 705	.mnd_width = 0,
 706	.hid_width = 5,
 707	.parent_map = camcc_parent_map_1,
 708	.freq_tbl = ftbl_camcc_ife_0_csid_clk_src,
 709	.clkr.hw.init = &(const struct clk_init_data) {
 710		.name = "camcc_ife_1_csid_clk_src",
 711		.parent_data = camcc_parent_data_1,
 712		.num_parents = ARRAY_SIZE(camcc_parent_data_1),
 713		.ops = &clk_rcg2_shared_ops,
 714	},
 715};
 716
 717static const struct freq_tbl ftbl_camcc_ife_lite_clk_src[] = {
 718	F(19200000, P_BI_TCXO, 1, 0, 0),
 719	F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
 720	F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
 721	F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
 722	F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
 723	{ }
 724};
 725
 726static struct clk_rcg2 camcc_ife_lite_clk_src = {
 727	.cmd_rcgr = 0xc004,
 728	.mnd_width = 0,
 729	.hid_width = 5,
 730	.parent_map = camcc_parent_map_0,
 731	.freq_tbl = ftbl_camcc_ife_lite_clk_src,
 732	.clkr.hw.init = &(const struct clk_init_data) {
 733		.name = "camcc_ife_lite_clk_src",
 734		.parent_data = camcc_parent_data_0,
 735		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 736		.ops = &clk_rcg2_ops,
 737	},
 738};
 739
 740static struct clk_rcg2 camcc_ife_lite_csid_clk_src = {
 741	.cmd_rcgr = 0xc020,
 742	.mnd_width = 0,
 743	.hid_width = 5,
 744	.parent_map = camcc_parent_map_1,
 745	.freq_tbl = ftbl_camcc_cphy_rx_clk_src,
 746	.clkr.hw.init = &(const struct clk_init_data) {
 747		.name = "camcc_ife_lite_csid_clk_src",
 748		.parent_data = camcc_parent_data_1,
 749		.num_parents = ARRAY_SIZE(camcc_parent_data_1),
 750		.ops = &clk_rcg2_shared_ops,
 751	},
 752};
 753
 754static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = {
 755	F(19200000, P_BI_TCXO, 1, 0, 0),
 756	F(340000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
 757	F(430000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
 758	F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
 759	F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
 760	{ }
 761};
 762
 763static struct clk_rcg2 camcc_ipe_0_clk_src = {
 764	.cmd_rcgr = 0x8010,
 765	.mnd_width = 0,
 766	.hid_width = 5,
 767	.parent_map = camcc_parent_map_6,
 768	.freq_tbl = ftbl_camcc_ipe_0_clk_src,
 769	.clkr.hw.init = &(const struct clk_init_data) {
 770		.name = "camcc_ipe_0_clk_src",
 771		.parent_data = camcc_parent_data_6,
 772		.num_parents = ARRAY_SIZE(camcc_parent_data_6),
 773		.flags = CLK_SET_RATE_PARENT,
 774		.ops = &clk_rcg2_shared_ops,
 775	},
 776};
 777
 778static struct clk_rcg2 camcc_jpeg_clk_src = {
 779	.cmd_rcgr = 0xc048,
 780	.mnd_width = 0,
 781	.hid_width = 5,
 782	.parent_map = camcc_parent_map_0,
 783	.freq_tbl = ftbl_camcc_bps_clk_src,
 784	.clkr.hw.init = &(const struct clk_init_data) {
 785		.name = "camcc_jpeg_clk_src",
 786		.parent_data = camcc_parent_data_0,
 787		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 788		.ops = &clk_rcg2_shared_ops,
 789	},
 790};
 791
 792static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = {
 793	F(19200000, P_BI_TCXO, 1, 0, 0),
 794	F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
 795	F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
 796	F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
 797	F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
 798	F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
 799	{ }
 800};
 801
 802static struct clk_rcg2 camcc_lrme_clk_src = {
 803	.cmd_rcgr = 0xc100,
 804	.mnd_width = 0,
 805	.hid_width = 5,
 806	.parent_map = camcc_parent_map_0,
 807	.freq_tbl = ftbl_camcc_lrme_clk_src,
 808	.clkr.hw.init = &(const struct clk_init_data) {
 809		.name = "camcc_lrme_clk_src",
 810		.parent_data = camcc_parent_data_0,
 811		.num_parents = ARRAY_SIZE(camcc_parent_data_0),
 812		.ops = &clk_rcg2_shared_ops,
 813	},
 814};
 815
 816static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = {
 817	F(19200000, P_BI_TCXO_MX, 1, 0, 0),
 818	F(24000000, P_CAMCC_PLL2_OUT_AUX, 1, 1, 20),
 819	F(34285714, P_CAMCC_PLL2_OUT_AUX, 14, 0, 0),
 820	{ }
 821};
 822
 823static struct clk_rcg2 camcc_mclk0_clk_src = {
 824	.cmd_rcgr = 0x5004,
 825	.mnd_width = 8,
 826	.hid_width = 5,
 827	.parent_map = camcc_parent_map_2,
 828	.freq_tbl = ftbl_camcc_mclk0_clk_src,
 829	.clkr.hw.init = &(const struct clk_init_data) {
 830		.name = "camcc_mclk0_clk_src",
 831		.parent_data = camcc_parent_data_2,
 832		.num_parents = ARRAY_SIZE(camcc_parent_data_2),
 833		.ops = &clk_rcg2_ops,
 834	},
 835};
 836
 837static struct clk_rcg2 camcc_mclk1_clk_src = {
 838	.cmd_rcgr = 0x5024,
 839	.mnd_width = 8,
 840	.hid_width = 5,
 841	.parent_map = camcc_parent_map_2,
 842	.freq_tbl = ftbl_camcc_mclk0_clk_src,
 843	.clkr.hw.init = &(const struct clk_init_data) {
 844		.name = "camcc_mclk1_clk_src",
 845		.parent_data = camcc_parent_data_2,
 846		.num_parents = ARRAY_SIZE(camcc_parent_data_2),
 847		.ops = &clk_rcg2_ops,
 848	},
 849};
 850
 851static struct clk_rcg2 camcc_mclk2_clk_src = {
 852	.cmd_rcgr = 0x5044,
 853	.mnd_width = 8,
 854	.hid_width = 5,
 855	.parent_map = camcc_parent_map_2,
 856	.freq_tbl = ftbl_camcc_mclk0_clk_src,
 857	.clkr.hw.init = &(const struct clk_init_data) {
 858		.name = "camcc_mclk2_clk_src",
 859		.parent_data = camcc_parent_data_2,
 860		.num_parents = ARRAY_SIZE(camcc_parent_data_2),
 861		.ops = &clk_rcg2_ops,
 862	},
 863};
 864
 865static struct clk_rcg2 camcc_mclk3_clk_src = {
 866	.cmd_rcgr = 0x5064,
 867	.mnd_width = 8,
 868	.hid_width = 5,
 869	.parent_map = camcc_parent_map_2,
 870	.freq_tbl = ftbl_camcc_mclk0_clk_src,
 871	.clkr.hw.init = &(const struct clk_init_data) {
 872		.name = "camcc_mclk3_clk_src",
 873		.parent_data = camcc_parent_data_2,
 874		.num_parents = ARRAY_SIZE(camcc_parent_data_2),
 875		.ops = &clk_rcg2_ops,
 876	},
 877};
 878
 879static const struct freq_tbl ftbl_camcc_sleep_clk_src[] = {
 880	F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0),
 881	{ }
 882};
 883
 884static struct clk_rcg2 camcc_sleep_clk_src = {
 885	.cmd_rcgr = 0xc1a4,
 886	.mnd_width = 0,
 887	.hid_width = 5,
 888	.parent_map = camcc_parent_map_7,
 889	.freq_tbl = ftbl_camcc_sleep_clk_src,
 890	.clkr.hw.init = &(const struct clk_init_data) {
 891		.name = "camcc_sleep_clk_src",
 892		.parent_data = camcc_parent_data_7,
 893		.num_parents = ARRAY_SIZE(camcc_parent_data_7),
 894		.ops = &clk_rcg2_ops,
 895	},
 896};
 897
 898static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = {
 899	F(19200000, P_BI_TCXO, 1, 0, 0),
 900	F(80000000, P_CAMCC_PLL0_OUT_ODD, 5, 0, 0),
 901	{ }
 902};
 903
 904static struct clk_rcg2 camcc_slow_ahb_clk_src = {
 905	.cmd_rcgr = 0x7058,
 906	.mnd_width = 0,
 907	.hid_width = 5,
 908	.parent_map = camcc_parent_map_8,
 909	.freq_tbl = ftbl_camcc_slow_ahb_clk_src,
 910	.clkr.hw.init = &(const struct clk_init_data) {
 911		.name = "camcc_slow_ahb_clk_src",
 912		.parent_data = camcc_parent_data_8,
 913		.num_parents = ARRAY_SIZE(camcc_parent_data_8),
 914		.ops = &clk_rcg2_shared_ops,
 915	},
 916};
 917
 918static const struct freq_tbl ftbl_camcc_xo_clk_src[] = {
 919	F(19200000, P_BI_TCXO, 1, 0, 0),
 920	{ }
 921};
 922
 923static struct clk_rcg2 camcc_xo_clk_src = {
 924	.cmd_rcgr = 0xc188,
 925	.mnd_width = 0,
 926	.hid_width = 5,
 927	.parent_map = camcc_parent_map_9,
 928	.freq_tbl = ftbl_camcc_xo_clk_src,
 929	.clkr.hw.init = &(const struct clk_init_data) {
 930		.name = "camcc_xo_clk_src",
 931		.parent_data = camcc_parent_data_9,
 932		.num_parents = ARRAY_SIZE(camcc_parent_data_9),
 933		.ops = &clk_rcg2_ops,
 934	},
 935};
 936
 937static struct clk_branch camcc_bps_ahb_clk = {
 938	.halt_reg = 0x7070,
 939	.halt_check = BRANCH_HALT,
 940	.clkr = {
 941		.enable_reg = 0x7070,
 942		.enable_mask = BIT(0),
 943		.hw.init = &(const struct clk_init_data) {
 944			.name = "camcc_bps_ahb_clk",
 945			.parent_hws = (const struct clk_hw*[]) {
 946				&camcc_slow_ahb_clk_src.clkr.hw,
 947			},
 948			.num_parents = 1,
 949			.flags = CLK_SET_RATE_PARENT,
 950			.ops = &clk_branch2_ops,
 951		},
 952	},
 953};
 954
 955static struct clk_branch camcc_bps_areg_clk = {
 956	.halt_reg = 0x7054,
 957	.halt_check = BRANCH_HALT,
 958	.clkr = {
 959		.enable_reg = 0x7054,
 960		.enable_mask = BIT(0),
 961		.hw.init = &(const struct clk_init_data) {
 962			.name = "camcc_bps_areg_clk",
 963			.parent_hws = (const struct clk_hw*[]) {
 964				&camcc_fast_ahb_clk_src.clkr.hw,
 965			},
 966			.num_parents = 1,
 967			.flags = CLK_SET_RATE_PARENT,
 968			.ops = &clk_branch2_ops,
 969		},
 970	},
 971};
 972
 973static struct clk_branch camcc_bps_axi_clk = {
 974	.halt_reg = 0x7038,
 975	.halt_check = BRANCH_HALT,
 976	.clkr = {
 977		.enable_reg = 0x7038,
 978		.enable_mask = BIT(0),
 979		.hw.init = &(const struct clk_init_data) {
 980			.name = "camcc_bps_axi_clk",
 981			.parent_hws = (const struct clk_hw*[]) {
 982				&camcc_camnoc_axi_clk_src.clkr.hw,
 983			},
 984			.num_parents = 1,
 985			.flags = CLK_SET_RATE_PARENT,
 986			.ops = &clk_branch2_ops,
 987		},
 988	},
 989};
 990
 991static struct clk_branch camcc_bps_clk = {
 992	.halt_reg = 0x7028,
 993	.halt_check = BRANCH_HALT,
 994	.clkr = {
 995		.enable_reg = 0x7028,
 996		.enable_mask = BIT(0),
 997		.hw.init = &(const struct clk_init_data) {
 998			.name = "camcc_bps_clk",
 999			.parent_hws = (const struct clk_hw*[]) {
1000				&camcc_bps_clk_src.clkr.hw,
1001			},
1002			.num_parents = 1,
1003			.flags = CLK_SET_RATE_PARENT,
1004			.ops = &clk_branch2_ops,
1005		},
1006	},
1007};
1008
1009static struct clk_branch camcc_camnoc_axi_clk = {
1010	.halt_reg = 0xc148,
1011	.halt_check = BRANCH_HALT,
1012	.clkr = {
1013		.enable_reg = 0xc148,
1014		.enable_mask = BIT(0),
1015		.hw.init = &(const struct clk_init_data) {
1016			.name = "camcc_camnoc_axi_clk",
1017			.parent_hws = (const struct clk_hw*[]) {
1018				&camcc_camnoc_axi_clk_src.clkr.hw,
1019			},
1020			.num_parents = 1,
1021			.flags = CLK_SET_RATE_PARENT,
1022			.ops = &clk_branch2_ops,
1023		},
1024	},
1025};
1026
1027static struct clk_branch camcc_camnoc_dcd_xo_clk = {
1028	.halt_reg = 0xc150,
1029	.halt_check = BRANCH_HALT,
1030	.clkr = {
1031		.enable_reg = 0xc150,
1032		.enable_mask = BIT(0),
1033		.hw.init = &(const struct clk_init_data) {
1034			.name = "camcc_camnoc_dcd_xo_clk",
1035			.parent_hws = (const struct clk_hw*[]) {
1036				&camcc_xo_clk_src.clkr.hw,
1037			},
1038			.num_parents = 1,
1039			.flags = CLK_SET_RATE_PARENT,
1040			.ops = &clk_branch2_ops,
1041		},
1042	},
1043};
1044
1045static struct clk_branch camcc_cci_0_clk = {
1046	.halt_reg = 0xc0dc,
1047	.halt_check = BRANCH_HALT,
1048	.clkr = {
1049		.enable_reg = 0xc0dc,
1050		.enable_mask = BIT(0),
1051		.hw.init = &(const struct clk_init_data) {
1052			.name = "camcc_cci_0_clk",
1053			.parent_hws = (const struct clk_hw*[]) {
1054				&camcc_cci_0_clk_src.clkr.hw,
1055			},
1056			.num_parents = 1,
1057			.flags = CLK_SET_RATE_PARENT,
1058			.ops = &clk_branch2_ops,
1059		},
1060	},
1061};
1062
1063static struct clk_branch camcc_cci_1_clk = {
1064	.halt_reg = 0xc0f8,
1065	.halt_check = BRANCH_HALT,
1066	.clkr = {
1067		.enable_reg = 0xc0f8,
1068		.enable_mask = BIT(0),
1069		.hw.init = &(const struct clk_init_data) {
1070			.name = "camcc_cci_1_clk",
1071			.parent_hws = (const struct clk_hw*[]) {
1072				&camcc_cci_1_clk_src.clkr.hw,
1073			},
1074			.num_parents = 1,
1075			.flags = CLK_SET_RATE_PARENT,
1076			.ops = &clk_branch2_ops,
1077		},
1078	},
1079};
1080
1081static struct clk_branch camcc_core_ahb_clk = {
1082	.halt_reg = 0xc184,
1083	.halt_check = BRANCH_HALT_DELAY,
1084	.clkr = {
1085		.enable_reg = 0xc184,
1086		.enable_mask = BIT(0),
1087		.hw.init = &(const struct clk_init_data) {
1088			.name = "camcc_core_ahb_clk",
1089			.parent_hws = (const struct clk_hw*[]) {
1090				&camcc_slow_ahb_clk_src.clkr.hw,
1091			},
1092			.num_parents = 1,
1093			.flags = CLK_SET_RATE_PARENT,
1094			.ops = &clk_branch2_ops,
1095		},
1096	},
1097};
1098
1099static struct clk_branch camcc_cpas_ahb_clk = {
1100	.halt_reg = 0xc124,
1101	.halt_check = BRANCH_HALT,
1102	.clkr = {
1103		.enable_reg = 0xc124,
1104		.enable_mask = BIT(0),
1105		.hw.init = &(const struct clk_init_data) {
1106			.name = "camcc_cpas_ahb_clk",
1107			.parent_hws = (const struct clk_hw*[]) {
1108				&camcc_slow_ahb_clk_src.clkr.hw,
1109			},
1110			.num_parents = 1,
1111			.flags = CLK_SET_RATE_PARENT,
1112			.ops = &clk_branch2_ops,
1113		},
1114	},
1115};
1116
1117static struct clk_branch camcc_csi0phytimer_clk = {
1118	.halt_reg = 0x601c,
1119	.halt_check = BRANCH_HALT,
1120	.clkr = {
1121		.enable_reg = 0x601c,
1122		.enable_mask = BIT(0),
1123		.hw.init = &(const struct clk_init_data) {
1124			.name = "camcc_csi0phytimer_clk",
1125			.parent_hws = (const struct clk_hw*[]) {
1126				&camcc_csi0phytimer_clk_src.clkr.hw,
1127			},
1128			.num_parents = 1,
1129			.flags = CLK_SET_RATE_PARENT,
1130			.ops = &clk_branch2_ops,
1131		},
1132	},
1133};
1134
1135static struct clk_branch camcc_csi1phytimer_clk = {
1136	.halt_reg = 0x6040,
1137	.halt_check = BRANCH_HALT,
1138	.clkr = {
1139		.enable_reg = 0x6040,
1140		.enable_mask = BIT(0),
1141		.hw.init = &(const struct clk_init_data) {
1142			.name = "camcc_csi1phytimer_clk",
1143			.parent_hws = (const struct clk_hw*[]) {
1144				&camcc_csi1phytimer_clk_src.clkr.hw,
1145			},
1146			.num_parents = 1,
1147			.flags = CLK_SET_RATE_PARENT,
1148			.ops = &clk_branch2_ops,
1149		},
1150	},
1151};
1152
1153static struct clk_branch camcc_csi2phytimer_clk = {
1154	.halt_reg = 0x6064,
1155	.halt_check = BRANCH_HALT,
1156	.clkr = {
1157		.enable_reg = 0x6064,
1158		.enable_mask = BIT(0),
1159		.hw.init = &(const struct clk_init_data) {
1160			.name = "camcc_csi2phytimer_clk",
1161			.parent_hws = (const struct clk_hw*[]) {
1162				&camcc_csi2phytimer_clk_src.clkr.hw,
1163			},
1164			.num_parents = 1,
1165			.flags = CLK_SET_RATE_PARENT,
1166			.ops = &clk_branch2_ops,
1167		},
1168	},
1169};
1170
1171static struct clk_branch camcc_csi3phytimer_clk = {
1172	.halt_reg = 0x6088,
1173	.halt_check = BRANCH_HALT,
1174	.clkr = {
1175		.enable_reg = 0x6088,
1176		.enable_mask = BIT(0),
1177		.hw.init = &(const struct clk_init_data) {
1178			.name = "camcc_csi3phytimer_clk",
1179			.parent_hws = (const struct clk_hw*[]) {
1180				&camcc_csi3phytimer_clk_src.clkr.hw,
1181			},
1182			.num_parents = 1,
1183			.flags = CLK_SET_RATE_PARENT,
1184			.ops = &clk_branch2_ops,
1185		},
1186	},
1187};
1188
1189static struct clk_branch camcc_csiphy0_clk = {
1190	.halt_reg = 0x6020,
1191	.halt_check = BRANCH_HALT,
1192	.clkr = {
1193		.enable_reg = 0x6020,
1194		.enable_mask = BIT(0),
1195		.hw.init = &(const struct clk_init_data) {
1196			.name = "camcc_csiphy0_clk",
1197			.parent_hws = (const struct clk_hw*[]) {
1198				&camcc_cphy_rx_clk_src.clkr.hw,
1199			},
1200			.num_parents = 1,
1201			.flags = CLK_SET_RATE_PARENT,
1202			.ops = &clk_branch2_ops,
1203		},
1204	},
1205};
1206
1207static struct clk_branch camcc_csiphy1_clk = {
1208	.halt_reg = 0x6044,
1209	.halt_check = BRANCH_HALT,
1210	.clkr = {
1211		.enable_reg = 0x6044,
1212		.enable_mask = BIT(0),
1213		.hw.init = &(const struct clk_init_data) {
1214			.name = "camcc_csiphy1_clk",
1215			.parent_hws = (const struct clk_hw*[]) {
1216				&camcc_cphy_rx_clk_src.clkr.hw,
1217			},
1218			.num_parents = 1,
1219			.flags = CLK_SET_RATE_PARENT,
1220			.ops = &clk_branch2_ops,
1221		},
1222	},
1223};
1224
1225static struct clk_branch camcc_csiphy2_clk = {
1226	.halt_reg = 0x6068,
1227	.halt_check = BRANCH_HALT,
1228	.clkr = {
1229		.enable_reg = 0x6068,
1230		.enable_mask = BIT(0),
1231		.hw.init = &(const struct clk_init_data) {
1232			.name = "camcc_csiphy2_clk",
1233			.parent_hws = (const struct clk_hw*[]) {
1234				&camcc_cphy_rx_clk_src.clkr.hw,
1235			},
1236			.num_parents = 1,
1237			.flags = CLK_SET_RATE_PARENT,
1238			.ops = &clk_branch2_ops,
1239		},
1240	},
1241};
1242
1243static struct clk_branch camcc_csiphy3_clk = {
1244	.halt_reg = 0x608c,
1245	.halt_check = BRANCH_HALT,
1246	.clkr = {
1247		.enable_reg = 0x608c,
1248		.enable_mask = BIT(0),
1249		.hw.init = &(const struct clk_init_data) {
1250			.name = "camcc_csiphy3_clk",
1251			.parent_hws = (const struct clk_hw*[]) {
1252				&camcc_cphy_rx_clk_src.clkr.hw,
1253			},
1254			.num_parents = 1,
1255			.flags = CLK_SET_RATE_PARENT,
1256			.ops = &clk_branch2_ops,
1257		},
1258	},
1259};
1260
1261static struct clk_branch camcc_fd_core_clk = {
1262	.halt_reg = 0xc0b4,
1263	.halt_check = BRANCH_HALT,
1264	.clkr = {
1265		.enable_reg = 0xc0b4,
1266		.enable_mask = BIT(0),
1267		.hw.init = &(const struct clk_init_data) {
1268			.name = "camcc_fd_core_clk",
1269			.parent_hws = (const struct clk_hw*[]) {
1270				&camcc_fd_core_clk_src.clkr.hw,
1271			},
1272			.num_parents = 1,
1273			.flags = CLK_SET_RATE_PARENT,
1274			.ops = &clk_branch2_ops,
1275		},
1276	},
1277};
1278
1279static struct clk_branch camcc_fd_core_uar_clk = {
1280	.halt_reg = 0xc0bc,
1281	.halt_check = BRANCH_HALT,
1282	.clkr = {
1283		.enable_reg = 0xc0bc,
1284		.enable_mask = BIT(0),
1285		.hw.init = &(const struct clk_init_data) {
1286			.name = "camcc_fd_core_uar_clk",
1287			.parent_hws = (const struct clk_hw*[]) {
1288				&camcc_fd_core_clk_src.clkr.hw,
1289			},
1290			.num_parents = 1,
1291			.flags = CLK_SET_RATE_PARENT,
1292			.ops = &clk_branch2_ops,
1293		},
1294	},
1295};
1296
1297static struct clk_branch camcc_icp_ahb_clk = {
1298	.halt_reg = 0xc094,
1299	.halt_check = BRANCH_HALT,
1300	.clkr = {
1301		.enable_reg = 0xc094,
1302		.enable_mask = BIT(0),
1303		.hw.init = &(const struct clk_init_data) {
1304			.name = "camcc_icp_ahb_clk",
1305			.parent_hws = (const struct clk_hw*[]) {
1306				&camcc_slow_ahb_clk_src.clkr.hw,
1307			},
1308			.num_parents = 1,
1309			.flags = CLK_SET_RATE_PARENT,
1310			.ops = &clk_branch2_ops,
1311		},
1312	},
1313};
1314
1315static struct clk_branch camcc_icp_clk = {
1316	.halt_reg = 0xc08c,
1317	.halt_check = BRANCH_HALT,
1318	.clkr = {
1319		.enable_reg = 0xc08c,
1320		.enable_mask = BIT(0),
1321		.hw.init = &(const struct clk_init_data) {
1322			.name = "camcc_icp_clk",
1323			.parent_hws = (const struct clk_hw*[]) {
1324				&camcc_icp_clk_src.clkr.hw,
1325			},
1326			.num_parents = 1,
1327			.flags = CLK_SET_RATE_PARENT,
1328			.ops = &clk_branch2_ops,
1329		},
1330	},
1331};
1332
1333static struct clk_branch camcc_ife_0_axi_clk = {
1334	.halt_reg = 0xa080,
1335	.halt_check = BRANCH_HALT,
1336	.clkr = {
1337		.enable_reg = 0xa080,
1338		.enable_mask = BIT(0),
1339		.hw.init = &(const struct clk_init_data) {
1340			.name = "camcc_ife_0_axi_clk",
1341			.parent_hws = (const struct clk_hw*[]) {
1342				&camcc_camnoc_axi_clk_src.clkr.hw,
1343			},
1344			.num_parents = 1,
1345			.flags = CLK_SET_RATE_PARENT,
1346			.ops = &clk_branch2_ops,
1347		},
1348	},
1349};
1350
1351static struct clk_branch camcc_ife_0_clk = {
1352	.halt_reg = 0xa028,
1353	.halt_check = BRANCH_HALT,
1354	.clkr = {
1355		.enable_reg = 0xa028,
1356		.enable_mask = BIT(0),
1357		.hw.init = &(const struct clk_init_data) {
1358			.name = "camcc_ife_0_clk",
1359			.parent_hws = (const struct clk_hw*[]) {
1360				&camcc_ife_0_clk_src.clkr.hw,
1361			},
1362			.num_parents = 1,
1363			.flags = CLK_SET_RATE_PARENT,
1364			.ops = &clk_branch2_ops,
1365		},
1366	},
1367};
1368
1369static struct clk_branch camcc_ife_0_cphy_rx_clk = {
1370	.halt_reg = 0xa07c,
1371	.halt_check = BRANCH_HALT,
1372	.clkr = {
1373		.enable_reg = 0xa07c,
1374		.enable_mask = BIT(0),
1375		.hw.init = &(const struct clk_init_data) {
1376			.name = "camcc_ife_0_cphy_rx_clk",
1377			.parent_hws = (const struct clk_hw*[]) {
1378				&camcc_cphy_rx_clk_src.clkr.hw,
1379			},
1380			.num_parents = 1,
1381			.flags = CLK_SET_RATE_PARENT,
1382			.ops = &clk_branch2_ops,
1383		},
1384	},
1385};
1386
1387static struct clk_branch camcc_ife_0_csid_clk = {
1388	.halt_reg = 0xa054,
1389	.halt_check = BRANCH_HALT,
1390	.clkr = {
1391		.enable_reg = 0xa054,
1392		.enable_mask = BIT(0),
1393		.hw.init = &(const struct clk_init_data) {
1394			.name = "camcc_ife_0_csid_clk",
1395			.parent_hws = (const struct clk_hw*[]) {
1396				&camcc_ife_0_csid_clk_src.clkr.hw,
1397			},
1398			.num_parents = 1,
1399			.flags = CLK_SET_RATE_PARENT,
1400			.ops = &clk_branch2_ops,
1401		},
1402	},
1403};
1404
1405static struct clk_branch camcc_ife_0_dsp_clk = {
1406	.halt_reg = 0xa038,
1407	.halt_check = BRANCH_HALT,
1408	.clkr = {
1409		.enable_reg = 0xa038,
1410		.enable_mask = BIT(0),
1411		.hw.init = &(const struct clk_init_data) {
1412			.name = "camcc_ife_0_dsp_clk",
1413			.parent_hws = (const struct clk_hw*[]) {
1414				&camcc_ife_0_clk_src.clkr.hw,
1415			},
1416			.num_parents = 1,
1417			.flags = CLK_SET_RATE_PARENT,
1418			.ops = &clk_branch2_ops,
1419		},
1420	},
1421};
1422
1423static struct clk_branch camcc_ife_1_axi_clk = {
1424	.halt_reg = 0xb058,
1425	.halt_check = BRANCH_HALT,
1426	.clkr = {
1427		.enable_reg = 0xb058,
1428		.enable_mask = BIT(0),
1429		.hw.init = &(const struct clk_init_data) {
1430			.name = "camcc_ife_1_axi_clk",
1431			.parent_hws = (const struct clk_hw*[]) {
1432				&camcc_camnoc_axi_clk_src.clkr.hw,
1433			},
1434			.num_parents = 1,
1435			.flags = CLK_SET_RATE_PARENT,
1436			.ops = &clk_branch2_ops,
1437		},
1438	},
1439};
1440
1441static struct clk_branch camcc_ife_1_clk = {
1442	.halt_reg = 0xb028,
1443	.halt_check = BRANCH_HALT,
1444	.clkr = {
1445		.enable_reg = 0xb028,
1446		.enable_mask = BIT(0),
1447		.hw.init = &(const struct clk_init_data) {
1448			.name = "camcc_ife_1_clk",
1449			.parent_hws = (const struct clk_hw*[]) {
1450				&camcc_ife_1_clk_src.clkr.hw,
1451			},
1452			.num_parents = 1,
1453			.flags = CLK_SET_RATE_PARENT,
1454			.ops = &clk_branch2_ops,
1455		},
1456	},
1457};
1458
1459static struct clk_branch camcc_ife_1_cphy_rx_clk = {
1460	.halt_reg = 0xb054,
1461	.halt_check = BRANCH_HALT,
1462	.clkr = {
1463		.enable_reg = 0xb054,
1464		.enable_mask = BIT(0),
1465		.hw.init = &(const struct clk_init_data) {
1466			.name = "camcc_ife_1_cphy_rx_clk",
1467			.parent_hws = (const struct clk_hw*[]) {
1468				&camcc_cphy_rx_clk_src.clkr.hw,
1469			},
1470			.num_parents = 1,
1471			.flags = CLK_SET_RATE_PARENT,
1472			.ops = &clk_branch2_ops,
1473		},
1474	},
1475};
1476
1477static struct clk_branch camcc_ife_1_csid_clk = {
1478	.halt_reg = 0xb04c,
1479	.halt_check = BRANCH_HALT,
1480	.clkr = {
1481		.enable_reg = 0xb04c,
1482		.enable_mask = BIT(0),
1483		.hw.init = &(const struct clk_init_data) {
1484			.name = "camcc_ife_1_csid_clk",
1485			.parent_hws = (const struct clk_hw*[]) {
1486				&camcc_ife_1_csid_clk_src.clkr.hw,
1487			},
1488			.num_parents = 1,
1489			.flags = CLK_SET_RATE_PARENT,
1490			.ops = &clk_branch2_ops,
1491		},
1492	},
1493};
1494
1495static struct clk_branch camcc_ife_1_dsp_clk = {
1496	.halt_reg = 0xb030,
1497	.halt_check = BRANCH_HALT,
1498	.clkr = {
1499		.enable_reg = 0xb030,
1500		.enable_mask = BIT(0),
1501		.hw.init = &(const struct clk_init_data) {
1502			.name = "camcc_ife_1_dsp_clk",
1503			.parent_hws = (const struct clk_hw*[]) {
1504				&camcc_ife_1_clk_src.clkr.hw,
1505			},
1506			.num_parents = 1,
1507			.flags = CLK_SET_RATE_PARENT,
1508			.ops = &clk_branch2_ops,
1509		},
1510	},
1511};
1512
1513static struct clk_branch camcc_ife_lite_clk = {
1514	.halt_reg = 0xc01c,
1515	.halt_check = BRANCH_HALT,
1516	.clkr = {
1517		.enable_reg = 0xc01c,
1518		.enable_mask = BIT(0),
1519		.hw.init = &(const struct clk_init_data) {
1520			.name = "camcc_ife_lite_clk",
1521			.parent_hws = (const struct clk_hw*[]) {
1522				&camcc_ife_lite_clk_src.clkr.hw,
1523			},
1524			.num_parents = 1,
1525			.flags = CLK_SET_RATE_PARENT,
1526			.ops = &clk_branch2_ops,
1527		},
1528	},
1529};
1530
1531static struct clk_branch camcc_ife_lite_cphy_rx_clk = {
1532	.halt_reg = 0xc040,
1533	.halt_check = BRANCH_HALT,
1534	.clkr = {
1535		.enable_reg = 0xc040,
1536		.enable_mask = BIT(0),
1537		.hw.init = &(const struct clk_init_data) {
1538			.name = "camcc_ife_lite_cphy_rx_clk",
1539			.parent_hws = (const struct clk_hw*[]) {
1540				&camcc_cphy_rx_clk_src.clkr.hw,
1541			},
1542			.num_parents = 1,
1543			.flags = CLK_SET_RATE_PARENT,
1544			.ops = &clk_branch2_ops,
1545		},
1546	},
1547};
1548
1549static struct clk_branch camcc_ife_lite_csid_clk = {
1550	.halt_reg = 0xc038,
1551	.halt_check = BRANCH_HALT,
1552	.clkr = {
1553		.enable_reg = 0xc038,
1554		.enable_mask = BIT(0),
1555		.hw.init = &(const struct clk_init_data) {
1556			.name = "camcc_ife_lite_csid_clk",
1557			.parent_hws = (const struct clk_hw*[]) {
1558				&camcc_ife_lite_csid_clk_src.clkr.hw,
1559			},
1560			.num_parents = 1,
1561			.flags = CLK_SET_RATE_PARENT,
1562			.ops = &clk_branch2_ops,
1563		},
1564	},
1565};
1566
1567static struct clk_branch camcc_ipe_0_ahb_clk = {
1568	.halt_reg = 0x8040,
1569	.halt_check = BRANCH_HALT,
1570	.clkr = {
1571		.enable_reg = 0x8040,
1572		.enable_mask = BIT(0),
1573		.hw.init = &(const struct clk_init_data) {
1574			.name = "camcc_ipe_0_ahb_clk",
1575			.parent_hws = (const struct clk_hw*[]) {
1576				&camcc_slow_ahb_clk_src.clkr.hw,
1577			},
1578			.num_parents = 1,
1579			.flags = CLK_SET_RATE_PARENT,
1580			.ops = &clk_branch2_ops,
1581		},
1582	},
1583};
1584
1585static struct clk_branch camcc_ipe_0_areg_clk = {
1586	.halt_reg = 0x803c,
1587	.halt_check = BRANCH_HALT,
1588	.clkr = {
1589		.enable_reg = 0x803c,
1590		.enable_mask = BIT(0),
1591		.hw.init = &(const struct clk_init_data) {
1592			.name = "camcc_ipe_0_areg_clk",
1593			.parent_hws = (const struct clk_hw*[]) {
1594				&camcc_fast_ahb_clk_src.clkr.hw,
1595			},
1596			.num_parents = 1,
1597			.flags = CLK_SET_RATE_PARENT,
1598			.ops = &clk_branch2_ops,
1599		},
1600	},
1601};
1602
1603static struct clk_branch camcc_ipe_0_axi_clk = {
1604	.halt_reg = 0x8038,
1605	.halt_check = BRANCH_HALT,
1606	.clkr = {
1607		.enable_reg = 0x8038,
1608		.enable_mask = BIT(0),
1609		.hw.init = &(const struct clk_init_data) {
1610			.name = "camcc_ipe_0_axi_clk",
1611			.parent_hws = (const struct clk_hw*[]) {
1612				&camcc_camnoc_axi_clk_src.clkr.hw,
1613			},
1614			.num_parents = 1,
1615			.flags = CLK_SET_RATE_PARENT,
1616			.ops = &clk_branch2_ops,
1617		},
1618	},
1619};
1620
1621static struct clk_branch camcc_ipe_0_clk = {
1622	.halt_reg = 0x8028,
1623	.halt_check = BRANCH_HALT,
1624	.clkr = {
1625		.enable_reg = 0x8028,
1626		.enable_mask = BIT(0),
1627		.hw.init = &(const struct clk_init_data) {
1628			.name = "camcc_ipe_0_clk",
1629			.parent_hws = (const struct clk_hw*[]) {
1630				&camcc_ipe_0_clk_src.clkr.hw,
1631			},
1632			.num_parents = 1,
1633			.flags = CLK_SET_RATE_PARENT,
1634			.ops = &clk_branch2_ops,
1635		},
1636	},
1637};
1638
1639static struct clk_branch camcc_ipe_1_ahb_clk = {
1640	.halt_reg = 0x9028,
1641	.halt_check = BRANCH_HALT,
1642	.clkr = {
1643		.enable_reg = 0x9028,
1644		.enable_mask = BIT(0),
1645		.hw.init = &(const struct clk_init_data) {
1646			.name = "camcc_ipe_1_ahb_clk",
1647			.parent_hws = (const struct clk_hw*[]) {
1648				&camcc_slow_ahb_clk_src.clkr.hw,
1649			},
1650			.num_parents = 1,
1651			.flags = CLK_SET_RATE_PARENT,
1652			.ops = &clk_branch2_ops,
1653		},
1654	},
1655};
1656
1657static struct clk_branch camcc_ipe_1_areg_clk = {
1658	.halt_reg = 0x9024,
1659	.halt_check = BRANCH_HALT,
1660	.clkr = {
1661		.enable_reg = 0x9024,
1662		.enable_mask = BIT(0),
1663		.hw.init = &(const struct clk_init_data) {
1664			.name = "camcc_ipe_1_areg_clk",
1665			.parent_hws = (const struct clk_hw*[]) {
1666				&camcc_fast_ahb_clk_src.clkr.hw,
1667			},
1668			.num_parents = 1,
1669			.flags = CLK_SET_RATE_PARENT,
1670			.ops = &clk_branch2_ops,
1671		},
1672	},
1673};
1674
1675static struct clk_branch camcc_ipe_1_axi_clk = {
1676	.halt_reg = 0x9020,
1677	.halt_check = BRANCH_HALT,
1678	.clkr = {
1679		.enable_reg = 0x9020,
1680		.enable_mask = BIT(0),
1681		.hw.init = &(const struct clk_init_data) {
1682			.name = "camcc_ipe_1_axi_clk",
1683			.parent_hws = (const struct clk_hw*[]) {
1684				&camcc_camnoc_axi_clk_src.clkr.hw,
1685			},
1686			.num_parents = 1,
1687			.flags = CLK_SET_RATE_PARENT,
1688			.ops = &clk_branch2_ops,
1689		},
1690	},
1691};
1692
1693static struct clk_branch camcc_ipe_1_clk = {
1694	.halt_reg = 0x9010,
1695	.halt_check = BRANCH_HALT,
1696	.clkr = {
1697		.enable_reg = 0x9010,
1698		.enable_mask = BIT(0),
1699		.hw.init = &(const struct clk_init_data) {
1700			.name = "camcc_ipe_1_clk",
1701			.parent_hws = (const struct clk_hw*[]) {
1702				&camcc_ipe_0_clk_src.clkr.hw,
1703			},
1704			.num_parents = 1,
1705			.flags = CLK_SET_RATE_PARENT,
1706			.ops = &clk_branch2_ops,
1707		},
1708	},
1709};
1710
1711static struct clk_branch camcc_jpeg_clk = {
1712	.halt_reg = 0xc060,
1713	.halt_check = BRANCH_HALT,
1714	.clkr = {
1715		.enable_reg = 0xc060,
1716		.enable_mask = BIT(0),
1717		.hw.init = &(const struct clk_init_data) {
1718			.name = "camcc_jpeg_clk",
1719			.parent_hws = (const struct clk_hw*[]) {
1720				&camcc_jpeg_clk_src.clkr.hw,
1721			},
1722			.num_parents = 1,
1723			.flags = CLK_SET_RATE_PARENT,
1724			.ops = &clk_branch2_ops,
1725		},
1726	},
1727};
1728
1729static struct clk_branch camcc_lrme_clk = {
1730	.halt_reg = 0xc118,
1731	.halt_check = BRANCH_HALT,
1732	.clkr = {
1733		.enable_reg = 0xc118,
1734		.enable_mask = BIT(0),
1735		.hw.init = &(const struct clk_init_data) {
1736			.name = "camcc_lrme_clk",
1737			.parent_hws = (const struct clk_hw*[]) {
1738				&camcc_lrme_clk_src.clkr.hw,
1739			},
1740			.num_parents = 1,
1741			.flags = CLK_SET_RATE_PARENT,
1742			.ops = &clk_branch2_ops,
1743		},
1744	},
1745};
1746
1747static struct clk_branch camcc_mclk0_clk = {
1748	.halt_reg = 0x501c,
1749	.halt_check = BRANCH_HALT,
1750	.clkr = {
1751		.enable_reg = 0x501c,
1752		.enable_mask = BIT(0),
1753		.hw.init = &(const struct clk_init_data) {
1754			.name = "camcc_mclk0_clk",
1755			.parent_hws = (const struct clk_hw*[]) {
1756				&camcc_mclk0_clk_src.clkr.hw,
1757			},
1758			.num_parents = 1,
1759			.flags = CLK_SET_RATE_PARENT,
1760			.ops = &clk_branch2_ops,
1761		},
1762	},
1763};
1764
1765static struct clk_branch camcc_mclk1_clk = {
1766	.halt_reg = 0x503c,
1767	.halt_check = BRANCH_HALT,
1768	.clkr = {
1769		.enable_reg = 0x503c,
1770		.enable_mask = BIT(0),
1771		.hw.init = &(const struct clk_init_data) {
1772			.name = "camcc_mclk1_clk",
1773			.parent_hws = (const struct clk_hw*[]) {
1774				&camcc_mclk1_clk_src.clkr.hw,
1775			},
1776			.num_parents = 1,
1777			.flags = CLK_SET_RATE_PARENT,
1778			.ops = &clk_branch2_ops,
1779		},
1780	},
1781};
1782
1783static struct clk_branch camcc_mclk2_clk = {
1784	.halt_reg = 0x505c,
1785	.halt_check = BRANCH_HALT,
1786	.clkr = {
1787		.enable_reg = 0x505c,
1788		.enable_mask = BIT(0),
1789		.hw.init = &(const struct clk_init_data) {
1790			.name = "camcc_mclk2_clk",
1791			.parent_hws = (const struct clk_hw*[]) {
1792				&camcc_mclk2_clk_src.clkr.hw,
1793			},
1794			.num_parents = 1,
1795			.flags = CLK_SET_RATE_PARENT,
1796			.ops = &clk_branch2_ops,
1797		},
1798	},
1799};
1800
1801static struct clk_branch camcc_mclk3_clk = {
1802	.halt_reg = 0x507c,
1803	.halt_check = BRANCH_HALT,
1804	.clkr = {
1805		.enable_reg = 0x507c,
1806		.enable_mask = BIT(0),
1807		.hw.init = &(const struct clk_init_data) {
1808			.name = "camcc_mclk3_clk",
1809			.parent_hws = (const struct clk_hw*[]) {
1810				&camcc_mclk3_clk_src.clkr.hw,
1811			},
1812			.num_parents = 1,
1813			.flags = CLK_SET_RATE_PARENT,
1814			.ops = &clk_branch2_ops,
1815		},
1816	},
1817};
1818
1819static struct clk_branch camcc_sleep_clk = {
1820	.halt_reg = 0xc1bc,
1821	.halt_check = BRANCH_HALT,
1822	.clkr = {
1823		.enable_reg = 0xc1bc,
1824		.enable_mask = BIT(0),
1825		.hw.init = &(const struct clk_init_data) {
1826			.name = "camcc_sleep_clk",
1827			.parent_hws = (const struct clk_hw*[]) {
1828				&camcc_sleep_clk_src.clkr.hw,
1829			},
1830			.num_parents = 1,
1831			.flags = CLK_SET_RATE_PARENT,
1832			.ops = &clk_branch2_ops,
1833		},
1834	},
1835};
1836
1837static struct gdsc camcc_titan_top_gdsc;
1838
1839static struct gdsc camcc_bps_gdsc = {
1840	.gdscr = 0x7004,
1841	.pd = {
1842		.name = "camcc_bps_gdsc",
1843	},
1844	.flags = HW_CTRL | POLL_CFG_GDSCR,
1845	.parent = &camcc_titan_top_gdsc.pd,
1846	.pwrsts = PWRSTS_OFF_ON,
1847};
1848
1849static struct gdsc camcc_ife_0_gdsc = {
1850	.gdscr = 0xa004,
1851	.pd = {
1852		.name = "camcc_ife_0_gdsc",
1853	},
1854	.flags = POLL_CFG_GDSCR,
1855	.parent = &camcc_titan_top_gdsc.pd,
1856	.pwrsts = PWRSTS_OFF_ON,
1857};
1858
1859static struct gdsc camcc_ife_1_gdsc = {
1860	.gdscr = 0xb004,
1861	.pd = {
1862		.name = "camcc_ife_1_gdsc",
1863	},
1864	.flags = POLL_CFG_GDSCR,
1865	.parent = &camcc_titan_top_gdsc.pd,
1866	.pwrsts = PWRSTS_OFF_ON,
1867};
1868
1869static struct gdsc camcc_ipe_0_gdsc = {
1870	.gdscr = 0x8004,
1871	.pd = {
1872		.name = "camcc_ipe_0_gdsc",
1873	},
1874	.flags = HW_CTRL | POLL_CFG_GDSCR,
1875	.parent = &camcc_titan_top_gdsc.pd,
1876	.pwrsts = PWRSTS_OFF_ON,
1877};
1878
1879static struct gdsc camcc_ipe_1_gdsc = {
1880	.gdscr = 0x9004,
1881	.pd = {
1882		.name = "camcc_ipe_1_gdsc",
1883	},
1884	.flags = HW_CTRL | POLL_CFG_GDSCR,
1885	.parent = &camcc_titan_top_gdsc.pd,
1886	.pwrsts = PWRSTS_OFF_ON,
1887};
1888
1889static struct gdsc camcc_titan_top_gdsc = {
1890	.gdscr = 0xc1c4,
1891	.pd = {
1892		.name = "camcc_titan_top_gdsc",
1893	},
1894	.flags = POLL_CFG_GDSCR,
1895	.pwrsts = PWRSTS_OFF_ON,
1896};
1897
1898static struct clk_hw *camcc_sm7150_hws[] = {
1899	[CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.hw,
1900	[CAMCC_PLL0_OUT_ODD] = &camcc_pll0_out_odd.hw,
1901	[CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.hw,
1902	[CAMCC_PLL2_OUT_EARLY] = &camcc_pll2_out_early.hw,
1903	[CAMCC_PLL3_OUT_EVEN] = &camcc_pll3_out_even.hw,
1904	[CAMCC_PLL4_OUT_EVEN] = &camcc_pll4_out_even.hw,
1905};
1906
1907static struct clk_regmap *camcc_sm7150_clocks[] = {
1908	[CAMCC_BPS_AHB_CLK] = &camcc_bps_ahb_clk.clkr,
1909	[CAMCC_BPS_AREG_CLK] = &camcc_bps_areg_clk.clkr,
1910	[CAMCC_BPS_AXI_CLK] = &camcc_bps_axi_clk.clkr,
1911	[CAMCC_BPS_CLK] = &camcc_bps_clk.clkr,
1912	[CAMCC_BPS_CLK_SRC] = &camcc_bps_clk_src.clkr,
1913	[CAMCC_CAMNOC_AXI_CLK] = &camcc_camnoc_axi_clk.clkr,
1914	[CAMCC_CAMNOC_AXI_CLK_SRC] = &camcc_camnoc_axi_clk_src.clkr,
1915	[CAMCC_CAMNOC_DCD_XO_CLK] = &camcc_camnoc_dcd_xo_clk.clkr,
1916	[CAMCC_CCI_0_CLK] = &camcc_cci_0_clk.clkr,
1917	[CAMCC_CCI_0_CLK_SRC] = &camcc_cci_0_clk_src.clkr,
1918	[CAMCC_CCI_1_CLK] = &camcc_cci_1_clk.clkr,
1919	[CAMCC_CCI_1_CLK_SRC] = &camcc_cci_1_clk_src.clkr,
1920	[CAMCC_CORE_AHB_CLK] = &camcc_core_ahb_clk.clkr,
1921	[CAMCC_CPAS_AHB_CLK] = &camcc_cpas_ahb_clk.clkr,
1922	[CAMCC_CPHY_RX_CLK_SRC] = &camcc_cphy_rx_clk_src.clkr,
1923	[CAMCC_CSI0PHYTIMER_CLK] = &camcc_csi0phytimer_clk.clkr,
1924	[CAMCC_CSI0PHYTIMER_CLK_SRC] = &camcc_csi0phytimer_clk_src.clkr,
1925	[CAMCC_CSI1PHYTIMER_CLK] = &camcc_csi1phytimer_clk.clkr,
1926	[CAMCC_CSI1PHYTIMER_CLK_SRC] = &camcc_csi1phytimer_clk_src.clkr,
1927	[CAMCC_CSI2PHYTIMER_CLK] = &camcc_csi2phytimer_clk.clkr,
1928	[CAMCC_CSI2PHYTIMER_CLK_SRC] = &camcc_csi2phytimer_clk_src.clkr,
1929	[CAMCC_CSI3PHYTIMER_CLK] = &camcc_csi3phytimer_clk.clkr,
1930	[CAMCC_CSI3PHYTIMER_CLK_SRC] = &camcc_csi3phytimer_clk_src.clkr,
1931	[CAMCC_CSIPHY0_CLK] = &camcc_csiphy0_clk.clkr,
1932	[CAMCC_CSIPHY1_CLK] = &camcc_csiphy1_clk.clkr,
1933	[CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr,
1934	[CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr,
1935	[CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr,
1936	[CAMCC_FD_CORE_CLK] = &camcc_fd_core_clk.clkr,
1937	[CAMCC_FD_CORE_CLK_SRC] = &camcc_fd_core_clk_src.clkr,
1938	[CAMCC_FD_CORE_UAR_CLK] = &camcc_fd_core_uar_clk.clkr,
1939	[CAMCC_ICP_AHB_CLK] = &camcc_icp_ahb_clk.clkr,
1940	[CAMCC_ICP_CLK] = &camcc_icp_clk.clkr,
1941	[CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr,
1942	[CAMCC_IFE_0_AXI_CLK] = &camcc_ife_0_axi_clk.clkr,
1943	[CAMCC_IFE_0_CLK] = &camcc_ife_0_clk.clkr,
1944	[CAMCC_IFE_0_CLK_SRC] = &camcc_ife_0_clk_src.clkr,
1945	[CAMCC_IFE_0_CPHY_RX_CLK] = &camcc_ife_0_cphy_rx_clk.clkr,
1946	[CAMCC_IFE_0_CSID_CLK] = &camcc_ife_0_csid_clk.clkr,
1947	[CAMCC_IFE_0_CSID_CLK_SRC] = &camcc_ife_0_csid_clk_src.clkr,
1948	[CAMCC_IFE_0_DSP_CLK] = &camcc_ife_0_dsp_clk.clkr,
1949	[CAMCC_IFE_1_AXI_CLK] = &camcc_ife_1_axi_clk.clkr,
1950	[CAMCC_IFE_1_CLK] = &camcc_ife_1_clk.clkr,
1951	[CAMCC_IFE_1_CLK_SRC] = &camcc_ife_1_clk_src.clkr,
1952	[CAMCC_IFE_1_CPHY_RX_CLK] = &camcc_ife_1_cphy_rx_clk.clkr,
1953	[CAMCC_IFE_1_CSID_CLK] = &camcc_ife_1_csid_clk.clkr,
1954	[CAMCC_IFE_1_CSID_CLK_SRC] = &camcc_ife_1_csid_clk_src.clkr,
1955	[CAMCC_IFE_1_DSP_CLK] = &camcc_ife_1_dsp_clk.clkr,
1956	[CAMCC_IFE_LITE_CLK] = &camcc_ife_lite_clk.clkr,
1957	[CAMCC_IFE_LITE_CLK_SRC] = &camcc_ife_lite_clk_src.clkr,
1958	[CAMCC_IFE_LITE_CPHY_RX_CLK] = &camcc_ife_lite_cphy_rx_clk.clkr,
1959	[CAMCC_IFE_LITE_CSID_CLK] = &camcc_ife_lite_csid_clk.clkr,
1960	[CAMCC_IFE_LITE_CSID_CLK_SRC] = &camcc_ife_lite_csid_clk_src.clkr,
1961	[CAMCC_IPE_0_AHB_CLK] = &camcc_ipe_0_ahb_clk.clkr,
1962	[CAMCC_IPE_0_AREG_CLK] = &camcc_ipe_0_areg_clk.clkr,
1963	[CAMCC_IPE_0_AXI_CLK] = &camcc_ipe_0_axi_clk.clkr,
1964	[CAMCC_IPE_0_CLK] = &camcc_ipe_0_clk.clkr,
1965	[CAMCC_IPE_0_CLK_SRC] = &camcc_ipe_0_clk_src.clkr,
1966	[CAMCC_IPE_1_AHB_CLK] = &camcc_ipe_1_ahb_clk.clkr,
1967	[CAMCC_IPE_1_AREG_CLK] = &camcc_ipe_1_areg_clk.clkr,
1968	[CAMCC_IPE_1_AXI_CLK] = &camcc_ipe_1_axi_clk.clkr,
1969	[CAMCC_IPE_1_CLK] = &camcc_ipe_1_clk.clkr,
1970	[CAMCC_JPEG_CLK] = &camcc_jpeg_clk.clkr,
1971	[CAMCC_JPEG_CLK_SRC] = &camcc_jpeg_clk_src.clkr,
1972	[CAMCC_LRME_CLK] = &camcc_lrme_clk.clkr,
1973	[CAMCC_LRME_CLK_SRC] = &camcc_lrme_clk_src.clkr,
1974	[CAMCC_MCLK0_CLK] = &camcc_mclk0_clk.clkr,
1975	[CAMCC_MCLK0_CLK_SRC] = &camcc_mclk0_clk_src.clkr,
1976	[CAMCC_MCLK1_CLK] = &camcc_mclk1_clk.clkr,
1977	[CAMCC_MCLK1_CLK_SRC] = &camcc_mclk1_clk_src.clkr,
1978	[CAMCC_MCLK2_CLK] = &camcc_mclk2_clk.clkr,
1979	[CAMCC_MCLK2_CLK_SRC] = &camcc_mclk2_clk_src.clkr,
1980	[CAMCC_MCLK3_CLK] = &camcc_mclk3_clk.clkr,
1981	[CAMCC_MCLK3_CLK_SRC] = &camcc_mclk3_clk_src.clkr,
1982	[CAMCC_PLL0] = &camcc_pll0.clkr,
1983	[CAMCC_PLL1] = &camcc_pll1.clkr,
1984	[CAMCC_PLL2] = &camcc_pll2.clkr,
1985	[CAMCC_PLL2_OUT_AUX] = &camcc_pll2_out_aux.clkr,
1986	[CAMCC_PLL2_OUT_MAIN] = &camcc_pll2_out_main.clkr,
1987	[CAMCC_PLL3] = &camcc_pll3.clkr,
1988	[CAMCC_PLL4] = &camcc_pll4.clkr,
1989	[CAMCC_SLEEP_CLK] = &camcc_sleep_clk.clkr,
1990	[CAMCC_SLEEP_CLK_SRC] = &camcc_sleep_clk_src.clkr,
1991	[CAMCC_SLOW_AHB_CLK_SRC] = &camcc_slow_ahb_clk_src.clkr,
1992	[CAMCC_XO_CLK_SRC] = &camcc_xo_clk_src.clkr,
1993};
1994
1995static struct gdsc *camcc_sm7150_gdscs[] = {
1996	[BPS_GDSC] = &camcc_bps_gdsc,
1997	[IFE_0_GDSC] = &camcc_ife_0_gdsc,
1998	[IFE_1_GDSC] = &camcc_ife_1_gdsc,
1999	[IPE_0_GDSC] = &camcc_ipe_0_gdsc,
2000	[IPE_1_GDSC] = &camcc_ipe_1_gdsc,
2001	[TITAN_TOP_GDSC] = &camcc_titan_top_gdsc,
2002};
2003
2004static const struct regmap_config camcc_sm7150_regmap_config = {
2005	.reg_bits	= 32,
2006	.reg_stride	= 4,
2007	.val_bits	= 32,
2008	.max_register	= 0xd024,
2009	.fast_io	= true,
2010};
2011
2012static const struct qcom_cc_desc camcc_sm7150_desc = {
2013	.config = &camcc_sm7150_regmap_config,
2014	.clk_hws = camcc_sm7150_hws,
2015	.num_clk_hws = ARRAY_SIZE(camcc_sm7150_hws),
2016	.clks = camcc_sm7150_clocks,
2017	.num_clks = ARRAY_SIZE(camcc_sm7150_clocks),
2018	.gdscs = camcc_sm7150_gdscs,
2019	.num_gdscs = ARRAY_SIZE(camcc_sm7150_gdscs),
2020};
2021
2022static const struct of_device_id camcc_sm7150_match_table[] = {
2023	{ .compatible = "qcom,sm7150-camcc" },
2024	{ }
2025};
2026MODULE_DEVICE_TABLE(of, camcc_sm7150_match_table);
2027
2028static int camcc_sm7150_probe(struct platform_device *pdev)
2029{
2030	struct regmap *regmap;
2031
2032	regmap = qcom_cc_map(pdev, &camcc_sm7150_desc);
2033	if (IS_ERR(regmap))
2034		return PTR_ERR(regmap);
2035
2036	clk_fabia_pll_configure(&camcc_pll0, regmap, &camcc_pll0_config);
2037	clk_fabia_pll_configure(&camcc_pll1, regmap, &camcc_pll1_config);
2038	clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config);
2039	clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config);
2040	clk_fabia_pll_configure(&camcc_pll4, regmap, &camcc_pll3_config);
2041
2042	/* Keep some clocks always-on */
2043	qcom_branch_set_clk_en(regmap, 0xc1a0); /* CAMCC_GDSC_CLK */
2044
2045	return qcom_cc_really_probe(&pdev->dev, &camcc_sm7150_desc, regmap);
2046}
2047
2048static struct platform_driver camcc_sm7150_driver = {
2049	.probe = camcc_sm7150_probe,
2050	.driver = {
2051		.name = "camcc-sm7150",
2052		.of_match_table = camcc_sm7150_match_table,
2053	},
2054};
2055
2056module_platform_driver(camcc_sm7150_driver);
2057
2058MODULE_DESCRIPTION("Qualcomm SM7150 Camera Clock Controller");
2059MODULE_LICENSE("GPL");