a7-pll.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Qualcomm A7 PLL driver
  4 *
  5 * Copyright (c) 2020, Linaro Limited
  6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  7 */
  8
  9#include <linux/clk-provider.h>
 10#include <linux/module.h>
 11#include <linux/platform_device.h>
 12#include <linux/regmap.h>
 13
 14#include "clk-alpha-pll.h"
 15
 16#define LUCID_PLL_OFF_L_VAL 0x04
 17
 18static const struct pll_vco lucid_vco[] = {
 19	{ 249600000, 2000000000, 0 },
 20};
 21
 22static struct clk_alpha_pll a7pll = {
 23	.offset = 0x100,
 24	.vco_table = lucid_vco,
 25	.num_vco = ARRAY_SIZE(lucid_vco),
 26	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 27	.clkr = {
 28		.hw.init = &(struct clk_init_data){
 29			.name = "a7pll",
 30			.parent_data = &(const struct clk_parent_data){
 31				.fw_name = "bi_tcxo",
 32			},
 33			.num_parents = 1,
 34			.ops = &clk_alpha_pll_lucid_ops,
 35		},
 36	},
 37};
 38
 39static const struct alpha_pll_config a7pll_config = {
 40	.l = 0x39,
 41	.config_ctl_val = 0x20485699,
 42	.config_ctl_hi_val = 0x2261,
 43	.config_ctl_hi1_val = 0x029A699C,
 44	.user_ctl_val = 0x1,
 45	.user_ctl_hi_val = 0x805,
 46};
 47
 48static const struct regmap_config a7pll_regmap_config = {
 49	.reg_bits		= 32,
 50	.reg_stride		= 4,
 51	.val_bits		= 32,
 52	.max_register		= 0x1000,
 53};
 54
 55static int qcom_a7pll_probe(struct platform_device *pdev)
 56{
 57	struct device *dev = &pdev->dev;
 58	struct regmap *regmap;
 59	void __iomem *base;
 60	u32 l_val;
 61	int ret;
 62
 63	base = devm_platform_ioremap_resource(pdev, 0);
 64	if (IS_ERR(base))
 65		return PTR_ERR(base);
 66
 67	regmap = devm_regmap_init_mmio(dev, base, &a7pll_regmap_config);
 68	if (IS_ERR(regmap))
 69		return PTR_ERR(regmap);
 70
 71	/* Configure PLL only if the l_val is zero */
 72	regmap_read(regmap, a7pll.offset + LUCID_PLL_OFF_L_VAL, &l_val);
 73	if (!l_val)
 74		clk_lucid_pll_configure(&a7pll, regmap, &a7pll_config);
 75
 76	ret = devm_clk_register_regmap(dev, &a7pll.clkr);
 77	if (ret)
 78		return ret;
 79
 80	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
 81					   &a7pll.clkr.hw);
 82}
 83
 84static const struct of_device_id qcom_a7pll_match_table[] = {
 85	{ .compatible = "qcom,sdx55-a7pll" },
 86	{ }
 87};
 88MODULE_DEVICE_TABLE(of, qcom_a7pll_match_table);
 89
 90static struct platform_driver qcom_a7pll_driver = {
 91	.probe = qcom_a7pll_probe,
 92	.driver = {
 93		.name = "qcom-a7pll",
 94		.of_match_table = qcom_a7pll_match_table,
 95	},
 96};
 97module_platform_driver(qcom_a7pll_driver);
 98
 99MODULE_DESCRIPTION("Qualcomm A7 PLL Driver");
100MODULE_LICENSE("GPL v2");