a53-pll.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Qualcomm A53 PLL driver
  4 *
  5 * Copyright (c) 2017, Linaro Limited
  6 * Author: Georgi Djakov <georgi.djakov@linaro.org>
  7 */
  8
  9#include <linux/clk.h>
 10#include <linux/clk-provider.h>
 11#include <linux/kernel.h>
 12#include <linux/platform_device.h>
 13#include <linux/pm_opp.h>
 14#include <linux/regmap.h>
 15#include <linux/module.h>
 16
 17#include "clk-pll.h"
 18#include "clk-regmap.h"
 19
 20static const struct pll_freq_tbl a53pll_freq[] = {
 21	{  998400000, 52, 0x0, 0x1, 0 },
 22	{ 1094400000, 57, 0x0, 0x1, 0 },
 23	{ 1152000000, 62, 0x0, 0x1, 0 },
 24	{ 1209600000, 63, 0x0, 0x1, 0 },
 25	{ 1248000000, 65, 0x0, 0x1, 0 },
 26	{ 1363200000, 71, 0x0, 0x1, 0 },
 27	{ 1401600000, 73, 0x0, 0x1, 0 },
 28	{ }
 29};
 30
 31static const struct regmap_config a53pll_regmap_config = {
 32	.reg_bits		= 32,
 33	.reg_stride		= 4,
 34	.val_bits		= 32,
 35	.max_register		= 0x40,
 36};
 37
 38static struct pll_freq_tbl *qcom_a53pll_get_freq_tbl(struct device *dev)
 39{
 40	struct pll_freq_tbl *freq_tbl;
 41	unsigned long xo_freq;
 42	unsigned long freq;
 43	struct clk *xo_clk;
 44	int count;
 45	int ret;
 46	int i;
 47
 48	xo_clk = devm_clk_get(dev, "xo");
 49	if (IS_ERR(xo_clk))
 50		return NULL;
 51
 52	xo_freq = clk_get_rate(xo_clk);
 53
 54	ret = devm_pm_opp_of_add_table(dev);
 55	if (ret)
 56		return NULL;
 57
 58	count = dev_pm_opp_get_opp_count(dev);
 59	if (count <= 0)
 60		return NULL;
 61
 62	freq_tbl = devm_kcalloc(dev, count + 1, sizeof(*freq_tbl), GFP_KERNEL);
 63	if (!freq_tbl)
 64		return NULL;
 65
 66	for (i = 0, freq = 0; i < count; i++, freq++) {
 67		struct dev_pm_opp *opp;
 68
 69		opp = dev_pm_opp_find_freq_ceil(dev, &freq);
 70		if (IS_ERR(opp))
 71			return NULL;
 72
 73		/* Skip the freq that is not divisible */
 74		if (freq % xo_freq)
 75			continue;
 76
 77		freq_tbl[i].freq = freq;
 78		freq_tbl[i].l = freq / xo_freq;
 79		freq_tbl[i].n = 1;
 80
 81		dev_pm_opp_put(opp);
 82	}
 83
 84	return freq_tbl;
 85}
 86
 87static int qcom_a53pll_probe(struct platform_device *pdev)
 88{
 89	struct device *dev = &pdev->dev;
 90	struct device_node *np = dev->of_node;
 91	struct regmap *regmap;
 92	struct clk_pll *pll;
 93	void __iomem *base;
 94	struct clk_init_data init = { };
 95	int ret;
 96
 97	pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
 98	if (!pll)
 99		return -ENOMEM;
100
101	base = devm_platform_ioremap_resource(pdev, 0);
102	if (IS_ERR(base))
103		return PTR_ERR(base);
104
105	regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config);
106	if (IS_ERR(regmap))
107		return PTR_ERR(regmap);
108
109	pll->l_reg = 0x04;
110	pll->m_reg = 0x08;
111	pll->n_reg = 0x0c;
112	pll->config_reg = 0x14;
113	pll->mode_reg = 0x00;
114	pll->status_reg = 0x1c;
115	pll->status_bit = 16;
116
117	pll->freq_tbl = qcom_a53pll_get_freq_tbl(dev);
118	if (!pll->freq_tbl) {
119		/* Fall on a53pll_freq if no freq_tbl is found from OPP */
120		pll->freq_tbl = a53pll_freq;
121	}
122
123	/* Use an unique name by appending @unit-address */
124	init.name = devm_kasprintf(dev, GFP_KERNEL, "a53pll%s",
125				   strchrnul(np->full_name, '@'));
126	if (!init.name)
127		return -ENOMEM;
128
129	init.parent_data = &(const struct clk_parent_data){
130		.fw_name = "xo", .name = "xo_board",
131	};
132	init.num_parents = 1;
133	init.ops = &clk_pll_sr2_ops;
134	pll->clkr.hw.init = &init;
135
136	ret = devm_clk_register_regmap(dev, &pll->clkr);
137	if (ret) {
138		dev_err(dev, "failed to register regmap clock: %d\n", ret);
139		return ret;
140	}
141
142	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
143					  &pll->clkr.hw);
144	if (ret) {
145		dev_err(dev, "failed to add clock provider: %d\n", ret);
146		return ret;
147	}
148
149	return 0;
150}
151
152static const struct of_device_id qcom_a53pll_match_table[] = {
153	{ .compatible = "qcom,msm8226-a7pll" },
154	{ .compatible = "qcom,msm8916-a53pll" },
155	{ .compatible = "qcom,msm8939-a53pll" },
156	{ }
157};
158MODULE_DEVICE_TABLE(of, qcom_a53pll_match_table);
159
160static struct platform_driver qcom_a53pll_driver = {
161	.probe = qcom_a53pll_probe,
162	.driver = {
163		.name = "qcom-a53pll",
164		.of_match_table = qcom_a53pll_match_table,
165	},
166};
167module_platform_driver(qcom_a53pll_driver);
168
169MODULE_DESCRIPTION("Qualcomm A53 PLL Driver");
170MODULE_LICENSE("GPL v2");