clk-lpc32xx.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
   4 */
   5
   6#include <linux/clk.h>
   7#include <linux/clk-provider.h>
   8#include <linux/io.h>
   9#include <linux/of_address.h>
  10#include <linux/regmap.h>
  11
  12#include <dt-bindings/clock/lpc32xx-clock.h>
  13
  14#undef pr_fmt
  15#define pr_fmt(fmt) "%s: " fmt, __func__
  16
  17/* Common bitfield definitions for x397 PLL (lock), USB PLL and HCLK PLL */
  18#define PLL_CTRL_ENABLE			BIT(16)
  19#define PLL_CTRL_BYPASS			BIT(15)
  20#define PLL_CTRL_DIRECT			BIT(14)
  21#define PLL_CTRL_FEEDBACK		BIT(13)
  22#define PLL_CTRL_POSTDIV		(BIT(12)|BIT(11))
  23#define PLL_CTRL_PREDIV			(BIT(10)|BIT(9))
  24#define PLL_CTRL_FEEDDIV		(0xFF << 1)
  25#define PLL_CTRL_LOCK			BIT(0)
  26
  27/* Clock registers on System Control Block */
  28#define LPC32XX_CLKPWR_DEBUG_CTRL	0x00
  29#define LPC32XX_CLKPWR_USB_DIV		0x1C
  30#define LPC32XX_CLKPWR_HCLKDIV_CTRL	0x40
  31#define LPC32XX_CLKPWR_PWR_CTRL		0x44
  32#define LPC32XX_CLKPWR_PLL397_CTRL	0x48
  33#define LPC32XX_CLKPWR_OSC_CTRL		0x4C
  34#define LPC32XX_CLKPWR_SYSCLK_CTRL	0x50
  35#define LPC32XX_CLKPWR_LCDCLK_CTRL	0x54
  36#define LPC32XX_CLKPWR_HCLKPLL_CTRL	0x58
  37#define LPC32XX_CLKPWR_ADCCLK_CTRL1	0x60
  38#define LPC32XX_CLKPWR_USB_CTRL		0x64
  39#define LPC32XX_CLKPWR_SSP_CTRL		0x78
  40#define LPC32XX_CLKPWR_I2S_CTRL		0x7C
  41#define LPC32XX_CLKPWR_MS_CTRL		0x80
  42#define LPC32XX_CLKPWR_MACCLK_CTRL	0x90
  43#define LPC32XX_CLKPWR_TEST_CLK_CTRL	0xA4
  44#define LPC32XX_CLKPWR_I2CCLK_CTRL	0xAC
  45#define LPC32XX_CLKPWR_KEYCLK_CTRL	0xB0
  46#define LPC32XX_CLKPWR_ADCCLK_CTRL	0xB4
  47#define LPC32XX_CLKPWR_PWMCLK_CTRL	0xB8
  48#define LPC32XX_CLKPWR_TIMCLK_CTRL	0xBC
  49#define LPC32XX_CLKPWR_TIMCLK_CTRL1	0xC0
  50#define LPC32XX_CLKPWR_SPI_CTRL		0xC4
  51#define LPC32XX_CLKPWR_FLASHCLK_CTRL	0xC8
  52#define LPC32XX_CLKPWR_UART3_CLK_CTRL	0xD0
  53#define LPC32XX_CLKPWR_UART4_CLK_CTRL	0xD4
  54#define LPC32XX_CLKPWR_UART5_CLK_CTRL	0xD8
  55#define LPC32XX_CLKPWR_UART6_CLK_CTRL	0xDC
  56#define LPC32XX_CLKPWR_IRDA_CLK_CTRL	0xE0
  57#define LPC32XX_CLKPWR_UART_CLK_CTRL	0xE4
  58#define LPC32XX_CLKPWR_DMA_CLK_CTRL	0xE8
  59
  60/* Clock registers on USB controller */
  61#define LPC32XX_USB_CLK_CTRL		0xF4
  62#define LPC32XX_USB_CLK_STS		0xF8
  63
  64static const struct regmap_config lpc32xx_scb_regmap_config = {
  65	.name = "scb",
  66	.reg_bits = 32,
  67	.val_bits = 32,
  68	.reg_stride = 4,
  69	.val_format_endian = REGMAP_ENDIAN_LITTLE,
  70	.max_register = 0x114,
  71};
  72
  73static struct regmap *clk_regmap;
  74static void __iomem *usb_clk_vbase;
  75
  76enum {
  77	LPC32XX_USB_CLK_OTG = LPC32XX_USB_CLK_HOST + 1,
  78	LPC32XX_USB_CLK_AHB,
  79
  80	LPC32XX_USB_CLK_MAX = LPC32XX_USB_CLK_AHB + 1,
  81};
  82
  83enum {
  84	/* Start from the last defined clock in dt bindings */
  85	LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_PERIPH + 1,
  86	LPC32XX_CLK_ADC_RTC,
  87	LPC32XX_CLK_TEST1,
  88	LPC32XX_CLK_TEST2,
  89
  90	/* System clocks, PLL 397x and HCLK PLL clocks */
  91	LPC32XX_CLK_OSC,
  92	LPC32XX_CLK_SYS,
  93	LPC32XX_CLK_PLL397X,
  94	LPC32XX_CLK_HCLK_DIV_PERIPH,
  95	LPC32XX_CLK_HCLK_DIV,
  96	LPC32XX_CLK_HCLK,
  97	LPC32XX_CLK_ARM,
  98	LPC32XX_CLK_ARM_VFP,
  99
 100	/* USB clocks */
 101	LPC32XX_CLK_USB_PLL,
 102	LPC32XX_CLK_USB_DIV,
 103	LPC32XX_CLK_USB,
 104
 105	/* Only one control PWR_CTRL[10] for both muxes */
 106	LPC32XX_CLK_PERIPH_HCLK_MUX,
 107	LPC32XX_CLK_PERIPH_ARM_MUX,
 108
 109	/* Only one control PWR_CTRL[2] for all three muxes */
 110	LPC32XX_CLK_SYSCLK_PERIPH_MUX,
 111	LPC32XX_CLK_SYSCLK_HCLK_MUX,
 112	LPC32XX_CLK_SYSCLK_ARM_MUX,
 113
 114	/* Two clock sources external to the driver */
 115	LPC32XX_CLK_XTAL_32K,
 116	LPC32XX_CLK_XTAL,
 117
 118	/* Renumbered USB clocks, may have a parent from SCB table */
 119	LPC32XX_CLK_USB_OFFSET,
 120	LPC32XX_CLK_USB_I2C = LPC32XX_USB_CLK_I2C + LPC32XX_CLK_USB_OFFSET,
 121	LPC32XX_CLK_USB_DEV = LPC32XX_USB_CLK_DEVICE + LPC32XX_CLK_USB_OFFSET,
 122	LPC32XX_CLK_USB_HOST = LPC32XX_USB_CLK_HOST + LPC32XX_CLK_USB_OFFSET,
 123	LPC32XX_CLK_USB_OTG = LPC32XX_USB_CLK_OTG + LPC32XX_CLK_USB_OFFSET,
 124	LPC32XX_CLK_USB_AHB = LPC32XX_USB_CLK_AHB + LPC32XX_CLK_USB_OFFSET,
 125
 126	/* Stub for composite clocks */
 127	LPC32XX_CLK__NULL,
 128
 129	/* Subclocks of composite clocks, clocks above are for CCF */
 130	LPC32XX_CLK_PWM1_MUX,
 131	LPC32XX_CLK_PWM1_DIV,
 132	LPC32XX_CLK_PWM1_GATE,
 133	LPC32XX_CLK_PWM2_MUX,
 134	LPC32XX_CLK_PWM2_DIV,
 135	LPC32XX_CLK_PWM2_GATE,
 136	LPC32XX_CLK_UART3_MUX,
 137	LPC32XX_CLK_UART3_DIV,
 138	LPC32XX_CLK_UART3_GATE,
 139	LPC32XX_CLK_UART4_MUX,
 140	LPC32XX_CLK_UART4_DIV,
 141	LPC32XX_CLK_UART4_GATE,
 142	LPC32XX_CLK_UART5_MUX,
 143	LPC32XX_CLK_UART5_DIV,
 144	LPC32XX_CLK_UART5_GATE,
 145	LPC32XX_CLK_UART6_MUX,
 146	LPC32XX_CLK_UART6_DIV,
 147	LPC32XX_CLK_UART6_GATE,
 148	LPC32XX_CLK_TEST1_MUX,
 149	LPC32XX_CLK_TEST1_GATE,
 150	LPC32XX_CLK_TEST2_MUX,
 151	LPC32XX_CLK_TEST2_GATE,
 152	LPC32XX_CLK_USB_DIV_DIV,
 153	LPC32XX_CLK_USB_DIV_GATE,
 154	LPC32XX_CLK_SD_DIV,
 155	LPC32XX_CLK_SD_GATE,
 156	LPC32XX_CLK_LCD_DIV,
 157	LPC32XX_CLK_LCD_GATE,
 158
 159	LPC32XX_CLK_HW_MAX,
 160	LPC32XX_CLK_MAX = LPC32XX_CLK_SYSCLK_ARM_MUX + 1,
 161	LPC32XX_CLK_CCF_MAX = LPC32XX_CLK_USB_AHB + 1,
 162};
 163
 164static struct clk *clk[LPC32XX_CLK_MAX];
 165static struct clk_onecell_data clk_data = {
 166	.clks = clk,
 167	.clk_num = LPC32XX_CLK_MAX,
 168};
 169
 170static struct clk *usb_clk[LPC32XX_USB_CLK_MAX];
 171static struct clk_onecell_data usb_clk_data = {
 172	.clks = usb_clk,
 173	.clk_num = LPC32XX_USB_CLK_MAX,
 174};
 175
 176#define LPC32XX_CLK_PARENTS_MAX			5
 177
 178struct clk_proto_t {
 179	const char *name;
 180	const u8 parents[LPC32XX_CLK_PARENTS_MAX];
 181	u8 num_parents;
 182	unsigned long flags;
 183};
 184
 185#define CLK_PREFIX(LITERAL)		LPC32XX_CLK_ ## LITERAL
 186#define NUMARGS(...)	(sizeof((int[]){__VA_ARGS__})/sizeof(int))
 187
 188#define LPC32XX_CLK_DEFINE(_idx, _name, _flags, ...)		\
 189	[CLK_PREFIX(_idx)] = {					\
 190		.name = _name,					\
 191		.flags = _flags,				\
 192		.parents = { __VA_ARGS__ },			\
 193		.num_parents = NUMARGS(__VA_ARGS__),		\
 194	 }
 195
 196static const struct clk_proto_t clk_proto[LPC32XX_CLK_CCF_MAX] __initconst = {
 197	LPC32XX_CLK_DEFINE(XTAL, "xtal", 0x0),
 198	LPC32XX_CLK_DEFINE(XTAL_32K, "xtal_32k", 0x0),
 199
 200	LPC32XX_CLK_DEFINE(RTC, "rtc", 0x0, LPC32XX_CLK_XTAL_32K),
 201	LPC32XX_CLK_DEFINE(OSC, "osc", CLK_IGNORE_UNUSED, LPC32XX_CLK_XTAL),
 202	LPC32XX_CLK_DEFINE(SYS, "sys", CLK_IGNORE_UNUSED,
 203		LPC32XX_CLK_OSC, LPC32XX_CLK_PLL397X),
 204	LPC32XX_CLK_DEFINE(PLL397X, "pll_397x", CLK_IGNORE_UNUSED,
 205		LPC32XX_CLK_RTC),
 206	LPC32XX_CLK_DEFINE(HCLK_PLL, "hclk_pll", CLK_IGNORE_UNUSED,
 207		LPC32XX_CLK_SYS),
 208	LPC32XX_CLK_DEFINE(HCLK_DIV_PERIPH, "hclk_div_periph",
 209		CLK_IGNORE_UNUSED, LPC32XX_CLK_HCLK_PLL),
 210	LPC32XX_CLK_DEFINE(HCLK_DIV, "hclk_div", CLK_IGNORE_UNUSED,
 211		LPC32XX_CLK_HCLK_PLL),
 212	LPC32XX_CLK_DEFINE(HCLK, "hclk", CLK_IGNORE_UNUSED,
 213		LPC32XX_CLK_PERIPH_HCLK_MUX),
 214	LPC32XX_CLK_DEFINE(PERIPH, "pclk", CLK_IGNORE_UNUSED,
 215		LPC32XX_CLK_SYSCLK_PERIPH_MUX),
 216	LPC32XX_CLK_DEFINE(ARM, "arm", CLK_IGNORE_UNUSED,
 217		LPC32XX_CLK_PERIPH_ARM_MUX),
 218
 219	LPC32XX_CLK_DEFINE(PERIPH_HCLK_MUX, "periph_hclk_mux",
 220		CLK_IGNORE_UNUSED,
 221		LPC32XX_CLK_SYSCLK_HCLK_MUX, LPC32XX_CLK_SYSCLK_PERIPH_MUX),
 222	LPC32XX_CLK_DEFINE(PERIPH_ARM_MUX, "periph_arm_mux", CLK_IGNORE_UNUSED,
 223		LPC32XX_CLK_SYSCLK_ARM_MUX, LPC32XX_CLK_SYSCLK_PERIPH_MUX),
 224	LPC32XX_CLK_DEFINE(SYSCLK_PERIPH_MUX, "sysclk_periph_mux",
 225		CLK_IGNORE_UNUSED,
 226		LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_DIV_PERIPH),
 227	LPC32XX_CLK_DEFINE(SYSCLK_HCLK_MUX, "sysclk_hclk_mux",
 228		CLK_IGNORE_UNUSED,
 229		LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_DIV),
 230	LPC32XX_CLK_DEFINE(SYSCLK_ARM_MUX, "sysclk_arm_mux", CLK_IGNORE_UNUSED,
 231		LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_PLL),
 232
 233	LPC32XX_CLK_DEFINE(ARM_VFP, "vfp9", CLK_IGNORE_UNUSED,
 234		LPC32XX_CLK_ARM),
 235	LPC32XX_CLK_DEFINE(USB_PLL, "usb_pll",
 236		CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, LPC32XX_CLK_USB_DIV),
 237	LPC32XX_CLK_DEFINE(USB_DIV, "usb_div", 0x0, LPC32XX_CLK_OSC),
 238	LPC32XX_CLK_DEFINE(USB, "usb", 0x0, LPC32XX_CLK_USB_PLL),
 239	LPC32XX_CLK_DEFINE(DMA, "dma", 0x0, LPC32XX_CLK_HCLK),
 240	LPC32XX_CLK_DEFINE(MLC, "mlc", 0x0, LPC32XX_CLK_HCLK),
 241	LPC32XX_CLK_DEFINE(SLC, "slc", 0x0, LPC32XX_CLK_HCLK),
 242	LPC32XX_CLK_DEFINE(LCD, "lcd", 0x0, LPC32XX_CLK_HCLK),
 243	LPC32XX_CLK_DEFINE(MAC, "mac", 0x0, LPC32XX_CLK_HCLK),
 244	LPC32XX_CLK_DEFINE(SD, "sd", 0x0, LPC32XX_CLK_ARM),
 245	LPC32XX_CLK_DEFINE(DDRAM, "ddram", CLK_GET_RATE_NOCACHE,
 246		LPC32XX_CLK_SYSCLK_ARM_MUX),
 247	LPC32XX_CLK_DEFINE(SSP0, "ssp0", 0x0, LPC32XX_CLK_HCLK),
 248	LPC32XX_CLK_DEFINE(SSP1, "ssp1", 0x0, LPC32XX_CLK_HCLK),
 249
 250	/*
 251	 * CLK_GET_RATE_NOCACHE is needed, if UART clock is disabled, its
 252	 * divider register does not contain information about selected rate.
 253	 */
 254	LPC32XX_CLK_DEFINE(UART3, "uart3", CLK_GET_RATE_NOCACHE,
 255		LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
 256	LPC32XX_CLK_DEFINE(UART4, "uart4", CLK_GET_RATE_NOCACHE,
 257		LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
 258	LPC32XX_CLK_DEFINE(UART5, "uart5", CLK_GET_RATE_NOCACHE,
 259		LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
 260	LPC32XX_CLK_DEFINE(UART6, "uart6", CLK_GET_RATE_NOCACHE,
 261		LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
 262	LPC32XX_CLK_DEFINE(IRDA, "irda", 0x0, LPC32XX_CLK_PERIPH),
 263	LPC32XX_CLK_DEFINE(I2C1, "i2c1", 0x0, LPC32XX_CLK_HCLK),
 264	LPC32XX_CLK_DEFINE(I2C2, "i2c2", 0x0, LPC32XX_CLK_HCLK),
 265	LPC32XX_CLK_DEFINE(TIMER0, "timer0", 0x0, LPC32XX_CLK_PERIPH),
 266	LPC32XX_CLK_DEFINE(TIMER1, "timer1", 0x0, LPC32XX_CLK_PERIPH),
 267	LPC32XX_CLK_DEFINE(TIMER2, "timer2", 0x0, LPC32XX_CLK_PERIPH),
 268	LPC32XX_CLK_DEFINE(TIMER3, "timer3", 0x0, LPC32XX_CLK_PERIPH),
 269	LPC32XX_CLK_DEFINE(TIMER4, "timer4", 0x0, LPC32XX_CLK_PERIPH),
 270	LPC32XX_CLK_DEFINE(TIMER5, "timer5", 0x0, LPC32XX_CLK_PERIPH),
 271	LPC32XX_CLK_DEFINE(WDOG, "watchdog", 0x0, LPC32XX_CLK_PERIPH),
 272	LPC32XX_CLK_DEFINE(I2S0, "i2s0", 0x0, LPC32XX_CLK_HCLK),
 273	LPC32XX_CLK_DEFINE(I2S1, "i2s1", 0x0, LPC32XX_CLK_HCLK),
 274	LPC32XX_CLK_DEFINE(SPI1, "spi1", 0x0, LPC32XX_CLK_HCLK),
 275	LPC32XX_CLK_DEFINE(SPI2, "spi2", 0x0, LPC32XX_CLK_HCLK),
 276	LPC32XX_CLK_DEFINE(MCPWM, "mcpwm", 0x0, LPC32XX_CLK_HCLK),
 277	LPC32XX_CLK_DEFINE(HSTIMER, "hstimer", 0x0, LPC32XX_CLK_PERIPH),
 278	LPC32XX_CLK_DEFINE(KEY, "key", 0x0, LPC32XX_CLK_RTC),
 279	LPC32XX_CLK_DEFINE(PWM1, "pwm1", 0x0,
 280		LPC32XX_CLK_RTC, LPC32XX_CLK_PERIPH),
 281	LPC32XX_CLK_DEFINE(PWM2, "pwm2", 0x0,
 282		LPC32XX_CLK_RTC, LPC32XX_CLK_PERIPH),
 283	LPC32XX_CLK_DEFINE(ADC, "adc", 0x0,
 284		LPC32XX_CLK_ADC_RTC, LPC32XX_CLK_ADC_DIV),
 285	LPC32XX_CLK_DEFINE(ADC_DIV, "adc_div", 0x0, LPC32XX_CLK_PERIPH),
 286	LPC32XX_CLK_DEFINE(ADC_RTC, "adc_rtc", 0x0, LPC32XX_CLK_RTC),
 287	LPC32XX_CLK_DEFINE(TEST1, "test1", 0x0,
 288		LPC32XX_CLK_PERIPH, LPC32XX_CLK_RTC, LPC32XX_CLK_OSC),
 289	LPC32XX_CLK_DEFINE(TEST2, "test2", 0x0,
 290		LPC32XX_CLK_HCLK, LPC32XX_CLK_PERIPH, LPC32XX_CLK_USB,
 291		LPC32XX_CLK_OSC, LPC32XX_CLK_PLL397X),
 292
 293	/* USB controller clocks */
 294	LPC32XX_CLK_DEFINE(USB_AHB, "usb_ahb", 0x0, LPC32XX_CLK_USB),
 295	LPC32XX_CLK_DEFINE(USB_OTG, "usb_otg", 0x0, LPC32XX_CLK_USB_AHB),
 296	LPC32XX_CLK_DEFINE(USB_I2C, "usb_i2c", 0x0, LPC32XX_CLK_USB_AHB),
 297	LPC32XX_CLK_DEFINE(USB_DEV, "usb_dev", 0x0, LPC32XX_CLK_USB_OTG),
 298	LPC32XX_CLK_DEFINE(USB_HOST, "usb_host", 0x0, LPC32XX_CLK_USB_OTG),
 299};
 300
 301struct lpc32xx_clk {
 302	struct clk_hw hw;
 303	u32 reg;
 304	u32 enable;
 305	u32 enable_mask;
 306	u32 disable;
 307	u32 disable_mask;
 308	u32 busy;
 309	u32 busy_mask;
 310};
 311
 312enum clk_pll_mode {
 313	PLL_UNKNOWN,
 314	PLL_DIRECT,
 315	PLL_BYPASS,
 316	PLL_DIRECT_BYPASS,
 317	PLL_INTEGER,
 318	PLL_NON_INTEGER,
 319};
 320
 321struct lpc32xx_pll_clk {
 322	struct clk_hw hw;
 323	u32 reg;
 324	u32 enable;
 325	unsigned long m_div;
 326	unsigned long n_div;
 327	unsigned long p_div;
 328	enum clk_pll_mode mode;
 329};
 330
 331struct lpc32xx_usb_clk {
 332	struct clk_hw hw;
 333	u32 ctrl_enable;
 334	u32 ctrl_disable;
 335	u32 ctrl_mask;
 336	u32 enable;
 337	u32 busy;
 338};
 339
 340struct lpc32xx_clk_mux {
 341	struct clk_hw	hw;
 342	u32		reg;
 343	u32		mask;
 344	u8		shift;
 345	u32		*table;
 346	u8		flags;
 347};
 348
 349struct lpc32xx_clk_div {
 350	struct clk_hw	hw;
 351	u32		reg;
 352	u8		shift;
 353	u8		width;
 354	const struct clk_div_table	*table;
 355	u8		flags;
 356};
 357
 358struct lpc32xx_clk_gate {
 359	struct clk_hw	hw;
 360	u32		reg;
 361	u8		bit_idx;
 362	u8		flags;
 363};
 364
 365#define to_lpc32xx_clk(_hw)	container_of(_hw, struct lpc32xx_clk, hw)
 366#define to_lpc32xx_pll_clk(_hw)	container_of(_hw, struct lpc32xx_pll_clk, hw)
 367#define to_lpc32xx_usb_clk(_hw)	container_of(_hw, struct lpc32xx_usb_clk, hw)
 368#define to_lpc32xx_mux(_hw)	container_of(_hw, struct lpc32xx_clk_mux, hw)
 369#define to_lpc32xx_div(_hw)	container_of(_hw, struct lpc32xx_clk_div, hw)
 370#define to_lpc32xx_gate(_hw)	container_of(_hw, struct lpc32xx_clk_gate, hw)
 371
 372static inline bool pll_is_valid(u64 val0, u64 val1, u64 min, u64 max)
 373{
 374	return (val0 >= (val1 * min) && val0 <= (val1 * max));
 375}
 376
 377static inline u32 lpc32xx_usb_clk_read(struct lpc32xx_usb_clk *clk)
 378{
 379	return readl(usb_clk_vbase + LPC32XX_USB_CLK_STS);
 380}
 381
 382static inline void lpc32xx_usb_clk_write(struct lpc32xx_usb_clk *clk, u32 val)
 383{
 384	writel(val, usb_clk_vbase + LPC32XX_USB_CLK_CTRL);
 385}
 386
 387static int clk_mask_enable(struct clk_hw *hw)
 388{
 389	struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
 390	u32 val;
 391
 392	regmap_read(clk_regmap, clk->reg, &val);
 393
 394	if (clk->busy_mask && (val & clk->busy_mask) == clk->busy)
 395		return -EBUSY;
 396
 397	return regmap_update_bits(clk_regmap, clk->reg,
 398				  clk->enable_mask, clk->enable);
 399}
 400
 401static void clk_mask_disable(struct clk_hw *hw)
 402{
 403	struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
 404
 405	regmap_update_bits(clk_regmap, clk->reg,
 406			   clk->disable_mask, clk->disable);
 407}
 408
 409static int clk_mask_is_enabled(struct clk_hw *hw)
 410{
 411	struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
 412	u32 val;
 413
 414	regmap_read(clk_regmap, clk->reg, &val);
 415
 416	return ((val & clk->enable_mask) == clk->enable);
 417}
 418
 419static const struct clk_ops clk_mask_ops = {
 420	.enable = clk_mask_enable,
 421	.disable = clk_mask_disable,
 422	.is_enabled = clk_mask_is_enabled,
 423};
 424
 425static int clk_pll_enable(struct clk_hw *hw)
 426{
 427	struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
 428	u32 val, count;
 429
 430	regmap_update_bits(clk_regmap, clk->reg, clk->enable, clk->enable);
 431
 432	for (count = 0; count < 1000; count++) {
 433		regmap_read(clk_regmap, clk->reg, &val);
 434		if (val & PLL_CTRL_LOCK)
 435			break;
 436	}
 437
 438	if (val & PLL_CTRL_LOCK)
 439		return 0;
 440
 441	return -ETIMEDOUT;
 442}
 443
 444static void clk_pll_disable(struct clk_hw *hw)
 445{
 446	struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
 447
 448	regmap_update_bits(clk_regmap, clk->reg, clk->enable, 0x0);
 449}
 450
 451static int clk_pll_is_enabled(struct clk_hw *hw)
 452{
 453	struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
 454	u32 val;
 455
 456	regmap_read(clk_regmap, clk->reg, &val);
 457
 458	val &= clk->enable | PLL_CTRL_LOCK;
 459	if (val == (clk->enable | PLL_CTRL_LOCK))
 460		return 1;
 461
 462	return 0;
 463}
 464
 465static unsigned long clk_pll_397x_recalc_rate(struct clk_hw *hw,
 466					      unsigned long parent_rate)
 467{
 468	return parent_rate * 397;
 469}
 470
 471static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 472					 unsigned long parent_rate)
 473{
 474	struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
 475	bool is_direct, is_bypass, is_feedback;
 476	unsigned long rate, cco_rate, ref_rate;
 477	u32 val;
 478
 479	regmap_read(clk_regmap, clk->reg, &val);
 480	is_direct = val & PLL_CTRL_DIRECT;
 481	is_bypass = val & PLL_CTRL_BYPASS;
 482	is_feedback = val & PLL_CTRL_FEEDBACK;
 483
 484	clk->m_div = ((val & PLL_CTRL_FEEDDIV) >> 1) + 1;
 485	clk->n_div = ((val & PLL_CTRL_PREDIV) >> 9) + 1;
 486	clk->p_div = ((val & PLL_CTRL_POSTDIV) >> 11) + 1;
 487
 488	if (is_direct && is_bypass) {
 489		clk->p_div = 0;
 490		clk->mode = PLL_DIRECT_BYPASS;
 491		return parent_rate;
 492	}
 493	if (is_bypass) {
 494		clk->mode = PLL_BYPASS;
 495		return parent_rate / (1 << clk->p_div);
 496	}
 497	if (is_direct) {
 498		clk->p_div = 0;
 499		clk->mode = PLL_DIRECT;
 500	}
 501
 502	ref_rate = parent_rate / clk->n_div;
 503	rate = cco_rate = ref_rate * clk->m_div;
 504
 505	if (!is_direct) {
 506		if (is_feedback) {
 507			cco_rate *= (1 << clk->p_div);
 508			clk->mode = PLL_INTEGER;
 509		} else {
 510			rate /= (1 << clk->p_div);
 511			clk->mode = PLL_NON_INTEGER;
 512		}
 513	}
 514
 515	pr_debug("%s: %lu: 0x%x: %d/%d/%d, %lu/%lu/%d => %lu\n",
 516		 clk_hw_get_name(hw),
 517		 parent_rate, val, is_direct, is_bypass, is_feedback,
 518		 clk->n_div, clk->m_div, (1 << clk->p_div), rate);
 519
 520	if (clk_pll_is_enabled(hw) &&
 521	    !(pll_is_valid(parent_rate, 1, 1000000, 20000000)
 522	      && pll_is_valid(cco_rate, 1, 156000000, 320000000)
 523	      && pll_is_valid(ref_rate, 1, 1000000, 27000000)))
 524		pr_err("%s: PLL clocks are not in valid ranges: %lu/%lu/%lu\n",
 525		       clk_hw_get_name(hw),
 526		       parent_rate, cco_rate, ref_rate);
 527
 528	return rate;
 529}
 530
 531static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 532			    unsigned long parent_rate)
 533{
 534	struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
 535	u32 val;
 536	unsigned long new_rate;
 537
 538	/* Validate PLL clock parameters computed on round rate stage */
 539	switch (clk->mode) {
 540	case PLL_DIRECT:
 541		val = PLL_CTRL_DIRECT;
 542		val |= (clk->m_div - 1) << 1;
 543		val |= (clk->n_div - 1) << 9;
 544		new_rate = (parent_rate * clk->m_div) / clk->n_div;
 545		break;
 546	case PLL_BYPASS:
 547		val = PLL_CTRL_BYPASS;
 548		val |= (clk->p_div - 1) << 11;
 549		new_rate = parent_rate / (1 << (clk->p_div));
 550		break;
 551	case PLL_DIRECT_BYPASS:
 552		val = PLL_CTRL_DIRECT | PLL_CTRL_BYPASS;
 553		new_rate = parent_rate;
 554		break;
 555	case PLL_INTEGER:
 556		val = PLL_CTRL_FEEDBACK;
 557		val |= (clk->m_div - 1) << 1;
 558		val |= (clk->n_div - 1) << 9;
 559		val |= (clk->p_div - 1) << 11;
 560		new_rate = (parent_rate * clk->m_div) / clk->n_div;
 561		break;
 562	case PLL_NON_INTEGER:
 563		val = 0x0;
 564		val |= (clk->m_div - 1) << 1;
 565		val |= (clk->n_div - 1) << 9;
 566		val |= (clk->p_div - 1) << 11;
 567		new_rate = (parent_rate * clk->m_div) /
 568				(clk->n_div * (1 << clk->p_div));
 569		break;
 570	default:
 571		return -EINVAL;
 572	}
 573
 574	/* Sanity check that round rate is equal to the requested one */
 575	if (new_rate != rate)
 576		return -EINVAL;
 577
 578	return regmap_update_bits(clk_regmap, clk->reg, 0x1FFFF, val);
 579}
 580
 581static int clk_hclk_pll_determine_rate(struct clk_hw *hw,
 582				       struct clk_rate_request *req)
 583{
 584	struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
 585	u64 m_i, o = req->rate, i = req->best_parent_rate, d = (u64)req->rate << 6;
 586	u64 m = 0, n = 0, p = 0;
 587	int p_i, n_i;
 588
 589	pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), req->best_parent_rate, req->rate);
 590
 591	if (req->rate > 266500000)
 592		return -EINVAL;
 593
 594	/* Have to check all 20 possibilities to find the minimal M */
 595	for (p_i = 4; p_i >= 0; p_i--) {
 596		for (n_i = 4; n_i > 0; n_i--) {
 597			m_i = div64_u64(o * n_i * (1 << p_i), i);
 598
 599			/* Check for valid PLL parameter constraints */
 600			if (!(m_i && m_i <= 256
 601			      && pll_is_valid(i, n_i, 1000000, 27000000)
 602			      && pll_is_valid(i * m_i * (1 << p_i), n_i,
 603					      156000000, 320000000)))
 604				continue;
 605
 606			/* Store some intermediate valid parameters */
 607			if (o * n_i * (1 << p_i) - i * m_i <= d) {
 608				m = m_i;
 609				n = n_i;
 610				p = p_i;
 611				d = o * n_i * (1 << p_i) - i * m_i;
 612			}
 613		}
 614	}
 615
 616	if (d == (u64)req->rate << 6) {
 617		pr_err("%s: %lu: no valid PLL parameters are found\n",
 618		       clk_hw_get_name(hw), req->rate);
 619		return -EINVAL;
 620	}
 621
 622	clk->m_div = m;
 623	clk->n_div = n;
 624	clk->p_div = p;
 625
 626	/* Set only direct or non-integer mode of PLL */
 627	if (!p)
 628		clk->mode = PLL_DIRECT;
 629	else
 630		clk->mode = PLL_NON_INTEGER;
 631
 632	o = div64_u64(i * m, n * (1 << p));
 633
 634	if (!d)
 635		pr_debug("%s: %lu: found exact match: %llu/%llu/%llu\n",
 636			 clk_hw_get_name(hw), req->rate, m, n, p);
 637	else
 638		pr_debug("%s: %lu: found closest: %llu/%llu/%llu - %llu\n",
 639			 clk_hw_get_name(hw), req->rate, m, n, p, o);
 640
 641	req->rate = o;
 642
 643	return 0;
 644}
 645
 646static int clk_usb_pll_determine_rate(struct clk_hw *hw,
 647				      struct clk_rate_request *req)
 648{
 649	struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
 650	struct clk_hw *usb_div_hw, *osc_hw;
 651	u64 d_i, n_i, m, o;
 652
 653	pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), req->best_parent_rate,
 654		 req->rate);
 655
 656	/*
 657	 * The only supported USB clock is 48MHz, with PLL internal constraints
 658	 * on Fclkin, Fcco and Fref this implies that Fcco must be 192MHz
 659	 * and post-divider must be 4, this slightly simplifies calculation of
 660	 * USB divider, USB PLL N and M parameters.
 661	 */
 662	if (req->rate != 48000000)
 663		return -EINVAL;
 664
 665	/* USB divider clock */
 666	usb_div_hw = clk_hw_get_parent_by_index(hw, 0);
 667	if (!usb_div_hw)
 668		return -EINVAL;
 669
 670	/* Main oscillator clock */
 671	osc_hw = clk_hw_get_parent_by_index(usb_div_hw, 0);
 672	if (!osc_hw)
 673		return -EINVAL;
 674	o = clk_hw_get_rate(osc_hw);	/* must be in range 1..20 MHz */
 675
 676	/* Check if valid USB divider and USB PLL parameters exists */
 677	for (d_i = 16; d_i >= 1; d_i--) {
 678		for (n_i = 1; n_i <= 4; n_i++) {
 679			m = div64_u64(192000000 * d_i * n_i, o);
 680			if (!(m && m <= 256
 681			      && m * o == 192000000 * d_i * n_i
 682			      && pll_is_valid(o, d_i, 1000000, 20000000)
 683			      && pll_is_valid(o, d_i * n_i, 1000000, 27000000)))
 684				continue;
 685
 686			clk->n_div = n_i;
 687			clk->m_div = m;
 688			clk->p_div = 2;
 689			clk->mode = PLL_NON_INTEGER;
 690			req->best_parent_rate = div64_u64(o, d_i);
 691
 692			return 0;
 693		}
 694	}
 695
 696	return -EINVAL;
 697}
 698
 699#define LPC32XX_DEFINE_PLL_OPS(_name, _rc, _sr, _dr)			\
 700	static const struct clk_ops clk_ ##_name ## _ops = {		\
 701		.enable = clk_pll_enable,				\
 702		.disable = clk_pll_disable,				\
 703		.is_enabled = clk_pll_is_enabled,			\
 704		.recalc_rate = _rc,					\
 705		.set_rate = _sr,					\
 706		.determine_rate = _dr,					\
 707	}
 708
 709LPC32XX_DEFINE_PLL_OPS(pll_397x, clk_pll_397x_recalc_rate, NULL, NULL);
 710LPC32XX_DEFINE_PLL_OPS(hclk_pll, clk_pll_recalc_rate,
 711		       clk_pll_set_rate, clk_hclk_pll_determine_rate);
 712LPC32XX_DEFINE_PLL_OPS(usb_pll,  clk_pll_recalc_rate,
 713		       clk_pll_set_rate, clk_usb_pll_determine_rate);
 714
 715static int clk_ddram_is_enabled(struct clk_hw *hw)
 716{
 717	struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
 718	u32 val;
 719
 720	regmap_read(clk_regmap, clk->reg, &val);
 721	val &= clk->enable_mask | clk->busy_mask;
 722
 723	return (val == (BIT(7) | BIT(0)) ||
 724		val == (BIT(8) | BIT(1)));
 725}
 726
 727static int clk_ddram_enable(struct clk_hw *hw)
 728{
 729	struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
 730	u32 val, hclk_div;
 731
 732	regmap_read(clk_regmap, clk->reg, &val);
 733	hclk_div = val & clk->busy_mask;
 734
 735	/*
 736	 * DDRAM clock must be 2 times higher than HCLK,
 737	 * this implies DDRAM clock can not be enabled,
 738	 * if HCLK clock rate is equal to ARM clock rate
 739	 */
 740	if (hclk_div == 0x0 || hclk_div == (BIT(1) | BIT(0)))
 741		return -EINVAL;
 742
 743	return regmap_update_bits(clk_regmap, clk->reg,
 744				  clk->enable_mask, hclk_div << 7);
 745}
 746
 747static unsigned long clk_ddram_recalc_rate(struct clk_hw *hw,
 748					   unsigned long parent_rate)
 749{
 750	struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
 751	u32 val;
 752
 753	if (!clk_ddram_is_enabled(hw))
 754		return 0;
 755
 756	regmap_read(clk_regmap, clk->reg, &val);
 757	val &= clk->enable_mask;
 758
 759	return parent_rate / (val >> 7);
 760}
 761
 762static const struct clk_ops clk_ddram_ops = {
 763	.enable = clk_ddram_enable,
 764	.disable = clk_mask_disable,
 765	.is_enabled = clk_ddram_is_enabled,
 766	.recalc_rate = clk_ddram_recalc_rate,
 767};
 768
 769static unsigned long lpc32xx_clk_uart_recalc_rate(struct clk_hw *hw,
 770						  unsigned long parent_rate)
 771{
 772	struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
 773	u32 val, x, y;
 774
 775	regmap_read(clk_regmap, clk->reg, &val);
 776	x = (val & 0xFF00) >> 8;
 777	y = val & 0xFF;
 778
 779	if (x && y)
 780		return (parent_rate * x) / y;
 781	else
 782		return 0;
 783}
 784
 785static const struct clk_ops lpc32xx_uart_div_ops = {
 786	.recalc_rate = lpc32xx_clk_uart_recalc_rate,
 787};
 788
 789static const struct clk_div_table clk_hclk_div_table[] = {
 790	{ .val = 0, .div = 1 },
 791	{ .val = 1, .div = 2 },
 792	{ .val = 2, .div = 4 },
 793	{ },
 794};
 795
 796static u32 test1_mux_table[] = { 0, 1, 2, };
 797static u32 test2_mux_table[] = { 0, 1, 2, 5, 7, };
 798
 799static int clk_usb_enable(struct clk_hw *hw)
 800{
 801	struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
 802	u32 val, ctrl_val, count;
 803
 804	pr_debug("%s: 0x%x\n", clk_hw_get_name(hw), clk->enable);
 805
 806	if (clk->ctrl_mask) {
 807		regmap_read(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, &ctrl_val);
 808		regmap_update_bits(clk_regmap, LPC32XX_CLKPWR_USB_CTRL,
 809				   clk->ctrl_mask, clk->ctrl_enable);
 810	}
 811
 812	val = lpc32xx_usb_clk_read(clk);
 813	if (clk->busy && (val & clk->busy) == clk->busy) {
 814		if (clk->ctrl_mask)
 815			regmap_write(clk_regmap, LPC32XX_CLKPWR_USB_CTRL,
 816				     ctrl_val);
 817		return -EBUSY;
 818	}
 819
 820	val |= clk->enable;
 821	lpc32xx_usb_clk_write(clk, val);
 822
 823	for (count = 0; count < 1000; count++) {
 824		val = lpc32xx_usb_clk_read(clk);
 825		if ((val & clk->enable) == clk->enable)
 826			break;
 827	}
 828
 829	if ((val & clk->enable) == clk->enable)
 830		return 0;
 831
 832	if (clk->ctrl_mask)
 833		regmap_write(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, ctrl_val);
 834
 835	return -ETIMEDOUT;
 836}
 837
 838static void clk_usb_disable(struct clk_hw *hw)
 839{
 840	struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
 841	u32 val = lpc32xx_usb_clk_read(clk);
 842
 843	val &= ~clk->enable;
 844	lpc32xx_usb_clk_write(clk, val);
 845
 846	if (clk->ctrl_mask)
 847		regmap_update_bits(clk_regmap, LPC32XX_CLKPWR_USB_CTRL,
 848				   clk->ctrl_mask, clk->ctrl_disable);
 849}
 850
 851static int clk_usb_is_enabled(struct clk_hw *hw)
 852{
 853	struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
 854	u32 ctrl_val, val;
 855
 856	if (clk->ctrl_mask) {
 857		regmap_read(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, &ctrl_val);
 858		if ((ctrl_val & clk->ctrl_mask) != clk->ctrl_enable)
 859			return 0;
 860	}
 861
 862	val = lpc32xx_usb_clk_read(clk);
 863
 864	return ((val & clk->enable) == clk->enable);
 865}
 866
 867static unsigned long clk_usb_i2c_recalc_rate(struct clk_hw *hw,
 868					     unsigned long parent_rate)
 869{
 870	return clk_get_rate(clk[LPC32XX_CLK_PERIPH]);
 871}
 872
 873static const struct clk_ops clk_usb_ops = {
 874	.enable = clk_usb_enable,
 875	.disable = clk_usb_disable,
 876	.is_enabled = clk_usb_is_enabled,
 877};
 878
 879static const struct clk_ops clk_usb_i2c_ops = {
 880	.enable = clk_usb_enable,
 881	.disable = clk_usb_disable,
 882	.is_enabled = clk_usb_is_enabled,
 883	.recalc_rate = clk_usb_i2c_recalc_rate,
 884};
 885
 886static int lpc32xx_clk_gate_enable(struct clk_hw *hw)
 887{
 888	struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
 889	u32 mask = BIT(clk->bit_idx);
 890	u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? 0x0 : mask);
 891
 892	return regmap_update_bits(clk_regmap, clk->reg, mask, val);
 893}
 894
 895static void lpc32xx_clk_gate_disable(struct clk_hw *hw)
 896{
 897	struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
 898	u32 mask = BIT(clk->bit_idx);
 899	u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? mask : 0x0);
 900
 901	regmap_update_bits(clk_regmap, clk->reg, mask, val);
 902}
 903
 904static int lpc32xx_clk_gate_is_enabled(struct clk_hw *hw)
 905{
 906	struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
 907	u32 val;
 908	bool is_set;
 909
 910	regmap_read(clk_regmap, clk->reg, &val);
 911	is_set = val & BIT(clk->bit_idx);
 912
 913	return (clk->flags & CLK_GATE_SET_TO_DISABLE ? !is_set : is_set);
 914}
 915
 916static const struct clk_ops lpc32xx_clk_gate_ops = {
 917	.enable = lpc32xx_clk_gate_enable,
 918	.disable = lpc32xx_clk_gate_disable,
 919	.is_enabled = lpc32xx_clk_gate_is_enabled,
 920};
 921
 922#define div_mask(width)	((1 << (width)) - 1)
 923
 924static unsigned int _get_table_div(const struct clk_div_table *table,
 925							unsigned int val)
 926{
 927	const struct clk_div_table *clkt;
 928
 929	for (clkt = table; clkt->div; clkt++)
 930		if (clkt->val == val)
 931			return clkt->div;
 932	return 0;
 933}
 934
 935static unsigned int _get_div(const struct clk_div_table *table,
 936			     unsigned int val, unsigned long flags, u8 width)
 937{
 938	if (flags & CLK_DIVIDER_ONE_BASED)
 939		return val;
 940	if (table)
 941		return _get_table_div(table, val);
 942	return val + 1;
 943}
 944
 945static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
 946		unsigned long parent_rate)
 947{
 948	struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
 949	unsigned int val;
 950
 951	regmap_read(clk_regmap, divider->reg, &val);
 952
 953	val >>= divider->shift;
 954	val &= div_mask(divider->width);
 955
 956	return divider_recalc_rate(hw, parent_rate, val, divider->table,
 957				   divider->flags, divider->width);
 958}
 959
 960static int clk_divider_determine_rate(struct clk_hw *hw,
 961				      struct clk_rate_request *req)
 962{
 963	struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
 964	unsigned int bestdiv;
 965
 966	/* if read only, just return current value */
 967	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
 968		regmap_read(clk_regmap, divider->reg, &bestdiv);
 969		bestdiv >>= divider->shift;
 970		bestdiv &= div_mask(divider->width);
 971		bestdiv = _get_div(divider->table, bestdiv, divider->flags,
 972			divider->width);
 973		req->rate = DIV_ROUND_UP(req->best_parent_rate, bestdiv);
 974
 975		return 0;
 976	}
 977
 978	return divider_determine_rate(hw, req, divider->table, divider->width,
 979				      divider->flags);
 980}
 981
 982static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 983				unsigned long parent_rate)
 984{
 985	struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
 986	unsigned int value;
 987
 988	value = divider_get_val(rate, parent_rate, divider->table,
 989				divider->width, divider->flags);
 990
 991	return regmap_update_bits(clk_regmap, divider->reg,
 992				  div_mask(divider->width) << divider->shift,
 993				  value << divider->shift);
 994}
 995
 996static const struct clk_ops lpc32xx_clk_divider_ops = {
 997	.recalc_rate = clk_divider_recalc_rate,
 998	.determine_rate = clk_divider_determine_rate,
 999	.set_rate = clk_divider_set_rate,
1000};
1001
1002static u8 clk_mux_get_parent(struct clk_hw *hw)
1003{
1004	struct lpc32xx_clk_mux *mux = to_lpc32xx_mux(hw);
1005	u32 num_parents = clk_hw_get_num_parents(hw);
1006	u32 val;
1007
1008	regmap_read(clk_regmap, mux->reg, &val);
1009	val >>= mux->shift;
1010	val &= mux->mask;
1011
1012	if (mux->table) {
1013		u32 i;
1014
1015		for (i = 0; i < num_parents; i++)
1016			if (mux->table[i] == val)
1017				return i;
1018		return -EINVAL;
1019	}
1020
1021	if (val >= num_parents)
1022		return -EINVAL;
1023
1024	return val;
1025}
1026
1027static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
1028{
1029	struct lpc32xx_clk_mux *mux = to_lpc32xx_mux(hw);
1030
1031	if (mux->table)
1032		index = mux->table[index];
1033
1034	return regmap_update_bits(clk_regmap, mux->reg,
1035			  mux->mask << mux->shift, index << mux->shift);
1036}
1037
1038static const struct clk_ops lpc32xx_clk_mux_ro_ops = {
1039	.get_parent = clk_mux_get_parent,
1040};
1041
1042static const struct clk_ops lpc32xx_clk_mux_ops = {
1043	.get_parent = clk_mux_get_parent,
1044	.set_parent = clk_mux_set_parent,
1045	.determine_rate = __clk_mux_determine_rate,
1046};
1047
1048enum lpc32xx_clk_type {
1049	CLK_FIXED,
1050	CLK_MUX,
1051	CLK_DIV,
1052	CLK_GATE,
1053	CLK_COMPOSITE,
1054	CLK_LPC32XX,
1055	CLK_LPC32XX_PLL,
1056	CLK_LPC32XX_USB,
1057};
1058
1059struct clk_hw_proto0 {
1060	const struct clk_ops *ops;
1061	union {
1062		struct lpc32xx_pll_clk pll;
1063		struct lpc32xx_clk clk;
1064		struct lpc32xx_usb_clk usb_clk;
1065		struct lpc32xx_clk_mux mux;
1066		struct lpc32xx_clk_div div;
1067		struct lpc32xx_clk_gate gate;
1068	};
1069};
1070
1071struct clk_hw_proto1 {
1072	struct clk_hw_proto0 *mux;
1073	struct clk_hw_proto0 *div;
1074	struct clk_hw_proto0 *gate;
1075};
1076
1077struct clk_hw_proto {
1078	enum lpc32xx_clk_type type;
1079
1080	union {
1081		struct clk_fixed_rate f;
1082		struct clk_hw_proto0 hw0;
1083		struct clk_hw_proto1 hw1;
1084	};
1085};
1086
1087#define LPC32XX_DEFINE_FIXED(_idx, _rate)			\
1088[CLK_PREFIX(_idx)] = {							\
1089	.type = CLK_FIXED,						\
1090	{								\
1091		.f = {							\
1092			.fixed_rate = (_rate),				\
1093		},							\
1094	},								\
1095}
1096
1097#define LPC32XX_DEFINE_PLL(_idx, _name, _reg, _enable)			\
1098[CLK_PREFIX(_idx)] = {							\
1099	.type = CLK_LPC32XX_PLL,					\
1100	{								\
1101		.hw0 = {						\
1102			.ops = &clk_ ##_name ## _ops,			\
1103			{						\
1104				.pll = {				\
1105					.reg = LPC32XX_CLKPWR_ ## _reg,	\
1106					.enable = (_enable),		\
1107				},					\
1108			},						\
1109		},							\
1110	},								\
1111}
1112
1113#define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags)	\
1114[CLK_PREFIX(_idx)] = {							\
1115	.type = CLK_MUX,						\
1116	{								\
1117		.hw0 = {						\
1118			.ops = (_flags & CLK_MUX_READ_ONLY ?		\
1119				&lpc32xx_clk_mux_ro_ops :		\
1120				&lpc32xx_clk_mux_ops),			\
1121			{						\
1122				.mux = {				\
1123					.reg = LPC32XX_CLKPWR_ ## _reg,	\
1124					.mask = (_mask),		\
1125					.shift = (_shift),		\
1126					.table = (_table),		\
1127					.flags = (_flags),		\
1128				},					\
1129			},						\
1130		},							\
1131	},								\
1132}
1133
1134#define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags)	\
1135[CLK_PREFIX(_idx)] = {							\
1136	.type = CLK_DIV,						\
1137	{								\
1138		.hw0 = {						\
1139			.ops = &lpc32xx_clk_divider_ops,		\
1140			{						\
1141				.div = {				\
1142					.reg = LPC32XX_CLKPWR_ ## _reg,	\
1143					.shift = (_shift),		\
1144					.width = (_width),		\
1145					.table = (_table),		\
1146					.flags = (_flags),		\
1147				 },					\
1148			},						\
1149		 },							\
1150	},								\
1151}
1152
1153#define LPC32XX_DEFINE_GATE(_idx, _reg, _bit, _flags)			\
1154[CLK_PREFIX(_idx)] = {							\
1155	.type = CLK_GATE,						\
1156	{								\
1157		.hw0 = {						\
1158			.ops = &lpc32xx_clk_gate_ops,			\
1159			{						\
1160				.gate = {				\
1161					.reg = LPC32XX_CLKPWR_ ## _reg,	\
1162					.bit_idx = (_bit),		\
1163					.flags = (_flags),		\
1164				},					\
1165			},						\
1166		},							\
1167	},								\
1168}
1169
1170#define LPC32XX_DEFINE_CLK(_idx, _reg, _e, _em, _d, _dm, _b, _bm, _ops)	\
1171[CLK_PREFIX(_idx)] = {							\
1172	.type = CLK_LPC32XX,						\
1173	{								\
1174		.hw0 = {						\
1175			.ops = &(_ops),					\
1176			{						\
1177				.clk = {				\
1178					.reg = LPC32XX_CLKPWR_ ## _reg,	\
1179					.enable = (_e),			\
1180					.enable_mask = (_em),		\
1181					.disable = (_d),		\
1182					.disable_mask = (_dm),		\
1183					.busy = (_b),			\
1184					.busy_mask = (_bm),		\
1185				},					\
1186			},						\
1187		},							\
1188	},								\
1189}
1190
1191#define LPC32XX_DEFINE_USB(_idx, _ce, _cd, _cm, _e, _b, _ops)		\
1192[CLK_PREFIX(_idx)] = {							\
1193	.type = CLK_LPC32XX_USB,					\
1194	{								\
1195		.hw0 = {						\
1196			.ops = &(_ops),					\
1197			{						\
1198				.usb_clk = {				\
1199					.ctrl_enable = (_ce),		\
1200					.ctrl_disable = (_cd),		\
1201					.ctrl_mask = (_cm),		\
1202					.enable = (_e),			\
1203					.busy = (_b),			\
1204				}					\
1205			},						\
1206		}							\
1207	},								\
1208}
1209
1210#define LPC32XX_DEFINE_COMPOSITE(_idx, _mux, _div, _gate)		\
1211[CLK_PREFIX(_idx)] = {							\
1212	.type = CLK_COMPOSITE,						\
1213	{								\
1214		.hw1 = {						\
1215		.mux = (CLK_PREFIX(_mux) == LPC32XX_CLK__NULL ? NULL :	\
1216			&clk_hw_proto[CLK_PREFIX(_mux)].hw0),		\
1217		.div = (CLK_PREFIX(_div) == LPC32XX_CLK__NULL ? NULL :	\
1218			&clk_hw_proto[CLK_PREFIX(_div)].hw0),		\
1219		.gate = (CLK_PREFIX(_gate) == LPC32XX_CLK__NULL ? NULL :\
1220			 &clk_hw_proto[CLK_PREFIX(_gate)].hw0),		\
1221		},							\
1222	},								\
1223}
1224
1225static struct clk_hw_proto clk_hw_proto[LPC32XX_CLK_HW_MAX] = {
1226	LPC32XX_DEFINE_FIXED(RTC, 32768),
1227	LPC32XX_DEFINE_PLL(PLL397X, pll_397x, HCLKPLL_CTRL, BIT(1)),
1228	LPC32XX_DEFINE_PLL(HCLK_PLL, hclk_pll, HCLKPLL_CTRL, PLL_CTRL_ENABLE),
1229	LPC32XX_DEFINE_PLL(USB_PLL, usb_pll, USB_CTRL, PLL_CTRL_ENABLE),
1230	LPC32XX_DEFINE_GATE(OSC, OSC_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
1231	LPC32XX_DEFINE_GATE(USB, USB_CTRL, 18, 0),
1232
1233	LPC32XX_DEFINE_DIV(HCLK_DIV_PERIPH, HCLKDIV_CTRL, 2, 5, NULL,
1234			   CLK_DIVIDER_READ_ONLY),
1235	LPC32XX_DEFINE_DIV(HCLK_DIV, HCLKDIV_CTRL, 0, 2, clk_hclk_div_table,
1236			   CLK_DIVIDER_READ_ONLY),
1237
1238	/* Register 3 read-only muxes with a single control PWR_CTRL[2] */
1239	LPC32XX_DEFINE_MUX(SYSCLK_PERIPH_MUX, PWR_CTRL, 2, 0x1, NULL,
1240			   CLK_MUX_READ_ONLY),
1241	LPC32XX_DEFINE_MUX(SYSCLK_HCLK_MUX, PWR_CTRL, 2, 0x1, NULL,
1242			   CLK_MUX_READ_ONLY),
1243	LPC32XX_DEFINE_MUX(SYSCLK_ARM_MUX, PWR_CTRL, 2, 0x1, NULL,
1244			   CLK_MUX_READ_ONLY),
1245	/* Register 2 read-only muxes with a single control PWR_CTRL[10] */
1246	LPC32XX_DEFINE_MUX(PERIPH_HCLK_MUX, PWR_CTRL, 10, 0x1, NULL,
1247			   CLK_MUX_READ_ONLY),
1248	LPC32XX_DEFINE_MUX(PERIPH_ARM_MUX, PWR_CTRL, 10, 0x1, NULL,
1249			   CLK_MUX_READ_ONLY),
1250
1251	/* 3 always on gates with a single control PWR_CTRL[0] same as OSC */
1252	LPC32XX_DEFINE_GATE(PERIPH, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
1253	LPC32XX_DEFINE_GATE(HCLK, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
1254	LPC32XX_DEFINE_GATE(ARM, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
1255
1256	LPC32XX_DEFINE_GATE(ARM_VFP, DEBUG_CTRL, 4, 0),
1257	LPC32XX_DEFINE_GATE(DMA, DMA_CLK_CTRL, 0, 0),
1258	LPC32XX_DEFINE_CLK(DDRAM, HCLKDIV_CTRL, 0x0, BIT(8) | BIT(7),
1259		   0x0, BIT(8) | BIT(7), 0x0, BIT(1) | BIT(0), clk_ddram_ops),
1260
1261	LPC32XX_DEFINE_GATE(TIMER0, TIMCLK_CTRL1, 2, 0),
1262	LPC32XX_DEFINE_GATE(TIMER1, TIMCLK_CTRL1, 3, 0),
1263	LPC32XX_DEFINE_GATE(TIMER2, TIMCLK_CTRL1, 4, 0),
1264	LPC32XX_DEFINE_GATE(TIMER3, TIMCLK_CTRL1, 5, 0),
1265	LPC32XX_DEFINE_GATE(TIMER4, TIMCLK_CTRL1, 0, 0),
1266	LPC32XX_DEFINE_GATE(TIMER5, TIMCLK_CTRL1, 1, 0),
1267
1268	LPC32XX_DEFINE_GATE(SSP0, SSP_CTRL, 0, 0),
1269	LPC32XX_DEFINE_GATE(SSP1, SSP_CTRL, 1, 0),
1270	LPC32XX_DEFINE_GATE(SPI1, SPI_CTRL, 0, 0),
1271	LPC32XX_DEFINE_GATE(SPI2, SPI_CTRL, 4, 0),
1272	LPC32XX_DEFINE_GATE(I2S0, I2S_CTRL, 0, 0),
1273	LPC32XX_DEFINE_GATE(I2S1, I2S_CTRL, 1, 0),
1274	LPC32XX_DEFINE_GATE(I2C1, I2CCLK_CTRL, 0, 0),
1275	LPC32XX_DEFINE_GATE(I2C2, I2CCLK_CTRL, 1, 0),
1276	LPC32XX_DEFINE_GATE(WDOG, TIMCLK_CTRL, 0, 0),
1277	LPC32XX_DEFINE_GATE(HSTIMER, TIMCLK_CTRL, 1, 0),
1278
1279	LPC32XX_DEFINE_GATE(KEY, KEYCLK_CTRL, 0, 0),
1280	LPC32XX_DEFINE_GATE(MCPWM, TIMCLK_CTRL1, 6, 0),
1281
1282	LPC32XX_DEFINE_MUX(PWM1_MUX, PWMCLK_CTRL, 1, 0x1, NULL, 0),
1283	LPC32XX_DEFINE_DIV(PWM1_DIV, PWMCLK_CTRL, 4, 4, NULL,
1284			   CLK_DIVIDER_ONE_BASED),
1285	LPC32XX_DEFINE_GATE(PWM1_GATE, PWMCLK_CTRL, 0, 0),
1286	LPC32XX_DEFINE_COMPOSITE(PWM1, PWM1_MUX, PWM1_DIV, PWM1_GATE),
1287
1288	LPC32XX_DEFINE_MUX(PWM2_MUX, PWMCLK_CTRL, 3, 0x1, NULL, 0),
1289	LPC32XX_DEFINE_DIV(PWM2_DIV, PWMCLK_CTRL, 8, 4, NULL,
1290			   CLK_DIVIDER_ONE_BASED),
1291	LPC32XX_DEFINE_GATE(PWM2_GATE, PWMCLK_CTRL, 2, 0),
1292	LPC32XX_DEFINE_COMPOSITE(PWM2, PWM2_MUX, PWM2_DIV, PWM2_GATE),
1293
1294	LPC32XX_DEFINE_MUX(UART3_MUX, UART3_CLK_CTRL, 16, 0x1, NULL, 0),
1295	LPC32XX_DEFINE_CLK(UART3_DIV, UART3_CLK_CTRL,
1296			   0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
1297	LPC32XX_DEFINE_GATE(UART3_GATE, UART_CLK_CTRL, 0, 0),
1298	LPC32XX_DEFINE_COMPOSITE(UART3, UART3_MUX, UART3_DIV, UART3_GATE),
1299
1300	LPC32XX_DEFINE_MUX(UART4_MUX, UART4_CLK_CTRL, 16, 0x1, NULL, 0),
1301	LPC32XX_DEFINE_CLK(UART4_DIV, UART4_CLK_CTRL,
1302			   0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
1303	LPC32XX_DEFINE_GATE(UART4_GATE, UART_CLK_CTRL, 1, 0),
1304	LPC32XX_DEFINE_COMPOSITE(UART4, UART4_MUX, UART4_DIV, UART4_GATE),
1305
1306	LPC32XX_DEFINE_MUX(UART5_MUX, UART5_CLK_CTRL, 16, 0x1, NULL, 0),
1307	LPC32XX_DEFINE_CLK(UART5_DIV, UART5_CLK_CTRL,
1308			   0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
1309	LPC32XX_DEFINE_GATE(UART5_GATE, UART_CLK_CTRL, 2, 0),
1310	LPC32XX_DEFINE_COMPOSITE(UART5, UART5_MUX, UART5_DIV, UART5_GATE),
1311
1312	LPC32XX_DEFINE_MUX(UART6_MUX, UART6_CLK_CTRL, 16, 0x1, NULL, 0),
1313	LPC32XX_DEFINE_CLK(UART6_DIV, UART6_CLK_CTRL,
1314			   0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
1315	LPC32XX_DEFINE_GATE(UART6_GATE, UART_CLK_CTRL, 3, 0),
1316	LPC32XX_DEFINE_COMPOSITE(UART6, UART6_MUX, UART6_DIV, UART6_GATE),
1317
1318	LPC32XX_DEFINE_CLK(IRDA, IRDA_CLK_CTRL,
1319			   0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
1320
1321	LPC32XX_DEFINE_MUX(TEST1_MUX, TEST_CLK_CTRL, 5, 0x3,
1322			   test1_mux_table, 0),
1323	LPC32XX_DEFINE_GATE(TEST1_GATE, TEST_CLK_CTRL, 4, 0),
1324	LPC32XX_DEFINE_COMPOSITE(TEST1, TEST1_MUX, _NULL, TEST1_GATE),
1325
1326	LPC32XX_DEFINE_MUX(TEST2_MUX, TEST_CLK_CTRL, 1, 0x7,
1327			   test2_mux_table, 0),
1328	LPC32XX_DEFINE_GATE(TEST2_GATE, TEST_CLK_CTRL, 0, 0),
1329	LPC32XX_DEFINE_COMPOSITE(TEST2, TEST2_MUX, _NULL, TEST2_GATE),
1330
1331	LPC32XX_DEFINE_MUX(SYS, SYSCLK_CTRL, 0, 0x1, NULL, CLK_MUX_READ_ONLY),
1332
1333	LPC32XX_DEFINE_DIV(USB_DIV_DIV, USB_DIV, 0, 4, NULL, 0),
1334	LPC32XX_DEFINE_GATE(USB_DIV_GATE, USB_CTRL, 17, 0),
1335	LPC32XX_DEFINE_COMPOSITE(USB_DIV, _NULL, USB_DIV_DIV, USB_DIV_GATE),
1336
1337	LPC32XX_DEFINE_DIV(SD_DIV, MS_CTRL, 0, 4, NULL, CLK_DIVIDER_ONE_BASED),
1338	LPC32XX_DEFINE_CLK(SD_GATE, MS_CTRL, BIT(5) | BIT(9), BIT(5) | BIT(9),
1339			   0x0, BIT(5) | BIT(9), 0x0, 0x0, clk_mask_ops),
1340	LPC32XX_DEFINE_COMPOSITE(SD, _NULL, SD_DIV, SD_GATE),
1341
1342	LPC32XX_DEFINE_DIV(LCD_DIV, LCDCLK_CTRL, 0, 5, NULL, 0),
1343	LPC32XX_DEFINE_GATE(LCD_GATE, LCDCLK_CTRL, 5, 0),
1344	LPC32XX_DEFINE_COMPOSITE(LCD, _NULL, LCD_DIV, LCD_GATE),
1345
1346	LPC32XX_DEFINE_CLK(MAC, MACCLK_CTRL,
1347			   BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0),
1348			   BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0),
1349			   0x0, 0x0, clk_mask_ops),
1350	LPC32XX_DEFINE_CLK(SLC, FLASHCLK_CTRL,
1351			   BIT(2) | BIT(0), BIT(2) | BIT(0), 0x0,
1352			   BIT(0), BIT(1), BIT(2) | BIT(1), clk_mask_ops),
1353	LPC32XX_DEFINE_CLK(MLC, FLASHCLK_CTRL,
1354			   BIT(1), BIT(2) | BIT(1), 0x0, BIT(1),
1355			   BIT(2) | BIT(0), BIT(2) | BIT(0), clk_mask_ops),
1356	/*
1357	 * ADC/TS clock unfortunately cannot be registered as a composite one
1358	 * due to a different connection of gate, div and mux, e.g. gating it
1359	 * won't mean that the clock is off, if peripheral clock is its parent:
1360	 *
1361	 * rtc-->[gate]-->|     |
1362	 *                | mux |--> adc/ts
1363	 * pclk-->[div]-->|     |
1364	 *
1365	 * Constraints:
1366	 * ADC --- resulting clock must be <= 4.5 MHz
1367	 * TS  --- resulting clock must be <= 400 KHz
1368	 */
1369	LPC32XX_DEFINE_DIV(ADC_DIV, ADCCLK_CTRL1, 0, 8, NULL, 0),
1370	LPC32XX_DEFINE_GATE(ADC_RTC, ADCCLK_CTRL, 0, 0),
1371	LPC32XX_DEFINE_MUX(ADC, ADCCLK_CTRL1, 8, 0x1, NULL, 0),
1372
1373	/* USB controller clocks */
1374	LPC32XX_DEFINE_USB(USB_AHB,
1375			   BIT(24), 0x0, BIT(24), BIT(4), 0, clk_usb_ops),
1376	LPC32XX_DEFINE_USB(USB_OTG,
1377			   0x0, 0x0, 0x0, BIT(3), 0, clk_usb_ops),
1378	LPC32XX_DEFINE_USB(USB_I2C,
1379			   0x0, BIT(23), BIT(23), BIT(2), 0, clk_usb_i2c_ops),
1380	LPC32XX_DEFINE_USB(USB_DEV,
1381			   BIT(22), 0x0, BIT(22), BIT(1), BIT(0), clk_usb_ops),
1382	LPC32XX_DEFINE_USB(USB_HOST,
1383			   BIT(21), 0x0, BIT(21), BIT(0), BIT(1), clk_usb_ops),
1384};
1385
1386static struct clk * __init lpc32xx_clk_register(u32 id)
1387{
1388	const struct clk_proto_t *lpc32xx_clk = &clk_proto[id];
1389	struct clk_hw_proto *clk_hw = &clk_hw_proto[id];
1390	const char *parents[LPC32XX_CLK_PARENTS_MAX];
1391	struct clk *clk;
1392	unsigned int i;
1393
1394	for (i = 0; i < lpc32xx_clk->num_parents; i++)
1395		parents[i] = clk_proto[lpc32xx_clk->parents[i]].name;
1396
1397	pr_debug("%s: derived from '%s', clock type %d\n", lpc32xx_clk->name,
1398		 parents[0], clk_hw->type);
1399
1400	switch (clk_hw->type) {
1401	case CLK_LPC32XX:
1402	case CLK_LPC32XX_PLL:
1403	case CLK_LPC32XX_USB:
1404	case CLK_MUX:
1405	case CLK_DIV:
1406	case CLK_GATE:
1407	{
1408		struct clk_init_data clk_init = {
1409			.name = lpc32xx_clk->name,
1410			.parent_names = parents,
1411			.num_parents = lpc32xx_clk->num_parents,
1412			.flags = lpc32xx_clk->flags,
1413			.ops = clk_hw->hw0.ops,
1414		};
1415		struct clk_hw *hw;
1416
1417		if (clk_hw->type == CLK_LPC32XX)
1418			hw = &clk_hw->hw0.clk.hw;
1419		else if (clk_hw->type == CLK_LPC32XX_PLL)
1420			hw = &clk_hw->hw0.pll.hw;
1421		else if (clk_hw->type == CLK_LPC32XX_USB)
1422			hw = &clk_hw->hw0.usb_clk.hw;
1423		else if (clk_hw->type == CLK_MUX)
1424			hw = &clk_hw->hw0.mux.hw;
1425		else if (clk_hw->type == CLK_DIV)
1426			hw = &clk_hw->hw0.div.hw;
1427		else if (clk_hw->type == CLK_GATE)
1428			hw = &clk_hw->hw0.gate.hw;
1429		else
1430			return ERR_PTR(-EINVAL);
1431
1432		hw->init = &clk_init;
1433		clk = clk_register(NULL, hw);
1434		break;
1435	}
1436	case CLK_COMPOSITE:
1437	{
1438		struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL;
1439		const struct clk_ops *mops = NULL, *dops = NULL, *gops = NULL;
1440		struct clk_hw_proto0 *mux0, *div0, *gate0;
1441
1442		mux0 = clk_hw->hw1.mux;
1443		div0 = clk_hw->hw1.div;
1444		gate0 = clk_hw->hw1.gate;
1445		if (mux0) {
1446			mops = mux0->ops;
1447			mux_hw = &mux0->clk.hw;
1448		}
1449		if (div0) {
1450			dops = div0->ops;
1451			div_hw = &div0->clk.hw;
1452		}
1453		if (gate0) {
1454			gops = gate0->ops;
1455			gate_hw = &gate0->clk.hw;
1456		}
1457
1458		clk = clk_register_composite(NULL, lpc32xx_clk->name,
1459				parents, lpc32xx_clk->num_parents,
1460				mux_hw, mops, div_hw, dops,
1461				gate_hw, gops, lpc32xx_clk->flags);
1462		break;
1463	}
1464	case CLK_FIXED:
1465	{
1466		struct clk_fixed_rate *fixed = &clk_hw->f;
1467
1468		clk = clk_register_fixed_rate(NULL, lpc32xx_clk->name,
1469			parents[0], 0, fixed->fixed_rate);
1470		break;
1471	}
1472	default:
1473		clk = ERR_PTR(-EINVAL);
1474	}
1475
1476	return clk;
1477}
1478
1479static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate)
1480{
1481	u32 val;
1482
1483	regmap_read(clk_regmap, reg, &val);
1484
1485	if (!(val & div_mask)) {
1486		val &= ~gate;
1487		val |= BIT(__ffs(div_mask));
1488	}
1489
1490	regmap_update_bits(clk_regmap, reg, gate | div_mask, val);
1491}
1492
1493static void __init lpc32xx_clk_init(struct device_node *np)
1494{
1495	unsigned int i;
1496	struct clk *clk_osc, *clk_32k;
1497	void __iomem *base = NULL;
1498
1499	/* Ensure that parent clocks are available and valid */
1500	clk_32k = of_clk_get_by_name(np, clk_proto[LPC32XX_CLK_XTAL_32K].name);
1501	if (IS_ERR(clk_32k)) {
1502		pr_err("failed to find external 32KHz clock: %ld\n",
1503		       PTR_ERR(clk_32k));
1504		return;
1505	}
1506	if (clk_get_rate(clk_32k) != 32768) {
1507		pr_err("invalid clock rate of external 32KHz oscillator\n");
1508		return;
1509	}
1510
1511	clk_osc = of_clk_get_by_name(np, clk_proto[LPC32XX_CLK_XTAL].name);
1512	if (IS_ERR(clk_osc)) {
1513		pr_err("failed to find external main oscillator clock: %ld\n",
1514		       PTR_ERR(clk_osc));
1515		return;
1516	}
1517
1518	base = of_iomap(np, 0);
1519	if (!base) {
1520		pr_err("failed to map system control block registers\n");
1521		return;
1522	}
1523
1524	clk_regmap = regmap_init_mmio(NULL, base, &lpc32xx_scb_regmap_config);
1525	if (IS_ERR(clk_regmap)) {
1526		pr_err("failed to regmap system control block: %ld\n",
1527			PTR_ERR(clk_regmap));
1528		iounmap(base);
1529		return;
1530	}
1531
1532	/*
1533	 * Divider part of PWM and MS clocks requires a quirk to avoid
1534	 * a misinterpretation of formally valid zero value in register
1535	 * bitfield, which indicates another clock gate. Instead of
1536	 * adding complexity to a gate clock ensure that zero value in
1537	 * divider clock is never met in runtime.
1538	 */
1539	lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, 0xf0, BIT(0));
1540	lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, 0xf00, BIT(2));
1541	lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_MS_CTRL, 0xf, BIT(5) | BIT(9));
1542
1543	for (i = 1; i < LPC32XX_CLK_MAX; i++) {
1544		clk[i] = lpc32xx_clk_register(i);
1545		if (IS_ERR(clk[i])) {
1546			pr_err("failed to register %s clock: %ld\n",
1547				clk_proto[i].name, PTR_ERR(clk[i]));
1548			clk[i] = NULL;
1549		}
1550	}
1551
1552	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1553
1554	/* Set 48MHz rate of USB PLL clock */
1555	clk_set_rate(clk[LPC32XX_CLK_USB_PLL], 48000000);
1556
1557	/* These two clocks must be always on independently on consumers */
1558	clk_prepare_enable(clk[LPC32XX_CLK_ARM]);
1559	clk_prepare_enable(clk[LPC32XX_CLK_HCLK]);
1560
1561	/* Enable ARM VFP by default */
1562	clk_prepare_enable(clk[LPC32XX_CLK_ARM_VFP]);
1563
1564	/* Disable enabled by default clocks for NAND MLC and SLC */
1565	clk_mask_disable(&clk_hw_proto[LPC32XX_CLK_SLC].hw0.clk.hw);
1566	clk_mask_disable(&clk_hw_proto[LPC32XX_CLK_MLC].hw0.clk.hw);
1567}
1568CLK_OF_DECLARE(lpc32xx_clk, "nxp,lpc3220-clk", lpc32xx_clk_init);
1569
1570static void __init lpc32xx_usb_clk_init(struct device_node *np)
1571{
1572	unsigned int i;
1573
1574	usb_clk_vbase = of_iomap(np, 0);
1575	if (!usb_clk_vbase) {
1576		pr_err("failed to map address range\n");
1577		return;
1578	}
1579
1580	for (i = 1; i < LPC32XX_USB_CLK_MAX; i++) {
1581		usb_clk[i] = lpc32xx_clk_register(i + LPC32XX_CLK_USB_OFFSET);
1582		if (IS_ERR(usb_clk[i])) {
1583			pr_err("failed to register %s clock: %ld\n",
1584				clk_proto[i].name, PTR_ERR(usb_clk[i]));
1585			usb_clk[i] = NULL;
1586		}
1587	}
1588
1589	of_clk_add_provider(np, of_clk_src_onecell_get, &usb_clk_data);
1590}
1591CLK_OF_DECLARE(lpc32xx_usb_clk, "nxp,lpc3220-usb-clk", lpc32xx_usb_clk_init);