clk-ma35d1-divider.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2023 Nuvoton Technology Corp.
  4 * Author: Chi-Fang Li <cfli0@nuvoton.com>
  5 */
  6
  7#include <linux/clk-provider.h>
  8#include <linux/device.h>
  9#include <linux/regmap.h>
 10#include <linux/spinlock.h>
 11
 12#include "clk-ma35d1.h"
 13
 14struct ma35d1_adc_clk_div {
 15	struct clk_hw hw;
 16	void __iomem *reg;
 17	u8 shift;
 18	u8 width;
 19	u32 mask;
 20	const struct clk_div_table *table;
 21	/* protects concurrent access to clock divider registers */
 22	spinlock_t *lock;
 23};
 24
 25static inline struct ma35d1_adc_clk_div *to_ma35d1_adc_clk_div(struct clk_hw *_hw)
 26{
 27	return container_of(_hw, struct ma35d1_adc_clk_div, hw);
 28}
 29
 30static unsigned long ma35d1_clkdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 31{
 32	unsigned int val;
 33	struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);
 34
 35	val = readl_relaxed(dclk->reg) >> dclk->shift;
 36	val &= clk_div_mask(dclk->width);
 37	val += 1;
 38	return divider_recalc_rate(hw, parent_rate, val, dclk->table,
 39				   CLK_DIVIDER_ROUND_CLOSEST, dclk->width);
 40}
 41
 42static int ma35d1_clkdiv_determine_rate(struct clk_hw *hw,
 43					struct clk_rate_request *req)
 44{
 45	struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);
 46
 47	return divider_determine_rate(hw, req, dclk->table, dclk->width,
 48				      CLK_DIVIDER_ROUND_CLOSEST);
 49}
 50
 51static int ma35d1_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
 52{
 53	int value;
 54	unsigned long flags = 0;
 55	u32 data;
 56	struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);
 57
 58	value = divider_get_val(rate, parent_rate, dclk->table,
 59				dclk->width, CLK_DIVIDER_ROUND_CLOSEST);
 60
 61	spin_lock_irqsave(dclk->lock, flags);
 62
 63	data = readl_relaxed(dclk->reg);
 64	data &= ~(clk_div_mask(dclk->width) << dclk->shift);
 65	data |= (value - 1) << dclk->shift;
 66	data |= dclk->mask;
 67	writel_relaxed(data, dclk->reg);
 68
 69	spin_unlock_irqrestore(dclk->lock, flags);
 70	return 0;
 71}
 72
 73static const struct clk_ops ma35d1_adc_clkdiv_ops = {
 74	.recalc_rate = ma35d1_clkdiv_recalc_rate,
 75	.determine_rate = ma35d1_clkdiv_determine_rate,
 76	.set_rate = ma35d1_clkdiv_set_rate,
 77};
 78
 79struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name,
 80				     struct clk_hw *parent_hw, spinlock_t *lock,
 81				     unsigned long flags, void __iomem *reg,
 82				     u8 shift, u8 width, u32 mask_bit)
 83{
 84	struct ma35d1_adc_clk_div *div;
 85	struct clk_init_data init;
 86	struct clk_div_table *table;
 87	struct clk_parent_data pdata = { .index = 0 };
 88	u32 max_div, min_div;
 89	struct clk_hw *hw;
 90	int ret;
 91	int i;
 92
 93	div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
 94	if (!div)
 95		return ERR_PTR(-ENOMEM);
 96
 97	max_div = clk_div_mask(width) + 1;
 98	min_div = 1;
 99
100	table = devm_kcalloc(dev, max_div + 1, sizeof(*table), GFP_KERNEL);
101	if (!table)
102		return ERR_PTR(-ENOMEM);
103
104	for (i = 0; i < max_div; i++) {
105		table[i].val = min_div + i;
106		table[i].div = 2 * table[i].val;
107	}
108	table[max_div].val = 0;
109	table[max_div].div = 0;
110
111	memset(&init, 0, sizeof(init));
112	init.name = name;
113	init.ops = &ma35d1_adc_clkdiv_ops;
114	init.flags |= flags;
115	pdata.hw = parent_hw;
116	init.parent_data = &pdata;
117	init.num_parents = 1;
118
119	div->reg = reg;
120	div->shift = shift;
121	div->width = width;
122	div->mask = mask_bit ? BIT(mask_bit) : 0;
123	div->lock = lock;
124	div->hw.init = &init;
125	div->table = table;
126
127	hw = &div->hw;
128	ret = devm_clk_hw_register(dev, hw);
129	if (ret)
130		return ERR_PTR(ret);
131	return hw;
132}
133EXPORT_SYMBOL_GPL(ma35d1_reg_adc_clkdiv);