clk-pxa1908-apmu.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2#include <linux/auxiliary_bus.h>
  3#include <linux/clk-provider.h>
  4#include <linux/module.h>
  5#include <linux/platform_device.h>
  6#include <linux/spinlock.h>
  7
  8#include <dt-bindings/clock/marvell,pxa1908.h>
  9
 10#include "clk.h"
 11
 12#define APMU_CLK_GATE_CTRL	0x40
 13#define APMU_CCIC1		0x24
 14#define APMU_ISP		0x38
 15#define APMU_DSI1		0x44
 16#define APMU_DISP1		0x4c
 17#define APMU_CCIC0		0x50
 18#define APMU_SDH0		0x54
 19#define APMU_SDH1		0x58
 20#define APMU_USB		0x5c
 21#define APMU_NF			0x60
 22#define APMU_VPU		0xa4
 23#define APMU_GC			0xcc
 24#define APMU_SDH2		0xe0
 25#define APMU_GC2D		0xf4
 26#define APMU_TRACE		0x108
 27#define APMU_DVC_DFC_DEBUG	0x140
 28
 29#define APMU_NR_CLKS		17
 30
 31struct pxa1908_clk_unit {
 32	struct mmp_clk_unit unit;
 33	void __iomem *base;
 34};
 35
 36static DEFINE_SPINLOCK(pll1_lock);
 37static struct mmp_param_general_gate_clk pll1_gate_clks[] = {
 38	{PXA1908_CLK_PLL1_D2_GATE, "pll1_d2_gate", "pll1_d2", 0, APMU_CLK_GATE_CTRL, 29, 0, &pll1_lock},
 39	{PXA1908_CLK_PLL1_416_GATE, "pll1_416_gate", "pll1_416", 0, APMU_CLK_GATE_CTRL, 27, 0, &pll1_lock},
 40	{PXA1908_CLK_PLL1_624_GATE, "pll1_624_gate", "pll1_624", 0, APMU_CLK_GATE_CTRL, 26, 0, &pll1_lock},
 41	{PXA1908_CLK_PLL1_832_GATE, "pll1_832_gate", "pll1_832", 0, APMU_CLK_GATE_CTRL, 30, 0, &pll1_lock},
 42	{PXA1908_CLK_PLL1_1248_GATE, "pll1_1248_gate", "pll1_1248", 0, APMU_CLK_GATE_CTRL, 28, 0, &pll1_lock},
 43};
 44
 45static DEFINE_SPINLOCK(sdh0_lock);
 46static DEFINE_SPINLOCK(sdh1_lock);
 47static DEFINE_SPINLOCK(sdh2_lock);
 48
 49static const char * const sdh_parent_names[] = {"pll1_416", "pll1_624"};
 50
 51static struct mmp_clk_mix_config sdh_mix_config = {
 52	.reg_info = DEFINE_MIX_REG_INFO(3, 8, 2, 6, 11),
 53};
 54
 55static struct mmp_param_gate_clk apmu_gate_clks[] = {
 56	{PXA1908_CLK_USB, "usb_clk", NULL, 0, APMU_USB, 0x9, 0x9, 0x1, 0, NULL},
 57	{PXA1908_CLK_SDH0, "sdh0_clk", "sdh0_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH0, 0x12, 0x12, 0x0, 0, &sdh0_lock},
 58	{PXA1908_CLK_SDH1, "sdh1_clk", "sdh1_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH1, 0x12, 0x12, 0x0, 0, &sdh1_lock},
 59	{PXA1908_CLK_SDH2, "sdh2_clk", "sdh2_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH2, 0x12, 0x12, 0x0, 0, &sdh2_lock}
 60};
 61
 62static void pxa1908_axi_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
 63{
 64	struct mmp_clk_unit *unit = &pxa_unit->unit;
 65
 66	mmp_register_general_gate_clks(unit, pll1_gate_clks,
 67			pxa_unit->base, ARRAY_SIZE(pll1_gate_clks));
 68
 69	sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->base + APMU_SDH0;
 70	mmp_clk_register_mix(NULL, "sdh0_mix_clk", sdh_parent_names,
 71			ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
 72			&sdh_mix_config, &sdh0_lock);
 73	sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->base + APMU_SDH1;
 74	mmp_clk_register_mix(NULL, "sdh1_mix_clk", sdh_parent_names,
 75			ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
 76			&sdh_mix_config, &sdh1_lock);
 77	sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->base + APMU_SDH2;
 78	mmp_clk_register_mix(NULL, "sdh2_mix_clk", sdh_parent_names,
 79			ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
 80			&sdh_mix_config, &sdh2_lock);
 81
 82	mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->base,
 83			ARRAY_SIZE(apmu_gate_clks));
 84}
 85
 86static int pxa1908_apmu_probe(struct platform_device *pdev)
 87{
 88	struct pxa1908_clk_unit *pxa_unit;
 89	struct auxiliary_device *adev;
 90
 91	pxa_unit = devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL);
 92	if (!pxa_unit)
 93		return -ENOMEM;
 94
 95	pxa_unit->base = devm_platform_ioremap_resource(pdev, 0);
 96	if (IS_ERR(pxa_unit->base))
 97		return PTR_ERR(pxa_unit->base);
 98
 99	adev = devm_auxiliary_device_create(&pdev->dev, "power", NULL);
100	if (IS_ERR(adev))
101		return dev_err_probe(&pdev->dev, PTR_ERR(adev),
102				     "Failed to register power controller\n");
103
104	mmp_clk_init(pdev->dev.of_node, &pxa_unit->unit, APMU_NR_CLKS);
105
106	pxa1908_axi_periph_clk_init(pxa_unit);
107
108	return 0;
109}
110
111static const struct of_device_id pxa1908_apmu_match_table[] = {
112	{ .compatible = "marvell,pxa1908-apmu" },
113	{ }
114};
115MODULE_DEVICE_TABLE(of, pxa1908_apmu_match_table);
116
117static struct platform_driver pxa1908_apmu_driver = {
118	.probe = pxa1908_apmu_probe,
119	.driver = {
120		.name = "pxa1908-apmu",
121		.of_match_table = pxa1908_apmu_match_table
122	}
123};
124module_platform_driver(pxa1908_apmu_driver);
125
126MODULE_AUTHOR("Duje Mihanović <duje.mihanovic@skole.hr>");
127MODULE_DESCRIPTION("Marvell PXA1908 APMU Clock Driver");
128MODULE_LICENSE("GPL");