clk-mpfs.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * PolarFire SoC MSS/core complex clock control
  4 *
  5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
  6 */
  7#include <linux/cleanup.h>
  8#include <linux/clk-provider.h>
  9#include <linux/io.h>
 10#include <linux/mfd/syscon.h>
 11#include <linux/module.h>
 12#include <linux/platform_device.h>
 13#include <linux/regmap.h>
 14#include <dt-bindings/clock/microchip,mpfs-clock.h>
 15#include <soc/microchip/mpfs.h>
 16
 17/* address offset of control registers */
 18#define REG_MSSPLL_REF_CR	0x08u
 19#define REG_MSSPLL_POSTDIV01_CR	0x10u
 20#define REG_MSSPLL_POSTDIV23_CR	0x14u
 21#define REG_MSSPLL_SSCG_2_CR	0x2Cu
 22#define REG_CLOCK_CONFIG_CR	0x08u
 23#define REG_RTC_CLOCK_CR	0x0Cu
 24#define REG_SUBBLK_CLOCK_CR	0x84u
 25#define REG_SUBBLK_RESET_CR	0x88u
 26
 27#define MSSPLL_FBDIV_SHIFT	0x00u
 28#define MSSPLL_FBDIV_WIDTH	0x0Cu
 29#define MSSPLL_REFDIV_SHIFT	0x08u
 30#define MSSPLL_REFDIV_WIDTH	0x06u
 31#define MSSPLL_POSTDIV02_SHIFT	0x08u
 32#define MSSPLL_POSTDIV13_SHIFT	0x18u
 33#define MSSPLL_POSTDIV_WIDTH	0x07u
 34#define MSSPLL_FIXED_DIV	4u
 35
 36static const struct regmap_config mpfs_clk_regmap_config = {
 37	.reg_bits = 32,
 38	.reg_stride = 4,
 39	.val_bits = 32,
 40	.val_format_endian = REGMAP_ENDIAN_LITTLE,
 41	.max_register = REG_SUBBLK_RESET_CR,
 42};
 43
 44/*
 45 * This clock ID is defined here, rather than the binding headers, as it is an
 46 * internal clock only, and therefore has no consumers in other peripheral
 47 * blocks.
 48 */
 49#define CLK_MSSPLL_INTERNAL	38u
 50
 51struct mpfs_clock_data {
 52	struct device *dev;
 53	struct regmap *regmap;
 54	void __iomem *base;
 55	void __iomem *msspll_base;
 56	struct clk_hw_onecell_data hw_data;
 57};
 58
 59struct mpfs_msspll_hw_clock {
 60	void __iomem *base;
 61	struct clk_hw hw;
 62	struct clk_init_data init;
 63	unsigned int id;
 64	u32 reg_offset;
 65	u32 shift;
 66	u32 width;
 67	u32 flags;
 68};
 69
 70#define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
 71
 72struct mpfs_msspll_out_hw_clock {
 73	void __iomem *base;
 74	struct clk_divider output;
 75	struct clk_init_data init;
 76	unsigned int id;
 77	u32 reg_offset;
 78};
 79
 80#define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_out_hw_clock, hw)
 81
 82struct mpfs_cfg_clock {
 83	struct regmap *map;
 84	const struct clk_div_table *table;
 85	u8 map_offset;
 86	u8 shift;
 87	u8 width;
 88	u8 flags;
 89};
 90
 91struct mpfs_cfg_hw_clock {
 92	struct clk_hw hw;
 93	struct mpfs_cfg_clock cfg;
 94	unsigned int id;
 95};
 96
 97#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw)
 98
 99struct mpfs_periph_clock {
100	struct regmap *map;
101	u8 map_offset;
102	u8 shift;
103};
104
105struct mpfs_periph_hw_clock {
106	struct clk_hw hw;
107	struct mpfs_periph_clock periph;
108	unsigned int id;
109};
110
111#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw)
112
113/*
114 * Protects MSSPLL outputs, since there's two to a register
115 */
116static DEFINE_SPINLOCK(mpfs_clk_lock);
117
118static const struct clk_parent_data mpfs_ext_ref[] = {
119	{ .index = 0 },
120};
121
122static const struct clk_div_table mpfs_div_cpu_axi_table[] = {
123	{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
124	{ 0, 0 }
125};
126
127static const struct clk_div_table mpfs_div_ahb_table[] = {
128	{ 1, 2 }, { 2, 4}, { 3, 8 },
129	{ 0, 0 }
130};
131
132/*
133 * The only two supported reference clock frequencies for the PolarFire SoC are
134 * 100 and 125 MHz, as the rtc reference is required to be 1 MHz.
135 * It therefore only needs to have divider table entries corresponding to
136 * divide by 100 and 125.
137 */
138static const struct clk_div_table mpfs_div_rtcref_table[] = {
139	{ 100, 100 }, { 125, 125 },
140	{ 0, 0 }
141};
142
143/*
144 * MSS PLL internal clock
145 */
146
147static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate)
148{
149	struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
150	void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
151	void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
152	u32 mult, ref_div;
153
154	mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
155	mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
156	ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
157	ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
158
159	return prate * mult / (ref_div * MSSPLL_FIXED_DIV);
160}
161
162static const struct clk_ops mpfs_clk_msspll_ops = {
163	.recalc_rate = mpfs_clk_msspll_recalc_rate,
164};
165
166#define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) {			\
167	.id = _id,									\
168	.flags = _flags,								\
169	.shift = _shift,								\
170	.width = _width,								\
171	.reg_offset = _offset,								\
172	.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0),	\
173}
174
175static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = {
176	CLK_PLL(CLK_MSSPLL_INTERNAL, "clk_msspll_internal", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT,
177		MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR),
178};
179
180static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws,
181				     unsigned int num_clks, struct mpfs_clock_data *data)
182{
183	unsigned int i;
184	int ret;
185
186	for (i = 0; i < num_clks; i++) {
187		struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i];
188
189		msspll_hw->base = data->msspll_base;
190		ret = devm_clk_hw_register(dev, &msspll_hw->hw);
191		if (ret)
192			return dev_err_probe(dev, ret, "failed to register msspll id: %d\n",
193					     CLK_MSSPLL_INTERNAL);
194
195		data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw;
196	}
197
198	return 0;
199}
200
201/*
202 * MSS PLL output clocks
203 */
204
205#define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) {	\
206	.id = _id,								\
207	.output.shift = _shift,							\
208	.output.width = _width,							\
209	.output.table = NULL,							\
210	.reg_offset = _offset,							\
211	.output.flags = _flags,							\
212	.output.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0),	\
213	.output.lock = &mpfs_clk_lock,						\
214}
215
216static struct mpfs_msspll_out_hw_clock mpfs_msspll_out_clks[] = {
217	CLK_PLL_OUT(CLK_MSSPLL0, "clk_msspll", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
218		    MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR),
219	CLK_PLL_OUT(CLK_MSSPLL1, "clk_msspll1", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
220		    MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR),
221	CLK_PLL_OUT(CLK_MSSPLL2, "clk_msspll2", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
222		    MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR),
223	CLK_PLL_OUT(CLK_MSSPLL3, "clk_msspll3", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED,
224		    MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR),
225};
226
227static int mpfs_clk_register_msspll_outs(struct device *dev,
228					 struct mpfs_msspll_out_hw_clock *msspll_out_hws,
229					 unsigned int num_clks, struct mpfs_clock_data *data)
230{
231	unsigned int i;
232	int ret;
233
234	for (i = 0; i < num_clks; i++) {
235		struct mpfs_msspll_out_hw_clock *msspll_out_hw = &msspll_out_hws[i];
236
237		msspll_out_hw->output.reg = data->msspll_base + msspll_out_hw->reg_offset;
238		ret = devm_clk_hw_register(dev, &msspll_out_hw->output.hw);
239		if (ret)
240			return dev_err_probe(dev, ret, "failed to register msspll out id: %d\n",
241					     msspll_out_hw->id);
242
243		data->hw_data.hws[msspll_out_hw->id] = &msspll_out_hw->output.hw;
244	}
245
246	return 0;
247}
248
249/*
250 * "CFG" clocks
251 */
252static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate)
253{
254	struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
255	struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
256	u32 val;
257
258	regmap_read(cfg->map, cfg->map_offset, &val);
259	val >>= cfg->shift;
260	val &= clk_div_mask(cfg->width);
261
262	return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width);
263}
264
265static int mpfs_cfg_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
266{
267	struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
268	struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
269
270	return divider_determine_rate(hw, req, cfg->table, cfg->width, 0);
271}
272
273static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
274{
275	struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
276	struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
277	int divider_setting;
278	u32 val;
279	u32 mask;
280
281	divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0);
282
283	if (divider_setting < 0)
284		return divider_setting;
285
286	mask = clk_div_mask(cfg->width) << cfg->shift;
287	val = divider_setting << cfg->shift;
288	regmap_update_bits(cfg->map, cfg->map_offset, val, mask);
289
290	return 0;
291}
292
293static const struct clk_ops mpfs_clk_cfg_ops = {
294	.recalc_rate = mpfs_cfg_clk_recalc_rate,
295	.determine_rate = mpfs_cfg_clk_determine_rate,
296	.set_rate = mpfs_cfg_clk_set_rate,
297};
298
299#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) {	\
300	.id = _id,								\
301	.cfg.shift = _shift,							\
302	.cfg.width = _width,							\
303	.cfg.table = _table,							\
304	.cfg.map_offset = _offset,						\
305	.cfg.flags = _flags,							\
306	.hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0),		\
307}
308
309#define CLK_CPU_OFFSET		0u
310#define CLK_AXI_OFFSET		1u
311#define CLK_AHB_OFFSET		2u
312#define CLK_RTCREF_OFFSET	3u
313
314static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
315	CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0,
316		REG_CLOCK_CONFIG_CR),
317	CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0,
318		REG_CLOCK_CONFIG_CR),
319	CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0,
320		REG_CLOCK_CONFIG_CR),
321	{
322		.id = CLK_RTCREF,
323		.cfg.shift = 0,
324		.cfg.width = 12,
325		.cfg.table = mpfs_div_rtcref_table,
326		.cfg.map_offset = REG_RTC_CLOCK_CR,
327		.cfg.flags = CLK_DIVIDER_ONE_BASED,
328		.hw.init =
329			CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0),
330	}
331};
332
333static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws,
334				  unsigned int num_clks, struct mpfs_clock_data *data)
335{
336	unsigned int i, id;
337	int ret;
338
339	for (i = 0; i < num_clks; i++) {
340		struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
341
342		cfg_hw->cfg.map = data->regmap;
343		ret = devm_clk_hw_register(dev, &cfg_hw->hw);
344		if (ret)
345			return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
346					     cfg_hw->id);
347
348		id = cfg_hw->id;
349		data->hw_data.hws[id] = &cfg_hw->hw;
350	}
351
352	return 0;
353}
354
355/*
356 * peripheral clocks - devices connected to axi or ahb buses.
357 */
358
359static int mpfs_periph_clk_enable(struct clk_hw *hw)
360{
361	struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
362	struct mpfs_periph_clock *periph = &periph_hw->periph;
363
364	regmap_update_bits(periph->map, periph->map_offset,
365			   BIT(periph->shift), BIT(periph->shift));
366
367	return 0;
368}
369
370static void mpfs_periph_clk_disable(struct clk_hw *hw)
371{
372	struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
373	struct mpfs_periph_clock *periph = &periph_hw->periph;
374
375	regmap_update_bits(periph->map, periph->map_offset, BIT(periph->shift), 0);
376}
377
378static int mpfs_periph_clk_is_enabled(struct clk_hw *hw)
379{
380	struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
381	struct mpfs_periph_clock *periph = &periph_hw->periph;
382	u32 val;
383
384	regmap_read(periph->map, periph->map_offset, &val);
385
386	return !!(val & BIT(periph->shift));
387}
388
389static const struct clk_ops mpfs_periph_clk_ops = {
390	.enable = mpfs_periph_clk_enable,
391	.disable = mpfs_periph_clk_disable,
392	.is_enabled = mpfs_periph_clk_is_enabled,
393};
394
395#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) {				\
396	.id = _id,									\
397	.periph.map_offset = REG_SUBBLK_CLOCK_CR,					\
398	.periph.shift = _shift,								\
399	.hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, _flags),	\
400}
401
402#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].hw)
403
404/*
405 * Critical clocks:
406 * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt
407 *   trap handler
408 * - CLK_MMUART0: reserved by the hss
409 * - CLK_DDRC: provides clock to the ddr subsystem
410 * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop
411 *   if the AHB interface clock is disabled
412 * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect)
413 *   clock domain crossers which provide the interface to the FPGA fabric. Disabling them
414 *   causes the FPGA fabric to go into reset.
415 * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire.
416 */
417
418static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
419	CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL),
420	CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0),
421	CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0),
422	CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0),
423	CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0),
424	CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL),
425	CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0),
426	CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0),
427	CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0),
428	CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0),
429	CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0),
430	CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0),
431	CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0),
432	CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0),
433	CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0),
434	CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0),
435	CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0),
436	CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL),
437	CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0),
438	CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0),
439	CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0),
440	CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0),
441	CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL),
442	CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL),
443	CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL),
444	CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL),
445	CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL),
446	CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL),
447	CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0),
448};
449
450static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws,
451				     int num_clks, struct mpfs_clock_data *data)
452{
453	unsigned int i, id;
454	int ret;
455
456	for (i = 0; i < num_clks; i++) {
457		struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
458
459		periph_hw->periph.map = data->regmap;
460		ret = devm_clk_hw_register(dev, &periph_hw->hw);
461		if (ret)
462			return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
463					     periph_hw->id);
464
465		id = periph_hws[i].id;
466		data->hw_data.hws[id] = &periph_hw->hw;
467	}
468
469	return 0;
470}
471
472static inline int mpfs_clk_syscon_probe(struct mpfs_clock_data *clk_data,
473					struct platform_device *pdev)
474{
475	clk_data->regmap = syscon_regmap_lookup_by_compatible("microchip,mpfs-mss-top-sysreg");
476	if (IS_ERR(clk_data->regmap))
477		return PTR_ERR(clk_data->regmap);
478
479	clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 0);
480	if (IS_ERR(clk_data->msspll_base))
481		return PTR_ERR(clk_data->msspll_base);
482
483	return 0;
484}
485
486static inline int mpfs_clk_old_format_probe(struct mpfs_clock_data *clk_data,
487					    struct platform_device *pdev)
488{
489	struct device *dev = &pdev->dev;
490
491	dev_warn(&pdev->dev, "falling back to old devicetree format");
492
493	clk_data->base = devm_platform_ioremap_resource(pdev, 0);
494	if (IS_ERR(clk_data->base))
495		return PTR_ERR(clk_data->base);
496
497	clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);
498	if (IS_ERR(clk_data->msspll_base))
499		return PTR_ERR(clk_data->msspll_base);
500
501	clk_data->regmap = devm_regmap_init_mmio(dev, clk_data->base, &mpfs_clk_regmap_config);
502	if (IS_ERR(clk_data->regmap))
503		return PTR_ERR(clk_data->regmap);
504
505	return mpfs_reset_controller_register(dev, clk_data->regmap);
506}
507
508static int mpfs_clk_probe(struct platform_device *pdev)
509{
510	struct device *dev = &pdev->dev;
511	struct mpfs_clock_data *clk_data;
512	unsigned int num_clks;
513	int ret;
514
515	/* CLK_RESERVED is not part of clock arrays, so add 1 */
516	num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_msspll_out_clks)
517		   + ARRAY_SIZE(mpfs_cfg_clks)  + ARRAY_SIZE(mpfs_periph_clks) + 1;
518
519	clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL);
520	if (!clk_data)
521		return -ENOMEM;
522
523	ret = mpfs_clk_syscon_probe(clk_data, pdev);
524	if (ret) {
525		ret = mpfs_clk_old_format_probe(clk_data, pdev);
526		if (ret)
527			return ret;
528	}
529
530	clk_data->hw_data.num = num_clks;
531	clk_data->dev = dev;
532	dev_set_drvdata(dev, clk_data);
533
534	ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks),
535					clk_data);
536	if (ret)
537		return ret;
538
539	ret = mpfs_clk_register_msspll_outs(dev, mpfs_msspll_out_clks,
540					    ARRAY_SIZE(mpfs_msspll_out_clks),
541					    clk_data);
542	if (ret)
543		return ret;
544
545	ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data);
546	if (ret)
547		return ret;
548
549	ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks),
550					clk_data);
551	if (ret)
552		return ret;
553
554	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);
555}
556
557static const struct of_device_id mpfs_clk_of_match_table[] = {
558	{ .compatible = "microchip,mpfs-clkcfg", },
559	{}
560};
561MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table);
562
563static struct platform_driver mpfs_clk_driver = {
564	.probe = mpfs_clk_probe,
565	.driver	= {
566		.name = "microchip-mpfs-clkcfg",
567		.of_match_table = mpfs_clk_of_match_table,
568	},
569};
570
571static int __init clk_mpfs_init(void)
572{
573	return platform_driver_register(&mpfs_clk_driver);
574}
575core_initcall(clk_mpfs_init);
576
577static void __exit clk_mpfs_exit(void)
578{
579	platform_driver_unregister(&mpfs_clk_driver);
580}
581module_exit(clk_mpfs_exit);
582
583MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver");
584MODULE_AUTHOR("Padmarao Begari <padmarao.begari@microchip.com>");
585MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
586MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
587MODULE_IMPORT_NS("MCHP_CLK_MPFS");