s4-peripherals.c

   1// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
   2/*
   3 * Amlogic S4 Peripherals Clock Controller Driver
   4 *
   5 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
   6 * Author: Yu Tu <yu.tu@amlogic.com>
   7 */
   8
   9#include <linux/clk-provider.h>
  10#include <linux/of_device.h>
  11#include <linux/platform_device.h>
  12
  13#include "clk-regmap.h"
  14#include "vid-pll-div.h"
  15#include "clk-dualdiv.h"
  16#include "meson-clkc-utils.h"
  17#include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
  18
  19#define CLKCTRL_RTC_BY_OSCIN_CTRL0                 0x008
  20#define CLKCTRL_RTC_BY_OSCIN_CTRL1                 0x00c
  21#define CLKCTRL_RTC_CTRL                           0x010
  22#define CLKCTRL_SYS_CLK_CTRL0                      0x040
  23#define CLKCTRL_SYS_CLK_EN0_REG0                   0x044
  24#define CLKCTRL_SYS_CLK_EN0_REG1                   0x048
  25#define CLKCTRL_SYS_CLK_EN0_REG2                   0x04c
  26#define CLKCTRL_SYS_CLK_EN0_REG3                   0x050
  27#define CLKCTRL_CECA_CTRL0                         0x088
  28#define CLKCTRL_CECA_CTRL1                         0x08c
  29#define CLKCTRL_CECB_CTRL0                         0x090
  30#define CLKCTRL_CECB_CTRL1                         0x094
  31#define CLKCTRL_SC_CLK_CTRL                        0x098
  32#define CLKCTRL_CLK12_24_CTRL                      0x0a8
  33#define CLKCTRL_VID_CLK_CTRL                       0x0c0
  34#define CLKCTRL_VID_CLK_CTRL2                      0x0c4
  35#define CLKCTRL_VID_CLK_DIV                        0x0c8
  36#define CLKCTRL_VIID_CLK_DIV                       0x0cc
  37#define CLKCTRL_VIID_CLK_CTRL                      0x0d0
  38#define CLKCTRL_HDMI_CLK_CTRL                      0x0e0
  39#define CLKCTRL_VID_PLL_CLK_DIV                    0x0e4
  40#define CLKCTRL_VPU_CLK_CTRL                       0x0e8
  41#define CLKCTRL_VPU_CLKB_CTRL                      0x0ec
  42#define CLKCTRL_VPU_CLKC_CTRL                      0x0f0
  43#define CLKCTRL_VID_LOCK_CLK_CTRL                  0x0f4
  44#define CLKCTRL_VDIN_MEAS_CLK_CTRL                 0x0f8
  45#define CLKCTRL_VAPBCLK_CTRL                       0x0fc
  46#define CLKCTRL_HDCP22_CTRL                        0x100
  47#define CLKCTRL_VDEC_CLK_CTRL                      0x140
  48#define CLKCTRL_VDEC2_CLK_CTRL                     0x144
  49#define CLKCTRL_VDEC3_CLK_CTRL                     0x148
  50#define CLKCTRL_VDEC4_CLK_CTRL                     0x14c
  51#define CLKCTRL_TS_CLK_CTRL                        0x158
  52#define CLKCTRL_MALI_CLK_CTRL                      0x15c
  53#define CLKCTRL_NAND_CLK_CTRL                      0x168
  54#define CLKCTRL_SD_EMMC_CLK_CTRL                   0x16c
  55#define CLKCTRL_SPICC_CLK_CTRL                     0x174
  56#define CLKCTRL_GEN_CLK_CTRL                       0x178
  57#define CLKCTRL_SAR_CLK_CTRL                       0x17c
  58#define CLKCTRL_PWM_CLK_AB_CTRL                    0x180
  59#define CLKCTRL_PWM_CLK_CD_CTRL                    0x184
  60#define CLKCTRL_PWM_CLK_EF_CTRL                    0x188
  61#define CLKCTRL_PWM_CLK_GH_CTRL                    0x18c
  62#define CLKCTRL_PWM_CLK_IJ_CTRL                    0x190
  63#define CLKCTRL_DEMOD_CLK_CTRL                     0x200
  64
  65#define S4_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
  66	MESON_COMP_SEL(s4_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
  67
  68#define S4_COMP_DIV(_name, _reg, _shift, _width) \
  69	MESON_COMP_DIV(s4_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
  70
  71#define S4_COMP_GATE(_name, _reg, _bit) \
  72	MESON_COMP_GATE(s4_, _name, _reg, _bit, CLK_SET_RATE_PARENT)
  73
  74static struct clk_regmap s4_rtc_32k_by_oscin_clkin = {
  75	.data = &(struct clk_regmap_gate_data){
  76		.offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
  77		.bit_idx = 31,
  78	},
  79	.hw.init = &(struct clk_init_data) {
  80		.name = "rtc_32k_by_oscin_clkin",
  81		.ops = &clk_regmap_gate_ops,
  82		.parent_data = (const struct clk_parent_data []) {
  83			{ .fw_name = "xtal", }
  84		},
  85		.num_parents = 1,
  86	},
  87};
  88
  89static const struct meson_clk_dualdiv_param s4_32k_div_table[] = {
  90	{
  91		.dual	= 1,
  92		.n1	= 733,
  93		.m1	= 8,
  94		.n2	= 732,
  95		.m2	= 11,
  96	},
  97	{}
  98};
  99
 100static struct clk_regmap s4_rtc_32k_by_oscin_div = {
 101	.data = &(struct meson_clk_dualdiv_data){
 102		.n1 = {
 103			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
 104			.shift   = 0,
 105			.width   = 12,
 106		},
 107		.n2 = {
 108			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
 109			.shift   = 12,
 110			.width   = 12,
 111		},
 112		.m1 = {
 113			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1,
 114			.shift   = 0,
 115			.width   = 12,
 116		},
 117		.m2 = {
 118			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1,
 119			.shift   = 12,
 120			.width   = 12,
 121		},
 122		.dual = {
 123			.reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0,
 124			.shift   = 28,
 125			.width   = 1,
 126		},
 127		.table = s4_32k_div_table,
 128	},
 129	.hw.init = &(struct clk_init_data){
 130		.name = "rtc_32k_by_oscin_div",
 131		.ops = &meson_clk_dualdiv_ops,
 132		.parent_hws = (const struct clk_hw *[]) {
 133			&s4_rtc_32k_by_oscin_clkin.hw
 134		},
 135		.num_parents = 1,
 136	},
 137};
 138
 139static struct clk_regmap s4_rtc_32k_by_oscin_sel = {
 140	.data = &(struct clk_regmap_mux_data) {
 141		.offset = CLKCTRL_RTC_BY_OSCIN_CTRL1,
 142		.mask = 0x1,
 143		.shift = 24,
 144		.flags = CLK_MUX_ROUND_CLOSEST,
 145	},
 146	.hw.init = &(struct clk_init_data){
 147		.name = "rtc_32k_by_oscin_sel",
 148		.ops = &clk_regmap_mux_ops,
 149		.parent_hws = (const struct clk_hw *[]) {
 150			&s4_rtc_32k_by_oscin_div.hw,
 151			&s4_rtc_32k_by_oscin_clkin.hw,
 152		},
 153		.num_parents = 2,
 154		.flags = CLK_SET_RATE_PARENT,
 155	},
 156};
 157
 158static struct clk_regmap s4_rtc_32k_by_oscin = {
 159	.data = &(struct clk_regmap_gate_data){
 160		.offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
 161		.bit_idx = 30,
 162	},
 163	.hw.init = &(struct clk_init_data) {
 164		.name = "rtc_32k_by_oscin",
 165		.ops = &clk_regmap_gate_ops,
 166		.parent_hws = (const struct clk_hw *[]) {
 167			&s4_rtc_32k_by_oscin_sel.hw
 168		},
 169		.num_parents = 1,
 170		.flags = CLK_SET_RATE_PARENT,
 171	},
 172};
 173
 174static struct clk_regmap s4_rtc_clk = {
 175	.data = &(struct clk_regmap_mux_data) {
 176		.offset = CLKCTRL_RTC_CTRL,
 177		.mask = 0x3,
 178		.shift = 0,
 179		.flags = CLK_MUX_ROUND_CLOSEST,
 180	},
 181	.hw.init = &(struct clk_init_data){
 182		.name = "rtc_clk_sel",
 183		.ops = &clk_regmap_mux_ops,
 184		.parent_hws = (const struct clk_hw *[]) {
 185			&s4_rtc_32k_by_oscin.hw,
 186			&s4_rtc_32k_by_oscin_div.hw,
 187		},
 188		.num_parents = 2,
 189		.flags = CLK_SET_RATE_PARENT,
 190	},
 191};
 192
 193/* The index 5 is AXI_CLK, which is dedicated to AXI. So skip it. */
 194static u32 s4_sysclk_parents_val_table[] = { 0, 1, 2, 3, 4, 6, 7 };
 195static const struct clk_parent_data s4_sysclk_parents[] = {
 196	{ .fw_name = "xtal" },
 197	{ .fw_name = "fclk_div2" },
 198	{ .fw_name = "fclk_div3" },
 199	{ .fw_name = "fclk_div4" },
 200	{ .fw_name = "fclk_div5" },
 201	{ .fw_name = "fclk_div7" },
 202	{ .hw = &s4_rtc_clk.hw }
 203};
 204
 205/*
 206 * This clock is initialized by ROMcode.
 207 * The chip was changed SYS CLK for security reasons. SYS CLK registers are not writable
 208 * in the kernel phase. Write of SYS related register will cause the system to crash.
 209 * Meanwhile, these clock won't ever change at runtime.
 210 * For the above reasons, we can only use ro_ops for SYS related clocks.
 211 */
 212static struct clk_regmap s4_sysclk_b_sel = {
 213	.data = &(struct clk_regmap_mux_data){
 214		.offset = CLKCTRL_SYS_CLK_CTRL0,
 215		.mask = 0x7,
 216		.shift = 26,
 217		.table = s4_sysclk_parents_val_table,
 218	},
 219	.hw.init = &(struct clk_init_data){
 220		.name = "sysclk_b_sel",
 221		.ops = &clk_regmap_mux_ro_ops,
 222		.parent_data = s4_sysclk_parents,
 223		.num_parents = ARRAY_SIZE(s4_sysclk_parents),
 224	},
 225};
 226
 227static struct clk_regmap s4_sysclk_b_div = {
 228	.data = &(struct clk_regmap_div_data){
 229		.offset = CLKCTRL_SYS_CLK_CTRL0,
 230		.shift = 16,
 231		.width = 10,
 232	},
 233	.hw.init = &(struct clk_init_data){
 234		.name = "sysclk_b_div",
 235		.ops = &clk_regmap_divider_ro_ops,
 236		.parent_hws = (const struct clk_hw *[]) {
 237			&s4_sysclk_b_sel.hw
 238		},
 239		.num_parents = 1,
 240	},
 241};
 242
 243static struct clk_regmap s4_sysclk_b = {
 244	.data = &(struct clk_regmap_gate_data){
 245		.offset = CLKCTRL_SYS_CLK_CTRL0,
 246		.bit_idx = 29,
 247	},
 248	.hw.init = &(struct clk_init_data) {
 249		.name = "sysclk_b",
 250		.ops = &clk_regmap_gate_ro_ops,
 251		.parent_hws = (const struct clk_hw *[]) {
 252			&s4_sysclk_b_div.hw
 253		},
 254		.num_parents = 1,
 255	},
 256};
 257
 258static struct clk_regmap s4_sysclk_a_sel = {
 259	.data = &(struct clk_regmap_mux_data){
 260		.offset = CLKCTRL_SYS_CLK_CTRL0,
 261		.mask = 0x7,
 262		.shift = 10,
 263		.table = s4_sysclk_parents_val_table,
 264	},
 265	.hw.init = &(struct clk_init_data){
 266		.name = "sysclk_a_sel",
 267		.ops = &clk_regmap_mux_ro_ops,
 268		.parent_data = s4_sysclk_parents,
 269		.num_parents = ARRAY_SIZE(s4_sysclk_parents),
 270	},
 271};
 272
 273static struct clk_regmap s4_sysclk_a_div = {
 274	.data = &(struct clk_regmap_div_data){
 275		.offset = CLKCTRL_SYS_CLK_CTRL0,
 276		.shift = 0,
 277		.width = 10,
 278	},
 279	.hw.init = &(struct clk_init_data){
 280		.name = "sysclk_a_div",
 281		.ops = &clk_regmap_divider_ro_ops,
 282		.parent_hws = (const struct clk_hw *[]) {
 283			&s4_sysclk_a_sel.hw
 284		},
 285		.num_parents = 1,
 286	},
 287};
 288
 289static struct clk_regmap s4_sysclk_a = {
 290	.data = &(struct clk_regmap_gate_data){
 291		.offset = CLKCTRL_SYS_CLK_CTRL0,
 292		.bit_idx = 13,
 293	},
 294	.hw.init = &(struct clk_init_data) {
 295		.name = "sysclk_a",
 296		.ops = &clk_regmap_gate_ro_ops,
 297		.parent_hws = (const struct clk_hw *[]) {
 298			&s4_sysclk_a_div.hw
 299		},
 300		.num_parents = 1,
 301	},
 302};
 303
 304static struct clk_regmap s4_sys_clk = {
 305	.data = &(struct clk_regmap_mux_data){
 306		.offset = CLKCTRL_SYS_CLK_CTRL0,
 307		.mask = 0x1,
 308		.shift = 31,
 309	},
 310	.hw.init = &(struct clk_init_data){
 311		.name = "sys_clk",
 312		.ops = &clk_regmap_mux_ro_ops,
 313		.parent_hws = (const struct clk_hw *[]) {
 314			&s4_sysclk_a.hw,
 315			&s4_sysclk_b.hw
 316		},
 317		.num_parents = 2,
 318	},
 319};
 320
 321static struct clk_regmap s4_ceca_32k_clkin = {
 322	.data = &(struct clk_regmap_gate_data){
 323		.offset = CLKCTRL_CECA_CTRL0,
 324		.bit_idx = 31,
 325	},
 326	.hw.init = &(struct clk_init_data) {
 327		.name = "ceca_32k_clkin",
 328		.ops = &clk_regmap_gate_ops,
 329		.parent_data = (const struct clk_parent_data []) {
 330			{ .fw_name = "xtal", }
 331		},
 332		.num_parents = 1,
 333	},
 334};
 335
 336static struct clk_regmap s4_ceca_32k_div = {
 337	.data = &(struct meson_clk_dualdiv_data){
 338		.n1 = {
 339			.reg_off = CLKCTRL_CECA_CTRL0,
 340			.shift   = 0,
 341			.width   = 12,
 342		},
 343		.n2 = {
 344			.reg_off = CLKCTRL_CECA_CTRL0,
 345			.shift   = 12,
 346			.width   = 12,
 347		},
 348		.m1 = {
 349			.reg_off = CLKCTRL_CECA_CTRL1,
 350			.shift   = 0,
 351			.width   = 12,
 352		},
 353		.m2 = {
 354			.reg_off = CLKCTRL_CECA_CTRL1,
 355			.shift   = 12,
 356			.width   = 12,
 357		},
 358		.dual = {
 359			.reg_off = CLKCTRL_CECA_CTRL0,
 360			.shift   = 28,
 361			.width   = 1,
 362		},
 363		.table = s4_32k_div_table,
 364	},
 365	.hw.init = &(struct clk_init_data){
 366		.name = "ceca_32k_div",
 367		.ops = &meson_clk_dualdiv_ops,
 368		.parent_hws = (const struct clk_hw *[]) {
 369			&s4_ceca_32k_clkin.hw
 370		},
 371		.num_parents = 1,
 372	},
 373};
 374
 375static struct clk_regmap s4_ceca_32k_sel_pre = {
 376	.data = &(struct clk_regmap_mux_data) {
 377		.offset = CLKCTRL_CECA_CTRL1,
 378		.mask = 0x1,
 379		.shift = 24,
 380		.flags = CLK_MUX_ROUND_CLOSEST,
 381	},
 382	.hw.init = &(struct clk_init_data){
 383		.name = "ceca_32k_sel_pre",
 384		.ops = &clk_regmap_mux_ops,
 385		.parent_hws = (const struct clk_hw *[]) {
 386			&s4_ceca_32k_div.hw,
 387			&s4_ceca_32k_clkin.hw
 388		},
 389		.num_parents = 2,
 390		.flags = CLK_SET_RATE_PARENT,
 391	},
 392};
 393
 394static struct clk_regmap s4_ceca_32k_sel = {
 395	.data = &(struct clk_regmap_mux_data) {
 396		.offset = CLKCTRL_CECA_CTRL1,
 397		.mask = 0x1,
 398		.shift = 31,
 399		.flags = CLK_MUX_ROUND_CLOSEST,
 400	},
 401	.hw.init = &(struct clk_init_data){
 402		.name = "ceca_32k_sel",
 403		.ops = &clk_regmap_mux_ops,
 404		.parent_hws = (const struct clk_hw *[]) {
 405			&s4_ceca_32k_sel_pre.hw,
 406			&s4_rtc_clk.hw
 407		},
 408		.num_parents = 2,
 409	},
 410};
 411
 412static struct clk_regmap s4_ceca_32k_clkout = {
 413	.data = &(struct clk_regmap_gate_data){
 414		.offset = CLKCTRL_CECA_CTRL0,
 415		.bit_idx = 30,
 416	},
 417	.hw.init = &(struct clk_init_data){
 418		.name = "ceca_32k_clkout",
 419		.ops = &clk_regmap_gate_ops,
 420		.parent_hws = (const struct clk_hw *[]) {
 421			&s4_ceca_32k_sel.hw
 422		},
 423		.num_parents = 1,
 424		.flags = CLK_SET_RATE_PARENT,
 425	},
 426};
 427
 428static struct clk_regmap s4_cecb_32k_clkin = {
 429	.data = &(struct clk_regmap_gate_data){
 430		.offset = CLKCTRL_CECB_CTRL0,
 431		.bit_idx = 31,
 432	},
 433	.hw.init = &(struct clk_init_data) {
 434		.name = "cecb_32k_clkin",
 435		.ops = &clk_regmap_gate_ops,
 436		.parent_data = (const struct clk_parent_data []) {
 437			{ .fw_name = "xtal", }
 438		},
 439		.num_parents = 1,
 440	},
 441};
 442
 443static struct clk_regmap s4_cecb_32k_div = {
 444	.data = &(struct meson_clk_dualdiv_data){
 445		.n1 = {
 446			.reg_off = CLKCTRL_CECB_CTRL0,
 447			.shift   = 0,
 448			.width   = 12,
 449		},
 450		.n2 = {
 451			.reg_off = CLKCTRL_CECB_CTRL0,
 452			.shift   = 12,
 453			.width   = 12,
 454		},
 455		.m1 = {
 456			.reg_off = CLKCTRL_CECB_CTRL1,
 457			.shift   = 0,
 458			.width   = 12,
 459		},
 460		.m2 = {
 461			.reg_off = CLKCTRL_CECB_CTRL1,
 462			.shift   = 12,
 463			.width   = 12,
 464		},
 465		.dual = {
 466			.reg_off = CLKCTRL_CECB_CTRL0,
 467			.shift   = 28,
 468			.width   = 1,
 469		},
 470		.table = s4_32k_div_table,
 471	},
 472	.hw.init = &(struct clk_init_data){
 473		.name = "cecb_32k_div",
 474		.ops = &meson_clk_dualdiv_ops,
 475		.parent_hws = (const struct clk_hw *[]) {
 476			&s4_cecb_32k_clkin.hw
 477		},
 478		.num_parents = 1,
 479	},
 480};
 481
 482static struct clk_regmap s4_cecb_32k_sel_pre = {
 483	.data = &(struct clk_regmap_mux_data) {
 484		.offset = CLKCTRL_CECB_CTRL1,
 485		.mask = 0x1,
 486		.shift = 24,
 487		.flags = CLK_MUX_ROUND_CLOSEST,
 488	},
 489	.hw.init = &(struct clk_init_data){
 490		.name = "cecb_32k_sel_pre",
 491		.ops = &clk_regmap_mux_ops,
 492		.parent_hws = (const struct clk_hw *[]) {
 493			&s4_cecb_32k_div.hw,
 494			&s4_cecb_32k_clkin.hw
 495		},
 496		.num_parents = 2,
 497		.flags = CLK_SET_RATE_PARENT,
 498	},
 499};
 500
 501static struct clk_regmap s4_cecb_32k_sel = {
 502	.data = &(struct clk_regmap_mux_data) {
 503		.offset = CLKCTRL_CECB_CTRL1,
 504		.mask = 0x1,
 505		.shift = 31,
 506		.flags = CLK_MUX_ROUND_CLOSEST,
 507	},
 508	.hw.init = &(struct clk_init_data){
 509		.name = "cecb_32k_sel",
 510		.ops = &clk_regmap_mux_ops,
 511		.parent_hws = (const struct clk_hw *[]) {
 512			&s4_cecb_32k_sel_pre.hw,
 513			&s4_rtc_clk.hw
 514		},
 515		.num_parents = 2,
 516	},
 517};
 518
 519static struct clk_regmap s4_cecb_32k_clkout = {
 520	.data = &(struct clk_regmap_gate_data){
 521		.offset = CLKCTRL_CECB_CTRL0,
 522		.bit_idx = 30,
 523	},
 524	.hw.init = &(struct clk_init_data){
 525		.name = "cecb_32k_clkout",
 526		.ops = &clk_regmap_gate_ops,
 527		.parent_hws = (const struct clk_hw *[]) {
 528			&s4_cecb_32k_sel.hw
 529		},
 530		.num_parents = 1,
 531		.flags = CLK_SET_RATE_PARENT,
 532	},
 533};
 534
 535static const struct clk_parent_data s4_sc_clk_parents[] = {
 536	{ .fw_name = "fclk_div4" },
 537	{ .fw_name = "fclk_div3" },
 538	{ .fw_name = "fclk_div5" },
 539	{ .fw_name = "xtal", }
 540};
 541
 542static struct clk_regmap s4_sc_clk_sel = {
 543	.data = &(struct clk_regmap_mux_data){
 544		.offset = CLKCTRL_SC_CLK_CTRL,
 545		.mask = 0x3,
 546		.shift = 9,
 547	},
 548	.hw.init = &(struct clk_init_data) {
 549		.name = "sc_clk_sel",
 550		.ops = &clk_regmap_mux_ops,
 551		.parent_data = s4_sc_clk_parents,
 552		.num_parents = ARRAY_SIZE(s4_sc_clk_parents),
 553		.flags = CLK_SET_RATE_PARENT,
 554	},
 555};
 556
 557static struct clk_regmap s4_sc_clk_div = {
 558	.data = &(struct clk_regmap_div_data){
 559		.offset = CLKCTRL_SC_CLK_CTRL,
 560		.shift = 0,
 561		.width = 8,
 562	},
 563	.hw.init = &(struct clk_init_data) {
 564		.name = "sc_clk_div",
 565		.ops = &clk_regmap_divider_ops,
 566		.parent_hws = (const struct clk_hw *[]) {
 567			&s4_sc_clk_sel.hw
 568		},
 569		.num_parents = 1,
 570		.flags = CLK_SET_RATE_PARENT,
 571	},
 572};
 573
 574static struct clk_regmap s4_sc_clk = {
 575	.data = &(struct clk_regmap_gate_data){
 576		.offset = CLKCTRL_SC_CLK_CTRL,
 577		.bit_idx = 8,
 578	},
 579	.hw.init = &(struct clk_init_data){
 580		.name = "sc_clk",
 581		.ops = &clk_regmap_gate_ops,
 582		.parent_hws = (const struct clk_hw *[]) {
 583			&s4_sc_clk_div.hw
 584		},
 585		.num_parents = 1,
 586		.flags = CLK_SET_RATE_PARENT,
 587	},
 588};
 589
 590static struct clk_regmap s4_12_24M = {
 591	.data = &(struct clk_regmap_gate_data){
 592		.offset = CLKCTRL_CLK12_24_CTRL,
 593		.bit_idx = 11,
 594	},
 595	.hw.init = &(struct clk_init_data) {
 596		.name = "12_24M",
 597		.ops = &clk_regmap_gate_ops,
 598		.parent_data = (const struct clk_parent_data []) {
 599			{ .fw_name = "xtal", }
 600		},
 601		.num_parents = 1,
 602	},
 603};
 604
 605static struct clk_fixed_factor s4_12M_div = {
 606	.mult = 1,
 607	.div = 2,
 608	.hw.init = &(struct clk_init_data){
 609		.name = "12M_div",
 610		.ops = &clk_fixed_factor_ops,
 611		.parent_hws = (const struct clk_hw *[]) {
 612			&s4_12_24M.hw
 613		},
 614		.num_parents = 1,
 615		.flags = CLK_SET_RATE_PARENT,
 616	},
 617};
 618
 619static struct clk_regmap s4_12_24M_sel = {
 620	.data = &(struct clk_regmap_mux_data){
 621		.offset = CLKCTRL_CLK12_24_CTRL,
 622		.mask = 0x1,
 623		.shift = 10,
 624	},
 625	.hw.init = &(struct clk_init_data) {
 626		.name = "12_24M_sel",
 627		.ops = &clk_regmap_mux_ops,
 628		.parent_hws = (const struct clk_hw *[]) {
 629			&s4_12_24M.hw,
 630			&s4_12M_div.hw,
 631		},
 632		.num_parents = 2,
 633		.flags = CLK_SET_RATE_PARENT,
 634	},
 635};
 636
 637/* Video Clocks */
 638static struct clk_regmap s4_vid_pll_div = {
 639	.data = &(struct meson_vid_pll_div_data){
 640		.val = {
 641			.reg_off = CLKCTRL_VID_PLL_CLK_DIV,
 642			.shift   = 0,
 643			.width   = 15,
 644		},
 645		.sel = {
 646			.reg_off = CLKCTRL_VID_PLL_CLK_DIV,
 647			.shift   = 16,
 648			.width   = 2,
 649		},
 650	},
 651	.hw.init = &(struct clk_init_data) {
 652		.name = "vid_pll_div",
 653		/*
 654		 * TODO meson_vid_pll_div_ro_ops to meson_vid_pll_div_ops
 655		 */
 656		.ops = &meson_vid_pll_div_ro_ops,
 657		.parent_data = (const struct clk_parent_data []) {
 658			{ .fw_name = "hdmi_pll", }
 659		},
 660		.num_parents = 1,
 661		.flags = CLK_SET_RATE_PARENT,
 662	},
 663};
 664
 665static struct clk_regmap s4_vid_pll_sel = {
 666	.data = &(struct clk_regmap_mux_data){
 667		.offset = CLKCTRL_VID_PLL_CLK_DIV,
 668		.mask = 0x1,
 669		.shift = 18,
 670	},
 671	.hw.init = &(struct clk_init_data){
 672		.name = "vid_pll_sel",
 673		.ops = &clk_regmap_mux_ops,
 674		.parent_data = (const struct clk_parent_data []) {
 675			{ .hw = &s4_vid_pll_div.hw },
 676			{ .fw_name = "hdmi_pll", }
 677		},
 678		.num_parents = 2,
 679		.flags = CLK_SET_RATE_PARENT,
 680	},
 681};
 682
 683static struct clk_regmap s4_vid_pll = {
 684	.data = &(struct clk_regmap_gate_data){
 685		.offset = CLKCTRL_VID_PLL_CLK_DIV,
 686		.bit_idx = 19,
 687	},
 688	.hw.init = &(struct clk_init_data) {
 689		.name = "vid_pll",
 690		.ops = &clk_regmap_gate_ops,
 691		.parent_hws = (const struct clk_hw *[]) {
 692			&s4_vid_pll_sel.hw
 693		},
 694		.num_parents = 1,
 695		.flags = CLK_SET_RATE_PARENT,
 696	},
 697};
 698
 699static const struct clk_parent_data s4_vclk_parents[] = {
 700	{ .hw = &s4_vid_pll.hw },
 701	{ .fw_name = "gp0_pll", },
 702	{ .fw_name = "hifi_pll", },
 703	{ .fw_name = "mpll1", },
 704	{ .fw_name = "fclk_div3", },
 705	{ .fw_name = "fclk_div4", },
 706	{ .fw_name = "fclk_div5", },
 707	{ .fw_name = "fclk_div7", },
 708};
 709
 710static struct clk_regmap s4_vclk_sel = {
 711	.data = &(struct clk_regmap_mux_data){
 712		.offset = CLKCTRL_VID_CLK_CTRL,
 713		.mask = 0x7,
 714		.shift = 16,
 715	},
 716	.hw.init = &(struct clk_init_data){
 717		.name = "vclk_sel",
 718		.ops = &clk_regmap_mux_ops,
 719		.parent_data = s4_vclk_parents,
 720		.num_parents = ARRAY_SIZE(s4_vclk_parents),
 721		.flags = 0,
 722	},
 723};
 724
 725static struct clk_regmap s4_vclk2_sel = {
 726	.data = &(struct clk_regmap_mux_data){
 727		.offset = CLKCTRL_VIID_CLK_CTRL,
 728		.mask = 0x7,
 729		.shift = 16,
 730	},
 731	.hw.init = &(struct clk_init_data){
 732		.name = "vclk2_sel",
 733		.ops = &clk_regmap_mux_ops,
 734		.parent_data = s4_vclk_parents,
 735		.num_parents = ARRAY_SIZE(s4_vclk_parents),
 736		.flags = 0,
 737	},
 738};
 739
 740static struct clk_regmap s4_vclk_input = {
 741	.data = &(struct clk_regmap_gate_data){
 742		.offset = CLKCTRL_VID_CLK_DIV,
 743		.bit_idx = 16,
 744	},
 745	.hw.init = &(struct clk_init_data) {
 746		.name = "vclk_input",
 747		.ops = &clk_regmap_gate_ops,
 748		.parent_hws = (const struct clk_hw *[]) { &s4_vclk_sel.hw },
 749		.num_parents = 1,
 750		.flags = CLK_SET_RATE_PARENT,
 751	},
 752};
 753
 754static struct clk_regmap s4_vclk2_input = {
 755	.data = &(struct clk_regmap_gate_data){
 756		.offset = CLKCTRL_VIID_CLK_DIV,
 757		.bit_idx = 16,
 758	},
 759	.hw.init = &(struct clk_init_data) {
 760		.name = "vclk2_input",
 761		.ops = &clk_regmap_gate_ops,
 762		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2_sel.hw },
 763		.num_parents = 1,
 764		.flags = CLK_SET_RATE_PARENT,
 765	},
 766};
 767
 768static struct clk_regmap s4_vclk_div = {
 769	.data = &(struct clk_regmap_div_data){
 770		.offset = CLKCTRL_VID_CLK_DIV,
 771		.shift = 0,
 772		.width = 8,
 773	},
 774	.hw.init = &(struct clk_init_data){
 775		.name = "vclk_div",
 776		.ops = &clk_regmap_divider_ops,
 777		.parent_hws = (const struct clk_hw *[]) {
 778			&s4_vclk_input.hw
 779		},
 780		.num_parents = 1,
 781		.flags = CLK_SET_RATE_PARENT,
 782	},
 783};
 784
 785static struct clk_regmap s4_vclk2_div = {
 786	.data = &(struct clk_regmap_div_data){
 787		.offset = CLKCTRL_VIID_CLK_DIV,
 788		.shift = 0,
 789		.width = 8,
 790	},
 791	.hw.init = &(struct clk_init_data){
 792		.name = "vclk2_div",
 793		.ops = &clk_regmap_divider_ops,
 794		.parent_hws = (const struct clk_hw *[]) {
 795			&s4_vclk2_input.hw
 796		},
 797		.num_parents = 1,
 798		.flags = CLK_SET_RATE_PARENT,
 799	},
 800};
 801
 802static struct clk_regmap s4_vclk = {
 803	.data = &(struct clk_regmap_gate_data){
 804		.offset = CLKCTRL_VID_CLK_CTRL,
 805		.bit_idx = 19,
 806	},
 807	.hw.init = &(struct clk_init_data) {
 808		.name = "vclk",
 809		.ops = &clk_regmap_gate_ops,
 810		.parent_hws = (const struct clk_hw *[]) { &s4_vclk_div.hw },
 811		.num_parents = 1,
 812		.flags = CLK_SET_RATE_PARENT,
 813	},
 814};
 815
 816static struct clk_regmap s4_vclk2 = {
 817	.data = &(struct clk_regmap_gate_data){
 818		.offset = CLKCTRL_VIID_CLK_CTRL,
 819		.bit_idx = 19,
 820	},
 821	.hw.init = &(struct clk_init_data) {
 822		.name = "vclk2",
 823		.ops = &clk_regmap_gate_ops,
 824		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2_div.hw },
 825		.num_parents = 1,
 826		.flags = CLK_SET_RATE_PARENT,
 827	},
 828};
 829
 830static struct clk_regmap s4_vclk_div1 = {
 831	.data = &(struct clk_regmap_gate_data){
 832		.offset = CLKCTRL_VID_CLK_CTRL,
 833		.bit_idx = 0,
 834	},
 835	.hw.init = &(struct clk_init_data) {
 836		.name = "vclk_div1",
 837		.ops = &clk_regmap_gate_ops,
 838		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
 839		.num_parents = 1,
 840		.flags = CLK_SET_RATE_PARENT,
 841	},
 842};
 843
 844static struct clk_regmap s4_vclk_div2_en = {
 845	.data = &(struct clk_regmap_gate_data){
 846		.offset = CLKCTRL_VID_CLK_CTRL,
 847		.bit_idx = 1,
 848	},
 849	.hw.init = &(struct clk_init_data) {
 850		.name = "vclk_div2_en",
 851		.ops = &clk_regmap_gate_ops,
 852		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
 853		.num_parents = 1,
 854		.flags = CLK_SET_RATE_PARENT,
 855	},
 856};
 857
 858static struct clk_regmap s4_vclk_div4_en = {
 859	.data = &(struct clk_regmap_gate_data){
 860		.offset = CLKCTRL_VID_CLK_CTRL,
 861		.bit_idx = 2,
 862	},
 863	.hw.init = &(struct clk_init_data) {
 864		.name = "vclk_div4_en",
 865		.ops = &clk_regmap_gate_ops,
 866		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
 867		.num_parents = 1,
 868		.flags = CLK_SET_RATE_PARENT,
 869	},
 870};
 871
 872static struct clk_regmap s4_vclk_div6_en = {
 873	.data = &(struct clk_regmap_gate_data){
 874		.offset = CLKCTRL_VID_CLK_CTRL,
 875		.bit_idx = 3,
 876	},
 877	.hw.init = &(struct clk_init_data) {
 878		.name = "vclk_div6_en",
 879		.ops = &clk_regmap_gate_ops,
 880		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
 881		.num_parents = 1,
 882		.flags = CLK_SET_RATE_PARENT,
 883	},
 884};
 885
 886static struct clk_regmap s4_vclk_div12_en = {
 887	.data = &(struct clk_regmap_gate_data){
 888		.offset = CLKCTRL_VID_CLK_CTRL,
 889		.bit_idx = 4,
 890	},
 891	.hw.init = &(struct clk_init_data) {
 892		.name = "vclk_div12_en",
 893		.ops = &clk_regmap_gate_ops,
 894		.parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw },
 895		.num_parents = 1,
 896		.flags = CLK_SET_RATE_PARENT,
 897	},
 898};
 899
 900static struct clk_regmap s4_vclk2_div1 = {
 901	.data = &(struct clk_regmap_gate_data){
 902		.offset = CLKCTRL_VIID_CLK_CTRL,
 903		.bit_idx = 0,
 904	},
 905	.hw.init = &(struct clk_init_data) {
 906		.name = "vclk2_div1",
 907		.ops = &clk_regmap_gate_ops,
 908		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
 909		.num_parents = 1,
 910		.flags = CLK_SET_RATE_PARENT,
 911	},
 912};
 913
 914static struct clk_regmap s4_vclk2_div2_en = {
 915	.data = &(struct clk_regmap_gate_data){
 916		.offset = CLKCTRL_VIID_CLK_CTRL,
 917		.bit_idx = 1,
 918	},
 919	.hw.init = &(struct clk_init_data) {
 920		.name = "vclk2_div2_en",
 921		.ops = &clk_regmap_gate_ops,
 922		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
 923		.num_parents = 1,
 924		.flags = CLK_SET_RATE_PARENT,
 925	},
 926};
 927
 928static struct clk_regmap s4_vclk2_div4_en = {
 929	.data = &(struct clk_regmap_gate_data){
 930		.offset = CLKCTRL_VIID_CLK_CTRL,
 931		.bit_idx = 2,
 932	},
 933	.hw.init = &(struct clk_init_data) {
 934		.name = "vclk2_div4_en",
 935		.ops = &clk_regmap_gate_ops,
 936		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
 937		.num_parents = 1,
 938		.flags = CLK_SET_RATE_PARENT,
 939	},
 940};
 941
 942static struct clk_regmap s4_vclk2_div6_en = {
 943	.data = &(struct clk_regmap_gate_data){
 944		.offset = CLKCTRL_VIID_CLK_CTRL,
 945		.bit_idx = 3,
 946	},
 947	.hw.init = &(struct clk_init_data) {
 948		.name = "vclk2_div6_en",
 949		.ops = &clk_regmap_gate_ops,
 950		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
 951		.num_parents = 1,
 952		.flags = CLK_SET_RATE_PARENT,
 953	},
 954};
 955
 956static struct clk_regmap s4_vclk2_div12_en = {
 957	.data = &(struct clk_regmap_gate_data){
 958		.offset = CLKCTRL_VIID_CLK_CTRL,
 959		.bit_idx = 4,
 960	},
 961	.hw.init = &(struct clk_init_data) {
 962		.name = "vclk2_div12_en",
 963		.ops = &clk_regmap_gate_ops,
 964		.parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw },
 965		.num_parents = 1,
 966		.flags = CLK_SET_RATE_PARENT,
 967	},
 968};
 969
 970static struct clk_fixed_factor s4_vclk_div2 = {
 971	.mult = 1,
 972	.div = 2,
 973	.hw.init = &(struct clk_init_data){
 974		.name = "vclk_div2",
 975		.ops = &clk_fixed_factor_ops,
 976		.parent_hws = (const struct clk_hw *[]) {
 977			&s4_vclk_div2_en.hw
 978		},
 979		.num_parents = 1,
 980		.flags = CLK_SET_RATE_PARENT,
 981	},
 982};
 983
 984static struct clk_fixed_factor s4_vclk_div4 = {
 985	.mult = 1,
 986	.div = 4,
 987	.hw.init = &(struct clk_init_data){
 988		.name = "vclk_div4",
 989		.ops = &clk_fixed_factor_ops,
 990		.parent_hws = (const struct clk_hw *[]) {
 991			&s4_vclk_div4_en.hw
 992		},
 993		.num_parents = 1,
 994		.flags = CLK_SET_RATE_PARENT,
 995	},
 996};
 997
 998static struct clk_fixed_factor s4_vclk_div6 = {
 999	.mult = 1,
1000	.div = 6,
1001	.hw.init = &(struct clk_init_data){
1002		.name = "vclk_div6",
1003		.ops = &clk_fixed_factor_ops,
1004		.parent_hws = (const struct clk_hw *[]) {
1005			&s4_vclk_div6_en.hw
1006		},
1007		.num_parents = 1,
1008		.flags = CLK_SET_RATE_PARENT,
1009	},
1010};
1011
1012static struct clk_fixed_factor s4_vclk_div12 = {
1013	.mult = 1,
1014	.div = 12,
1015	.hw.init = &(struct clk_init_data){
1016		.name = "vclk_div12",
1017		.ops = &clk_fixed_factor_ops,
1018		.parent_hws = (const struct clk_hw *[]) {
1019			&s4_vclk_div12_en.hw
1020		},
1021		.num_parents = 1,
1022		.flags = CLK_SET_RATE_PARENT,
1023	},
1024};
1025
1026static struct clk_fixed_factor s4_vclk2_div2 = {
1027	.mult = 1,
1028	.div = 2,
1029	.hw.init = &(struct clk_init_data){
1030		.name = "vclk2_div2",
1031		.ops = &clk_fixed_factor_ops,
1032		.parent_hws = (const struct clk_hw *[]) {
1033			&s4_vclk2_div2_en.hw
1034		},
1035		.num_parents = 1,
1036		.flags = CLK_SET_RATE_PARENT,
1037	},
1038};
1039
1040static struct clk_fixed_factor s4_vclk2_div4 = {
1041	.mult = 1,
1042	.div = 4,
1043	.hw.init = &(struct clk_init_data){
1044		.name = "vclk2_div4",
1045		.ops = &clk_fixed_factor_ops,
1046		.parent_hws = (const struct clk_hw *[]) {
1047			&s4_vclk2_div4_en.hw
1048		},
1049		.num_parents = 1,
1050		.flags = CLK_SET_RATE_PARENT,
1051	},
1052};
1053
1054static struct clk_fixed_factor s4_vclk2_div6 = {
1055	.mult = 1,
1056	.div = 6,
1057	.hw.init = &(struct clk_init_data){
1058		.name = "vclk2_div6",
1059		.ops = &clk_fixed_factor_ops,
1060		.parent_hws = (const struct clk_hw *[]) {
1061			&s4_vclk2_div6_en.hw
1062		},
1063		.num_parents = 1,
1064		.flags = CLK_SET_RATE_PARENT,
1065	},
1066};
1067
1068static struct clk_fixed_factor s4_vclk2_div12 = {
1069	.mult = 1,
1070	.div = 12,
1071	.hw.init = &(struct clk_init_data){
1072		.name = "vclk2_div12",
1073		.ops = &clk_fixed_factor_ops,
1074		.parent_hws = (const struct clk_hw *[]) {
1075			&s4_vclk2_div12_en.hw
1076		},
1077		.num_parents = 1,
1078		.flags = CLK_SET_RATE_PARENT,
1079	},
1080};
1081
1082/* The 5,6,7 indexes corresponds to no real clock, so there are not used. */
1083static u32 s4_cts_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1084static const struct clk_hw *s4_cts_parents[] = {
1085	&s4_vclk_div1.hw,
1086	&s4_vclk_div2.hw,
1087	&s4_vclk_div4.hw,
1088	&s4_vclk_div6.hw,
1089	&s4_vclk_div12.hw,
1090	&s4_vclk2_div1.hw,
1091	&s4_vclk2_div2.hw,
1092	&s4_vclk2_div4.hw,
1093	&s4_vclk2_div6.hw,
1094	&s4_vclk2_div12.hw
1095};
1096
1097static struct clk_regmap s4_cts_enci_sel = {
1098	.data = &(struct clk_regmap_mux_data){
1099		.offset = CLKCTRL_VID_CLK_DIV,
1100		.mask = 0xf,
1101		.shift = 28,
1102		.table = s4_cts_parents_val_table,
1103	},
1104	.hw.init = &(struct clk_init_data){
1105		.name = "cts_enci_sel",
1106		.ops = &clk_regmap_mux_ops,
1107		.parent_hws = s4_cts_parents,
1108		.num_parents = ARRAY_SIZE(s4_cts_parents),
1109	},
1110};
1111
1112static struct clk_regmap s4_cts_encp_sel = {
1113	.data = &(struct clk_regmap_mux_data){
1114		.offset = CLKCTRL_VID_CLK_DIV,
1115		.mask = 0xf,
1116		.shift = 20,
1117		.table = s4_cts_parents_val_table,
1118	},
1119	.hw.init = &(struct clk_init_data){
1120		.name = "cts_encp_sel",
1121		.ops = &clk_regmap_mux_ops,
1122		.parent_hws = s4_cts_parents,
1123		.num_parents = ARRAY_SIZE(s4_cts_parents),
1124	},
1125};
1126
1127static struct clk_regmap s4_cts_vdac_sel = {
1128	.data = &(struct clk_regmap_mux_data){
1129		.offset = CLKCTRL_VIID_CLK_DIV,
1130		.mask = 0xf,
1131		.shift = 28,
1132		.table = s4_cts_parents_val_table,
1133	},
1134	.hw.init = &(struct clk_init_data){
1135		.name = "cts_vdac_sel",
1136		.ops = &clk_regmap_mux_ops,
1137		.parent_hws = s4_cts_parents,
1138		.num_parents = ARRAY_SIZE(s4_cts_parents),
1139	},
1140};
1141
1142/* The 5,6,7 indexes corresponds to no real clock, so there are not used. */
1143static u32 s4_hdmi_tx_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1144static const struct clk_hw *s4_hdmi_tx_parents[] = {
1145	&s4_vclk_div1.hw,
1146	&s4_vclk_div2.hw,
1147	&s4_vclk_div4.hw,
1148	&s4_vclk_div6.hw,
1149	&s4_vclk_div12.hw,
1150	&s4_vclk2_div1.hw,
1151	&s4_vclk2_div2.hw,
1152	&s4_vclk2_div4.hw,
1153	&s4_vclk2_div6.hw,
1154	&s4_vclk2_div12.hw
1155};
1156
1157static struct clk_regmap s4_hdmi_tx_sel = {
1158	.data = &(struct clk_regmap_mux_data){
1159		.offset = CLKCTRL_HDMI_CLK_CTRL,
1160		.mask = 0xf,
1161		.shift = 16,
1162		.table = s4_hdmi_tx_parents_val_table,
1163	},
1164	.hw.init = &(struct clk_init_data){
1165		.name = "hdmi_tx_sel",
1166		.ops = &clk_regmap_mux_ops,
1167		.parent_hws = s4_hdmi_tx_parents,
1168		.num_parents = ARRAY_SIZE(s4_hdmi_tx_parents),
1169	},
1170};
1171
1172static struct clk_regmap s4_cts_enci = {
1173	.data = &(struct clk_regmap_gate_data){
1174		.offset = CLKCTRL_VID_CLK_CTRL2,
1175		.bit_idx = 0,
1176	},
1177	.hw.init = &(struct clk_init_data) {
1178		.name = "cts_enci",
1179		.ops = &clk_regmap_gate_ops,
1180		.parent_hws = (const struct clk_hw *[]) {
1181			&s4_cts_enci_sel.hw
1182		},
1183		.num_parents = 1,
1184		.flags = CLK_SET_RATE_PARENT,
1185	},
1186};
1187
1188static struct clk_regmap s4_cts_encp = {
1189	.data = &(struct clk_regmap_gate_data){
1190		.offset = CLKCTRL_VID_CLK_CTRL2,
1191		.bit_idx = 2,
1192	},
1193	.hw.init = &(struct clk_init_data) {
1194		.name = "cts_encp",
1195		.ops = &clk_regmap_gate_ops,
1196		.parent_hws = (const struct clk_hw *[]) {
1197			&s4_cts_encp_sel.hw
1198		},
1199		.num_parents = 1,
1200		.flags = CLK_SET_RATE_PARENT,
1201	},
1202};
1203
1204static struct clk_regmap s4_cts_vdac = {
1205	.data = &(struct clk_regmap_gate_data){
1206		.offset = CLKCTRL_VID_CLK_CTRL2,
1207		.bit_idx = 4,
1208	},
1209	.hw.init = &(struct clk_init_data) {
1210		.name = "cts_vdac",
1211		.ops = &clk_regmap_gate_ops,
1212		.parent_hws = (const struct clk_hw *[]) {
1213			&s4_cts_vdac_sel.hw
1214		},
1215		.num_parents = 1,
1216		.flags = CLK_SET_RATE_PARENT,
1217	},
1218};
1219
1220static struct clk_regmap s4_hdmi_tx = {
1221	.data = &(struct clk_regmap_gate_data){
1222		.offset = CLKCTRL_VID_CLK_CTRL2,
1223		.bit_idx = 5,
1224	},
1225	.hw.init = &(struct clk_init_data) {
1226		.name = "hdmi_tx",
1227		.ops = &clk_regmap_gate_ops,
1228		.parent_hws = (const struct clk_hw *[]) {
1229			&s4_hdmi_tx_sel.hw
1230		},
1231		.num_parents = 1,
1232		.flags = CLK_SET_RATE_PARENT,
1233	},
1234};
1235
1236/* HDMI Clocks */
1237static const struct clk_parent_data s4_hdmi_parents[] = {
1238	{ .fw_name = "xtal", },
1239	{ .fw_name = "fclk_div4", },
1240	{ .fw_name = "fclk_div3", },
1241	{ .fw_name = "fclk_div5", }
1242};
1243
1244static struct clk_regmap s4_hdmi_sel = {
1245	.data = &(struct clk_regmap_mux_data){
1246		.offset = CLKCTRL_HDMI_CLK_CTRL,
1247		.mask = 0x3,
1248		.shift = 9,
1249		.flags = CLK_MUX_ROUND_CLOSEST,
1250	},
1251	.hw.init = &(struct clk_init_data){
1252		.name = "hdmi_sel",
1253		.ops = &clk_regmap_mux_ops,
1254		.parent_data = s4_hdmi_parents,
1255		.num_parents = ARRAY_SIZE(s4_hdmi_parents),
1256		.flags = CLK_SET_RATE_PARENT,
1257	},
1258};
1259
1260static struct clk_regmap s4_hdmi_div = {
1261	.data = &(struct clk_regmap_div_data){
1262		.offset = CLKCTRL_HDMI_CLK_CTRL,
1263		.shift = 0,
1264		.width = 7,
1265	},
1266	.hw.init = &(struct clk_init_data){
1267		.name = "hdmi_div",
1268		.ops = &clk_regmap_divider_ops,
1269		.parent_hws = (const struct clk_hw *[]) { &s4_hdmi_sel.hw },
1270		.num_parents = 1,
1271		.flags = CLK_SET_RATE_PARENT,
1272	},
1273};
1274
1275static struct clk_regmap s4_hdmi = {
1276	.data = &(struct clk_regmap_gate_data){
1277		.offset = CLKCTRL_HDMI_CLK_CTRL,
1278		.bit_idx = 8,
1279	},
1280	.hw.init = &(struct clk_init_data) {
1281		.name = "hdmi",
1282		.ops = &clk_regmap_gate_ops,
1283		.parent_hws = (const struct clk_hw *[]) { &s4_hdmi_div.hw },
1284		.num_parents = 1,
1285		.flags = CLK_SET_RATE_PARENT,
1286	},
1287};
1288
1289static struct clk_regmap s4_ts_clk_div = {
1290	.data = &(struct clk_regmap_div_data){
1291		.offset = CLKCTRL_TS_CLK_CTRL,
1292		.shift = 0,
1293		.width = 8,
1294	},
1295	.hw.init = &(struct clk_init_data){
1296		.name = "ts_clk_div",
1297		.ops = &clk_regmap_divider_ops,
1298		.parent_data = &(const struct clk_parent_data) {
1299			.fw_name = "xtal",
1300		},
1301		.num_parents = 1,
1302		.flags = CLK_SET_RATE_PARENT,
1303	},
1304};
1305
1306static struct clk_regmap s4_ts_clk = {
1307	.data = &(struct clk_regmap_gate_data){
1308		.offset = CLKCTRL_TS_CLK_CTRL,
1309		.bit_idx = 8,
1310	},
1311	.hw.init = &(struct clk_init_data){
1312		.name = "ts_clk",
1313		.ops = &clk_regmap_gate_ops,
1314		.parent_hws = (const struct clk_hw *[]) {
1315			&s4_ts_clk_div.hw
1316		},
1317		.num_parents = 1,
1318		.flags = CLK_SET_RATE_PARENT,
1319	},
1320};
1321
1322/*
1323 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
1324 * muxed by a glitch-free switch. The CCF can manage this glitch-free
1325 * mux because it does top-to-bottom updates the each clock tree and
1326 * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
1327 */
1328static const struct clk_parent_data s4_mali_parents[] = {
1329	{ .fw_name = "xtal", },
1330	{ .fw_name = "gp0_pll", },
1331	{ .fw_name = "hifi_pll", },
1332	{ .fw_name = "fclk_div2p5", },
1333	{ .fw_name = "fclk_div3", },
1334	{ .fw_name = "fclk_div4", },
1335	{ .fw_name = "fclk_div5", },
1336	{ .fw_name = "fclk_div7", }
1337};
1338
1339static struct clk_regmap s4_mali_0_sel = {
1340	.data = &(struct clk_regmap_mux_data){
1341		.offset = CLKCTRL_MALI_CLK_CTRL,
1342		.mask = 0x7,
1343		.shift = 9,
1344	},
1345	.hw.init = &(struct clk_init_data){
1346		.name = "mali_0_sel",
1347		.ops = &clk_regmap_mux_ops,
1348		.parent_data = s4_mali_parents,
1349		.num_parents = ARRAY_SIZE(s4_mali_parents),
1350		/*
1351		 * Don't request the parent to change the rate because
1352		 * all GPU frequencies can be derived from the fclk_*
1353		 * clocks and one special GP0_PLL setting. This is
1354		 * important because we need the HIFI PLL clock for audio.
1355		 */
1356		.flags = 0,
1357	},
1358};
1359
1360static struct clk_regmap s4_mali_0_div = {
1361	.data = &(struct clk_regmap_div_data){
1362		.offset = CLKCTRL_MALI_CLK_CTRL,
1363		.shift = 0,
1364		.width = 7,
1365	},
1366	.hw.init = &(struct clk_init_data){
1367		.name = "mali_0_div",
1368		.ops = &clk_regmap_divider_ops,
1369		.parent_hws = (const struct clk_hw *[]) {
1370			&s4_mali_0_sel.hw
1371		},
1372		.num_parents = 1,
1373		.flags = CLK_SET_RATE_PARENT,
1374	},
1375};
1376
1377static struct clk_regmap s4_mali_0 = {
1378	.data = &(struct clk_regmap_gate_data){
1379		.offset = CLKCTRL_MALI_CLK_CTRL,
1380		.bit_idx = 8,
1381	},
1382	.hw.init = &(struct clk_init_data){
1383		.name = "mali_0",
1384		.ops = &clk_regmap_gate_ops,
1385		.parent_hws = (const struct clk_hw *[]) {
1386			&s4_mali_0_div.hw
1387		},
1388		.num_parents = 1,
1389		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1390	},
1391};
1392
1393static struct clk_regmap s4_mali_1_sel = {
1394	.data = &(struct clk_regmap_mux_data){
1395		.offset = CLKCTRL_MALI_CLK_CTRL,
1396		.mask = 0x7,
1397		.shift = 25,
1398	},
1399	.hw.init = &(struct clk_init_data){
1400		.name = "mali_1_sel",
1401		.ops = &clk_regmap_mux_ops,
1402		.parent_data = s4_mali_parents,
1403		.num_parents = ARRAY_SIZE(s4_mali_parents),
1404		.flags = 0,
1405	},
1406};
1407
1408static struct clk_regmap s4_mali_1_div = {
1409	.data = &(struct clk_regmap_div_data){
1410		.offset = CLKCTRL_MALI_CLK_CTRL,
1411		.shift = 16,
1412		.width = 7,
1413	},
1414	.hw.init = &(struct clk_init_data){
1415		.name = "mali_1_div",
1416		.ops = &clk_regmap_divider_ops,
1417		.parent_hws = (const struct clk_hw *[]) {
1418			&s4_mali_1_sel.hw
1419		},
1420		.num_parents = 1,
1421		.flags = CLK_SET_RATE_PARENT,
1422	},
1423};
1424
1425static struct clk_regmap s4_mali_1 = {
1426	.data = &(struct clk_regmap_gate_data){
1427		.offset = CLKCTRL_MALI_CLK_CTRL,
1428		.bit_idx = 24,
1429	},
1430	.hw.init = &(struct clk_init_data){
1431		.name = "mali_1",
1432		.ops = &clk_regmap_gate_ops,
1433		.parent_hws = (const struct clk_hw *[]) {
1434			&s4_mali_1_div.hw
1435		},
1436		.num_parents = 1,
1437		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1438	},
1439};
1440
1441static struct clk_regmap s4_mali_sel = {
1442	.data = &(struct clk_regmap_mux_data){
1443		.offset = CLKCTRL_MALI_CLK_CTRL,
1444		.mask = 1,
1445		.shift = 31,
1446	},
1447	.hw.init = &(struct clk_init_data){
1448		.name = "mali_sel",
1449		.ops = &clk_regmap_mux_ops,
1450		.parent_hws = (const struct clk_hw *[]) {
1451			&s4_mali_0.hw,
1452			&s4_mali_1.hw,
1453		},
1454		.num_parents = 2,
1455		.flags = CLK_SET_RATE_PARENT,
1456	},
1457};
1458
1459/* VDEC clocks */
1460static const struct clk_parent_data s4_dec_parents[] = {
1461	{ .fw_name = "fclk_div2p5", },
1462	{ .fw_name = "fclk_div3", },
1463	{ .fw_name = "fclk_div4", },
1464	{ .fw_name = "fclk_div5", },
1465	{ .fw_name = "fclk_div7", },
1466	{ .fw_name = "hifi_pll", },
1467	{ .fw_name = "gp0_pll", },
1468	{ .fw_name = "xtal", }
1469};
1470
1471static struct clk_regmap s4_vdec_p0_sel = {
1472	.data = &(struct clk_regmap_mux_data){
1473		.offset = CLKCTRL_VDEC_CLK_CTRL,
1474		.mask = 0x7,
1475		.shift = 9,
1476		.flags = CLK_MUX_ROUND_CLOSEST,
1477	},
1478	.hw.init = &(struct clk_init_data) {
1479		.name = "vdec_p0_sel",
1480		.ops = &clk_regmap_mux_ops,
1481		.parent_data = s4_dec_parents,
1482		.num_parents = ARRAY_SIZE(s4_dec_parents),
1483		.flags = 0,
1484	},
1485};
1486
1487static struct clk_regmap s4_vdec_p0_div = {
1488	.data = &(struct clk_regmap_div_data){
1489		.offset = CLKCTRL_VDEC_CLK_CTRL,
1490		.shift = 0,
1491		.width = 7,
1492		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1493	},
1494	.hw.init = &(struct clk_init_data) {
1495		.name = "vdec_p0_div",
1496		.ops = &clk_regmap_divider_ops,
1497		.parent_hws = (const struct clk_hw *[]) {
1498			&s4_vdec_p0_sel.hw
1499		},
1500		.num_parents = 1,
1501		.flags = CLK_SET_RATE_PARENT,
1502	},
1503};
1504
1505static struct clk_regmap s4_vdec_p0 = {
1506	.data = &(struct clk_regmap_gate_data){
1507		.offset = CLKCTRL_VDEC_CLK_CTRL,
1508		.bit_idx = 8,
1509	},
1510	.hw.init = &(struct clk_init_data){
1511		.name = "vdec_p0",
1512		.ops = &clk_regmap_gate_ops,
1513		.parent_hws = (const struct clk_hw *[]) {
1514			&s4_vdec_p0_div.hw
1515		},
1516		.num_parents = 1,
1517		.flags = CLK_SET_RATE_PARENT,
1518	},
1519};
1520
1521static struct clk_regmap s4_vdec_p1_sel = {
1522	.data = &(struct clk_regmap_mux_data){
1523		.offset = CLKCTRL_VDEC3_CLK_CTRL,
1524		.mask = 0x7,
1525		.shift = 9,
1526		.flags = CLK_MUX_ROUND_CLOSEST,
1527	},
1528	.hw.init = &(struct clk_init_data) {
1529		.name = "vdec_p1_sel",
1530		.ops = &clk_regmap_mux_ops,
1531		.parent_data = s4_dec_parents,
1532		.num_parents = ARRAY_SIZE(s4_dec_parents),
1533		.flags = 0,
1534	},
1535};
1536
1537static struct clk_regmap s4_vdec_p1_div = {
1538	.data = &(struct clk_regmap_div_data){
1539		.offset = CLKCTRL_VDEC3_CLK_CTRL,
1540		.shift = 0,
1541		.width = 7,
1542		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1543	},
1544	.hw.init = &(struct clk_init_data) {
1545		.name = "vdec_p1_div",
1546		.ops = &clk_regmap_divider_ops,
1547		.parent_hws = (const struct clk_hw *[]) {
1548			&s4_vdec_p1_sel.hw
1549		},
1550		.num_parents = 1,
1551		.flags = CLK_SET_RATE_PARENT,
1552	},
1553};
1554
1555static struct clk_regmap s4_vdec_p1 = {
1556	.data = &(struct clk_regmap_gate_data){
1557		.offset = CLKCTRL_VDEC3_CLK_CTRL,
1558		.bit_idx = 8,
1559	},
1560	.hw.init = &(struct clk_init_data){
1561		.name = "vdec_p1",
1562		.ops = &clk_regmap_gate_ops,
1563		.parent_hws = (const struct clk_hw *[]) {
1564			&s4_vdec_p1_div.hw
1565		},
1566		.num_parents = 1,
1567		.flags = CLK_SET_RATE_PARENT,
1568	},
1569};
1570
1571static struct clk_regmap s4_vdec_sel = {
1572	.data = &(struct clk_regmap_mux_data){
1573		.offset = CLKCTRL_VDEC3_CLK_CTRL,
1574		.mask = 0x1,
1575		.shift = 15,
1576	},
1577	.hw.init = &(struct clk_init_data) {
1578		.name = "vdec_sel",
1579		.ops = &clk_regmap_mux_ops,
1580		.parent_hws = (const struct clk_hw *[]) {
1581			&s4_vdec_p0.hw,
1582			&s4_vdec_p1.hw,
1583		},
1584		.num_parents = 2,
1585		.flags = CLK_SET_RATE_PARENT,
1586	},
1587};
1588
1589static struct clk_regmap s4_hevcf_p0_sel = {
1590	.data = &(struct clk_regmap_mux_data){
1591		.offset = CLKCTRL_VDEC2_CLK_CTRL,
1592		.mask = 0x7,
1593		.shift = 9,
1594		.flags = CLK_MUX_ROUND_CLOSEST,
1595	},
1596	.hw.init = &(struct clk_init_data) {
1597		.name = "hevcf_p0_sel",
1598		.ops = &clk_regmap_mux_ops,
1599		.parent_data = s4_dec_parents,
1600		.num_parents = ARRAY_SIZE(s4_dec_parents),
1601		.flags = 0,
1602	},
1603};
1604
1605static struct clk_regmap s4_hevcf_p0_div = {
1606	.data = &(struct clk_regmap_div_data){
1607		.offset = CLKCTRL_VDEC2_CLK_CTRL,
1608		.shift = 0,
1609		.width = 7,
1610		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1611	},
1612	.hw.init = &(struct clk_init_data) {
1613		.name = "hevcf_p0_div",
1614		.ops = &clk_regmap_divider_ops,
1615		.parent_hws = (const struct clk_hw *[]) {
1616			&s4_hevcf_p0_sel.hw
1617		},
1618		.num_parents = 1,
1619		.flags = CLK_SET_RATE_PARENT,
1620	},
1621};
1622
1623static struct clk_regmap s4_hevcf_p0 = {
1624	.data = &(struct clk_regmap_gate_data){
1625		.offset = CLKCTRL_VDEC2_CLK_CTRL,
1626		.bit_idx = 8,
1627	},
1628	.hw.init = &(struct clk_init_data){
1629		.name = "hevcf_p0",
1630		.ops = &clk_regmap_gate_ops,
1631		.parent_hws = (const struct clk_hw *[]) {
1632			&s4_hevcf_p0_div.hw
1633		},
1634		.num_parents = 1,
1635		.flags = CLK_SET_RATE_PARENT,
1636	},
1637};
1638
1639static struct clk_regmap s4_hevcf_p1_sel = {
1640	.data = &(struct clk_regmap_mux_data){
1641		.offset = CLKCTRL_VDEC4_CLK_CTRL,
1642		.mask = 0x7,
1643		.shift = 9,
1644		.flags = CLK_MUX_ROUND_CLOSEST,
1645	},
1646	.hw.init = &(struct clk_init_data) {
1647		.name = "hevcf_p1_sel",
1648		.ops = &clk_regmap_mux_ops,
1649		.parent_data = s4_dec_parents,
1650		.num_parents = ARRAY_SIZE(s4_dec_parents),
1651		.flags = 0,
1652	},
1653};
1654
1655static struct clk_regmap s4_hevcf_p1_div = {
1656	.data = &(struct clk_regmap_div_data){
1657		.offset = CLKCTRL_VDEC4_CLK_CTRL,
1658		.shift = 0,
1659		.width = 7,
1660		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1661	},
1662	.hw.init = &(struct clk_init_data) {
1663		.name = "hevcf_p1_div",
1664		.ops = &clk_regmap_divider_ops,
1665		.parent_hws = (const struct clk_hw *[]) {
1666			&s4_hevcf_p1_sel.hw
1667		},
1668		.num_parents = 1,
1669		.flags = CLK_SET_RATE_PARENT,
1670	},
1671};
1672
1673static struct clk_regmap s4_hevcf_p1 = {
1674	.data = &(struct clk_regmap_gate_data){
1675		.offset = CLKCTRL_VDEC4_CLK_CTRL,
1676		.bit_idx = 8,
1677	},
1678	.hw.init = &(struct clk_init_data){
1679		.name = "hevcf_p1",
1680		.ops = &clk_regmap_gate_ops,
1681		.parent_hws = (const struct clk_hw *[]) {
1682			&s4_hevcf_p1_div.hw
1683		},
1684		.num_parents = 1,
1685		.flags = CLK_SET_RATE_PARENT,
1686	},
1687};
1688
1689static struct clk_regmap s4_hevcf_sel = {
1690	.data = &(struct clk_regmap_mux_data){
1691		.offset = CLKCTRL_VDEC4_CLK_CTRL,
1692		.mask = 0x1,
1693		.shift = 15,
1694	},
1695	.hw.init = &(struct clk_init_data) {
1696		.name = "hevcf_sel",
1697		.ops = &clk_regmap_mux_ops,
1698		.parent_hws = (const struct clk_hw *[]) {
1699			&s4_hevcf_p0.hw,
1700			&s4_hevcf_p1.hw,
1701		},
1702		.num_parents = 2,
1703		.flags = CLK_SET_RATE_PARENT,
1704	},
1705};
1706
1707/* VPU Clock */
1708static const struct clk_parent_data s4_vpu_parents[] = {
1709	{ .fw_name = "fclk_div3", },
1710	{ .fw_name = "fclk_div4", },
1711	{ .fw_name = "fclk_div5", },
1712	{ .fw_name = "fclk_div7", },
1713	{ .fw_name = "mpll1", },
1714	{ .hw = &s4_vid_pll.hw },
1715	{ .fw_name = "hifi_pll", },
1716	{ .fw_name = "gp0_pll", },
1717};
1718
1719static struct clk_regmap s4_vpu_0_sel = {
1720	.data = &(struct clk_regmap_mux_data){
1721		.offset = CLKCTRL_VPU_CLK_CTRL,
1722		.mask = 0x7,
1723		.shift = 9,
1724	},
1725	.hw.init = &(struct clk_init_data){
1726		.name = "vpu_0_sel",
1727		.ops = &clk_regmap_mux_ops,
1728		.parent_data = s4_vpu_parents,
1729		.num_parents = ARRAY_SIZE(s4_vpu_parents),
1730		.flags = 0,
1731	},
1732};
1733
1734static struct clk_regmap s4_vpu_0_div = {
1735	.data = &(struct clk_regmap_div_data){
1736		.offset = CLKCTRL_VPU_CLK_CTRL,
1737		.shift = 0,
1738		.width = 7,
1739	},
1740	.hw.init = &(struct clk_init_data){
1741		.name = "vpu_0_div",
1742		.ops = &clk_regmap_divider_ops,
1743		.parent_hws = (const struct clk_hw *[]) { &s4_vpu_0_sel.hw },
1744		.num_parents = 1,
1745		.flags = CLK_SET_RATE_PARENT,
1746	},
1747};
1748
1749static struct clk_regmap s4_vpu_0 = {
1750	.data = &(struct clk_regmap_gate_data){
1751		.offset = CLKCTRL_VPU_CLK_CTRL,
1752		.bit_idx = 8,
1753	},
1754	.hw.init = &(struct clk_init_data) {
1755		.name = "vpu_0",
1756		.ops = &clk_regmap_gate_ops,
1757		.parent_hws = (const struct clk_hw *[]) { &s4_vpu_0_div.hw },
1758		.num_parents = 1,
1759		.flags = CLK_SET_RATE_PARENT,
1760	},
1761};
1762
1763static struct clk_regmap s4_vpu_1_sel = {
1764	.data = &(struct clk_regmap_mux_data){
1765		.offset = CLKCTRL_VPU_CLK_CTRL,
1766		.mask = 0x7,
1767		.shift = 25,
1768	},
1769	.hw.init = &(struct clk_init_data){
1770		.name = "vpu_1_sel",
1771		.ops = &clk_regmap_mux_ops,
1772		.parent_data = s4_vpu_parents,
1773		.num_parents = ARRAY_SIZE(s4_vpu_parents),
1774		.flags = 0,
1775	},
1776};
1777
1778static struct clk_regmap s4_vpu_1_div = {
1779	.data = &(struct clk_regmap_div_data){
1780		.offset = CLKCTRL_VPU_CLK_CTRL,
1781		.shift = 16,
1782		.width = 7,
1783	},
1784	.hw.init = &(struct clk_init_data){
1785		.name = "vpu_1_div",
1786		.ops = &clk_regmap_divider_ops,
1787		.parent_hws = (const struct clk_hw *[]) { &s4_vpu_1_sel.hw },
1788		.num_parents = 1,
1789		.flags = CLK_SET_RATE_PARENT,
1790	},
1791};
1792
1793static struct clk_regmap s4_vpu_1 = {
1794	.data = &(struct clk_regmap_gate_data){
1795		.offset = CLKCTRL_VPU_CLK_CTRL,
1796		.bit_idx = 24,
1797	},
1798	.hw.init = &(struct clk_init_data) {
1799		.name = "vpu_1",
1800		.ops = &clk_regmap_gate_ops,
1801		.parent_hws = (const struct clk_hw *[]) { &s4_vpu_1_div.hw },
1802		.num_parents = 1,
1803		.flags = CLK_SET_RATE_PARENT,
1804	},
1805};
1806
1807static struct clk_regmap s4_vpu = {
1808	.data = &(struct clk_regmap_mux_data){
1809		.offset = CLKCTRL_VPU_CLK_CTRL,
1810		.mask = 1,
1811		.shift = 31,
1812	},
1813	.hw.init = &(struct clk_init_data){
1814		.name = "vpu",
1815		.ops = &clk_regmap_mux_ops,
1816		.parent_hws = (const struct clk_hw *[]) {
1817			&s4_vpu_0.hw,
1818			&s4_vpu_1.hw,
1819		},
1820		.num_parents = 2,
1821		.flags = CLK_SET_RATE_PARENT,
1822	},
1823};
1824
1825static const struct clk_parent_data vpu_clkb_tmp_parents[] = {
1826	{ .hw = &s4_vpu.hw },
1827	{ .fw_name = "fclk_div4", },
1828	{ .fw_name = "fclk_div5", },
1829	{ .fw_name = "fclk_div7", }
1830};
1831
1832static struct clk_regmap s4_vpu_clkb_tmp_sel = {
1833	.data = &(struct clk_regmap_mux_data){
1834		.offset = CLKCTRL_VPU_CLKB_CTRL,
1835		.mask = 0x3,
1836		.shift = 20,
1837	},
1838	.hw.init = &(struct clk_init_data) {
1839		.name = "vpu_clkb_tmp_sel",
1840		.ops = &clk_regmap_mux_ops,
1841		.parent_data = vpu_clkb_tmp_parents,
1842		.num_parents = ARRAY_SIZE(vpu_clkb_tmp_parents),
1843		.flags = CLK_SET_RATE_PARENT,
1844	},
1845};
1846
1847static struct clk_regmap s4_vpu_clkb_tmp_div = {
1848	.data = &(struct clk_regmap_div_data){
1849		.offset = CLKCTRL_VPU_CLKB_CTRL,
1850		.shift = 16,
1851		.width = 4,
1852	},
1853	.hw.init = &(struct clk_init_data) {
1854		.name = "vpu_clkb_tmp_div",
1855		.ops = &clk_regmap_divider_ops,
1856		.parent_hws = (const struct clk_hw *[]) {
1857			&s4_vpu_clkb_tmp_sel.hw
1858		},
1859		.num_parents = 1,
1860		.flags = CLK_SET_RATE_PARENT,
1861	},
1862};
1863
1864static struct clk_regmap s4_vpu_clkb_tmp = {
1865	.data = &(struct clk_regmap_gate_data){
1866		.offset = CLKCTRL_VPU_CLKB_CTRL,
1867		.bit_idx = 24,
1868	},
1869	.hw.init = &(struct clk_init_data){
1870		.name = "vpu_clkb_tmp",
1871		.ops = &clk_regmap_gate_ops,
1872		.parent_hws = (const struct clk_hw *[]) {
1873			&s4_vpu_clkb_tmp_div.hw
1874		},
1875		.num_parents = 1,
1876		.flags = CLK_SET_RATE_PARENT,
1877	},
1878};
1879
1880static struct clk_regmap s4_vpu_clkb_div = {
1881	.data = &(struct clk_regmap_div_data){
1882		.offset = CLKCTRL_VPU_CLKB_CTRL,
1883		.shift = 0,
1884		.width = 8,
1885	},
1886	.hw.init = &(struct clk_init_data) {
1887		.name = "vpu_clkb_div",
1888		.ops = &clk_regmap_divider_ops,
1889		.parent_hws = (const struct clk_hw *[]) {
1890			&s4_vpu_clkb_tmp.hw
1891		},
1892		.num_parents = 1,
1893		.flags = CLK_SET_RATE_PARENT,
1894	},
1895};
1896
1897static struct clk_regmap s4_vpu_clkb = {
1898	.data = &(struct clk_regmap_gate_data){
1899		.offset = CLKCTRL_VPU_CLKB_CTRL,
1900		.bit_idx = 8,
1901	},
1902	.hw.init = &(struct clk_init_data){
1903		.name = "vpu_clkb",
1904		.ops = &clk_regmap_gate_ops,
1905		.parent_hws = (const struct clk_hw *[]) {
1906			&s4_vpu_clkb_div.hw
1907		},
1908		.num_parents = 1,
1909		.flags = CLK_SET_RATE_PARENT,
1910	},
1911};
1912
1913static const struct clk_parent_data s4_vpu_clkc_parents[] = {
1914	{ .fw_name = "fclk_div4", },
1915	{ .fw_name = "fclk_div3", },
1916	{ .fw_name = "fclk_div5", },
1917	{ .fw_name = "fclk_div7", },
1918	{ .fw_name = "mpll1", },
1919	{ .hw = &s4_vid_pll.hw },
1920	{ .fw_name = "mpll2", },
1921	{ .fw_name = "gp0_pll", },
1922};
1923
1924static struct clk_regmap s4_vpu_clkc_p0_sel  = {
1925	.data = &(struct clk_regmap_mux_data){
1926		.offset = CLKCTRL_VPU_CLKC_CTRL,
1927		.mask = 0x7,
1928		.shift = 9,
1929	},
1930	.hw.init = &(struct clk_init_data) {
1931		.name = "vpu_clkc_p0_sel",
1932		.ops = &clk_regmap_mux_ops,
1933		.parent_data = s4_vpu_clkc_parents,
1934		.num_parents = ARRAY_SIZE(s4_vpu_clkc_parents),
1935		.flags = 0,
1936	},
1937};
1938
1939static struct clk_regmap s4_vpu_clkc_p0_div = {
1940	.data = &(struct clk_regmap_div_data){
1941		.offset = CLKCTRL_VPU_CLKC_CTRL,
1942		.shift = 0,
1943		.width = 7,
1944	},
1945	.hw.init = &(struct clk_init_data) {
1946		.name = "vpu_clkc_p0_div",
1947		.ops = &clk_regmap_divider_ops,
1948		.parent_hws = (const struct clk_hw *[]) {
1949			&s4_vpu_clkc_p0_sel.hw
1950		},
1951		.num_parents = 1,
1952		.flags = CLK_SET_RATE_PARENT,
1953	},
1954};
1955
1956static struct clk_regmap s4_vpu_clkc_p0 = {
1957	.data = &(struct clk_regmap_gate_data){
1958		.offset = CLKCTRL_VPU_CLKC_CTRL,
1959		.bit_idx = 8,
1960	},
1961	.hw.init = &(struct clk_init_data){
1962		.name = "vpu_clkc_p0",
1963		.ops = &clk_regmap_gate_ops,
1964		.parent_hws = (const struct clk_hw *[]) {
1965			&s4_vpu_clkc_p0_div.hw
1966		},
1967		.num_parents = 1,
1968		.flags = CLK_SET_RATE_PARENT,
1969	},
1970};
1971
1972static struct clk_regmap s4_vpu_clkc_p1_sel = {
1973	.data = &(struct clk_regmap_mux_data){
1974		.offset = CLKCTRL_VPU_CLKC_CTRL,
1975		.mask = 0x7,
1976		.shift = 25,
1977	},
1978	.hw.init = &(struct clk_init_data) {
1979		.name = "vpu_clkc_p1_sel",
1980		.ops = &clk_regmap_mux_ops,
1981		.parent_data = s4_vpu_clkc_parents,
1982		.num_parents = ARRAY_SIZE(s4_vpu_clkc_parents),
1983		.flags = 0,
1984	},
1985};
1986
1987static struct clk_regmap s4_vpu_clkc_p1_div = {
1988	.data = &(struct clk_regmap_div_data){
1989		.offset = CLKCTRL_VPU_CLKC_CTRL,
1990		.shift = 16,
1991		.width = 7,
1992	},
1993	.hw.init = &(struct clk_init_data) {
1994		.name = "vpu_clkc_p1_div",
1995		.ops = &clk_regmap_divider_ops,
1996		.parent_hws = (const struct clk_hw *[]) {
1997			&s4_vpu_clkc_p1_sel.hw
1998		},
1999		.num_parents = 1,
2000		.flags = CLK_SET_RATE_PARENT,
2001	},
2002};
2003
2004static struct clk_regmap s4_vpu_clkc_p1 = {
2005	.data = &(struct clk_regmap_gate_data){
2006		.offset = CLKCTRL_VPU_CLKC_CTRL,
2007		.bit_idx = 24,
2008	},
2009	.hw.init = &(struct clk_init_data){
2010		.name = "vpu_clkc_p1",
2011		.ops = &clk_regmap_gate_ops,
2012		.parent_hws = (const struct clk_hw *[]) {
2013			&s4_vpu_clkc_p1_div.hw
2014		},
2015		.num_parents = 1,
2016		.flags = CLK_SET_RATE_PARENT,
2017	},
2018};
2019
2020static struct clk_regmap s4_vpu_clkc_sel = {
2021	.data = &(struct clk_regmap_mux_data){
2022		.offset = CLKCTRL_VPU_CLKC_CTRL,
2023		.mask = 0x1,
2024		.shift = 31,
2025	},
2026	.hw.init = &(struct clk_init_data) {
2027		.name = "vpu_clkc_sel",
2028		.ops = &clk_regmap_mux_ops,
2029		.parent_hws = (const struct clk_hw *[]) {
2030			&s4_vpu_clkc_p0.hw,
2031			&s4_vpu_clkc_p1.hw,
2032		},
2033		.num_parents = 2,
2034		.flags = CLK_SET_RATE_PARENT,
2035	},
2036};
2037
2038/* VAPB Clock */
2039static const struct clk_parent_data s4_vapb_parents[] = {
2040	{ .fw_name = "fclk_div4", },
2041	{ .fw_name = "fclk_div3", },
2042	{ .fw_name = "fclk_div5", },
2043	{ .fw_name = "fclk_div7", },
2044	{ .fw_name = "mpll1", },
2045	{ .hw = &s4_vid_pll.hw },
2046	{ .fw_name = "mpll2", },
2047	{ .fw_name = "fclk_div2p5", },
2048};
2049
2050static struct clk_regmap s4_vapb_0_sel = {
2051	.data = &(struct clk_regmap_mux_data){
2052		.offset = CLKCTRL_VAPBCLK_CTRL,
2053		.mask = 0x7,
2054		.shift = 9,
2055	},
2056	.hw.init = &(struct clk_init_data){
2057		.name = "vapb_0_sel",
2058		.ops = &clk_regmap_mux_ops,
2059		.parent_data = s4_vapb_parents,
2060		.num_parents = ARRAY_SIZE(s4_vapb_parents),
2061		.flags = 0,
2062	},
2063};
2064
2065static struct clk_regmap s4_vapb_0_div = {
2066	.data = &(struct clk_regmap_div_data){
2067		.offset = CLKCTRL_VAPBCLK_CTRL,
2068		.shift = 0,
2069		.width = 7,
2070	},
2071	.hw.init = &(struct clk_init_data){
2072		.name = "vapb_0_div",
2073		.ops = &clk_regmap_divider_ops,
2074		.parent_hws = (const struct clk_hw *[]) {
2075			&s4_vapb_0_sel.hw
2076		},
2077		.num_parents = 1,
2078		.flags = CLK_SET_RATE_PARENT,
2079	},
2080};
2081
2082static struct clk_regmap s4_vapb_0 = {
2083	.data = &(struct clk_regmap_gate_data){
2084		.offset = CLKCTRL_VAPBCLK_CTRL,
2085		.bit_idx = 8,
2086	},
2087	.hw.init = &(struct clk_init_data) {
2088		.name = "vapb_0",
2089		.ops = &clk_regmap_gate_ops,
2090		.parent_hws = (const struct clk_hw *[]) {
2091			&s4_vapb_0_div.hw
2092		},
2093		.num_parents = 1,
2094		.flags = CLK_SET_RATE_PARENT,
2095	},
2096};
2097
2098static struct clk_regmap s4_vapb_1_sel = {
2099	.data = &(struct clk_regmap_mux_data){
2100		.offset = CLKCTRL_VAPBCLK_CTRL,
2101		.mask = 0x7,
2102		.shift = 25,
2103	},
2104	.hw.init = &(struct clk_init_data){
2105		.name = "vapb_1_sel",
2106		.ops = &clk_regmap_mux_ops,
2107		.parent_data = s4_vapb_parents,
2108		.num_parents = ARRAY_SIZE(s4_vapb_parents),
2109		.flags = 0,
2110	},
2111};
2112
2113static struct clk_regmap s4_vapb_1_div = {
2114	.data = &(struct clk_regmap_div_data){
2115		.offset = CLKCTRL_VAPBCLK_CTRL,
2116		.shift = 16,
2117		.width = 7,
2118	},
2119	.hw.init = &(struct clk_init_data){
2120		.name = "vapb_1_div",
2121		.ops = &clk_regmap_divider_ops,
2122		.parent_hws = (const struct clk_hw *[]) {
2123			&s4_vapb_1_sel.hw
2124		},
2125		.num_parents = 1,
2126		.flags = CLK_SET_RATE_PARENT,
2127	},
2128};
2129
2130static struct clk_regmap s4_vapb_1 = {
2131	.data = &(struct clk_regmap_gate_data){
2132		.offset = CLKCTRL_VAPBCLK_CTRL,
2133		.bit_idx = 24,
2134	},
2135	.hw.init = &(struct clk_init_data) {
2136		.name = "vapb_1",
2137		.ops = &clk_regmap_gate_ops,
2138		.parent_hws = (const struct clk_hw *[]) {
2139			&s4_vapb_1_div.hw
2140		},
2141		.num_parents = 1,
2142		.flags = CLK_SET_RATE_PARENT,
2143	},
2144};
2145
2146static struct clk_regmap s4_vapb = {
2147	.data = &(struct clk_regmap_mux_data){
2148		.offset = CLKCTRL_VAPBCLK_CTRL,
2149		.mask = 1,
2150		.shift = 31,
2151	},
2152	.hw.init = &(struct clk_init_data){
2153		.name = "vapb_sel",
2154		.ops = &clk_regmap_mux_ops,
2155		.parent_hws = (const struct clk_hw *[]) {
2156			&s4_vapb_0.hw,
2157			&s4_vapb_1.hw
2158		},
2159		.num_parents = 2,
2160		.flags = CLK_SET_RATE_PARENT,
2161	},
2162};
2163
2164static struct clk_regmap s4_ge2d = {
2165	.data = &(struct clk_regmap_gate_data){
2166		.offset = CLKCTRL_VAPBCLK_CTRL,
2167		.bit_idx = 30,
2168	},
2169	.hw.init = &(struct clk_init_data) {
2170		.name = "ge2d",
2171		.ops = &clk_regmap_gate_ops,
2172		.parent_hws = (const struct clk_hw *[]) { &s4_vapb.hw },
2173		.num_parents = 1,
2174		.flags = CLK_SET_RATE_PARENT,
2175	},
2176};
2177
2178static const struct clk_parent_data s4_hdcp22_esmclk_parents[] = {
2179	{ .fw_name = "fclk_div7", },
2180	{ .fw_name = "fclk_div4", },
2181	{ .fw_name = "fclk_div3", },
2182	{ .fw_name = "fclk_div5", },
2183};
2184
2185static struct clk_regmap s4_hdcp22_esmclk_sel = {
2186	.data = &(struct clk_regmap_mux_data){
2187		.offset = CLKCTRL_HDCP22_CTRL,
2188		.mask = 0x3,
2189		.shift = 9,
2190	},
2191	.hw.init = &(struct clk_init_data) {
2192		.name = "hdcp22_esmclk_sel",
2193		.ops = &clk_regmap_mux_ops,
2194		.parent_data = s4_hdcp22_esmclk_parents,
2195		.num_parents = ARRAY_SIZE(s4_hdcp22_esmclk_parents),
2196		.flags = CLK_SET_RATE_PARENT,
2197	},
2198};
2199
2200static struct clk_regmap s4_hdcp22_esmclk_div = {
2201	.data = &(struct clk_regmap_div_data){
2202		.offset = CLKCTRL_HDCP22_CTRL,
2203		.shift = 0,
2204		.width = 7,
2205	},
2206	.hw.init = &(struct clk_init_data) {
2207		.name = "hdcp22_esmclk_div",
2208		.ops = &clk_regmap_divider_ops,
2209		.parent_hws = (const struct clk_hw *[]) {
2210			&s4_hdcp22_esmclk_sel.hw
2211		},
2212		.num_parents = 1,
2213		.flags = CLK_SET_RATE_PARENT,
2214	},
2215};
2216
2217static struct clk_regmap s4_hdcp22_esmclk = {
2218	.data = &(struct clk_regmap_gate_data){
2219		.offset = CLKCTRL_HDCP22_CTRL,
2220		.bit_idx = 8,
2221	},
2222	.hw.init = &(struct clk_init_data){
2223		.name = "hdcp22_esmclk",
2224		.ops = &clk_regmap_gate_ops,
2225		.parent_hws = (const struct clk_hw *[]) {
2226			&s4_hdcp22_esmclk_div.hw
2227		},
2228		.num_parents = 1,
2229		.flags = CLK_SET_RATE_PARENT,
2230	},
2231};
2232
2233static const struct clk_parent_data s4_hdcp22_skpclk_parents[] = {
2234	{ .fw_name = "xtal", },
2235	{ .fw_name = "fclk_div4", },
2236	{ .fw_name = "fclk_div3", },
2237	{ .fw_name = "fclk_div5", },
2238};
2239
2240static struct clk_regmap s4_hdcp22_skpclk_sel = {
2241	.data = &(struct clk_regmap_mux_data){
2242		.offset = CLKCTRL_HDCP22_CTRL,
2243		.mask = 0x3,
2244		.shift = 25,
2245	},
2246	.hw.init = &(struct clk_init_data) {
2247		.name = "hdcp22_skpclk_sel",
2248		.ops = &clk_regmap_mux_ops,
2249		.parent_data = s4_hdcp22_skpclk_parents,
2250		.num_parents = ARRAY_SIZE(s4_hdcp22_skpclk_parents),
2251		.flags = CLK_SET_RATE_PARENT,
2252	},
2253};
2254
2255static struct clk_regmap s4_hdcp22_skpclk_div = {
2256	.data = &(struct clk_regmap_div_data){
2257		.offset = CLKCTRL_HDCP22_CTRL,
2258		.shift = 16,
2259		.width = 7,
2260	},
2261	.hw.init = &(struct clk_init_data) {
2262		.name = "hdcp22_skpclk_div",
2263		.ops = &clk_regmap_divider_ops,
2264		.parent_hws = (const struct clk_hw *[]) {
2265			&s4_hdcp22_skpclk_sel.hw
2266		},
2267		.num_parents = 1,
2268		.flags = CLK_SET_RATE_PARENT,
2269	},
2270};
2271
2272static struct clk_regmap s4_hdcp22_skpclk = {
2273	.data = &(struct clk_regmap_gate_data){
2274		.offset = CLKCTRL_HDCP22_CTRL,
2275		.bit_idx = 24,
2276	},
2277	.hw.init = &(struct clk_init_data){
2278		.name = "hdcp22_skpclk",
2279		.ops = &clk_regmap_gate_ops,
2280		.parent_hws = (const struct clk_hw *[]) {
2281			&s4_hdcp22_skpclk_div.hw
2282		},
2283		.num_parents = 1,
2284		.flags = CLK_SET_RATE_PARENT,
2285	},
2286};
2287
2288static const struct clk_parent_data s4_vdin_parents[]  = {
2289	{ .fw_name = "xtal", },
2290	{ .fw_name = "fclk_div4", },
2291	{ .fw_name = "fclk_div3", },
2292	{ .fw_name = "fclk_div5", },
2293	{ .hw = &s4_vid_pll.hw }
2294};
2295
2296static struct clk_regmap s4_vdin_meas_sel = {
2297	.data = &(struct clk_regmap_mux_data){
2298		.offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
2299		.mask = 0x7,
2300		.shift = 9,
2301	},
2302	.hw.init = &(struct clk_init_data) {
2303		.name = "vdin_meas_sel",
2304		.ops = &clk_regmap_mux_ops,
2305		.parent_data = s4_vdin_parents,
2306		.num_parents = ARRAY_SIZE(s4_vdin_parents),
2307		.flags = CLK_SET_RATE_PARENT,
2308	},
2309};
2310
2311static struct clk_regmap s4_vdin_meas_div = {
2312	.data = &(struct clk_regmap_div_data){
2313		.offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
2314		.shift = 0,
2315		.width = 7,
2316	},
2317	.hw.init = &(struct clk_init_data) {
2318		.name = "vdin_meas_div",
2319		.ops = &clk_regmap_divider_ops,
2320		.parent_hws = (const struct clk_hw *[]) {
2321			&s4_vdin_meas_sel.hw
2322		},
2323		.num_parents = 1,
2324		.flags = CLK_SET_RATE_PARENT,
2325	},
2326};
2327
2328static struct clk_regmap s4_vdin_meas = {
2329	.data = &(struct clk_regmap_gate_data){
2330		.offset = CLKCTRL_VDIN_MEAS_CLK_CTRL,
2331		.bit_idx = 8,
2332	},
2333	.hw.init = &(struct clk_init_data){
2334		.name = "vdin_meas",
2335		.ops = &clk_regmap_gate_ops,
2336		.parent_hws = (const struct clk_hw *[]) {
2337			&s4_vdin_meas_div.hw
2338		},
2339		.num_parents = 1,
2340		.flags = CLK_SET_RATE_PARENT,
2341	},
2342};
2343
2344/* EMMC/NAND clock */
2345static const struct clk_parent_data s4_sd_emmc_clk0_parents[] = {
2346	{ .fw_name = "xtal", },
2347	{ .fw_name = "fclk_div2", },
2348	{ .fw_name = "fclk_div3", },
2349	{ .fw_name = "hifi_pll", },
2350	{ .fw_name = "fclk_div2p5", },
2351	{ .fw_name = "mpll2", },
2352	{ .fw_name = "mpll3", },
2353	{ .fw_name = "gp0_pll", },
2354};
2355
2356static struct clk_regmap s4_sd_emmc_c_clk0_sel = {
2357	.data = &(struct clk_regmap_mux_data){
2358		.offset = CLKCTRL_NAND_CLK_CTRL,
2359		.mask = 0x7,
2360		.shift = 9,
2361	},
2362	.hw.init = &(struct clk_init_data) {
2363		.name = "sd_emmc_c_clk0_sel",
2364		.ops = &clk_regmap_mux_ops,
2365		.parent_data = s4_sd_emmc_clk0_parents,
2366		.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parents),
2367		.flags = 0,
2368	},
2369};
2370
2371static struct clk_regmap s4_sd_emmc_c_clk0_div = {
2372	.data = &(struct clk_regmap_div_data){
2373		.offset = CLKCTRL_NAND_CLK_CTRL,
2374		.shift = 0,
2375		.width = 7,
2376	},
2377	.hw.init = &(struct clk_init_data) {
2378		.name = "sd_emmc_c_clk0_div",
2379		.ops = &clk_regmap_divider_ops,
2380		.parent_hws = (const struct clk_hw *[]) {
2381			&s4_sd_emmc_c_clk0_sel.hw
2382		},
2383		.num_parents = 1,
2384		.flags = CLK_SET_RATE_PARENT,
2385	},
2386};
2387
2388static struct clk_regmap s4_sd_emmc_c_clk0 = {
2389	.data = &(struct clk_regmap_gate_data){
2390		.offset = CLKCTRL_NAND_CLK_CTRL,
2391		.bit_idx = 7,
2392	},
2393	.hw.init = &(struct clk_init_data){
2394		.name = "sd_emmc_c_clk0",
2395		.ops = &clk_regmap_gate_ops,
2396		.parent_hws = (const struct clk_hw *[]) {
2397			&s4_sd_emmc_c_clk0_div.hw
2398		},
2399		.num_parents = 1,
2400		.flags = CLK_SET_RATE_PARENT,
2401	},
2402};
2403
2404static struct clk_regmap s4_sd_emmc_a_clk0_sel = {
2405	.data = &(struct clk_regmap_mux_data){
2406		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
2407		.mask = 0x7,
2408		.shift = 9,
2409	},
2410	.hw.init = &(struct clk_init_data) {
2411		.name = "sd_emmc_a_clk0_sel",
2412		.ops = &clk_regmap_mux_ops,
2413		.parent_data = s4_sd_emmc_clk0_parents,
2414		.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parents),
2415		.flags = 0,
2416	},
2417};
2418
2419static struct clk_regmap s4_sd_emmc_a_clk0_div = {
2420	.data = &(struct clk_regmap_div_data){
2421		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
2422		.shift = 0,
2423		.width = 7,
2424	},
2425	.hw.init = &(struct clk_init_data) {
2426		.name = "sd_emmc_a_clk0_div",
2427		.ops = &clk_regmap_divider_ops,
2428		.parent_hws = (const struct clk_hw *[]) {
2429			&s4_sd_emmc_a_clk0_sel.hw
2430		},
2431		.num_parents = 1,
2432		.flags = CLK_SET_RATE_PARENT,
2433	},
2434};
2435
2436static struct clk_regmap s4_sd_emmc_a_clk0 = {
2437	.data = &(struct clk_regmap_gate_data){
2438		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
2439		.bit_idx = 7,
2440	},
2441	.hw.init = &(struct clk_init_data){
2442		.name = "sd_emmc_a_clk0",
2443		.ops = &clk_regmap_gate_ops,
2444		.parent_hws = (const struct clk_hw *[]) {
2445			&s4_sd_emmc_a_clk0_div.hw
2446		},
2447		.num_parents = 1,
2448		.flags = CLK_SET_RATE_PARENT,
2449	},
2450};
2451
2452static struct clk_regmap s4_sd_emmc_b_clk0_sel = {
2453	.data = &(struct clk_regmap_mux_data){
2454		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
2455		.mask = 0x7,
2456		.shift = 25,
2457	},
2458	.hw.init = &(struct clk_init_data) {
2459		.name = "sd_emmc_b_clk0_sel",
2460		.ops = &clk_regmap_mux_ops,
2461		.parent_data = s4_sd_emmc_clk0_parents,
2462		.num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parents),
2463		.flags = 0,
2464	},
2465};
2466
2467static struct clk_regmap s4_sd_emmc_b_clk0_div = {
2468	.data = &(struct clk_regmap_div_data){
2469		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
2470		.shift = 16,
2471		.width = 7,
2472	},
2473	.hw.init = &(struct clk_init_data) {
2474		.name = "sd_emmc_b_clk0_div",
2475		.ops = &clk_regmap_divider_ops,
2476		.parent_hws = (const struct clk_hw *[]) {
2477			&s4_sd_emmc_b_clk0_sel.hw
2478		},
2479		.num_parents = 1,
2480		.flags = CLK_SET_RATE_PARENT,
2481	},
2482};
2483
2484static struct clk_regmap s4_sd_emmc_b_clk0 = {
2485	.data = &(struct clk_regmap_gate_data){
2486		.offset = CLKCTRL_SD_EMMC_CLK_CTRL,
2487		.bit_idx = 23,
2488	},
2489	.hw.init = &(struct clk_init_data){
2490		.name = "sd_emmc_b_clk0",
2491		.ops = &clk_regmap_gate_ops,
2492		.parent_hws = (const struct clk_hw *[]) {
2493			&s4_sd_emmc_b_clk0_div.hw
2494		},
2495		.num_parents = 1,
2496		.flags = CLK_SET_RATE_PARENT,
2497	},
2498};
2499
2500/* SPICC Clock */
2501static const struct clk_parent_data s4_spicc_parents[] = {
2502	{ .fw_name = "xtal", },
2503	{ .hw = &s4_sys_clk.hw },
2504	{ .fw_name = "fclk_div4", },
2505	{ .fw_name = "fclk_div3", },
2506	{ .fw_name = "fclk_div2", },
2507	{ .fw_name = "fclk_div5", },
2508	{ .fw_name = "fclk_div7", },
2509};
2510
2511static struct clk_regmap s4_spicc0_sel = {
2512	.data = &(struct clk_regmap_mux_data){
2513		.offset = CLKCTRL_SPICC_CLK_CTRL,
2514		.mask = 0x7,
2515		.shift = 7,
2516	},
2517	.hw.init = &(struct clk_init_data) {
2518		.name = "spicc0_sel",
2519		.ops = &clk_regmap_mux_ops,
2520		.parent_data = s4_spicc_parents,
2521		.num_parents = ARRAY_SIZE(s4_spicc_parents),
2522		.flags = CLK_SET_RATE_PARENT,
2523	},
2524};
2525
2526static struct clk_regmap s4_spicc0_div = {
2527	.data = &(struct clk_regmap_div_data){
2528		.offset = CLKCTRL_SPICC_CLK_CTRL,
2529		.shift = 0,
2530		.width = 6,
2531	},
2532	.hw.init = &(struct clk_init_data) {
2533		.name = "spicc0_div",
2534		.ops = &clk_regmap_divider_ops,
2535		.parent_hws = (const struct clk_hw *[]) {
2536			&s4_spicc0_sel.hw
2537		},
2538		.num_parents = 1,
2539		.flags = CLK_SET_RATE_PARENT,
2540	},
2541};
2542
2543static struct clk_regmap s4_spicc0_en = {
2544	.data = &(struct clk_regmap_gate_data){
2545		.offset = CLKCTRL_SPICC_CLK_CTRL,
2546		.bit_idx = 6,
2547	},
2548	.hw.init = &(struct clk_init_data){
2549		.name = "spicc0_en",
2550		.ops = &clk_regmap_gate_ops,
2551		.parent_hws = (const struct clk_hw *[]) {
2552			&s4_spicc0_div.hw
2553		},
2554		.num_parents = 1,
2555		.flags = CLK_SET_RATE_PARENT,
2556	},
2557};
2558
2559/* PWM Clock */
2560static const struct clk_parent_data s4_pwm_parents[] = {
2561	{ .fw_name = "xtal", },
2562	{ .hw = &s4_vid_pll.hw },
2563	{ .fw_name = "fclk_div4", },
2564	{ .fw_name = "fclk_div3", },
2565};
2566
2567static S4_COMP_SEL(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 9, 0x3, s4_pwm_parents);
2568static S4_COMP_DIV(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0, 8);
2569static S4_COMP_GATE(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 8);
2570
2571static S4_COMP_SEL(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 25, 0x3, s4_pwm_parents);
2572static S4_COMP_DIV(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 16, 8);
2573static S4_COMP_GATE(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 24);
2574
2575static S4_COMP_SEL(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 9, 0x3, s4_pwm_parents);
2576static S4_COMP_DIV(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0, 8);
2577static S4_COMP_GATE(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 8);
2578
2579static S4_COMP_SEL(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 25, 0x3, s4_pwm_parents);
2580static S4_COMP_DIV(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 16, 8);
2581static S4_COMP_GATE(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 24);
2582
2583static S4_COMP_SEL(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 9, 0x3, s4_pwm_parents);
2584static S4_COMP_DIV(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0, 8);
2585static S4_COMP_GATE(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 8);
2586
2587static S4_COMP_SEL(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 25, 0x3, s4_pwm_parents);
2588static S4_COMP_DIV(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 16, 8);
2589static S4_COMP_GATE(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 24);
2590
2591static S4_COMP_SEL(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 9, 0x3, s4_pwm_parents);
2592static S4_COMP_DIV(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 0, 8);
2593static S4_COMP_GATE(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 8);
2594
2595static S4_COMP_SEL(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 25, 0x3, s4_pwm_parents);
2596static S4_COMP_DIV(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 16, 8);
2597static S4_COMP_GATE(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 24);
2598
2599static S4_COMP_SEL(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 9, 0x3, s4_pwm_parents);
2600static S4_COMP_DIV(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 0, 8);
2601static S4_COMP_GATE(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 8);
2602
2603static S4_COMP_SEL(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 25, 0x3, s4_pwm_parents);
2604static S4_COMP_DIV(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 16, 8);
2605static S4_COMP_GATE(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 24);
2606
2607static struct clk_regmap s4_saradc_sel = {
2608	.data = &(struct clk_regmap_mux_data) {
2609		.offset = CLKCTRL_SAR_CLK_CTRL,
2610		.mask = 0x3,
2611		.shift = 9,
2612	},
2613	.hw.init = &(struct clk_init_data){
2614		.name = "saradc_sel",
2615		.ops = &clk_regmap_mux_ops,
2616		.parent_data = (const struct clk_parent_data []) {
2617			{ .fw_name = "xtal", },
2618			{ .hw = &s4_sys_clk.hw },
2619		},
2620		.num_parents = 2,
2621		.flags = CLK_SET_RATE_PARENT,
2622	},
2623};
2624
2625static struct clk_regmap s4_saradc_div = {
2626	.data = &(struct clk_regmap_div_data) {
2627		.offset = CLKCTRL_SAR_CLK_CTRL,
2628		.shift = 0,
2629		.width = 8,
2630	},
2631	.hw.init = &(struct clk_init_data){
2632		.name = "saradc_div",
2633		.ops = &clk_regmap_divider_ops,
2634		.parent_hws = (const struct clk_hw *[]) {
2635			&s4_saradc_sel.hw
2636		},
2637		.num_parents = 1,
2638		.flags = CLK_SET_RATE_PARENT,
2639	},
2640};
2641
2642static struct clk_regmap s4_saradc = {
2643	.data = &(struct clk_regmap_gate_data) {
2644		.offset = CLKCTRL_SAR_CLK_CTRL,
2645		.bit_idx = 8,
2646	},
2647	.hw.init = &(struct clk_init_data){
2648		.name = "saradc",
2649		.ops = &clk_regmap_gate_ops,
2650		.parent_hws = (const struct clk_hw *[]) {
2651			&s4_saradc_div.hw
2652		},
2653		.num_parents = 1,
2654		.flags = CLK_SET_RATE_PARENT,
2655	},
2656};
2657
2658/*
2659 * gen clk is designed for debug/monitor some internal clock quality. Some of the
2660 * corresponding clock sources are not described in the clock tree and internal clock
2661 * for debug, so they are skipped.
2662 */
2663static u32 s4_gen_clk_parents_val_table[] = { 0, 4, 5, 7, 19, 21, 22, 23, 24, 25, 26, 27, 28 };
2664static const struct clk_parent_data s4_gen_clk_parents[] = {
2665	{ .fw_name = "xtal", },
2666	{ .hw = &s4_vid_pll.hw },
2667	{ .fw_name = "gp0_pll", },
2668	{ .fw_name = "hifi_pll", },
2669	{ .fw_name = "fclk_div2", },
2670	{ .fw_name = "fclk_div3", },
2671	{ .fw_name = "fclk_div4", },
2672	{ .fw_name = "fclk_div5", },
2673	{ .fw_name = "fclk_div7", },
2674	{ .fw_name = "mpll0", },
2675	{ .fw_name = "mpll1", },
2676	{ .fw_name = "mpll2", },
2677	{ .fw_name = "mpll3", },
2678};
2679
2680static struct clk_regmap s4_gen_clk_sel = {
2681	.data = &(struct clk_regmap_mux_data){
2682		.offset = CLKCTRL_GEN_CLK_CTRL,
2683		.mask = 0x1f,
2684		.shift = 12,
2685		.table = s4_gen_clk_parents_val_table,
2686	},
2687	.hw.init = &(struct clk_init_data){
2688		.name = "gen_clk_sel",
2689		.ops = &clk_regmap_mux_ops,
2690		.parent_data = s4_gen_clk_parents,
2691		.num_parents = ARRAY_SIZE(s4_gen_clk_parents),
2692		/*
2693		 *  Because the GEN clock can be connected to an external pad
2694		 *  and may be set up directly from the device tree. Don't
2695		 *  really want to automatically reparent.
2696		 */
2697		.flags = CLK_SET_RATE_NO_REPARENT,
2698	},
2699};
2700
2701static struct clk_regmap s4_gen_clk_div = {
2702	.data = &(struct clk_regmap_div_data){
2703		.offset = CLKCTRL_GEN_CLK_CTRL,
2704		.shift = 0,
2705		.width = 11,
2706	},
2707	.hw.init = &(struct clk_init_data){
2708		.name = "gen_clk_div",
2709		.ops = &clk_regmap_divider_ops,
2710		.parent_hws = (const struct clk_hw *[]) {
2711			&s4_gen_clk_sel.hw
2712		},
2713		.num_parents = 1,
2714		.flags = CLK_SET_RATE_PARENT,
2715	},
2716};
2717
2718static struct clk_regmap s4_gen_clk = {
2719	.data = &(struct clk_regmap_gate_data){
2720		.offset = CLKCTRL_GEN_CLK_CTRL,
2721		.bit_idx = 11,
2722	},
2723	.hw.init = &(struct clk_init_data) {
2724		.name = "gen_clk",
2725		.ops = &clk_regmap_gate_ops,
2726		.parent_hws = (const struct clk_hw *[]) {
2727			&s4_gen_clk_div.hw
2728		},
2729		.num_parents = 1,
2730		.flags = CLK_SET_RATE_PARENT,
2731	},
2732};
2733
2734static const struct clk_parent_data s4_pclk_parents = { .hw = &s4_sys_clk.hw };
2735
2736#define S4_PCLK(_name, _reg, _bit, _flags) \
2737	MESON_PCLK(_name, _reg, _bit, &s4_pclk_parents, _flags)
2738
2739/*
2740 * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons
2741 * Users are encouraged to test without it and submit changes to:
2742 *  - remove the flag if not necessary
2743 *  - replace the flag with something more adequate, such as CLK_IS_CRITICAL,
2744 *    if appropriate.
2745 *  - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable
2746 *    for a particular clock.
2747 */
2748static S4_PCLK(s4_ddr,		CLKCTRL_SYS_CLK_EN0_REG0,  0, CLK_IGNORE_UNUSED);
2749static S4_PCLK(s4_dos,		CLKCTRL_SYS_CLK_EN0_REG0,  1, CLK_IGNORE_UNUSED);
2750static S4_PCLK(s4_ethphy,	CLKCTRL_SYS_CLK_EN0_REG0,  4, CLK_IGNORE_UNUSED);
2751static S4_PCLK(s4_mali,		CLKCTRL_SYS_CLK_EN0_REG0,  6, CLK_IGNORE_UNUSED);
2752static S4_PCLK(s4_aocpu,	CLKCTRL_SYS_CLK_EN0_REG0, 13, CLK_IGNORE_UNUSED);
2753static S4_PCLK(s4_aucpu,	CLKCTRL_SYS_CLK_EN0_REG0, 14, CLK_IGNORE_UNUSED);
2754static S4_PCLK(s4_cec,		CLKCTRL_SYS_CLK_EN0_REG0, 16, CLK_IGNORE_UNUSED);
2755static S4_PCLK(s4_sdemmca,	CLKCTRL_SYS_CLK_EN0_REG0, 24, CLK_IGNORE_UNUSED);
2756static S4_PCLK(s4_sdemmcb,	CLKCTRL_SYS_CLK_EN0_REG0, 25, CLK_IGNORE_UNUSED);
2757static S4_PCLK(s4_nand,		CLKCTRL_SYS_CLK_EN0_REG0, 26, CLK_IGNORE_UNUSED);
2758static S4_PCLK(s4_smartcard,	CLKCTRL_SYS_CLK_EN0_REG0, 27, CLK_IGNORE_UNUSED);
2759static S4_PCLK(s4_acodec,	CLKCTRL_SYS_CLK_EN0_REG0, 28, CLK_IGNORE_UNUSED);
2760static S4_PCLK(s4_spifc,	CLKCTRL_SYS_CLK_EN0_REG0, 29, CLK_IGNORE_UNUSED);
2761static S4_PCLK(s4_msr_clk,	CLKCTRL_SYS_CLK_EN0_REG0, 30, CLK_IGNORE_UNUSED);
2762static S4_PCLK(s4_ir_ctrl,	CLKCTRL_SYS_CLK_EN0_REG0, 31, CLK_IGNORE_UNUSED);
2763
2764static S4_PCLK(s4_audio,	CLKCTRL_SYS_CLK_EN0_REG1,  0, CLK_IGNORE_UNUSED);
2765static S4_PCLK(s4_eth,		CLKCTRL_SYS_CLK_EN0_REG1,  3, CLK_IGNORE_UNUSED);
2766static S4_PCLK(s4_uart_a,	CLKCTRL_SYS_CLK_EN0_REG1,  5, CLK_IGNORE_UNUSED);
2767static S4_PCLK(s4_uart_b,	CLKCTRL_SYS_CLK_EN0_REG1,  6, CLK_IGNORE_UNUSED);
2768static S4_PCLK(s4_uart_c,	CLKCTRL_SYS_CLK_EN0_REG1,  7, CLK_IGNORE_UNUSED);
2769static S4_PCLK(s4_uart_d,	CLKCTRL_SYS_CLK_EN0_REG1,  8, CLK_IGNORE_UNUSED);
2770static S4_PCLK(s4_uart_e,	CLKCTRL_SYS_CLK_EN0_REG1,  9, CLK_IGNORE_UNUSED);
2771static S4_PCLK(s4_aififo,	CLKCTRL_SYS_CLK_EN0_REG1, 11, CLK_IGNORE_UNUSED);
2772static S4_PCLK(s4_ts_ddr,	CLKCTRL_SYS_CLK_EN0_REG1, 15, CLK_IGNORE_UNUSED);
2773static S4_PCLK(s4_ts_pll,	CLKCTRL_SYS_CLK_EN0_REG1, 16, CLK_IGNORE_UNUSED);
2774static S4_PCLK(s4_g2d,		CLKCTRL_SYS_CLK_EN0_REG1, 20, CLK_IGNORE_UNUSED);
2775static S4_PCLK(s4_spicc0,	CLKCTRL_SYS_CLK_EN0_REG1, 21, CLK_IGNORE_UNUSED);
2776static S4_PCLK(s4_usb,		CLKCTRL_SYS_CLK_EN0_REG1, 26, CLK_IGNORE_UNUSED);
2777static S4_PCLK(s4_i2c_m_a,	CLKCTRL_SYS_CLK_EN0_REG1, 30, CLK_IGNORE_UNUSED);
2778static S4_PCLK(s4_i2c_m_b,	CLKCTRL_SYS_CLK_EN0_REG1, 31, CLK_IGNORE_UNUSED);
2779
2780static S4_PCLK(s4_i2c_m_c,	CLKCTRL_SYS_CLK_EN0_REG2,  0, CLK_IGNORE_UNUSED);
2781static S4_PCLK(s4_i2c_m_d,	CLKCTRL_SYS_CLK_EN0_REG2,  1, CLK_IGNORE_UNUSED);
2782static S4_PCLK(s4_i2c_m_e,	CLKCTRL_SYS_CLK_EN0_REG2,  2, CLK_IGNORE_UNUSED);
2783static S4_PCLK(s4_hdmitx_apb,	CLKCTRL_SYS_CLK_EN0_REG2,  4, CLK_IGNORE_UNUSED);
2784static S4_PCLK(s4_i2c_s_a,	CLKCTRL_SYS_CLK_EN0_REG2,  5, CLK_IGNORE_UNUSED);
2785static S4_PCLK(s4_usb1_to_ddr,	CLKCTRL_SYS_CLK_EN0_REG2,  8, CLK_IGNORE_UNUSED);
2786static S4_PCLK(s4_hdcp22,	CLKCTRL_SYS_CLK_EN0_REG2, 10, CLK_IGNORE_UNUSED);
2787static S4_PCLK(s4_mmc_apb,	CLKCTRL_SYS_CLK_EN0_REG2, 11, CLK_IGNORE_UNUSED);
2788static S4_PCLK(s4_rsa,		CLKCTRL_SYS_CLK_EN0_REG2, 18, CLK_IGNORE_UNUSED);
2789static S4_PCLK(s4_cpu_debug,	CLKCTRL_SYS_CLK_EN0_REG2, 19, CLK_IGNORE_UNUSED);
2790static S4_PCLK(s4_vpu_intr,	CLKCTRL_SYS_CLK_EN0_REG2, 25, CLK_IGNORE_UNUSED);
2791static S4_PCLK(s4_demod,	CLKCTRL_SYS_CLK_EN0_REG2, 27, CLK_IGNORE_UNUSED);
2792static S4_PCLK(s4_sar_adc,	CLKCTRL_SYS_CLK_EN0_REG2, 28, CLK_IGNORE_UNUSED);
2793static S4_PCLK(s4_gic,		CLKCTRL_SYS_CLK_EN0_REG2, 30, CLK_IGNORE_UNUSED);
2794
2795static S4_PCLK(s4_pwm_ab,	CLKCTRL_SYS_CLK_EN0_REG3,  7, CLK_IGNORE_UNUSED);
2796static S4_PCLK(s4_pwm_cd,	CLKCTRL_SYS_CLK_EN0_REG3,  8, CLK_IGNORE_UNUSED);
2797static S4_PCLK(s4_pwm_ef,	CLKCTRL_SYS_CLK_EN0_REG3,  9, CLK_IGNORE_UNUSED);
2798static S4_PCLK(s4_pwm_gh,	CLKCTRL_SYS_CLK_EN0_REG3, 10, CLK_IGNORE_UNUSED);
2799static S4_PCLK(s4_pwm_ij,	CLKCTRL_SYS_CLK_EN0_REG3, 11, CLK_IGNORE_UNUSED);
2800
2801/* Array of all clocks provided by this provider */
2802static struct clk_hw *s4_peripherals_hw_clks[] = {
2803	[CLKID_RTC_32K_CLKIN]		= &s4_rtc_32k_by_oscin_clkin.hw,
2804	[CLKID_RTC_32K_DIV]		= &s4_rtc_32k_by_oscin_div.hw,
2805	[CLKID_RTC_32K_SEL]		= &s4_rtc_32k_by_oscin_sel.hw,
2806	[CLKID_RTC_32K_XATL]		= &s4_rtc_32k_by_oscin.hw,
2807	[CLKID_RTC]			= &s4_rtc_clk.hw,
2808	[CLKID_SYS_CLK_B_SEL]		= &s4_sysclk_b_sel.hw,
2809	[CLKID_SYS_CLK_B_DIV]		= &s4_sysclk_b_div.hw,
2810	[CLKID_SYS_CLK_B]		= &s4_sysclk_b.hw,
2811	[CLKID_SYS_CLK_A_SEL]		= &s4_sysclk_a_sel.hw,
2812	[CLKID_SYS_CLK_A_DIV]		= &s4_sysclk_a_div.hw,
2813	[CLKID_SYS_CLK_A]		= &s4_sysclk_a.hw,
2814	[CLKID_SYS]			= &s4_sys_clk.hw,
2815	[CLKID_CECA_32K_CLKIN]		= &s4_ceca_32k_clkin.hw,
2816	[CLKID_CECA_32K_DIV]		= &s4_ceca_32k_div.hw,
2817	[CLKID_CECA_32K_SEL_PRE]	= &s4_ceca_32k_sel_pre.hw,
2818	[CLKID_CECA_32K_SEL]		= &s4_ceca_32k_sel.hw,
2819	[CLKID_CECA_32K_CLKOUT]		= &s4_ceca_32k_clkout.hw,
2820	[CLKID_CECB_32K_CLKIN]		= &s4_cecb_32k_clkin.hw,
2821	[CLKID_CECB_32K_DIV]		= &s4_cecb_32k_div.hw,
2822	[CLKID_CECB_32K_SEL_PRE]	= &s4_cecb_32k_sel_pre.hw,
2823	[CLKID_CECB_32K_SEL]		= &s4_cecb_32k_sel.hw,
2824	[CLKID_CECB_32K_CLKOUT]		= &s4_cecb_32k_clkout.hw,
2825	[CLKID_SC_CLK_SEL]		= &s4_sc_clk_sel.hw,
2826	[CLKID_SC_CLK_DIV]		= &s4_sc_clk_div.hw,
2827	[CLKID_SC]			= &s4_sc_clk.hw,
2828	[CLKID_12_24M]			= &s4_12_24M.hw,
2829	[CLKID_12M_CLK_DIV]		= &s4_12M_div.hw,
2830	[CLKID_12_24M_CLK_SEL]		= &s4_12_24M_sel.hw,
2831	[CLKID_VID_PLL_DIV]		= &s4_vid_pll_div.hw,
2832	[CLKID_VID_PLL_SEL]		= &s4_vid_pll_sel.hw,
2833	[CLKID_VID_PLL]			= &s4_vid_pll.hw,
2834	[CLKID_VCLK_SEL]		= &s4_vclk_sel.hw,
2835	[CLKID_VCLK2_SEL]		= &s4_vclk2_sel.hw,
2836	[CLKID_VCLK_INPUT]		= &s4_vclk_input.hw,
2837	[CLKID_VCLK2_INPUT]		= &s4_vclk2_input.hw,
2838	[CLKID_VCLK_DIV]		= &s4_vclk_div.hw,
2839	[CLKID_VCLK2_DIV]		= &s4_vclk2_div.hw,
2840	[CLKID_VCLK]			= &s4_vclk.hw,
2841	[CLKID_VCLK2]			= &s4_vclk2.hw,
2842	[CLKID_VCLK_DIV1]		= &s4_vclk_div1.hw,
2843	[CLKID_VCLK_DIV2_EN]		= &s4_vclk_div2_en.hw,
2844	[CLKID_VCLK_DIV4_EN]		= &s4_vclk_div4_en.hw,
2845	[CLKID_VCLK_DIV6_EN]		= &s4_vclk_div6_en.hw,
2846	[CLKID_VCLK_DIV12_EN]		= &s4_vclk_div12_en.hw,
2847	[CLKID_VCLK2_DIV1]		= &s4_vclk2_div1.hw,
2848	[CLKID_VCLK2_DIV2_EN]		= &s4_vclk2_div2_en.hw,
2849	[CLKID_VCLK2_DIV4_EN]		= &s4_vclk2_div4_en.hw,
2850	[CLKID_VCLK2_DIV6_EN]		= &s4_vclk2_div6_en.hw,
2851	[CLKID_VCLK2_DIV12_EN]		= &s4_vclk2_div12_en.hw,
2852	[CLKID_VCLK_DIV2]		= &s4_vclk_div2.hw,
2853	[CLKID_VCLK_DIV4]		= &s4_vclk_div4.hw,
2854	[CLKID_VCLK_DIV6]		= &s4_vclk_div6.hw,
2855	[CLKID_VCLK_DIV12]		= &s4_vclk_div12.hw,
2856	[CLKID_VCLK2_DIV2]		= &s4_vclk2_div2.hw,
2857	[CLKID_VCLK2_DIV4]		= &s4_vclk2_div4.hw,
2858	[CLKID_VCLK2_DIV6]		= &s4_vclk2_div6.hw,
2859	[CLKID_VCLK2_DIV12]		= &s4_vclk2_div12.hw,
2860	[CLKID_CTS_ENCI_SEL]		= &s4_cts_enci_sel.hw,
2861	[CLKID_CTS_ENCP_SEL]		= &s4_cts_encp_sel.hw,
2862	[CLKID_CTS_VDAC_SEL]		= &s4_cts_vdac_sel.hw,
2863	[CLKID_HDMI_TX_SEL]		= &s4_hdmi_tx_sel.hw,
2864	[CLKID_CTS_ENCI]		= &s4_cts_enci.hw,
2865	[CLKID_CTS_ENCP]		= &s4_cts_encp.hw,
2866	[CLKID_CTS_VDAC]		= &s4_cts_vdac.hw,
2867	[CLKID_HDMI_TX]			= &s4_hdmi_tx.hw,
2868	[CLKID_HDMI_SEL]		= &s4_hdmi_sel.hw,
2869	[CLKID_HDMI_DIV]		= &s4_hdmi_div.hw,
2870	[CLKID_HDMI]			= &s4_hdmi.hw,
2871	[CLKID_TS_CLK_DIV]		= &s4_ts_clk_div.hw,
2872	[CLKID_TS]			= &s4_ts_clk.hw,
2873	[CLKID_MALI_0_SEL]		= &s4_mali_0_sel.hw,
2874	[CLKID_MALI_0_DIV]		= &s4_mali_0_div.hw,
2875	[CLKID_MALI_0]			= &s4_mali_0.hw,
2876	[CLKID_MALI_1_SEL]		= &s4_mali_1_sel.hw,
2877	[CLKID_MALI_1_DIV]		= &s4_mali_1_div.hw,
2878	[CLKID_MALI_1]			= &s4_mali_1.hw,
2879	[CLKID_MALI_SEL]		= &s4_mali_sel.hw,
2880	[CLKID_VDEC_P0_SEL]		= &s4_vdec_p0_sel.hw,
2881	[CLKID_VDEC_P0_DIV]		= &s4_vdec_p0_div.hw,
2882	[CLKID_VDEC_P0]			= &s4_vdec_p0.hw,
2883	[CLKID_VDEC_P1_SEL]		= &s4_vdec_p1_sel.hw,
2884	[CLKID_VDEC_P1_DIV]		= &s4_vdec_p1_div.hw,
2885	[CLKID_VDEC_P1]			= &s4_vdec_p1.hw,
2886	[CLKID_VDEC_SEL]		= &s4_vdec_sel.hw,
2887	[CLKID_HEVCF_P0_SEL]		= &s4_hevcf_p0_sel.hw,
2888	[CLKID_HEVCF_P0_DIV]		= &s4_hevcf_p0_div.hw,
2889	[CLKID_HEVCF_P0]		= &s4_hevcf_p0.hw,
2890	[CLKID_HEVCF_P1_SEL]		= &s4_hevcf_p1_sel.hw,
2891	[CLKID_HEVCF_P1_DIV]		= &s4_hevcf_p1_div.hw,
2892	[CLKID_HEVCF_P1]		= &s4_hevcf_p1.hw,
2893	[CLKID_HEVCF_SEL]		= &s4_hevcf_sel.hw,
2894	[CLKID_VPU_0_SEL]		= &s4_vpu_0_sel.hw,
2895	[CLKID_VPU_0_DIV]		= &s4_vpu_0_div.hw,
2896	[CLKID_VPU_0]			= &s4_vpu_0.hw,
2897	[CLKID_VPU_1_SEL]		= &s4_vpu_1_sel.hw,
2898	[CLKID_VPU_1_DIV]		= &s4_vpu_1_div.hw,
2899	[CLKID_VPU_1]			= &s4_vpu_1.hw,
2900	[CLKID_VPU]			= &s4_vpu.hw,
2901	[CLKID_VPU_CLKB_TMP_SEL]	= &s4_vpu_clkb_tmp_sel.hw,
2902	[CLKID_VPU_CLKB_TMP_DIV]	= &s4_vpu_clkb_tmp_div.hw,
2903	[CLKID_VPU_CLKB_TMP]		= &s4_vpu_clkb_tmp.hw,
2904	[CLKID_VPU_CLKB_DIV]		= &s4_vpu_clkb_div.hw,
2905	[CLKID_VPU_CLKB]		= &s4_vpu_clkb.hw,
2906	[CLKID_VPU_CLKC_P0_SEL]		= &s4_vpu_clkc_p0_sel.hw,
2907	[CLKID_VPU_CLKC_P0_DIV]		= &s4_vpu_clkc_p0_div.hw,
2908	[CLKID_VPU_CLKC_P0]		= &s4_vpu_clkc_p0.hw,
2909	[CLKID_VPU_CLKC_P1_SEL]		= &s4_vpu_clkc_p1_sel.hw,
2910	[CLKID_VPU_CLKC_P1_DIV]		= &s4_vpu_clkc_p1_div.hw,
2911	[CLKID_VPU_CLKC_P1]		= &s4_vpu_clkc_p1.hw,
2912	[CLKID_VPU_CLKC_SEL]		= &s4_vpu_clkc_sel.hw,
2913	[CLKID_VAPB_0_SEL]		= &s4_vapb_0_sel.hw,
2914	[CLKID_VAPB_0_DIV]		= &s4_vapb_0_div.hw,
2915	[CLKID_VAPB_0]			= &s4_vapb_0.hw,
2916	[CLKID_VAPB_1_SEL]		= &s4_vapb_1_sel.hw,
2917	[CLKID_VAPB_1_DIV]		= &s4_vapb_1_div.hw,
2918	[CLKID_VAPB_1]			= &s4_vapb_1.hw,
2919	[CLKID_VAPB]			= &s4_vapb.hw,
2920	[CLKID_GE2D]			= &s4_ge2d.hw,
2921	[CLKID_VDIN_MEAS_SEL]		= &s4_vdin_meas_sel.hw,
2922	[CLKID_VDIN_MEAS_DIV]		= &s4_vdin_meas_div.hw,
2923	[CLKID_VDIN_MEAS]		= &s4_vdin_meas.hw,
2924	[CLKID_SD_EMMC_C_CLK_SEL]	= &s4_sd_emmc_c_clk0_sel.hw,
2925	[CLKID_SD_EMMC_C_CLK_DIV]	= &s4_sd_emmc_c_clk0_div.hw,
2926	[CLKID_SD_EMMC_C]		= &s4_sd_emmc_c_clk0.hw,
2927	[CLKID_SD_EMMC_A_CLK_SEL]	= &s4_sd_emmc_a_clk0_sel.hw,
2928	[CLKID_SD_EMMC_A_CLK_DIV]	= &s4_sd_emmc_a_clk0_div.hw,
2929	[CLKID_SD_EMMC_A]		= &s4_sd_emmc_a_clk0.hw,
2930	[CLKID_SD_EMMC_B_CLK_SEL]	= &s4_sd_emmc_b_clk0_sel.hw,
2931	[CLKID_SD_EMMC_B_CLK_DIV]	= &s4_sd_emmc_b_clk0_div.hw,
2932	[CLKID_SD_EMMC_B]		= &s4_sd_emmc_b_clk0.hw,
2933	[CLKID_SPICC0_SEL]		= &s4_spicc0_sel.hw,
2934	[CLKID_SPICC0_DIV]		= &s4_spicc0_div.hw,
2935	[CLKID_SPICC0_EN]		= &s4_spicc0_en.hw,
2936	[CLKID_PWM_A_SEL]		= &s4_pwm_a_sel.hw,
2937	[CLKID_PWM_A_DIV]		= &s4_pwm_a_div.hw,
2938	[CLKID_PWM_A]			= &s4_pwm_a.hw,
2939	[CLKID_PWM_B_SEL]		= &s4_pwm_b_sel.hw,
2940	[CLKID_PWM_B_DIV]		= &s4_pwm_b_div.hw,
2941	[CLKID_PWM_B]			= &s4_pwm_b.hw,
2942	[CLKID_PWM_C_SEL]		= &s4_pwm_c_sel.hw,
2943	[CLKID_PWM_C_DIV]		= &s4_pwm_c_div.hw,
2944	[CLKID_PWM_C]			= &s4_pwm_c.hw,
2945	[CLKID_PWM_D_SEL]		= &s4_pwm_d_sel.hw,
2946	[CLKID_PWM_D_DIV]		= &s4_pwm_d_div.hw,
2947	[CLKID_PWM_D]			= &s4_pwm_d.hw,
2948	[CLKID_PWM_E_SEL]		= &s4_pwm_e_sel.hw,
2949	[CLKID_PWM_E_DIV]		= &s4_pwm_e_div.hw,
2950	[CLKID_PWM_E]			= &s4_pwm_e.hw,
2951	[CLKID_PWM_F_SEL]		= &s4_pwm_f_sel.hw,
2952	[CLKID_PWM_F_DIV]		= &s4_pwm_f_div.hw,
2953	[CLKID_PWM_F]			= &s4_pwm_f.hw,
2954	[CLKID_PWM_G_SEL]		= &s4_pwm_g_sel.hw,
2955	[CLKID_PWM_G_DIV]		= &s4_pwm_g_div.hw,
2956	[CLKID_PWM_G]			= &s4_pwm_g.hw,
2957	[CLKID_PWM_H_SEL]		= &s4_pwm_h_sel.hw,
2958	[CLKID_PWM_H_DIV]		= &s4_pwm_h_div.hw,
2959	[CLKID_PWM_H]			= &s4_pwm_h.hw,
2960	[CLKID_PWM_I_SEL]		= &s4_pwm_i_sel.hw,
2961	[CLKID_PWM_I_DIV]		= &s4_pwm_i_div.hw,
2962	[CLKID_PWM_I]			= &s4_pwm_i.hw,
2963	[CLKID_PWM_J_SEL]		= &s4_pwm_j_sel.hw,
2964	[CLKID_PWM_J_DIV]		= &s4_pwm_j_div.hw,
2965	[CLKID_PWM_J]			= &s4_pwm_j.hw,
2966	[CLKID_SARADC_SEL]		= &s4_saradc_sel.hw,
2967	[CLKID_SARADC_DIV]		= &s4_saradc_div.hw,
2968	[CLKID_SARADC]			= &s4_saradc.hw,
2969	[CLKID_GEN_SEL]			= &s4_gen_clk_sel.hw,
2970	[CLKID_GEN_DIV]			= &s4_gen_clk_div.hw,
2971	[CLKID_GEN]			= &s4_gen_clk.hw,
2972	[CLKID_DDR]			= &s4_ddr.hw,
2973	[CLKID_DOS]			= &s4_dos.hw,
2974	[CLKID_ETHPHY]			= &s4_ethphy.hw,
2975	[CLKID_MALI]			= &s4_mali.hw,
2976	[CLKID_AOCPU]			= &s4_aocpu.hw,
2977	[CLKID_AUCPU]			= &s4_aucpu.hw,
2978	[CLKID_CEC]			= &s4_cec.hw,
2979	[CLKID_SDEMMC_A]		= &s4_sdemmca.hw,
2980	[CLKID_SDEMMC_B]		= &s4_sdemmcb.hw,
2981	[CLKID_NAND]			= &s4_nand.hw,
2982	[CLKID_SMARTCARD]		= &s4_smartcard.hw,
2983	[CLKID_ACODEC]			= &s4_acodec.hw,
2984	[CLKID_SPIFC]			= &s4_spifc.hw,
2985	[CLKID_MSR]			= &s4_msr_clk.hw,
2986	[CLKID_IR_CTRL]			= &s4_ir_ctrl.hw,
2987	[CLKID_AUDIO]			= &s4_audio.hw,
2988	[CLKID_ETH]			= &s4_eth.hw,
2989	[CLKID_UART_A]			= &s4_uart_a.hw,
2990	[CLKID_UART_B]			= &s4_uart_b.hw,
2991	[CLKID_UART_C]			= &s4_uart_c.hw,
2992	[CLKID_UART_D]			= &s4_uart_d.hw,
2993	[CLKID_UART_E]			= &s4_uart_e.hw,
2994	[CLKID_AIFIFO]			= &s4_aififo.hw,
2995	[CLKID_TS_DDR]			= &s4_ts_ddr.hw,
2996	[CLKID_TS_PLL]			= &s4_ts_pll.hw,
2997	[CLKID_G2D]			= &s4_g2d.hw,
2998	[CLKID_SPICC0]			= &s4_spicc0.hw,
2999	[CLKID_USB]			= &s4_usb.hw,
3000	[CLKID_I2C_M_A]			= &s4_i2c_m_a.hw,
3001	[CLKID_I2C_M_B]			= &s4_i2c_m_b.hw,
3002	[CLKID_I2C_M_C]			= &s4_i2c_m_c.hw,
3003	[CLKID_I2C_M_D]			= &s4_i2c_m_d.hw,
3004	[CLKID_I2C_M_E]			= &s4_i2c_m_e.hw,
3005	[CLKID_HDMITX_APB]		= &s4_hdmitx_apb.hw,
3006	[CLKID_I2C_S_A]			= &s4_i2c_s_a.hw,
3007	[CLKID_USB1_TO_DDR]		= &s4_usb1_to_ddr.hw,
3008	[CLKID_HDCP22]			= &s4_hdcp22.hw,
3009	[CLKID_MMC_APB]			= &s4_mmc_apb.hw,
3010	[CLKID_RSA]			= &s4_rsa.hw,
3011	[CLKID_CPU_DEBUG]		= &s4_cpu_debug.hw,
3012	[CLKID_VPU_INTR]		= &s4_vpu_intr.hw,
3013	[CLKID_DEMOD]			= &s4_demod.hw,
3014	[CLKID_SAR_ADC]			= &s4_sar_adc.hw,
3015	[CLKID_GIC]			= &s4_gic.hw,
3016	[CLKID_PWM_AB]			= &s4_pwm_ab.hw,
3017	[CLKID_PWM_CD]			= &s4_pwm_cd.hw,
3018	[CLKID_PWM_EF]			= &s4_pwm_ef.hw,
3019	[CLKID_PWM_GH]			= &s4_pwm_gh.hw,
3020	[CLKID_PWM_IJ]			= &s4_pwm_ij.hw,
3021	[CLKID_HDCP22_ESMCLK_SEL]	= &s4_hdcp22_esmclk_sel.hw,
3022	[CLKID_HDCP22_ESMCLK_DIV]	= &s4_hdcp22_esmclk_div.hw,
3023	[CLKID_HDCP22_ESMCLK]		= &s4_hdcp22_esmclk.hw,
3024	[CLKID_HDCP22_SKPCLK_SEL]	= &s4_hdcp22_skpclk_sel.hw,
3025	[CLKID_HDCP22_SKPCLK_DIV]	= &s4_hdcp22_skpclk_div.hw,
3026	[CLKID_HDCP22_SKPCLK]		= &s4_hdcp22_skpclk.hw,
3027};
3028
3029static const struct meson_clkc_data s4_peripherals_clkc_data = {
3030	.hw_clks = {
3031		.hws = s4_peripherals_hw_clks,
3032		.num = ARRAY_SIZE(s4_peripherals_hw_clks),
3033	},
3034};
3035
3036static const struct of_device_id s4_peripherals_clkc_match_table[] = {
3037	{
3038		.compatible = "amlogic,s4-peripherals-clkc",
3039		.data = &s4_peripherals_clkc_data,
3040	},
3041	{}
3042};
3043MODULE_DEVICE_TABLE(of, s4_peripherals_clkc_match_table);
3044
3045static struct platform_driver s4_peripherals_clkc_driver = {
3046	.probe		= meson_clkc_mmio_probe,
3047	.driver		= {
3048		.name	= "s4-peripherals-clkc",
3049		.of_match_table = s4_peripherals_clkc_match_table,
3050	},
3051};
3052module_platform_driver(s4_peripherals_clkc_driver);
3053
3054MODULE_DESCRIPTION("Amlogic S4 Peripherals Clock Controller driver");
3055MODULE_AUTHOR("Yu Tu <yu.tu@amlogic.com>");
3056MODULE_LICENSE("GPL");
3057MODULE_IMPORT_NS("CLK_MESON");