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gxbb.c
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linux-6.19.14/drivers/clk/meson/gxbb.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2016 AmLogic, Inc. 4 * Michael Turquette <mturquette@baylibre.com> 5 */ 6 7#include <linux/clk-provider.h> 8#include <linux/init.h> 9#include <linux/mod_devicetable.h> 10#include <linux/platform_device.h> 11#include <linux/module.h> 12 13#include "clk-regmap.h" 14#include "clk-pll.h" 15#include "clk-mpll.h" 16#include "meson-clkc-utils.h" 17#include "vid-pll-div.h" 18 19#include <dt-bindings/clock/gxbb-clkc.h> 20 21#define SCR 0x2c 22#define TIMEOUT_VALUE 0x3c 23 24#define HHI_GP0_PLL_CNTL 0x40 25#define HHI_GP0_PLL_CNTL2 0x44 26#define HHI_GP0_PLL_CNTL3 0x48 27#define HHI_GP0_PLL_CNTL4 0x4c 28#define HHI_GP0_PLL_CNTL5 0x50 29#define HHI_GP0_PLL_CNTL1 0x58 30 31#define HHI_XTAL_DIVN_CNTL 0xbc 32#define HHI_TIMER90K 0xec 33 34#define HHI_MEM_PD_REG0 0x100 35#define HHI_MEM_PD_REG1 0x104 36#define HHI_VPU_MEM_PD_REG1 0x108 37#define HHI_VIID_CLK_DIV 0x128 38#define HHI_VIID_CLK_CNTL 0x12c 39 40#define HHI_GCLK_MPEG0 0x140 41#define HHI_GCLK_MPEG1 0x144 42#define HHI_GCLK_MPEG2 0x148 43#define HHI_GCLK_OTHER 0x150 44#define HHI_GCLK_AO 0x154 45#define HHI_SYS_OSCIN_CNTL 0x158 46#define HHI_SYS_CPU_CLK_CNTL1 0x15c 47#define HHI_SYS_CPU_RESET_CNTL 0x160 48#define HHI_VID_CLK_DIV 0x164 49 50#define HHI_MPEG_CLK_CNTL 0x174 51#define HHI_AUD_CLK_CNTL 0x178 52#define HHI_VID_CLK_CNTL 0x17c 53#define HHI_AUD_CLK_CNTL2 0x190 54#define HHI_VID_CLK_CNTL2 0x194 55#define HHI_SYS_CPU_CLK_CNTL0 0x19c 56#define HHI_VID_PLL_CLK_DIV 0x1a0 57#define HHI_AUD_CLK_CNTL3 0x1a4 58#define HHI_MALI_CLK_CNTL 0x1b0 59#define HHI_VPU_CLK_CNTL 0x1bc 60 61#define HHI_HDMI_CLK_CNTL 0x1cc 62#define HHI_VDEC_CLK_CNTL 0x1e0 63#define HHI_VDEC2_CLK_CNTL 0x1e4 64#define HHI_VDEC3_CLK_CNTL 0x1e8 65#define HHI_VDEC4_CLK_CNTL 0x1ec 66#define HHI_HDCP22_CLK_CNTL 0x1f0 67#define HHI_VAPBCLK_CNTL 0x1f4 68 69#define HHI_VPU_CLKB_CNTL 0x20c 70#define HHI_USB_CLK_CNTL 0x220 71#define HHI_32K_CLK_CNTL 0x224 72#define HHI_GEN_CLK_CNTL 0x228 73 74#define HHI_PCM_CLK_CNTL 0x258 75#define HHI_NAND_CLK_CNTL 0x25c 76#define HHI_SD_EMMC_CLK_CNTL 0x264 77 78#define HHI_MPLL_CNTL 0x280 79#define HHI_MPLL_CNTL2 0x284 80#define HHI_MPLL_CNTL3 0x288 81#define HHI_MPLL_CNTL4 0x28c 82#define HHI_MPLL_CNTL5 0x290 83#define HHI_MPLL_CNTL6 0x294 84#define HHI_MPLL_CNTL7 0x298 85#define HHI_MPLL_CNTL8 0x29c 86#define HHI_MPLL_CNTL9 0x2a0 87#define HHI_MPLL_CNTL10 0x2a4 88 89#define HHI_MPLL3_CNTL0 0x2e0 90#define HHI_MPLL3_CNTL1 0x2e4 91#define HHI_VDAC_CNTL0 0x2f4 92#define HHI_VDAC_CNTL1 0x2f8 93 94#define HHI_SYS_PLL_CNTL 0x300 95#define HHI_SYS_PLL_CNTL2 0x304 96#define HHI_SYS_PLL_CNTL3 0x308 97#define HHI_SYS_PLL_CNTL4 0x30c 98#define HHI_SYS_PLL_CNTL5 0x310 99#define HHI_DPLL_TOP_I 0x318 100#define HHI_DPLL_TOP2_I 0x31c 101#define HHI_HDMI_PLL_CNTL 0x320 102#define HHI_HDMI_PLL_CNTL2 0x324 103#define HHI_HDMI_PLL_CNTL3 0x328 104#define HHI_HDMI_PLL_CNTL4 0x32c 105#define HHI_HDMI_PLL_CNTL5 0x330 106#define HHI_HDMI_PLL_CNTL6 0x334 107#define HHI_HDMI_PLL_CNTL_I 0x338 108#define HHI_HDMI_PLL_CNTL7 0x33c 109 110#define HHI_HDMI_PHY_CNTL0 0x3a0 111#define HHI_HDMI_PHY_CNTL1 0x3a4 112#define HHI_HDMI_PHY_CNTL2 0x3a8 113#define HHI_HDMI_PHY_CNTL3 0x3ac 114 115#define HHI_VID_LOCK_CLK_CNTL 0x3c8 116#define HHI_BT656_CLK_CNTL 0x3d4 117#define HHI_SAR_CLK_CNTL 0x3d8 118 119static struct clk_regmap gxbb_fixed_pll_dco = { 120 .data = &(struct meson_clk_pll_data){ 121 .en = { 122 .reg_off = HHI_MPLL_CNTL, 123 .shift = 30, 124 .width = 1, 125 }, 126 .m = { 127 .reg_off = HHI_MPLL_CNTL, 128 .shift = 0, 129 .width = 9, 130 }, 131 .n = { 132 .reg_off = HHI_MPLL_CNTL, 133 .shift = 9, 134 .width = 5, 135 }, 136 .frac = { 137 .reg_off = HHI_MPLL_CNTL2, 138 .shift = 0, 139 .width = 12, 140 }, 141 .l = { 142 .reg_off = HHI_MPLL_CNTL, 143 .shift = 31, 144 .width = 1, 145 }, 146 .rst = { 147 .reg_off = HHI_MPLL_CNTL, 148 .shift = 29, 149 .width = 1, 150 }, 151 }, 152 .hw.init = &(struct clk_init_data){ 153 .name = "fixed_pll_dco", 154 .ops = &meson_clk_pll_ro_ops, 155 .parent_data = &(const struct clk_parent_data) { 156 .fw_name = "xtal", 157 }, 158 .num_parents = 1, 159 }, 160}; 161 162static struct clk_regmap gxbb_fixed_pll = { 163 .data = &(struct clk_regmap_div_data){ 164 .offset = HHI_MPLL_CNTL, 165 .shift = 16, 166 .width = 2, 167 .flags = CLK_DIVIDER_POWER_OF_TWO, 168 }, 169 .hw.init = &(struct clk_init_data){ 170 .name = "fixed_pll", 171 .ops = &clk_regmap_divider_ro_ops, 172 .parent_hws = (const struct clk_hw *[]) { 173 &gxbb_fixed_pll_dco.hw 174 }, 175 .num_parents = 1, 176 /* 177 * This clock won't ever change at runtime so 178 * CLK_SET_RATE_PARENT is not required 179 */ 180 }, 181}; 182 183static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { 184 .mult = 2, 185 .div = 1, 186 .hw.init = &(struct clk_init_data){ 187 .name = "hdmi_pll_pre_mult", 188 .ops = &clk_fixed_factor_ops, 189 .parent_data = &(const struct clk_parent_data) { 190 .fw_name = "xtal", 191 }, 192 .num_parents = 1, 193 }, 194}; 195 196static struct clk_regmap gxbb_hdmi_pll_dco = { 197 .data = &(struct meson_clk_pll_data){ 198 .en = { 199 .reg_off = HHI_HDMI_PLL_CNTL, 200 .shift = 30, 201 .width = 1, 202 }, 203 .m = { 204 .reg_off = HHI_HDMI_PLL_CNTL, 205 .shift = 0, 206 .width = 9, 207 }, 208 .n = { 209 .reg_off = HHI_HDMI_PLL_CNTL, 210 .shift = 9, 211 .width = 5, 212 }, 213 .frac = { 214 .reg_off = HHI_HDMI_PLL_CNTL2, 215 .shift = 0, 216 .width = 12, 217 }, 218 .l = { 219 .reg_off = HHI_HDMI_PLL_CNTL, 220 .shift = 31, 221 .width = 1, 222 }, 223 .rst = { 224 .reg_off = HHI_HDMI_PLL_CNTL, 225 .shift = 28, 226 .width = 1, 227 }, 228 }, 229 .hw.init = &(struct clk_init_data){ 230 .name = "hdmi_pll_dco", 231 .ops = &meson_clk_pll_ro_ops, 232 .parent_hws = (const struct clk_hw *[]) { 233 &gxbb_hdmi_pll_pre_mult.hw 234 }, 235 .num_parents = 1, 236 /* 237 * Display directly handle hdmi pll registers ATM, we need 238 * NOCACHE to keep our view of the clock as accurate as possible 239 */ 240 .flags = CLK_GET_RATE_NOCACHE, 241 }, 242}; 243 244static struct clk_regmap gxl_hdmi_pll_dco = { 245 .data = &(struct meson_clk_pll_data){ 246 .en = { 247 .reg_off = HHI_HDMI_PLL_CNTL, 248 .shift = 30, 249 .width = 1, 250 }, 251 .m = { 252 .reg_off = HHI_HDMI_PLL_CNTL, 253 .shift = 0, 254 .width = 9, 255 }, 256 .n = { 257 .reg_off = HHI_HDMI_PLL_CNTL, 258 .shift = 9, 259 .width = 5, 260 }, 261 /* 262 * On gxl, there is a register shift due to 263 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb, 264 * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB 265 * instead which is defined at the same offset. 266 */ 267 .frac = { 268 .reg_off = HHI_HDMI_PLL_CNTL2, 269 .shift = 0, 270 .width = 10, 271 }, 272 .l = { 273 .reg_off = HHI_HDMI_PLL_CNTL, 274 .shift = 31, 275 .width = 1, 276 }, 277 .rst = { 278 .reg_off = HHI_HDMI_PLL_CNTL, 279 .shift = 28, 280 .width = 1, 281 }, 282 }, 283 .hw.init = &(struct clk_init_data){ 284 .name = "hdmi_pll_dco", 285 .ops = &meson_clk_pll_ro_ops, 286 .parent_data = &(const struct clk_parent_data) { 287 .fw_name = "xtal", 288 }, 289 .num_parents = 1, 290 /* 291 * Display directly handle hdmi pll registers ATM, we need 292 * NOCACHE to keep our view of the clock as accurate as possible 293 */ 294 .flags = CLK_GET_RATE_NOCACHE, 295 }, 296}; 297 298static struct clk_regmap gxbb_hdmi_pll_od = { 299 .data = &(struct clk_regmap_div_data){ 300 .offset = HHI_HDMI_PLL_CNTL2, 301 .shift = 16, 302 .width = 2, 303 .flags = CLK_DIVIDER_POWER_OF_TWO, 304 }, 305 .hw.init = &(struct clk_init_data){ 306 .name = "hdmi_pll_od", 307 .ops = &clk_regmap_divider_ro_ops, 308 .parent_hws = (const struct clk_hw *[]) { 309 &gxbb_hdmi_pll_dco.hw 310 }, 311 .num_parents = 1, 312 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 313 }, 314}; 315 316static struct clk_regmap gxbb_hdmi_pll_od2 = { 317 .data = &(struct clk_regmap_div_data){ 318 .offset = HHI_HDMI_PLL_CNTL2, 319 .shift = 22, 320 .width = 2, 321 .flags = CLK_DIVIDER_POWER_OF_TWO, 322 }, 323 .hw.init = &(struct clk_init_data){ 324 .name = "hdmi_pll_od2", 325 .ops = &clk_regmap_divider_ro_ops, 326 .parent_hws = (const struct clk_hw *[]) { 327 &gxbb_hdmi_pll_od.hw 328 }, 329 .num_parents = 1, 330 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 331 }, 332}; 333 334static struct clk_regmap gxbb_hdmi_pll = { 335 .data = &(struct clk_regmap_div_data){ 336 .offset = HHI_HDMI_PLL_CNTL2, 337 .shift = 18, 338 .width = 2, 339 .flags = CLK_DIVIDER_POWER_OF_TWO, 340 }, 341 .hw.init = &(struct clk_init_data){ 342 .name = "hdmi_pll", 343 .ops = &clk_regmap_divider_ro_ops, 344 .parent_hws = (const struct clk_hw *[]) { 345 &gxbb_hdmi_pll_od2.hw 346 }, 347 .num_parents = 1, 348 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 349 }, 350}; 351 352/* 353 * GXL hdmi OD dividers are POWER_OF_TWO dividers but limited to /4. 354 * A divider value of 3 should map to /8 but instead map /4 so ignore it. 355 */ 356static const struct clk_div_table gxl_hdmi_pll_od_div_table[] = { 357 { .val = 0, .div = 1 }, 358 { .val = 1, .div = 2 }, 359 { .val = 2, .div = 4 }, 360 { /* sentinel */ } 361}; 362 363static struct clk_regmap gxl_hdmi_pll_od = { 364 .data = &(struct clk_regmap_div_data){ 365 .offset = HHI_HDMI_PLL_CNTL + 8, 366 .shift = 21, 367 .width = 2, 368 .table = gxl_hdmi_pll_od_div_table, 369 }, 370 .hw.init = &(struct clk_init_data){ 371 .name = "hdmi_pll_od", 372 .ops = &clk_regmap_divider_ro_ops, 373 .parent_hws = (const struct clk_hw *[]) { 374 &gxl_hdmi_pll_dco.hw 375 }, 376 .num_parents = 1, 377 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 378 }, 379}; 380 381static struct clk_regmap gxl_hdmi_pll_od2 = { 382 .data = &(struct clk_regmap_div_data){ 383 .offset = HHI_HDMI_PLL_CNTL + 8, 384 .shift = 23, 385 .width = 2, 386 .table = gxl_hdmi_pll_od_div_table, 387 }, 388 .hw.init = &(struct clk_init_data){ 389 .name = "hdmi_pll_od2", 390 .ops = &clk_regmap_divider_ro_ops, 391 .parent_hws = (const struct clk_hw *[]) { 392 &gxl_hdmi_pll_od.hw 393 }, 394 .num_parents = 1, 395 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 396 }, 397}; 398 399static struct clk_regmap gxl_hdmi_pll = { 400 .data = &(struct clk_regmap_div_data){ 401 .offset = HHI_HDMI_PLL_CNTL + 8, 402 .shift = 19, 403 .width = 2, 404 .table = gxl_hdmi_pll_od_div_table, 405 }, 406 .hw.init = &(struct clk_init_data){ 407 .name = "hdmi_pll", 408 .ops = &clk_regmap_divider_ro_ops, 409 .parent_hws = (const struct clk_hw *[]) { 410 &gxl_hdmi_pll_od2.hw 411 }, 412 .num_parents = 1, 413 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 414 }, 415}; 416 417static struct clk_regmap gxbb_sys_pll_dco = { 418 .data = &(struct meson_clk_pll_data){ 419 .en = { 420 .reg_off = HHI_SYS_PLL_CNTL, 421 .shift = 30, 422 .width = 1, 423 }, 424 .m = { 425 .reg_off = HHI_SYS_PLL_CNTL, 426 .shift = 0, 427 .width = 9, 428 }, 429 .n = { 430 .reg_off = HHI_SYS_PLL_CNTL, 431 .shift = 9, 432 .width = 5, 433 }, 434 .l = { 435 .reg_off = HHI_SYS_PLL_CNTL, 436 .shift = 31, 437 .width = 1, 438 }, 439 .rst = { 440 .reg_off = HHI_SYS_PLL_CNTL, 441 .shift = 29, 442 .width = 1, 443 }, 444 }, 445 .hw.init = &(struct clk_init_data){ 446 .name = "sys_pll_dco", 447 .ops = &meson_clk_pll_ro_ops, 448 .parent_data = &(const struct clk_parent_data) { 449 .fw_name = "xtal", 450 }, 451 .num_parents = 1, 452 }, 453}; 454 455static struct clk_regmap gxbb_sys_pll = { 456 .data = &(struct clk_regmap_div_data){ 457 .offset = HHI_SYS_PLL_CNTL, 458 .shift = 10, 459 .width = 2, 460 .flags = CLK_DIVIDER_POWER_OF_TWO, 461 }, 462 .hw.init = &(struct clk_init_data){ 463 .name = "sys_pll", 464 .ops = &clk_regmap_divider_ro_ops, 465 .parent_hws = (const struct clk_hw *[]) { 466 &gxbb_sys_pll_dco.hw 467 }, 468 .num_parents = 1, 469 .flags = CLK_SET_RATE_PARENT, 470 }, 471}; 472 473static const struct pll_params_table gxbb_gp0_pll_params_table[] = { 474 PLL_PARAMS(32, 1), 475 PLL_PARAMS(33, 1), 476 PLL_PARAMS(34, 1), 477 PLL_PARAMS(35, 1), 478 PLL_PARAMS(36, 1), 479 PLL_PARAMS(37, 1), 480 PLL_PARAMS(38, 1), 481 PLL_PARAMS(39, 1), 482 PLL_PARAMS(40, 1), 483 PLL_PARAMS(41, 1), 484 PLL_PARAMS(42, 1), 485 PLL_PARAMS(43, 1), 486 PLL_PARAMS(44, 1), 487 PLL_PARAMS(45, 1), 488 PLL_PARAMS(46, 1), 489 PLL_PARAMS(47, 1), 490 PLL_PARAMS(48, 1), 491 PLL_PARAMS(49, 1), 492 PLL_PARAMS(50, 1), 493 PLL_PARAMS(51, 1), 494 PLL_PARAMS(52, 1), 495 PLL_PARAMS(53, 1), 496 PLL_PARAMS(54, 1), 497 PLL_PARAMS(55, 1), 498 PLL_PARAMS(56, 1), 499 PLL_PARAMS(57, 1), 500 PLL_PARAMS(58, 1), 501 PLL_PARAMS(59, 1), 502 PLL_PARAMS(60, 1), 503 PLL_PARAMS(61, 1), 504 PLL_PARAMS(62, 1), 505 { /* sentinel */ }, 506}; 507 508static const struct reg_sequence gxbb_gp0_pll_init_regs[] = { 509 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, 510 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, 511 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, 512}; 513 514static struct clk_regmap gxbb_gp0_pll_dco = { 515 .data = &(struct meson_clk_pll_data){ 516 .en = { 517 .reg_off = HHI_GP0_PLL_CNTL, 518 .shift = 30, 519 .width = 1, 520 }, 521 .m = { 522 .reg_off = HHI_GP0_PLL_CNTL, 523 .shift = 0, 524 .width = 9, 525 }, 526 .n = { 527 .reg_off = HHI_GP0_PLL_CNTL, 528 .shift = 9, 529 .width = 5, 530 }, 531 .l = { 532 .reg_off = HHI_GP0_PLL_CNTL, 533 .shift = 31, 534 .width = 1, 535 }, 536 .rst = { 537 .reg_off = HHI_GP0_PLL_CNTL, 538 .shift = 29, 539 .width = 1, 540 }, 541 .table = gxbb_gp0_pll_params_table, 542 .init_regs = gxbb_gp0_pll_init_regs, 543 .init_count = ARRAY_SIZE(gxbb_gp0_pll_init_regs), 544 }, 545 .hw.init = &(struct clk_init_data){ 546 .name = "gp0_pll_dco", 547 .ops = &meson_clk_pll_ops, 548 .parent_data = &(const struct clk_parent_data) { 549 .fw_name = "xtal", 550 }, 551 .num_parents = 1, 552 }, 553}; 554 555static const struct pll_params_table gxl_gp0_pll_params_table[] = { 556 PLL_PARAMS(42, 1), 557 PLL_PARAMS(43, 1), 558 PLL_PARAMS(44, 1), 559 PLL_PARAMS(45, 1), 560 PLL_PARAMS(46, 1), 561 PLL_PARAMS(47, 1), 562 PLL_PARAMS(48, 1), 563 PLL_PARAMS(49, 1), 564 PLL_PARAMS(50, 1), 565 PLL_PARAMS(51, 1), 566 PLL_PARAMS(52, 1), 567 PLL_PARAMS(53, 1), 568 PLL_PARAMS(54, 1), 569 PLL_PARAMS(55, 1), 570 PLL_PARAMS(56, 1), 571 PLL_PARAMS(57, 1), 572 PLL_PARAMS(58, 1), 573 PLL_PARAMS(59, 1), 574 PLL_PARAMS(60, 1), 575 PLL_PARAMS(61, 1), 576 PLL_PARAMS(62, 1), 577 PLL_PARAMS(63, 1), 578 PLL_PARAMS(64, 1), 579 PLL_PARAMS(65, 1), 580 PLL_PARAMS(66, 1), 581 { /* sentinel */ }, 582}; 583 584static const struct reg_sequence gxl_gp0_pll_init_regs[] = { 585 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 586 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 587 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 588 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 589 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 590}; 591 592static struct clk_regmap gxl_gp0_pll_dco = { 593 .data = &(struct meson_clk_pll_data){ 594 .en = { 595 .reg_off = HHI_GP0_PLL_CNTL, 596 .shift = 30, 597 .width = 1, 598 }, 599 .m = { 600 .reg_off = HHI_GP0_PLL_CNTL, 601 .shift = 0, 602 .width = 9, 603 }, 604 .n = { 605 .reg_off = HHI_GP0_PLL_CNTL, 606 .shift = 9, 607 .width = 5, 608 }, 609 .frac = { 610 .reg_off = HHI_GP0_PLL_CNTL1, 611 .shift = 0, 612 .width = 10, 613 }, 614 .l = { 615 .reg_off = HHI_GP0_PLL_CNTL, 616 .shift = 31, 617 .width = 1, 618 }, 619 .rst = { 620 .reg_off = HHI_GP0_PLL_CNTL, 621 .shift = 29, 622 .width = 1, 623 }, 624 .table = gxl_gp0_pll_params_table, 625 .init_regs = gxl_gp0_pll_init_regs, 626 .init_count = ARRAY_SIZE(gxl_gp0_pll_init_regs), 627 }, 628 .hw.init = &(struct clk_init_data){ 629 .name = "gp0_pll_dco", 630 .ops = &meson_clk_pll_ops, 631 .parent_data = &(const struct clk_parent_data) { 632 .fw_name = "xtal", 633 }, 634 .num_parents = 1, 635 }, 636}; 637 638static struct clk_regmap gxbb_gp0_pll = { 639 .data = &(struct clk_regmap_div_data){ 640 .offset = HHI_GP0_PLL_CNTL, 641 .shift = 16, 642 .width = 2, 643 .flags = CLK_DIVIDER_POWER_OF_TWO, 644 }, 645 .hw.init = &(struct clk_init_data){ 646 .name = "gp0_pll", 647 .ops = &clk_regmap_divider_ops, 648 .parent_data = &(const struct clk_parent_data) { 649 /* 650 * Note: 651 * GXL and GXBB have different gp0_pll_dco (with 652 * different struct clk_hw). We fallback to the global 653 * naming string mechanism so gp0_pll picks up the 654 * appropriate one. 655 */ 656 .name = "gp0_pll_dco", 657 .index = -1, 658 }, 659 .num_parents = 1, 660 .flags = CLK_SET_RATE_PARENT, 661 }, 662}; 663 664static struct clk_fixed_factor gxbb_fclk_div2_div = { 665 .mult = 1, 666 .div = 2, 667 .hw.init = &(struct clk_init_data){ 668 .name = "fclk_div2_div", 669 .ops = &clk_fixed_factor_ops, 670 .parent_hws = (const struct clk_hw *[]) { 671 &gxbb_fixed_pll.hw 672 }, 673 .num_parents = 1, 674 }, 675}; 676 677static struct clk_regmap gxbb_fclk_div2 = { 678 .data = &(struct clk_regmap_gate_data){ 679 .offset = HHI_MPLL_CNTL6, 680 .bit_idx = 27, 681 }, 682 .hw.init = &(struct clk_init_data){ 683 .name = "fclk_div2", 684 .ops = &clk_regmap_gate_ops, 685 .parent_hws = (const struct clk_hw *[]) { 686 &gxbb_fclk_div2_div.hw 687 }, 688 .num_parents = 1, 689 .flags = CLK_IS_CRITICAL, 690 }, 691}; 692 693static struct clk_fixed_factor gxbb_fclk_div3_div = { 694 .mult = 1, 695 .div = 3, 696 .hw.init = &(struct clk_init_data){ 697 .name = "fclk_div3_div", 698 .ops = &clk_fixed_factor_ops, 699 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 700 .num_parents = 1, 701 }, 702}; 703 704static struct clk_regmap gxbb_fclk_div3 = { 705 .data = &(struct clk_regmap_gate_data){ 706 .offset = HHI_MPLL_CNTL6, 707 .bit_idx = 28, 708 }, 709 .hw.init = &(struct clk_init_data){ 710 .name = "fclk_div3", 711 .ops = &clk_regmap_gate_ops, 712 .parent_hws = (const struct clk_hw *[]) { 713 &gxbb_fclk_div3_div.hw 714 }, 715 .num_parents = 1, 716 /* 717 * FIXME: 718 * This clock, as fdiv2, is used by the SCPI FW and is required 719 * by the platform to operate correctly. 720 * Until the following condition are met, we need this clock to 721 * be marked as critical: 722 * a) The SCPI generic driver claims and enable all the clocks 723 * it needs 724 * b) CCF has a clock hand-off mechanism to make the sure the 725 * clock stays on until the proper driver comes along 726 */ 727 .flags = CLK_IS_CRITICAL, 728 }, 729}; 730 731static struct clk_fixed_factor gxbb_fclk_div4_div = { 732 .mult = 1, 733 .div = 4, 734 .hw.init = &(struct clk_init_data){ 735 .name = "fclk_div4_div", 736 .ops = &clk_fixed_factor_ops, 737 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 738 .num_parents = 1, 739 }, 740}; 741 742static struct clk_regmap gxbb_fclk_div4 = { 743 .data = &(struct clk_regmap_gate_data){ 744 .offset = HHI_MPLL_CNTL6, 745 .bit_idx = 29, 746 }, 747 .hw.init = &(struct clk_init_data){ 748 .name = "fclk_div4", 749 .ops = &clk_regmap_gate_ops, 750 .parent_hws = (const struct clk_hw *[]) { 751 &gxbb_fclk_div4_div.hw 752 }, 753 .num_parents = 1, 754 }, 755}; 756 757static struct clk_fixed_factor gxbb_fclk_div5_div = { 758 .mult = 1, 759 .div = 5, 760 .hw.init = &(struct clk_init_data){ 761 .name = "fclk_div5_div", 762 .ops = &clk_fixed_factor_ops, 763 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 764 .num_parents = 1, 765 }, 766}; 767 768static struct clk_regmap gxbb_fclk_div5 = { 769 .data = &(struct clk_regmap_gate_data){ 770 .offset = HHI_MPLL_CNTL6, 771 .bit_idx = 30, 772 }, 773 .hw.init = &(struct clk_init_data){ 774 .name = "fclk_div5", 775 .ops = &clk_regmap_gate_ops, 776 .parent_hws = (const struct clk_hw *[]) { 777 &gxbb_fclk_div5_div.hw 778 }, 779 .num_parents = 1, 780 }, 781}; 782 783static struct clk_fixed_factor gxbb_fclk_div7_div = { 784 .mult = 1, 785 .div = 7, 786 .hw.init = &(struct clk_init_data){ 787 .name = "fclk_div7_div", 788 .ops = &clk_fixed_factor_ops, 789 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 790 .num_parents = 1, 791 }, 792}; 793 794static struct clk_regmap gxbb_fclk_div7 = { 795 .data = &(struct clk_regmap_gate_data){ 796 .offset = HHI_MPLL_CNTL6, 797 .bit_idx = 31, 798 }, 799 .hw.init = &(struct clk_init_data){ 800 .name = "fclk_div7", 801 .ops = &clk_regmap_gate_ops, 802 .parent_hws = (const struct clk_hw *[]) { 803 &gxbb_fclk_div7_div.hw 804 }, 805 .num_parents = 1, 806 }, 807}; 808 809static struct clk_regmap gxbb_mpll_prediv = { 810 .data = &(struct clk_regmap_div_data){ 811 .offset = HHI_MPLL_CNTL5, 812 .shift = 12, 813 .width = 1, 814 }, 815 .hw.init = &(struct clk_init_data){ 816 .name = "mpll_prediv", 817 .ops = &clk_regmap_divider_ro_ops, 818 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 819 .num_parents = 1, 820 }, 821}; 822 823static struct clk_regmap gxbb_mpll0_div = { 824 .data = &(struct meson_clk_mpll_data){ 825 .sdm = { 826 .reg_off = HHI_MPLL_CNTL7, 827 .shift = 0, 828 .width = 14, 829 }, 830 .sdm_en = { 831 .reg_off = HHI_MPLL_CNTL, 832 .shift = 25, 833 .width = 1, 834 }, 835 .n2 = { 836 .reg_off = HHI_MPLL_CNTL7, 837 .shift = 16, 838 .width = 9, 839 }, 840 }, 841 .hw.init = &(struct clk_init_data){ 842 .name = "mpll0_div", 843 .ops = &meson_clk_mpll_ops, 844 .parent_hws = (const struct clk_hw *[]) { 845 &gxbb_mpll_prediv.hw 846 }, 847 .num_parents = 1, 848 }, 849}; 850 851static struct clk_regmap gxl_mpll0_div = { 852 .data = &(struct meson_clk_mpll_data){ 853 .sdm = { 854 .reg_off = HHI_MPLL_CNTL7, 855 .shift = 0, 856 .width = 14, 857 }, 858 .sdm_en = { 859 .reg_off = HHI_MPLL_CNTL7, 860 .shift = 15, 861 .width = 1, 862 }, 863 .n2 = { 864 .reg_off = HHI_MPLL_CNTL7, 865 .shift = 16, 866 .width = 9, 867 }, 868 }, 869 .hw.init = &(struct clk_init_data){ 870 .name = "mpll0_div", 871 .ops = &meson_clk_mpll_ops, 872 .parent_hws = (const struct clk_hw *[]) { 873 &gxbb_mpll_prediv.hw 874 }, 875 .num_parents = 1, 876 }, 877}; 878 879static struct clk_regmap gxbb_mpll0 = { 880 .data = &(struct clk_regmap_gate_data){ 881 .offset = HHI_MPLL_CNTL7, 882 .bit_idx = 14, 883 }, 884 .hw.init = &(struct clk_init_data){ 885 .name = "mpll0", 886 .ops = &clk_regmap_gate_ops, 887 .parent_data = &(const struct clk_parent_data) { 888 /* 889 * Note: 890 * GXL and GXBB have different SDM_EN registers. We 891 * fallback to the global naming string mechanism so 892 * mpll0_div picks up the appropriate one. 893 */ 894 .name = "mpll0_div", 895 .index = -1, 896 }, 897 .num_parents = 1, 898 .flags = CLK_SET_RATE_PARENT, 899 }, 900}; 901 902static struct clk_regmap gxbb_mpll1_div = { 903 .data = &(struct meson_clk_mpll_data){ 904 .sdm = { 905 .reg_off = HHI_MPLL_CNTL8, 906 .shift = 0, 907 .width = 14, 908 }, 909 .sdm_en = { 910 .reg_off = HHI_MPLL_CNTL8, 911 .shift = 15, 912 .width = 1, 913 }, 914 .n2 = { 915 .reg_off = HHI_MPLL_CNTL8, 916 .shift = 16, 917 .width = 9, 918 }, 919 }, 920 .hw.init = &(struct clk_init_data){ 921 .name = "mpll1_div", 922 .ops = &meson_clk_mpll_ops, 923 .parent_hws = (const struct clk_hw *[]) { 924 &gxbb_mpll_prediv.hw 925 }, 926 .num_parents = 1, 927 }, 928}; 929 930static struct clk_regmap gxbb_mpll1 = { 931 .data = &(struct clk_regmap_gate_data){ 932 .offset = HHI_MPLL_CNTL8, 933 .bit_idx = 14, 934 }, 935 .hw.init = &(struct clk_init_data){ 936 .name = "mpll1", 937 .ops = &clk_regmap_gate_ops, 938 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw }, 939 .num_parents = 1, 940 .flags = CLK_SET_RATE_PARENT, 941 }, 942}; 943 944static struct clk_regmap gxbb_mpll2_div = { 945 .data = &(struct meson_clk_mpll_data){ 946 .sdm = { 947 .reg_off = HHI_MPLL_CNTL9, 948 .shift = 0, 949 .width = 14, 950 }, 951 .sdm_en = { 952 .reg_off = HHI_MPLL_CNTL9, 953 .shift = 15, 954 .width = 1, 955 }, 956 .n2 = { 957 .reg_off = HHI_MPLL_CNTL9, 958 .shift = 16, 959 .width = 9, 960 }, 961 }, 962 .hw.init = &(struct clk_init_data){ 963 .name = "mpll2_div", 964 .ops = &meson_clk_mpll_ops, 965 .parent_hws = (const struct clk_hw *[]) { 966 &gxbb_mpll_prediv.hw 967 }, 968 .num_parents = 1, 969 }, 970}; 971 972static struct clk_regmap gxbb_mpll2 = { 973 .data = &(struct clk_regmap_gate_data){ 974 .offset = HHI_MPLL_CNTL9, 975 .bit_idx = 14, 976 }, 977 .hw.init = &(struct clk_init_data){ 978 .name = "mpll2", 979 .ops = &clk_regmap_gate_ops, 980 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw }, 981 .num_parents = 1, 982 .flags = CLK_SET_RATE_PARENT, 983 }, 984}; 985 986/* clk81 is often referred as "mpeg_clk" */ 987static u32 clk81_parents_val_table[] = { 0, 2, 3, 4, 5, 6, 7 }; 988static const struct clk_parent_data clk81_parents[] = { 989 { .fw_name = "xtal", }, 990 { .hw = &gxbb_fclk_div7.hw }, 991 { .hw = &gxbb_mpll1.hw }, 992 { .hw = &gxbb_mpll2.hw }, 993 { .hw = &gxbb_fclk_div4.hw }, 994 { .hw = &gxbb_fclk_div3.hw }, 995 { .hw = &gxbb_fclk_div5.hw }, 996}; 997 998static struct clk_regmap gxbb_clk81_sel = { 999 .data = &(struct clk_regmap_mux_data){ 1000 .offset = HHI_MPEG_CLK_CNTL, 1001 .mask = 0x7, 1002 .shift = 12, 1003 .table = clk81_parents_val_table, 1004 }, 1005 .hw.init = &(struct clk_init_data){ 1006 .name = "clk81_sel", 1007 .ops = &clk_regmap_mux_ro_ops, 1008 /* 1009 * bits 14:12 selects from 8 possible parents: 1010 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 1011 * fclk_div4, fclk_div3, fclk_div5 1012 */ 1013 .parent_data = clk81_parents, 1014 .num_parents = ARRAY_SIZE(clk81_parents), 1015 }, 1016}; 1017 1018static struct clk_regmap gxbb_clk81_div = { 1019 .data = &(struct clk_regmap_div_data){ 1020 .offset = HHI_MPEG_CLK_CNTL, 1021 .shift = 0, 1022 .width = 7, 1023 }, 1024 .hw.init = &(struct clk_init_data){ 1025 .name = "clk81_div", 1026 .ops = &clk_regmap_divider_ro_ops, 1027 .parent_hws = (const struct clk_hw *[]) { 1028 &gxbb_clk81_sel.hw 1029 }, 1030 .num_parents = 1, 1031 }, 1032}; 1033 1034/* the mother of dragons gates */ 1035static struct clk_regmap gxbb_clk81 = { 1036 .data = &(struct clk_regmap_gate_data){ 1037 .offset = HHI_MPEG_CLK_CNTL, 1038 .bit_idx = 7, 1039 }, 1040 .hw.init = &(struct clk_init_data){ 1041 .name = "clk81", 1042 .ops = &clk_regmap_gate_ops, 1043 .parent_hws = (const struct clk_hw *[]) { 1044 &gxbb_clk81_div.hw 1045 }, 1046 .num_parents = 1, 1047 .flags = CLK_IS_CRITICAL, 1048 }, 1049}; 1050 1051static struct clk_regmap gxbb_sar_adc_clk_sel = { 1052 .data = &(struct clk_regmap_mux_data){ 1053 .offset = HHI_SAR_CLK_CNTL, 1054 .mask = 0x3, 1055 .shift = 9, 1056 }, 1057 .hw.init = &(struct clk_init_data){ 1058 .name = "sar_adc_clk_sel", 1059 .ops = &clk_regmap_mux_ops, 1060 /* NOTE: The datasheet doesn't list the parents for bit 10 */ 1061 .parent_data = (const struct clk_parent_data []) { 1062 { .fw_name = "xtal", }, 1063 { .hw = &gxbb_clk81.hw }, 1064 }, 1065 .num_parents = 2, 1066 }, 1067}; 1068 1069static struct clk_regmap gxbb_sar_adc_clk_div = { 1070 .data = &(struct clk_regmap_div_data){ 1071 .offset = HHI_SAR_CLK_CNTL, 1072 .shift = 0, 1073 .width = 8, 1074 }, 1075 .hw.init = &(struct clk_init_data){ 1076 .name = "sar_adc_clk_div", 1077 .ops = &clk_regmap_divider_ops, 1078 .parent_hws = (const struct clk_hw *[]) { 1079 &gxbb_sar_adc_clk_sel.hw 1080 }, 1081 .num_parents = 1, 1082 .flags = CLK_SET_RATE_PARENT, 1083 }, 1084}; 1085 1086static struct clk_regmap gxbb_sar_adc_clk = { 1087 .data = &(struct clk_regmap_gate_data){ 1088 .offset = HHI_SAR_CLK_CNTL, 1089 .bit_idx = 8, 1090 }, 1091 .hw.init = &(struct clk_init_data){ 1092 .name = "sar_adc_clk", 1093 .ops = &clk_regmap_gate_ops, 1094 .parent_hws = (const struct clk_hw *[]) { 1095 &gxbb_sar_adc_clk_div.hw 1096 }, 1097 .num_parents = 1, 1098 .flags = CLK_SET_RATE_PARENT, 1099 }, 1100}; 1101 1102/* 1103 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 1104 * muxed by a glitch-free switch. The CCF can manage this glitch-free 1105 * mux because it does top-to-bottom updates the each clock tree and 1106 * switches to the "inactive" one when CLK_SET_RATE_GATE is set. 1107 */ 1108 1109static const struct clk_parent_data gxbb_mali_parents[] = { 1110 { .fw_name = "xtal", }, 1111 { .hw = &gxbb_gp0_pll.hw }, 1112 { .hw = &gxbb_mpll2.hw }, 1113 { .hw = &gxbb_mpll1.hw }, 1114 { .hw = &gxbb_fclk_div7.hw }, 1115 { .hw = &gxbb_fclk_div4.hw }, 1116 { .hw = &gxbb_fclk_div3.hw }, 1117 { .hw = &gxbb_fclk_div5.hw }, 1118}; 1119 1120static struct clk_regmap gxbb_mali_0_sel = { 1121 .data = &(struct clk_regmap_mux_data){ 1122 .offset = HHI_MALI_CLK_CNTL, 1123 .mask = 0x7, 1124 .shift = 9, 1125 }, 1126 .hw.init = &(struct clk_init_data){ 1127 .name = "mali_0_sel", 1128 .ops = &clk_regmap_mux_ops, 1129 .parent_data = gxbb_mali_parents, 1130 .num_parents = ARRAY_SIZE(gxbb_mali_parents), 1131 /* 1132 * Don't request the parent to change the rate because 1133 * all GPU frequencies can be derived from the fclk_* 1134 * clocks and one special GP0_PLL setting. This is 1135 * important because we need the MPLL clocks for audio. 1136 */ 1137 .flags = 0, 1138 }, 1139}; 1140 1141static struct clk_regmap gxbb_mali_0_div = { 1142 .data = &(struct clk_regmap_div_data){ 1143 .offset = HHI_MALI_CLK_CNTL, 1144 .shift = 0, 1145 .width = 7, 1146 }, 1147 .hw.init = &(struct clk_init_data){ 1148 .name = "mali_0_div", 1149 .ops = &clk_regmap_divider_ops, 1150 .parent_hws = (const struct clk_hw *[]) { 1151 &gxbb_mali_0_sel.hw 1152 }, 1153 .num_parents = 1, 1154 .flags = CLK_SET_RATE_PARENT, 1155 }, 1156}; 1157 1158static struct clk_regmap gxbb_mali_0 = { 1159 .data = &(struct clk_regmap_gate_data){ 1160 .offset = HHI_MALI_CLK_CNTL, 1161 .bit_idx = 8, 1162 }, 1163 .hw.init = &(struct clk_init_data){ 1164 .name = "mali_0", 1165 .ops = &clk_regmap_gate_ops, 1166 .parent_hws = (const struct clk_hw *[]) { 1167 &gxbb_mali_0_div.hw 1168 }, 1169 .num_parents = 1, 1170 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1171 }, 1172}; 1173 1174static struct clk_regmap gxbb_mali_1_sel = { 1175 .data = &(struct clk_regmap_mux_data){ 1176 .offset = HHI_MALI_CLK_CNTL, 1177 .mask = 0x7, 1178 .shift = 25, 1179 }, 1180 .hw.init = &(struct clk_init_data){ 1181 .name = "mali_1_sel", 1182 .ops = &clk_regmap_mux_ops, 1183 .parent_data = gxbb_mali_parents, 1184 .num_parents = ARRAY_SIZE(gxbb_mali_parents), 1185 /* 1186 * Don't request the parent to change the rate because 1187 * all GPU frequencies can be derived from the fclk_* 1188 * clocks and one special GP0_PLL setting. This is 1189 * important because we need the MPLL clocks for audio. 1190 */ 1191 .flags = 0, 1192 }, 1193}; 1194 1195static struct clk_regmap gxbb_mali_1_div = { 1196 .data = &(struct clk_regmap_div_data){ 1197 .offset = HHI_MALI_CLK_CNTL, 1198 .shift = 16, 1199 .width = 7, 1200 }, 1201 .hw.init = &(struct clk_init_data){ 1202 .name = "mali_1_div", 1203 .ops = &clk_regmap_divider_ops, 1204 .parent_hws = (const struct clk_hw *[]) { 1205 &gxbb_mali_1_sel.hw 1206 }, 1207 .num_parents = 1, 1208 .flags = CLK_SET_RATE_PARENT, 1209 }, 1210}; 1211 1212static struct clk_regmap gxbb_mali_1 = { 1213 .data = &(struct clk_regmap_gate_data){ 1214 .offset = HHI_MALI_CLK_CNTL, 1215 .bit_idx = 24, 1216 }, 1217 .hw.init = &(struct clk_init_data){ 1218 .name = "mali_1", 1219 .ops = &clk_regmap_gate_ops, 1220 .parent_hws = (const struct clk_hw *[]) { 1221 &gxbb_mali_1_div.hw 1222 }, 1223 .num_parents = 1, 1224 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1225 }, 1226}; 1227 1228static struct clk_regmap gxbb_mali = { 1229 .data = &(struct clk_regmap_mux_data){ 1230 .offset = HHI_MALI_CLK_CNTL, 1231 .mask = 1, 1232 .shift = 31, 1233 }, 1234 .hw.init = &(struct clk_init_data){ 1235 .name = "mali", 1236 .ops = &clk_regmap_mux_ops, 1237 .parent_hws = (const struct clk_hw *[]) { 1238 &gxbb_mali_0.hw, 1239 &gxbb_mali_1.hw, 1240 }, 1241 .num_parents = 2, 1242 .flags = CLK_SET_RATE_PARENT, 1243 }, 1244}; 1245 1246static u32 gxbb_cts_mclk_parents_val_table[] = { 1, 2, 3 }; 1247static const struct clk_hw *gxbb_cts_mclk_parents[] = { 1248 &gxbb_mpll0.hw, 1249 &gxbb_mpll1.hw, 1250 &gxbb_mpll2.hw, 1251}; 1252 1253static struct clk_regmap gxbb_cts_amclk_sel = { 1254 .data = &(struct clk_regmap_mux_data){ 1255 .offset = HHI_AUD_CLK_CNTL, 1256 .mask = 0x3, 1257 .shift = 9, 1258 .table = gxbb_cts_mclk_parents_val_table, 1259 .flags = CLK_MUX_ROUND_CLOSEST, 1260 }, 1261 .hw.init = &(struct clk_init_data){ 1262 .name = "cts_amclk_sel", 1263 .ops = &clk_regmap_mux_ops, 1264 .parent_hws = gxbb_cts_mclk_parents, 1265 .num_parents = ARRAY_SIZE(gxbb_cts_mclk_parents), 1266 }, 1267}; 1268 1269static struct clk_regmap gxbb_cts_amclk_div = { 1270 .data = &(struct clk_regmap_div_data) { 1271 .offset = HHI_AUD_CLK_CNTL, 1272 .shift = 0, 1273 .width = 8, 1274 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1275 }, 1276 .hw.init = &(struct clk_init_data){ 1277 .name = "cts_amclk_div", 1278 .ops = &clk_regmap_divider_ops, 1279 .parent_hws = (const struct clk_hw *[]) { 1280 &gxbb_cts_amclk_sel.hw 1281 }, 1282 .num_parents = 1, 1283 .flags = CLK_SET_RATE_PARENT, 1284 }, 1285}; 1286 1287static struct clk_regmap gxbb_cts_amclk = { 1288 .data = &(struct clk_regmap_gate_data){ 1289 .offset = HHI_AUD_CLK_CNTL, 1290 .bit_idx = 8, 1291 }, 1292 .hw.init = &(struct clk_init_data){ 1293 .name = "cts_amclk", 1294 .ops = &clk_regmap_gate_ops, 1295 .parent_hws = (const struct clk_hw *[]) { 1296 &gxbb_cts_amclk_div.hw 1297 }, 1298 .num_parents = 1, 1299 .flags = CLK_SET_RATE_PARENT, 1300 }, 1301}; 1302 1303static struct clk_regmap gxbb_cts_mclk_i958_sel = { 1304 .data = &(struct clk_regmap_mux_data){ 1305 .offset = HHI_AUD_CLK_CNTL2, 1306 .mask = 0x3, 1307 .shift = 25, 1308 .table = gxbb_cts_mclk_parents_val_table, 1309 .flags = CLK_MUX_ROUND_CLOSEST, 1310 }, 1311 .hw.init = &(struct clk_init_data) { 1312 .name = "cts_mclk_i958_sel", 1313 .ops = &clk_regmap_mux_ops, 1314 .parent_hws = gxbb_cts_mclk_parents, 1315 .num_parents = ARRAY_SIZE(gxbb_cts_mclk_parents), 1316 }, 1317}; 1318 1319static struct clk_regmap gxbb_cts_mclk_i958_div = { 1320 .data = &(struct clk_regmap_div_data){ 1321 .offset = HHI_AUD_CLK_CNTL2, 1322 .shift = 16, 1323 .width = 8, 1324 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1325 }, 1326 .hw.init = &(struct clk_init_data) { 1327 .name = "cts_mclk_i958_div", 1328 .ops = &clk_regmap_divider_ops, 1329 .parent_hws = (const struct clk_hw *[]) { 1330 &gxbb_cts_mclk_i958_sel.hw 1331 }, 1332 .num_parents = 1, 1333 .flags = CLK_SET_RATE_PARENT, 1334 }, 1335}; 1336 1337static struct clk_regmap gxbb_cts_mclk_i958 = { 1338 .data = &(struct clk_regmap_gate_data){ 1339 .offset = HHI_AUD_CLK_CNTL2, 1340 .bit_idx = 24, 1341 }, 1342 .hw.init = &(struct clk_init_data){ 1343 .name = "cts_mclk_i958", 1344 .ops = &clk_regmap_gate_ops, 1345 .parent_hws = (const struct clk_hw *[]) { 1346 &gxbb_cts_mclk_i958_div.hw 1347 }, 1348 .num_parents = 1, 1349 .flags = CLK_SET_RATE_PARENT, 1350 }, 1351}; 1352 1353static struct clk_regmap gxbb_cts_i958 = { 1354 .data = &(struct clk_regmap_mux_data){ 1355 .offset = HHI_AUD_CLK_CNTL2, 1356 .mask = 0x1, 1357 .shift = 27, 1358 }, 1359 .hw.init = &(struct clk_init_data){ 1360 .name = "cts_i958", 1361 .ops = &clk_regmap_mux_ops, 1362 .parent_hws = (const struct clk_hw *[]) { 1363 &gxbb_cts_amclk.hw, 1364 &gxbb_cts_mclk_i958.hw 1365 }, 1366 .num_parents = 2, 1367 /* 1368 *The parent is specific to origin of the audio data. Let the 1369 * consumer choose the appropriate parent 1370 */ 1371 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 1372 }, 1373}; 1374 1375/* 1376 * This table skips a clock named 'cts_slow_oscin' in the documentation 1377 * This clock does not exist yet in this controller or the AO one 1378 */ 1379static u32 gxbb_32k_clk_parents_val_table[] = { 0, 2, 3 }; 1380static const struct clk_parent_data gxbb_32k_clk_parents[] = { 1381 { .fw_name = "xtal", }, 1382 { .hw = &gxbb_fclk_div3.hw }, 1383 { .hw = &gxbb_fclk_div5.hw }, 1384}; 1385 1386static struct clk_regmap gxbb_32k_clk_sel = { 1387 .data = &(struct clk_regmap_mux_data){ 1388 .offset = HHI_32K_CLK_CNTL, 1389 .mask = 0x3, 1390 .shift = 16, 1391 .table = gxbb_32k_clk_parents_val_table, 1392 }, 1393 .hw.init = &(struct clk_init_data){ 1394 .name = "32k_clk_sel", 1395 .ops = &clk_regmap_mux_ops, 1396 .parent_data = gxbb_32k_clk_parents, 1397 .num_parents = 4, 1398 .flags = CLK_SET_RATE_PARENT, 1399 }, 1400}; 1401 1402static struct clk_regmap gxbb_32k_clk_div = { 1403 .data = &(struct clk_regmap_div_data){ 1404 .offset = HHI_32K_CLK_CNTL, 1405 .shift = 0, 1406 .width = 14, 1407 }, 1408 .hw.init = &(struct clk_init_data){ 1409 .name = "32k_clk_div", 1410 .ops = &clk_regmap_divider_ops, 1411 .parent_hws = (const struct clk_hw *[]) { 1412 &gxbb_32k_clk_sel.hw 1413 }, 1414 .num_parents = 1, 1415 .flags = CLK_SET_RATE_PARENT, 1416 }, 1417}; 1418 1419static struct clk_regmap gxbb_32k_clk = { 1420 .data = &(struct clk_regmap_gate_data){ 1421 .offset = HHI_32K_CLK_CNTL, 1422 .bit_idx = 15, 1423 }, 1424 .hw.init = &(struct clk_init_data){ 1425 .name = "32k_clk", 1426 .ops = &clk_regmap_gate_ops, 1427 .parent_hws = (const struct clk_hw *[]) { 1428 &gxbb_32k_clk_div.hw 1429 }, 1430 .num_parents = 1, 1431 .flags = CLK_SET_RATE_PARENT, 1432 }, 1433}; 1434 1435static const struct clk_parent_data gxbb_sd_emmc_clk0_parents[] = { 1436 { .fw_name = "xtal", }, 1437 { .hw = &gxbb_fclk_div2.hw }, 1438 { .hw = &gxbb_fclk_div3.hw }, 1439 { .hw = &gxbb_fclk_div5.hw }, 1440 { .hw = &gxbb_fclk_div7.hw }, 1441 /* 1442 * Following these parent clocks, we should also have had mpll2, mpll3 1443 * and gp0_pll but these clocks are too precious to be used here. All 1444 * the necessary rates for MMC and NAND operation can be achieved using 1445 * xtal or fclk_div clocks 1446 */ 1447}; 1448 1449/* SDIO clock */ 1450static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = { 1451 .data = &(struct clk_regmap_mux_data){ 1452 .offset = HHI_SD_EMMC_CLK_CNTL, 1453 .mask = 0x7, 1454 .shift = 9, 1455 }, 1456 .hw.init = &(struct clk_init_data) { 1457 .name = "sd_emmc_a_clk0_sel", 1458 .ops = &clk_regmap_mux_ops, 1459 .parent_data = gxbb_sd_emmc_clk0_parents, 1460 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents), 1461 .flags = CLK_SET_RATE_PARENT, 1462 }, 1463}; 1464 1465static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { 1466 .data = &(struct clk_regmap_div_data){ 1467 .offset = HHI_SD_EMMC_CLK_CNTL, 1468 .shift = 0, 1469 .width = 7, 1470 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1471 }, 1472 .hw.init = &(struct clk_init_data) { 1473 .name = "sd_emmc_a_clk0_div", 1474 .ops = &clk_regmap_divider_ops, 1475 .parent_hws = (const struct clk_hw *[]) { 1476 &gxbb_sd_emmc_a_clk0_sel.hw 1477 }, 1478 .num_parents = 1, 1479 .flags = CLK_SET_RATE_PARENT, 1480 }, 1481}; 1482 1483static struct clk_regmap gxbb_sd_emmc_a_clk0 = { 1484 .data = &(struct clk_regmap_gate_data){ 1485 .offset = HHI_SD_EMMC_CLK_CNTL, 1486 .bit_idx = 7, 1487 }, 1488 .hw.init = &(struct clk_init_data){ 1489 .name = "sd_emmc_a_clk0", 1490 .ops = &clk_regmap_gate_ops, 1491 .parent_hws = (const struct clk_hw *[]) { 1492 &gxbb_sd_emmc_a_clk0_div.hw 1493 }, 1494 .num_parents = 1, 1495 .flags = CLK_SET_RATE_PARENT, 1496 }, 1497}; 1498 1499/* SDcard clock */ 1500static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = { 1501 .data = &(struct clk_regmap_mux_data){ 1502 .offset = HHI_SD_EMMC_CLK_CNTL, 1503 .mask = 0x7, 1504 .shift = 25, 1505 }, 1506 .hw.init = &(struct clk_init_data) { 1507 .name = "sd_emmc_b_clk0_sel", 1508 .ops = &clk_regmap_mux_ops, 1509 .parent_data = gxbb_sd_emmc_clk0_parents, 1510 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents), 1511 .flags = CLK_SET_RATE_PARENT, 1512 }, 1513}; 1514 1515static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { 1516 .data = &(struct clk_regmap_div_data){ 1517 .offset = HHI_SD_EMMC_CLK_CNTL, 1518 .shift = 16, 1519 .width = 7, 1520 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1521 }, 1522 .hw.init = &(struct clk_init_data) { 1523 .name = "sd_emmc_b_clk0_div", 1524 .ops = &clk_regmap_divider_ops, 1525 .parent_hws = (const struct clk_hw *[]) { 1526 &gxbb_sd_emmc_b_clk0_sel.hw 1527 }, 1528 .num_parents = 1, 1529 .flags = CLK_SET_RATE_PARENT, 1530 }, 1531}; 1532 1533static struct clk_regmap gxbb_sd_emmc_b_clk0 = { 1534 .data = &(struct clk_regmap_gate_data){ 1535 .offset = HHI_SD_EMMC_CLK_CNTL, 1536 .bit_idx = 23, 1537 }, 1538 .hw.init = &(struct clk_init_data){ 1539 .name = "sd_emmc_b_clk0", 1540 .ops = &clk_regmap_gate_ops, 1541 .parent_hws = (const struct clk_hw *[]) { 1542 &gxbb_sd_emmc_b_clk0_div.hw 1543 }, 1544 .num_parents = 1, 1545 .flags = CLK_SET_RATE_PARENT, 1546 }, 1547}; 1548 1549/* EMMC/NAND clock */ 1550static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = { 1551 .data = &(struct clk_regmap_mux_data){ 1552 .offset = HHI_NAND_CLK_CNTL, 1553 .mask = 0x7, 1554 .shift = 9, 1555 }, 1556 .hw.init = &(struct clk_init_data) { 1557 .name = "sd_emmc_c_clk0_sel", 1558 .ops = &clk_regmap_mux_ops, 1559 .parent_data = gxbb_sd_emmc_clk0_parents, 1560 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parents), 1561 .flags = CLK_SET_RATE_PARENT, 1562 }, 1563}; 1564 1565static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { 1566 .data = &(struct clk_regmap_div_data){ 1567 .offset = HHI_NAND_CLK_CNTL, 1568 .shift = 0, 1569 .width = 7, 1570 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1571 }, 1572 .hw.init = &(struct clk_init_data) { 1573 .name = "sd_emmc_c_clk0_div", 1574 .ops = &clk_regmap_divider_ops, 1575 .parent_hws = (const struct clk_hw *[]) { 1576 &gxbb_sd_emmc_c_clk0_sel.hw 1577 }, 1578 .num_parents = 1, 1579 .flags = CLK_SET_RATE_PARENT, 1580 }, 1581}; 1582 1583static struct clk_regmap gxbb_sd_emmc_c_clk0 = { 1584 .data = &(struct clk_regmap_gate_data){ 1585 .offset = HHI_NAND_CLK_CNTL, 1586 .bit_idx = 7, 1587 }, 1588 .hw.init = &(struct clk_init_data){ 1589 .name = "sd_emmc_c_clk0", 1590 .ops = &clk_regmap_gate_ops, 1591 .parent_hws = (const struct clk_hw *[]) { 1592 &gxbb_sd_emmc_c_clk0_div.hw 1593 }, 1594 .num_parents = 1, 1595 .flags = CLK_SET_RATE_PARENT, 1596 }, 1597}; 1598 1599/* VPU Clock */ 1600 1601static const struct clk_hw *gxbb_vpu_parents[] = { 1602 &gxbb_fclk_div4.hw, 1603 &gxbb_fclk_div3.hw, 1604 &gxbb_fclk_div5.hw, 1605 &gxbb_fclk_div7.hw, 1606}; 1607 1608static struct clk_regmap gxbb_vpu_0_sel = { 1609 .data = &(struct clk_regmap_mux_data){ 1610 .offset = HHI_VPU_CLK_CNTL, 1611 .mask = 0x3, 1612 .shift = 9, 1613 }, 1614 .hw.init = &(struct clk_init_data){ 1615 .name = "vpu_0_sel", 1616 .ops = &clk_regmap_mux_ops, 1617 /* 1618 * bits 9:10 selects from 4 possible parents: 1619 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1620 */ 1621 .parent_hws = gxbb_vpu_parents, 1622 .num_parents = ARRAY_SIZE(gxbb_vpu_parents), 1623 .flags = CLK_SET_RATE_NO_REPARENT, 1624 }, 1625}; 1626 1627static struct clk_regmap gxbb_vpu_0_div = { 1628 .data = &(struct clk_regmap_div_data){ 1629 .offset = HHI_VPU_CLK_CNTL, 1630 .shift = 0, 1631 .width = 7, 1632 }, 1633 .hw.init = &(struct clk_init_data){ 1634 .name = "vpu_0_div", 1635 .ops = &clk_regmap_divider_ops, 1636 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw }, 1637 .num_parents = 1, 1638 .flags = CLK_SET_RATE_PARENT, 1639 }, 1640}; 1641 1642static struct clk_regmap gxbb_vpu_0 = { 1643 .data = &(struct clk_regmap_gate_data){ 1644 .offset = HHI_VPU_CLK_CNTL, 1645 .bit_idx = 8, 1646 }, 1647 .hw.init = &(struct clk_init_data) { 1648 .name = "vpu_0", 1649 .ops = &clk_regmap_gate_ops, 1650 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw }, 1651 .num_parents = 1, 1652 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1653 }, 1654}; 1655 1656static struct clk_regmap gxbb_vpu_1_sel = { 1657 .data = &(struct clk_regmap_mux_data){ 1658 .offset = HHI_VPU_CLK_CNTL, 1659 .mask = 0x3, 1660 .shift = 25, 1661 }, 1662 .hw.init = &(struct clk_init_data){ 1663 .name = "vpu_1_sel", 1664 .ops = &clk_regmap_mux_ops, 1665 /* 1666 * bits 25:26 selects from 4 possible parents: 1667 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1668 */ 1669 .parent_hws = gxbb_vpu_parents, 1670 .num_parents = ARRAY_SIZE(gxbb_vpu_parents), 1671 .flags = CLK_SET_RATE_NO_REPARENT, 1672 }, 1673}; 1674 1675static struct clk_regmap gxbb_vpu_1_div = { 1676 .data = &(struct clk_regmap_div_data){ 1677 .offset = HHI_VPU_CLK_CNTL, 1678 .shift = 16, 1679 .width = 7, 1680 }, 1681 .hw.init = &(struct clk_init_data){ 1682 .name = "vpu_1_div", 1683 .ops = &clk_regmap_divider_ops, 1684 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw }, 1685 .num_parents = 1, 1686 .flags = CLK_SET_RATE_PARENT, 1687 }, 1688}; 1689 1690static struct clk_regmap gxbb_vpu_1 = { 1691 .data = &(struct clk_regmap_gate_data){ 1692 .offset = HHI_VPU_CLK_CNTL, 1693 .bit_idx = 24, 1694 }, 1695 .hw.init = &(struct clk_init_data) { 1696 .name = "vpu_1", 1697 .ops = &clk_regmap_gate_ops, 1698 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw }, 1699 .num_parents = 1, 1700 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1701 }, 1702}; 1703 1704static struct clk_regmap gxbb_vpu = { 1705 .data = &(struct clk_regmap_mux_data){ 1706 .offset = HHI_VPU_CLK_CNTL, 1707 .mask = 1, 1708 .shift = 31, 1709 }, 1710 .hw.init = &(struct clk_init_data){ 1711 .name = "vpu", 1712 .ops = &clk_regmap_mux_ops, 1713 /* 1714 * bit 31 selects from 2 possible parents: 1715 * vpu_0 or vpu_1 1716 */ 1717 .parent_hws = (const struct clk_hw *[]) { 1718 &gxbb_vpu_0.hw, 1719 &gxbb_vpu_1.hw 1720 }, 1721 .num_parents = 2, 1722 .flags = CLK_SET_RATE_NO_REPARENT, 1723 }, 1724}; 1725 1726/* VAPB Clock */ 1727 1728static const struct clk_hw *gxbb_vapb_parents[] = { 1729 &gxbb_fclk_div4.hw, 1730 &gxbb_fclk_div3.hw, 1731 &gxbb_fclk_div5.hw, 1732 &gxbb_fclk_div7.hw, 1733}; 1734 1735static struct clk_regmap gxbb_vapb_0_sel = { 1736 .data = &(struct clk_regmap_mux_data){ 1737 .offset = HHI_VAPBCLK_CNTL, 1738 .mask = 0x3, 1739 .shift = 9, 1740 }, 1741 .hw.init = &(struct clk_init_data){ 1742 .name = "vapb_0_sel", 1743 .ops = &clk_regmap_mux_ops, 1744 /* 1745 * bits 9:10 selects from 4 possible parents: 1746 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1747 */ 1748 .parent_hws = gxbb_vapb_parents, 1749 .num_parents = ARRAY_SIZE(gxbb_vapb_parents), 1750 .flags = CLK_SET_RATE_NO_REPARENT, 1751 }, 1752}; 1753 1754static struct clk_regmap gxbb_vapb_0_div = { 1755 .data = &(struct clk_regmap_div_data){ 1756 .offset = HHI_VAPBCLK_CNTL, 1757 .shift = 0, 1758 .width = 7, 1759 }, 1760 .hw.init = &(struct clk_init_data){ 1761 .name = "vapb_0_div", 1762 .ops = &clk_regmap_divider_ops, 1763 .parent_hws = (const struct clk_hw *[]) { 1764 &gxbb_vapb_0_sel.hw 1765 }, 1766 .num_parents = 1, 1767 .flags = CLK_SET_RATE_PARENT, 1768 }, 1769}; 1770 1771static struct clk_regmap gxbb_vapb_0 = { 1772 .data = &(struct clk_regmap_gate_data){ 1773 .offset = HHI_VAPBCLK_CNTL, 1774 .bit_idx = 8, 1775 }, 1776 .hw.init = &(struct clk_init_data) { 1777 .name = "vapb_0", 1778 .ops = &clk_regmap_gate_ops, 1779 .parent_hws = (const struct clk_hw *[]) { 1780 &gxbb_vapb_0_div.hw 1781 }, 1782 .num_parents = 1, 1783 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1784 }, 1785}; 1786 1787static struct clk_regmap gxbb_vapb_1_sel = { 1788 .data = &(struct clk_regmap_mux_data){ 1789 .offset = HHI_VAPBCLK_CNTL, 1790 .mask = 0x3, 1791 .shift = 25, 1792 }, 1793 .hw.init = &(struct clk_init_data){ 1794 .name = "vapb_1_sel", 1795 .ops = &clk_regmap_mux_ops, 1796 /* 1797 * bits 25:26 selects from 4 possible parents: 1798 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1799 */ 1800 .parent_hws = gxbb_vapb_parents, 1801 .num_parents = ARRAY_SIZE(gxbb_vapb_parents), 1802 .flags = CLK_SET_RATE_NO_REPARENT, 1803 }, 1804}; 1805 1806static struct clk_regmap gxbb_vapb_1_div = { 1807 .data = &(struct clk_regmap_div_data){ 1808 .offset = HHI_VAPBCLK_CNTL, 1809 .shift = 16, 1810 .width = 7, 1811 }, 1812 .hw.init = &(struct clk_init_data){ 1813 .name = "vapb_1_div", 1814 .ops = &clk_regmap_divider_ops, 1815 .parent_hws = (const struct clk_hw *[]) { 1816 &gxbb_vapb_1_sel.hw 1817 }, 1818 .num_parents = 1, 1819 .flags = CLK_SET_RATE_PARENT, 1820 }, 1821}; 1822 1823static struct clk_regmap gxbb_vapb_1 = { 1824 .data = &(struct clk_regmap_gate_data){ 1825 .offset = HHI_VAPBCLK_CNTL, 1826 .bit_idx = 24, 1827 }, 1828 .hw.init = &(struct clk_init_data) { 1829 .name = "vapb_1", 1830 .ops = &clk_regmap_gate_ops, 1831 .parent_hws = (const struct clk_hw *[]) { 1832 &gxbb_vapb_1_div.hw 1833 }, 1834 .num_parents = 1, 1835 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1836 }, 1837}; 1838 1839static struct clk_regmap gxbb_vapb_sel = { 1840 .data = &(struct clk_regmap_mux_data){ 1841 .offset = HHI_VAPBCLK_CNTL, 1842 .mask = 1, 1843 .shift = 31, 1844 }, 1845 .hw.init = &(struct clk_init_data){ 1846 .name = "vapb_sel", 1847 .ops = &clk_regmap_mux_ops, 1848 /* 1849 * bit 31 selects from 2 possible parents: 1850 * vapb_0 or vapb_1 1851 */ 1852 .parent_hws = (const struct clk_hw *[]) { 1853 &gxbb_vapb_0.hw, 1854 &gxbb_vapb_1.hw 1855 }, 1856 .num_parents = 2, 1857 .flags = CLK_SET_RATE_NO_REPARENT, 1858 }, 1859}; 1860 1861static struct clk_regmap gxbb_vapb = { 1862 .data = &(struct clk_regmap_gate_data){ 1863 .offset = HHI_VAPBCLK_CNTL, 1864 .bit_idx = 30, 1865 }, 1866 .hw.init = &(struct clk_init_data) { 1867 .name = "vapb", 1868 .ops = &clk_regmap_gate_ops, 1869 .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw }, 1870 .num_parents = 1, 1871 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1872 }, 1873}; 1874 1875/* Video Clocks */ 1876 1877static struct clk_regmap gxbb_vid_pll_div = { 1878 .data = &(struct meson_vid_pll_div_data){ 1879 .val = { 1880 .reg_off = HHI_VID_PLL_CLK_DIV, 1881 .shift = 0, 1882 .width = 15, 1883 }, 1884 .sel = { 1885 .reg_off = HHI_VID_PLL_CLK_DIV, 1886 .shift = 16, 1887 .width = 2, 1888 }, 1889 }, 1890 .hw.init = &(struct clk_init_data) { 1891 .name = "vid_pll_div", 1892 .ops = &meson_vid_pll_div_ro_ops, 1893 .parent_data = &(const struct clk_parent_data) { 1894 /* 1895 * Note: 1896 * GXL and GXBB have different hdmi_plls (with 1897 * different struct clk_hw). We fallback to the global 1898 * naming string mechanism so vid_pll_div picks up the 1899 * appropriate one. 1900 */ 1901 .name = "hdmi_pll", 1902 .index = -1, 1903 }, 1904 .num_parents = 1, 1905 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 1906 }, 1907}; 1908 1909static const struct clk_parent_data gxbb_vid_pll_parents[] = { 1910 { .hw = &gxbb_vid_pll_div.hw }, 1911 /* 1912 * Note: 1913 * GXL and GXBB have different hdmi_plls (with 1914 * different struct clk_hw). We fallback to the global 1915 * naming string mechanism so vid_pll_div picks up the 1916 * appropriate one. 1917 */ 1918 { .name = "hdmi_pll", .index = -1 }, 1919}; 1920 1921static struct clk_regmap gxbb_vid_pll_sel = { 1922 .data = &(struct clk_regmap_mux_data){ 1923 .offset = HHI_VID_PLL_CLK_DIV, 1924 .mask = 0x1, 1925 .shift = 18, 1926 }, 1927 .hw.init = &(struct clk_init_data){ 1928 .name = "vid_pll_sel", 1929 .ops = &clk_regmap_mux_ops, 1930 /* 1931 * bit 18 selects from 2 possible parents: 1932 * vid_pll_div or hdmi_pll 1933 */ 1934 .parent_data = gxbb_vid_pll_parents, 1935 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parents), 1936 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1937 }, 1938}; 1939 1940static struct clk_regmap gxbb_vid_pll = { 1941 .data = &(struct clk_regmap_gate_data){ 1942 .offset = HHI_VID_PLL_CLK_DIV, 1943 .bit_idx = 19, 1944 }, 1945 .hw.init = &(struct clk_init_data) { 1946 .name = "vid_pll", 1947 .ops = &clk_regmap_gate_ops, 1948 .parent_hws = (const struct clk_hw *[]) { 1949 &gxbb_vid_pll_sel.hw 1950 }, 1951 .num_parents = 1, 1952 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1953 }, 1954}; 1955 1956static const struct clk_hw *gxbb_vclk_parents[] = { 1957 &gxbb_vid_pll.hw, 1958 &gxbb_fclk_div4.hw, 1959 &gxbb_fclk_div3.hw, 1960 &gxbb_fclk_div5.hw, 1961 &gxbb_vid_pll.hw, 1962 &gxbb_fclk_div7.hw, 1963 &gxbb_mpll1.hw, 1964}; 1965 1966static struct clk_regmap gxbb_vclk_sel = { 1967 .data = &(struct clk_regmap_mux_data){ 1968 .offset = HHI_VID_CLK_CNTL, 1969 .mask = 0x7, 1970 .shift = 16, 1971 }, 1972 .hw.init = &(struct clk_init_data){ 1973 .name = "vclk_sel", 1974 .ops = &clk_regmap_mux_ops, 1975 /* 1976 * bits 16:18 selects from 8 possible parents: 1977 * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1978 * vid_pll, fclk_div7, mp1 1979 */ 1980 .parent_hws = gxbb_vclk_parents, 1981 .num_parents = ARRAY_SIZE(gxbb_vclk_parents), 1982 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1983 }, 1984}; 1985 1986static struct clk_regmap gxbb_vclk2_sel = { 1987 .data = &(struct clk_regmap_mux_data){ 1988 .offset = HHI_VIID_CLK_CNTL, 1989 .mask = 0x7, 1990 .shift = 16, 1991 }, 1992 .hw.init = &(struct clk_init_data){ 1993 .name = "vclk2_sel", 1994 .ops = &clk_regmap_mux_ops, 1995 /* 1996 * bits 16:18 selects from 8 possible parents: 1997 * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1998 * vid_pll, fclk_div7, mp1 1999 */ 2000 .parent_hws = gxbb_vclk_parents, 2001 .num_parents = ARRAY_SIZE(gxbb_vclk_parents), 2002 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2003 }, 2004}; 2005 2006static struct clk_regmap gxbb_vclk_input = { 2007 .data = &(struct clk_regmap_gate_data){ 2008 .offset = HHI_VID_CLK_DIV, 2009 .bit_idx = 16, 2010 }, 2011 .hw.init = &(struct clk_init_data) { 2012 .name = "vclk_input", 2013 .ops = &clk_regmap_gate_ops, 2014 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw }, 2015 .num_parents = 1, 2016 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2017 }, 2018}; 2019 2020static struct clk_regmap gxbb_vclk2_input = { 2021 .data = &(struct clk_regmap_gate_data){ 2022 .offset = HHI_VIID_CLK_DIV, 2023 .bit_idx = 16, 2024 }, 2025 .hw.init = &(struct clk_init_data) { 2026 .name = "vclk2_input", 2027 .ops = &clk_regmap_gate_ops, 2028 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw }, 2029 .num_parents = 1, 2030 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2031 }, 2032}; 2033 2034static struct clk_regmap gxbb_vclk_div = { 2035 .data = &(struct clk_regmap_div_data){ 2036 .offset = HHI_VID_CLK_DIV, 2037 .shift = 0, 2038 .width = 8, 2039 }, 2040 .hw.init = &(struct clk_init_data){ 2041 .name = "vclk_div", 2042 .ops = &clk_regmap_divider_ops, 2043 .parent_hws = (const struct clk_hw *[]) { 2044 &gxbb_vclk_input.hw 2045 }, 2046 .num_parents = 1, 2047 .flags = CLK_GET_RATE_NOCACHE, 2048 }, 2049}; 2050 2051static struct clk_regmap gxbb_vclk2_div = { 2052 .data = &(struct clk_regmap_div_data){ 2053 .offset = HHI_VIID_CLK_DIV, 2054 .shift = 0, 2055 .width = 8, 2056 }, 2057 .hw.init = &(struct clk_init_data){ 2058 .name = "vclk2_div", 2059 .ops = &clk_regmap_divider_ops, 2060 .parent_hws = (const struct clk_hw *[]) { 2061 &gxbb_vclk2_input.hw 2062 }, 2063 .num_parents = 1, 2064 .flags = CLK_GET_RATE_NOCACHE, 2065 }, 2066}; 2067 2068static struct clk_regmap gxbb_vclk = { 2069 .data = &(struct clk_regmap_gate_data){ 2070 .offset = HHI_VID_CLK_CNTL, 2071 .bit_idx = 19, 2072 }, 2073 .hw.init = &(struct clk_init_data) { 2074 .name = "vclk", 2075 .ops = &clk_regmap_gate_ops, 2076 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw }, 2077 .num_parents = 1, 2078 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2079 }, 2080}; 2081 2082static struct clk_regmap gxbb_vclk2 = { 2083 .data = &(struct clk_regmap_gate_data){ 2084 .offset = HHI_VIID_CLK_CNTL, 2085 .bit_idx = 19, 2086 }, 2087 .hw.init = &(struct clk_init_data) { 2088 .name = "vclk2", 2089 .ops = &clk_regmap_gate_ops, 2090 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw }, 2091 .num_parents = 1, 2092 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2093 }, 2094}; 2095 2096static struct clk_regmap gxbb_vclk_div1 = { 2097 .data = &(struct clk_regmap_gate_data){ 2098 .offset = HHI_VID_CLK_CNTL, 2099 .bit_idx = 0, 2100 }, 2101 .hw.init = &(struct clk_init_data) { 2102 .name = "vclk_div1", 2103 .ops = &clk_regmap_gate_ops, 2104 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2105 .num_parents = 1, 2106 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2107 }, 2108}; 2109 2110static struct clk_regmap gxbb_vclk_div2_en = { 2111 .data = &(struct clk_regmap_gate_data){ 2112 .offset = HHI_VID_CLK_CNTL, 2113 .bit_idx = 1, 2114 }, 2115 .hw.init = &(struct clk_init_data) { 2116 .name = "vclk_div2_en", 2117 .ops = &clk_regmap_gate_ops, 2118 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2119 .num_parents = 1, 2120 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2121 }, 2122}; 2123 2124static struct clk_regmap gxbb_vclk_div4_en = { 2125 .data = &(struct clk_regmap_gate_data){ 2126 .offset = HHI_VID_CLK_CNTL, 2127 .bit_idx = 2, 2128 }, 2129 .hw.init = &(struct clk_init_data) { 2130 .name = "vclk_div4_en", 2131 .ops = &clk_regmap_gate_ops, 2132 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2133 .num_parents = 1, 2134 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2135 }, 2136}; 2137 2138static struct clk_regmap gxbb_vclk_div6_en = { 2139 .data = &(struct clk_regmap_gate_data){ 2140 .offset = HHI_VID_CLK_CNTL, 2141 .bit_idx = 3, 2142 }, 2143 .hw.init = &(struct clk_init_data) { 2144 .name = "vclk_div6_en", 2145 .ops = &clk_regmap_gate_ops, 2146 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2147 .num_parents = 1, 2148 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2149 }, 2150}; 2151 2152static struct clk_regmap gxbb_vclk_div12_en = { 2153 .data = &(struct clk_regmap_gate_data){ 2154 .offset = HHI_VID_CLK_CNTL, 2155 .bit_idx = 4, 2156 }, 2157 .hw.init = &(struct clk_init_data) { 2158 .name = "vclk_div12_en", 2159 .ops = &clk_regmap_gate_ops, 2160 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2161 .num_parents = 1, 2162 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2163 }, 2164}; 2165 2166static struct clk_regmap gxbb_vclk2_div1 = { 2167 .data = &(struct clk_regmap_gate_data){ 2168 .offset = HHI_VIID_CLK_CNTL, 2169 .bit_idx = 0, 2170 }, 2171 .hw.init = &(struct clk_init_data) { 2172 .name = "vclk2_div1", 2173 .ops = &clk_regmap_gate_ops, 2174 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2175 .num_parents = 1, 2176 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2177 }, 2178}; 2179 2180static struct clk_regmap gxbb_vclk2_div2_en = { 2181 .data = &(struct clk_regmap_gate_data){ 2182 .offset = HHI_VIID_CLK_CNTL, 2183 .bit_idx = 1, 2184 }, 2185 .hw.init = &(struct clk_init_data) { 2186 .name = "vclk2_div2_en", 2187 .ops = &clk_regmap_gate_ops, 2188 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2189 .num_parents = 1, 2190 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2191 }, 2192}; 2193 2194static struct clk_regmap gxbb_vclk2_div4_en = { 2195 .data = &(struct clk_regmap_gate_data){ 2196 .offset = HHI_VIID_CLK_CNTL, 2197 .bit_idx = 2, 2198 }, 2199 .hw.init = &(struct clk_init_data) { 2200 .name = "vclk2_div4_en", 2201 .ops = &clk_regmap_gate_ops, 2202 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2203 .num_parents = 1, 2204 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2205 }, 2206}; 2207 2208static struct clk_regmap gxbb_vclk2_div6_en = { 2209 .data = &(struct clk_regmap_gate_data){ 2210 .offset = HHI_VIID_CLK_CNTL, 2211 .bit_idx = 3, 2212 }, 2213 .hw.init = &(struct clk_init_data) { 2214 .name = "vclk2_div6_en", 2215 .ops = &clk_regmap_gate_ops, 2216 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2217 .num_parents = 1, 2218 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2219 }, 2220}; 2221 2222static struct clk_regmap gxbb_vclk2_div12_en = { 2223 .data = &(struct clk_regmap_gate_data){ 2224 .offset = HHI_VIID_CLK_CNTL, 2225 .bit_idx = 4, 2226 }, 2227 .hw.init = &(struct clk_init_data) { 2228 .name = "vclk2_div12_en", 2229 .ops = &clk_regmap_gate_ops, 2230 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2231 .num_parents = 1, 2232 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2233 }, 2234}; 2235 2236static struct clk_fixed_factor gxbb_vclk_div2 = { 2237 .mult = 1, 2238 .div = 2, 2239 .hw.init = &(struct clk_init_data){ 2240 .name = "vclk_div2", 2241 .ops = &clk_fixed_factor_ops, 2242 .parent_hws = (const struct clk_hw *[]) { 2243 &gxbb_vclk_div2_en.hw 2244 }, 2245 .num_parents = 1, 2246 }, 2247}; 2248 2249static struct clk_fixed_factor gxbb_vclk_div4 = { 2250 .mult = 1, 2251 .div = 4, 2252 .hw.init = &(struct clk_init_data){ 2253 .name = "vclk_div4", 2254 .ops = &clk_fixed_factor_ops, 2255 .parent_hws = (const struct clk_hw *[]) { 2256 &gxbb_vclk_div4_en.hw 2257 }, 2258 .num_parents = 1, 2259 }, 2260}; 2261 2262static struct clk_fixed_factor gxbb_vclk_div6 = { 2263 .mult = 1, 2264 .div = 6, 2265 .hw.init = &(struct clk_init_data){ 2266 .name = "vclk_div6", 2267 .ops = &clk_fixed_factor_ops, 2268 .parent_hws = (const struct clk_hw *[]) { 2269 &gxbb_vclk_div6_en.hw 2270 }, 2271 .num_parents = 1, 2272 }, 2273}; 2274 2275static struct clk_fixed_factor gxbb_vclk_div12 = { 2276 .mult = 1, 2277 .div = 12, 2278 .hw.init = &(struct clk_init_data){ 2279 .name = "vclk_div12", 2280 .ops = &clk_fixed_factor_ops, 2281 .parent_hws = (const struct clk_hw *[]) { 2282 &gxbb_vclk_div12_en.hw 2283 }, 2284 .num_parents = 1, 2285 }, 2286}; 2287 2288static struct clk_fixed_factor gxbb_vclk2_div2 = { 2289 .mult = 1, 2290 .div = 2, 2291 .hw.init = &(struct clk_init_data){ 2292 .name = "vclk2_div2", 2293 .ops = &clk_fixed_factor_ops, 2294 .parent_hws = (const struct clk_hw *[]) { 2295 &gxbb_vclk2_div2_en.hw 2296 }, 2297 .num_parents = 1, 2298 }, 2299}; 2300 2301static struct clk_fixed_factor gxbb_vclk2_div4 = { 2302 .mult = 1, 2303 .div = 4, 2304 .hw.init = &(struct clk_init_data){ 2305 .name = "vclk2_div4", 2306 .ops = &clk_fixed_factor_ops, 2307 .parent_hws = (const struct clk_hw *[]) { 2308 &gxbb_vclk2_div4_en.hw 2309 }, 2310 .num_parents = 1, 2311 }, 2312}; 2313 2314static struct clk_fixed_factor gxbb_vclk2_div6 = { 2315 .mult = 1, 2316 .div = 6, 2317 .hw.init = &(struct clk_init_data){ 2318 .name = "vclk2_div6", 2319 .ops = &clk_fixed_factor_ops, 2320 .parent_hws = (const struct clk_hw *[]) { 2321 &gxbb_vclk2_div6_en.hw 2322 }, 2323 .num_parents = 1, 2324 }, 2325}; 2326 2327static struct clk_fixed_factor gxbb_vclk2_div12 = { 2328 .mult = 1, 2329 .div = 12, 2330 .hw.init = &(struct clk_init_data){ 2331 .name = "vclk2_div12", 2332 .ops = &clk_fixed_factor_ops, 2333 .parent_hws = (const struct clk_hw *[]) { 2334 &gxbb_vclk2_div12_en.hw 2335 }, 2336 .num_parents = 1, 2337 }, 2338}; 2339 2340static u32 gxbb_cts_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 2341static const struct clk_hw *gxbb_cts_parents[] = { 2342 &gxbb_vclk_div1.hw, 2343 &gxbb_vclk_div2.hw, 2344 &gxbb_vclk_div4.hw, 2345 &gxbb_vclk_div6.hw, 2346 &gxbb_vclk_div12.hw, 2347 &gxbb_vclk2_div1.hw, 2348 &gxbb_vclk2_div2.hw, 2349 &gxbb_vclk2_div4.hw, 2350 &gxbb_vclk2_div6.hw, 2351 &gxbb_vclk2_div12.hw, 2352}; 2353 2354static struct clk_regmap gxbb_cts_enci_sel = { 2355 .data = &(struct clk_regmap_mux_data){ 2356 .offset = HHI_VID_CLK_DIV, 2357 .mask = 0xf, 2358 .shift = 28, 2359 .table = gxbb_cts_parents_val_table, 2360 }, 2361 .hw.init = &(struct clk_init_data){ 2362 .name = "cts_enci_sel", 2363 .ops = &clk_regmap_mux_ops, 2364 .parent_hws = gxbb_cts_parents, 2365 .num_parents = ARRAY_SIZE(gxbb_cts_parents), 2366 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2367 }, 2368}; 2369 2370static struct clk_regmap gxbb_cts_encp_sel = { 2371 .data = &(struct clk_regmap_mux_data){ 2372 .offset = HHI_VID_CLK_DIV, 2373 .mask = 0xf, 2374 .shift = 20, 2375 .table = gxbb_cts_parents_val_table, 2376 }, 2377 .hw.init = &(struct clk_init_data){ 2378 .name = "cts_encp_sel", 2379 .ops = &clk_regmap_mux_ops, 2380 .parent_hws = gxbb_cts_parents, 2381 .num_parents = ARRAY_SIZE(gxbb_cts_parents), 2382 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2383 }, 2384}; 2385 2386static struct clk_regmap gxbb_cts_vdac_sel = { 2387 .data = &(struct clk_regmap_mux_data){ 2388 .offset = HHI_VIID_CLK_DIV, 2389 .mask = 0xf, 2390 .shift = 28, 2391 .table = gxbb_cts_parents_val_table, 2392 }, 2393 .hw.init = &(struct clk_init_data){ 2394 .name = "cts_vdac_sel", 2395 .ops = &clk_regmap_mux_ops, 2396 .parent_hws = gxbb_cts_parents, 2397 .num_parents = ARRAY_SIZE(gxbb_cts_parents), 2398 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2399 }, 2400}; 2401 2402static struct clk_regmap gxbb_cts_enci = { 2403 .data = &(struct clk_regmap_gate_data){ 2404 .offset = HHI_VID_CLK_CNTL2, 2405 .bit_idx = 0, 2406 }, 2407 .hw.init = &(struct clk_init_data) { 2408 .name = "cts_enci", 2409 .ops = &clk_regmap_gate_ops, 2410 .parent_hws = (const struct clk_hw *[]) { 2411 &gxbb_cts_enci_sel.hw 2412 }, 2413 .num_parents = 1, 2414 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2415 }, 2416}; 2417 2418static struct clk_regmap gxbb_cts_encp = { 2419 .data = &(struct clk_regmap_gate_data){ 2420 .offset = HHI_VID_CLK_CNTL2, 2421 .bit_idx = 2, 2422 }, 2423 .hw.init = &(struct clk_init_data) { 2424 .name = "cts_encp", 2425 .ops = &clk_regmap_gate_ops, 2426 .parent_hws = (const struct clk_hw *[]) { 2427 &gxbb_cts_encp_sel.hw 2428 }, 2429 .num_parents = 1, 2430 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2431 }, 2432}; 2433 2434static struct clk_regmap gxbb_cts_vdac = { 2435 .data = &(struct clk_regmap_gate_data){ 2436 .offset = HHI_VID_CLK_CNTL2, 2437 .bit_idx = 4, 2438 }, 2439 .hw.init = &(struct clk_init_data) { 2440 .name = "cts_vdac", 2441 .ops = &clk_regmap_gate_ops, 2442 .parent_hws = (const struct clk_hw *[]) { 2443 &gxbb_cts_vdac_sel.hw 2444 }, 2445 .num_parents = 1, 2446 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2447 }, 2448}; 2449 2450/* TOFIX: add support for cts_tcon */ 2451static u32 gxbb_hdmi_tx_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 2452static const struct clk_hw *gxbb_hdmi_tx_parents[] = { 2453 &gxbb_vclk_div1.hw, 2454 &gxbb_vclk_div2.hw, 2455 &gxbb_vclk_div4.hw, 2456 &gxbb_vclk_div6.hw, 2457 &gxbb_vclk_div12.hw, 2458 &gxbb_vclk2_div1.hw, 2459 &gxbb_vclk2_div2.hw, 2460 &gxbb_vclk2_div4.hw, 2461 &gxbb_vclk2_div6.hw, 2462 &gxbb_vclk2_div12.hw, 2463}; 2464 2465static struct clk_regmap gxbb_hdmi_tx_sel = { 2466 .data = &(struct clk_regmap_mux_data){ 2467 .offset = HHI_HDMI_CLK_CNTL, 2468 .mask = 0xf, 2469 .shift = 16, 2470 .table = gxbb_hdmi_tx_parents_val_table, 2471 }, 2472 .hw.init = &(struct clk_init_data){ 2473 .name = "hdmi_tx_sel", 2474 .ops = &clk_regmap_mux_ops, 2475 /* 2476 * bits 31:28 selects from 12 possible parents: 2477 * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12 2478 * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12, 2479 * cts_tcon 2480 */ 2481 .parent_hws = gxbb_hdmi_tx_parents, 2482 .num_parents = ARRAY_SIZE(gxbb_hdmi_tx_parents), 2483 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2484 }, 2485}; 2486 2487static struct clk_regmap gxbb_hdmi_tx = { 2488 .data = &(struct clk_regmap_gate_data){ 2489 .offset = HHI_VID_CLK_CNTL2, 2490 .bit_idx = 5, 2491 }, 2492 .hw.init = &(struct clk_init_data) { 2493 .name = "hdmi_tx", 2494 .ops = &clk_regmap_gate_ops, 2495 .parent_hws = (const struct clk_hw *[]) { 2496 &gxbb_hdmi_tx_sel.hw 2497 }, 2498 .num_parents = 1, 2499 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2500 }, 2501}; 2502 2503/* HDMI Clocks */ 2504 2505static const struct clk_parent_data gxbb_hdmi_parents[] = { 2506 { .fw_name = "xtal", }, 2507 { .hw = &gxbb_fclk_div4.hw }, 2508 { .hw = &gxbb_fclk_div3.hw }, 2509 { .hw = &gxbb_fclk_div5.hw }, 2510}; 2511 2512static struct clk_regmap gxbb_hdmi_sel = { 2513 .data = &(struct clk_regmap_mux_data){ 2514 .offset = HHI_HDMI_CLK_CNTL, 2515 .mask = 0x3, 2516 .shift = 9, 2517 .flags = CLK_MUX_ROUND_CLOSEST, 2518 }, 2519 .hw.init = &(struct clk_init_data){ 2520 .name = "hdmi_sel", 2521 .ops = &clk_regmap_mux_ops, 2522 .parent_data = gxbb_hdmi_parents, 2523 .num_parents = ARRAY_SIZE(gxbb_hdmi_parents), 2524 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2525 }, 2526}; 2527 2528static struct clk_regmap gxbb_hdmi_div = { 2529 .data = &(struct clk_regmap_div_data){ 2530 .offset = HHI_HDMI_CLK_CNTL, 2531 .shift = 0, 2532 .width = 7, 2533 }, 2534 .hw.init = &(struct clk_init_data){ 2535 .name = "hdmi_div", 2536 .ops = &clk_regmap_divider_ops, 2537 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw }, 2538 .num_parents = 1, 2539 .flags = CLK_GET_RATE_NOCACHE, 2540 }, 2541}; 2542 2543static struct clk_regmap gxbb_hdmi = { 2544 .data = &(struct clk_regmap_gate_data){ 2545 .offset = HHI_HDMI_CLK_CNTL, 2546 .bit_idx = 8, 2547 }, 2548 .hw.init = &(struct clk_init_data) { 2549 .name = "hdmi", 2550 .ops = &clk_regmap_gate_ops, 2551 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw }, 2552 .num_parents = 1, 2553 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2554 }, 2555}; 2556 2557/* VDEC clocks */ 2558 2559static const struct clk_hw *gxbb_vdec_parents[] = { 2560 &gxbb_fclk_div4.hw, 2561 &gxbb_fclk_div3.hw, 2562 &gxbb_fclk_div5.hw, 2563 &gxbb_fclk_div7.hw, 2564}; 2565 2566static struct clk_regmap gxbb_vdec_1_sel = { 2567 .data = &(struct clk_regmap_mux_data){ 2568 .offset = HHI_VDEC_CLK_CNTL, 2569 .mask = 0x3, 2570 .shift = 9, 2571 .flags = CLK_MUX_ROUND_CLOSEST, 2572 }, 2573 .hw.init = &(struct clk_init_data){ 2574 .name = "vdec_1_sel", 2575 .ops = &clk_regmap_mux_ops, 2576 .parent_hws = gxbb_vdec_parents, 2577 .num_parents = ARRAY_SIZE(gxbb_vdec_parents), 2578 .flags = CLK_SET_RATE_PARENT, 2579 }, 2580}; 2581 2582static struct clk_regmap gxbb_vdec_1_div = { 2583 .data = &(struct clk_regmap_div_data){ 2584 .offset = HHI_VDEC_CLK_CNTL, 2585 .shift = 0, 2586 .width = 7, 2587 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2588 }, 2589 .hw.init = &(struct clk_init_data){ 2590 .name = "vdec_1_div", 2591 .ops = &clk_regmap_divider_ops, 2592 .parent_hws = (const struct clk_hw *[]) { 2593 &gxbb_vdec_1_sel.hw 2594 }, 2595 .num_parents = 1, 2596 .flags = CLK_SET_RATE_PARENT, 2597 }, 2598}; 2599 2600static struct clk_regmap gxbb_vdec_1 = { 2601 .data = &(struct clk_regmap_gate_data){ 2602 .offset = HHI_VDEC_CLK_CNTL, 2603 .bit_idx = 8, 2604 }, 2605 .hw.init = &(struct clk_init_data) { 2606 .name = "vdec_1", 2607 .ops = &clk_regmap_gate_ops, 2608 .parent_hws = (const struct clk_hw *[]) { 2609 &gxbb_vdec_1_div.hw 2610 }, 2611 .num_parents = 1, 2612 .flags = CLK_SET_RATE_PARENT, 2613 }, 2614}; 2615 2616static struct clk_regmap gxbb_vdec_hevc_sel = { 2617 .data = &(struct clk_regmap_mux_data){ 2618 .offset = HHI_VDEC2_CLK_CNTL, 2619 .mask = 0x3, 2620 .shift = 25, 2621 .flags = CLK_MUX_ROUND_CLOSEST, 2622 }, 2623 .hw.init = &(struct clk_init_data){ 2624 .name = "vdec_hevc_sel", 2625 .ops = &clk_regmap_mux_ops, 2626 .parent_hws = gxbb_vdec_parents, 2627 .num_parents = ARRAY_SIZE(gxbb_vdec_parents), 2628 .flags = CLK_SET_RATE_PARENT, 2629 }, 2630}; 2631 2632static struct clk_regmap gxbb_vdec_hevc_div = { 2633 .data = &(struct clk_regmap_div_data){ 2634 .offset = HHI_VDEC2_CLK_CNTL, 2635 .shift = 16, 2636 .width = 7, 2637 .flags = CLK_DIVIDER_ROUND_CLOSEST, 2638 }, 2639 .hw.init = &(struct clk_init_data){ 2640 .name = "vdec_hevc_div", 2641 .ops = &clk_regmap_divider_ops, 2642 .parent_hws = (const struct clk_hw *[]) { 2643 &gxbb_vdec_hevc_sel.hw 2644 }, 2645 .num_parents = 1, 2646 .flags = CLK_SET_RATE_PARENT, 2647 }, 2648}; 2649 2650static struct clk_regmap gxbb_vdec_hevc = { 2651 .data = &(struct clk_regmap_gate_data){ 2652 .offset = HHI_VDEC2_CLK_CNTL, 2653 .bit_idx = 24, 2654 }, 2655 .hw.init = &(struct clk_init_data) { 2656 .name = "vdec_hevc", 2657 .ops = &clk_regmap_gate_ops, 2658 .parent_hws = (const struct clk_hw *[]) { 2659 &gxbb_vdec_hevc_div.hw 2660 }, 2661 .num_parents = 1, 2662 .flags = CLK_SET_RATE_PARENT, 2663 }, 2664}; 2665 2666static u32 gxbb_gen_clk_parents_val_table[] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, }; 2667static const struct clk_parent_data gxbb_gen_clk_parents[] = { 2668 { .fw_name = "xtal", }, 2669 { .hw = &gxbb_vdec_1.hw }, 2670 { .hw = &gxbb_vdec_hevc.hw }, 2671 { .hw = &gxbb_mpll0.hw }, 2672 { .hw = &gxbb_mpll1.hw }, 2673 { .hw = &gxbb_mpll2.hw }, 2674 { .hw = &gxbb_fclk_div4.hw }, 2675 { .hw = &gxbb_fclk_div3.hw }, 2676 { .hw = &gxbb_fclk_div5.hw }, 2677 { .hw = &gxbb_fclk_div7.hw }, 2678 { .hw = &gxbb_gp0_pll.hw }, 2679}; 2680 2681static struct clk_regmap gxbb_gen_clk_sel = { 2682 .data = &(struct clk_regmap_mux_data){ 2683 .offset = HHI_GEN_CLK_CNTL, 2684 .mask = 0xf, 2685 .shift = 12, 2686 .table = gxbb_gen_clk_parents_val_table, 2687 }, 2688 .hw.init = &(struct clk_init_data){ 2689 .name = "gen_clk_sel", 2690 .ops = &clk_regmap_mux_ops, 2691 /* 2692 * bits 15:12 selects from 14 possible parents: 2693 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 2694 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4, 2695 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 2696 */ 2697 .parent_data = gxbb_gen_clk_parents, 2698 .num_parents = ARRAY_SIZE(gxbb_gen_clk_parents), 2699 }, 2700}; 2701 2702static struct clk_regmap gxbb_gen_clk_div = { 2703 .data = &(struct clk_regmap_div_data){ 2704 .offset = HHI_GEN_CLK_CNTL, 2705 .shift = 0, 2706 .width = 11, 2707 }, 2708 .hw.init = &(struct clk_init_data){ 2709 .name = "gen_clk_div", 2710 .ops = &clk_regmap_divider_ops, 2711 .parent_hws = (const struct clk_hw *[]) { 2712 &gxbb_gen_clk_sel.hw 2713 }, 2714 .num_parents = 1, 2715 .flags = CLK_SET_RATE_PARENT, 2716 }, 2717}; 2718 2719static struct clk_regmap gxbb_gen_clk = { 2720 .data = &(struct clk_regmap_gate_data){ 2721 .offset = HHI_GEN_CLK_CNTL, 2722 .bit_idx = 7, 2723 }, 2724 .hw.init = &(struct clk_init_data){ 2725 .name = "gen_clk", 2726 .ops = &clk_regmap_gate_ops, 2727 .parent_hws = (const struct clk_hw *[]) { 2728 &gxbb_gen_clk_div.hw 2729 }, 2730 .num_parents = 1, 2731 .flags = CLK_SET_RATE_PARENT, 2732 }, 2733}; 2734 2735static const struct clk_parent_data gxbb_pclk_parents = { .hw = &gxbb_clk81.hw }; 2736 2737#define GXBB_PCLK(_name, _reg, _bit, _flags) \ 2738 MESON_PCLK(_name, _reg, _bit, &gxbb_pclk_parents, _flags) 2739 2740/* 2741 * Everything Else (EE) domain gates 2742 * 2743 * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons 2744 * Users are encouraged to test without it and submit changes to: 2745 * - remove the flag if not necessary 2746 * - replace the flag with something more adequate, such as CLK_IS_CRITICAL, 2747 * if appropriate. 2748 * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable 2749 * for a particular clock. 2750 */ 2751static GXBB_PCLK(gxbb_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED); 2752static GXBB_PCLK(gxbb_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED); 2753static GXBB_PCLK(gxbb_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED); 2754static GXBB_PCLK(gxbb_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED); 2755static GXBB_PCLK(gxbb_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED); 2756static GXBB_PCLK(gxbb_spicc, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED); 2757static GXBB_PCLK(gxbb_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED); 2758static GXBB_PCLK(gxbb_sana, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSED); 2759static GXBB_PCLK(gxbb_smart_card, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UNUSED); 2760static GXBB_PCLK(gxbb_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED); 2761static GXBB_PCLK(gxbb_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED); 2762static GXBB_PCLK(gxbb_sdhc, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED); 2763static GXBB_PCLK(gxbb_stream, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED); 2764static GXBB_PCLK(gxbb_async_fifo, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UNUSED); 2765static GXBB_PCLK(gxbb_sdio, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED); 2766static GXBB_PCLK(gxbb_abuf, HHI_GCLK_MPEG0, 18, CLK_IGNORE_UNUSED); 2767static GXBB_PCLK(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED); 2768static GXBB_PCLK(gxbb_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED); 2769static GXBB_PCLK(gxbb_emmc_a, HHI_GCLK_MPEG0, 24, CLK_IGNORE_UNUSED); 2770static GXBB_PCLK(gxbb_emmc_b, HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED); 2771static GXBB_PCLK(gxbb_emmc_c, HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED); 2772static GXBB_PCLK(gxl_acodec, HHI_GCLK_MPEG0, 28, CLK_IGNORE_UNUSED); 2773static GXBB_PCLK(gxbb_spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED); 2774 2775static GXBB_PCLK(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2, CLK_IGNORE_UNUSED); 2776static GXBB_PCLK(gxbb_eth, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED); 2777static GXBB_PCLK(gxbb_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED); 2778static GXBB_PCLK(gxbb_blkmv, HHI_GCLK_MPEG1, 14, CLK_IGNORE_UNUSED); 2779static GXBB_PCLK(gxbb_aiu, HHI_GCLK_MPEG1, 15, CLK_IGNORE_UNUSED); 2780static GXBB_PCLK(gxbb_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED); 2781static GXBB_PCLK(gxbb_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED); 2782static GXBB_PCLK(gxbb_usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED); 2783static GXBB_PCLK(gxbb_usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED); 2784static GXBB_PCLK(gxbb_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED); 2785static GXBB_PCLK(gxbb_nand, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED); 2786static GXBB_PCLK(gxbb_dos_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UNUSED); 2787static GXBB_PCLK(gxbb_usb, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED); 2788static GXBB_PCLK(gxbb_vdin1, HHI_GCLK_MPEG1, 28, CLK_IGNORE_UNUSED); 2789static GXBB_PCLK(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED); 2790static GXBB_PCLK(gxbb_efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED); 2791static GXBB_PCLK(gxbb_boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUSED); 2792 2793static GXBB_PCLK(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED); 2794static GXBB_PCLK(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED); 2795static GXBB_PCLK(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3, CLK_IGNORE_UNUSED); 2796static GXBB_PCLK(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNUSED); 2797static GXBB_PCLK(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED); 2798static GXBB_PCLK(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9, CLK_IGNORE_UNUSED); 2799static GXBB_PCLK(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED); 2800static GXBB_PCLK(gxbb_dvin, HHI_GCLK_MPEG2, 12, CLK_IGNORE_UNUSED); 2801static GXBB_PCLK(gxbb_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED); 2802static GXBB_PCLK(gxbb_sar_adc, HHI_GCLK_MPEG2, 22, CLK_IGNORE_UNUSED); 2803static GXBB_PCLK(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED); 2804static GXBB_PCLK(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_IGNORE_UNUSED); 2805static GXBB_PCLK(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUSED); 2806 2807static GXBB_PCLK(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_UNUSED); 2808static GXBB_PCLK(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_UNUSED); 2809static GXBB_PCLK(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_UNUSED); 2810static GXBB_PCLK(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_UNUSED); 2811static GXBB_PCLK(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8, CLK_IGNORE_UNUSED); 2812static GXBB_PCLK(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9, CLK_IGNORE_UNUSED); 2813static GXBB_PCLK(gxbb_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSED); 2814static GXBB_PCLK(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UNUSED); 2815static GXBB_PCLK(gxbb_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UNUSED); 2816static GXBB_PCLK(gxbb_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSED); 2817static GXBB_PCLK(gxbb_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED); 2818static GXBB_PCLK(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22, CLK_IGNORE_UNUSED); 2819static GXBB_PCLK(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24, CLK_IGNORE_UNUSED); 2820static GXBB_PCLK(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UNUSED); 2821static GXBB_PCLK(gxbb_vclk_other, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED); 2822static GXBB_PCLK(gxbb_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED); 2823 2824/* Always On (AO) domain gates */ 2825 2826static GXBB_PCLK(gxbb_ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSED); 2827static GXBB_PCLK(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED); 2828static GXBB_PCLK(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED); 2829static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED); 2830static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED); 2831 2832/* AIU gates */ 2833static const struct clk_parent_data gxbb_aiu_glue_parents = { .hw = &gxbb_aiu.hw }; 2834static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu_glue_parents, CLK_IGNORE_UNUSED); 2835 2836static const struct clk_parent_data gxbb_aiu_pclk_parents = { .hw = &gxbb_aiu_glue.hw }; 2837#define GXBB_AIU_PCLK(_name, _bit, _flags) \ 2838 MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &gxbb_aiu_pclk_parents, _flags) 2839 2840static GXBB_AIU_PCLK(gxbb_iec958, 7, CLK_IGNORE_UNUSED); 2841static GXBB_AIU_PCLK(gxbb_i2s_out, 8, CLK_IGNORE_UNUSED); 2842static GXBB_AIU_PCLK(gxbb_amclk, 9, CLK_IGNORE_UNUSED); 2843static GXBB_AIU_PCLK(gxbb_aififo2, 10, CLK_IGNORE_UNUSED); 2844static GXBB_AIU_PCLK(gxbb_mixer, 11, CLK_IGNORE_UNUSED); 2845static GXBB_AIU_PCLK(gxbb_mixer_iface, 12, CLK_IGNORE_UNUSED); 2846static GXBB_AIU_PCLK(gxbb_adc, 13, CLK_IGNORE_UNUSED); 2847 2848/* Array of all clocks provided by this provider */ 2849 2850static struct clk_hw *gxbb_hw_clks[] = { 2851 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 2852 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 2853 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 2854 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 2855 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 2856 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 2857 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 2858 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 2859 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 2860 [CLKID_MPEG_SEL] = &gxbb_clk81_sel.hw, 2861 [CLKID_MPEG_DIV] = &gxbb_clk81_div.hw, 2862 [CLKID_CLK81] = &gxbb_clk81.hw, 2863 [CLKID_MPLL0] = &gxbb_mpll0.hw, 2864 [CLKID_MPLL1] = &gxbb_mpll1.hw, 2865 [CLKID_MPLL2] = &gxbb_mpll2.hw, 2866 [CLKID_DDR] = &gxbb_ddr.hw, 2867 [CLKID_DOS] = &gxbb_dos.hw, 2868 [CLKID_ISA] = &gxbb_isa.hw, 2869 [CLKID_PL301] = &gxbb_pl301.hw, 2870 [CLKID_PERIPHS] = &gxbb_periphs.hw, 2871 [CLKID_SPICC] = &gxbb_spicc.hw, 2872 [CLKID_I2C] = &gxbb_i2c.hw, 2873 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 2874 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 2875 [CLKID_RNG0] = &gxbb_rng0.hw, 2876 [CLKID_UART0] = &gxbb_uart0.hw, 2877 [CLKID_SDHC] = &gxbb_sdhc.hw, 2878 [CLKID_STREAM] = &gxbb_stream.hw, 2879 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 2880 [CLKID_SDIO] = &gxbb_sdio.hw, 2881 [CLKID_ABUF] = &gxbb_abuf.hw, 2882 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 2883 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 2884 [CLKID_SPI] = &gxbb_spi.hw, 2885 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 2886 [CLKID_ETH] = &gxbb_eth.hw, 2887 [CLKID_DEMUX] = &gxbb_demux.hw, 2888 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 2889 [CLKID_IEC958] = &gxbb_iec958.hw, 2890 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 2891 [CLKID_AMCLK] = &gxbb_amclk.hw, 2892 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 2893 [CLKID_MIXER] = &gxbb_mixer.hw, 2894 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 2895 [CLKID_ADC] = &gxbb_adc.hw, 2896 [CLKID_BLKMV] = &gxbb_blkmv.hw, 2897 [CLKID_AIU] = &gxbb_aiu.hw, 2898 [CLKID_UART1] = &gxbb_uart1.hw, 2899 [CLKID_G2D] = &gxbb_g2d.hw, 2900 [CLKID_USB0] = &gxbb_usb0.hw, 2901 [CLKID_USB1] = &gxbb_usb1.hw, 2902 [CLKID_RESET] = &gxbb_reset.hw, 2903 [CLKID_NAND] = &gxbb_nand.hw, 2904 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 2905 [CLKID_USB] = &gxbb_usb.hw, 2906 [CLKID_VDIN1] = &gxbb_vdin1.hw, 2907 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 2908 [CLKID_EFUSE] = &gxbb_efuse.hw, 2909 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 2910 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 2911 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 2912 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 2913 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 2914 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 2915 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 2916 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 2917 [CLKID_DVIN] = &gxbb_dvin.hw, 2918 [CLKID_UART2] = &gxbb_uart2.hw, 2919 [CLKID_SANA] = &gxbb_sana.hw, 2920 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 2921 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 2922 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 2923 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 2924 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 2925 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 2926 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 2927 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 2928 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 2929 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 2930 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 2931 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 2932 [CLKID_ENC480P] = &gxbb_enc480p.hw, 2933 [CLKID_RNG1] = &gxbb_rng1.hw, 2934 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 2935 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 2936 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 2937 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 2938 [CLKID_EDP] = &gxbb_edp.hw, 2939 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 2940 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 2941 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 2942 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 2943 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 2944 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 2945 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 2946 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 2947 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 2948 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 2949 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 2950 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 2951 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 2952 [CLKID_MALI_0] = &gxbb_mali_0.hw, 2953 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 2954 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 2955 [CLKID_MALI_1] = &gxbb_mali_1.hw, 2956 [CLKID_MALI] = &gxbb_mali.hw, 2957 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 2958 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 2959 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 2960 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 2961 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 2962 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 2963 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 2964 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 2965 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 2966 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 2967 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 2968 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 2969 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 2970 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 2971 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 2972 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 2973 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 2974 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 2975 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 2976 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 2977 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 2978 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 2979 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 2980 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 2981 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 2982 [CLKID_VPU] = &gxbb_vpu.hw, 2983 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 2984 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 2985 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 2986 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 2987 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 2988 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 2989 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 2990 [CLKID_VAPB] = &gxbb_vapb.hw, 2991 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw, 2992 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 2993 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 2994 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 2995 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 2996 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 2997 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 2998 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 2999 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 3000 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 3001 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 3002 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 3003 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 3004 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 3005 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 3006 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 3007 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 3008 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 3009 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 3010 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 3011 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw, 3012 [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw, 3013 [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw, 3014 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 3015 [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw, 3016 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 3017 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 3018 [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 3019 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 3020 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 3021 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 3022 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 3023 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 3024 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 3025 [CLKID_VCLK] = &gxbb_vclk.hw, 3026 [CLKID_VCLK2] = &gxbb_vclk2.hw, 3027 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 3028 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 3029 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 3030 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 3031 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 3032 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 3033 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 3034 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 3035 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 3036 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 3037 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 3038 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 3039 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 3040 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 3041 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 3042 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 3043 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 3044 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 3045 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 3046 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 3047 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 3048 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 3049 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 3050 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 3051 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 3052 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 3053 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 3054 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 3055 [CLKID_HDMI] = &gxbb_hdmi.hw, 3056}; 3057 3058static struct clk_hw *gxl_hw_clks[] = { 3059 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 3060 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, 3061 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 3062 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 3063 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 3064 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 3065 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 3066 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 3067 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 3068 [CLKID_MPEG_SEL] = &gxbb_clk81_sel.hw, 3069 [CLKID_MPEG_DIV] = &gxbb_clk81_div.hw, 3070 [CLKID_CLK81] = &gxbb_clk81.hw, 3071 [CLKID_MPLL0] = &gxbb_mpll0.hw, 3072 [CLKID_MPLL1] = &gxbb_mpll1.hw, 3073 [CLKID_MPLL2] = &gxbb_mpll2.hw, 3074 [CLKID_DDR] = &gxbb_ddr.hw, 3075 [CLKID_DOS] = &gxbb_dos.hw, 3076 [CLKID_ISA] = &gxbb_isa.hw, 3077 [CLKID_PL301] = &gxbb_pl301.hw, 3078 [CLKID_PERIPHS] = &gxbb_periphs.hw, 3079 [CLKID_SPICC] = &gxbb_spicc.hw, 3080 [CLKID_I2C] = &gxbb_i2c.hw, 3081 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 3082 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 3083 [CLKID_RNG0] = &gxbb_rng0.hw, 3084 [CLKID_UART0] = &gxbb_uart0.hw, 3085 [CLKID_SDHC] = &gxbb_sdhc.hw, 3086 [CLKID_STREAM] = &gxbb_stream.hw, 3087 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 3088 [CLKID_SDIO] = &gxbb_sdio.hw, 3089 [CLKID_ABUF] = &gxbb_abuf.hw, 3090 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 3091 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 3092 [CLKID_SPI] = &gxbb_spi.hw, 3093 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 3094 [CLKID_ETH] = &gxbb_eth.hw, 3095 [CLKID_DEMUX] = &gxbb_demux.hw, 3096 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 3097 [CLKID_IEC958] = &gxbb_iec958.hw, 3098 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 3099 [CLKID_AMCLK] = &gxbb_amclk.hw, 3100 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 3101 [CLKID_MIXER] = &gxbb_mixer.hw, 3102 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 3103 [CLKID_ADC] = &gxbb_adc.hw, 3104 [CLKID_BLKMV] = &gxbb_blkmv.hw, 3105 [CLKID_AIU] = &gxbb_aiu.hw, 3106 [CLKID_UART1] = &gxbb_uart1.hw, 3107 [CLKID_G2D] = &gxbb_g2d.hw, 3108 [CLKID_USB0] = &gxbb_usb0.hw, 3109 [CLKID_USB1] = &gxbb_usb1.hw, 3110 [CLKID_RESET] = &gxbb_reset.hw, 3111 [CLKID_NAND] = &gxbb_nand.hw, 3112 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 3113 [CLKID_USB] = &gxbb_usb.hw, 3114 [CLKID_VDIN1] = &gxbb_vdin1.hw, 3115 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 3116 [CLKID_EFUSE] = &gxbb_efuse.hw, 3117 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 3118 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 3119 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 3120 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 3121 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 3122 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 3123 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 3124 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 3125 [CLKID_DVIN] = &gxbb_dvin.hw, 3126 [CLKID_UART2] = &gxbb_uart2.hw, 3127 [CLKID_SANA] = &gxbb_sana.hw, 3128 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 3129 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 3130 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 3131 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 3132 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 3133 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 3134 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 3135 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 3136 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 3137 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 3138 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 3139 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 3140 [CLKID_ENC480P] = &gxbb_enc480p.hw, 3141 [CLKID_RNG1] = &gxbb_rng1.hw, 3142 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 3143 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 3144 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 3145 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 3146 [CLKID_EDP] = &gxbb_edp.hw, 3147 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 3148 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 3149 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 3150 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 3151 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 3152 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 3153 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 3154 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 3155 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 3156 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 3157 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 3158 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 3159 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 3160 [CLKID_MALI_0] = &gxbb_mali_0.hw, 3161 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 3162 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 3163 [CLKID_MALI_1] = &gxbb_mali_1.hw, 3164 [CLKID_MALI] = &gxbb_mali.hw, 3165 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 3166 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 3167 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 3168 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 3169 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 3170 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 3171 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 3172 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 3173 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 3174 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 3175 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 3176 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 3177 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 3178 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 3179 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 3180 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 3181 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 3182 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 3183 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 3184 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 3185 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 3186 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 3187 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 3188 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 3189 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 3190 [CLKID_VPU] = &gxbb_vpu.hw, 3191 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 3192 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 3193 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 3194 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 3195 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 3196 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 3197 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 3198 [CLKID_VAPB] = &gxbb_vapb.hw, 3199 [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw, 3200 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 3201 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 3202 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 3203 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 3204 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 3205 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 3206 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 3207 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 3208 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 3209 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 3210 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 3211 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 3212 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 3213 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 3214 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 3215 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 3216 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 3217 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 3218 [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw, 3219 [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw, 3220 [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw, 3221 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 3222 [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw, 3223 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 3224 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 3225 [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 3226 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 3227 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 3228 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 3229 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 3230 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 3231 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 3232 [CLKID_VCLK] = &gxbb_vclk.hw, 3233 [CLKID_VCLK2] = &gxbb_vclk2.hw, 3234 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 3235 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 3236 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 3237 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 3238 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 3239 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 3240 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 3241 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 3242 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 3243 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 3244 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 3245 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 3246 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 3247 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 3248 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 3249 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 3250 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 3251 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 3252 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 3253 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 3254 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 3255 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 3256 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 3257 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 3258 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 3259 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 3260 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 3261 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 3262 [CLKID_HDMI] = &gxbb_hdmi.hw, 3263 [CLKID_ACODEC] = &gxl_acodec.hw, 3264}; 3265 3266static const struct meson_clkc_data gxbb_clkc_data = { 3267 .hw_clks = { 3268 .hws = gxbb_hw_clks, 3269 .num = ARRAY_SIZE(gxbb_hw_clks), 3270 }, 3271}; 3272 3273static const struct meson_clkc_data gxl_clkc_data = { 3274 .hw_clks = { 3275 .hws = gxl_hw_clks, 3276 .num = ARRAY_SIZE(gxl_hw_clks), 3277 }, 3278}; 3279 3280static const struct of_device_id gxbb_clkc_match_table[] = { 3281 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 3282 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 3283 {}, 3284}; 3285MODULE_DEVICE_TABLE(of, gxbb_clkc_match_table); 3286 3287static struct platform_driver gxbb_clkc_driver = { 3288 .probe = meson_clkc_syscon_probe, 3289 .driver = { 3290 .name = "gxbb-clkc", 3291 .of_match_table = gxbb_clkc_match_table, 3292 }, 3293}; 3294module_platform_driver(gxbb_clkc_driver); 3295 3296MODULE_DESCRIPTION("Amlogic GXBB Main Clock Controller driver"); 3297MODULE_LICENSE("GPL"); 3298MODULE_IMPORT_NS("CLK_MESON");
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