c3-peripherals.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Amlogic C3 Peripherals Clock Controller Driver
   4 *
   5 * Copyright (c) 2023 Amlogic, inc.
   6 * Author: Chuan Liu <chuan.liu@amlogic.com>
   7 */
   8
   9#include <linux/clk-provider.h>
  10#include <linux/platform_device.h>
  11#include "clk-regmap.h"
  12#include "clk-dualdiv.h"
  13#include "meson-clkc-utils.h"
  14#include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
  15
  16#define RTC_BY_OSCIN_CTRL0			0x8
  17#define RTC_BY_OSCIN_CTRL1			0xc
  18#define RTC_CTRL				0x10
  19#define SYS_CLK_EN0_REG0			0x44
  20#define SYS_CLK_EN0_REG1			0x48
  21#define SYS_CLK_EN0_REG2			0x4c
  22#define CLK12_24_CTRL				0xa8
  23#define AXI_CLK_EN0				0xac
  24#define VDIN_MEAS_CLK_CTRL			0xf8
  25#define VAPB_CLK_CTRL				0xfc
  26#define MIPIDSI_PHY_CLK_CTRL			0x104
  27#define GE2D_CLK_CTRL				0x10c
  28#define ISP0_CLK_CTRL				0x110
  29#define DEWARPA_CLK_CTRL			0x114
  30#define VOUTENC_CLK_CTRL			0x118
  31#define VDEC_CLK_CTRL				0x140
  32#define VDEC3_CLK_CTRL				0x148
  33#define TS_CLK_CTRL				0x158
  34#define ETH_CLK_CTRL				0x164
  35#define NAND_CLK_CTRL				0x168
  36#define SD_EMMC_CLK_CTRL			0x16c
  37#define SPICC_CLK_CTRL				0x174
  38#define GEN_CLK_CTRL				0x178
  39#define SAR_CLK_CTRL0				0x17c
  40#define PWM_CLK_AB_CTRL				0x180
  41#define PWM_CLK_CD_CTRL				0x184
  42#define PWM_CLK_EF_CTRL				0x188
  43#define PWM_CLK_GH_CTRL				0x18c
  44#define PWM_CLK_IJ_CTRL				0x190
  45#define PWM_CLK_KL_CTRL				0x194
  46#define PWM_CLK_MN_CTRL				0x198
  47#define VC9000E_CLK_CTRL			0x19c
  48#define SPIFC_CLK_CTRL				0x1a0
  49#define NNA_CLK_CTRL				0x220
  50
  51#define C3_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
  52	MESON_COMP_SEL(c3_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
  53
  54#define C3_COMP_DIV(_name, _reg, _shift, _width) \
  55	MESON_COMP_DIV(c3_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
  56
  57#define C3_COMP_GATE(_name, _reg, _bit) \
  58	MESON_COMP_GATE(c3_, _name, _reg, _bit, CLK_SET_RATE_PARENT)
  59
  60static struct clk_regmap c3_rtc_xtal_clkin = {
  61	.data = &(struct clk_regmap_gate_data) {
  62		.offset = RTC_BY_OSCIN_CTRL0,
  63		.bit_idx = 31,
  64	},
  65	.hw.init = &(struct clk_init_data) {
  66		.name = "rtc_xtal_clkin",
  67		.ops = &clk_regmap_gate_ops,
  68		.parent_data = &(const struct clk_parent_data) {
  69			.fw_name = "oscin",
  70		},
  71		.num_parents = 1,
  72	},
  73};
  74
  75static const struct meson_clk_dualdiv_param c3_rtc_32k_div_table[] = {
  76	{ 733, 732, 8, 11, 1 },
  77	{ /* sentinel */ }
  78};
  79
  80static struct clk_regmap c3_rtc_32k_div = {
  81	.data = &(struct meson_clk_dualdiv_data) {
  82		.n1 = {
  83			.reg_off = RTC_BY_OSCIN_CTRL0,
  84			.shift   = 0,
  85			.width   = 12,
  86		},
  87		.n2 = {
  88			.reg_off = RTC_BY_OSCIN_CTRL0,
  89			.shift   = 12,
  90			.width   = 12,
  91		},
  92		.m1 = {
  93			.reg_off = RTC_BY_OSCIN_CTRL1,
  94			.shift   = 0,
  95			.width   = 12,
  96		},
  97		.m2 = {
  98			.reg_off = RTC_BY_OSCIN_CTRL1,
  99			.shift   = 12,
 100			.width   = 12,
 101		},
 102		.dual = {
 103			.reg_off = RTC_BY_OSCIN_CTRL0,
 104			.shift   = 28,
 105			.width   = 1,
 106		},
 107		.table = c3_rtc_32k_div_table,
 108	},
 109	.hw.init = &(struct clk_init_data) {
 110		.name = "rtc_32k_div",
 111		.ops = &meson_clk_dualdiv_ops,
 112		.parent_hws = (const struct clk_hw *[]) {
 113			&c3_rtc_xtal_clkin.hw
 114		},
 115		.num_parents = 1,
 116	},
 117};
 118
 119static const struct clk_parent_data c3_rtc_32k_parents[] = {
 120	{ .hw = &c3_rtc_32k_div.hw },
 121	{ .hw = &c3_rtc_xtal_clkin.hw }
 122};
 123
 124static struct clk_regmap c3_rtc_32k_sel = {
 125	.data = &(struct clk_regmap_mux_data) {
 126		.offset = RTC_BY_OSCIN_CTRL1,
 127		.mask = 0x1,
 128		.shift = 24,
 129	},
 130	.hw.init = &(struct clk_init_data) {
 131		.name = "rtc_32k_sel",
 132		.ops = &clk_regmap_mux_ops,
 133		.parent_data = c3_rtc_32k_parents,
 134		.num_parents = ARRAY_SIZE(c3_rtc_32k_parents),
 135		.flags = CLK_SET_RATE_PARENT,
 136	},
 137};
 138
 139static struct clk_regmap c3_rtc_32k = {
 140	.data = &(struct clk_regmap_gate_data) {
 141		.offset = RTC_BY_OSCIN_CTRL0,
 142		.bit_idx = 30,
 143	},
 144	.hw.init = &(struct clk_init_data) {
 145		.name = "rtc_32k",
 146		.ops = &clk_regmap_gate_ops,
 147		.parent_hws = (const struct clk_hw *[]) {
 148			&c3_rtc_32k_sel.hw
 149		},
 150		.num_parents = 1,
 151		.flags = CLK_SET_RATE_PARENT,
 152	},
 153};
 154
 155static const struct clk_parent_data c3_rtc_clk_parents[] = {
 156	{ .fw_name = "oscin" },
 157	{ .hw = &c3_rtc_32k.hw },
 158	{ .fw_name = "pad_osc" }
 159};
 160
 161static struct clk_regmap c3_rtc_clk = {
 162	.data = &(struct clk_regmap_mux_data) {
 163		.offset = RTC_CTRL,
 164		.mask = 0x3,
 165		.shift = 0,
 166	},
 167	.hw.init = &(struct clk_init_data) {
 168		.name = "rtc_clk",
 169		.ops = &clk_regmap_mux_ops,
 170		.parent_data = c3_rtc_clk_parents,
 171		.num_parents = ARRAY_SIZE(c3_rtc_clk_parents),
 172		.flags = CLK_SET_RATE_PARENT,
 173	},
 174};
 175
 176static const struct clk_parent_data c3_sys_pclk_parents = { .fw_name = "sysclk" };
 177
 178#define C3_SYS_PCLK(_name, _reg, _bit, _flags) \
 179	MESON_PCLK(c3_##_name, _reg, _bit, &c3_sys_pclk_parents, _flags)
 180
 181#define C3_SYS_PCLK_RO(_name, _reg, _bit) \
 182	MESON_PCLK_RO(c3_##_name, _reg, _bit, &c3_sys_pclk_parents, 0)
 183
 184static C3_SYS_PCLK(sys_reset_ctrl,	SYS_CLK_EN0_REG0, 1, 0);
 185static C3_SYS_PCLK(sys_pwr_ctrl,	SYS_CLK_EN0_REG0, 3, 0);
 186static C3_SYS_PCLK(sys_pad_ctrl,	SYS_CLK_EN0_REG0, 4, 0);
 187static C3_SYS_PCLK(sys_ctrl,		SYS_CLK_EN0_REG0, 5, 0);
 188static C3_SYS_PCLK(sys_ts_pll,		SYS_CLK_EN0_REG0, 6, 0);
 189
 190/*
 191 * NOTE: sys_dev_arb provides the clock to the ETH and SPICC arbiters that
 192 * access the AXI bus.
 193 */
 194static C3_SYS_PCLK(sys_dev_arb,		SYS_CLK_EN0_REG0, 7, 0);
 195
 196/*
 197 * FIXME: sys_mmc_pclk provides the clock for the DDR PHY, DDR will only be
 198 * initialized in bl2, and this clock should not be touched in linux.
 199 */
 200static C3_SYS_PCLK_RO(sys_mmc_pclk,	SYS_CLK_EN0_REG0, 8);
 201
 202/*
 203 * NOTE: sys_cpu_ctrl provides the clock for CPU controller. After clock is
 204 * disabled, cpu_clk and other key CPU-related configurations cannot take effect.
 205 */
 206static C3_SYS_PCLK(sys_cpu_ctrl,	SYS_CLK_EN0_REG0, 11, CLK_IS_CRITICAL);
 207static C3_SYS_PCLK(sys_jtag_ctrl,	SYS_CLK_EN0_REG0, 12, 0);
 208static C3_SYS_PCLK(sys_ir_ctrl,		SYS_CLK_EN0_REG0, 13, 0);
 209
 210/*
 211 * NOTE: sys_irq_ctrl provides the clock for IRQ controller. The IRQ controller
 212 * collects and distributes the interrupt signal to the GIC, PWR_CTRL, and
 213 * AOCPU. If the clock is disabled, interrupt-related functions will occurs an
 214 * exception.
 215 */
 216static C3_SYS_PCLK(sys_irq_ctrl,	SYS_CLK_EN0_REG0, 14, CLK_IS_CRITICAL);
 217static C3_SYS_PCLK(sys_msr_clk,		SYS_CLK_EN0_REG0, 15, 0);
 218static C3_SYS_PCLK(sys_rom,		SYS_CLK_EN0_REG0, 16, 0);
 219static C3_SYS_PCLK(sys_uart_f,		SYS_CLK_EN0_REG0, 17, 0);
 220static C3_SYS_PCLK(sys_cpu_apb,		SYS_CLK_EN0_REG0, 18, 0);
 221static C3_SYS_PCLK(sys_rsa,		SYS_CLK_EN0_REG0, 19, 0);
 222static C3_SYS_PCLK(sys_sar_adc,		SYS_CLK_EN0_REG0, 20, 0);
 223static C3_SYS_PCLK(sys_startup,		SYS_CLK_EN0_REG0, 21, 0);
 224static C3_SYS_PCLK(sys_secure,		SYS_CLK_EN0_REG0, 22, 0);
 225static C3_SYS_PCLK(sys_spifc,		SYS_CLK_EN0_REG0, 23, 0);
 226static C3_SYS_PCLK(sys_nna,		SYS_CLK_EN0_REG0, 25, 0);
 227static C3_SYS_PCLK(sys_eth_mac,		SYS_CLK_EN0_REG0, 26, 0);
 228
 229/*
 230 * FIXME: sys_gic provides the clock for GIC(Generic Interrupt Controller).
 231 * After clock is disabled, The GIC cannot work properly. At present, the driver
 232 * used by our GIC is the public driver in kernel, and there is no management
 233 * clock in the driver.
 234 */
 235static C3_SYS_PCLK(sys_gic,		SYS_CLK_EN0_REG0, 27, CLK_IS_CRITICAL);
 236static C3_SYS_PCLK(sys_rama,		SYS_CLK_EN0_REG0, 28, 0);
 237
 238/*
 239 * NOTE: sys_big_nic provides the clock to the control bus of the NIC(Network
 240 * Interface Controller) between multiple devices(CPU, DDR, RAM, ROM, GIC,
 241 * SPIFC, CAPU, JTAG, EMMC, SDIO, sec_top, USB, Audio, ETH, SPICC) in the
 242 * system. After clock is disabled, The NIC cannot work.
 243 */
 244static C3_SYS_PCLK(sys_big_nic,		SYS_CLK_EN0_REG0, 29, CLK_IS_CRITICAL);
 245static C3_SYS_PCLK(sys_ramb,		SYS_CLK_EN0_REG0, 30, 0);
 246static C3_SYS_PCLK(sys_audio_pclk,	SYS_CLK_EN0_REG0, 31, 0);
 247static C3_SYS_PCLK(sys_pwm_kl,		SYS_CLK_EN0_REG1, 0, 0);
 248static C3_SYS_PCLK(sys_pwm_ij,		SYS_CLK_EN0_REG1, 1, 0);
 249static C3_SYS_PCLK(sys_usb,		SYS_CLK_EN0_REG1, 2, 0);
 250static C3_SYS_PCLK(sys_sd_emmc_a,	SYS_CLK_EN0_REG1, 3, 0);
 251static C3_SYS_PCLK(sys_sd_emmc_c,	SYS_CLK_EN0_REG1, 4, 0);
 252static C3_SYS_PCLK(sys_pwm_ab,		SYS_CLK_EN0_REG1, 5, 0);
 253static C3_SYS_PCLK(sys_pwm_cd,		SYS_CLK_EN0_REG1, 6, 0);
 254static C3_SYS_PCLK(sys_pwm_ef,		SYS_CLK_EN0_REG1, 7, 0);
 255static C3_SYS_PCLK(sys_pwm_gh,		SYS_CLK_EN0_REG1, 8, 0);
 256static C3_SYS_PCLK(sys_spicc_1,		SYS_CLK_EN0_REG1, 9, 0);
 257static C3_SYS_PCLK(sys_spicc_0,		SYS_CLK_EN0_REG1, 10, 0);
 258static C3_SYS_PCLK(sys_uart_a,		SYS_CLK_EN0_REG1, 11, 0);
 259static C3_SYS_PCLK(sys_uart_b,		SYS_CLK_EN0_REG1, 12, 0);
 260static C3_SYS_PCLK(sys_uart_c,		SYS_CLK_EN0_REG1, 13, 0);
 261static C3_SYS_PCLK(sys_uart_d,		SYS_CLK_EN0_REG1, 14, 0);
 262static C3_SYS_PCLK(sys_uart_e,		SYS_CLK_EN0_REG1, 15, 0);
 263static C3_SYS_PCLK(sys_i2c_m_a,		SYS_CLK_EN0_REG1, 16, 0);
 264static C3_SYS_PCLK(sys_i2c_m_b,		SYS_CLK_EN0_REG1, 17, 0);
 265static C3_SYS_PCLK(sys_i2c_m_c,		SYS_CLK_EN0_REG1, 18, 0);
 266static C3_SYS_PCLK(sys_i2c_m_d,		SYS_CLK_EN0_REG1, 19, 0);
 267static C3_SYS_PCLK(sys_i2c_s_a,		SYS_CLK_EN0_REG1, 20, 0);
 268static C3_SYS_PCLK(sys_rtc,		SYS_CLK_EN0_REG1, 21, 0);
 269static C3_SYS_PCLK(sys_ge2d,		SYS_CLK_EN0_REG1, 22, 0);
 270static C3_SYS_PCLK(sys_isp,		SYS_CLK_EN0_REG1, 23, 0);
 271static C3_SYS_PCLK(sys_gpv_isp_nic,	SYS_CLK_EN0_REG1, 24, 0);
 272static C3_SYS_PCLK(sys_gpv_cve_nic,	SYS_CLK_EN0_REG1, 25, 0);
 273static C3_SYS_PCLK(sys_mipi_dsi_host,	SYS_CLK_EN0_REG1, 26, 0);
 274static C3_SYS_PCLK(sys_mipi_dsi_phy,	SYS_CLK_EN0_REG1, 27, 0);
 275static C3_SYS_PCLK(sys_eth_phy,		SYS_CLK_EN0_REG1, 28, 0);
 276static C3_SYS_PCLK(sys_acodec,		SYS_CLK_EN0_REG1, 29, 0);
 277static C3_SYS_PCLK(sys_dwap,		SYS_CLK_EN0_REG1, 30, 0);
 278static C3_SYS_PCLK(sys_dos,		SYS_CLK_EN0_REG1, 31, 0);
 279static C3_SYS_PCLK(sys_cve,		SYS_CLK_EN0_REG2, 0, 0);
 280static C3_SYS_PCLK(sys_vout,		SYS_CLK_EN0_REG2, 1, 0);
 281static C3_SYS_PCLK(sys_vc9000e,		SYS_CLK_EN0_REG2, 2, 0);
 282static C3_SYS_PCLK(sys_pwm_mn,		SYS_CLK_EN0_REG2, 3, 0);
 283static C3_SYS_PCLK(sys_sd_emmc_b,	SYS_CLK_EN0_REG2, 4, 0);
 284
 285static const struct clk_parent_data c3_axi_pclk_parents = { .fw_name = "axiclk" };
 286
 287#define C3_AXI_PCLK(_name, _reg, _bit, _flags) \
 288	MESON_PCLK(c3_##_name, _reg, _bit, &c3_axi_pclk_parents, _flags)
 289
 290/*
 291 * NOTE: axi_sys_nic provides the clock to the AXI bus of the system NIC. After
 292 * clock is disabled, The NIC cannot work.
 293 */
 294static C3_AXI_PCLK(axi_sys_nic,		AXI_CLK_EN0, 2, CLK_IS_CRITICAL);
 295static C3_AXI_PCLK(axi_isp_nic,		AXI_CLK_EN0, 3, 0);
 296static C3_AXI_PCLK(axi_cve_nic,		AXI_CLK_EN0, 4, 0);
 297static C3_AXI_PCLK(axi_ramb,		AXI_CLK_EN0, 5, 0);
 298static C3_AXI_PCLK(axi_rama,		AXI_CLK_EN0, 6, 0);
 299
 300/*
 301 * NOTE: axi_cpu_dmc provides the clock to the AXI bus where the CPU accesses
 302 * the DDR. After clock is disabled, The CPU will not have access to the DDR.
 303 */
 304static C3_AXI_PCLK(axi_cpu_dmc,		AXI_CLK_EN0, 7, CLK_IS_CRITICAL);
 305static C3_AXI_PCLK(axi_nic,		AXI_CLK_EN0, 8, 0);
 306static C3_AXI_PCLK(axi_dma,		AXI_CLK_EN0, 9, 0);
 307
 308/*
 309 * NOTE: axi_mux_nic provides the clock to the NIC's AXI bus for NN(Neural
 310 * Network) and other devices(CPU, EMMC, SDIO, sec_top, USB, Audio, ETH, SPICC)
 311 * to access RAM space.
 312 */
 313static C3_AXI_PCLK(axi_mux_nic,		AXI_CLK_EN0, 10, 0);
 314static C3_AXI_PCLK(axi_cve,		AXI_CLK_EN0, 12, 0);
 315
 316/*
 317 * NOTE: axi_dev1_dmc provides the clock for the peripherals(EMMC, SDIO,
 318 * sec_top, USB, Audio, ETH, SPICC) to access the AXI bus of the DDR.
 319 */
 320static C3_AXI_PCLK(axi_dev1_dmc,	AXI_CLK_EN0, 13, 0);
 321static C3_AXI_PCLK(axi_dev0_dmc,	AXI_CLK_EN0, 14, 0);
 322static C3_AXI_PCLK(axi_dsp_dmc,		AXI_CLK_EN0, 15, 0);
 323
 324/*
 325 * clk_12_24m model
 326 *
 327 *          |------|     |-----| clk_12m_24m |-----|
 328 * xtal---->| gate |---->| div |------------>| pad |
 329 *          |------|     |-----|             |-----|
 330 */
 331static struct clk_regmap c3_clk_12_24m_in = {
 332	.data = &(struct clk_regmap_gate_data) {
 333		.offset = CLK12_24_CTRL,
 334		.bit_idx = 11,
 335	},
 336	.hw.init = &(struct clk_init_data) {
 337		.name = "clk_12_24m_in",
 338		.ops = &clk_regmap_gate_ops,
 339		.parent_data = &(const struct clk_parent_data) {
 340			.fw_name = "xtal_24m",
 341		},
 342		.num_parents = 1,
 343	},
 344};
 345
 346static struct clk_regmap c3_clk_12_24m = {
 347	.data = &(struct clk_regmap_div_data) {
 348		.offset = CLK12_24_CTRL,
 349		.shift = 10,
 350		.width = 1,
 351	},
 352	.hw.init = &(struct clk_init_data) {
 353		.name = "clk_12_24m",
 354		.ops = &clk_regmap_divider_ops,
 355		.parent_hws = (const struct clk_hw *[]) {
 356			&c3_clk_12_24m_in.hw
 357		},
 358		.num_parents = 1,
 359	},
 360};
 361
 362/* Fix me: set value 0 will div by 2 like value 1 */
 363static struct clk_regmap c3_fclk_25m_div = {
 364	.data = &(struct clk_regmap_div_data) {
 365		.offset = CLK12_24_CTRL,
 366		.shift = 0,
 367		.width = 8,
 368	},
 369	.hw.init = &(struct clk_init_data) {
 370		.name = "fclk_25m_div",
 371		.ops = &clk_regmap_divider_ops,
 372		.parent_data = &(const struct clk_parent_data) {
 373			.fw_name = "fix",
 374		},
 375		.num_parents = 1,
 376	},
 377};
 378
 379static struct clk_regmap c3_fclk_25m = {
 380	.data = &(struct clk_regmap_gate_data) {
 381		.offset = CLK12_24_CTRL,
 382		.bit_idx = 12,
 383	},
 384	.hw.init = &(struct clk_init_data) {
 385		.name = "fclk_25m",
 386		.ops = &clk_regmap_gate_ops,
 387		.parent_hws = (const struct clk_hw *[]) {
 388			&c3_fclk_25m_div.hw
 389		},
 390		.num_parents = 1,
 391		.flags = CLK_SET_RATE_PARENT,
 392	},
 393};
 394
 395/*
 396 * Channel 3(ddr_dpll_pt_clk) is manged by the DDR module; channel 12(cts_msr_clk)
 397 * is manged by clock measures module. Their hardware are out of clock tree.
 398 * Channel 4 8 9 10 11 13 14 15 16 18 are not connected.
 399 */
 400static u32 c3_gen_parents_val_table[] = { 0, 1, 2, 5, 6, 7, 17, 19, 20, 21, 22, 23, 24};
 401static const struct clk_parent_data c3_gen_parents[] = {
 402	{ .fw_name = "oscin" },
 403	{ .hw = &c3_rtc_clk.hw },
 404	{ .fw_name = "sysplldiv16" },
 405	{ .fw_name = "gp0" },
 406	{ .fw_name = "gp1" },
 407	{ .fw_name = "hifi" },
 408	{ .fw_name = "cpudiv16" },
 409	{ .fw_name = "fdiv2" },
 410	{ .fw_name = "fdiv2p5" },
 411	{ .fw_name = "fdiv3" },
 412	{ .fw_name = "fdiv4" },
 413	{ .fw_name = "fdiv5" },
 414	{ .fw_name = "fdiv7" }
 415};
 416
 417static struct clk_regmap c3_gen_sel = {
 418	.data = &(struct clk_regmap_mux_data) {
 419		.offset = GEN_CLK_CTRL,
 420		.mask = 0x1f,
 421		.shift = 12,
 422		.table = c3_gen_parents_val_table,
 423	},
 424	.hw.init = &(struct clk_init_data) {
 425		.name = "gen_sel",
 426		.ops = &clk_regmap_mux_ops,
 427		.parent_data = c3_gen_parents,
 428		.num_parents = ARRAY_SIZE(c3_gen_parents),
 429	},
 430};
 431
 432static struct clk_regmap c3_gen_div = {
 433	.data = &(struct clk_regmap_div_data) {
 434		.offset = GEN_CLK_CTRL,
 435		.shift = 0,
 436		.width = 11,
 437	},
 438	.hw.init = &(struct clk_init_data) {
 439		.name = "gen_div",
 440		.ops = &clk_regmap_divider_ops,
 441		.parent_hws = (const struct clk_hw *[]) {
 442			&c3_gen_sel.hw
 443		},
 444		.num_parents = 1,
 445		.flags = CLK_SET_RATE_PARENT,
 446	},
 447};
 448
 449static struct clk_regmap c3_gen = {
 450	.data = &(struct clk_regmap_gate_data) {
 451		.offset = GEN_CLK_CTRL,
 452		.bit_idx = 11,
 453	},
 454	.hw.init = &(struct clk_init_data) {
 455		.name = "gen",
 456		.ops = &clk_regmap_gate_ops,
 457		.parent_hws = (const struct clk_hw *[]) {
 458			&c3_gen_div.hw
 459		},
 460		.num_parents = 1,
 461		.flags = CLK_SET_RATE_PARENT,
 462	},
 463};
 464
 465static const struct clk_parent_data c3_saradc_parents[] = {
 466	{ .fw_name = "oscin" },
 467	{ .fw_name = "sysclk" }
 468};
 469
 470static C3_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x1, c3_saradc_parents);
 471static C3_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8);
 472static C3_COMP_GATE(saradc, SAR_CLK_CTRL0, 8);
 473
 474static const struct clk_parent_data c3_pwm_parents[] = {
 475	{ .fw_name = "oscin" },
 476	{ .fw_name = "gp1" },
 477	{ .fw_name = "fdiv4" },
 478	{ .fw_name = "fdiv3" }
 479};
 480
 481static C3_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, c3_pwm_parents);
 482static C3_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8);
 483static C3_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8);
 484
 485static C3_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, c3_pwm_parents);
 486static C3_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8);
 487static C3_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24);
 488
 489static C3_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, c3_pwm_parents);
 490static C3_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8);
 491static C3_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8);
 492
 493static C3_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, c3_pwm_parents);
 494static C3_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8);
 495static C3_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24);
 496
 497static C3_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, c3_pwm_parents);
 498static C3_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8);
 499static C3_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8);
 500
 501static C3_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, c3_pwm_parents);
 502static C3_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8);
 503static C3_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24);
 504
 505static C3_COMP_SEL(pwm_g, PWM_CLK_GH_CTRL, 9, 0x3, c3_pwm_parents);
 506static C3_COMP_DIV(pwm_g, PWM_CLK_GH_CTRL, 0, 8);
 507static C3_COMP_GATE(pwm_g, PWM_CLK_GH_CTRL, 8);
 508
 509static C3_COMP_SEL(pwm_h, PWM_CLK_GH_CTRL, 25, 0x3, c3_pwm_parents);
 510static C3_COMP_DIV(pwm_h, PWM_CLK_GH_CTRL, 16, 8);
 511static C3_COMP_GATE(pwm_h, PWM_CLK_GH_CTRL, 24);
 512
 513static C3_COMP_SEL(pwm_i, PWM_CLK_IJ_CTRL, 9, 0x3, c3_pwm_parents);
 514static C3_COMP_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0, 8);
 515static C3_COMP_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8);
 516
 517static C3_COMP_SEL(pwm_j, PWM_CLK_IJ_CTRL, 25, 0x3, c3_pwm_parents);
 518static C3_COMP_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16, 8);
 519static C3_COMP_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24);
 520
 521static C3_COMP_SEL(pwm_k, PWM_CLK_KL_CTRL, 9, 0x3, c3_pwm_parents);
 522static C3_COMP_DIV(pwm_k, PWM_CLK_KL_CTRL, 0, 8);
 523static C3_COMP_GATE(pwm_k, PWM_CLK_KL_CTRL, 8);
 524
 525static C3_COMP_SEL(pwm_l, PWM_CLK_KL_CTRL, 25, 0x3, c3_pwm_parents);
 526static C3_COMP_DIV(pwm_l, PWM_CLK_KL_CTRL, 16, 8);
 527static C3_COMP_GATE(pwm_l, PWM_CLK_KL_CTRL, 24);
 528
 529static C3_COMP_SEL(pwm_m, PWM_CLK_MN_CTRL, 9, 0x3, c3_pwm_parents);
 530static C3_COMP_DIV(pwm_m, PWM_CLK_MN_CTRL, 0, 8);
 531static C3_COMP_GATE(pwm_m, PWM_CLK_MN_CTRL, 8);
 532
 533static C3_COMP_SEL(pwm_n, PWM_CLK_MN_CTRL, 25, 0x3, c3_pwm_parents);
 534static C3_COMP_DIV(pwm_n, PWM_CLK_MN_CTRL, 16, 8);
 535static C3_COMP_GATE(pwm_n, PWM_CLK_MN_CTRL, 24);
 536
 537static const struct clk_parent_data c3_spicc_parents[] = {
 538	{ .fw_name = "oscin" },
 539	{ .fw_name = "sysclk" },
 540	{ .fw_name = "fdiv4" },
 541	{ .fw_name = "fdiv3" },
 542	{ .fw_name = "fdiv2" },
 543	{ .fw_name = "fdiv5" },
 544	{ .fw_name = "fdiv7" },
 545	{ .fw_name = "gp1" }
 546};
 547
 548static C3_COMP_SEL(spicc_a, SPICC_CLK_CTRL, 7, 0x7, c3_spicc_parents);
 549static C3_COMP_DIV(spicc_a, SPICC_CLK_CTRL, 0, 6);
 550static C3_COMP_GATE(spicc_a, SPICC_CLK_CTRL,  6);
 551
 552static C3_COMP_SEL(spicc_b, SPICC_CLK_CTRL, 23, 0x7, c3_spicc_parents);
 553static C3_COMP_DIV(spicc_b, SPICC_CLK_CTRL, 16, 6);
 554static C3_COMP_GATE(spicc_b, SPICC_CLK_CTRL, 22);
 555
 556static const struct clk_parent_data c3_spifc_parents[] = {
 557	{ .fw_name = "gp0" },
 558	{ .fw_name = "fdiv2" },
 559	{ .fw_name = "fdiv3" },
 560	{ .fw_name = "fdiv2p5" },
 561	{ .fw_name = "hifi" },
 562	{ .fw_name = "fdiv4" },
 563	{ .fw_name = "fdiv5" },
 564	{ .fw_name = "fdiv7" }
 565};
 566
 567static C3_COMP_SEL(spifc, SPIFC_CLK_CTRL, 9, 0x7, c3_spifc_parents);
 568static C3_COMP_DIV(spifc, SPIFC_CLK_CTRL, 0, 7);
 569static C3_COMP_GATE(spifc, SPIFC_CLK_CTRL,  8);
 570
 571static const struct clk_parent_data c3_sd_emmc_parents[] = {
 572	{ .fw_name = "oscin" },
 573	{ .fw_name = "fdiv2" },
 574	{ .fw_name = "fdiv3" },
 575	{ .fw_name = "hifi" },
 576	{ .fw_name = "fdiv2p5" },
 577	{ .fw_name = "fdiv4" },
 578	{ .fw_name = "gp1" },
 579	{ .fw_name = "gp0" }
 580};
 581
 582static C3_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, c3_sd_emmc_parents);
 583static C3_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7);
 584static C3_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL,  7);
 585
 586static C3_COMP_SEL(sd_emmc_b, SD_EMMC_CLK_CTRL, 25, 0x7, c3_sd_emmc_parents);
 587static C3_COMP_DIV(sd_emmc_b, SD_EMMC_CLK_CTRL, 16, 7);
 588static C3_COMP_GATE(sd_emmc_b, SD_EMMC_CLK_CTRL, 23);
 589
 590static C3_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, c3_sd_emmc_parents);
 591static C3_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7);
 592static C3_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7);
 593
 594static struct clk_regmap c3_ts_div = {
 595	.data = &(struct clk_regmap_div_data) {
 596		.offset = TS_CLK_CTRL,
 597		.shift = 0,
 598		.width = 8,
 599	},
 600	.hw.init = &(struct clk_init_data) {
 601		.name = "ts_div",
 602		.ops = &clk_regmap_divider_ops,
 603		.parent_data = &(const struct clk_parent_data) {
 604			.fw_name = "oscin",
 605		},
 606		.num_parents = 1,
 607	},
 608};
 609
 610static struct clk_regmap c3_ts = {
 611	.data = &(struct clk_regmap_gate_data) {
 612		.offset = TS_CLK_CTRL,
 613		.bit_idx = 8,
 614	},
 615	.hw.init = &(struct clk_init_data) {
 616		.name = "ts",
 617		.ops = &clk_regmap_gate_ops,
 618		.parent_hws = (const struct clk_hw *[]) {
 619			&c3_ts_div.hw
 620		},
 621		.num_parents = 1,
 622		.flags = CLK_SET_RATE_PARENT,
 623	},
 624};
 625
 626static const struct clk_parent_data c3_eth_parents = {
 627	.fw_name = "fdiv2",
 628};
 629
 630static struct clk_fixed_factor c3_eth_125m_div = {
 631	.mult = 1,
 632	.div = 8,
 633	.hw.init = &(struct clk_init_data) {
 634		.name = "eth_125m_div",
 635		.ops = &clk_fixed_factor_ops,
 636		.parent_data = &c3_eth_parents,
 637		.num_parents = 1,
 638	},
 639};
 640
 641static struct clk_regmap c3_eth_125m = {
 642	.data = &(struct clk_regmap_gate_data) {
 643		.offset = ETH_CLK_CTRL,
 644		.bit_idx = 7,
 645	},
 646	.hw.init = &(struct clk_init_data) {
 647		.name = "eth_125m",
 648		.ops = &clk_regmap_gate_ops,
 649		.parent_hws = (const struct clk_hw *[]) {
 650			&c3_eth_125m_div.hw
 651		},
 652		.num_parents = 1,
 653		.flags = CLK_SET_RATE_PARENT,
 654	},
 655};
 656
 657static struct clk_regmap c3_eth_rmii_div = {
 658	.data = &(struct clk_regmap_div_data) {
 659		.offset = ETH_CLK_CTRL,
 660		.shift = 0,
 661		.width = 7,
 662	},
 663	.hw.init = &(struct clk_init_data) {
 664		.name = "eth_rmii_div",
 665		.ops = &clk_regmap_divider_ops,
 666		.parent_data = &c3_eth_parents,
 667		.num_parents = 1,
 668	},
 669};
 670
 671static struct clk_regmap c3_eth_rmii = {
 672	.data = &(struct clk_regmap_gate_data) {
 673		.offset = ETH_CLK_CTRL,
 674		.bit_idx = 8,
 675	},
 676	.hw.init = &(struct clk_init_data) {
 677		.name = "eth_rmii",
 678		.ops = &clk_regmap_gate_ops,
 679		.parent_hws = (const struct clk_hw *[]) {
 680			&c3_eth_rmii_div.hw
 681		},
 682		.num_parents = 1,
 683		.flags = CLK_SET_RATE_PARENT,
 684	},
 685};
 686
 687static const struct clk_parent_data c3_mipi_dsi_meas_parents[] = {
 688	{ .fw_name = "oscin" },
 689	{ .fw_name = "fdiv4" },
 690	{ .fw_name = "fdiv3" },
 691	{ .fw_name = "fdiv5" },
 692	{ .fw_name = "gp1" },
 693	{ .fw_name = "gp0" },
 694	{ .fw_name = "fdiv2" },
 695	{ .fw_name = "fdiv7" }
 696};
 697
 698static C3_COMP_SEL(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 21, 0x7, c3_mipi_dsi_meas_parents);
 699static C3_COMP_DIV(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 12, 7);
 700static C3_COMP_GATE(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 20);
 701
 702static const struct clk_parent_data c3_dsi_phy_parents[] = {
 703	{ .fw_name = "gp1" },
 704	{ .fw_name = "gp0" },
 705	{ .fw_name = "hifi" },
 706	{ .fw_name = "fdiv3" },
 707	{ .fw_name = "fdiv2" },
 708	{ .fw_name = "fdiv2p5" },
 709	{ .fw_name = "fdiv4" },
 710	{ .fw_name = "fdiv7" }
 711};
 712
 713static C3_COMP_SEL(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 12, 0x7, c3_dsi_phy_parents);
 714static C3_COMP_DIV(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 0, 7);
 715static C3_COMP_GATE(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 8);
 716
 717static const struct clk_parent_data c3_vout_mclk_parents[] = {
 718	{ .fw_name = "fdiv2p5" },
 719	{ .fw_name = "fdiv3" },
 720	{ .fw_name = "fdiv4" },
 721	{ .fw_name = "fdiv5" },
 722	{ .fw_name = "gp0" },
 723	{ .fw_name = "hifi" },
 724	{ .fw_name = "gp1" },
 725	{ .fw_name = "fdiv7" }
 726};
 727
 728static C3_COMP_SEL(vout_mclk, VOUTENC_CLK_CTRL, 9, 0x7, c3_vout_mclk_parents);
 729static C3_COMP_DIV(vout_mclk, VOUTENC_CLK_CTRL, 0, 7);
 730static C3_COMP_GATE(vout_mclk, VOUTENC_CLK_CTRL, 8);
 731
 732static const struct clk_parent_data c3_vout_enc_parents[] = {
 733	{ .fw_name = "gp1" },
 734	{ .fw_name = "fdiv3" },
 735	{ .fw_name = "fdiv4" },
 736	{ .fw_name = "fdiv5" },
 737	{ .fw_name = "gp0" },
 738	{ .fw_name = "hifi" },
 739	{ .fw_name = "fdiv2p5" },
 740	{ .fw_name = "fdiv7" }
 741};
 742
 743static C3_COMP_SEL(vout_enc, VOUTENC_CLK_CTRL, 25, 0x7, c3_vout_enc_parents);
 744static C3_COMP_DIV(vout_enc, VOUTENC_CLK_CTRL, 16, 7);
 745static C3_COMP_GATE(vout_enc, VOUTENC_CLK_CTRL, 24);
 746
 747static const struct clk_parent_data c3_hcodec_pre_parents[] = {
 748	{ .fw_name = "fdiv2p5" },
 749	{ .fw_name = "fdiv3" },
 750	{ .fw_name = "fdiv4" },
 751	{ .fw_name = "fdiv5" },
 752	{ .fw_name = "fdiv7" },
 753	{ .fw_name = "hifi" },
 754	{ .fw_name = "gp0" },
 755	{ .fw_name = "oscin" }
 756};
 757
 758static C3_COMP_SEL(hcodec_0,  VDEC_CLK_CTRL, 9, 0x7, c3_hcodec_pre_parents);
 759static C3_COMP_DIV(hcodec_0,  VDEC_CLK_CTRL, 0, 7);
 760static C3_COMP_GATE(hcodec_0,  VDEC_CLK_CTRL, 8);
 761
 762static C3_COMP_SEL(hcodec_1, VDEC3_CLK_CTRL, 9, 0x7, c3_hcodec_pre_parents);
 763static C3_COMP_DIV(hcodec_1, VDEC3_CLK_CTRL, 0, 7);
 764static C3_COMP_GATE(hcodec_1, VDEC3_CLK_CTRL, 8);
 765
 766static const struct clk_parent_data c3_hcodec_parents[] = {
 767	{ .hw = &c3_hcodec_0.hw },
 768	{ .hw = &c3_hcodec_1.hw }
 769};
 770
 771static struct clk_regmap c3_hcodec = {
 772	.data = &(struct clk_regmap_mux_data) {
 773		.offset = VDEC3_CLK_CTRL,
 774		.mask = 0x1,
 775		.shift = 15,
 776	},
 777	.hw.init = &(struct clk_init_data) {
 778		.name = "hcodec",
 779		.ops = &clk_regmap_mux_ops,
 780		.parent_data = c3_hcodec_parents,
 781		.num_parents = ARRAY_SIZE(c3_hcodec_parents),
 782		.flags = CLK_SET_RATE_PARENT,
 783	},
 784};
 785
 786static const struct clk_parent_data c3_vc9000e_parents[] = {
 787	{ .fw_name = "oscin" },
 788	{ .fw_name = "fdiv4" },
 789	{ .fw_name = "fdiv3" },
 790	{ .fw_name = "fdiv5" },
 791	{ .fw_name = "fdiv7" },
 792	{ .fw_name = "fdiv2p5" },
 793	{ .fw_name = "hifi" },
 794	{ .fw_name = "gp0" }
 795};
 796
 797static C3_COMP_SEL(vc9000e_aclk, VC9000E_CLK_CTRL, 9, 0x7, c3_vc9000e_parents);
 798static C3_COMP_DIV(vc9000e_aclk, VC9000E_CLK_CTRL, 0, 7);
 799static C3_COMP_GATE(vc9000e_aclk, VC9000E_CLK_CTRL, 8);
 800
 801static C3_COMP_SEL(vc9000e_core, VC9000E_CLK_CTRL, 25, 0x7, c3_vc9000e_parents);
 802static C3_COMP_DIV(vc9000e_core, VC9000E_CLK_CTRL, 16, 7);
 803static C3_COMP_GATE(vc9000e_core, VC9000E_CLK_CTRL, 24);
 804
 805static const struct clk_parent_data c3_csi_phy_parents[] = {
 806	{ .fw_name = "fdiv2p5" },
 807	{ .fw_name = "fdiv3" },
 808	{ .fw_name = "fdiv4" },
 809	{ .fw_name = "fdiv5" },
 810	{ .fw_name = "gp0" },
 811	{ .fw_name = "hifi" },
 812	{ .fw_name = "gp1" },
 813	{ .fw_name = "oscin" }
 814};
 815
 816static C3_COMP_SEL(csi_phy0, ISP0_CLK_CTRL, 25, 0x7, c3_csi_phy_parents);
 817static C3_COMP_DIV(csi_phy0, ISP0_CLK_CTRL, 16, 7);
 818static C3_COMP_GATE(csi_phy0, ISP0_CLK_CTRL, 24);
 819
 820static const struct clk_parent_data c3_dewarpa_parents[] = {
 821	{ .fw_name = "fdiv2p5" },
 822	{ .fw_name = "fdiv3" },
 823	{ .fw_name = "fdiv4" },
 824	{ .fw_name = "fdiv5" },
 825	{ .fw_name = "gp0" },
 826	{ .fw_name = "hifi" },
 827	{ .fw_name = "gp1" },
 828	{ .fw_name = "fdiv7" }
 829};
 830
 831static C3_COMP_SEL(dewarpa, DEWARPA_CLK_CTRL, 9, 0x7, c3_dewarpa_parents);
 832static C3_COMP_DIV(dewarpa, DEWARPA_CLK_CTRL, 0, 7);
 833static C3_COMP_GATE(dewarpa, DEWARPA_CLK_CTRL, 8);
 834
 835static const struct clk_parent_data c3_isp_parents[] = {
 836	{ .fw_name = "fdiv2p5" },
 837	{ .fw_name = "fdiv3" },
 838	{ .fw_name = "fdiv4" },
 839	{ .fw_name = "fdiv5" },
 840	{ .fw_name = "gp0" },
 841	{ .fw_name = "hifi" },
 842	{ .fw_name = "gp1" },
 843	{ .fw_name = "oscin" }
 844};
 845
 846static C3_COMP_SEL(isp0, ISP0_CLK_CTRL, 9, 0x7, c3_isp_parents);
 847static C3_COMP_DIV(isp0, ISP0_CLK_CTRL, 0, 7);
 848static C3_COMP_GATE(isp0, ISP0_CLK_CTRL, 8);
 849
 850static const struct clk_parent_data c3_nna_core_parents[] = {
 851	{ .fw_name = "oscin" },
 852	{ .fw_name = "fdiv2p5" },
 853	{ .fw_name = "fdiv4" },
 854	{ .fw_name = "fdiv3" },
 855	{ .fw_name = "fdiv5" },
 856	{ .fw_name = "fdiv2" },
 857	{ .fw_name = "gp1" },
 858	{ .fw_name = "hifi" }
 859};
 860
 861static C3_COMP_SEL(nna_core, NNA_CLK_CTRL, 9, 0x7, c3_nna_core_parents);
 862static C3_COMP_DIV(nna_core, NNA_CLK_CTRL, 0, 7);
 863static C3_COMP_GATE(nna_core, NNA_CLK_CTRL, 8);
 864
 865static const struct clk_parent_data c3_ge2d_parents[] = {
 866	{ .fw_name = "oscin" },
 867	{ .fw_name = "fdiv2p5" },
 868	{ .fw_name = "fdiv3" },
 869	{ .fw_name = "fdiv4" },
 870	{ .fw_name = "hifi" },
 871	{ .fw_name = "fdiv5" },
 872	{ .fw_name = "gp0" },
 873	{ .hw = &c3_rtc_clk.hw }
 874};
 875
 876static C3_COMP_SEL(ge2d, GE2D_CLK_CTRL, 9, 0x7, c3_ge2d_parents);
 877static C3_COMP_DIV(ge2d, GE2D_CLK_CTRL, 0, 7);
 878static C3_COMP_GATE(ge2d, GE2D_CLK_CTRL, 8);
 879
 880static const struct clk_parent_data c3_vapb_parents[] = {
 881	{ .fw_name = "fdiv2p5" },
 882	{ .fw_name = "fdiv3" },
 883	{ .fw_name = "fdiv4" },
 884	{ .fw_name = "fdiv5" },
 885	{ .fw_name = "gp0" },
 886	{ .fw_name = "hifi" },
 887	{ .fw_name = "gp1" },
 888	{ .fw_name = "oscin" },
 889};
 890
 891static C3_COMP_SEL(vapb, VAPB_CLK_CTRL, 9, 0x7, c3_vapb_parents);
 892static C3_COMP_DIV(vapb, VAPB_CLK_CTRL, 0, 7);
 893static C3_COMP_GATE(vapb, VAPB_CLK_CTRL, 8);
 894
 895static struct clk_hw *c3_peripherals_hw_clks[] = {
 896	[CLKID_RTC_XTAL_CLKIN]		= &c3_rtc_xtal_clkin.hw,
 897	[CLKID_RTC_32K_DIV]		= &c3_rtc_32k_div.hw,
 898	[CLKID_RTC_32K_MUX]		= &c3_rtc_32k_sel.hw,
 899	[CLKID_RTC_32K]			= &c3_rtc_32k.hw,
 900	[CLKID_RTC_CLK]			= &c3_rtc_clk.hw,
 901	[CLKID_SYS_RESET_CTRL]		= &c3_sys_reset_ctrl.hw,
 902	[CLKID_SYS_PWR_CTRL]		= &c3_sys_pwr_ctrl.hw,
 903	[CLKID_SYS_PAD_CTRL]		= &c3_sys_pad_ctrl.hw,
 904	[CLKID_SYS_CTRL]		= &c3_sys_ctrl.hw,
 905	[CLKID_SYS_TS_PLL]		= &c3_sys_ts_pll.hw,
 906	[CLKID_SYS_DEV_ARB]		= &c3_sys_dev_arb.hw,
 907	[CLKID_SYS_MMC_PCLK]		= &c3_sys_mmc_pclk.hw,
 908	[CLKID_SYS_CPU_CTRL]		= &c3_sys_cpu_ctrl.hw,
 909	[CLKID_SYS_JTAG_CTRL]		= &c3_sys_jtag_ctrl.hw,
 910	[CLKID_SYS_IR_CTRL]		= &c3_sys_ir_ctrl.hw,
 911	[CLKID_SYS_IRQ_CTRL]		= &c3_sys_irq_ctrl.hw,
 912	[CLKID_SYS_MSR_CLK]		= &c3_sys_msr_clk.hw,
 913	[CLKID_SYS_ROM]			= &c3_sys_rom.hw,
 914	[CLKID_SYS_UART_F]		= &c3_sys_uart_f.hw,
 915	[CLKID_SYS_CPU_ARB]		= &c3_sys_cpu_apb.hw,
 916	[CLKID_SYS_RSA]			= &c3_sys_rsa.hw,
 917	[CLKID_SYS_SAR_ADC]		= &c3_sys_sar_adc.hw,
 918	[CLKID_SYS_STARTUP]		= &c3_sys_startup.hw,
 919	[CLKID_SYS_SECURE]		= &c3_sys_secure.hw,
 920	[CLKID_SYS_SPIFC]		= &c3_sys_spifc.hw,
 921	[CLKID_SYS_NNA]			= &c3_sys_nna.hw,
 922	[CLKID_SYS_ETH_MAC]		= &c3_sys_eth_mac.hw,
 923	[CLKID_SYS_GIC]			= &c3_sys_gic.hw,
 924	[CLKID_SYS_RAMA]		= &c3_sys_rama.hw,
 925	[CLKID_SYS_BIG_NIC]		= &c3_sys_big_nic.hw,
 926	[CLKID_SYS_RAMB]		= &c3_sys_ramb.hw,
 927	[CLKID_SYS_AUDIO_PCLK]		= &c3_sys_audio_pclk.hw,
 928	[CLKID_SYS_PWM_KL]		= &c3_sys_pwm_kl.hw,
 929	[CLKID_SYS_PWM_IJ]		= &c3_sys_pwm_ij.hw,
 930	[CLKID_SYS_USB]			= &c3_sys_usb.hw,
 931	[CLKID_SYS_SD_EMMC_A]		= &c3_sys_sd_emmc_a.hw,
 932	[CLKID_SYS_SD_EMMC_C]		= &c3_sys_sd_emmc_c.hw,
 933	[CLKID_SYS_PWM_AB]		= &c3_sys_pwm_ab.hw,
 934	[CLKID_SYS_PWM_CD]		= &c3_sys_pwm_cd.hw,
 935	[CLKID_SYS_PWM_EF]		= &c3_sys_pwm_ef.hw,
 936	[CLKID_SYS_PWM_GH]		= &c3_sys_pwm_gh.hw,
 937	[CLKID_SYS_SPICC_1]		= &c3_sys_spicc_1.hw,
 938	[CLKID_SYS_SPICC_0]		= &c3_sys_spicc_0.hw,
 939	[CLKID_SYS_UART_A]		= &c3_sys_uart_a.hw,
 940	[CLKID_SYS_UART_B]		= &c3_sys_uart_b.hw,
 941	[CLKID_SYS_UART_C]		= &c3_sys_uart_c.hw,
 942	[CLKID_SYS_UART_D]		= &c3_sys_uart_d.hw,
 943	[CLKID_SYS_UART_E]		= &c3_sys_uart_e.hw,
 944	[CLKID_SYS_I2C_M_A]		= &c3_sys_i2c_m_a.hw,
 945	[CLKID_SYS_I2C_M_B]		= &c3_sys_i2c_m_b.hw,
 946	[CLKID_SYS_I2C_M_C]		= &c3_sys_i2c_m_c.hw,
 947	[CLKID_SYS_I2C_M_D]		= &c3_sys_i2c_m_d.hw,
 948	[CLKID_SYS_I2S_S_A]		= &c3_sys_i2c_s_a.hw,
 949	[CLKID_SYS_RTC]			= &c3_sys_rtc.hw,
 950	[CLKID_SYS_GE2D]		= &c3_sys_ge2d.hw,
 951	[CLKID_SYS_ISP]			= &c3_sys_isp.hw,
 952	[CLKID_SYS_GPV_ISP_NIC]		= &c3_sys_gpv_isp_nic.hw,
 953	[CLKID_SYS_GPV_CVE_NIC]		= &c3_sys_gpv_cve_nic.hw,
 954	[CLKID_SYS_MIPI_DSI_HOST]	= &c3_sys_mipi_dsi_host.hw,
 955	[CLKID_SYS_MIPI_DSI_PHY]	= &c3_sys_mipi_dsi_phy.hw,
 956	[CLKID_SYS_ETH_PHY]		= &c3_sys_eth_phy.hw,
 957	[CLKID_SYS_ACODEC]		= &c3_sys_acodec.hw,
 958	[CLKID_SYS_DWAP]		= &c3_sys_dwap.hw,
 959	[CLKID_SYS_DOS]			= &c3_sys_dos.hw,
 960	[CLKID_SYS_CVE]			= &c3_sys_cve.hw,
 961	[CLKID_SYS_VOUT]		= &c3_sys_vout.hw,
 962	[CLKID_SYS_VC9000E]		= &c3_sys_vc9000e.hw,
 963	[CLKID_SYS_PWM_MN]		= &c3_sys_pwm_mn.hw,
 964	[CLKID_SYS_SD_EMMC_B]		= &c3_sys_sd_emmc_b.hw,
 965	[CLKID_AXI_SYS_NIC]		= &c3_axi_sys_nic.hw,
 966	[CLKID_AXI_ISP_NIC]		= &c3_axi_isp_nic.hw,
 967	[CLKID_AXI_CVE_NIC]		= &c3_axi_cve_nic.hw,
 968	[CLKID_AXI_RAMB]		= &c3_axi_ramb.hw,
 969	[CLKID_AXI_RAMA]		= &c3_axi_rama.hw,
 970	[CLKID_AXI_CPU_DMC]		= &c3_axi_cpu_dmc.hw,
 971	[CLKID_AXI_NIC]			= &c3_axi_nic.hw,
 972	[CLKID_AXI_DMA]			= &c3_axi_dma.hw,
 973	[CLKID_AXI_MUX_NIC]		= &c3_axi_mux_nic.hw,
 974	[CLKID_AXI_CVE]			= &c3_axi_cve.hw,
 975	[CLKID_AXI_DEV1_DMC]		= &c3_axi_dev1_dmc.hw,
 976	[CLKID_AXI_DEV0_DMC]		= &c3_axi_dev0_dmc.hw,
 977	[CLKID_AXI_DSP_DMC]		= &c3_axi_dsp_dmc.hw,
 978	[CLKID_12_24M_IN]		= &c3_clk_12_24m_in.hw,
 979	[CLKID_12M_24M]			= &c3_clk_12_24m.hw,
 980	[CLKID_FCLK_25M_DIV]		= &c3_fclk_25m_div.hw,
 981	[CLKID_FCLK_25M]		= &c3_fclk_25m.hw,
 982	[CLKID_GEN_SEL]			= &c3_gen_sel.hw,
 983	[CLKID_GEN_DIV]			= &c3_gen_div.hw,
 984	[CLKID_GEN]			= &c3_gen.hw,
 985	[CLKID_SARADC_SEL]		= &c3_saradc_sel.hw,
 986	[CLKID_SARADC_DIV]		= &c3_saradc_div.hw,
 987	[CLKID_SARADC]			= &c3_saradc.hw,
 988	[CLKID_PWM_A_SEL]		= &c3_pwm_a_sel.hw,
 989	[CLKID_PWM_A_DIV]		= &c3_pwm_a_div.hw,
 990	[CLKID_PWM_A]			= &c3_pwm_a.hw,
 991	[CLKID_PWM_B_SEL]		= &c3_pwm_b_sel.hw,
 992	[CLKID_PWM_B_DIV]		= &c3_pwm_b_div.hw,
 993	[CLKID_PWM_B]			= &c3_pwm_b.hw,
 994	[CLKID_PWM_C_SEL]		= &c3_pwm_c_sel.hw,
 995	[CLKID_PWM_C_DIV]		= &c3_pwm_c_div.hw,
 996	[CLKID_PWM_C]			= &c3_pwm_c.hw,
 997	[CLKID_PWM_D_SEL]		= &c3_pwm_d_sel.hw,
 998	[CLKID_PWM_D_DIV]		= &c3_pwm_d_div.hw,
 999	[CLKID_PWM_D]			= &c3_pwm_d.hw,
1000	[CLKID_PWM_E_SEL]		= &c3_pwm_e_sel.hw,
1001	[CLKID_PWM_E_DIV]		= &c3_pwm_e_div.hw,
1002	[CLKID_PWM_E]			= &c3_pwm_e.hw,
1003	[CLKID_PWM_F_SEL]		= &c3_pwm_f_sel.hw,
1004	[CLKID_PWM_F_DIV]		= &c3_pwm_f_div.hw,
1005	[CLKID_PWM_F]			= &c3_pwm_f.hw,
1006	[CLKID_PWM_G_SEL]		= &c3_pwm_g_sel.hw,
1007	[CLKID_PWM_G_DIV]		= &c3_pwm_g_div.hw,
1008	[CLKID_PWM_G]			= &c3_pwm_g.hw,
1009	[CLKID_PWM_H_SEL]		= &c3_pwm_h_sel.hw,
1010	[CLKID_PWM_H_DIV]		= &c3_pwm_h_div.hw,
1011	[CLKID_PWM_H]			= &c3_pwm_h.hw,
1012	[CLKID_PWM_I_SEL]		= &c3_pwm_i_sel.hw,
1013	[CLKID_PWM_I_DIV]		= &c3_pwm_i_div.hw,
1014	[CLKID_PWM_I]			= &c3_pwm_i.hw,
1015	[CLKID_PWM_J_SEL]		= &c3_pwm_j_sel.hw,
1016	[CLKID_PWM_J_DIV]		= &c3_pwm_j_div.hw,
1017	[CLKID_PWM_J]			= &c3_pwm_j.hw,
1018	[CLKID_PWM_K_SEL]		= &c3_pwm_k_sel.hw,
1019	[CLKID_PWM_K_DIV]		= &c3_pwm_k_div.hw,
1020	[CLKID_PWM_K]			= &c3_pwm_k.hw,
1021	[CLKID_PWM_L_SEL]		= &c3_pwm_l_sel.hw,
1022	[CLKID_PWM_L_DIV]		= &c3_pwm_l_div.hw,
1023	[CLKID_PWM_L]			= &c3_pwm_l.hw,
1024	[CLKID_PWM_M_SEL]		= &c3_pwm_m_sel.hw,
1025	[CLKID_PWM_M_DIV]		= &c3_pwm_m_div.hw,
1026	[CLKID_PWM_M]			= &c3_pwm_m.hw,
1027	[CLKID_PWM_N_SEL]		= &c3_pwm_n_sel.hw,
1028	[CLKID_PWM_N_DIV]		= &c3_pwm_n_div.hw,
1029	[CLKID_PWM_N]			= &c3_pwm_n.hw,
1030	[CLKID_SPICC_A_SEL]		= &c3_spicc_a_sel.hw,
1031	[CLKID_SPICC_A_DIV]		= &c3_spicc_a_div.hw,
1032	[CLKID_SPICC_A]			= &c3_spicc_a.hw,
1033	[CLKID_SPICC_B_SEL]		= &c3_spicc_b_sel.hw,
1034	[CLKID_SPICC_B_DIV]		= &c3_spicc_b_div.hw,
1035	[CLKID_SPICC_B]			= &c3_spicc_b.hw,
1036	[CLKID_SPIFC_SEL]		= &c3_spifc_sel.hw,
1037	[CLKID_SPIFC_DIV]		= &c3_spifc_div.hw,
1038	[CLKID_SPIFC]			= &c3_spifc.hw,
1039	[CLKID_SD_EMMC_A_SEL]		= &c3_sd_emmc_a_sel.hw,
1040	[CLKID_SD_EMMC_A_DIV]		= &c3_sd_emmc_a_div.hw,
1041	[CLKID_SD_EMMC_A]		= &c3_sd_emmc_a.hw,
1042	[CLKID_SD_EMMC_B_SEL]		= &c3_sd_emmc_b_sel.hw,
1043	[CLKID_SD_EMMC_B_DIV]		= &c3_sd_emmc_b_div.hw,
1044	[CLKID_SD_EMMC_B]		= &c3_sd_emmc_b.hw,
1045	[CLKID_SD_EMMC_C_SEL]		= &c3_sd_emmc_c_sel.hw,
1046	[CLKID_SD_EMMC_C_DIV]		= &c3_sd_emmc_c_div.hw,
1047	[CLKID_SD_EMMC_C]		= &c3_sd_emmc_c.hw,
1048	[CLKID_TS_DIV]			= &c3_ts_div.hw,
1049	[CLKID_TS]			= &c3_ts.hw,
1050	[CLKID_ETH_125M_DIV]		= &c3_eth_125m_div.hw,
1051	[CLKID_ETH_125M]		= &c3_eth_125m.hw,
1052	[CLKID_ETH_RMII_DIV]		= &c3_eth_rmii_div.hw,
1053	[CLKID_ETH_RMII]		= &c3_eth_rmii.hw,
1054	[CLKID_MIPI_DSI_MEAS_SEL]	= &c3_mipi_dsi_meas_sel.hw,
1055	[CLKID_MIPI_DSI_MEAS_DIV]	= &c3_mipi_dsi_meas_div.hw,
1056	[CLKID_MIPI_DSI_MEAS]		= &c3_mipi_dsi_meas.hw,
1057	[CLKID_DSI_PHY_SEL]		= &c3_dsi_phy_sel.hw,
1058	[CLKID_DSI_PHY_DIV]		= &c3_dsi_phy_div.hw,
1059	[CLKID_DSI_PHY]			= &c3_dsi_phy.hw,
1060	[CLKID_VOUT_MCLK_SEL]		= &c3_vout_mclk_sel.hw,
1061	[CLKID_VOUT_MCLK_DIV]		= &c3_vout_mclk_div.hw,
1062	[CLKID_VOUT_MCLK]		= &c3_vout_mclk.hw,
1063	[CLKID_VOUT_ENC_SEL]		= &c3_vout_enc_sel.hw,
1064	[CLKID_VOUT_ENC_DIV]		= &c3_vout_enc_div.hw,
1065	[CLKID_VOUT_ENC]		= &c3_vout_enc.hw,
1066	[CLKID_HCODEC_0_SEL]		= &c3_hcodec_0_sel.hw,
1067	[CLKID_HCODEC_0_DIV]		= &c3_hcodec_0_div.hw,
1068	[CLKID_HCODEC_0]		= &c3_hcodec_0.hw,
1069	[CLKID_HCODEC_1_SEL]		= &c3_hcodec_1_sel.hw,
1070	[CLKID_HCODEC_1_DIV]		= &c3_hcodec_1_div.hw,
1071	[CLKID_HCODEC_1]		= &c3_hcodec_1.hw,
1072	[CLKID_HCODEC]			= &c3_hcodec.hw,
1073	[CLKID_VC9000E_ACLK_SEL]	= &c3_vc9000e_aclk_sel.hw,
1074	[CLKID_VC9000E_ACLK_DIV]	= &c3_vc9000e_aclk_div.hw,
1075	[CLKID_VC9000E_ACLK]		= &c3_vc9000e_aclk.hw,
1076	[CLKID_VC9000E_CORE_SEL]	= &c3_vc9000e_core_sel.hw,
1077	[CLKID_VC9000E_CORE_DIV]	= &c3_vc9000e_core_div.hw,
1078	[CLKID_VC9000E_CORE]		= &c3_vc9000e_core.hw,
1079	[CLKID_CSI_PHY0_SEL]		= &c3_csi_phy0_sel.hw,
1080	[CLKID_CSI_PHY0_DIV]		= &c3_csi_phy0_div.hw,
1081	[CLKID_CSI_PHY0]		= &c3_csi_phy0.hw,
1082	[CLKID_DEWARPA_SEL]		= &c3_dewarpa_sel.hw,
1083	[CLKID_DEWARPA_DIV]		= &c3_dewarpa_div.hw,
1084	[CLKID_DEWARPA]			= &c3_dewarpa.hw,
1085	[CLKID_ISP0_SEL]		= &c3_isp0_sel.hw,
1086	[CLKID_ISP0_DIV]		= &c3_isp0_div.hw,
1087	[CLKID_ISP0]			= &c3_isp0.hw,
1088	[CLKID_NNA_CORE_SEL]		= &c3_nna_core_sel.hw,
1089	[CLKID_NNA_CORE_DIV]		= &c3_nna_core_div.hw,
1090	[CLKID_NNA_CORE]		= &c3_nna_core.hw,
1091	[CLKID_GE2D_SEL]		= &c3_ge2d_sel.hw,
1092	[CLKID_GE2D_DIV]		= &c3_ge2d_div.hw,
1093	[CLKID_GE2D]			= &c3_ge2d.hw,
1094	[CLKID_VAPB_SEL]		= &c3_vapb_sel.hw,
1095	[CLKID_VAPB_DIV]		= &c3_vapb_div.hw,
1096	[CLKID_VAPB]			= &c3_vapb.hw,
1097};
1098
1099static const struct meson_clkc_data c3_peripherals_clkc_data = {
1100	.hw_clks = {
1101		.hws = c3_peripherals_hw_clks,
1102		.num = ARRAY_SIZE(c3_peripherals_hw_clks),
1103	},
1104};
1105
1106static const struct of_device_id c3_peripherals_clkc_match_table[] = {
1107	{
1108		.compatible = "amlogic,c3-peripherals-clkc",
1109		.data = &c3_peripherals_clkc_data,
1110	},
1111	{ /* sentinel */ }
1112};
1113
1114MODULE_DEVICE_TABLE(of, c3_peripherals_clkc_match_table);
1115
1116static struct platform_driver c3_peripherals_clkc_driver = {
1117	.probe		= meson_clkc_mmio_probe,
1118	.driver		= {
1119		.name	= "c3-peripherals-clkc",
1120		.of_match_table = c3_peripherals_clkc_match_table,
1121	},
1122};
1123module_platform_driver(c3_peripherals_clkc_driver);
1124
1125MODULE_DESCRIPTION("Amlogic C3 Peripherals Clock Controller driver");
1126MODULE_AUTHOR("Chuan Liu <chuan.liu@amlogic.com>");
1127MODULE_LICENSE("GPL");
1128MODULE_IMPORT_NS("CLK_MESON");