axg.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * AmLogic Meson-AXG Clock Controller Driver
   4 *
   5 * Copyright (c) 2016 Baylibre SAS.
   6 * Author: Michael Turquette <mturquette@baylibre.com>
   7 *
   8 * Copyright (c) 2017 Amlogic, inc.
   9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
  10 */
  11
  12#include <linux/clk-provider.h>
  13#include <linux/init.h>
  14#include <linux/mod_devicetable.h>
  15#include <linux/platform_device.h>
  16#include <linux/module.h>
  17
  18#include "clk-regmap.h"
  19#include "clk-pll.h"
  20#include "clk-mpll.h"
  21#include "meson-clkc-utils.h"
  22
  23#include <dt-bindings/clock/axg-clkc.h>
  24
  25#define HHI_GP0_PLL_CNTL		0x40
  26#define HHI_GP0_PLL_CNTL2		0x44
  27#define HHI_GP0_PLL_CNTL3		0x48
  28#define HHI_GP0_PLL_CNTL4		0x4c
  29#define HHI_GP0_PLL_CNTL5		0x50
  30#define HHI_GP0_PLL_STS			0x54
  31#define HHI_GP0_PLL_CNTL1		0x58
  32#define HHI_HIFI_PLL_CNTL		0x80
  33#define HHI_HIFI_PLL_CNTL2		0x84
  34#define HHI_HIFI_PLL_CNTL3		0x88
  35#define HHI_HIFI_PLL_CNTL4		0x8C
  36#define HHI_HIFI_PLL_CNTL5		0x90
  37#define HHI_HIFI_PLL_STS		0x94
  38#define HHI_HIFI_PLL_CNTL1		0x98
  39
  40#define HHI_XTAL_DIVN_CNTL		0xbc
  41#define HHI_GCLK2_MPEG0			0xc0
  42#define HHI_GCLK2_MPEG1			0xc4
  43#define HHI_GCLK2_MPEG2			0xc8
  44#define HHI_GCLK2_OTHER			0xd0
  45#define HHI_GCLK2_AO			0xd4
  46#define HHI_PCIE_PLL_CNTL		0xd8
  47#define HHI_PCIE_PLL_CNTL1		0xdC
  48#define HHI_PCIE_PLL_CNTL2		0xe0
  49#define HHI_PCIE_PLL_CNTL3		0xe4
  50#define HHI_PCIE_PLL_CNTL4		0xe8
  51#define HHI_PCIE_PLL_CNTL5		0xec
  52#define HHI_PCIE_PLL_CNTL6		0xf0
  53#define HHI_PCIE_PLL_STS		0xf4
  54
  55#define HHI_MEM_PD_REG0			0x100
  56#define HHI_VPU_MEM_PD_REG0		0x104
  57#define HHI_VIID_CLK_DIV		0x128
  58#define HHI_VIID_CLK_CNTL		0x12c
  59
  60#define HHI_GCLK_MPEG0			0x140
  61#define HHI_GCLK_MPEG1			0x144
  62#define HHI_GCLK_MPEG2			0x148
  63#define HHI_GCLK_OTHER			0x150
  64#define HHI_GCLK_AO			0x154
  65#define HHI_SYS_CPU_CLK_CNTL1		0x15c
  66#define HHI_SYS_CPU_RESET_CNTL		0x160
  67#define HHI_VID_CLK_DIV			0x164
  68#define HHI_SPICC_HCLK_CNTL		0x168
  69
  70#define HHI_MPEG_CLK_CNTL		0x174
  71#define HHI_VID_CLK_CNTL		0x17c
  72#define HHI_TS_CLK_CNTL			0x190
  73#define HHI_VID_CLK_CNTL2		0x194
  74#define HHI_SYS_CPU_CLK_CNTL0		0x19c
  75#define HHI_VID_PLL_CLK_DIV		0x1a0
  76#define HHI_VPU_CLK_CNTL		0x1bC
  77
  78#define HHI_VAPBCLK_CNTL		0x1F4
  79
  80#define HHI_GEN_CLK_CNTL		0x228
  81
  82#define HHI_VDIN_MEAS_CLK_CNTL		0x250
  83#define HHI_NAND_CLK_CNTL		0x25C
  84#define HHI_SD_EMMC_CLK_CNTL		0x264
  85
  86#define HHI_MPLL_CNTL			0x280
  87#define HHI_MPLL_CNTL2			0x284
  88#define HHI_MPLL_CNTL3			0x288
  89#define HHI_MPLL_CNTL4			0x28C
  90#define HHI_MPLL_CNTL5			0x290
  91#define HHI_MPLL_CNTL6			0x294
  92#define HHI_MPLL_CNTL7			0x298
  93#define HHI_MPLL_CNTL8			0x29C
  94#define HHI_MPLL_CNTL9			0x2A0
  95#define HHI_MPLL_CNTL10			0x2A4
  96
  97#define HHI_MPLL3_CNTL0			0x2E0
  98#define HHI_MPLL3_CNTL1			0x2E4
  99#define HHI_PLL_TOP_MISC		0x2E8
 100
 101#define HHI_SYS_PLL_CNTL1		0x2FC
 102#define HHI_SYS_PLL_CNTL		0x300
 103#define HHI_SYS_PLL_CNTL2		0x304
 104#define HHI_SYS_PLL_CNTL3		0x308
 105#define HHI_SYS_PLL_CNTL4		0x30c
 106#define HHI_SYS_PLL_CNTL5		0x310
 107#define HHI_SYS_PLL_STS			0x314
 108#define HHI_DPLL_TOP_I			0x318
 109#define HHI_DPLL_TOP2_I			0x31C
 110
 111static struct clk_regmap axg_fixed_pll_dco = {
 112	.data = &(struct meson_clk_pll_data){
 113		.en = {
 114			.reg_off = HHI_MPLL_CNTL,
 115			.shift   = 30,
 116			.width   = 1,
 117		},
 118		.m = {
 119			.reg_off = HHI_MPLL_CNTL,
 120			.shift   = 0,
 121			.width   = 9,
 122		},
 123		.n = {
 124			.reg_off = HHI_MPLL_CNTL,
 125			.shift   = 9,
 126			.width   = 5,
 127		},
 128		.frac = {
 129			.reg_off = HHI_MPLL_CNTL2,
 130			.shift   = 0,
 131			.width   = 12,
 132		},
 133		.l = {
 134			.reg_off = HHI_MPLL_CNTL,
 135			.shift   = 31,
 136			.width   = 1,
 137		},
 138		.rst = {
 139			.reg_off = HHI_MPLL_CNTL,
 140			.shift   = 29,
 141			.width   = 1,
 142		},
 143	},
 144	.hw.init = &(struct clk_init_data){
 145		.name = "fixed_pll_dco",
 146		.ops = &meson_clk_pll_ro_ops,
 147		.parent_data = &(const struct clk_parent_data) {
 148			.fw_name = "xtal",
 149		},
 150		.num_parents = 1,
 151	},
 152};
 153
 154static struct clk_regmap axg_fixed_pll = {
 155	.data = &(struct clk_regmap_div_data){
 156		.offset = HHI_MPLL_CNTL,
 157		.shift = 16,
 158		.width = 2,
 159		.flags = CLK_DIVIDER_POWER_OF_TWO,
 160	},
 161	.hw.init = &(struct clk_init_data){
 162		.name = "fixed_pll",
 163		.ops = &clk_regmap_divider_ro_ops,
 164		.parent_hws = (const struct clk_hw *[]) {
 165			&axg_fixed_pll_dco.hw
 166		},
 167		.num_parents = 1,
 168		/*
 169		 * This clock won't ever change at runtime so
 170		 * CLK_SET_RATE_PARENT is not required
 171		 */
 172	},
 173};
 174
 175static struct clk_regmap axg_sys_pll_dco = {
 176	.data = &(struct meson_clk_pll_data){
 177		.en = {
 178			.reg_off = HHI_SYS_PLL_CNTL,
 179			.shift   = 30,
 180			.width   = 1,
 181		},
 182		.m = {
 183			.reg_off = HHI_SYS_PLL_CNTL,
 184			.shift   = 0,
 185			.width   = 9,
 186		},
 187		.n = {
 188			.reg_off = HHI_SYS_PLL_CNTL,
 189			.shift   = 9,
 190			.width   = 5,
 191		},
 192		.l = {
 193			.reg_off = HHI_SYS_PLL_CNTL,
 194			.shift   = 31,
 195			.width   = 1,
 196		},
 197		.rst = {
 198			.reg_off = HHI_SYS_PLL_CNTL,
 199			.shift   = 29,
 200			.width   = 1,
 201		},
 202	},
 203	.hw.init = &(struct clk_init_data){
 204		.name = "sys_pll_dco",
 205		.ops = &meson_clk_pll_ro_ops,
 206		.parent_data = &(const struct clk_parent_data) {
 207			.fw_name = "xtal",
 208		},
 209		.num_parents = 1,
 210	},
 211};
 212
 213static struct clk_regmap axg_sys_pll = {
 214	.data = &(struct clk_regmap_div_data){
 215		.offset = HHI_SYS_PLL_CNTL,
 216		.shift = 16,
 217		.width = 2,
 218		.flags = CLK_DIVIDER_POWER_OF_TWO,
 219	},
 220	.hw.init = &(struct clk_init_data){
 221		.name = "sys_pll",
 222		.ops = &clk_regmap_divider_ro_ops,
 223		.parent_hws = (const struct clk_hw *[]) {
 224			&axg_sys_pll_dco.hw
 225		},
 226		.num_parents = 1,
 227		.flags = CLK_SET_RATE_PARENT,
 228	},
 229};
 230
 231static const struct pll_params_table axg_gp0_pll_params_table[] = {
 232	PLL_PARAMS(40, 1),
 233	PLL_PARAMS(41, 1),
 234	PLL_PARAMS(42, 1),
 235	PLL_PARAMS(43, 1),
 236	PLL_PARAMS(44, 1),
 237	PLL_PARAMS(45, 1),
 238	PLL_PARAMS(46, 1),
 239	PLL_PARAMS(47, 1),
 240	PLL_PARAMS(48, 1),
 241	PLL_PARAMS(49, 1),
 242	PLL_PARAMS(50, 1),
 243	PLL_PARAMS(51, 1),
 244	PLL_PARAMS(52, 1),
 245	PLL_PARAMS(53, 1),
 246	PLL_PARAMS(54, 1),
 247	PLL_PARAMS(55, 1),
 248	PLL_PARAMS(56, 1),
 249	PLL_PARAMS(57, 1),
 250	PLL_PARAMS(58, 1),
 251	PLL_PARAMS(59, 1),
 252	PLL_PARAMS(60, 1),
 253	PLL_PARAMS(61, 1),
 254	PLL_PARAMS(62, 1),
 255	PLL_PARAMS(63, 1),
 256	PLL_PARAMS(64, 1),
 257	PLL_PARAMS(65, 1),
 258	PLL_PARAMS(66, 1),
 259	PLL_PARAMS(67, 1),
 260	PLL_PARAMS(68, 1),
 261	{ /* sentinel */ },
 262};
 263
 264static const struct reg_sequence axg_gp0_init_regs[] = {
 265	{ .reg = HHI_GP0_PLL_CNTL1,	.def = 0xc084b000 },
 266	{ .reg = HHI_GP0_PLL_CNTL2,	.def = 0xb75020be },
 267	{ .reg = HHI_GP0_PLL_CNTL3,	.def = 0x0a59a288 },
 268	{ .reg = HHI_GP0_PLL_CNTL4,	.def = 0xc000004d },
 269	{ .reg = HHI_GP0_PLL_CNTL5,	.def = 0x00078000 },
 270};
 271
 272static struct clk_regmap axg_gp0_pll_dco = {
 273	.data = &(struct meson_clk_pll_data){
 274		.en = {
 275			.reg_off = HHI_GP0_PLL_CNTL,
 276			.shift   = 30,
 277			.width   = 1,
 278		},
 279		.m = {
 280			.reg_off = HHI_GP0_PLL_CNTL,
 281			.shift   = 0,
 282			.width   = 9,
 283		},
 284		.n = {
 285			.reg_off = HHI_GP0_PLL_CNTL,
 286			.shift   = 9,
 287			.width   = 5,
 288		},
 289		.frac = {
 290			.reg_off = HHI_GP0_PLL_CNTL1,
 291			.shift   = 0,
 292			.width   = 10,
 293		},
 294		.l = {
 295			.reg_off = HHI_GP0_PLL_CNTL,
 296			.shift   = 31,
 297			.width   = 1,
 298		},
 299		.rst = {
 300			.reg_off = HHI_GP0_PLL_CNTL,
 301			.shift   = 29,
 302			.width   = 1,
 303		},
 304		.table = axg_gp0_pll_params_table,
 305		.init_regs = axg_gp0_init_regs,
 306		.init_count = ARRAY_SIZE(axg_gp0_init_regs),
 307	},
 308	.hw.init = &(struct clk_init_data){
 309		.name = "gp0_pll_dco",
 310		.ops = &meson_clk_pll_ops,
 311		.parent_data = &(const struct clk_parent_data) {
 312			.fw_name = "xtal",
 313		},
 314		.num_parents = 1,
 315	},
 316};
 317
 318static struct clk_regmap axg_gp0_pll = {
 319	.data = &(struct clk_regmap_div_data){
 320		.offset = HHI_GP0_PLL_CNTL,
 321		.shift = 16,
 322		.width = 2,
 323		.flags = CLK_DIVIDER_POWER_OF_TWO,
 324	},
 325	.hw.init = &(struct clk_init_data){
 326		.name = "gp0_pll",
 327		.ops = &clk_regmap_divider_ops,
 328		.parent_hws = (const struct clk_hw *[]) {
 329			&axg_gp0_pll_dco.hw
 330		},
 331		.num_parents = 1,
 332		.flags = CLK_SET_RATE_PARENT,
 333	},
 334};
 335
 336static const struct reg_sequence axg_hifi_pll_init_regs[] = {
 337	{ .reg = HHI_HIFI_PLL_CNTL1,	.def = 0xc084b000 },
 338	{ .reg = HHI_HIFI_PLL_CNTL2,	.def = 0xb75020be },
 339	{ .reg = HHI_HIFI_PLL_CNTL3,	.def = 0x0a6a3a88 },
 340	{ .reg = HHI_HIFI_PLL_CNTL4,	.def = 0xc000004d },
 341	{ .reg = HHI_HIFI_PLL_CNTL5,	.def = 0x00058000 },
 342};
 343
 344static struct clk_regmap axg_hifi_pll_dco = {
 345	.data = &(struct meson_clk_pll_data){
 346		.en = {
 347			.reg_off = HHI_HIFI_PLL_CNTL,
 348			.shift   = 30,
 349			.width   = 1,
 350		},
 351		.m = {
 352			.reg_off = HHI_HIFI_PLL_CNTL,
 353			.shift   = 0,
 354			.width   = 9,
 355		},
 356		.n = {
 357			.reg_off = HHI_HIFI_PLL_CNTL,
 358			.shift   = 9,
 359			.width   = 5,
 360		},
 361		.frac = {
 362			.reg_off = HHI_HIFI_PLL_CNTL5,
 363			.shift   = 0,
 364			.width   = 13,
 365		},
 366		.l = {
 367			.reg_off = HHI_HIFI_PLL_CNTL,
 368			.shift   = 31,
 369			.width   = 1,
 370		},
 371		.rst = {
 372			.reg_off = HHI_HIFI_PLL_CNTL,
 373			.shift   = 29,
 374			.width   = 1,
 375		},
 376		.table = axg_gp0_pll_params_table,
 377		.init_regs = axg_hifi_pll_init_regs,
 378		.init_count = ARRAY_SIZE(axg_hifi_pll_init_regs),
 379		.flags = CLK_MESON_PLL_ROUND_CLOSEST,
 380	},
 381	.hw.init = &(struct clk_init_data){
 382		.name = "hifi_pll_dco",
 383		.ops = &meson_clk_pll_ops,
 384		.parent_data = &(const struct clk_parent_data) {
 385			.fw_name = "xtal",
 386		},
 387		.num_parents = 1,
 388	},
 389};
 390
 391static struct clk_regmap axg_hifi_pll = {
 392	.data = &(struct clk_regmap_div_data){
 393		.offset = HHI_HIFI_PLL_CNTL,
 394		.shift = 16,
 395		.width = 2,
 396		.flags = CLK_DIVIDER_POWER_OF_TWO,
 397	},
 398	.hw.init = &(struct clk_init_data){
 399		.name = "hifi_pll",
 400		.ops = &clk_regmap_divider_ops,
 401		.parent_hws = (const struct clk_hw *[]) {
 402			&axg_hifi_pll_dco.hw
 403		},
 404		.num_parents = 1,
 405		.flags = CLK_SET_RATE_PARENT,
 406	},
 407};
 408
 409static struct clk_fixed_factor axg_fclk_div2_div = {
 410	.mult = 1,
 411	.div = 2,
 412	.hw.init = &(struct clk_init_data){
 413		.name = "fclk_div2_div",
 414		.ops = &clk_fixed_factor_ops,
 415		.parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
 416		.num_parents = 1,
 417	},
 418};
 419
 420static struct clk_regmap axg_fclk_div2 = {
 421	.data = &(struct clk_regmap_gate_data){
 422		.offset = HHI_MPLL_CNTL6,
 423		.bit_idx = 27,
 424	},
 425	.hw.init = &(struct clk_init_data){
 426		.name = "fclk_div2",
 427		.ops = &clk_regmap_gate_ops,
 428		.parent_hws = (const struct clk_hw *[]) {
 429			&axg_fclk_div2_div.hw
 430		},
 431		.num_parents = 1,
 432		.flags = CLK_IS_CRITICAL,
 433	},
 434};
 435
 436static struct clk_fixed_factor axg_fclk_div3_div = {
 437	.mult = 1,
 438	.div = 3,
 439	.hw.init = &(struct clk_init_data){
 440		.name = "fclk_div3_div",
 441		.ops = &clk_fixed_factor_ops,
 442		.parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
 443		.num_parents = 1,
 444	},
 445};
 446
 447static struct clk_regmap axg_fclk_div3 = {
 448	.data = &(struct clk_regmap_gate_data){
 449		.offset = HHI_MPLL_CNTL6,
 450		.bit_idx = 28,
 451	},
 452	.hw.init = &(struct clk_init_data){
 453		.name = "fclk_div3",
 454		.ops = &clk_regmap_gate_ops,
 455		.parent_hws = (const struct clk_hw *[]) {
 456			&axg_fclk_div3_div.hw
 457		},
 458		.num_parents = 1,
 459		/*
 460		 * FIXME:
 461		 * This clock, as fdiv2, is used by the SCPI FW and is required
 462		 * by the platform to operate correctly.
 463		 * Until the following condition are met, we need this clock to
 464		 * be marked as critical:
 465		 * a) The SCPI generic driver claims and enable all the clocks
 466		 *    it needs
 467		 * b) CCF has a clock hand-off mechanism to make the sure the
 468		 *    clock stays on until the proper driver comes along
 469		 */
 470		.flags = CLK_IS_CRITICAL,
 471	},
 472};
 473
 474static struct clk_fixed_factor axg_fclk_div4_div = {
 475	.mult = 1,
 476	.div = 4,
 477	.hw.init = &(struct clk_init_data){
 478		.name = "fclk_div4_div",
 479		.ops = &clk_fixed_factor_ops,
 480		.parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
 481		.num_parents = 1,
 482	},
 483};
 484
 485static struct clk_regmap axg_fclk_div4 = {
 486	.data = &(struct clk_regmap_gate_data){
 487		.offset = HHI_MPLL_CNTL6,
 488		.bit_idx = 29,
 489	},
 490	.hw.init = &(struct clk_init_data){
 491		.name = "fclk_div4",
 492		.ops = &clk_regmap_gate_ops,
 493		.parent_hws = (const struct clk_hw *[]) {
 494			&axg_fclk_div4_div.hw
 495		},
 496		.num_parents = 1,
 497	},
 498};
 499
 500static struct clk_fixed_factor axg_fclk_div5_div = {
 501	.mult = 1,
 502	.div = 5,
 503	.hw.init = &(struct clk_init_data){
 504		.name = "fclk_div5_div",
 505		.ops = &clk_fixed_factor_ops,
 506		.parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
 507		.num_parents = 1,
 508	},
 509};
 510
 511static struct clk_regmap axg_fclk_div5 = {
 512	.data = &(struct clk_regmap_gate_data){
 513		.offset = HHI_MPLL_CNTL6,
 514		.bit_idx = 30,
 515	},
 516	.hw.init = &(struct clk_init_data){
 517		.name = "fclk_div5",
 518		.ops = &clk_regmap_gate_ops,
 519		.parent_hws = (const struct clk_hw *[]) {
 520			&axg_fclk_div5_div.hw
 521		},
 522		.num_parents = 1,
 523	},
 524};
 525
 526static struct clk_fixed_factor axg_fclk_div7_div = {
 527	.mult = 1,
 528	.div = 7,
 529	.hw.init = &(struct clk_init_data){
 530		.name = "fclk_div7_div",
 531		.ops = &clk_fixed_factor_ops,
 532		.parent_hws = (const struct clk_hw *[]) {
 533			&axg_fixed_pll.hw
 534		},
 535		.num_parents = 1,
 536	},
 537};
 538
 539static struct clk_regmap axg_fclk_div7 = {
 540	.data = &(struct clk_regmap_gate_data){
 541		.offset = HHI_MPLL_CNTL6,
 542		.bit_idx = 31,
 543	},
 544	.hw.init = &(struct clk_init_data){
 545		.name = "fclk_div7",
 546		.ops = &clk_regmap_gate_ops,
 547		.parent_hws = (const struct clk_hw *[]) {
 548			&axg_fclk_div7_div.hw
 549		},
 550		.num_parents = 1,
 551	},
 552};
 553
 554static struct clk_regmap axg_mpll_prediv = {
 555	.data = &(struct clk_regmap_div_data){
 556		.offset = HHI_MPLL_CNTL5,
 557		.shift = 12,
 558		.width = 1,
 559	},
 560	.hw.init = &(struct clk_init_data){
 561		.name = "mpll_prediv",
 562		.ops = &clk_regmap_divider_ro_ops,
 563		.parent_hws = (const struct clk_hw *[]) {
 564			&axg_fixed_pll.hw
 565		},
 566		.num_parents = 1,
 567	},
 568};
 569
 570static struct clk_regmap axg_mpll0_div = {
 571	.data = &(struct meson_clk_mpll_data){
 572		.sdm = {
 573			.reg_off = HHI_MPLL_CNTL7,
 574			.shift   = 0,
 575			.width   = 14,
 576		},
 577		.sdm_en = {
 578			.reg_off = HHI_MPLL_CNTL7,
 579			.shift   = 15,
 580			.width	 = 1,
 581		},
 582		.n2 = {
 583			.reg_off = HHI_MPLL_CNTL7,
 584			.shift   = 16,
 585			.width   = 9,
 586		},
 587		.misc = {
 588			.reg_off = HHI_PLL_TOP_MISC,
 589			.shift   = 0,
 590			.width	 = 1,
 591		},
 592		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 593	},
 594	.hw.init = &(struct clk_init_data){
 595		.name = "mpll0_div",
 596		.ops = &meson_clk_mpll_ops,
 597		.parent_hws = (const struct clk_hw *[]) {
 598			&axg_mpll_prediv.hw
 599		},
 600		.num_parents = 1,
 601	},
 602};
 603
 604static struct clk_regmap axg_mpll0 = {
 605	.data = &(struct clk_regmap_gate_data){
 606		.offset = HHI_MPLL_CNTL7,
 607		.bit_idx = 14,
 608	},
 609	.hw.init = &(struct clk_init_data){
 610		.name = "mpll0",
 611		.ops = &clk_regmap_gate_ops,
 612		.parent_hws = (const struct clk_hw *[]) {
 613			&axg_mpll0_div.hw
 614		},
 615		.num_parents = 1,
 616		.flags = CLK_SET_RATE_PARENT,
 617	},
 618};
 619
 620static struct clk_regmap axg_mpll1_div = {
 621	.data = &(struct meson_clk_mpll_data){
 622		.sdm = {
 623			.reg_off = HHI_MPLL_CNTL8,
 624			.shift   = 0,
 625			.width   = 14,
 626		},
 627		.sdm_en = {
 628			.reg_off = HHI_MPLL_CNTL8,
 629			.shift   = 15,
 630			.width	 = 1,
 631		},
 632		.n2 = {
 633			.reg_off = HHI_MPLL_CNTL8,
 634			.shift   = 16,
 635			.width   = 9,
 636		},
 637		.misc = {
 638			.reg_off = HHI_PLL_TOP_MISC,
 639			.shift   = 1,
 640			.width	 = 1,
 641		},
 642		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 643	},
 644	.hw.init = &(struct clk_init_data){
 645		.name = "mpll1_div",
 646		.ops = &meson_clk_mpll_ops,
 647		.parent_hws = (const struct clk_hw *[]) {
 648			&axg_mpll_prediv.hw
 649		},
 650		.num_parents = 1,
 651	},
 652};
 653
 654static struct clk_regmap axg_mpll1 = {
 655	.data = &(struct clk_regmap_gate_data){
 656		.offset = HHI_MPLL_CNTL8,
 657		.bit_idx = 14,
 658	},
 659	.hw.init = &(struct clk_init_data){
 660		.name = "mpll1",
 661		.ops = &clk_regmap_gate_ops,
 662		.parent_hws = (const struct clk_hw *[]) {
 663			&axg_mpll1_div.hw
 664		},
 665		.num_parents = 1,
 666		.flags = CLK_SET_RATE_PARENT,
 667	},
 668};
 669
 670static struct clk_regmap axg_mpll2_div = {
 671	.data = &(struct meson_clk_mpll_data){
 672		.sdm = {
 673			.reg_off = HHI_MPLL_CNTL9,
 674			.shift   = 0,
 675			.width   = 14,
 676		},
 677		.sdm_en = {
 678			.reg_off = HHI_MPLL_CNTL9,
 679			.shift   = 15,
 680			.width	 = 1,
 681		},
 682		.n2 = {
 683			.reg_off = HHI_MPLL_CNTL9,
 684			.shift   = 16,
 685			.width   = 9,
 686		},
 687		.ssen = {
 688			.reg_off = HHI_MPLL_CNTL,
 689			.shift   = 25,
 690			.width	 = 1,
 691		},
 692		.misc = {
 693			.reg_off = HHI_PLL_TOP_MISC,
 694			.shift   = 2,
 695			.width	 = 1,
 696		},
 697		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 698	},
 699	.hw.init = &(struct clk_init_data){
 700		.name = "mpll2_div",
 701		.ops = &meson_clk_mpll_ops,
 702		.parent_hws = (const struct clk_hw *[]) {
 703			&axg_mpll_prediv.hw
 704		},
 705		.num_parents = 1,
 706	},
 707};
 708
 709static struct clk_regmap axg_mpll2 = {
 710	.data = &(struct clk_regmap_gate_data){
 711		.offset = HHI_MPLL_CNTL9,
 712		.bit_idx = 14,
 713	},
 714	.hw.init = &(struct clk_init_data){
 715		.name = "mpll2",
 716		.ops = &clk_regmap_gate_ops,
 717		.parent_hws = (const struct clk_hw *[]) {
 718			&axg_mpll2_div.hw
 719		},
 720		.num_parents = 1,
 721		.flags = CLK_SET_RATE_PARENT,
 722	},
 723};
 724
 725static struct clk_regmap axg_mpll3_div = {
 726	.data = &(struct meson_clk_mpll_data){
 727		.sdm = {
 728			.reg_off = HHI_MPLL3_CNTL0,
 729			.shift   = 12,
 730			.width   = 14,
 731		},
 732		.sdm_en = {
 733			.reg_off = HHI_MPLL3_CNTL0,
 734			.shift   = 11,
 735			.width	 = 1,
 736		},
 737		.n2 = {
 738			.reg_off = HHI_MPLL3_CNTL0,
 739			.shift   = 2,
 740			.width   = 9,
 741		},
 742		.misc = {
 743			.reg_off = HHI_PLL_TOP_MISC,
 744			.shift   = 3,
 745			.width	 = 1,
 746		},
 747		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,
 748	},
 749	.hw.init = &(struct clk_init_data){
 750		.name = "mpll3_div",
 751		.ops = &meson_clk_mpll_ops,
 752		.parent_hws = (const struct clk_hw *[]) {
 753			&axg_mpll_prediv.hw
 754		},
 755		.num_parents = 1,
 756	},
 757};
 758
 759static struct clk_regmap axg_mpll3 = {
 760	.data = &(struct clk_regmap_gate_data){
 761		.offset = HHI_MPLL3_CNTL0,
 762		.bit_idx = 0,
 763	},
 764	.hw.init = &(struct clk_init_data){
 765		.name = "mpll3",
 766		.ops = &clk_regmap_gate_ops,
 767		.parent_hws = (const struct clk_hw *[]) {
 768			&axg_mpll3_div.hw
 769		},
 770		.num_parents = 1,
 771		.flags = CLK_SET_RATE_PARENT,
 772	},
 773};
 774
 775static const struct pll_params_table axg_pcie_pll_params_table[] = {
 776	{
 777		.m = 200,
 778		.n = 3,
 779	},
 780	{ /* sentinel */ },
 781};
 782
 783static const struct reg_sequence axg_pcie_pll_init_regs[] = {
 784	{ .reg = HHI_PCIE_PLL_CNTL1,	.def = 0x0084a2aa },
 785	{ .reg = HHI_PCIE_PLL_CNTL2,	.def = 0xb75020be },
 786	{ .reg = HHI_PCIE_PLL_CNTL3,	.def = 0x0a47488e },
 787	{ .reg = HHI_PCIE_PLL_CNTL4,	.def = 0xc000004d },
 788	{ .reg = HHI_PCIE_PLL_CNTL5,	.def = 0x00078000 },
 789	{ .reg = HHI_PCIE_PLL_CNTL6,	.def = 0x002323c6 },
 790	{ .reg = HHI_PCIE_PLL_CNTL,     .def = 0x400106c8 },
 791};
 792
 793static struct clk_regmap axg_pcie_pll_dco = {
 794	.data = &(struct meson_clk_pll_data){
 795		.en = {
 796			.reg_off = HHI_PCIE_PLL_CNTL,
 797			.shift   = 30,
 798			.width   = 1,
 799		},
 800		.m = {
 801			.reg_off = HHI_PCIE_PLL_CNTL,
 802			.shift   = 0,
 803			.width   = 9,
 804		},
 805		.n = {
 806			.reg_off = HHI_PCIE_PLL_CNTL,
 807			.shift   = 9,
 808			.width   = 5,
 809		},
 810		.frac = {
 811			.reg_off = HHI_PCIE_PLL_CNTL1,
 812			.shift   = 0,
 813			.width   = 12,
 814		},
 815		.l = {
 816			.reg_off = HHI_PCIE_PLL_CNTL,
 817			.shift   = 31,
 818			.width   = 1,
 819		},
 820		.rst = {
 821			.reg_off = HHI_PCIE_PLL_CNTL,
 822			.shift   = 29,
 823			.width   = 1,
 824		},
 825		.table = axg_pcie_pll_params_table,
 826		.init_regs = axg_pcie_pll_init_regs,
 827		.init_count = ARRAY_SIZE(axg_pcie_pll_init_regs),
 828	},
 829	.hw.init = &(struct clk_init_data){
 830		.name = "pcie_pll_dco",
 831		.ops = &meson_clk_pll_ops,
 832		.parent_data = &(const struct clk_parent_data) {
 833			.fw_name = "xtal",
 834		},
 835		.num_parents = 1,
 836	},
 837};
 838
 839static struct clk_regmap axg_pcie_pll_od = {
 840	.data = &(struct clk_regmap_div_data){
 841		.offset = HHI_PCIE_PLL_CNTL,
 842		.shift = 16,
 843		.width = 2,
 844		.flags = CLK_DIVIDER_POWER_OF_TWO,
 845	},
 846	.hw.init = &(struct clk_init_data){
 847		.name = "pcie_pll_od",
 848		.ops = &clk_regmap_divider_ops,
 849		.parent_hws = (const struct clk_hw *[]) {
 850			&axg_pcie_pll_dco.hw
 851		},
 852		.num_parents = 1,
 853		.flags = CLK_SET_RATE_PARENT,
 854	},
 855};
 856
 857static struct clk_regmap axg_pcie_pll = {
 858	.data = &(struct clk_regmap_div_data){
 859		.offset = HHI_PCIE_PLL_CNTL6,
 860		.shift = 6,
 861		.width = 2,
 862		.flags = CLK_DIVIDER_POWER_OF_TWO,
 863	},
 864	.hw.init = &(struct clk_init_data){
 865		.name = "pcie_pll",
 866		.ops = &clk_regmap_divider_ops,
 867		.parent_hws = (const struct clk_hw *[]) {
 868			&axg_pcie_pll_od.hw
 869		},
 870		.num_parents = 1,
 871		.flags = CLK_SET_RATE_PARENT,
 872	},
 873};
 874
 875static struct clk_regmap axg_pcie_mux = {
 876	.data = &(struct clk_regmap_mux_data){
 877		.offset = HHI_PCIE_PLL_CNTL6,
 878		.mask = 0x1,
 879		.shift = 2,
 880		/* skip the parent mpll3, reserved for debug */
 881		.table = (u32[]){ 1 },
 882	},
 883	.hw.init = &(struct clk_init_data){
 884		.name = "pcie_mux",
 885		.ops = &clk_regmap_mux_ops,
 886		.parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw },
 887		.num_parents = 1,
 888		.flags = CLK_SET_RATE_PARENT,
 889	},
 890};
 891
 892static struct clk_regmap axg_pcie_ref = {
 893	.data = &(struct clk_regmap_mux_data){
 894		.offset = HHI_PCIE_PLL_CNTL6,
 895		.mask = 0x1,
 896		.shift = 1,
 897		/* skip the parent 0, reserved for debug */
 898		.table = (u32[]){ 1 },
 899	},
 900	.hw.init = &(struct clk_init_data){
 901		.name = "pcie_ref",
 902		.ops = &clk_regmap_mux_ops,
 903		.parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw },
 904		.num_parents = 1,
 905		.flags = CLK_SET_RATE_PARENT,
 906	},
 907};
 908
 909static struct clk_regmap axg_pcie_cml_en0 = {
 910	.data = &(struct clk_regmap_gate_data){
 911		.offset = HHI_PCIE_PLL_CNTL6,
 912		.bit_idx = 4,
 913	},
 914	.hw.init = &(struct clk_init_data) {
 915		.name = "pcie_cml_en0",
 916		.ops = &clk_regmap_gate_ops,
 917		.parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
 918		.num_parents = 1,
 919		.flags = CLK_SET_RATE_PARENT,
 920
 921	},
 922};
 923
 924static struct clk_regmap axg_pcie_cml_en1 = {
 925	.data = &(struct clk_regmap_gate_data){
 926		.offset = HHI_PCIE_PLL_CNTL6,
 927		.bit_idx = 3,
 928	},
 929	.hw.init = &(struct clk_init_data) {
 930		.name = "pcie_cml_en1",
 931		.ops = &clk_regmap_gate_ops,
 932		.parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
 933		.num_parents = 1,
 934		.flags = CLK_SET_RATE_PARENT,
 935	},
 936};
 937
 938/* clk81 is often referred as "mpeg_clk" */
 939static u32 clk81_parents_val_table[] = { 0, 2, 3, 4, 5, 6, 7 };
 940static const struct clk_parent_data clk81_parents[] = {
 941	{ .fw_name = "xtal", },
 942	{ .hw = &axg_fclk_div7.hw },
 943	{ .hw = &axg_mpll1.hw },
 944	{ .hw = &axg_mpll2.hw },
 945	{ .hw = &axg_fclk_div4.hw },
 946	{ .hw = &axg_fclk_div3.hw },
 947	{ .hw = &axg_fclk_div5.hw },
 948};
 949
 950static struct clk_regmap axg_clk81_sel = {
 951	.data = &(struct clk_regmap_mux_data){
 952		.offset = HHI_MPEG_CLK_CNTL,
 953		.mask = 0x7,
 954		.shift = 12,
 955		.table = clk81_parents_val_table,
 956	},
 957	.hw.init = &(struct clk_init_data){
 958		.name = "clk81_sel",
 959		.ops = &clk_regmap_mux_ro_ops,
 960		.parent_data = clk81_parents,
 961		.num_parents = ARRAY_SIZE(clk81_parents),
 962	},
 963};
 964
 965static struct clk_regmap axg_clk81_div = {
 966	.data = &(struct clk_regmap_div_data){
 967		.offset = HHI_MPEG_CLK_CNTL,
 968		.shift = 0,
 969		.width = 7,
 970	},
 971	.hw.init = &(struct clk_init_data){
 972		.name = "clk81_div",
 973		.ops = &clk_regmap_divider_ops,
 974		.parent_hws = (const struct clk_hw *[]) {
 975			&axg_clk81_sel.hw
 976		},
 977		.num_parents = 1,
 978		.flags = CLK_SET_RATE_PARENT,
 979	},
 980};
 981
 982static struct clk_regmap axg_clk81 = {
 983	.data = &(struct clk_regmap_gate_data){
 984		.offset = HHI_MPEG_CLK_CNTL,
 985		.bit_idx = 7,
 986	},
 987	.hw.init = &(struct clk_init_data){
 988		.name = "clk81",
 989		.ops = &clk_regmap_gate_ops,
 990		.parent_hws = (const struct clk_hw *[]) {
 991			&axg_clk81_div.hw
 992		},
 993		.num_parents = 1,
 994		.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
 995	},
 996};
 997
 998static const struct clk_parent_data axg_sd_emmc_clk0_parents[] = {
 999	{ .fw_name = "xtal", },
1000	{ .hw = &axg_fclk_div2.hw },
1001	{ .hw = &axg_fclk_div3.hw },
1002	{ .hw = &axg_fclk_div5.hw },
1003	{ .hw = &axg_fclk_div7.hw },
1004	/*
1005	 * Following these parent clocks, we should also have had mpll2, mpll3
1006	 * and gp0_pll but these clocks are too precious to be used here. All
1007	 * the necessary rates for MMC and NAND operation can be achieved using
1008	 * xtal or fclk_div clocks
1009	 */
1010};
1011
1012/* SDcard clock */
1013static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
1014	.data = &(struct clk_regmap_mux_data){
1015		.offset = HHI_SD_EMMC_CLK_CNTL,
1016		.mask = 0x7,
1017		.shift = 25,
1018	},
1019	.hw.init = &(struct clk_init_data) {
1020		.name = "sd_emmc_b_clk0_sel",
1021		.ops = &clk_regmap_mux_ops,
1022		.parent_data = axg_sd_emmc_clk0_parents,
1023		.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parents),
1024		.flags = CLK_SET_RATE_PARENT,
1025	},
1026};
1027
1028static struct clk_regmap axg_sd_emmc_b_clk0_div = {
1029	.data = &(struct clk_regmap_div_data){
1030		.offset = HHI_SD_EMMC_CLK_CNTL,
1031		.shift = 16,
1032		.width = 7,
1033		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1034	},
1035	.hw.init = &(struct clk_init_data) {
1036		.name = "sd_emmc_b_clk0_div",
1037		.ops = &clk_regmap_divider_ops,
1038		.parent_hws = (const struct clk_hw *[]) {
1039			&axg_sd_emmc_b_clk0_sel.hw
1040		},
1041		.num_parents = 1,
1042		.flags = CLK_SET_RATE_PARENT,
1043	},
1044};
1045
1046static struct clk_regmap axg_sd_emmc_b_clk0 = {
1047	.data = &(struct clk_regmap_gate_data){
1048		.offset = HHI_SD_EMMC_CLK_CNTL,
1049		.bit_idx = 23,
1050	},
1051	.hw.init = &(struct clk_init_data){
1052		.name = "sd_emmc_b_clk0",
1053		.ops = &clk_regmap_gate_ops,
1054		.parent_hws = (const struct clk_hw *[]) {
1055			&axg_sd_emmc_b_clk0_div.hw
1056		},
1057		.num_parents = 1,
1058		.flags = CLK_SET_RATE_PARENT,
1059	},
1060};
1061
1062/* EMMC/NAND clock */
1063static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
1064	.data = &(struct clk_regmap_mux_data){
1065		.offset = HHI_NAND_CLK_CNTL,
1066		.mask = 0x7,
1067		.shift = 9,
1068	},
1069	.hw.init = &(struct clk_init_data) {
1070		.name = "sd_emmc_c_clk0_sel",
1071		.ops = &clk_regmap_mux_ops,
1072		.parent_data = axg_sd_emmc_clk0_parents,
1073		.num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parents),
1074		.flags = CLK_SET_RATE_PARENT,
1075	},
1076};
1077
1078static struct clk_regmap axg_sd_emmc_c_clk0_div = {
1079	.data = &(struct clk_regmap_div_data){
1080		.offset = HHI_NAND_CLK_CNTL,
1081		.shift = 0,
1082		.width = 7,
1083		.flags = CLK_DIVIDER_ROUND_CLOSEST,
1084	},
1085	.hw.init = &(struct clk_init_data) {
1086		.name = "sd_emmc_c_clk0_div",
1087		.ops = &clk_regmap_divider_ops,
1088		.parent_hws = (const struct clk_hw *[]) {
1089			&axg_sd_emmc_c_clk0_sel.hw
1090		},
1091		.num_parents = 1,
1092		.flags = CLK_SET_RATE_PARENT,
1093	},
1094};
1095
1096static struct clk_regmap axg_sd_emmc_c_clk0 = {
1097	.data = &(struct clk_regmap_gate_data){
1098		.offset = HHI_NAND_CLK_CNTL,
1099		.bit_idx = 7,
1100	},
1101	.hw.init = &(struct clk_init_data){
1102		.name = "sd_emmc_c_clk0",
1103		.ops = &clk_regmap_gate_ops,
1104		.parent_hws = (const struct clk_hw *[]) {
1105			&axg_sd_emmc_c_clk0_div.hw
1106		},
1107		.num_parents = 1,
1108		.flags = CLK_SET_RATE_PARENT,
1109	},
1110};
1111
1112/* VPU Clock */
1113
1114static const struct clk_hw *axg_vpu_parents[] = {
1115	&axg_fclk_div4.hw,
1116	&axg_fclk_div3.hw,
1117	&axg_fclk_div5.hw,
1118	&axg_fclk_div7.hw,
1119};
1120
1121static struct clk_regmap axg_vpu_0_sel = {
1122	.data = &(struct clk_regmap_mux_data){
1123		.offset = HHI_VPU_CLK_CNTL,
1124		.mask = 0x3,
1125		.shift = 9,
1126	},
1127	.hw.init = &(struct clk_init_data){
1128		.name = "vpu_0_sel",
1129		.ops = &clk_regmap_mux_ops,
1130		.parent_hws = axg_vpu_parents,
1131		.num_parents = ARRAY_SIZE(axg_vpu_parents),
1132		/* We need a specific parent for VPU clock source, let it be set in DT */
1133		.flags = CLK_SET_RATE_NO_REPARENT,
1134	},
1135};
1136
1137static struct clk_regmap axg_vpu_0_div = {
1138	.data = &(struct clk_regmap_div_data){
1139		.offset = HHI_VPU_CLK_CNTL,
1140		.shift = 0,
1141		.width = 7,
1142	},
1143	.hw.init = &(struct clk_init_data){
1144		.name = "vpu_0_div",
1145		.ops = &clk_regmap_divider_ops,
1146		.parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_sel.hw },
1147		.num_parents = 1,
1148		.flags = CLK_SET_RATE_PARENT,
1149	},
1150};
1151
1152static struct clk_regmap axg_vpu_0 = {
1153	.data = &(struct clk_regmap_gate_data){
1154		.offset = HHI_VPU_CLK_CNTL,
1155		.bit_idx = 8,
1156	},
1157	.hw.init = &(struct clk_init_data) {
1158		.name = "vpu_0",
1159		.ops = &clk_regmap_gate_ops,
1160		.parent_hws = (const struct clk_hw *[]) { &axg_vpu_0_div.hw },
1161		.num_parents = 1,
1162		/*
1163		 * We want to avoid CCF to disable the VPU clock if
1164		 * display has been set by Bootloader
1165		 */
1166		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1167	},
1168};
1169
1170static struct clk_regmap axg_vpu_1_sel = {
1171	.data = &(struct clk_regmap_mux_data){
1172		.offset = HHI_VPU_CLK_CNTL,
1173		.mask = 0x3,
1174		.shift = 25,
1175	},
1176	.hw.init = &(struct clk_init_data){
1177		.name = "vpu_1_sel",
1178		.ops = &clk_regmap_mux_ops,
1179		.parent_hws = axg_vpu_parents,
1180		.num_parents = ARRAY_SIZE(axg_vpu_parents),
1181		/* We need a specific parent for VPU clock source, let it be set in DT */
1182		.flags = CLK_SET_RATE_NO_REPARENT,
1183	},
1184};
1185
1186static struct clk_regmap axg_vpu_1_div = {
1187	.data = &(struct clk_regmap_div_data){
1188		.offset = HHI_VPU_CLK_CNTL,
1189		.shift = 16,
1190		.width = 7,
1191	},
1192	.hw.init = &(struct clk_init_data){
1193		.name = "vpu_1_div",
1194		.ops = &clk_regmap_divider_ops,
1195		.parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_sel.hw },
1196		.num_parents = 1,
1197		.flags = CLK_SET_RATE_PARENT,
1198	},
1199};
1200
1201static struct clk_regmap axg_vpu_1 = {
1202	.data = &(struct clk_regmap_gate_data){
1203		.offset = HHI_VPU_CLK_CNTL,
1204		.bit_idx = 24,
1205	},
1206	.hw.init = &(struct clk_init_data) {
1207		.name = "vpu_1",
1208		.ops = &clk_regmap_gate_ops,
1209		.parent_hws = (const struct clk_hw *[]) { &axg_vpu_1_div.hw },
1210		.num_parents = 1,
1211		/*
1212		 * We want to avoid CCF to disable the VPU clock if
1213		 * display has been set by Bootloader
1214		 */
1215		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1216	},
1217};
1218
1219static struct clk_regmap axg_vpu = {
1220	.data = &(struct clk_regmap_mux_data){
1221		.offset = HHI_VPU_CLK_CNTL,
1222		.mask = 1,
1223		.shift = 31,
1224	},
1225	.hw.init = &(struct clk_init_data){
1226		.name = "vpu",
1227		.ops = &clk_regmap_mux_ops,
1228		.parent_hws = (const struct clk_hw *[]) {
1229			&axg_vpu_0.hw,
1230			&axg_vpu_1.hw
1231		},
1232		.num_parents = 2,
1233		.flags = CLK_SET_RATE_NO_REPARENT,
1234	},
1235};
1236
1237/* VAPB Clock */
1238
1239static struct clk_regmap axg_vapb_0_sel = {
1240	.data = &(struct clk_regmap_mux_data){
1241		.offset = HHI_VAPBCLK_CNTL,
1242		.mask = 0x3,
1243		.shift = 9,
1244	},
1245	.hw.init = &(struct clk_init_data){
1246		.name = "vapb_0_sel",
1247		.ops = &clk_regmap_mux_ops,
1248		.parent_hws = axg_vpu_parents,
1249		.num_parents = ARRAY_SIZE(axg_vpu_parents),
1250		.flags = CLK_SET_RATE_NO_REPARENT,
1251	},
1252};
1253
1254static struct clk_regmap axg_vapb_0_div = {
1255	.data = &(struct clk_regmap_div_data){
1256		.offset = HHI_VAPBCLK_CNTL,
1257		.shift = 0,
1258		.width = 7,
1259	},
1260	.hw.init = &(struct clk_init_data){
1261		.name = "vapb_0_div",
1262		.ops = &clk_regmap_divider_ops,
1263		.parent_hws = (const struct clk_hw *[]) {
1264			&axg_vapb_0_sel.hw
1265		},
1266		.num_parents = 1,
1267		.flags = CLK_SET_RATE_PARENT,
1268	},
1269};
1270
1271static struct clk_regmap axg_vapb_0 = {
1272	.data = &(struct clk_regmap_gate_data){
1273		.offset = HHI_VAPBCLK_CNTL,
1274		.bit_idx = 8,
1275	},
1276	.hw.init = &(struct clk_init_data) {
1277		.name = "vapb_0",
1278		.ops = &clk_regmap_gate_ops,
1279		.parent_hws = (const struct clk_hw *[]) {
1280			&axg_vapb_0_div.hw
1281		},
1282		.num_parents = 1,
1283		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1284	},
1285};
1286
1287static struct clk_regmap axg_vapb_1_sel = {
1288	.data = &(struct clk_regmap_mux_data){
1289		.offset = HHI_VAPBCLK_CNTL,
1290		.mask = 0x3,
1291		.shift = 25,
1292	},
1293	.hw.init = &(struct clk_init_data){
1294		.name = "vapb_1_sel",
1295		.ops = &clk_regmap_mux_ops,
1296		.parent_hws = axg_vpu_parents,
1297		.num_parents = ARRAY_SIZE(axg_vpu_parents),
1298		.flags = CLK_SET_RATE_NO_REPARENT,
1299	},
1300};
1301
1302static struct clk_regmap axg_vapb_1_div = {
1303	.data = &(struct clk_regmap_div_data){
1304		.offset = HHI_VAPBCLK_CNTL,
1305		.shift = 16,
1306		.width = 7,
1307	},
1308	.hw.init = &(struct clk_init_data){
1309		.name = "vapb_1_div",
1310		.ops = &clk_regmap_divider_ops,
1311		.parent_hws = (const struct clk_hw *[]) {
1312			&axg_vapb_1_sel.hw
1313		},
1314		.num_parents = 1,
1315		.flags = CLK_SET_RATE_PARENT,
1316	},
1317};
1318
1319static struct clk_regmap axg_vapb_1 = {
1320	.data = &(struct clk_regmap_gate_data){
1321		.offset = HHI_VAPBCLK_CNTL,
1322		.bit_idx = 24,
1323	},
1324	.hw.init = &(struct clk_init_data) {
1325		.name = "vapb_1",
1326		.ops = &clk_regmap_gate_ops,
1327		.parent_hws = (const struct clk_hw *[]) {
1328			&axg_vapb_1_div.hw
1329		},
1330		.num_parents = 1,
1331		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1332	},
1333};
1334
1335static struct clk_regmap axg_vapb_sel = {
1336	.data = &(struct clk_regmap_mux_data){
1337		.offset = HHI_VAPBCLK_CNTL,
1338		.mask = 1,
1339		.shift = 31,
1340	},
1341	.hw.init = &(struct clk_init_data){
1342		.name = "vapb_sel",
1343		.ops = &clk_regmap_mux_ops,
1344		.parent_hws = (const struct clk_hw *[]) {
1345			&axg_vapb_0.hw,
1346			&axg_vapb_1.hw
1347		},
1348		.num_parents = 2,
1349		.flags = CLK_SET_RATE_NO_REPARENT,
1350	},
1351};
1352
1353static struct clk_regmap axg_vapb = {
1354	.data = &(struct clk_regmap_gate_data){
1355		.offset = HHI_VAPBCLK_CNTL,
1356		.bit_idx = 30,
1357	},
1358	.hw.init = &(struct clk_init_data) {
1359		.name = "vapb",
1360		.ops = &clk_regmap_gate_ops,
1361		.parent_hws = (const struct clk_hw *[]) { &axg_vapb_sel.hw },
1362		.num_parents = 1,
1363		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1364	},
1365};
1366
1367/* Video Clocks */
1368
1369static const struct clk_hw *axg_vclk_parents[] = {
1370	&axg_gp0_pll.hw,
1371	&axg_fclk_div4.hw,
1372	&axg_fclk_div3.hw,
1373	&axg_fclk_div5.hw,
1374	&axg_fclk_div2.hw,
1375	&axg_fclk_div7.hw,
1376	&axg_mpll1.hw,
1377};
1378
1379static struct clk_regmap axg_vclk_sel = {
1380	.data = &(struct clk_regmap_mux_data){
1381		.offset = HHI_VID_CLK_CNTL,
1382		.mask = 0x7,
1383		.shift = 16,
1384	},
1385	.hw.init = &(struct clk_init_data){
1386		.name = "vclk_sel",
1387		.ops = &clk_regmap_mux_ops,
1388		.parent_hws = axg_vclk_parents,
1389		.num_parents = ARRAY_SIZE(axg_vclk_parents),
1390		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1391	},
1392};
1393
1394static struct clk_regmap axg_vclk2_sel = {
1395	.data = &(struct clk_regmap_mux_data){
1396		.offset = HHI_VIID_CLK_CNTL,
1397		.mask = 0x7,
1398		.shift = 16,
1399	},
1400	.hw.init = &(struct clk_init_data){
1401		.name = "vclk2_sel",
1402		.ops = &clk_regmap_mux_ops,
1403		.parent_hws = axg_vclk_parents,
1404		.num_parents = ARRAY_SIZE(axg_vclk_parents),
1405		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1406	},
1407};
1408
1409static struct clk_regmap axg_vclk_input = {
1410	.data = &(struct clk_regmap_gate_data){
1411		.offset = HHI_VID_CLK_DIV,
1412		.bit_idx = 16,
1413	},
1414	.hw.init = &(struct clk_init_data) {
1415		.name = "vclk_input",
1416		.ops = &clk_regmap_gate_ops,
1417		.parent_hws = (const struct clk_hw *[]) { &axg_vclk_sel.hw },
1418		.num_parents = 1,
1419		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1420	},
1421};
1422
1423static struct clk_regmap axg_vclk2_input = {
1424	.data = &(struct clk_regmap_gate_data){
1425		.offset = HHI_VIID_CLK_DIV,
1426		.bit_idx = 16,
1427	},
1428	.hw.init = &(struct clk_init_data) {
1429		.name = "vclk2_input",
1430		.ops = &clk_regmap_gate_ops,
1431		.parent_hws = (const struct clk_hw *[]) { &axg_vclk2_sel.hw },
1432		.num_parents = 1,
1433		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1434	},
1435};
1436
1437static struct clk_regmap axg_vclk_div = {
1438	.data = &(struct clk_regmap_div_data){
1439		.offset = HHI_VID_CLK_DIV,
1440		.shift = 0,
1441		.width = 8,
1442	},
1443	.hw.init = &(struct clk_init_data){
1444		.name = "vclk_div",
1445		.ops = &clk_regmap_divider_ops,
1446		.parent_hws = (const struct clk_hw *[]) {
1447			&axg_vclk_input.hw
1448		},
1449		.num_parents = 1,
1450		.flags = CLK_GET_RATE_NOCACHE,
1451	},
1452};
1453
1454static struct clk_regmap axg_vclk2_div = {
1455	.data = &(struct clk_regmap_div_data){
1456		.offset = HHI_VIID_CLK_DIV,
1457		.shift = 0,
1458		.width = 8,
1459	},
1460	.hw.init = &(struct clk_init_data){
1461		.name = "vclk2_div",
1462		.ops = &clk_regmap_divider_ops,
1463		.parent_hws = (const struct clk_hw *[]) {
1464			&axg_vclk2_input.hw
1465		},
1466		.num_parents = 1,
1467		.flags = CLK_GET_RATE_NOCACHE,
1468	},
1469};
1470
1471static struct clk_regmap axg_vclk = {
1472	.data = &(struct clk_regmap_gate_data){
1473		.offset = HHI_VID_CLK_CNTL,
1474		.bit_idx = 19,
1475	},
1476	.hw.init = &(struct clk_init_data) {
1477		.name = "vclk",
1478		.ops = &clk_regmap_gate_ops,
1479		.parent_hws = (const struct clk_hw *[]) { &axg_vclk_div.hw },
1480		.num_parents = 1,
1481		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1482	},
1483};
1484
1485static struct clk_regmap axg_vclk2 = {
1486	.data = &(struct clk_regmap_gate_data){
1487		.offset = HHI_VIID_CLK_CNTL,
1488		.bit_idx = 19,
1489	},
1490	.hw.init = &(struct clk_init_data) {
1491		.name = "vclk2",
1492		.ops = &clk_regmap_gate_ops,
1493		.parent_hws = (const struct clk_hw *[]) { &axg_vclk2_div.hw },
1494		.num_parents = 1,
1495		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1496	},
1497};
1498
1499static struct clk_regmap axg_vclk_div1 = {
1500	.data = &(struct clk_regmap_gate_data){
1501		.offset = HHI_VID_CLK_CNTL,
1502		.bit_idx = 0,
1503	},
1504	.hw.init = &(struct clk_init_data) {
1505		.name = "vclk_div1",
1506		.ops = &clk_regmap_gate_ops,
1507		.parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1508		.num_parents = 1,
1509		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1510	},
1511};
1512
1513static struct clk_regmap axg_vclk_div2_en = {
1514	.data = &(struct clk_regmap_gate_data){
1515		.offset = HHI_VID_CLK_CNTL,
1516		.bit_idx = 1,
1517	},
1518	.hw.init = &(struct clk_init_data) {
1519		.name = "vclk_div2_en",
1520		.ops = &clk_regmap_gate_ops,
1521		.parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1522		.num_parents = 1,
1523		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1524	},
1525};
1526
1527static struct clk_regmap axg_vclk_div4_en = {
1528	.data = &(struct clk_regmap_gate_data){
1529		.offset = HHI_VID_CLK_CNTL,
1530		.bit_idx = 2,
1531	},
1532	.hw.init = &(struct clk_init_data) {
1533		.name = "vclk_div4_en",
1534		.ops = &clk_regmap_gate_ops,
1535		.parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1536		.num_parents = 1,
1537		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1538	},
1539};
1540
1541static struct clk_regmap axg_vclk_div6_en = {
1542	.data = &(struct clk_regmap_gate_data){
1543		.offset = HHI_VID_CLK_CNTL,
1544		.bit_idx = 3,
1545	},
1546	.hw.init = &(struct clk_init_data) {
1547		.name = "vclk_div6_en",
1548		.ops = &clk_regmap_gate_ops,
1549		.parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1550		.num_parents = 1,
1551		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1552	},
1553};
1554
1555static struct clk_regmap axg_vclk_div12_en = {
1556	.data = &(struct clk_regmap_gate_data){
1557		.offset = HHI_VID_CLK_CNTL,
1558		.bit_idx = 4,
1559	},
1560	.hw.init = &(struct clk_init_data) {
1561		.name = "vclk_div12_en",
1562		.ops = &clk_regmap_gate_ops,
1563		.parent_hws = (const struct clk_hw *[]) { &axg_vclk.hw },
1564		.num_parents = 1,
1565		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1566	},
1567};
1568
1569static struct clk_regmap axg_vclk2_div1 = {
1570	.data = &(struct clk_regmap_gate_data){
1571		.offset = HHI_VIID_CLK_CNTL,
1572		.bit_idx = 0,
1573	},
1574	.hw.init = &(struct clk_init_data) {
1575		.name = "vclk2_div1",
1576		.ops = &clk_regmap_gate_ops,
1577		.parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1578		.num_parents = 1,
1579		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1580	},
1581};
1582
1583static struct clk_regmap axg_vclk2_div2_en = {
1584	.data = &(struct clk_regmap_gate_data){
1585		.offset = HHI_VIID_CLK_CNTL,
1586		.bit_idx = 1,
1587	},
1588	.hw.init = &(struct clk_init_data) {
1589		.name = "vclk2_div2_en",
1590		.ops = &clk_regmap_gate_ops,
1591		.parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1592		.num_parents = 1,
1593		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1594	},
1595};
1596
1597static struct clk_regmap axg_vclk2_div4_en = {
1598	.data = &(struct clk_regmap_gate_data){
1599		.offset = HHI_VIID_CLK_CNTL,
1600		.bit_idx = 2,
1601	},
1602	.hw.init = &(struct clk_init_data) {
1603		.name = "vclk2_div4_en",
1604		.ops = &clk_regmap_gate_ops,
1605		.parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1606		.num_parents = 1,
1607		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1608	},
1609};
1610
1611static struct clk_regmap axg_vclk2_div6_en = {
1612	.data = &(struct clk_regmap_gate_data){
1613		.offset = HHI_VIID_CLK_CNTL,
1614		.bit_idx = 3,
1615	},
1616	.hw.init = &(struct clk_init_data) {
1617		.name = "vclk2_div6_en",
1618		.ops = &clk_regmap_gate_ops,
1619		.parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1620		.num_parents = 1,
1621		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1622	},
1623};
1624
1625static struct clk_regmap axg_vclk2_div12_en = {
1626	.data = &(struct clk_regmap_gate_data){
1627		.offset = HHI_VIID_CLK_CNTL,
1628		.bit_idx = 4,
1629	},
1630	.hw.init = &(struct clk_init_data) {
1631		.name = "vclk2_div12_en",
1632		.ops = &clk_regmap_gate_ops,
1633		.parent_hws = (const struct clk_hw *[]) { &axg_vclk2.hw },
1634		.num_parents = 1,
1635		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1636	},
1637};
1638
1639static struct clk_fixed_factor axg_vclk_div2 = {
1640	.mult = 1,
1641	.div = 2,
1642	.hw.init = &(struct clk_init_data){
1643		.name = "vclk_div2",
1644		.ops = &clk_fixed_factor_ops,
1645		.parent_hws = (const struct clk_hw *[]) {
1646			&axg_vclk_div2_en.hw
1647		},
1648		.num_parents = 1,
1649	},
1650};
1651
1652static struct clk_fixed_factor axg_vclk_div4 = {
1653	.mult = 1,
1654	.div = 4,
1655	.hw.init = &(struct clk_init_data){
1656		.name = "vclk_div4",
1657		.ops = &clk_fixed_factor_ops,
1658		.parent_hws = (const struct clk_hw *[]) {
1659			&axg_vclk_div4_en.hw
1660		},
1661		.num_parents = 1,
1662	},
1663};
1664
1665static struct clk_fixed_factor axg_vclk_div6 = {
1666	.mult = 1,
1667	.div = 6,
1668	.hw.init = &(struct clk_init_data){
1669		.name = "vclk_div6",
1670		.ops = &clk_fixed_factor_ops,
1671		.parent_hws = (const struct clk_hw *[]) {
1672			&axg_vclk_div6_en.hw
1673		},
1674		.num_parents = 1,
1675	},
1676};
1677
1678static struct clk_fixed_factor axg_vclk_div12 = {
1679	.mult = 1,
1680	.div = 12,
1681	.hw.init = &(struct clk_init_data){
1682		.name = "vclk_div12",
1683		.ops = &clk_fixed_factor_ops,
1684		.parent_hws = (const struct clk_hw *[]) {
1685			&axg_vclk_div12_en.hw
1686		},
1687		.num_parents = 1,
1688	},
1689};
1690
1691static struct clk_fixed_factor axg_vclk2_div2 = {
1692	.mult = 1,
1693	.div = 2,
1694	.hw.init = &(struct clk_init_data){
1695		.name = "vclk2_div2",
1696		.ops = &clk_fixed_factor_ops,
1697		.parent_hws = (const struct clk_hw *[]) {
1698			&axg_vclk2_div2_en.hw
1699		},
1700		.num_parents = 1,
1701	},
1702};
1703
1704static struct clk_fixed_factor axg_vclk2_div4 = {
1705	.mult = 1,
1706	.div = 4,
1707	.hw.init = &(struct clk_init_data){
1708		.name = "vclk2_div4",
1709		.ops = &clk_fixed_factor_ops,
1710		.parent_hws = (const struct clk_hw *[]) {
1711			&axg_vclk2_div4_en.hw
1712		},
1713		.num_parents = 1,
1714	},
1715};
1716
1717static struct clk_fixed_factor axg_vclk2_div6 = {
1718	.mult = 1,
1719	.div = 6,
1720	.hw.init = &(struct clk_init_data){
1721		.name = "vclk2_div6",
1722		.ops = &clk_fixed_factor_ops,
1723		.parent_hws = (const struct clk_hw *[]) {
1724			&axg_vclk2_div6_en.hw
1725		},
1726		.num_parents = 1,
1727	},
1728};
1729
1730static struct clk_fixed_factor axg_vclk2_div12 = {
1731	.mult = 1,
1732	.div = 12,
1733	.hw.init = &(struct clk_init_data){
1734		.name = "vclk2_div12",
1735		.ops = &clk_fixed_factor_ops,
1736		.parent_hws = (const struct clk_hw *[]) {
1737			&axg_vclk2_div12_en.hw
1738		},
1739		.num_parents = 1,
1740	},
1741};
1742
1743static u32 axg_cts_encl_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1744static const struct clk_hw *axg_cts_encl_parents[] = {
1745	&axg_vclk_div1.hw,
1746	&axg_vclk_div2.hw,
1747	&axg_vclk_div4.hw,
1748	&axg_vclk_div6.hw,
1749	&axg_vclk_div12.hw,
1750	&axg_vclk2_div1.hw,
1751	&axg_vclk2_div2.hw,
1752	&axg_vclk2_div4.hw,
1753	&axg_vclk2_div6.hw,
1754	&axg_vclk2_div12.hw,
1755};
1756
1757static struct clk_regmap axg_cts_encl_sel = {
1758	.data = &(struct clk_regmap_mux_data){
1759		.offset = HHI_VIID_CLK_DIV,
1760		.mask = 0xf,
1761		.shift = 12,
1762		.table = axg_cts_encl_parents_val_table,
1763	},
1764	.hw.init = &(struct clk_init_data){
1765		.name = "cts_encl_sel",
1766		.ops = &clk_regmap_mux_ops,
1767		.parent_hws = axg_cts_encl_parents,
1768		.num_parents = ARRAY_SIZE(axg_cts_encl_parents),
1769		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1770	},
1771};
1772
1773static struct clk_regmap axg_cts_encl = {
1774	.data = &(struct clk_regmap_gate_data){
1775		.offset = HHI_VID_CLK_CNTL2,
1776		.bit_idx = 3,
1777	},
1778	.hw.init = &(struct clk_init_data) {
1779		.name = "cts_encl",
1780		.ops = &clk_regmap_gate_ops,
1781		.parent_hws = (const struct clk_hw *[]) {
1782			&axg_cts_encl_sel.hw
1783		},
1784		.num_parents = 1,
1785		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1786	},
1787};
1788
1789/* MIPI DSI Host Clock */
1790
1791static u32 axg_vdin_meas_parents_val_table[] = { 0, 1, 2, 3, 6, 7 };
1792static const struct clk_parent_data axg_vdin_meas_parents[] = {
1793	{ .fw_name = "xtal", },
1794	{ .hw = &axg_fclk_div4.hw },
1795	{ .hw = &axg_fclk_div3.hw },
1796	{ .hw = &axg_fclk_div5.hw },
1797	{ .hw = &axg_fclk_div2.hw },
1798	{ .hw = &axg_fclk_div7.hw },
1799};
1800
1801static struct clk_regmap axg_vdin_meas_sel = {
1802	.data = &(struct clk_regmap_mux_data){
1803		.offset = HHI_VDIN_MEAS_CLK_CNTL,
1804		.mask = 0x7,
1805		.shift = 21,
1806		.flags = CLK_MUX_ROUND_CLOSEST,
1807		.table = axg_vdin_meas_parents_val_table,
1808	},
1809	.hw.init = &(struct clk_init_data){
1810		.name = "vdin_meas_sel",
1811		.ops = &clk_regmap_mux_ops,
1812		.parent_data = axg_vdin_meas_parents,
1813		.num_parents = ARRAY_SIZE(axg_vdin_meas_parents),
1814		.flags = CLK_SET_RATE_PARENT,
1815	},
1816};
1817
1818static struct clk_regmap axg_vdin_meas_div = {
1819	.data = &(struct clk_regmap_div_data){
1820		.offset = HHI_VDIN_MEAS_CLK_CNTL,
1821		.shift = 12,
1822		.width = 7,
1823	},
1824	.hw.init = &(struct clk_init_data){
1825		.name = "vdin_meas_div",
1826		.ops = &clk_regmap_divider_ops,
1827		.parent_hws = (const struct clk_hw *[]) {
1828			&axg_vdin_meas_sel.hw },
1829		.num_parents = 1,
1830		.flags = CLK_SET_RATE_PARENT,
1831	},
1832};
1833
1834static struct clk_regmap axg_vdin_meas = {
1835	.data = &(struct clk_regmap_gate_data){
1836		.offset = HHI_VDIN_MEAS_CLK_CNTL,
1837		.bit_idx = 20,
1838	},
1839	.hw.init = &(struct clk_init_data) {
1840		.name = "vdin_meas",
1841		.ops = &clk_regmap_gate_ops,
1842		.parent_hws = (const struct clk_hw *[]) {
1843			&axg_vdin_meas_div.hw },
1844		.num_parents = 1,
1845		.flags = CLK_SET_RATE_PARENT,
1846	},
1847};
1848
1849static u32 gen_clk_parents_val_table[] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, };
1850static const struct clk_parent_data gen_clk_parents[] = {
1851	{ .fw_name = "xtal", },
1852	{ .hw = &axg_hifi_pll.hw },
1853	{ .hw = &axg_mpll0.hw },
1854	{ .hw = &axg_mpll1.hw },
1855	{ .hw = &axg_mpll2.hw },
1856	{ .hw = &axg_mpll3.hw },
1857	{ .hw = &axg_fclk_div4.hw },
1858	{ .hw = &axg_fclk_div3.hw },
1859	{ .hw = &axg_fclk_div5.hw },
1860	{ .hw = &axg_fclk_div7.hw },
1861	{ .hw = &axg_gp0_pll.hw },
1862};
1863
1864static struct clk_regmap axg_gen_clk_sel = {
1865	.data = &(struct clk_regmap_mux_data){
1866		.offset = HHI_GEN_CLK_CNTL,
1867		.mask = 0xf,
1868		.shift = 12,
1869		.table = gen_clk_parents_val_table,
1870	},
1871	.hw.init = &(struct clk_init_data){
1872		.name = "gen_clk_sel",
1873		.ops = &clk_regmap_mux_ops,
1874		/*
1875		 * bits 15:12 selects from 14 possible parents:
1876		 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
1877		 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
1878		 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
1879		 */
1880		.parent_data = gen_clk_parents,
1881		.num_parents = ARRAY_SIZE(gen_clk_parents),
1882	},
1883};
1884
1885static struct clk_regmap axg_gen_clk_div = {
1886	.data = &(struct clk_regmap_div_data){
1887		.offset = HHI_GEN_CLK_CNTL,
1888		.shift = 0,
1889		.width = 11,
1890	},
1891	.hw.init = &(struct clk_init_data){
1892		.name = "gen_clk_div",
1893		.ops = &clk_regmap_divider_ops,
1894		.parent_hws = (const struct clk_hw *[]) {
1895			&axg_gen_clk_sel.hw
1896		},
1897		.num_parents = 1,
1898		.flags = CLK_SET_RATE_PARENT,
1899	},
1900};
1901
1902static struct clk_regmap axg_gen_clk = {
1903	.data = &(struct clk_regmap_gate_data){
1904		.offset = HHI_GEN_CLK_CNTL,
1905		.bit_idx = 7,
1906	},
1907	.hw.init = &(struct clk_init_data){
1908		.name = "gen_clk",
1909		.ops = &clk_regmap_gate_ops,
1910		.parent_hws = (const struct clk_hw *[]) {
1911			&axg_gen_clk_div.hw
1912		},
1913		.num_parents = 1,
1914		.flags = CLK_SET_RATE_PARENT,
1915	},
1916};
1917
1918static const struct clk_parent_data axg_pclk_parents = { .hw = &axg_clk81.hw };
1919
1920#define AXG_PCLK(_name, _reg, _bit, _flags) \
1921	MESON_PCLK(axg_##_name, _reg, _bit, &axg_pclk_parents, _flags)
1922
1923/*
1924 * Everything Else (EE) domain gates
1925 *
1926 * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons
1927 * Users are encouraged to test without it and submit changes to:
1928 *  - remove the flag if not necessary
1929 *  - replace the flag with something more adequate, such as CLK_IS_CRITICAL,
1930 *    if appropriate.
1931 *  - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable
1932 *    for a particular clock.
1933 */
1934static AXG_PCLK(ddr,			HHI_GCLK_MPEG0,  0, CLK_IGNORE_UNUSED);
1935static AXG_PCLK(audio_locker,		HHI_GCLK_MPEG0,  2, CLK_IGNORE_UNUSED);
1936static AXG_PCLK(mipi_dsi_host,		HHI_GCLK_MPEG0,  3, CLK_IGNORE_UNUSED);
1937static AXG_PCLK(isa,			HHI_GCLK_MPEG0,  5, CLK_IGNORE_UNUSED);
1938static AXG_PCLK(pl301,			HHI_GCLK_MPEG0,  6, CLK_IGNORE_UNUSED);
1939static AXG_PCLK(periphs,		HHI_GCLK_MPEG0,  7, CLK_IGNORE_UNUSED);
1940static AXG_PCLK(spicc_0,		HHI_GCLK_MPEG0,  8, CLK_IGNORE_UNUSED);
1941static AXG_PCLK(i2c,			HHI_GCLK_MPEG0,  9, CLK_IGNORE_UNUSED);
1942static AXG_PCLK(rng0,			HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED);
1943static AXG_PCLK(uart0,			HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED);
1944static AXG_PCLK(mipi_dsi_phy,		HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED);
1945static AXG_PCLK(spicc_1,		HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED);
1946static AXG_PCLK(pcie_a,			HHI_GCLK_MPEG0, 16, CLK_IGNORE_UNUSED);
1947static AXG_PCLK(pcie_b,			HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED);
1948static AXG_PCLK(hiu_reg,		HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED);
1949static AXG_PCLK(assist_misc,		HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED);
1950static AXG_PCLK(emmc_b,			HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED);
1951static AXG_PCLK(emmc_c,			HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED);
1952static AXG_PCLK(dma,			HHI_GCLK_MPEG0, 27, CLK_IGNORE_UNUSED);
1953static AXG_PCLK(spi,			HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED);
1954
1955static AXG_PCLK(audio,			HHI_GCLK_MPEG1,  0, CLK_IGNORE_UNUSED);
1956static AXG_PCLK(eth_core,		HHI_GCLK_MPEG1,  3, CLK_IGNORE_UNUSED);
1957static AXG_PCLK(uart1,			HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED);
1958static AXG_PCLK(g2d,			HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED);
1959static AXG_PCLK(usb0,			HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED);
1960static AXG_PCLK(usb1,			HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED);
1961static AXG_PCLK(reset,			HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED);
1962static AXG_PCLK(usb_general,		HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED);
1963static AXG_PCLK(ahb_arb0,		HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED);
1964static AXG_PCLK(efuse,			HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED);
1965static AXG_PCLK(boot_rom,		HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUSED);
1966
1967static AXG_PCLK(ahb_data_bus,		HHI_GCLK_MPEG2,  1, CLK_IGNORE_UNUSED);
1968static AXG_PCLK(ahb_ctrl_bus,		HHI_GCLK_MPEG2,  2, CLK_IGNORE_UNUSED);
1969static AXG_PCLK(usb1_to_ddr,		HHI_GCLK_MPEG2,  8, CLK_IGNORE_UNUSED);
1970static AXG_PCLK(usb0_to_ddr,		HHI_GCLK_MPEG2,  9, CLK_IGNORE_UNUSED);
1971static AXG_PCLK(mmc_pclk,		HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED);
1972static AXG_PCLK(vpu_intr,		HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED);
1973static AXG_PCLK(sec_ahb_ahb3_bridge,	HHI_GCLK_MPEG2, 26, CLK_IGNORE_UNUSED);
1974static AXG_PCLK(gic,			HHI_GCLK_MPEG2, 30, CLK_IGNORE_UNUSED);
1975
1976/* Always On (AO) domain gates */
1977
1978static AXG_PCLK(ao_media_cpu,		HHI_GCLK_AO, 0, CLK_IGNORE_UNUSED);
1979static AXG_PCLK(ao_ahb_sram,		HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED);
1980static AXG_PCLK(ao_ahb_bus,		HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED);
1981static AXG_PCLK(ao_iface,		HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED);
1982static AXG_PCLK(ao_i2c,			HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED);
1983
1984/* Array of all clocks provided by this provider */
1985
1986static struct clk_hw *axg_hw_clks[] = {
1987	[CLKID_SYS_PLL]			= &axg_sys_pll.hw,
1988	[CLKID_FIXED_PLL]		= &axg_fixed_pll.hw,
1989	[CLKID_FCLK_DIV2]		= &axg_fclk_div2.hw,
1990	[CLKID_FCLK_DIV3]		= &axg_fclk_div3.hw,
1991	[CLKID_FCLK_DIV4]		= &axg_fclk_div4.hw,
1992	[CLKID_FCLK_DIV5]		= &axg_fclk_div5.hw,
1993	[CLKID_FCLK_DIV7]		= &axg_fclk_div7.hw,
1994	[CLKID_GP0_PLL]			= &axg_gp0_pll.hw,
1995	[CLKID_MPEG_SEL]		= &axg_clk81_sel.hw,
1996	[CLKID_MPEG_DIV]		= &axg_clk81_div.hw,
1997	[CLKID_CLK81]			= &axg_clk81.hw,
1998	[CLKID_MPLL0]			= &axg_mpll0.hw,
1999	[CLKID_MPLL1]			= &axg_mpll1.hw,
2000	[CLKID_MPLL2]			= &axg_mpll2.hw,
2001	[CLKID_MPLL3]			= &axg_mpll3.hw,
2002	[CLKID_DDR]			= &axg_ddr.hw,
2003	[CLKID_AUDIO_LOCKER]		= &axg_audio_locker.hw,
2004	[CLKID_MIPI_DSI_HOST]		= &axg_mipi_dsi_host.hw,
2005	[CLKID_ISA]			= &axg_isa.hw,
2006	[CLKID_PL301]			= &axg_pl301.hw,
2007	[CLKID_PERIPHS]			= &axg_periphs.hw,
2008	[CLKID_SPICC0]			= &axg_spicc_0.hw,
2009	[CLKID_I2C]			= &axg_i2c.hw,
2010	[CLKID_RNG0]			= &axg_rng0.hw,
2011	[CLKID_UART0]			= &axg_uart0.hw,
2012	[CLKID_MIPI_DSI_PHY]		= &axg_mipi_dsi_phy.hw,
2013	[CLKID_SPICC1]			= &axg_spicc_1.hw,
2014	[CLKID_PCIE_A]			= &axg_pcie_a.hw,
2015	[CLKID_PCIE_B]			= &axg_pcie_b.hw,
2016	[CLKID_HIU_IFACE]		= &axg_hiu_reg.hw,
2017	[CLKID_ASSIST_MISC]		= &axg_assist_misc.hw,
2018	[CLKID_SD_EMMC_B]		= &axg_emmc_b.hw,
2019	[CLKID_SD_EMMC_C]		= &axg_emmc_c.hw,
2020	[CLKID_DMA]			= &axg_dma.hw,
2021	[CLKID_SPI]			= &axg_spi.hw,
2022	[CLKID_AUDIO]			= &axg_audio.hw,
2023	[CLKID_ETH]			= &axg_eth_core.hw,
2024	[CLKID_UART1]			= &axg_uart1.hw,
2025	[CLKID_G2D]			= &axg_g2d.hw,
2026	[CLKID_USB0]			= &axg_usb0.hw,
2027	[CLKID_USB1]			= &axg_usb1.hw,
2028	[CLKID_RESET]			= &axg_reset.hw,
2029	[CLKID_USB]			= &axg_usb_general.hw,
2030	[CLKID_AHB_ARB0]		= &axg_ahb_arb0.hw,
2031	[CLKID_EFUSE]			= &axg_efuse.hw,
2032	[CLKID_BOOT_ROM]		= &axg_boot_rom.hw,
2033	[CLKID_AHB_DATA_BUS]		= &axg_ahb_data_bus.hw,
2034	[CLKID_AHB_CTRL_BUS]		= &axg_ahb_ctrl_bus.hw,
2035	[CLKID_USB1_DDR_BRIDGE]		= &axg_usb1_to_ddr.hw,
2036	[CLKID_USB0_DDR_BRIDGE]		= &axg_usb0_to_ddr.hw,
2037	[CLKID_MMC_PCLK]		= &axg_mmc_pclk.hw,
2038	[CLKID_VPU_INTR]		= &axg_vpu_intr.hw,
2039	[CLKID_SEC_AHB_AHB3_BRIDGE]	= &axg_sec_ahb_ahb3_bridge.hw,
2040	[CLKID_GIC]			= &axg_gic.hw,
2041	[CLKID_AO_MEDIA_CPU]		= &axg_ao_media_cpu.hw,
2042	[CLKID_AO_AHB_SRAM]		= &axg_ao_ahb_sram.hw,
2043	[CLKID_AO_AHB_BUS]		= &axg_ao_ahb_bus.hw,
2044	[CLKID_AO_IFACE]		= &axg_ao_iface.hw,
2045	[CLKID_AO_I2C]			= &axg_ao_i2c.hw,
2046	[CLKID_SD_EMMC_B_CLK0_SEL]	= &axg_sd_emmc_b_clk0_sel.hw,
2047	[CLKID_SD_EMMC_B_CLK0_DIV]	= &axg_sd_emmc_b_clk0_div.hw,
2048	[CLKID_SD_EMMC_B_CLK0]		= &axg_sd_emmc_b_clk0.hw,
2049	[CLKID_SD_EMMC_C_CLK0_SEL]	= &axg_sd_emmc_c_clk0_sel.hw,
2050	[CLKID_SD_EMMC_C_CLK0_DIV]	= &axg_sd_emmc_c_clk0_div.hw,
2051	[CLKID_SD_EMMC_C_CLK0]		= &axg_sd_emmc_c_clk0.hw,
2052	[CLKID_MPLL0_DIV]		= &axg_mpll0_div.hw,
2053	[CLKID_MPLL1_DIV]		= &axg_mpll1_div.hw,
2054	[CLKID_MPLL2_DIV]		= &axg_mpll2_div.hw,
2055	[CLKID_MPLL3_DIV]		= &axg_mpll3_div.hw,
2056	[CLKID_HIFI_PLL]		= &axg_hifi_pll.hw,
2057	[CLKID_MPLL_PREDIV]		= &axg_mpll_prediv.hw,
2058	[CLKID_FCLK_DIV2_DIV]		= &axg_fclk_div2_div.hw,
2059	[CLKID_FCLK_DIV3_DIV]		= &axg_fclk_div3_div.hw,
2060	[CLKID_FCLK_DIV4_DIV]		= &axg_fclk_div4_div.hw,
2061	[CLKID_FCLK_DIV5_DIV]		= &axg_fclk_div5_div.hw,
2062	[CLKID_FCLK_DIV7_DIV]		= &axg_fclk_div7_div.hw,
2063	[CLKID_PCIE_PLL]		= &axg_pcie_pll.hw,
2064	[CLKID_PCIE_MUX]		= &axg_pcie_mux.hw,
2065	[CLKID_PCIE_REF]		= &axg_pcie_ref.hw,
2066	[CLKID_PCIE_CML_EN0]		= &axg_pcie_cml_en0.hw,
2067	[CLKID_PCIE_CML_EN1]		= &axg_pcie_cml_en1.hw,
2068	[CLKID_GEN_CLK_SEL]		= &axg_gen_clk_sel.hw,
2069	[CLKID_GEN_CLK_DIV]		= &axg_gen_clk_div.hw,
2070	[CLKID_GEN_CLK]			= &axg_gen_clk.hw,
2071	[CLKID_SYS_PLL_DCO]		= &axg_sys_pll_dco.hw,
2072	[CLKID_FIXED_PLL_DCO]		= &axg_fixed_pll_dco.hw,
2073	[CLKID_GP0_PLL_DCO]		= &axg_gp0_pll_dco.hw,
2074	[CLKID_HIFI_PLL_DCO]		= &axg_hifi_pll_dco.hw,
2075	[CLKID_PCIE_PLL_DCO]		= &axg_pcie_pll_dco.hw,
2076	[CLKID_PCIE_PLL_OD]		= &axg_pcie_pll_od.hw,
2077	[CLKID_VPU_0_DIV]		= &axg_vpu_0_div.hw,
2078	[CLKID_VPU_0_SEL]		= &axg_vpu_0_sel.hw,
2079	[CLKID_VPU_0]			= &axg_vpu_0.hw,
2080	[CLKID_VPU_1_DIV]		= &axg_vpu_1_div.hw,
2081	[CLKID_VPU_1_SEL]		= &axg_vpu_1_sel.hw,
2082	[CLKID_VPU_1]			= &axg_vpu_1.hw,
2083	[CLKID_VPU]			= &axg_vpu.hw,
2084	[CLKID_VAPB_0_DIV]		= &axg_vapb_0_div.hw,
2085	[CLKID_VAPB_0_SEL]		= &axg_vapb_0_sel.hw,
2086	[CLKID_VAPB_0]			= &axg_vapb_0.hw,
2087	[CLKID_VAPB_1_DIV]		= &axg_vapb_1_div.hw,
2088	[CLKID_VAPB_1_SEL]		= &axg_vapb_1_sel.hw,
2089	[CLKID_VAPB_1]			= &axg_vapb_1.hw,
2090	[CLKID_VAPB_SEL]		= &axg_vapb_sel.hw,
2091	[CLKID_VAPB]			= &axg_vapb.hw,
2092	[CLKID_VCLK]			= &axg_vclk.hw,
2093	[CLKID_VCLK2]			= &axg_vclk2.hw,
2094	[CLKID_VCLK_SEL]		= &axg_vclk_sel.hw,
2095	[CLKID_VCLK2_SEL]		= &axg_vclk2_sel.hw,
2096	[CLKID_VCLK_INPUT]		= &axg_vclk_input.hw,
2097	[CLKID_VCLK2_INPUT]		= &axg_vclk2_input.hw,
2098	[CLKID_VCLK_DIV]		= &axg_vclk_div.hw,
2099	[CLKID_VCLK2_DIV]		= &axg_vclk2_div.hw,
2100	[CLKID_VCLK_DIV2_EN]		= &axg_vclk_div2_en.hw,
2101	[CLKID_VCLK_DIV4_EN]		= &axg_vclk_div4_en.hw,
2102	[CLKID_VCLK_DIV6_EN]		= &axg_vclk_div6_en.hw,
2103	[CLKID_VCLK_DIV12_EN]		= &axg_vclk_div12_en.hw,
2104	[CLKID_VCLK2_DIV2_EN]		= &axg_vclk2_div2_en.hw,
2105	[CLKID_VCLK2_DIV4_EN]		= &axg_vclk2_div4_en.hw,
2106	[CLKID_VCLK2_DIV6_EN]		= &axg_vclk2_div6_en.hw,
2107	[CLKID_VCLK2_DIV12_EN]		= &axg_vclk2_div12_en.hw,
2108	[CLKID_VCLK_DIV1]		= &axg_vclk_div1.hw,
2109	[CLKID_VCLK_DIV2]		= &axg_vclk_div2.hw,
2110	[CLKID_VCLK_DIV4]		= &axg_vclk_div4.hw,
2111	[CLKID_VCLK_DIV6]		= &axg_vclk_div6.hw,
2112	[CLKID_VCLK_DIV12]		= &axg_vclk_div12.hw,
2113	[CLKID_VCLK2_DIV1]		= &axg_vclk2_div1.hw,
2114	[CLKID_VCLK2_DIV2]		= &axg_vclk2_div2.hw,
2115	[CLKID_VCLK2_DIV4]		= &axg_vclk2_div4.hw,
2116	[CLKID_VCLK2_DIV6]		= &axg_vclk2_div6.hw,
2117	[CLKID_VCLK2_DIV12]		= &axg_vclk2_div12.hw,
2118	[CLKID_CTS_ENCL_SEL]		= &axg_cts_encl_sel.hw,
2119	[CLKID_CTS_ENCL]		= &axg_cts_encl.hw,
2120	[CLKID_VDIN_MEAS_SEL]		= &axg_vdin_meas_sel.hw,
2121	[CLKID_VDIN_MEAS_DIV]		= &axg_vdin_meas_div.hw,
2122	[CLKID_VDIN_MEAS]		= &axg_vdin_meas.hw,
2123};
2124
2125static const struct meson_clkc_data axg_clkc_data = {
2126	.hw_clks = {
2127		.hws = axg_hw_clks,
2128		.num = ARRAY_SIZE(axg_hw_clks),
2129	},
2130};
2131
2132static const struct of_device_id axg_clkc_match_table[] = {
2133	{ .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
2134	{}
2135};
2136MODULE_DEVICE_TABLE(of, axg_clkc_match_table);
2137
2138static struct platform_driver axg_clkc_driver = {
2139	.probe		= meson_clkc_syscon_probe,
2140	.driver		= {
2141		.name	= "axg-clkc",
2142		.of_match_table = axg_clkc_match_table,
2143	},
2144};
2145module_platform_driver(axg_clkc_driver);
2146
2147MODULE_DESCRIPTION("Amlogic AXG Main Clock Controller driver");
2148MODULE_LICENSE("GPL");
2149MODULE_IMPORT_NS("CLK_MESON");