clk-pll.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2014 MediaTek Inc.
  4 * Author: James Liao <jamesjj.liao@mediatek.com>
  5 */
  6
  7#ifndef __DRV_CLK_MTK_PLL_H
  8#define __DRV_CLK_MTK_PLL_H
  9
 10#include <linux/clk-provider.h>
 11#include <linux/types.h>
 12
 13struct clk_ops;
 14struct clk_hw_onecell_data;
 15struct device_node;
 16
 17struct mtk_pll_div_table {
 18	u32 div;
 19	unsigned long freq;
 20};
 21
 22#define HAVE_RST_BAR	BIT(0)
 23#define PLL_AO		BIT(1)
 24#define PLL_PARENT_EN	BIT(2)
 25#define POSTDIV_MASK	GENMASK(2, 0)
 26
 27struct mtk_pll_data {
 28	int id;
 29	const char *name;
 30	u32 reg;
 31	u32 pwr_reg;
 32	u32 en_mask;
 33	u32 fenc_sta_ofs;
 34	u32 pd_reg;
 35	u32 tuner_reg;
 36	u32 tuner_en_reg;
 37	u8 tuner_en_bit;
 38	int pd_shift;
 39	unsigned int flags;
 40	const struct clk_ops *ops;
 41	u32 rst_bar_mask;
 42	unsigned long fmin;
 43	unsigned long fmax;
 44	int pcwbits;
 45	int pcwibits;
 46	u32 pcw_reg;
 47	int pcw_shift;
 48	u32 pcw_chg_reg;
 49	const struct mtk_pll_div_table *div_table;
 50	const char *parent_name;
 51	u32 en_reg;
 52	u32 en_set_reg;
 53	u32 en_clr_reg;
 54	u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
 55	u8 pcw_chg_bit;
 56	u8 fenc_sta_bit;
 57};
 58
 59/*
 60 * MediaTek PLLs are configured through their pcw value. The pcw value describes
 61 * a divider in the PLL feedback loop which consists of 7 bits for the integer
 62 * part and the remaining bits (if present) for the fractional part. Also they
 63 * have a 3 bit power-of-two post divider.
 64 */
 65
 66struct mtk_clk_pll {
 67	struct clk_hw	hw;
 68	void __iomem	*base_addr;
 69	void __iomem	*pd_addr;
 70	void __iomem	*pwr_addr;
 71	void __iomem	*tuner_addr;
 72	void __iomem	*tuner_en_addr;
 73	void __iomem	*pcw_addr;
 74	void __iomem	*pcw_chg_addr;
 75	void __iomem	*en_addr;
 76	void __iomem	*en_set_addr;
 77	void __iomem	*en_clr_addr;
 78	void __iomem	*fenc_addr;
 79	const struct mtk_pll_data *data;
 80};
 81
 82int mtk_clk_register_plls(struct device_node *node,
 83			  const struct mtk_pll_data *plls, int num_plls,
 84			  struct clk_hw_onecell_data *clk_data);
 85void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
 86			     struct clk_hw_onecell_data *clk_data);
 87
 88extern const struct clk_ops mtk_pll_ops;
 89extern const struct clk_ops mtk_pll_fenc_clr_set_ops;
 90
 91static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
 92{
 93	return container_of(hw, struct mtk_clk_pll, hw);
 94}
 95
 96int mtk_pll_is_prepared(struct clk_hw *hw);
 97
 98int mtk_pll_prepare(struct clk_hw *hw);
 99
100void mtk_pll_unprepare(struct clk_hw *hw);
101
102unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate);
103
104void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
105			 u32 freq, u32 fin);
106int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
107		     unsigned long parent_rate);
108int mtk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req);
109
110struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
111					const struct mtk_pll_data *data,
112					void __iomem *base,
113					const struct clk_ops *pll_ops);
114struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
115				    void __iomem *base);
116void mtk_clk_unregister_pll(struct clk_hw *hw);
117
118__iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
119				   const struct mtk_pll_data *data);
120
121#endif /* __DRV_CLK_MTK_PLL_H */