clk-mt8196-venc.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2025 MediaTek Inc.
  4 *                    Guangjie Song <guangjie.song@mediatek.com>
  5 * Copyright (c) 2025 Collabora Ltd.
  6 *                    Laura Nao <laura.nao@collabora.com>
  7 */
  8#include <dt-bindings/clock/mediatek,mt8196-clock.h>
  9
 10#include <linux/clk-provider.h>
 11#include <linux/module.h>
 12#include <linux/of_device.h>
 13#include <linux/platform_device.h>
 14
 15#include "clk-gate.h"
 16#include "clk-mtk.h"
 17
 18static const struct mtk_gate_regs ven10_cg_regs = {
 19	.set_ofs = 0x4,
 20	.clr_ofs = 0x8,
 21	.sta_ofs = 0x0,
 22};
 23
 24static const struct mtk_gate_regs ven10_hwv_regs = {
 25	.set_ofs = 0x00b8,
 26	.clr_ofs = 0x00bc,
 27	.sta_ofs = 0x2c5c,
 28};
 29
 30static const struct mtk_gate_regs ven11_cg_regs = {
 31	.set_ofs = 0x10,
 32	.clr_ofs = 0x14,
 33	.sta_ofs = 0x10,
 34};
 35
 36static const struct mtk_gate_regs ven11_hwv_regs = {
 37	.set_ofs = 0x00c0,
 38	.clr_ofs = 0x00c4,
 39	.sta_ofs = 0x2c60,
 40};
 41
 42#define GATE_VEN10(_id, _name, _parent, _shift) {	\
 43		.id = _id,				\
 44		.name = _name,				\
 45		.parent_name = _parent,			\
 46		.regs = &ven10_cg_regs,			\
 47		.shift = _shift,			\
 48		.flags = CLK_OPS_PARENT_ENABLE,		\
 49		.ops = &mtk_clk_gate_ops_setclr_inv,	\
 50	}
 51
 52#define GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, _flags) {	\
 53		.id = _id,						\
 54		.name = _name,						\
 55		.parent_name = _parent,					\
 56		.regs = &ven10_cg_regs,					\
 57		.hwv_regs = &ven10_hwv_regs,				\
 58		.shift = _shift,					\
 59		.ops = &mtk_clk_gate_hwv_ops_setclr_inv,		\
 60		.flags = (_flags) |					\
 61			 CLK_OPS_PARENT_ENABLE,				\
 62	}
 63
 64#define GATE_HWV_VEN10(_id, _name, _parent, _shift)	\
 65	GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, 0)
 66
 67#define GATE_HWV_VEN11(_id, _name, _parent, _shift) {	\
 68		.id = _id,				\
 69		.name = _name,				\
 70		.parent_name = _parent,			\
 71		.regs = &ven11_cg_regs,			\
 72		.hwv_regs = &ven11_hwv_regs,		\
 73		.shift = _shift,			\
 74		.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
 75		.flags = CLK_OPS_PARENT_ENABLE		\
 76	}
 77
 78static const struct mtk_gate ven1_clks[] = {
 79	/* VEN10 */
 80	GATE_HWV_VEN10(CLK_VEN1_CKE0_LARB, "ven1_larb", "venc", 0),
 81	GATE_HWV_VEN10(CLK_VEN1_CKE1_VENC, "ven1_venc", "venc", 4),
 82	GATE_VEN10(CLK_VEN1_CKE2_JPGENC, "ven1_jpgenc", "venc", 8),
 83	GATE_VEN10(CLK_VEN1_CKE3_JPGDEC, "ven1_jpgdec", "venc", 12),
 84	GATE_VEN10(CLK_VEN1_CKE4_JPGDEC_C1, "ven1_jpgdec_c1", "venc", 16),
 85	GATE_HWV_VEN10(CLK_VEN1_CKE5_GALS, "ven1_gals", "venc", 28),
 86	GATE_HWV_VEN10(CLK_VEN1_CKE29_VENC_ADAB_CTRL, "ven1_venc_adab_ctrl",
 87			"venc", 29),
 88	GATE_HWV_VEN10_FLAGS(CLK_VEN1_CKE29_VENC_XPC_CTRL,
 89			      "ven1_venc_xpc_ctrl", "venc", 30,
 90			      CLK_IGNORE_UNUSED),
 91	GATE_HWV_VEN10(CLK_VEN1_CKE6_GALS_SRAM, "ven1_gals_sram", "venc", 31),
 92	/* VEN11 */
 93	GATE_HWV_VEN11(CLK_VEN1_RES_FLAT, "ven1_res_flat", "venc", 0),
 94};
 95
 96static const struct mtk_clk_desc ven1_mcd = {
 97	.clks = ven1_clks,
 98	.num_clks = ARRAY_SIZE(ven1_clks),
 99	.need_runtime_pm = true,
100};
101
102static const struct mtk_gate_regs ven20_hwv_regs = {
103	.set_ofs = 0x00c8,
104	.clr_ofs = 0x00cc,
105	.sta_ofs = 0x2c64,
106};
107
108static const struct mtk_gate_regs ven21_hwv_regs = {
109	.set_ofs = 0x00d0,
110	.clr_ofs = 0x00d4,
111	.sta_ofs = 0x2c68,
112};
113
114#define GATE_VEN20(_id, _name, _parent, _shift) {	\
115		.id = _id,				\
116		.name = _name,				\
117		.parent_name = _parent,			\
118		.regs = &ven10_cg_regs,			\
119		.shift = _shift,			\
120		.flags = CLK_OPS_PARENT_ENABLE,		\
121		.ops = &mtk_clk_gate_ops_setclr_inv,	\
122	}
123
124#define GATE_HWV_VEN20(_id, _name, _parent, _shift) {	\
125		.id = _id,				\
126		.name = _name,				\
127		.parent_name = _parent,			\
128		.regs = &ven10_cg_regs,			\
129		.hwv_regs = &ven20_hwv_regs,		\
130		.shift = _shift,			\
131		.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
132		.flags = CLK_OPS_PARENT_ENABLE,		\
133	}
134
135#define GATE_HWV_VEN21(_id, _name, _parent, _shift) {	\
136		.id = _id,				\
137		.name = _name,				\
138		.parent_name = _parent,			\
139		.regs = &ven11_cg_regs,			\
140		.hwv_regs = &ven21_hwv_regs,		\
141		.shift = _shift,			\
142		.ops = &mtk_clk_gate_hwv_ops_setclr,	\
143		.flags = CLK_OPS_PARENT_ENABLE		\
144	}
145
146static const struct mtk_gate ven2_clks[] = {
147	/* VEN20 */
148	GATE_HWV_VEN20(CLK_VEN2_CKE0_LARB, "ven2_larb", "venc", 0),
149	GATE_HWV_VEN20(CLK_VEN2_CKE1_VENC, "ven2_venc", "venc", 4),
150	GATE_VEN20(CLK_VEN2_CKE2_JPGENC, "ven2_jpgenc", "venc", 8),
151	GATE_VEN20(CLK_VEN2_CKE3_JPGDEC, "ven2_jpgdec", "venc", 12),
152	GATE_HWV_VEN20(CLK_VEN2_CKE5_GALS, "ven2_gals", "venc", 28),
153	GATE_HWV_VEN20(CLK_VEN2_CKE29_VENC_XPC_CTRL, "ven2_venc_xpc_ctrl", "venc", 30),
154	GATE_HWV_VEN20(CLK_VEN2_CKE6_GALS_SRAM, "ven2_gals_sram", "venc", 31),
155	/* VEN21 */
156	GATE_HWV_VEN21(CLK_VEN2_RES_FLAT, "ven2_res_flat", "venc", 0),
157};
158
159static const struct mtk_clk_desc ven2_mcd = {
160	.clks = ven2_clks,
161	.num_clks = ARRAY_SIZE(ven2_clks),
162	.need_runtime_pm = true,
163};
164
165static const struct mtk_gate_regs ven_c20_hwv_regs = {
166	.set_ofs = 0x00d8,
167	.clr_ofs = 0x00dc,
168	.sta_ofs = 0x2c6c,
169};
170
171static const struct mtk_gate_regs ven_c21_hwv_regs = {
172	.set_ofs = 0x00e0,
173	.clr_ofs = 0x00e4,
174	.sta_ofs = 0x2c70,
175};
176
177#define GATE_HWV_VEN_C20(_id, _name, _parent, _shift) {\
178		.id = _id,				\
179		.name = _name,				\
180		.parent_name = _parent,			\
181		.regs = &ven10_cg_regs,		\
182		.hwv_regs = &ven_c20_hwv_regs,		\
183		.shift = _shift,			\
184		.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
185		.flags = CLK_OPS_PARENT_ENABLE,		\
186	}
187
188#define GATE_HWV_VEN_C21(_id, _name, _parent, _shift) {\
189		.id = _id,				\
190		.name = _name,				\
191		.parent_name = _parent,			\
192		.regs = &ven11_cg_regs,		\
193		.hwv_regs = &ven_c21_hwv_regs,		\
194		.shift = _shift,			\
195		.ops = &mtk_clk_gate_hwv_ops_setclr,	\
196		.flags = CLK_OPS_PARENT_ENABLE,		\
197	}
198
199static const struct mtk_gate ven_c2_clks[] = {
200	/* VEN_C20 */
201	GATE_HWV_VEN_C20(CLK_VEN_C2_CKE0_LARB, "ven_c2_larb", "venc", 0),
202	GATE_HWV_VEN_C20(CLK_VEN_C2_CKE1_VENC, "ven_c2_venc", "venc", 4),
203	GATE_HWV_VEN_C20(CLK_VEN_C2_CKE5_GALS, "ven_c2_gals", "venc", 28),
204	GATE_HWV_VEN_C20(CLK_VEN_C2_CKE29_VENC_XPC_CTRL, "ven_c2_venc_xpc_ctrl",
205			  "venc", 30),
206	GATE_HWV_VEN_C20(CLK_VEN_C2_CKE6_GALS_SRAM, "ven_c2_gals_sram", "venc", 31),
207	/* VEN_C21 */
208	GATE_HWV_VEN_C21(CLK_VEN_C2_RES_FLAT, "ven_c2_res_flat", "venc", 0),
209};
210
211static const struct mtk_clk_desc ven_c2_mcd = {
212	.clks = ven_c2_clks,
213	.num_clks = ARRAY_SIZE(ven_c2_clks),
214	.need_runtime_pm = true,
215};
216
217static const struct of_device_id of_match_clk_mt8196_venc[] = {
218	{ .compatible = "mediatek,mt8196-vencsys", .data = &ven1_mcd },
219	{ .compatible = "mediatek,mt8196-vencsys-c1", .data = &ven2_mcd },
220	{ .compatible = "mediatek,mt8196-vencsys-c2", .data = &ven_c2_mcd },
221	{ /* sentinel */ }
222};
223MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_venc);
224
225static struct platform_driver clk_mt8196_venc_drv = {
226	.probe = mtk_clk_simple_probe,
227	.remove = mtk_clk_simple_remove,
228	.driver = {
229		.name = "clk-mt8196-venc",
230		.of_match_table = of_match_clk_mt8196_venc,
231	},
232};
233module_platform_driver(clk_mt8196_venc_drv);
234
235MODULE_DESCRIPTION("MediaTek MT8196 Video Encoders clocks driver");
236MODULE_LICENSE("GPL");