clk-mt8196-ovl0.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2025 MediaTek Inc.
  4 *                    Guangjie Song <guangjie.song@mediatek.com>
  5 * Copyright (c) 2025 Collabora Ltd.
  6 *                    Laura Nao <laura.nao@collabora.com>
  7 */
  8#include <dt-bindings/clock/mediatek,mt8196-clock.h>
  9
 10#include <linux/clk-provider.h>
 11#include <linux/module.h>
 12#include <linux/of_device.h>
 13#include <linux/platform_device.h>
 14
 15#include "clk-gate.h"
 16#include "clk-mtk.h"
 17
 18static const struct mtk_gate_regs ovl0_cg_regs = {
 19	.set_ofs = 0x104,
 20	.clr_ofs = 0x108,
 21	.sta_ofs = 0x100,
 22};
 23
 24static const struct mtk_gate_regs ovl0_hwv_regs = {
 25	.set_ofs = 0x0060,
 26	.clr_ofs = 0x0064,
 27	.sta_ofs = 0x2c30,
 28};
 29
 30static const struct mtk_gate_regs ovl1_cg_regs = {
 31	.set_ofs = 0x114,
 32	.clr_ofs = 0x118,
 33	.sta_ofs = 0x110,
 34};
 35
 36static const struct mtk_gate_regs ovl1_hwv_regs = {
 37	.set_ofs = 0x0068,
 38	.clr_ofs = 0x006c,
 39	.sta_ofs = 0x2c34,
 40};
 41
 42#define GATE_HWV_OVL0(_id, _name, _parent, _shift) {	\
 43		.id = _id,				\
 44		.name = _name,				\
 45		.parent_name = _parent,			\
 46		.regs = &ovl0_cg_regs,			\
 47		.hwv_regs = &ovl0_hwv_regs,		\
 48		.shift = _shift,			\
 49		.ops = &mtk_clk_gate_hwv_ops_setclr,	\
 50		.flags = CLK_OPS_PARENT_ENABLE,		\
 51	}
 52
 53#define GATE_HWV_OVL1(_id, _name, _parent, _shift) {	\
 54		.id = _id,				\
 55		.name = _name,				\
 56		.parent_name = _parent,			\
 57		.regs = &ovl1_cg_regs,			\
 58		.hwv_regs = &ovl1_hwv_regs,		\
 59		.shift = _shift,			\
 60		.ops = &mtk_clk_gate_hwv_ops_setclr,	\
 61		.flags = CLK_OPS_PARENT_ENABLE,		\
 62	}
 63
 64static const struct mtk_gate ovl_clks[] = {
 65	/* OVL0 */
 66	GATE_HWV_OVL0(CLK_OVLSYS_CONFIG, "ovlsys_config", "disp", 0),
 67	GATE_HWV_OVL0(CLK_OVL_FAKE_ENG0, "ovl_fake_eng0", "disp", 1),
 68	GATE_HWV_OVL0(CLK_OVL_FAKE_ENG1, "ovl_fake_eng1", "disp", 2),
 69	GATE_HWV_OVL0(CLK_OVL_MUTEX0, "ovl_mutex0", "disp", 3),
 70	GATE_HWV_OVL0(CLK_OVL_EXDMA0, "ovl_exdma0", "disp", 4),
 71	GATE_HWV_OVL0(CLK_OVL_EXDMA1, "ovl_exdma1", "disp", 5),
 72	GATE_HWV_OVL0(CLK_OVL_EXDMA2, "ovl_exdma2", "disp", 6),
 73	GATE_HWV_OVL0(CLK_OVL_EXDMA3, "ovl_exdma3", "disp", 7),
 74	GATE_HWV_OVL0(CLK_OVL_EXDMA4, "ovl_exdma4", "disp", 8),
 75	GATE_HWV_OVL0(CLK_OVL_EXDMA5, "ovl_exdma5", "disp", 9),
 76	GATE_HWV_OVL0(CLK_OVL_EXDMA6, "ovl_exdma6", "disp", 10),
 77	GATE_HWV_OVL0(CLK_OVL_EXDMA7, "ovl_exdma7", "disp", 11),
 78	GATE_HWV_OVL0(CLK_OVL_EXDMA8, "ovl_exdma8", "disp", 12),
 79	GATE_HWV_OVL0(CLK_OVL_EXDMA9, "ovl_exdma9", "disp", 13),
 80	GATE_HWV_OVL0(CLK_OVL_BLENDER0, "ovl_blender0", "disp", 14),
 81	GATE_HWV_OVL0(CLK_OVL_BLENDER1, "ovl_blender1", "disp", 15),
 82	GATE_HWV_OVL0(CLK_OVL_BLENDER2, "ovl_blender2", "disp", 16),
 83	GATE_HWV_OVL0(CLK_OVL_BLENDER3, "ovl_blender3", "disp", 17),
 84	GATE_HWV_OVL0(CLK_OVL_BLENDER4, "ovl_blender4", "disp", 18),
 85	GATE_HWV_OVL0(CLK_OVL_BLENDER5, "ovl_blender5", "disp", 19),
 86	GATE_HWV_OVL0(CLK_OVL_BLENDER6, "ovl_blender6", "disp", 20),
 87	GATE_HWV_OVL0(CLK_OVL_BLENDER7, "ovl_blender7", "disp", 21),
 88	GATE_HWV_OVL0(CLK_OVL_BLENDER8, "ovl_blender8", "disp", 22),
 89	GATE_HWV_OVL0(CLK_OVL_BLENDER9, "ovl_blender9", "disp", 23),
 90	GATE_HWV_OVL0(CLK_OVL_OUTPROC0, "ovl_outproc0", "disp", 24),
 91	GATE_HWV_OVL0(CLK_OVL_OUTPROC1, "ovl_outproc1", "disp", 25),
 92	GATE_HWV_OVL0(CLK_OVL_OUTPROC2, "ovl_outproc2", "disp", 26),
 93	GATE_HWV_OVL0(CLK_OVL_OUTPROC3, "ovl_outproc3", "disp", 27),
 94	GATE_HWV_OVL0(CLK_OVL_OUTPROC4, "ovl_outproc4", "disp", 28),
 95	GATE_HWV_OVL0(CLK_OVL_OUTPROC5, "ovl_outproc5", "disp", 29),
 96	GATE_HWV_OVL0(CLK_OVL_MDP_RSZ0, "ovl_mdp_rsz0", "disp", 30),
 97	GATE_HWV_OVL0(CLK_OVL_MDP_RSZ1, "ovl_mdp_rsz1", "disp", 31),
 98	/* OVL1 */
 99	GATE_HWV_OVL1(CLK_OVL_DISP_WDMA0, "ovl_disp_wdma0", "disp", 0),
100	GATE_HWV_OVL1(CLK_OVL_DISP_WDMA1, "ovl_disp_wdma1", "disp", 1),
101	GATE_HWV_OVL1(CLK_OVL_UFBC_WDMA0, "ovl_ufbc_wdma0", "disp", 2),
102	GATE_HWV_OVL1(CLK_OVL_MDP_RDMA0, "ovl_mdp_rdma0", "disp", 3),
103	GATE_HWV_OVL1(CLK_OVL_MDP_RDMA1, "ovl_mdp_rdma1", "disp", 4),
104	GATE_HWV_OVL1(CLK_OVL_BWM0, "ovl_bwm0", "disp", 5),
105	GATE_HWV_OVL1(CLK_OVL_DLI0, "ovl_dli0", "disp", 6),
106	GATE_HWV_OVL1(CLK_OVL_DLI1, "ovl_dli1", "disp", 7),
107	GATE_HWV_OVL1(CLK_OVL_DLI2, "ovl_dli2", "disp", 8),
108	GATE_HWV_OVL1(CLK_OVL_DLI3, "ovl_dli3", "disp", 9),
109	GATE_HWV_OVL1(CLK_OVL_DLI4, "ovl_dli4", "disp", 10),
110	GATE_HWV_OVL1(CLK_OVL_DLI5, "ovl_dli5", "disp", 11),
111	GATE_HWV_OVL1(CLK_OVL_DLI6, "ovl_dli6", "disp", 12),
112	GATE_HWV_OVL1(CLK_OVL_DLI7, "ovl_dli7", "disp", 13),
113	GATE_HWV_OVL1(CLK_OVL_DLI8, "ovl_dli8", "disp", 14),
114	GATE_HWV_OVL1(CLK_OVL_DLO0, "ovl_dlo0", "disp", 15),
115	GATE_HWV_OVL1(CLK_OVL_DLO1, "ovl_dlo1", "disp", 16),
116	GATE_HWV_OVL1(CLK_OVL_DLO2, "ovl_dlo2", "disp", 17),
117	GATE_HWV_OVL1(CLK_OVL_DLO3, "ovl_dlo3", "disp", 18),
118	GATE_HWV_OVL1(CLK_OVL_DLO4, "ovl_dlo4", "disp", 19),
119	GATE_HWV_OVL1(CLK_OVL_DLO5, "ovl_dlo5", "disp", 20),
120	GATE_HWV_OVL1(CLK_OVL_DLO6, "ovl_dlo6", "disp", 21),
121	GATE_HWV_OVL1(CLK_OVL_DLO7, "ovl_dlo7", "disp", 22),
122	GATE_HWV_OVL1(CLK_OVL_DLO8, "ovl_dlo8", "disp", 23),
123	GATE_HWV_OVL1(CLK_OVL_DLO9, "ovl_dlo9", "disp", 24),
124	GATE_HWV_OVL1(CLK_OVL_DLO10, "ovl_dlo10", "disp", 25),
125	GATE_HWV_OVL1(CLK_OVL_DLO11, "ovl_dlo11", "disp", 26),
126	GATE_HWV_OVL1(CLK_OVL_DLO12, "ovl_dlo12", "disp", 27),
127	GATE_HWV_OVL1(CLK_OVLSYS_RELAY0, "ovlsys_relay0", "disp", 28),
128	GATE_HWV_OVL1(CLK_OVL_INLINEROT0, "ovl_inlinerot0", "disp", 29),
129	GATE_HWV_OVL1(CLK_OVL_SMI, "ovl_smi", "disp", 30),
130};
131
132static const struct mtk_clk_desc ovl_mcd = {
133	.clks = ovl_clks,
134	.num_clks = ARRAY_SIZE(ovl_clks),
135};
136
137static const struct platform_device_id clk_mt8196_ovl0_id_table[] = {
138	{ .name = "clk-mt8196-ovl0", .driver_data = (kernel_ulong_t)&ovl_mcd },
139	{ /* sentinel */ }
140};
141MODULE_DEVICE_TABLE(platform, clk_mt8196_ovl0_id_table);
142
143static struct platform_driver clk_mt8196_ovl0_drv = {
144	.probe = mtk_clk_pdev_probe,
145	.remove = mtk_clk_pdev_remove,
146	.driver = {
147		.name = "clk-mt8196-ovl0",
148	},
149	.id_table = clk_mt8196_ovl0_id_table,
150};
151module_platform_driver(clk_mt8196_ovl0_drv);
152
153MODULE_DESCRIPTION("MediaTek MT8196 ovl0 clocks driver");
154MODULE_LICENSE("GPL");