File Index
Files and directories
Sign in
FILE

clk-mt8195-topckgen.c

File preview with syntax highlighting.

linux-6.19.14/drivers/clk/mediatek/clk-mt8195-topckgen.c C 
   1// SPDX-License-Identifier: GPL-2.0-only
   2//
   3// Copyright (c) 2021 MediaTek Inc.
   4// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
   5
   6#include "clk-gate.h"
   7#include "clk-mtk.h"
   8#include "clk-mux.h"
   9
  10#include <dt-bindings/clock/mt8195-clk.h>
  11#include <linux/mod_devicetable.h>
  12#include <linux/platform_device.h>
  13
  14static DEFINE_SPINLOCK(mt8195_clk_lock);
  15
  16static const struct mtk_fixed_clk top_fixed_clks[] = {
  17	FIXED_CLK(CLK_TOP_IN_DGI, "in_dgi", NULL, 165000000),
  18	FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc1", NULL, 248000000),
  19	FIXED_CLK(CLK_TOP_ULPOSC2, "ulposc2", NULL, 326000000),
  20	FIXED_CLK(CLK_TOP_MEM_466M, "mem_466m", NULL, 533000000),
  21	FIXED_CLK(CLK_TOP_MPHONE_SLAVE_B, "mphone_slave_b", NULL, 49152000),
  22	FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000),
  23	FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL, "ufs_rx_symbol", NULL, 166000000),
  24	FIXED_CLK(CLK_TOP_UFS_TX_SYMBOL, "ufs_tx_symbol", NULL, 166000000),
  25	FIXED_CLK(CLK_TOP_SSUSB_U3PHY_P1_P_P0, "ssusb_u3phy_p1_p_p0", NULL, 131000000),
  26	FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL1, "ufs_rx_symbol1", NULL, 166000000),
  27	FIXED_CLK(CLK_TOP_FPC, "fpc", NULL, 50000000),
  28	FIXED_CLK(CLK_TOP_HDMIRX_P, "hdmirx_p", NULL, 594000000),
  29};
  30
  31static const struct mtk_fixed_factor top_divs[] = {
  32	FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
  33	FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52),
  34	FACTOR(CLK_TOP_IN_DGI_D2, "in_dgi_d2", "in_dgi", 1, 2),
  35	FACTOR(CLK_TOP_IN_DGI_D4, "in_dgi_d4", "in_dgi", 1, 4),
  36	FACTOR(CLK_TOP_IN_DGI_D6, "in_dgi_d6", "in_dgi", 1, 6),
  37	FACTOR(CLK_TOP_IN_DGI_D8, "in_dgi_d8", "in_dgi", 1, 8),
  38	FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
  39	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
  40	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
  41	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
  42	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
  43	FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
  44	FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
  45	FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
  46	FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
  47	FACTOR_FLAGS(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6, 0),
  48	FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2, 0),
  49	FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4, 0),
  50	FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8, 0),
  51	FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0),
  52	FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0),
  53	FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0),
  54	FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8, 0),
  55	FACTOR_FLAGS(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9, 0),
  56	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2, 0),
  57	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
  58	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0),
  59	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2, 0),
  60	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4, 0),
  61	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8, 0),
  62	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
  63	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
  64	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
  65	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
  66	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6, 0),
  67	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2, 0),
  68	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4, 0),
  69	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8, 0),
  70	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16, 0),
  71	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
  72	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0),
  73	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0),
  74	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0),
  75	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0),
  76	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0),
  77	FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
  78	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
  79	FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
  80	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
  81	FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3", 1, 4),
  82	FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4", 1, 4),
  83	FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5", 1, 4),
  84	FACTOR(CLK_TOP_HDMIRX_APLL_D3, "hdmirx_apll_d3", "hdmirx_apll", 1, 3),
  85	FACTOR(CLK_TOP_HDMIRX_APLL_D4, "hdmirx_apll_d4", "hdmirx_apll", 1, 4),
  86	FACTOR(CLK_TOP_HDMIRX_APLL_D6, "hdmirx_apll_d6", "hdmirx_apll", 1, 6),
  87	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
  88	FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
  89	FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
  90	FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
  91	FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
  92	FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
  93	FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
  94	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
  95	FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
  96	FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
  97	FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
  98	FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
  99	FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
 100	FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16),
 101	FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
 102	FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
 103	FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
 104	FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 1, 16),
 105	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
 106	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
 107	FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
 108	FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll", 1, 2),
 109	FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll", 1, 8),
 110	FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll", 1, 10),
 111	FACTOR(CLK_TOP_DGIPLL_D2, "dgipll_d2", "dgipll", 1, 2),
 112	FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1", 1, 2),
 113	FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1", 1, 4),
 114	FACTOR(CLK_TOP_ULPOSC1_D7, "ulposc1_d7", "ulposc1", 1, 7),
 115	FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1", 1, 8),
 116	FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc1", 1, 10),
 117	FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1", 1, 16),
 118	FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll", 1, 2),
 119	FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
 120	FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll", 1, 8),
 121};
 122
 123static const char * const axi_parents[] = {
 124	"clk26m",
 125	"mainpll_d4_d4",
 126	"mainpll_d7_d2",
 127	"mainpll_d4_d2",
 128	"mainpll_d5_d2",
 129	"mainpll_d6_d2",
 130	"ulposc1_d4"
 131};
 132
 133static const char * const spm_parents[] = {
 134	"clk26m",
 135	"ulposc1_d10",
 136	"mainpll_d7_d4",
 137	"clk32k"
 138};
 139
 140static const char * const scp_parents[] = {
 141	"clk26m",
 142	"univpll_d4",
 143	"mainpll_d6",
 144	"univpll_d6",
 145	"univpll_d4_d2",
 146	"mainpll_d4_d2",
 147	"mainpll_d4",
 148	"mainpll_d6_d2"
 149};
 150
 151static const char * const bus_aximem_parents[] = {
 152	"clk26m",
 153	"mainpll_d7_d2",
 154	"mainpll_d4_d2",
 155	"mainpll_d5_d2",
 156	"mainpll_d6"
 157};
 158
 159static const char * const vpp_parents[] = {
 160	"clk26m",
 161	"univpll_d6_d2",
 162	"mainpll_d5_d2",
 163	"mmpll_d6_d2",
 164	"univpll_d5_d2",
 165	"univpll_d4_d2",
 166	"mmpll_d4_d2",
 167	"mmpll_d7",
 168	"univpll_d6",
 169	"mainpll_d4",
 170	"mmpll_d5",
 171	"tvdpll1",
 172	"tvdpll2",
 173	"univpll_d4",
 174	"mmpll_d4"
 175};
 176
 177static const char * const ethdr_parents[] = {
 178	"clk26m",
 179	"univpll_d6_d2",
 180	"mainpll_d5_d2",
 181	"mmpll_d6_d2",
 182	"univpll_d5_d2",
 183	"univpll_d4_d2",
 184	"mmpll_d4_d2",
 185	"mmpll_d7",
 186	"univpll_d6",
 187	"mainpll_d4",
 188	"mmpll_d5_d4",
 189	"tvdpll1",
 190	"tvdpll2",
 191	"univpll_d4",
 192	"mmpll_d4"
 193};
 194
 195static const char * const ipe_parents[] = {
 196	"clk26m",
 197	"imgpll",
 198	"mainpll_d4",
 199	"mmpll_d6",
 200	"univpll_d6",
 201	"mainpll_d6",
 202	"mmpll_d4_d2",
 203	"univpll_d4_d2",
 204	"mainpll_d4_d2",
 205	"mmpll_d6_d2",
 206	"univpll_d5_d2"
 207};
 208
 209static const char * const cam_parents[] = {
 210	"clk26m",
 211	"mainpll_d4",
 212	"mmpll_d4",
 213	"univpll_d4",
 214	"univpll_d5",
 215	"univpll_d6",
 216	"mmpll_d7",
 217	"univpll_d4_d2",
 218	"mainpll_d4_d2",
 219	"imgpll"
 220};
 221
 222static const char * const ccu_parents[] = {
 223	"clk26m",
 224	"univpll_d6",
 225	"mainpll_d4_d2",
 226	"mainpll_d4",
 227	"univpll_d5",
 228	"mainpll_d6",
 229	"mmpll_d6",
 230	"mmpll_d7",
 231	"univpll_d4_d2",
 232	"univpll_d7"
 233};
 234
 235static const char * const img_parents[] = {
 236	"clk26m",
 237	"imgpll",
 238	"univpll_d4",
 239	"mainpll_d4",
 240	"univpll_d5",
 241	"mmpll_d6",
 242	"univpll_d6",
 243	"mainpll_d6",
 244	"mmpll_d4_d2",
 245	"univpll_d4_d2",
 246	"mainpll_d4_d2",
 247	"univpll_d5_d2"
 248};
 249
 250static const char * const camtm_parents[] = {
 251	"clk26m",
 252	"univpll_d4_d4",
 253	"univpll_d6_d2",
 254	"univpll_d6_d4"
 255};
 256
 257static const char * const dsp_parents[] = {
 258	"clk26m",
 259	"univpll_d6_d2",
 260	"univpll_d4_d2",
 261	"univpll_d5",
 262	"univpll_d4",
 263	"mmpll_d4",
 264	"mainpll_d3",
 265	"univpll_d3"
 266};
 267
 268static const char * const dsp1_parents[] = {
 269	"clk26m",
 270	"univpll_d6_d2",
 271	"mainpll_d4_d2",
 272	"univpll_d5",
 273	"mmpll_d5",
 274	"univpll_d4",
 275	"mainpll_d3",
 276	"univpll_d3"
 277};
 278
 279static const char * const dsp2_parents[] = {
 280	"clk26m",
 281	"univpll_d6_d2",
 282	"univpll_d4_d2",
 283	"mainpll_d4",
 284	"univpll_d4",
 285	"mmpll_d4",
 286	"mainpll_d3",
 287	"univpll_d3"
 288};
 289
 290static const char * const ipu_if_parents[] = {
 291	"clk26m",
 292	"univpll_d6_d2",
 293	"univpll_d5_d2",
 294	"mainpll_d4_d2",
 295	"mainpll_d6",
 296	"univpll_d5",
 297	"univpll_d4",
 298	"mmpll_d4"
 299};
 300
 301/*
 302 * MFG can be also parented to "univpll_d6" and "univpll_d7":
 303 * these have been removed from the parents list to let us
 304 * achieve GPU DVFS without any special clock handlers.
 305 */
 306static const char * const mfg_parents[] = {
 307	"clk26m",
 308	"mainpll_d5_d2"
 309};
 310
 311static const char * const camtg_parents[] = {
 312	"clk26m",
 313	"univpll_192m_d8",
 314	"univpll_d6_d8",
 315	"univpll_192m_d4",
 316	"univpll_d6_d16",
 317	"clk26m_d2",
 318	"univpll_192m_d16",
 319	"univpll_192m_d32"
 320};
 321
 322static const char * const uart_parents[] = {
 323	"clk26m",
 324	"univpll_d6_d8"
 325};
 326
 327static const char * const spi_parents[] = {
 328	"clk26m",
 329	"mainpll_d5_d4",
 330	"mainpll_d6_d4",
 331	"msdcpll_d4",
 332	"univpll_d6_d2",
 333	"mainpll_d6_d2",
 334	"mainpll_d4_d4",
 335	"univpll_d5_d4"
 336};
 337
 338static const char * const spis_parents[] = {
 339	"clk26m",
 340	"univpll_d6",
 341	"mainpll_d6",
 342	"univpll_d4_d2",
 343	"univpll_d6_d2",
 344	"univpll_d4_d4",
 345	"univpll_d6_d4",
 346	"mainpll_d7_d4"
 347};
 348
 349static const char * const msdc50_0_h_parents[] = {
 350	"clk26m",
 351	"mainpll_d4_d2",
 352	"mainpll_d6_d2"
 353};
 354
 355static const char * const msdc50_0_parents[] = {
 356	"clk26m",
 357	"msdcpll",
 358	"msdcpll_d2",
 359	"univpll_d4_d4",
 360	"mainpll_d6_d2",
 361	"univpll_d4_d2"
 362};
 363
 364static const char * const msdc30_parents[] = {
 365	"clk26m",
 366	"univpll_d6_d2",
 367	"mainpll_d6_d2",
 368	"mainpll_d7_d2",
 369	"msdcpll_d2"
 370};
 371
 372static const char * const intdir_parents[] = {
 373	"clk26m",
 374	"univpll_d6",
 375	"mainpll_d4",
 376	"univpll_d4"
 377};
 378
 379static const char * const aud_intbus_parents[] = {
 380	"clk26m",
 381	"mainpll_d4_d4",
 382	"mainpll_d7_d4"
 383};
 384
 385static const char * const audio_h_parents[] = {
 386	"clk26m",
 387	"univpll_d7",
 388	"apll1",
 389	"apll2"
 390};
 391
 392static const char * const pwrap_ulposc_parents[] = {
 393	"ulposc1_d10",
 394	"clk26m",
 395	"ulposc1_d4",
 396	"ulposc1_d7",
 397	"ulposc1_d8",
 398	"ulposc1_d16",
 399	"mainpll_d4_d8",
 400	"univpll_d5_d8"
 401};
 402
 403static const char * const atb_parents[] = {
 404	"clk26m",
 405	"mainpll_d4_d2",
 406	"mainpll_d5_d2"
 407};
 408
 409static const char * const pwrmcu_parents[] = {
 410	"clk26m",
 411	"mainpll_d7_d2",
 412	"mainpll_d6_d2",
 413	"mainpll_d5_d2",
 414	"mainpll_d9",
 415	"mainpll_d4_d2"
 416};
 417
 418/*
 419 * Both DP/eDP can be parented to TVDPLL1 and TVDPLL2, but we force using
 420 * TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate
 421 * in dual output case, which would lead to corruption of functionality loss.
 422 */
 423static const char * const dp_parents[] = {
 424	"clk26m",
 425	"tvdpll2_d2",
 426	"tvdpll2_d4",
 427	"tvdpll2_d8",
 428	"tvdpll2_d16"
 429};
 430static const u8 dp_parents_idx[] = { 0, 2, 4, 6, 8 };
 431
 432static const char * const edp_parents[] = {
 433	"clk26m",
 434	"tvdpll1_d2",
 435	"tvdpll1_d4",
 436	"tvdpll1_d8",
 437	"tvdpll1_d16"
 438};
 439static const u8 edp_parents_idx[] = { 0, 1, 3, 5, 7 };
 440
 441static const char * const disp_pwm_parents[] = {
 442	"clk26m",
 443	"univpll_d6_d4",
 444	"ulposc1_d2",
 445	"ulposc1_d4",
 446	"ulposc1_d16"
 447};
 448
 449static const char * const usb_parents[] = {
 450	"clk26m",
 451	"univpll_d5_d4",
 452	"univpll_d6_d4",
 453	"univpll_d5_d2"
 454};
 455
 456static const char * const i2c_parents[] = {
 457	"clk26m",
 458	"mainpll_d4_d8",
 459	"univpll_d5_d4"
 460};
 461
 462static const char * const seninf_parents[] = {
 463	"clk26m",
 464	"univpll_d4_d4",
 465	"univpll_d6_d2",
 466	"univpll_d4_d2",
 467	"univpll_d7",
 468	"univpll_d6",
 469	"mmpll_d6",
 470	"univpll_d5"
 471};
 472
 473static const char * const gcpu_parents[] = {
 474	"clk26m",
 475	"mainpll_d6",
 476	"univpll_d4_d2",
 477	"mmpll_d5_d2",
 478	"univpll_d5_d2"
 479};
 480
 481static const char * const dxcc_parents[] = {
 482	"clk26m",
 483	"mainpll_d4_d2",
 484	"mainpll_d4_d4",
 485	"mainpll_d4_d8"
 486};
 487
 488static const char * const dpmaif_parents[] = {
 489	"clk26m",
 490	"univpll_d4_d4",
 491	"mainpll_d6",
 492	"mainpll_d4_d2",
 493	"univpll_d4_d2"
 494};
 495
 496static const char * const aes_fde_parents[] = {
 497	"clk26m",
 498	"mainpll_d4_d2",
 499	"mainpll_d6",
 500	"mainpll_d4_d4",
 501	"univpll_d4_d2",
 502	"univpll_d6"
 503};
 504
 505static const char * const ufs_parents[] = {
 506	"clk26m",
 507	"mainpll_d4_d4",
 508	"mainpll_d4_d8",
 509	"univpll_d4_d4",
 510	"mainpll_d6_d2",
 511	"univpll_d6_d2",
 512	"msdcpll_d2"
 513};
 514
 515static const char * const ufs_tick1us_parents[] = {
 516	"clk26m_d52",
 517	"clk26m"
 518};
 519
 520static const char * const ufs_mp_sap_parents[] = {
 521	"clk26m",
 522	"msdcpll_d16"
 523};
 524
 525static const char * const venc_parents[] = {
 526	"clk26m",
 527	"mmpll_d4_d2",
 528	"mainpll_d6",
 529	"univpll_d4_d2",
 530	"mainpll_d4_d2",
 531	"univpll_d6",
 532	"mmpll_d6",
 533	"mainpll_d5_d2",
 534	"mainpll_d6_d2",
 535	"mmpll_d9",
 536	"univpll_d4_d4",
 537	"mainpll_d4",
 538	"univpll_d4",
 539	"univpll_d5",
 540	"univpll_d5_d2",
 541	"mainpll_d5"
 542};
 543
 544static const char * const vdec_parents[] = {
 545	"clk26m",
 546	"mainpll_d5_d2",
 547	"mmpll_d6_d2",
 548	"univpll_d4_d2",
 549	"mmpll_d4_d2",
 550	"mainpll_d5",
 551	"mmpll_d6",
 552	"mmpll_d5",
 553	"vdecpll",
 554	"univpll_d4",
 555	"mmpll_d4",
 556	"univpll_d6_d2",
 557	"mmpll_d9",
 558	"univpll_d6",
 559	"univpll_d5",
 560	"mainpll_d4"
 561};
 562
 563static const char * const pwm_parents[] = {
 564	"clk26m",
 565	"univpll_d4_d8"
 566};
 567
 568static const char * const mcupm_parents[] = {
 569	"clk26m",
 570	"mainpll_d6_d2",
 571	"mainpll_d7_d4",
 572};
 573
 574static const char * const spmi_parents[] = {
 575	"clk26m",
 576	"clk26m_d2",
 577	"ulposc1_d8",
 578	"ulposc1_d10",
 579	"ulposc1_d16",
 580	"ulposc1_d7",
 581	"clk32k",
 582	"mainpll_d7_d8",
 583	"mainpll_d6_d8",
 584	"mainpll_d5_d8"
 585};
 586
 587static const char * const dvfsrc_parents[] = {
 588	"clk26m",
 589	"ulposc1_d10",
 590	"univpll_d6_d8",
 591	"msdcpll_d16"
 592};
 593
 594static const char * const tl_parents[] = {
 595	"clk26m",
 596	"univpll_d5_d4",
 597	"mainpll_d4_d4"
 598};
 599
 600static const char * const dsi_occ_parents[] = {
 601	"clk26m",
 602	"mainpll_d6_d2",
 603	"univpll_d5_d2",
 604	"univpll_d4_d2"
 605};
 606
 607static const char * const wpe_vpp_parents[] = {
 608	"clk26m",
 609	"mainpll_d5_d2",
 610	"mmpll_d6_d2",
 611	"univpll_d5_d2",
 612	"mainpll_d4_d2",
 613	"univpll_d4_d2",
 614	"mmpll_d4_d2",
 615	"mainpll_d6",
 616	"mmpll_d7",
 617	"univpll_d6",
 618	"mainpll_d5",
 619	"univpll_d5",
 620	"mainpll_d4",
 621	"tvdpll1",
 622	"univpll_d4"
 623};
 624
 625static const char * const hdcp_parents[] = {
 626	"clk26m",
 627	"univpll_d4_d8",
 628	"mainpll_d5_d8",
 629	"univpll_d6_d4"
 630};
 631
 632static const char * const hdcp_24m_parents[] = {
 633	"clk26m",
 634	"univpll_192m_d4",
 635	"univpll_192m_d8",
 636	"univpll_d6_d8"
 637};
 638
 639static const char * const hd20_dacr_ref_parents[] = {
 640	"clk26m",
 641	"univpll_d4_d2",
 642	"univpll_d4_d4",
 643	"univpll_d4_d8"
 644};
 645
 646static const char * const hd20_hdcp_c_parents[] = {
 647	"clk26m",
 648	"msdcpll_d4",
 649	"univpll_d4_d8",
 650	"univpll_d6_d8"
 651};
 652
 653static const char * const hdmi_xtal_parents[] = {
 654	"clk26m",
 655	"clk26m_d2"
 656};
 657
 658static const char * const hdmi_apb_parents[] = {
 659	"clk26m",
 660	"univpll_d6_d4",
 661	"msdcpll_d2"
 662};
 663
 664static const char * const snps_eth_250m_parents[] = {
 665	"clk26m",
 666	"ethpll_d2"
 667};
 668
 669static const char * const snps_eth_62p4m_ptp_parents[] = {
 670	"apll2_d3",
 671	"apll1_d3",
 672	"clk26m",
 673	"ethpll_d8"
 674};
 675
 676static const char * const snps_eth_50m_rmii_parents[] = {
 677	"clk26m",
 678	"ethpll_d10"
 679};
 680
 681static const char * const dgi_out_parents[] = {
 682	"clk26m",
 683	"dgipll",
 684	"dgipll_d2",
 685	"in_dgi",
 686	"in_dgi_d2",
 687	"mmpll_d4_d4"
 688};
 689
 690static const char * const nna_parents[] = {
 691	"clk26m",
 692	"nnapll",
 693	"univpll_d4",
 694	"mainpll_d4",
 695	"univpll_d5",
 696	"mmpll_d6",
 697	"univpll_d6",
 698	"mainpll_d6",
 699	"mmpll_d4_d2",
 700	"univpll_d4_d2",
 701	"mainpll_d4_d2",
 702	"mmpll_d6_d2"
 703};
 704
 705static const char * const adsp_parents[] = {
 706	"clk26m",
 707	"clk26m_d2",
 708	"mainpll_d6",
 709	"mainpll_d5_d2",
 710	"univpll_d4_d4",
 711	"univpll_d4",
 712	"univpll_d6",
 713	"ulposc1",
 714	"adsppll",
 715	"adsppll_d2",
 716	"adsppll_d4",
 717	"adsppll_d8"
 718};
 719
 720static const char * const asm_parents[] = {
 721	"clk26m",
 722	"univpll_d6_d4",
 723	"univpll_d6_d2",
 724	"mainpll_d5_d2"
 725};
 726
 727static const char * const apll1_parents[] = {
 728	"clk26m",
 729	"apll1_d4"
 730};
 731
 732static const char * const apll2_parents[] = {
 733	"clk26m",
 734	"apll2_d4"
 735};
 736
 737static const char * const apll3_parents[] = {
 738	"clk26m",
 739	"apll3_d4"
 740};
 741
 742static const char * const apll4_parents[] = {
 743	"clk26m",
 744	"apll4_d4"
 745};
 746
 747static const char * const apll5_parents[] = {
 748	"clk26m",
 749	"apll5_d4"
 750};
 751
 752static const char * const i2s_parents[] = {
 753	"clk26m",
 754	"apll1",
 755	"apll2",
 756	"apll3",
 757	"apll4",
 758	"apll5",
 759	"hdmirx_apll"
 760};
 761
 762static const char * const a1sys_hp_parents[] = {
 763	"clk26m",
 764	"apll1_d4"
 765};
 766
 767static const char * const a2sys_parents[] = {
 768	"clk26m",
 769	"apll2_d4"
 770};
 771
 772static const char * const a3sys_parents[] = {
 773	"clk26m",
 774	"apll3_d4",
 775	"apll4_d4",
 776	"apll5_d4",
 777	"hdmirx_apll_d3",
 778	"hdmirx_apll_d4",
 779	"hdmirx_apll_d6"
 780};
 781
 782static const char * const spinfi_b_parents[] = {
 783	"clk26m",
 784	"univpll_d6_d8",
 785	"univpll_d5_d8",
 786	"mainpll_d4_d8",
 787	"mainpll_d7_d4",
 788	"mainpll_d6_d4",
 789	"univpll_d6_d4",
 790	"univpll_d5_d4"
 791};
 792
 793static const char * const nfi1x_parents[] = {
 794	"clk26m",
 795	"univpll_d5_d4",
 796	"mainpll_d7_d4",
 797	"mainpll_d6_d4",
 798	"univpll_d6_d4",
 799	"mainpll_d4_d4",
 800	"mainpll_d7_d2",
 801	"mainpll_d6_d2"
 802};
 803
 804static const char * const ecc_parents[] = {
 805	"clk26m",
 806	"mainpll_d4_d4",
 807	"mainpll_d5_d2",
 808	"mainpll_d4_d2",
 809	"mainpll_d6",
 810	"univpll_d6"
 811};
 812
 813static const char * const audio_local_bus_parents[] = {
 814	"clk26m",
 815	"clk26m_d2",
 816	"mainpll_d4_d4",
 817	"mainpll_d7_d2",
 818	"mainpll_d4_d2",
 819	"mainpll_d5_d2",
 820	"mainpll_d6_d2",
 821	"mainpll_d7",
 822	"univpll_d6",
 823	"ulposc1",
 824	"ulposc1_d4",
 825	"ulposc1_d2"
 826};
 827
 828static const char * const spinor_parents[] = {
 829	"clk26m",
 830	"clk26m_d2",
 831	"mainpll_d7_d8",
 832	"univpll_d6_d8"
 833};
 834
 835static const char * const dvio_dgi_ref_parents[] = {
 836	"clk26m",
 837	"in_dgi",
 838	"in_dgi_d2",
 839	"in_dgi_d4",
 840	"in_dgi_d6",
 841	"in_dgi_d8",
 842	"mmpll_d4_d4"
 843};
 844
 845static const char * const ulposc_parents[] = {
 846	"ulposc1",
 847	"ethpll_d2",
 848	"mainpll_d4_d2",
 849	"ethpll_d10"
 850};
 851
 852static const char * const ulposc_core_parents[] = {
 853	"ulposc2",
 854	"univpll_d7",
 855	"mainpll_d6",
 856	"ethpll_d10"
 857};
 858
 859static const char * const srck_parents[] = {
 860	"ulposc1_d10",
 861	"clk26m"
 862};
 863
 864static const char * const mfg_fast_parents[] = {
 865	"top_mfg_core_tmp",
 866	"mfgpll"
 867};
 868
 869static const struct mtk_mux top_mtk_muxes[] = {
 870	/*
 871	 * CLK_CFG_0
 872	 * top_axi and top_bus_aximem are bus clocks, should not be closed by Linux.
 873	 * top_spm and top_scp are main clocks in always-on co-processor.
 874	 */
 875	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi",
 876		axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0,
 877		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 878	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm",
 879		spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1,
 880		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 881	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp",
 882		scp_parents, 0x020, 0x024, 0x028, 16, 3, 23, 0x04, 2,
 883		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 884	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem",
 885		bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3,
 886		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 887	/* CLK_CFG_1 */
 888	MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
 889		vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
 890	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
 891		ethdr_parents, 0x02C, 0x030, 0x034, 8, 4, 15, 0x04, 5),
 892	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
 893		ipe_parents, 0x02C, 0x030, 0x034, 16, 4, 23, 0x04, 6),
 894	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
 895		cam_parents, 0x02C, 0x030, 0x034, 24, 4, 31, 0x04, 7),
 896	/* CLK_CFG_2 */
 897	MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
 898		ccu_parents, 0x038, 0x03C, 0x040, 0, 4, 7, 0x04, 8),
 899	MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
 900		img_parents, 0x038, 0x03C, 0x040, 8, 4, 15, 0x04, 9),
 901	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
 902		camtm_parents, 0x038, 0x03C, 0x040, 16, 2, 23, 0x04, 10),
 903	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
 904		dsp_parents, 0x038, 0x03C, 0x040, 24, 3, 31, 0x04, 11),
 905	/* CLK_CFG_3 */
 906	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
 907		dsp1_parents, 0x044, 0x048, 0x04C, 0, 3, 7, 0x04, 12),
 908	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
 909		dsp1_parents, 0x044, 0x048, 0x04C, 8, 3, 15, 0x04, 13),
 910	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3",
 911		dsp1_parents, 0x044, 0x048, 0x04C, 16, 3, 23, 0x04, 14),
 912	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4",
 913		dsp2_parents, 0x044, 0x048, 0x04C, 24, 3, 31, 0x04, 15),
 914	/* CLK_CFG_4 */
 915	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5",
 916		dsp2_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x04, 16),
 917	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6",
 918		dsp2_parents, 0x050, 0x054, 0x058, 8, 3, 15, 0x04, 17),
 919	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7",
 920		dsp_parents, 0x050, 0x054, 0x058, 16, 3, 23, 0x04, 18),
 921	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "top_ipu_if",
 922		ipu_if_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x04, 19),
 923	/* CLK_CFG_5 */
 924	MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP, "top_mfg_core_tmp",
 925		mfg_parents, 0x05C, 0x060, 0x064, 0, 2, 7, 0x04, 20),
 926	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
 927		camtg_parents, 0x05C, 0x060, 0x064, 8, 3, 15, 0x04, 21),
 928	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
 929		camtg_parents, 0x05C, 0x060, 0x064, 16, 3, 23, 0x04, 22),
 930	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
 931		camtg_parents, 0x05C, 0x060, 0x064, 24, 3, 31, 0x04, 23),
 932	/* CLK_CFG_6 */
 933	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "top_camtg4",
 934		camtg_parents, 0x068, 0x06C, 0x070, 0, 3, 7, 0x04, 24),
 935	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "top_camtg5",
 936		camtg_parents, 0x068, 0x06C, 0x070, 8, 3, 15, 0x04, 25),
 937	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
 938		uart_parents, 0x068, 0x06C, 0x070, 16, 1, 23, 0x04, 26),
 939	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
 940		spi_parents, 0x068, 0x06C, 0x070, 24, 3, 31, 0x04, 27),
 941	/* CLK_CFG_7 */
 942	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIS, "top_spis",
 943		spis_parents, 0x074, 0x078, 0x07C, 0, 3, 7, 0x04, 28),
 944	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk",
 945		msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29, 0),
 946	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
 947		msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30, 0),
 948	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1",
 949		msdc30_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31, 0),
 950	/* CLK_CFG_8 */
 951	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2, "top_msdc30_2",
 952		msdc30_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0, 0),
 953	MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
 954		intdir_parents, 0x080, 0x084, 0x088, 8, 2, 15, 0x08, 1),
 955	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
 956		aud_intbus_parents, 0x080, 0x084, 0x088, 16, 2, 23, 0x08, 2),
 957	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
 958		audio_h_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x08, 3),
 959	/*
 960	 * CLK_CFG_9
 961	 * top_pwrmcu is main clock in other co-processor, should not be
 962	 * handled by Linux.
 963	 */
 964	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
 965		pwrap_ulposc_parents, 0x08C, 0x090, 0x094, 0, 3, 7, 0x08, 4),
 966	MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
 967		atb_parents, 0x08C, 0x090, 0x094, 8, 2, 15, 0x08, 5),
 968	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRMCU, "top_pwrmcu",
 969		pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6,
 970		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 971	MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_DP, "top_dp",
 972		dp_parents, dp_parents_idx, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
 973	/* CLK_CFG_10 */
 974	MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_EDP, "top_edp",
 975		edp_parents, edp_parents_idx, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
 976	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
 977		dp_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),
 978	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
 979		disp_pwm_parents, 0x098, 0x09C, 0x0A0, 16, 3, 23, 0x08, 10),
 980	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1",
 981		disp_pwm_parents, 0x098, 0x09C, 0x0A0, 24, 3, 31, 0x08, 11),
 982	/* CLK_CFG_11 */
 983	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top",
 984		usb_parents, 0x0A4, 0x0A8, 0x0AC, 0, 2, 7, 0x08, 12),
 985	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
 986		usb_parents, 0x0A4, 0x0A8, 0x0AC, 8, 2, 15, 0x08, 13),
 987	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_1P, "top_usb_top_1p",
 988		usb_parents, 0x0A4, 0x0A8, 0x0AC, 16, 2, 23, 0x08, 14),
 989	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P, "top_ssusb_xhci_1p",
 990		usb_parents, 0x0A4, 0x0A8, 0x0AC, 24, 2, 31, 0x08, 15),
 991	/* CLK_CFG_12 */
 992	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p",
 993		usb_parents, 0x0B0, 0x0B4, 0x0B8, 0, 2, 7, 0x08, 16),
 994	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P, "top_ssusb_xhci_2p",
 995		usb_parents, 0x0B0, 0x0B4, 0x0B8, 8, 2, 15, 0x08, 17),
 996	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p",
 997		usb_parents, 0x0B0, 0x0B4, 0x0B8, 16, 2, 23, 0x08, 18),
 998	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P, "top_ssusb_xhci_3p",
 999		usb_parents, 0x0B0, 0x0B4, 0x0B8, 24, 2, 31, 0x08, 19),
1000	/* CLK_CFG_13 */
1001	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
1002		i2c_parents, 0x0BC, 0x0C0, 0x0C4, 0, 2, 7, 0x08, 20),
1003	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
1004		seninf_parents, 0x0BC, 0x0C0, 0x0C4, 8, 3, 15, 0x08, 21),
1005	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
1006		seninf_parents, 0x0BC, 0x0C0, 0x0C4, 16, 3, 23, 0x08, 22),
1007	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "top_seninf2",
1008		seninf_parents, 0x0BC, 0x0C0, 0x0C4, 24, 3, 31, 0x08, 23),
1009	/* CLK_CFG_14 */
1010	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3, "top_seninf3",
1011		seninf_parents, 0x0C8, 0x0CC, 0x0D0, 0, 3, 7, 0x08, 24),
1012	MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu",
1013		gcpu_parents, 0x0C8, 0x0CC, 0x0D0, 8, 3, 15, 0x08, 25),
1014	MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "top_dxcc",
1015		dxcc_parents, 0x0C8, 0x0CC, 0x0D0, 16, 2, 23, 0x08, 26),
1016	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN, "top_dpmaif_main",
1017		dpmaif_parents, 0x0C8, 0x0CC, 0x0D0, 24, 3, 31, 0x08, 27),
1018	/* CLK_CFG_15 */
1019	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE, "top_aes_ufsfde",
1020		aes_fde_parents, 0x0D4, 0x0D8, 0x0DC, 0, 3, 7, 0x08, 28),
1021	MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS, "top_ufs",
1022		ufs_parents, 0x0D4, 0x0D8, 0x0DC, 8, 3, 15, 0x08, 29),
1023	MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_TICK1US, "top_ufs_tick1us",
1024		ufs_tick1us_parents, 0x0D4, 0x0D8, 0x0DC, 16, 1, 23, 0x08, 30),
1025	MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_MP_SAP_CFG, "top_ufs_mp_sap_cfg",
1026		ufs_mp_sap_parents, 0x0D4, 0x0D8, 0x0DC, 24, 1, 31, 0x08, 31),
1027	/*
1028	 * CLK_CFG_16
1029	 * top_mcupm is main clock in other co-processor, should not be
1030	 * handled by Linux.
1031	 */
1032	MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
1033		venc_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7, 0x0C, 0),
1034	MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
1035		vdec_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15, 0x0C, 1),
1036	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
1037		pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23, 0x0C, 2),
1038	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm",
1039		mcupm_parents, 0x0E0, 0x0E4, 0x0E8, 24, 2, 31, 0x0C, 3,
1040		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1041	/*
1042	 * CLK_CFG_17
1043	 * top_dvfsrc is for internal DVFS usage, should not be handled by Linux.
1044	 */
1045	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
1046		spmi_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4, 7, 0x0C, 4),
1047	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
1048		spmi_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5),
1049	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc",
1050		dvfsrc_parents, 0x0EC, 0x0F0, 0x0F4, 16, 2, 23, 0x0C, 6,
1051		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1052	MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
1053		tl_parents, 0x0EC, 0x0F0, 0x0F4, 24, 2, 31, 0x0C, 7),
1054	/* CLK_CFG_18 */
1055	MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_P1, "top_tl_p1",
1056		tl_parents, 0x0F8, 0x0FC, 0x0100, 0, 2, 7, 0x0C, 8),
1057	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
1058		aes_fde_parents, 0x0F8, 0x0FC, 0x0100, 8, 3, 15, 0x0C, 9),
1059	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
1060		dsi_occ_parents, 0x0F8, 0x0FC, 0x0100, 16, 2, 23, 0x0C, 10),
1061	MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp",
1062		wpe_vpp_parents, 0x0F8, 0x0FC, 0x0100, 24, 4, 31, 0x0C, 11),
1063	/* CLK_CFG_19 */
1064	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp",
1065		hdcp_parents, 0x0104, 0x0108, 0x010C, 0, 2, 7, 0x0C, 12),
1066	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m",
1067		hdcp_24m_parents, 0x0104, 0x0108, 0x010C, 8, 2, 15, 0x0C, 13),
1068	MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_DACR_REF_CLK, "top_hd20_dacr_ref_clk",
1069		hd20_dacr_ref_parents, 0x0104, 0x0108, 0x010C, 16, 2, 23, 0x0C, 14),
1070	MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_HDCP_CCLK, "top_hd20_hdcp_cclk",
1071		hd20_hdcp_c_parents, 0x0104, 0x0108, 0x010C, 24, 2, 31, 0x0C, 15),
1072	/* CLK_CFG_20 */
1073	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_XTAL, "top_hdmi_xtal",
1074		hdmi_xtal_parents, 0x0110, 0x0114, 0x0118, 0, 1, 7, 0x0C, 16),
1075	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb",
1076		hdmi_apb_parents, 0x0110, 0x0114, 0x0118, 8, 2, 15, 0x0C, 17),
1077	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M, "top_snps_eth_250m",
1078		snps_eth_250m_parents, 0x0110, 0x0114, 0x0118, 16, 1, 23, 0x0C, 18),
1079	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP, "top_snps_eth_62p4m_ptp",
1080		snps_eth_62p4m_ptp_parents, 0x0110, 0x0114, 0x0118, 24, 2, 31, 0x0C, 19),
1081	/* CLK_CFG_21 */
1082	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
1083		snps_eth_50m_rmii_parents, 0x011C, 0x0120, 0x0124, 0, 1, 7, 0x0C, 20),
1084	MUX_GATE_CLR_SET_UPD(CLK_TOP_DGI_OUT, "top_dgi_out",
1085		dgi_out_parents, 0x011C, 0x0120, 0x0124, 8, 3, 15, 0x0C, 21),
1086	MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA0, "top_nna0",
1087		nna_parents, 0x011C, 0x0120, 0x0124, 16, 4, 23, 0x0C, 22),
1088	MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA1, "top_nna1",
1089		nna_parents, 0x011C, 0x0120, 0x0124, 24, 4, 31, 0x0C, 23),
1090	/* CLK_CFG_22 */
1091	MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp",
1092		adsp_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24),
1093	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h",
1094		asm_parents, 0x0128, 0x012C, 0x0130, 8, 2, 15, 0x0C, 25),
1095	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_M, "top_asm_m",
1096		asm_parents, 0x0128, 0x012C, 0x0130, 16, 2, 23, 0x0C, 26),
1097	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l",
1098		asm_parents, 0x0128, 0x012C, 0x0130, 24, 2, 31, 0x0C, 27),
1099	/* CLK_CFG_23 */
1100	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
1101		apll1_parents, 0x0134, 0x0138, 0x013C, 0, 1, 7, 0x0C, 28),
1102	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
1103		apll2_parents, 0x0134, 0x0138, 0x013C, 8, 1, 15, 0x0C, 29),
1104	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3",
1105		apll3_parents, 0x0134, 0x0138, 0x013C, 16, 1, 23, 0x0C, 30),
1106	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4",
1107		apll4_parents, 0x0134, 0x0138, 0x013C, 24, 1, 31, 0x0C, 31),
1108	/*
1109	 * CLK_CFG_24
1110	 * i2so4_mck is not used in MT8195.
1111	 */
1112	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
1113		apll5_parents, 0x0140, 0x0144, 0x0148, 0, 1, 7, 0x010, 0),
1114	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1_MCK, "top_i2so1_mck",
1115		i2s_parents, 0x0140, 0x0144, 0x0148, 8, 3, 15, 0x010, 1),
1116	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2_MCK, "top_i2so2_mck",
1117		i2s_parents, 0x0140, 0x0144, 0x0148, 16, 3, 23, 0x010, 2),
1118	/*
1119	 * CLK_CFG_25
1120	 * i2so5_mck and i2si4_mck are not used in MT8195.
1121	 */
1122	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1_MCK, "top_i2si1_mck",
1123		i2s_parents, 0x014C, 0x0150, 0x0154, 8, 3, 15, 0x010, 5),
1124	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2_MCK, "top_i2si2_mck",
1125		i2s_parents, 0x014C, 0x0150, 0x0154, 16, 3, 23, 0x010, 6),
1126	/*
1127	 * CLK_CFG_26
1128	 * i2si5_mck is not used in MT8195.
1129	 */
1130	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX_MCK, "top_dptx_mck",
1131		i2s_parents, 0x0158, 0x015C, 0x0160, 8, 3, 15, 0x010, 9),
1132	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC_CLK, "top_aud_iec_clk",
1133		i2s_parents, 0x0158, 0x015C, 0x0160, 16, 3, 23, 0x010, 10),
1134	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp",
1135		a1sys_hp_parents, 0x0158, 0x015C, 0x0160, 24, 1, 31, 0x010, 11),
1136	/* CLK_CFG_27 */
1137	MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS_HF, "top_a2sys_hf",
1138		a2sys_parents, 0x0164, 0x0168, 0x016C, 0, 1, 7, 0x010, 12),
1139	MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS_HF, "top_a3sys_hf",
1140		a3sys_parents, 0x0164, 0x0168, 0x016C, 8, 3, 15, 0x010, 13),
1141	MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS_HF, "top_a4sys_hf",
1142		a3sys_parents, 0x0164, 0x0168, 0x016C, 16, 3, 23, 0x010, 14),
1143	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_BCLK, "top_spinfi_bclk",
1144		spinfi_b_parents, 0x0164, 0x0168, 0x016C, 24, 3, 31, 0x010, 15),
1145	/* CLK_CFG_28 */
1146	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X, "top_nfi1x",
1147		nfi1x_parents, 0x0170, 0x0174, 0x0178, 0, 3, 7, 0x010, 16),
1148	MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc",
1149		ecc_parents, 0x0170, 0x0174, 0x0178, 8, 3, 15, 0x010, 17),
1150	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS, "top_audio_local_bus",
1151		audio_local_bus_parents, 0x0170, 0x0174, 0x0178, 16, 4, 23, 0x010, 18),
1152	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
1153		spinor_parents, 0x0170, 0x0174, 0x0178, 24, 2, 31, 0x010, 19),
1154	/*
1155	 * CLK_CFG_29
1156	 * top_ulposc/top_ulposc_core/top_srck are clock source of always on co-processor,
1157	 * should not be closed by Linux.
1158	 */
1159	MUX_GATE_CLR_SET_UPD(CLK_TOP_DVIO_DGI_REF, "top_dvio_dgi_ref",
1160		dvio_dgi_ref_parents, 0x017C, 0x0180, 0x0184, 0, 3, 7, 0x010, 20),
1161	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc",
1162		ulposc_parents, 0x017C, 0x0180, 0x0184, 8, 2, 15, 0x010, 21,
1163		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1164	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC_CORE, "top_ulposc_core",
1165		ulposc_core_parents, 0x017C, 0x0180, 0x0184, 16, 2, 23, 0x010, 22,
1166		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1167	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck",
1168		srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23,
1169		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1170	/*
1171	 * the clocks in CLK_CFG_30 ~ 37 are backup clock source, no need to handled
1172	 * by Linux.
1173	 */
1174};
1175
1176static const struct mtk_composite top_adj_divs[] = {
1177	DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "top_i2si1_mck", 0x0320, 0, 0x0328, 8, 0),
1178	DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "top_i2si2_mck", 0x0320, 1, 0x0328, 8, 8),
1179	DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "top_i2so1_mck", 0x0320, 2, 0x0328, 8, 16),
1180	DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "top_i2so2_mck", 0x0320, 3, 0x0328, 8, 24),
1181	DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "top_aud_iec_clk", 0x0320, 4, 0x0334, 8, 0),
1182	/* apll12_div5 ~ 8 are not used in MT8195. */
1183	DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "top_dptx_mck", 0x0320, 9, 0x0338, 8, 8),
1184};
1185
1186static const struct mtk_gate_regs top0_cg_regs = {
1187	.set_ofs = 0x238,
1188	.clr_ofs = 0x238,
1189	.sta_ofs = 0x238,
1190};
1191
1192static const struct mtk_gate_regs top1_cg_regs = {
1193	.set_ofs = 0x250,
1194	.clr_ofs = 0x250,
1195	.sta_ofs = 0x250,
1196};
1197
1198#define GATE_TOP0_FLAGS(_id, _name, _parent, _shift, _flag)		\
1199	GATE_MTK_FLAGS(_id, _name, _parent, &top0_cg_regs, _shift,	\
1200		&mtk_clk_gate_ops_no_setclr_inv, _flag)
1201
1202#define GATE_TOP0(_id, _name, _parent, _shift)			\
1203	GATE_TOP0_FLAGS(_id, _name, _parent, _shift, 0)
1204
1205#define GATE_TOP1(_id, _name, _parent, _shift)			\
1206	GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1207
1208static const struct mtk_gate top_clks[] = {
1209	/* TOP0 */
1210	GATE_TOP0(CLK_TOP_CFG_VPP0, "cfg_vpp0", "top_vpp", 0),
1211	GATE_TOP0(CLK_TOP_CFG_VPP1, "cfg_vpp1", "top_vpp", 1),
1212	GATE_TOP0(CLK_TOP_CFG_VDO0, "cfg_vdo0", "top_vpp", 2),
1213	GATE_TOP0(CLK_TOP_CFG_VDO1, "cfg_vdo1", "top_vpp", 3),
1214	GATE_TOP0(CLK_TOP_CFG_UNIPLL_SES, "cfg_unipll_ses", "univpll_d2", 4),
1215	GATE_TOP0(CLK_TOP_CFG_26M_VPP0, "cfg_26m_vpp0", "clk26m", 5),
1216	GATE_TOP0(CLK_TOP_CFG_26M_VPP1, "cfg_26m_vpp1", "clk26m", 6),
1217	GATE_TOP0(CLK_TOP_CFG_26M_AUD, "cfg_26m_aud", "clk26m", 9),
1218	/*
1219	 * cfg_axi_east, cfg_axi_east_north, cfg_axi_north and cfg_axi_south
1220	 * are peripheral bus clock branches.
1221	 */
1222	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST, "cfg_axi_east", "top_axi", 10, CLK_IS_CRITICAL),
1223	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST_NORTH, "cfg_axi_east_north", "top_axi", 11,
1224		CLK_IS_CRITICAL),
1225	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_NORTH, "cfg_axi_north", "top_axi", 12, CLK_IS_CRITICAL),
1226	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_SOUTH, "cfg_axi_south", "top_axi", 13, CLK_IS_CRITICAL),
1227	GATE_TOP0(CLK_TOP_CFG_EXT_TEST, "cfg_ext_test", "msdcpll_d2", 15),
1228	/* TOP1 */
1229	GATE_TOP1(CLK_TOP_SSUSB_REF, "ssusb_ref", "clk26m", 0),
1230	GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1),
1231	GATE_TOP1(CLK_TOP_SSUSB_P1_REF, "ssusb_p1_ref", "clk26m", 2),
1232	GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3),
1233	GATE_TOP1(CLK_TOP_SSUSB_P2_REF, "ssusb_p2_ref", "clk26m", 4),
1234	GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5),
1235	GATE_TOP1(CLK_TOP_SSUSB_P3_REF, "ssusb_p3_ref", "clk26m", 6),
1236	GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7),
1237};
1238
1239static const struct of_device_id of_match_clk_mt8195_topck[] = {
1240	{ .compatible = "mediatek,mt8195-topckgen", },
1241	{}
1242};
1243MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_topck);
1244
1245/* Register mux notifier for MFG mux */
1246static int clk_mt8195_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
1247{
1248	struct mtk_mux_nb *mfg_mux_nb;
1249
1250	mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
1251	if (!mfg_mux_nb)
1252		return -ENOMEM;
1253
1254	mfg_mux_nb->ops = &clk_mux_ops;
1255	mfg_mux_nb->bypass_index = 0; /* Bypass to TOP_MFG_CORE_TMP */
1256
1257	return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
1258}
1259
1260static int clk_mt8195_topck_probe(struct platform_device *pdev)
1261{
1262	struct clk_hw_onecell_data *top_clk_data;
1263	struct device_node *node = pdev->dev.of_node;
1264	struct clk_hw *hw;
1265	int r;
1266	void __iomem *base;
1267
1268	top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1269	if (!top_clk_data)
1270		return -ENOMEM;
1271
1272	base = devm_platform_ioremap_resource(pdev, 0);
1273	if (IS_ERR(base)) {
1274		r = PTR_ERR(base);
1275		goto free_top_data;
1276	}
1277
1278	r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1279					top_clk_data);
1280	if (r)
1281		goto free_top_data;
1282
1283	r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1284	if (r)
1285		goto unregister_fixed_clks;
1286
1287	r = mtk_clk_register_muxes(&pdev->dev, top_mtk_muxes,
1288				   ARRAY_SIZE(top_mtk_muxes), node,
1289				   &mt8195_clk_lock, top_clk_data);
1290	if (r)
1291		goto unregister_factors;
1292
1293	hw = devm_clk_hw_register_mux(&pdev->dev, "mfg_ck_fast_ref", mfg_fast_parents,
1294				      ARRAY_SIZE(mfg_fast_parents), CLK_SET_RATE_PARENT,
1295				      (base + 0x250), 8, 1, 0, &mt8195_clk_lock);
1296	if (IS_ERR(hw)) {
1297		r = PTR_ERR(hw);
1298		goto unregister_muxes;
1299	}
1300	top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] = hw;
1301
1302	r = clk_mt8195_reg_mfg_mux_notifier(&pdev->dev,
1303					    top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF]->clk);
1304	if (r)
1305		goto unregister_muxes;
1306
1307	r = mtk_clk_register_composites(&pdev->dev, top_adj_divs,
1308					ARRAY_SIZE(top_adj_divs), base,
1309					&mt8195_clk_lock, top_clk_data);
1310	if (r)
1311		goto unregister_muxes;
1312
1313	r = mtk_clk_register_gates(&pdev->dev, node, top_clks,
1314				   ARRAY_SIZE(top_clks), top_clk_data);
1315	if (r)
1316		goto unregister_composite_divs;
1317
1318	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
1319	if (r)
1320		goto unregister_gates;
1321
1322	platform_set_drvdata(pdev, top_clk_data);
1323
1324	return r;
1325
1326unregister_gates:
1327	mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1328unregister_composite_divs:
1329	mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
1330unregister_muxes:
1331	mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
1332unregister_factors:
1333	mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1334unregister_fixed_clks:
1335	mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
1336free_top_data:
1337	mtk_free_clk_data(top_clk_data);
1338	return r;
1339}
1340
1341static void clk_mt8195_topck_remove(struct platform_device *pdev)
1342{
1343	struct clk_hw_onecell_data *top_clk_data = platform_get_drvdata(pdev);
1344	struct device_node *node = pdev->dev.of_node;
1345
1346	of_clk_del_provider(node);
1347	mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1348	mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
1349	mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
1350	mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1351	mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
1352	mtk_free_clk_data(top_clk_data);
1353}
1354
1355static struct platform_driver clk_mt8195_topck_drv = {
1356	.probe = clk_mt8195_topck_probe,
1357	.remove = clk_mt8195_topck_remove,
1358	.driver = {
1359		.name = "clk-mt8195-topck",
1360		.of_match_table = of_match_clk_mt8195_topck,
1361	},
1362};
1363module_platform_driver(clk_mt8195_topck_drv);
1364
1365MODULE_DESCRIPTION("MediaTek MT8195 top clock generators driver");
1366MODULE_LICENSE("GPL");
~/ Read-only file preview.