clk-mt8188-vdo0.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2022 MediaTek Inc.
  4 * Author: Garmin Chang <garmin.chang@mediatek.com>
  5 */
  6
  7#include <linux/clk-provider.h>
  8#include <linux/mod_devicetable.h>
  9#include <linux/platform_device.h>
 10
 11#include <dt-bindings/clock/mediatek,mt8188-clk.h>
 12
 13#include "clk-gate.h"
 14#include "clk-mtk.h"
 15
 16static const struct mtk_gate_regs vdo0_0_cg_regs = {
 17	.set_ofs = 0x104,
 18	.clr_ofs = 0x108,
 19	.sta_ofs = 0x100,
 20};
 21
 22static const struct mtk_gate_regs vdo0_1_cg_regs = {
 23	.set_ofs = 0x114,
 24	.clr_ofs = 0x118,
 25	.sta_ofs = 0x110,
 26};
 27
 28static const struct mtk_gate_regs vdo0_2_cg_regs = {
 29	.set_ofs = 0x124,
 30	.clr_ofs = 0x128,
 31	.sta_ofs = 0x120,
 32};
 33
 34#define GATE_VDO0_0(_id, _name, _parent, _shift)			\
 35	GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
 36
 37#define GATE_VDO0_1(_id, _name, _parent, _shift)			\
 38	GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
 39
 40#define GATE_VDO0_2(_id, _name, _parent, _shift)			\
 41	GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
 42
 43#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags)		\
 44	GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift,	\
 45	&mtk_clk_gate_ops_setclr, _flags)
 46
 47static const struct mtk_gate vdo0_clks[] = {
 48	/* VDO0_0 */
 49	GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0),
 50	GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "top_vpp", 2),
 51	GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "top_vpp", 4),
 52	GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "top_vpp", 6),
 53	GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "top_vpp", 8),
 54	GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "top_vpp", 10),
 55	GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "top_vpp", 17),
 56	GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "top_vpp", 19),
 57	GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0", "top_vpp", 21),
 58	GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1", "top_vpp", 22),
 59	GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "top_vpp", 23),
 60	GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "top_vpp", 24),
 61	GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "top_vpp", 25),
 62	GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "top_vpp", 26),
 63	GATE_VDO0_0(CLK_VDO0_INLINEROT0, "vdo0_inlinerot0", "top_vpp", 27),
 64	GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "top_vpp", 28),
 65	GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "top_vpp", 29),
 66	GATE_VDO0_0(CLK_VDO0_MDP_WROT0, "vdo0_mdp_wrot0", "top_vpp", 30),
 67	GATE_VDO0_0(CLK_VDO0_DISP_RSZ0, "vdo0_disp_rsz0", "top_vpp", 31),
 68	/* VDO0_1 */
 69	GATE_VDO0_1(CLK_VDO0_DISP_POSTMASK0, "vdo0_disp_postmask0", "top_vpp", 0),
 70	GATE_VDO0_1(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "top_vpp", 1),
 71	GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "top_vpp", 5),
 72	GATE_VDO0_1(CLK_VDO0_DL_RELAY3, "vdo0_dl_relay3", "top_vpp", 6),
 73	GATE_VDO0_1(CLK_VDO0_DL_RELAY4, "vdo0_dl_relay4", "top_vpp", 7),
 74	GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "top_vpp", 10),
 75	GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "top_vpp", 11),
 76	GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "top_vpp", 12),
 77	GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "top_vpp", 13),
 78	GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "top_vpp", 14),
 79	GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "top_vpp", 15),
 80	/* VDO0_2 */
 81	GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0),
 82	GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8),
 83	GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf",
 84		"top_edp", 16, CLK_SET_RATE_PARENT),
 85};
 86
 87static const struct mtk_clk_desc vdo0_desc = {
 88	.clks = vdo0_clks,
 89	.num_clks = ARRAY_SIZE(vdo0_clks),
 90};
 91
 92static const struct platform_device_id clk_mt8188_vdo0_id_table[] = {
 93	{ .name = "clk-mt8188-vdo0", .driver_data = (kernel_ulong_t)&vdo0_desc },
 94	{ /* sentinel */ }
 95};
 96MODULE_DEVICE_TABLE(platform, clk_mt8188_vdo0_id_table);
 97
 98static struct platform_driver clk_mt8188_vdo0_drv = {
 99	.probe = mtk_clk_pdev_probe,
100	.remove = mtk_clk_pdev_remove,
101	.driver = {
102		.name = "clk-mt8188-vdo0",
103	},
104	.id_table = clk_mt8188_vdo0_id_table,
105};
106module_platform_driver(clk_mt8188_vdo0_drv);
107
108MODULE_DESCRIPTION("MediaTek MT8188 Video Output 0 clocks driver");
109MODULE_LICENSE("GPL");