clk-mt8188-topckgen.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2022 MediaTek Inc.
   4 * Author: Garmin Chang <garmin.chang@mediatek.com>
   5 */
   6
   7#include <dt-bindings/clock/mediatek,mt8188-clk.h>
   8#include <linux/mod_devicetable.h>
   9#include <linux/platform_device.h>
  10
  11#include "clk-gate.h"
  12#include "clk-mtk.h"
  13#include "clk-mux.h"
  14
  15static DEFINE_SPINLOCK(mt8188_clk_lock);
  16
  17static const struct mtk_fixed_clk top_fixed_clks[] = {
  18	FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc_ck1", NULL, 260000000),
  19	FIXED_CLK(CLK_TOP_MPHONE_SLAVE_BCK, "mphone_slave_bck", NULL, 49152000),
  20	FIXED_CLK(CLK_TOP_PAD_FPC, "pad_fpc_ck", NULL, 50000000),
  21	FIXED_CLK(CLK_TOP_466M_FMEM, "hd_466m_fmem_ck", NULL, 533000000),
  22	FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000),
  23	FIXED_CLK(CLK_TOP_DSI_PHY, "dsi_phy", NULL, 500000000),
  24};
  25
  26static const struct mtk_fixed_factor top_divs[] = {
  27	FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
  28	FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
  29	FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
  30	FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
  31	FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
  32	FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
  33	FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
  34	FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
  35	FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
  36	FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
  37	FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
  38	FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
  39	FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8),
  40	FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
  41	FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
  42	FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
  43	FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
  44	FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9),
  45	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
  46	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
  47	FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
  48	FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
  49	FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
  50	FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
  51	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
  52	FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
  53	FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
  54	FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
  55	FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
  56	FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
  57	FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
  58	FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
  59	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
  60	FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
  61	FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
  62	FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
  63	FACTOR(CLK_TOP_UNIVPLL_192M_D10, "univpll_192m_d10", "univpll_192m", 1, 10),
  64	FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
  65	FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
  66	FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
  67	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
  68	FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
  69	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
  70	FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3", 1, 4),
  71	FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4", 1, 4),
  72	FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5", 1, 4),
  73	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
  74	FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
  75	FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
  76	FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
  77	FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
  78	FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
  79	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
  80	FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
  81	FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
  82	FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
  83	FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
  84	FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
  85	FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16),
  86	FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
  87	FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
  88	FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
  89	FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 1, 16),
  90	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
  91	FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
  92	FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll", 1, 2),
  93	FACTOR(CLK_TOP_ETHPLL_D4, "ethpll_d4", "ethpll", 1, 4),
  94	FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll", 1, 8),
  95	FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll", 1, 10),
  96	FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll", 1, 2),
  97	FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
  98	FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll", 1, 8),
  99	FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc_ck1", 1, 2),
 100	FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc_ck1", 1, 4),
 101	FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc_ck1", 1, 8),
 102	FACTOR(CLK_TOP_ULPOSC1_D7, "ulposc1_d7", "ulposc_ck1", 1, 7),
 103	FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc_ck1", 1, 10),
 104	FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc_ck1", 1, 16),
 105};
 106
 107static const char * const axi_parents[] = {
 108	"clk26m",
 109	"mainpll_d4_d4",
 110	"mainpll_d7_d2",
 111	"mainpll_d4_d2",
 112	"mainpll_d5_d2",
 113	"mainpll_d6_d2",
 114	"ulposc1_d4"
 115};
 116
 117static const char * const spm_parents[] = {
 118	"clk26m",
 119	"ulposc1_d10",
 120	"mainpll_d7_d4",
 121	"clk32k"
 122};
 123
 124static const char * const scp_parents[] = {
 125	"clk26m",
 126	"univpll_d4",
 127	"mainpll_d6",
 128	"univpll_d6",
 129	"univpll_d4_d2",
 130	"mainpll_d4_d2",
 131	"univpll_d3",
 132	"mainpll_d3"
 133};
 134
 135static const char * const bus_aximem_parents[] = {
 136	"clk26m",
 137	"mainpll_d7_d2",
 138	"mainpll_d4_d2",
 139	"mainpll_d5_d2",
 140	"mainpll_d6"
 141};
 142
 143static const char * const vpp_parents[] = {
 144	"clk26m",
 145	"univpll_d6_d2",
 146	"mainpll_d5_d2",
 147	"mmpll_d6_d2",
 148	"univpll_d5_d2",
 149	"univpll_d4_d2",
 150	"mmpll_d4_d2",
 151	"mmpll_d7",
 152	"univpll_d6",
 153	"mainpll_d4",
 154	"mmpll_d5",
 155	"tvdpll1",
 156	"tvdpll2",
 157	"univpll_d4",
 158	"mmpll_d4"
 159};
 160
 161static const char * const ethdr_parents[] = {
 162	"clk26m",
 163	"univpll_d6_d2",
 164	"mainpll_d5_d2",
 165	"mmpll_d6_d2",
 166	"univpll_d5_d2",
 167	"univpll_d4_d2",
 168	"mmpll_d4_d2",
 169	"mmpll_d7",
 170	"univpll_d6",
 171	"mainpll_d4",
 172	"mmpll_d5_d4",
 173	"tvdpll1",
 174	"tvdpll2",
 175	"univpll_d4",
 176	"mmpll_d4"
 177};
 178
 179static const char * const ipe_parents[] = {
 180	"clk26m",
 181	"imgpll",
 182	"mainpll_d4",
 183	"mmpll_d6",
 184	"univpll_d6",
 185	"mainpll_d6",
 186	"mmpll_d4_d2",
 187	"univpll_d4_d2",
 188	"mainpll_d4_d2",
 189	"mmpll_d6_d2",
 190	"univpll_d5_d2",
 191	"mainpll_d7"
 192};
 193
 194static const char * const cam_parents[] = {
 195	"clk26m",
 196	"tvdpll1",
 197	"mainpll_d4",
 198	"mmpll_d4",
 199	"univpll_d4",
 200	"univpll_d5",
 201	"univpll_d6",
 202	"mmpll_d7",
 203	"univpll_d4_d2",
 204	"mainpll_d4_d2",
 205	"imgpll"
 206};
 207
 208static const char * const ccu_parents[] = {
 209	"clk26m",
 210	"univpll_d6",
 211	"mainpll_d4_d2",
 212	"mainpll_d4",
 213	"univpll_d5",
 214	"mainpll_d6",
 215	"mmpll_d6",
 216	"mmpll_d7",
 217	"univpll_d4_d2",
 218	"univpll_d7"
 219};
 220
 221static const char * const ccu_ahb_parents[] = {
 222	"clk26m",
 223	"univpll_d6",
 224	"mainpll_d4_d2",
 225	"mainpll_d4",
 226	"univpll_d5",
 227	"mainpll_d6",
 228	"mmpll_d6",
 229	"mmpll_d7",
 230	"univpll_d4_d2",
 231	"univpll_d7"
 232};
 233
 234static const char * const img_parents[] = {
 235	"clk26m",
 236	"imgpll",
 237	"univpll_d4",
 238	"mainpll_d4",
 239	"univpll_d5",
 240	"mmpll_d6",
 241	"mmpll_d7",
 242	"univpll_d6",
 243	"mainpll_d6",
 244	"mmpll_d4_d2",
 245	"univpll_d4_d2",
 246	"mainpll_d4_d2",
 247	"univpll_d5_d2"
 248};
 249
 250static const char * const camtm_parents[] = {
 251	"clk26m",
 252	"univpll_d4_d4",
 253	"univpll_d6_d2",
 254	"univpll_d6_d4"
 255};
 256
 257static const char * const dsp_parents[] = {
 258	"clk26m",
 259	"univpll_d6_d2",
 260	"univpll_d4_d2",
 261	"univpll_d5",
 262	"univpll_d4",
 263	"mmpll_d4",
 264	"mainpll_d3",
 265	"univpll_d3"
 266};
 267
 268static const char * const dsp1_parents[] = {
 269	"clk26m",
 270	"univpll_d6_d2",
 271	"mainpll_d4_d2",
 272	"univpll_d5",
 273	"mmpll_d5",
 274	"univpll_d4",
 275	"mainpll_d3",
 276	"univpll_d3"
 277};
 278
 279static const char * const dsp2_parents[] = {
 280	"clk26m",
 281	"univpll_d6_d2",
 282	"mainpll_d4_d2",
 283	"univpll_d5",
 284	"mmpll_d5",
 285	"univpll_d4",
 286	"mainpll_d3",
 287	"univpll_d3"
 288};
 289
 290static const char * const dsp3_parents[] = {
 291	"clk26m",
 292	"univpll_d6_d2",
 293	"mainpll_d4_d2",
 294	"univpll_d5",
 295	"mmpll_d5",
 296	"univpll_d4",
 297	"mainpll_d3",
 298	"univpll_d3"
 299};
 300
 301static const char * const dsp4_parents[] = {
 302	"clk26m",
 303	"univpll_d6_d2",
 304	"univpll_d4_d2",
 305	"mainpll_d4",
 306	"univpll_d4",
 307	"mmpll_d4",
 308	"mainpll_d3",
 309	"univpll_d3"
 310};
 311
 312static const char * const dsp5_parents[] = {
 313	"clk26m",
 314	"univpll_d6_d2",
 315	"univpll_d4_d2",
 316	"mainpll_d4",
 317	"univpll_d4",
 318	"mmpll_d4",
 319	"mainpll_d3",
 320	"univpll_d3"
 321};
 322
 323static const char * const dsp6_parents[] = {
 324	"clk26m",
 325	"univpll_d6_d2",
 326	"univpll_d4_d2",
 327	"mainpll_d4",
 328	"univpll_d4",
 329	"mmpll_d4",
 330	"mainpll_d3",
 331	"univpll_d3"
 332};
 333
 334static const char * const dsp7_parents[] = {
 335	"clk26m",
 336	"univpll_d6_d2",
 337	"univpll_d4_d2",
 338	"univpll_d5",
 339	"univpll_d4",
 340	"mmpll_d4",
 341	"mainpll_d3",
 342	"univpll_d3"
 343};
 344
 345/*
 346 * MFG can be also parented to "univpll_d6" and "univpll_d7":
 347 * these have been removed from the parents list to let us
 348 * achieve GPU DVFS without any special clock handlers.
 349 */
 350static const char * const mfg_core_tmp_parents[] = {
 351	"clk26m",
 352	"mainpll_d5_d2"
 353};
 354
 355static const char * const camtg_parents[] = {
 356	"clk26m",
 357	"univpll_192m_d8",
 358	"univpll_d6_d8",
 359	"univpll_192m_d4",
 360	"univpll_192m_d10",
 361	"clk13m",
 362	"univpll_192m_d16",
 363	"univpll_192m_d32"
 364};
 365
 366static const char * const camtg2_parents[] = {
 367	"clk26m",
 368	"univpll_192m_d8",
 369	"univpll_d6_d8",
 370	"univpll_192m_d4",
 371	"univpll_192m_d10",
 372	"clk13m",
 373	"univpll_192m_d16",
 374	"univpll_192m_d32"
 375};
 376
 377static const char * const camtg3_parents[] = {
 378	"clk26m",
 379	"univpll_192m_d8",
 380	"univpll_d6_d8",
 381	"univpll_192m_d4",
 382	"univpll_192m_d10",
 383	"clk13m",
 384	"univpll_192m_d16",
 385	"univpll_192m_d32"
 386};
 387
 388static const char * const uart_parents[] = {
 389	"clk26m",
 390	"univpll_d6_d8"
 391};
 392
 393static const char * const spi_parents[] = {
 394	"clk26m",
 395	"mainpll_d5_d4",
 396	"mainpll_d6_d4",
 397	"univpll_d6_d4",
 398	"univpll_d6_d2",
 399	"mainpll_d6_d2",
 400	"mainpll_d4_d4",
 401	"univpll_d5_d4"
 402};
 403
 404static const char * const msdc5hclk_parents[] = {
 405	"clk26m",
 406	"mainpll_d4_d2",
 407	"mainpll_d6_d2"
 408};
 409
 410static const char * const msdc50_0_parents[] = {
 411	"clk26m",
 412	"msdcpll",
 413	"msdcpll_d2",
 414	"univpll_d4_d4",
 415	"mainpll_d6_d2",
 416	"univpll_d4_d2"
 417};
 418
 419static const char * const msdc30_1_parents[] = {
 420	"clk26m",
 421	"univpll_d6_d2",
 422	"mainpll_d6_d2",
 423	"mainpll_d7_d2",
 424	"msdcpll_d2"
 425};
 426
 427static const char * const msdc30_2_parents[] = {
 428	"clk26m",
 429	"univpll_d6_d2",
 430	"mainpll_d6_d2",
 431	"mainpll_d7_d2",
 432	"msdcpll_d2"
 433};
 434
 435static const char * const intdir_parents[] = {
 436	"clk26m",
 437	"univpll_d6",
 438	"mainpll_d4",
 439	"univpll_d4"
 440};
 441
 442static const char * const aud_intbus_parents[] = {
 443	"clk26m",
 444	"mainpll_d4_d4",
 445	"mainpll_d7_d4"
 446};
 447
 448static const char * const audio_h_parents[] = {
 449	"clk26m",
 450	"univpll_d7",
 451	"apll1",
 452	"apll2"
 453};
 454
 455static const char * const pwrap_ulposc_parents[] = {
 456	"clk26m",
 457	"ulposc1_d10",
 458	"ulposc1_d7",
 459	"ulposc1_d8",
 460	"ulposc1_d16",
 461	"mainpll_d4_d8",
 462	"univpll_d5_d8",
 463	"tvdpll1_d16"
 464};
 465
 466static const char * const atb_parents[] = {
 467	"clk26m",
 468	"mainpll_d4_d2",
 469	"mainpll_d5_d2"
 470};
 471
 472static const char * const sspm_parents[] = {
 473	"clk26m",
 474	"mainpll_d7_d2",
 475	"mainpll_d6_d2",
 476	"mainpll_d5_d2",
 477	"mainpll_d9",
 478	"mainpll_d4_d2"
 479};
 480
 481/*
 482 * Both DP/eDP can be parented to TVDPLL1 and TVDPLL2, but we force using
 483 * TVDPLL1 on eDP and TVDPLL2 on DP to avoid changing the "other" PLL rate
 484 * in dual output case, which would lead to corruption of functionality loss.
 485 */
 486static const char * const dp_parents[] = {
 487	"clk26m",
 488	"tvdpll2_d2",
 489	"tvdpll2_d4",
 490	"tvdpll2_d8",
 491	"tvdpll2_d16"
 492};
 493static const u8 dp_parents_idx[] = { 0, 2, 4, 6, 8 };
 494
 495static const char * const edp_parents[] = {
 496	"clk26m",
 497	"tvdpll1_d2",
 498	"tvdpll1_d4",
 499	"tvdpll1_d8",
 500	"tvdpll1_d16"
 501};
 502static const u8 edp_parents_idx[] = { 0, 1, 3, 5, 7 };
 503
 504static const char * const dpi_parents[] = {
 505	"clk26m",
 506	"tvdpll1_d2",
 507	"tvdpll2_d2",
 508	"tvdpll1_d4",
 509	"tvdpll2_d4",
 510	"tvdpll1_d8",
 511	"tvdpll2_d8",
 512	"tvdpll1_d16",
 513	"tvdpll2_d16"
 514};
 515
 516static const char * const disp_pwm0_parents[] = {
 517	"clk26m",
 518	"univpll_d6_d4",
 519	"ulposc1_d2",
 520	"ulposc1_d4",
 521	"ulposc1_d16",
 522	"ethpll_d4"
 523};
 524
 525static const char * const disp_pwm1_parents[] = {
 526	"clk26m",
 527	"univpll_d6_d4",
 528	"ulposc1_d2",
 529	"ulposc1_d4",
 530	"ulposc1_d16"
 531};
 532
 533static const char * const usb_parents[] = {
 534	"clk26m",
 535	"univpll_d5_d4",
 536	"univpll_d6_d4",
 537	"univpll_d5_d2"
 538};
 539
 540static const char * const ssusb_xhci_parents[] = {
 541	"clk26m",
 542	"univpll_d5_d4",
 543	"univpll_d6_d4",
 544	"univpll_d5_d2"
 545};
 546
 547static const char * const usb_2p_parents[] = {
 548	"clk26m",
 549	"univpll_d5_d4",
 550	"univpll_d6_d4",
 551	"univpll_d5_d2"
 552};
 553
 554static const char * const ssusb_xhci_2p_parents[] = {
 555	"clk26m",
 556	"univpll_d5_d4",
 557	"univpll_d6_d4",
 558	"univpll_d5_d2"
 559};
 560
 561static const char * const usb_3p_parents[] = {
 562	"clk26m",
 563	"univpll_d5_d4",
 564	"univpll_d6_d4",
 565	"univpll_d5_d2"
 566};
 567
 568static const char * const ssusb_xhci_3p_parents[] = {
 569	"clk26m",
 570	"univpll_d5_d4",
 571	"univpll_d6_d4",
 572	"univpll_d5_d2"
 573};
 574
 575static const char * const i2c_parents[] = {
 576	"clk26m",
 577	"mainpll_d4_d8",
 578	"univpll_d5_d4"
 579};
 580
 581static const char * const seninf_parents[] = {
 582	"clk26m",
 583	"univpll_d4_d4",
 584	"univpll_d6_d2",
 585	"mainpll_d4_d2",
 586	"univpll_d7",
 587	"univpll_d6",
 588	"mmpll_d6",
 589	"univpll_d5"
 590};
 591
 592static const char * const seninf1_parents[] = {
 593	"clk26m",
 594	"univpll_d4_d4",
 595	"univpll_d6_d2",
 596	"mainpll_d4_d2",
 597	"univpll_d7",
 598	"univpll_d6",
 599	"mmpll_d6",
 600	"univpll_d5"
 601};
 602
 603static const char * const gcpu_parents[] = {
 604	"clk26m",
 605	"mainpll_d6",
 606	"univpll_d4_d2",
 607	"mmpll_d5_d2",
 608	"univpll_d5_d2"
 609};
 610
 611static const char * const venc_parents[] = {
 612	"clk26m",
 613	"mmpll_d4_d2",
 614	"mainpll_d6",
 615	"univpll_d4_d2",
 616	"mainpll_d4_d2",
 617	"univpll_d6",
 618	"mmpll_d6",
 619	"mainpll_d5_d2",
 620	"mainpll_d6_d2",
 621	"mmpll_d9",
 622	"univpll_d4_d4",
 623	"mainpll_d4",
 624	"univpll_d4",
 625	"univpll_d5",
 626	"univpll_d5_d2",
 627	"mainpll_d5"
 628};
 629
 630static const char * const vdec_parents[] = {
 631	"clk26m",
 632	"mainpll_d5_d2",
 633	"mmpll_d6_d2",
 634	"univpll_d5_d2",
 635	"univpll_d4_d2",
 636	"mmpll_d4_d2",
 637	"univpll_d6",
 638	"mainpll_d5",
 639	"univpll_d5",
 640	"mmpll_d6",
 641	"mainpll_d4",
 642	"tvdpll2",
 643	"univpll_d4",
 644	"imgpll",
 645	"univpll_d6_d2",
 646	"mmpll_d9"
 647};
 648
 649static const char * const pwm_parents[] = {
 650	"clk32k",
 651	"clk26m",
 652	"univpll_d4_d8",
 653	"univpll_d6_d4"
 654};
 655
 656static const char * const mcupm_parents[] = {
 657	"clk26m",
 658	"mainpll_d6_d2",
 659	"mainpll_d7_d4"
 660};
 661
 662static const char * const spmi_p_mst_parents[] = {
 663	"clk26m",
 664	"clk13m",
 665	"ulposc1_d8",
 666	"ulposc1_d10",
 667	"ulposc1_d16",
 668	"ulposc1_d7",
 669	"clk32k",
 670	"mainpll_d7_d8",
 671	"mainpll_d6_d8",
 672	"mainpll_d5_d8"
 673};
 674
 675static const char * const spmi_m_mst_parents[] = {
 676	"clk26m",
 677	"clk13m",
 678	"ulposc1_d8",
 679	"ulposc1_d10",
 680	"ulposc1_d16",
 681	"ulposc1_d7",
 682	"clk32k",
 683	"mainpll_d7_d8",
 684	"mainpll_d6_d8",
 685	"mainpll_d5_d8"
 686};
 687
 688static const char * const dvfsrc_parents[] = {
 689	"clk26m",
 690	"ulposc1_d10",
 691	"univpll_d6_d8",
 692	"msdcpll_d16"
 693};
 694
 695static const char * const tl_parents[] = {
 696	"clk26m",
 697	"univpll_d5_d4",
 698	"mainpll_d4_d4"
 699};
 700
 701static const char * const aes_msdcfde_parents[] = {
 702	"clk26m",
 703	"mainpll_d4_d2",
 704	"mainpll_d6",
 705	"mainpll_d4_d4",
 706	"univpll_d4_d2",
 707	"univpll_d6"
 708};
 709
 710static const char * const dsi_occ_parents[] = {
 711	"clk26m",
 712	"univpll_d6_d2",
 713	"univpll_d5_d2",
 714	"univpll_d4_d2"
 715};
 716
 717static const char * const wpe_vpp_parents[] = {
 718	"clk26m",
 719	"mainpll_d5_d2",
 720	"mmpll_d6_d2",
 721	"univpll_d5_d2",
 722	"mainpll_d4_d2",
 723	"univpll_d4_d2",
 724	"mmpll_d4_d2",
 725	"mainpll_d6",
 726	"mmpll_d7",
 727	"univpll_d6",
 728	"mainpll_d5",
 729	"univpll_d5",
 730	"mainpll_d4",
 731	"tvdpll1",
 732	"univpll_d4"
 733};
 734
 735static const char * const hdcp_parents[] = {
 736	"clk26m",
 737	"univpll_d4_d8",
 738	"mainpll_d5_d8",
 739	"univpll_d6_d4"
 740};
 741
 742static const char * const hdcp_24m_parents[] = {
 743	"clk26m",
 744	"univpll_192m_d4",
 745	"univpll_192m_d8",
 746	"univpll_d6_d8"
 747};
 748
 749static const char * const hdmi_apb_parents[] = {
 750	"clk26m",
 751	"univpll_d6_d4",
 752	"msdcpll_d2"
 753};
 754
 755static const char * const snps_eth_250m_parents[] = {
 756	"clk26m",
 757	"ethpll_d2"
 758};
 759
 760static const char * const snps_eth_62p4m_ptp_parents[] = {
 761	"apll2_d3",
 762	"apll1_d3",
 763	"clk26m",
 764	"ethpll_d8"
 765};
 766
 767static const char * const snps_eth_50m_rmii_parents[] = {
 768	"clk26m",
 769	"ethpll_d10"
 770};
 771
 772static const char * const adsp_parents[] = {
 773	"clk26m",
 774	"clk13m",
 775	"mainpll_d6",
 776	"mainpll_d5_d2",
 777	"univpll_d4_d4",
 778	"univpll_d4",
 779	"ulposc1_d2",
 780	"ulposc1_ck1",
 781	"adsppll",
 782	"adsppll_d2",
 783	"adsppll_d4",
 784	"adsppll_d8"
 785};
 786
 787static const char * const audio_local_bus_parents[] = {
 788	"clk26m",
 789	"clk13m",
 790	"mainpll_d4_d4",
 791	"mainpll_d7_d2",
 792	"mainpll_d5_d2",
 793	"mainpll_d4_d2",
 794	"mainpll_d7",
 795	"mainpll_d4",
 796	"univpll_d6",
 797	"ulposc1_ck1",
 798	"ulposc1_d4",
 799	"ulposc1_d2"
 800};
 801
 802static const char * const asm_h_parents[] = {
 803	"clk26m",
 804	"univpll_d6_d4",
 805	"univpll_d6_d2",
 806	"mainpll_d5_d2"
 807};
 808
 809static const char * const asm_l_parents[] = {
 810	"clk26m",
 811	"univpll_d6_d4",
 812	"univpll_d6_d2",
 813	"mainpll_d5_d2"
 814};
 815
 816static const char * const apll1_parents[] = {
 817	"clk26m",
 818	"apll1_d4"
 819};
 820
 821static const char * const apll2_parents[] = {
 822	"clk26m",
 823	"apll2_d4"
 824};
 825
 826static const char * const apll3_parents[] = {
 827	"clk26m",
 828	"apll3_d4"
 829};
 830
 831static const char * const apll4_parents[] = {
 832	"clk26m",
 833	"apll4_d4"
 834};
 835
 836static const char * const apll5_parents[] = {
 837	"clk26m",
 838	"apll5_d4"
 839};
 840
 841static const char * const i2so1_parents[] = {
 842	"clk26m",
 843	"apll1",
 844	"apll2",
 845	"apll3",
 846	"apll4",
 847	"apll5"
 848};
 849
 850static const char * const i2so2_parents[] = {
 851	"clk26m",
 852	"apll1",
 853	"apll2",
 854	"apll3",
 855	"apll4",
 856	"apll5"
 857};
 858
 859static const char * const i2si1_parents[] = {
 860	"clk26m",
 861	"apll1",
 862	"apll2",
 863	"apll3",
 864	"apll4",
 865	"apll5"
 866};
 867
 868static const char * const i2si2_parents[] = {
 869	"clk26m",
 870	"apll1",
 871	"apll2",
 872	"apll3",
 873	"apll4",
 874	"apll5"
 875};
 876
 877static const char * const dptx_parents[] = {
 878	"clk26m",
 879	"apll1",
 880	"apll2",
 881	"apll3",
 882	"apll4",
 883	"apll5"
 884};
 885
 886static const char * const aud_iec_parents[] = {
 887	"clk26m",
 888	"apll1",
 889	"apll2",
 890	"apll3",
 891	"apll4",
 892	"apll5"
 893};
 894
 895static const char * const a1sys_hp_parents[] = {
 896	"clk26m",
 897	"apll1_d4"
 898};
 899
 900static const char * const a2sys_parents[] = {
 901	"clk26m",
 902	"apll2_d4"
 903};
 904
 905static const char * const a3sys_parents[] = {
 906	"clk26m",
 907	"apll3_d4",
 908	"apll4_d4",
 909	"apll5_d4"
 910};
 911
 912static const char * const a4sys_parents[] = {
 913	"clk26m",
 914	"apll3_d4",
 915	"apll4_d4",
 916	"apll5_d4"
 917};
 918
 919static const char * const ecc_parents[] = {
 920	"clk26m",
 921	"mainpll_d4_d4",
 922	"mainpll_d5_d2",
 923	"mainpll_d4_d2",
 924	"mainpll_d6",
 925	"univpll_d6"
 926};
 927
 928static const char * const spinor_parents[] = {
 929	"clk26m",
 930	"clk13m",
 931	"mainpll_d7_d8",
 932	"univpll_d6_d8"
 933};
 934
 935static const char * const ulposc_parents[] = {
 936	"ulposc_ck1",
 937	"ethpll_d2",
 938	"mainpll_d4_d2",
 939	"ethpll_d10"
 940};
 941
 942static const char * const srck_parents[] = {
 943	"ulposc1_d10",
 944	"clk26m"
 945};
 946
 947static const char * const mfg_fast_ref_parents[] = {
 948	"top_mfg_core_tmp",
 949	"mfgpll"
 950};
 951
 952static const struct mtk_mux top_mtk_muxes[] = {
 953	/*
 954	 * CLK_CFG_0
 955	 * axi_sel and bus_aximem_sel are bus clocks, should not be closed by Linux.
 956	 * spm_sel and scp_sel are main clocks in always-on co-processor.
 957	 */
 958	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", axi_parents,
 959				   0x020, 0x024, 0x028, 0, 4, 7, 0x04, 0,
 960				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 961	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", spm_parents,
 962				   0x020, 0x024, 0x028, 8, 4, 15, 0x04, 1,
 963				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 964	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", scp_parents,
 965				   0x020, 0x024, 0x028, 16, 4, 23, 0x04, 2,
 966				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 967	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem", bus_aximem_parents,
 968				   0x020, 0x024, 0x028, 24, 4, 31, 0x04, 3,
 969				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 970	/* CLK_CFG_1 */
 971	MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
 972			     vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
 973	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
 974			     ethdr_parents, 0x02C, 0x030, 0x034, 8, 4, 15, 0x04, 5),
 975	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
 976			     ipe_parents, 0x02C, 0x030, 0x034, 16, 4, 23, 0x04, 6),
 977	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
 978			     cam_parents, 0x02C, 0x030, 0x034, 24, 4, 31, 0x04, 7),
 979	/* CLK_CFG_2 */
 980	MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
 981			     ccu_parents, 0x038, 0x03C, 0x040, 0, 4, 7, 0x04, 8),
 982	MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_AHB, "top_ccu_ahb",
 983			     ccu_ahb_parents, 0x038, 0x03C, 0x040, 8, 4, 15, 0x04, 9),
 984	MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
 985			     img_parents, 0x038, 0x03C, 0x040, 16, 4, 23, 0x04, 10),
 986	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
 987			     camtm_parents, 0x038, 0x03C, 0x040, 24, 4, 31, 0x04, 11),
 988	/* CLK_CFG_3 */
 989	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
 990			     dsp_parents, 0x044, 0x048, 0x04C, 0, 4, 7, 0x04, 12),
 991	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
 992			     dsp1_parents, 0x044, 0x048, 0x04C, 8, 4, 15, 0x04, 13),
 993	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
 994			     dsp2_parents, 0x044, 0x048, 0x04C, 16, 4, 23, 0x04, 14),
 995	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3",
 996			     dsp3_parents, 0x044, 0x048, 0x04C, 24, 4, 31, 0x04, 15),
 997	/* CLK_CFG_4 */
 998	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4",
 999			     dsp4_parents, 0x050, 0x054, 0x058, 0, 4, 7, 0x04, 16),
1000	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5",
1001			     dsp5_parents, 0x050, 0x054, 0x058, 8, 4, 15, 0x04, 17),
1002	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6",
1003			     dsp6_parents, 0x050, 0x054, 0x058, 16, 4, 23, 0x04, 18),
1004	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7",
1005			     dsp7_parents, 0x050, 0x054, 0x058, 24, 4, 31, 0x04, 19),
1006	/* CLK_CFG_5 */
1007	MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP, "top_mfg_core_tmp",
1008			     mfg_core_tmp_parents, 0x05C, 0x060, 0x064, 0, 4, 7, 0x04, 20),
1009	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
1010			     camtg_parents, 0x05C, 0x060, 0x064, 8, 4, 15, 0x04, 21),
1011	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
1012			     camtg2_parents, 0x05C, 0x060, 0x064, 16, 4, 23, 0x04, 22),
1013	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
1014			     camtg3_parents, 0x05C, 0x060, 0x064, 24, 4, 31, 0x04, 23),
1015	/* CLK_CFG_6 */
1016	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
1017			     uart_parents, 0x068, 0x06C, 0x070, 0, 4, 7, 0x04, 24),
1018	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
1019			     spi_parents, 0x068, 0x06C, 0x070, 8, 4, 15, 0x04, 25),
1020	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
1021				   msdc5hclk_parents, 0x068, 0x06C, 0x070, 16, 4, 23, 0x04, 26, 0),
1022	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
1023				   msdc50_0_parents, 0x068, 0x06C, 0x070, 24, 4, 31, 0x04, 27, 0),
1024	/* CLK_CFG_7 */
1025	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1",
1026				   msdc30_1_parents, 0x074, 0x078, 0x07C, 0, 4, 7, 0x04, 28, 0),
1027	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2, "top_msdc30_2",
1028				   msdc30_2_parents, 0x074, 0x078, 0x07C, 8, 4, 15, 0x04, 29, 0),
1029	MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
1030			     intdir_parents, 0x074, 0x078, 0x07C, 16, 4, 23, 0x04, 30),
1031	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
1032			     aud_intbus_parents, 0x074, 0x078, 0x07C, 24, 4, 31, 0x04, 31),
1033	/* CLK_CFG_8 */
1034	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
1035			     audio_h_parents, 0x080, 0x084, 0x088, 0, 4, 7, 0x08, 0),
1036	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
1037			     pwrap_ulposc_parents, 0x080, 0x084, 0x088, 8, 4, 15, 0x08, 1),
1038	MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
1039			     atb_parents, 0x080, 0x084, 0x088, 16, 4, 23, 0x08, 2),
1040	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM, "top_sspm",
1041			     sspm_parents, 0x080, 0x084, 0x088, 24, 4, 31, 0x08, 3),
1042	/* CLK_CFG_9 */
1043	MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_DP, "top_dp",
1044				     dp_parents, dp_parents_idx, 0x08C, 0x090, 0x094,
1045				     0, 4, 7, 0x08, 4),
1046	MUX_GATE_CLR_SET_UPD_INDEXED(CLK_TOP_EDP, "top_edp",
1047				     edp_parents, edp_parents_idx, 0x08C, 0x090, 0x094,
1048				     8, 4, 15, 0x08, 5),
1049	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
1050			     dpi_parents, 0x08C, 0x090, 0x094, 16, 4, 23, 0x08, 6),
1051	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
1052			     disp_pwm0_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
1053	/* CLK_CFG_10 */
1054	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1",
1055			     disp_pwm1_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
1056	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top",
1057			     usb_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),
1058	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
1059			     ssusb_xhci_parents, 0x098, 0x09C, 0x0A0, 16, 4, 23, 0x08, 10),
1060	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p",
1061			     usb_2p_parents, 0x098, 0x09C, 0x0A0, 24, 4, 31, 0x08, 11),
1062	/* CLK_CFG_11 */
1063	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P, "top_ssusb_xhci_2p",
1064			     ssusb_xhci_2p_parents, 0x0A4, 0x0A8, 0x0AC, 0, 4, 7, 0x08, 12),
1065	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p",
1066			     usb_3p_parents, 0x0A4, 0x0A8, 0x0AC, 8, 4, 15, 0x08, 13),
1067	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P, "top_ssusb_xhci_3p",
1068			     ssusb_xhci_3p_parents, 0x0A4, 0x0A8, 0x0AC, 16, 4, 23, 0x08, 14),
1069	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
1070			     i2c_parents, 0x0A4, 0x0A8, 0x0AC, 24, 4, 31, 0x08, 15),
1071	/* CLK_CFG_12 */
1072	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
1073			     seninf_parents, 0x0B0, 0x0B4, 0x0B8, 0, 4, 7, 0x08, 16),
1074	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
1075			     seninf1_parents, 0x0B0, 0x0B4, 0x0B8, 8, 4, 15, 0x08, 17),
1076	MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu",
1077			     gcpu_parents, 0x0B0, 0x0B4, 0x0B8, 16, 4, 23, 0x08, 18),
1078	MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
1079			     venc_parents, 0x0B0, 0x0B4, 0x0B8, 24, 4, 31, 0x08, 19),
1080	/*
1081	 * CLK_CFG_13
1082	 * top_mcupm is main clock in co-processor, should not be handled by Linux.
1083	 */
1084	MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
1085			     vdec_parents, 0x0BC, 0x0C0, 0x0C4, 0, 4, 7, 0x08, 20),
1086	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
1087			     pwm_parents, 0x0BC, 0x0C0, 0x0C4, 8, 4, 15, 0x08, 21),
1088	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm", mcupm_parents,
1089				   0x0BC, 0x0C0, 0x0C4, 16, 4, 23, 0x08, 22,
1090				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1091	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
1092			     spmi_p_mst_parents, 0x0BC, 0x0C0, 0x0C4, 24, 4, 31, 0x08, 23),
1093	/*
1094	 * CLK_CFG_14
1095	 * dvfsrc_sel is for internal DVFS usage, should not be handled by Linux.
1096	 */
1097	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
1098			     spmi_m_mst_parents, 0x0C8, 0x0CC, 0x0D0, 0, 4, 7, 0x08, 24),
1099	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", dvfsrc_parents,
1100				   0x0C8, 0x0CC, 0x0D0, 8, 4, 15, 0x08, 25,
1101				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1102	MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
1103			     tl_parents, 0x0C8, 0x0CC, 0x0D0, 16, 4, 23, 0x08, 26),
1104	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
1105			     aes_msdcfde_parents, 0x0C8, 0x0CC, 0x0D0, 24, 4, 31, 0x08, 27),
1106	/* CLK_CFG_15 */
1107	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
1108			     dsi_occ_parents, 0x0D4, 0x0D8, 0x0DC, 0, 4, 7, 0x08, 28),
1109	MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp",
1110			     wpe_vpp_parents, 0x0D4, 0x0D8, 0x0DC, 8, 4, 15, 0x08, 29),
1111	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp",
1112			     hdcp_parents, 0x0D4, 0x0D8, 0x0DC, 16, 4, 23, 0x08, 30),
1113	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m",
1114			     hdcp_24m_parents, 0x0D4, 0x0D8, 0x0DC, 24, 4, 31, 0x08, 31),
1115	/* CLK_CFG_16 */
1116	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb",
1117			     hdmi_apb_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7, 0x0C, 0),
1118	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M, "top_snps_eth_250m",
1119			     snps_eth_250m_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15, 0x0C, 1),
1120	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP, "top_snps_eth_62p4m_ptp",
1121			     snps_eth_62p4m_ptp_parents, 0x0E0, 0x0E4, 0x0E8, 16, 4, 23, 0x0C, 2),
1122	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
1123			     snps_eth_50m_rmii_parents, 0x0E0, 0x0E4, 0x0E8, 24, 4, 31, 0x0C, 3),
1124	/* CLK_CFG_17 */
1125	MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp",
1126			     adsp_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4, 7, 0x0C, 4),
1127	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS, "top_audio_local_bus",
1128			     audio_local_bus_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5),
1129	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h",
1130			     asm_h_parents, 0x0EC, 0x0F0, 0x0F4, 16, 4, 23, 0x0C, 6),
1131	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l",
1132			     asm_l_parents, 0x0EC, 0x0F0, 0x0F4, 24, 4, 31, 0x0C, 7),
1133	/* CLK_CFG_18 */
1134	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
1135			     apll1_parents, 0x0F8, 0x0FC, 0x100, 0, 4, 7, 0x0C, 8),
1136	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
1137			     apll2_parents, 0x0F8, 0x0FC, 0x100, 8, 4, 15, 0x0C, 9),
1138	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3",
1139			     apll3_parents, 0x0F8, 0x0FC, 0x100, 16, 4, 23, 0x0C, 10),
1140	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4",
1141			     apll4_parents, 0x0F8, 0x0FC, 0x100, 24, 4, 31, 0x0C, 11),
1142	/* CLK_CFG_19 */
1143	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
1144			     apll5_parents, 0x0104, 0x0108, 0x010C, 0, 4, 7, 0x0C, 12),
1145	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1, "top_i2so1",
1146			     i2so1_parents, 0x0104, 0x0108, 0x010C, 8, 4, 15, 0x0C, 13),
1147	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2, "top_i2so2",
1148			     i2so2_parents, 0x0104, 0x0108, 0x010C, 16, 4, 23, 0x0C, 14),
1149	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1, "top_i2si1",
1150			     i2si1_parents, 0x0104, 0x0108, 0x010C, 24, 4, 31, 0x0C, 15),
1151	/* CLK_CFG_20 */
1152	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2, "top_i2si2",
1153			     i2si2_parents, 0x0110, 0x0114, 0x0118, 0, 4, 7, 0x0C, 16),
1154	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX, "top_dptx",
1155			     dptx_parents, 0x0110, 0x0114, 0x0118, 8, 4, 15, 0x0C, 17),
1156	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC, "top_aud_iec",
1157			     aud_iec_parents, 0x0110, 0x0114, 0x0118, 16, 4, 23, 0x0C, 18),
1158	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp",
1159			     a1sys_hp_parents, 0x0110, 0x0114, 0x0118, 24, 4, 31, 0x0C, 19),
1160	/* CLK_CFG_21 */
1161	MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS, "top_a2sys",
1162			     a2sys_parents, 0x011C, 0x0120, 0x0124, 0, 4, 7, 0x0C, 20),
1163	MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS, "top_a3sys",
1164			     a3sys_parents, 0x011C, 0x0120, 0x0124, 8, 4, 15, 0x0C, 21),
1165	MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS, "top_a4sys",
1166			     a4sys_parents, 0x011C, 0x0120, 0x0124, 16, 4, 23, 0x0C, 22),
1167	MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc",
1168			     ecc_parents, 0x011C, 0x0120, 0x0124, 24, 4, 31, 0x0C, 23),
1169	/*
1170	 * CLK_CFG_22
1171	 * top_ulposc/top_srck are clock source of always on co-processor,
1172	 * should not be closed by Linux.
1173	 */
1174	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
1175			     spinor_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24),
1176	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc", ulposc_parents,
1177				   0x0128, 0x012C, 0x0130, 8, 4, 15, 0x0C, 25,
1178				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1179	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", srck_parents,
1180				   0x0128, 0x012C, 0x0130, 16, 4, 23, 0x0C, 26,
1181				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1182};
1183
1184static const struct mtk_composite top_adj_divs[] = {
1185	DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "top_i2si1", 0x0320, 0, 0x0328, 8, 0),
1186	DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1", "top_i2si2", 0x0320, 1, 0x0328, 8, 8),
1187	DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "top_i2so1", 0x0320, 2, 0x0328, 8, 16),
1188	DIV_GATE(CLK_TOP_APLL12_CK_DIV3, "apll12_div3", "top_i2so2", 0x0320, 3, 0x0328, 8, 24),
1189	DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "top_aud_iec", 0x0320, 4, 0x0334, 8, 0),
1190	DIV_GATE(CLK_TOP_APLL12_CK_DIV9, "apll12_div9", "top_dptx", 0x0320, 9, 0x0338, 8, 8),
1191};
1192static const struct mtk_gate_regs top0_cg_regs = {
1193	.set_ofs = 0x238,
1194	.clr_ofs = 0x238,
1195	.sta_ofs = 0x238,
1196};
1197
1198static const struct mtk_gate_regs top1_cg_regs = {
1199	.set_ofs = 0x250,
1200	.clr_ofs = 0x250,
1201	.sta_ofs = 0x250,
1202};
1203
1204#define GATE_TOP0(_id, _name, _parent, _shift)			\
1205	GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1206
1207#define GATE_TOP1(_id, _name, _parent, _shift)			\
1208	GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1209
1210static const struct mtk_gate top_clks[] = {
1211	/* TOP0 */
1212	GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP0, "cfgreg_clock_vpp0", "top_vpp", 0),
1213	GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VPP1, "cfgreg_clock_vpp1", "top_vpp", 1),
1214	GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO0, "cfgreg_clock_vdo0", "top_vpp", 2),
1215	GATE_TOP0(CLK_TOP_CFGREG_CLOCK_EN_VDO1, "cfgreg_clock_vdo1", "top_vpp", 3),
1216	GATE_TOP0(CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS, "cfgreg_clock_isp_axi_gals", "top_vpp", 4),
1217	GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP0, "cfgreg_f26m_vpp0", "clk26m", 5),
1218	GATE_TOP0(CLK_TOP_CFGREG_F26M_VPP1, "cfgreg_f26m_vpp1", "clk26m", 6),
1219	GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO0, "cfgreg_f26m_vdo0", "clk26m", 7),
1220	GATE_TOP0(CLK_TOP_CFGREG_F26M_VDO1, "cfgreg_f26m_vdo1", "clk26m", 8),
1221	GATE_TOP0(CLK_TOP_CFGREG_AUD_F26M_AUD, "cfgreg_aud_f26m_aud", "clk26m", 9),
1222	GATE_TOP0(CLK_TOP_CFGREG_UNIPLL_SES, "cfgreg_unipll_ses", "univpll_d2", 15),
1223	GATE_TOP0(CLK_TOP_CFGREG_F_PCIE_PHY_REF, "cfgreg_f_pcie_phy_ref", "clk26m", 18),
1224	/* TOP1 */
1225	GATE_TOP1(CLK_TOP_SSUSB_TOP_REF, "ssusb_ref", "clk26m", 0),
1226	GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1),
1227	GATE_TOP1(CLK_TOP_SSUSB_TOP_P1_REF, "ssusb_p1_ref", "clk26m", 2),
1228	GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3),
1229	GATE_TOP1(CLK_TOP_SSUSB_TOP_P2_REF, "ssusb_p2_ref", "clk26m", 4),
1230	GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5),
1231	GATE_TOP1(CLK_TOP_SSUSB_TOP_P3_REF, "ssusb_p3_ref", "clk26m", 6),
1232	GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7),
1233};
1234
1235static const struct of_device_id of_match_clk_mt8188_topck[] = {
1236	{ .compatible = "mediatek,mt8188-topckgen" },
1237	{ /* sentinel */ }
1238};
1239MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_topck);
1240
1241/* Register mux notifier for MFG mux */
1242static int clk_mt8188_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
1243{
1244	struct mtk_mux_nb *mfg_mux_nb;
1245
1246	mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
1247	if (!mfg_mux_nb)
1248		return -ENOMEM;
1249
1250	mfg_mux_nb->ops = &clk_mux_ops;
1251	mfg_mux_nb->bypass_index = 0; /* Bypass to TOP_MFG_CORE_TMP */
1252
1253	return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
1254}
1255
1256static int clk_mt8188_topck_probe(struct platform_device *pdev)
1257{
1258	struct clk_hw_onecell_data *top_clk_data;
1259	struct device_node *node = pdev->dev.of_node;
1260	struct clk_hw *hw;
1261	int r;
1262	void __iomem *base;
1263
1264	top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1265	if (!top_clk_data)
1266		return -ENOMEM;
1267
1268	base = devm_platform_ioremap_resource(pdev, 0);
1269	if (IS_ERR(base)) {
1270		r = PTR_ERR(base);
1271		goto free_top_data;
1272	}
1273
1274	r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1275					top_clk_data);
1276	if (r)
1277		goto free_top_data;
1278
1279	r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1280	if (r)
1281		goto unregister_fixed_clks;
1282
1283	r = mtk_clk_register_muxes(&pdev->dev, top_mtk_muxes,
1284				   ARRAY_SIZE(top_mtk_muxes), node,
1285				   &mt8188_clk_lock, top_clk_data);
1286	if (r)
1287		goto unregister_factors;
1288
1289	hw = devm_clk_hw_register_mux(&pdev->dev, "mfg_ck_fast_ref", mfg_fast_ref_parents,
1290				      ARRAY_SIZE(mfg_fast_ref_parents), CLK_SET_RATE_PARENT,
1291				      (base + 0x250), 8, 1, 0, &mt8188_clk_lock);
1292	if (IS_ERR(hw)) {
1293		r = PTR_ERR(hw);
1294		goto unregister_muxes;
1295	}
1296	top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] = hw;
1297
1298	r = clk_mt8188_reg_mfg_mux_notifier(&pdev->dev,
1299					    top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF]->clk);
1300	if (r)
1301		goto unregister_muxes;
1302
1303	r = mtk_clk_register_composites(&pdev->dev, top_adj_divs,
1304					ARRAY_SIZE(top_adj_divs), base,
1305					&mt8188_clk_lock, top_clk_data);
1306	if (r)
1307		goto unregister_muxes;
1308
1309	r = mtk_clk_register_gates(&pdev->dev, node, top_clks,
1310				   ARRAY_SIZE(top_clks), top_clk_data);
1311	if (r)
1312		goto unregister_composite_divs;
1313
1314	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
1315	if (r)
1316		goto unregister_gates;
1317
1318	platform_set_drvdata(pdev, top_clk_data);
1319
1320	return r;
1321
1322unregister_gates:
1323	mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1324unregister_composite_divs:
1325	mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
1326unregister_muxes:
1327	mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
1328unregister_factors:
1329	mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1330unregister_fixed_clks:
1331	mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
1332free_top_data:
1333	mtk_free_clk_data(top_clk_data);
1334	return r;
1335}
1336
1337static void clk_mt8188_topck_remove(struct platform_device *pdev)
1338{
1339	struct clk_hw_onecell_data *top_clk_data = platform_get_drvdata(pdev);
1340	struct device_node *node = pdev->dev.of_node;
1341
1342	of_clk_del_provider(node);
1343	mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1344	mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
1345	mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
1346	mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1347	mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
1348	mtk_free_clk_data(top_clk_data);
1349}
1350
1351static struct platform_driver clk_mt8188_topck_drv = {
1352	.probe = clk_mt8188_topck_probe,
1353	.remove = clk_mt8188_topck_remove,
1354	.driver = {
1355		.name = "clk-mt8188-topck",
1356		.of_match_table = of_match_clk_mt8188_topck,
1357	},
1358};
1359module_platform_driver(clk_mt8188_topck_drv);
1360
1361MODULE_DESCRIPTION("MediaTek MT8188 top clock generators driver");
1362MODULE_LICENSE("GPL");